1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit boundary. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
171 SelectionDAG &DAG,SDLoc dl) {
172 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
176 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
177 SelectionDAG &DAG, SDLoc dl) {
178 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
179 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
182 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
183 /// instructions. This is used because creating CONCAT_VECTOR nodes of
184 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
185 /// large BUILD_VECTORS.
186 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
189 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
193 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
194 unsigned NumElems, SelectionDAG &DAG,
196 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
197 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
200 // FIXME: This should stop caching the target machine as soon as
201 // we can remove resetOperationActions et al.
202 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
203 : TargetLowering(TM) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
223 FirstTimeThrough = false;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird. It always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit, since we have so many registers, use the ILP scheduler.
237 // For 32-bit, use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2.
250 if (TM.getOptLevel() >= CodeGenOpt::Default) {
251 if (Subtarget->hasSlowDivide32())
252 addBypassSlowDiv(32, 8);
253 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
254 addBypassSlowDiv(64, 16);
257 if (Subtarget->isTargetKnownWindowsMSVC()) {
258 // Setup Windows compiler runtime calls.
259 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
260 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
261 setLibcallName(RTLIB::SREM_I64, "_allrem");
262 setLibcallName(RTLIB::UREM_I64, "_aullrem");
263 setLibcallName(RTLIB::MUL_I64, "_allmul");
264 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
270 // The _ftol2 runtime function has an unusual calling conv, which
271 // is modeled by a special pseudo-instruction.
272 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
278 if (Subtarget->isTargetDarwin()) {
279 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
280 setUseUnderscoreSetJmp(false);
281 setUseUnderscoreLongJmp(false);
282 } else if (Subtarget->isTargetWindowsGNU()) {
283 // MS runtime is weird: it exports _setjmp, but longjmp!
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(false);
287 setUseUnderscoreSetJmp(true);
288 setUseUnderscoreLongJmp(true);
291 // Set up the register classes.
292 addRegisterClass(MVT::i8, &X86::GR8RegClass);
293 addRegisterClass(MVT::i16, &X86::GR16RegClass);
294 addRegisterClass(MVT::i32, &X86::GR32RegClass);
295 if (Subtarget->is64Bit())
296 addRegisterClass(MVT::i64, &X86::GR64RegClass);
298 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
300 // We don't accept any truncstore of integer registers.
301 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
308 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
310 // SETOEQ and SETUNE require checking two conditions.
311 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
318 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
320 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
321 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
324 if (Subtarget->is64Bit()) {
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
327 } else if (!TM.Options.UseSoftFloat) {
328 // We have an algorithm for SSE2->double, and we turn this into a
329 // 64-bit FILD followed by conditional FADD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
331 // We have an algorithm for SSE2, and we turn this into a 64-bit
332 // FILD for other targets.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
336 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
338 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
339 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
341 if (!TM.Options.UseSoftFloat) {
342 // SSE has no i16 to fp conversion, only i32
343 if (X86ScalarSSEf32) {
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 // f32 and f64 cases are Legal, f80 case is not
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
356 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
357 // are Legal, f80 is custom lowered.
358 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
361 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
363 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
366 if (X86ScalarSSEf32) {
367 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
368 // f32 and f64 cases are Legal, f80 case is not
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
371 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
375 // Handle FP_TO_UINT by promoting the destination to a larger signed
377 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
378 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
384 } else if (!TM.Options.UseSoftFloat) {
385 // Since AVX is a superset of SSE3, only check for SSE here.
386 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
387 // Expand FP_TO_UINT into a select.
388 // FIXME: We would like to use a Custom expander here eventually to do
389 // the optimal thing for SSE vs. the default expansion in the legalizer.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
392 // With SSE3 we can use fisttpll to convert to a signed i64; without
393 // SSE, we're stuck with a fistpll.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
397 if (isTargetFTOL()) {
398 // Use the _ftol2 runtime function, which has a pseudo-instruction
399 // to handle its weird calling convention.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
403 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
404 if (!X86ScalarSSEf64) {
405 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
406 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
409 // Without SSE, i64->f64 goes through memory.
410 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
414 // Scalar integer divide and remainder are lowered to use operations that
415 // produce two results, to match the available instructions. This exposes
416 // the two-result form to trivial CSE, which is able to combine x/y and x%y
417 // into a single instruction.
419 // Scalar integer multiply-high is also lowered to use two-result
420 // operations, to match the available instructions. However, plain multiply
421 // (low) operations are left as Legal, as there are single-result
422 // instructions for this in x86. Using the two-result multiply instructions
423 // when both high and low results are needed must be arranged by dagcombine.
424 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
426 setOperationAction(ISD::MULHS, VT, Expand);
427 setOperationAction(ISD::MULHU, VT, Expand);
428 setOperationAction(ISD::SDIV, VT, Expand);
429 setOperationAction(ISD::UDIV, VT, Expand);
430 setOperationAction(ISD::SREM, VT, Expand);
431 setOperationAction(ISD::UREM, VT, Expand);
433 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
434 setOperationAction(ISD::ADDC, VT, Custom);
435 setOperationAction(ISD::ADDE, VT, Custom);
436 setOperationAction(ISD::SUBC, VT, Custom);
437 setOperationAction(ISD::SUBE, VT, Custom);
440 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
441 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
442 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
443 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
461 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
462 setOperationAction(ISD::FREM , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f64 , Expand);
464 setOperationAction(ISD::FREM , MVT::f80 , Expand);
465 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
467 // Promote the i8 variants and force them on up to i32 which has a shorter
469 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
473 if (Subtarget->hasBMI()) {
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
476 if (Subtarget->is64Bit())
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
479 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
480 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
485 if (Subtarget->hasLZCNT()) {
486 // When promoting the i8 variants, force them to i32 for a shorter
488 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
497 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
503 if (Subtarget->is64Bit()) {
504 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
509 // Special handling for half-precision floating point conversions.
510 // If we don't have F16C support, then lower half float conversions
511 // into library calls.
512 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
513 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
514 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
517 // There's never any support for operations beyond MVT::f32.
518 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
519 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
520 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
808 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
809 MVT VT = (MVT::SimpleValueType)i;
810 setOperationAction(ISD::ADD , VT, Expand);
811 setOperationAction(ISD::SUB , VT, Expand);
812 setOperationAction(ISD::FADD, VT, Expand);
813 setOperationAction(ISD::FNEG, VT, Expand);
814 setOperationAction(ISD::FSUB, VT, Expand);
815 setOperationAction(ISD::MUL , VT, Expand);
816 setOperationAction(ISD::FMUL, VT, Expand);
817 setOperationAction(ISD::SDIV, VT, Expand);
818 setOperationAction(ISD::UDIV, VT, Expand);
819 setOperationAction(ISD::FDIV, VT, Expand);
820 setOperationAction(ISD::SREM, VT, Expand);
821 setOperationAction(ISD::UREM, VT, Expand);
822 setOperationAction(ISD::LOAD, VT, Expand);
823 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
827 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::FABS, VT, Expand);
829 setOperationAction(ISD::FSIN, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FCOS, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FREM, VT, Expand);
834 setOperationAction(ISD::FMA, VT, Expand);
835 setOperationAction(ISD::FPOWI, VT, Expand);
836 setOperationAction(ISD::FSQRT, VT, Expand);
837 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
838 setOperationAction(ISD::FFLOOR, VT, Expand);
839 setOperationAction(ISD::FCEIL, VT, Expand);
840 setOperationAction(ISD::FTRUNC, VT, Expand);
841 setOperationAction(ISD::FRINT, VT, Expand);
842 setOperationAction(ISD::FNEARBYINT, VT, Expand);
843 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHS, VT, Expand);
845 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHU, VT, Expand);
847 setOperationAction(ISD::SDIVREM, VT, Expand);
848 setOperationAction(ISD::UDIVREM, VT, Expand);
849 setOperationAction(ISD::FPOW, VT, Expand);
850 setOperationAction(ISD::CTPOP, VT, Expand);
851 setOperationAction(ISD::CTTZ, VT, Expand);
852 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::CTLZ, VT, Expand);
854 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::SHL, VT, Expand);
856 setOperationAction(ISD::SRA, VT, Expand);
857 setOperationAction(ISD::SRL, VT, Expand);
858 setOperationAction(ISD::ROTL, VT, Expand);
859 setOperationAction(ISD::ROTR, VT, Expand);
860 setOperationAction(ISD::BSWAP, VT, Expand);
861 setOperationAction(ISD::SETCC, VT, Expand);
862 setOperationAction(ISD::FLOG, VT, Expand);
863 setOperationAction(ISD::FLOG2, VT, Expand);
864 setOperationAction(ISD::FLOG10, VT, Expand);
865 setOperationAction(ISD::FEXP, VT, Expand);
866 setOperationAction(ISD::FEXP2, VT, Expand);
867 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
868 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
869 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
870 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
872 setOperationAction(ISD::TRUNCATE, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
874 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
875 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
876 setOperationAction(ISD::VSELECT, VT, Expand);
877 setOperationAction(ISD::SELECT_CC, VT, Expand);
878 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
879 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
880 setTruncStoreAction(VT,
881 (MVT::SimpleValueType)InnerVT, Expand);
882 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
883 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
885 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
886 // we have to deal with them whether we ask for Expansion or not. Setting
887 // Expand causes its own optimisation problems though, so leave them legal.
888 if (VT.getVectorElementType() == MVT::i1)
889 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
892 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
893 // with -msoft-float, disable use of MMX as well.
894 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
895 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
896 // No operations on x86mmx supported, everything uses intrinsics.
899 // MMX-sized vectors (other than x86mmx) are expected to be expanded
900 // into smaller operations.
901 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
902 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
903 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
904 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
905 setOperationAction(ISD::AND, MVT::v8i8, Expand);
906 setOperationAction(ISD::AND, MVT::v4i16, Expand);
907 setOperationAction(ISD::AND, MVT::v2i32, Expand);
908 setOperationAction(ISD::AND, MVT::v1i64, Expand);
909 setOperationAction(ISD::OR, MVT::v8i8, Expand);
910 setOperationAction(ISD::OR, MVT::v4i16, Expand);
911 setOperationAction(ISD::OR, MVT::v2i32, Expand);
912 setOperationAction(ISD::OR, MVT::v1i64, Expand);
913 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
914 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
915 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
916 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
922 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
923 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
924 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
925 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
931 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
932 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
934 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
936 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
937 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
938 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
940 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
941 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
942 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
943 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
945 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
946 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
949 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
950 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
952 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
953 // registers cannot be used even for integer operations.
954 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
955 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
956 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
957 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
959 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
960 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
961 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
962 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
963 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
964 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
965 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
966 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
968 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
970 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
972 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
974 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
976 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
977 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
978 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
979 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
980 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
982 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
984 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
985 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
996 // Do not attempt to custom lower non-power-of-2 vectors
997 if (!isPowerOf2_32(VT.getVectorNumElements()))
999 // Do not attempt to custom lower non-128-bit vectors
1000 if (!VT.is128BitVector())
1002 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1003 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1007 // We support custom legalizing of sext and anyext loads for specific
1008 // memory vector types which we can load as a scalar (or sequence of
1009 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1010 // loads these must work with a single scalar load.
1011 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1021 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1023 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1025 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1026 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1028 if (Subtarget->is64Bit()) {
1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1030 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1033 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1034 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1035 MVT VT = (MVT::SimpleValueType)i;
1037 // Do not attempt to promote non-128-bit vectors
1038 if (!VT.is128BitVector())
1041 setOperationAction(ISD::AND, VT, Promote);
1042 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1043 setOperationAction(ISD::OR, VT, Promote);
1044 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1045 setOperationAction(ISD::XOR, VT, Promote);
1046 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1047 setOperationAction(ISD::LOAD, VT, Promote);
1048 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1049 setOperationAction(ISD::SELECT, VT, Promote);
1050 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1053 // Custom lower v2i64 and v2f64 selects.
1054 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1055 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1056 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1060 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1062 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1064 // As there is no 64-bit GPR available, we need build a special custom
1065 // sequence to convert from v2i32 to v2f32.
1066 if (!Subtarget->is64Bit())
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1069 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1072 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1074 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1075 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1079 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1080 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1102 // FIXME: Do we need to handle scalar-to-vector here?
1103 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1105 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1110 // There is no BLENDI for byte vectors. We don't need to custom lower
1111 // some vselects for now.
1112 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1114 // SSE41 brings specific instructions for doing vector sign extend even in
1115 // cases where we don't have SRA.
1116 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1216 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1223 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1230 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1248 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1252 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1253 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::f64, Legal);
1261 if (Subtarget->hasInt256()) {
1262 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1263 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1264 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1265 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1267 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1268 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1269 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1270 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1272 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1273 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1274 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1275 // Don't lower v32i8 because there is no 128-bit byte mul
1277 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1278 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1280 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1282 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1283 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1285 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1286 // when we have a 256bit-wide blend with immediate.
1287 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1289 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1290 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1292 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1294 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1295 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1296 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1297 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1299 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1300 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1301 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1302 // Don't lower v32i8 because there is no 128-bit byte mul
1305 // In the customized shift lowering, the legal cases in AVX2 will be
1307 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1311 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1313 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1315 // Custom lower several nodes for 256-bit types.
1316 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1317 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1318 MVT VT = (MVT::SimpleValueType)i;
1320 // Extract subvector is special because the value type
1321 // (result) is 128-bit but the source is 256-bit wide.
1322 if (VT.is128BitVector()) {
1323 if (VT.getScalarSizeInBits() >= 32) {
1324 setOperationAction(ISD::MLOAD, VT, Custom);
1325 setOperationAction(ISD::MSTORE, VT, Custom);
1327 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1329 // Do not attempt to custom lower other non-256-bit vectors
1330 if (!VT.is256BitVector())
1333 if (VT.getScalarSizeInBits() >= 32) {
1334 setOperationAction(ISD::MLOAD, VT, Legal);
1335 setOperationAction(ISD::MSTORE, VT, Legal);
1337 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1338 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1339 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1341 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1342 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1343 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1346 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1347 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1348 MVT VT = (MVT::SimpleValueType)i;
1350 // Do not attempt to promote non-256-bit vectors
1351 if (!VT.is256BitVector())
1354 setOperationAction(ISD::AND, VT, Promote);
1355 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1356 setOperationAction(ISD::OR, VT, Promote);
1357 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1358 setOperationAction(ISD::XOR, VT, Promote);
1359 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1360 setOperationAction(ISD::LOAD, VT, Promote);
1361 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1362 setOperationAction(ISD::SELECT, VT, Promote);
1363 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1367 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1368 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1374 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1375 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1377 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1378 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1379 setOperationAction(ISD::XOR, MVT::i1, Legal);
1380 setOperationAction(ISD::OR, MVT::i1, Legal);
1381 setOperationAction(ISD::AND, MVT::i1, Legal);
1382 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1389 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1396 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1402 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1407 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1409 if (Subtarget->is64Bit()) {
1410 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1427 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1428 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1430 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1433 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1434 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1435 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1436 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1437 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1466 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1467 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1470 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1472 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1474 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1477 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1480 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1483 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1484 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1485 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1486 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1487 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1488 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1490 if (Subtarget->hasCDI()) {
1491 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1492 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1495 // Custom lower several nodes.
1496 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1497 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1498 MVT VT = (MVT::SimpleValueType)i;
1500 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1501 // Extract subvector is special because the value type
1502 // (result) is 256/128-bit but the source is 512-bit wide.
1503 if (VT.is128BitVector() || VT.is256BitVector()) {
1504 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1505 if ( EltSize >= 32) {
1506 setOperationAction(ISD::MLOAD, VT, Legal);
1507 setOperationAction(ISD::MSTORE, VT, Legal);
1510 if (VT.getVectorElementType() == MVT::i1)
1511 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1513 // Do not attempt to custom lower other non-512-bit vectors
1514 if (!VT.is512BitVector())
1517 if ( EltSize >= 32) {
1518 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1519 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1521 setOperationAction(ISD::VSELECT, VT, Legal);
1522 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1523 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1524 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1525 setOperationAction(ISD::MLOAD, VT, Legal);
1526 setOperationAction(ISD::MSTORE, VT, Legal);
1529 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1530 MVT VT = (MVT::SimpleValueType)i;
1532 // Do not attempt to promote non-256-bit vectors.
1533 if (!VT.is512BitVector())
1536 setOperationAction(ISD::SELECT, VT, Promote);
1537 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1541 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1542 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1543 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1545 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1546 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1548 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1549 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1550 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1551 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1553 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1554 const MVT VT = (MVT::SimpleValueType)i;
1556 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 // Do not attempt to promote non-256-bit vectors.
1559 if (!VT.is512BitVector())
1563 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1564 setOperationAction(ISD::VSELECT, VT, Legal);
1569 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1570 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1571 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1573 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1574 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1575 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1578 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1579 // of this type with custom code.
1580 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1581 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1582 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1586 // We want to custom lower some of our intrinsics.
1587 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1588 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1589 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1590 if (!Subtarget->is64Bit())
1591 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1593 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1594 // handle type legalization for these operations here.
1596 // FIXME: We really should do custom legalization for addition and
1597 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1598 // than generic legalization for 64-bit multiplication-with-overflow, though.
1599 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1600 // Add/Sub/Mul with overflow operations are custom lowered.
1602 setOperationAction(ISD::SADDO, VT, Custom);
1603 setOperationAction(ISD::UADDO, VT, Custom);
1604 setOperationAction(ISD::SSUBO, VT, Custom);
1605 setOperationAction(ISD::USUBO, VT, Custom);
1606 setOperationAction(ISD::SMULO, VT, Custom);
1607 setOperationAction(ISD::UMULO, VT, Custom);
1611 if (!Subtarget->is64Bit()) {
1612 // These libcalls are not available in 32-bit.
1613 setLibcallName(RTLIB::SHL_I128, nullptr);
1614 setLibcallName(RTLIB::SRL_I128, nullptr);
1615 setLibcallName(RTLIB::SRA_I128, nullptr);
1618 // Combine sin / cos into one node or libcall if possible.
1619 if (Subtarget->hasSinCos()) {
1620 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1621 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1622 if (Subtarget->isTargetDarwin()) {
1623 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1624 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1625 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1626 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1630 if (Subtarget->isTargetWin64()) {
1631 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1632 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1633 setOperationAction(ISD::SREM, MVT::i128, Custom);
1634 setOperationAction(ISD::UREM, MVT::i128, Custom);
1635 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1636 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1639 // We have target-specific dag combine patterns for the following nodes:
1640 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1641 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1642 setTargetDAGCombine(ISD::VSELECT);
1643 setTargetDAGCombine(ISD::SELECT);
1644 setTargetDAGCombine(ISD::SHL);
1645 setTargetDAGCombine(ISD::SRA);
1646 setTargetDAGCombine(ISD::SRL);
1647 setTargetDAGCombine(ISD::OR);
1648 setTargetDAGCombine(ISD::AND);
1649 setTargetDAGCombine(ISD::ADD);
1650 setTargetDAGCombine(ISD::FADD);
1651 setTargetDAGCombine(ISD::FSUB);
1652 setTargetDAGCombine(ISD::FMA);
1653 setTargetDAGCombine(ISD::SUB);
1654 setTargetDAGCombine(ISD::LOAD);
1655 setTargetDAGCombine(ISD::STORE);
1656 setTargetDAGCombine(ISD::ZERO_EXTEND);
1657 setTargetDAGCombine(ISD::ANY_EXTEND);
1658 setTargetDAGCombine(ISD::SIGN_EXTEND);
1659 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1660 setTargetDAGCombine(ISD::TRUNCATE);
1661 setTargetDAGCombine(ISD::SINT_TO_FP);
1662 setTargetDAGCombine(ISD::SETCC);
1663 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1664 setTargetDAGCombine(ISD::BUILD_VECTOR);
1665 if (Subtarget->is64Bit())
1666 setTargetDAGCombine(ISD::MUL);
1667 setTargetDAGCombine(ISD::XOR);
1669 computeRegisterProperties();
1671 // On Darwin, -Os means optimize for size without hurting performance,
1672 // do not reduce the limit.
1673 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1674 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1675 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1676 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1677 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1678 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1679 setPrefLoopAlignment(4); // 2^4 bytes.
1681 // Predictable cmov don't hurt on atom because it's in-order.
1682 PredictableSelectIsExpensive = !Subtarget->isAtom();
1684 setPrefFunctionAlignment(4); // 2^4 bytes.
1686 verifyIntrinsicTables();
1689 // This has so far only been implemented for 64-bit MachO.
1690 bool X86TargetLowering::useLoadStackGuardNode() const {
1691 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1692 Subtarget->is64Bit();
1695 TargetLoweringBase::LegalizeTypeAction
1696 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1697 if (ExperimentalVectorWideningLegalization &&
1698 VT.getVectorNumElements() != 1 &&
1699 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1700 return TypeWidenVector;
1702 return TargetLoweringBase::getPreferredVectorAction(VT);
1705 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1707 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1709 const unsigned NumElts = VT.getVectorNumElements();
1710 const EVT EltVT = VT.getVectorElementType();
1711 if (VT.is512BitVector()) {
1712 if (Subtarget->hasAVX512())
1713 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1714 EltVT == MVT::f32 || EltVT == MVT::f64)
1716 case 8: return MVT::v8i1;
1717 case 16: return MVT::v16i1;
1719 if (Subtarget->hasBWI())
1720 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1722 case 32: return MVT::v32i1;
1723 case 64: return MVT::v64i1;
1727 if (VT.is256BitVector() || VT.is128BitVector()) {
1728 if (Subtarget->hasVLX())
1729 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1730 EltVT == MVT::f32 || EltVT == MVT::f64)
1732 case 2: return MVT::v2i1;
1733 case 4: return MVT::v4i1;
1734 case 8: return MVT::v8i1;
1736 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1737 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1739 case 8: return MVT::v8i1;
1740 case 16: return MVT::v16i1;
1741 case 32: return MVT::v32i1;
1745 return VT.changeVectorElementTypeToInteger();
1748 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1749 /// the desired ByVal argument alignment.
1750 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1753 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1754 if (VTy->getBitWidth() == 128)
1756 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1757 unsigned EltAlign = 0;
1758 getMaxByValAlign(ATy->getElementType(), EltAlign);
1759 if (EltAlign > MaxAlign)
1760 MaxAlign = EltAlign;
1761 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1762 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1763 unsigned EltAlign = 0;
1764 getMaxByValAlign(STy->getElementType(i), EltAlign);
1765 if (EltAlign > MaxAlign)
1766 MaxAlign = EltAlign;
1773 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1774 /// function arguments in the caller parameter area. For X86, aggregates
1775 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1776 /// are at 4-byte boundaries.
1777 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1778 if (Subtarget->is64Bit()) {
1779 // Max of 8 and alignment of type.
1780 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1787 if (Subtarget->hasSSE1())
1788 getMaxByValAlign(Ty, Align);
1792 /// getOptimalMemOpType - Returns the target specific optimal type for load
1793 /// and store operations as a result of memset, memcpy, and memmove
1794 /// lowering. If DstAlign is zero that means it's safe to destination
1795 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1796 /// means there isn't a need to check it against alignment requirement,
1797 /// probably because the source does not need to be loaded. If 'IsMemset' is
1798 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1799 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1800 /// source is constant so it does not need to be loaded.
1801 /// It returns EVT::Other if the type should be determined using generic
1802 /// target-independent logic.
1804 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1805 unsigned DstAlign, unsigned SrcAlign,
1806 bool IsMemset, bool ZeroMemset,
1808 MachineFunction &MF) const {
1809 const Function *F = MF.getFunction();
1810 if ((!IsMemset || ZeroMemset) &&
1811 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1812 Attribute::NoImplicitFloat)) {
1814 (Subtarget->isUnalignedMemAccessFast() ||
1815 ((DstAlign == 0 || DstAlign >= 16) &&
1816 (SrcAlign == 0 || SrcAlign >= 16)))) {
1818 if (Subtarget->hasInt256())
1820 if (Subtarget->hasFp256())
1823 if (Subtarget->hasSSE2())
1825 if (Subtarget->hasSSE1())
1827 } else if (!MemcpyStrSrc && Size >= 8 &&
1828 !Subtarget->is64Bit() &&
1829 Subtarget->hasSSE2()) {
1830 // Do not use f64 to lower memcpy if source is string constant. It's
1831 // better to use i32 to avoid the loads.
1835 if (Subtarget->is64Bit() && Size >= 8)
1840 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1842 return X86ScalarSSEf32;
1843 else if (VT == MVT::f64)
1844 return X86ScalarSSEf64;
1849 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1854 *Fast = Subtarget->isUnalignedMemAccessFast();
1858 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1859 /// current function. The returned value is a member of the
1860 /// MachineJumpTableInfo::JTEntryKind enum.
1861 unsigned X86TargetLowering::getJumpTableEncoding() const {
1862 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1864 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT())
1866 return MachineJumpTableInfo::EK_Custom32;
1868 // Otherwise, use the normal jump table encoding heuristics.
1869 return TargetLowering::getJumpTableEncoding();
1873 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1874 const MachineBasicBlock *MBB,
1875 unsigned uid,MCContext &Ctx) const{
1876 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1877 Subtarget->isPICStyleGOT());
1878 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1880 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1881 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1884 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1886 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1887 SelectionDAG &DAG) const {
1888 if (!Subtarget->is64Bit())
1889 // This doesn't have SDLoc associated with it, but is not really the
1890 // same as a Register.
1891 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1895 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1896 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1898 const MCExpr *X86TargetLowering::
1899 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1900 MCContext &Ctx) const {
1901 // X86-64 uses RIP relative addressing based on the jump table label.
1902 if (Subtarget->isPICStyleRIPRel())
1903 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1905 // Otherwise, the reference is relative to the PIC base.
1906 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1909 // FIXME: Why this routine is here? Move to RegInfo!
1910 std::pair<const TargetRegisterClass*, uint8_t>
1911 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1912 const TargetRegisterClass *RRC = nullptr;
1914 switch (VT.SimpleTy) {
1916 return TargetLowering::findRepresentativeClass(VT);
1917 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1918 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1921 RRC = &X86::VR64RegClass;
1923 case MVT::f32: case MVT::f64:
1924 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1925 case MVT::v4f32: case MVT::v2f64:
1926 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1928 RRC = &X86::VR128RegClass;
1931 return std::make_pair(RRC, Cost);
1934 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1935 unsigned &Offset) const {
1936 if (!Subtarget->isTargetLinux())
1939 if (Subtarget->is64Bit()) {
1940 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1942 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1954 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1955 unsigned DestAS) const {
1956 assert(SrcAS != DestAS && "Expected different address spaces!");
1958 return SrcAS < 256 && DestAS < 256;
1961 //===----------------------------------------------------------------------===//
1962 // Return Value Calling Convention Implementation
1963 //===----------------------------------------------------------------------===//
1965 #include "X86GenCallingConv.inc"
1968 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1969 MachineFunction &MF, bool isVarArg,
1970 const SmallVectorImpl<ISD::OutputArg> &Outs,
1971 LLVMContext &Context) const {
1972 SmallVector<CCValAssign, 16> RVLocs;
1973 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1974 return CCInfo.CheckReturn(Outs, RetCC_X86);
1977 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1978 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1983 X86TargetLowering::LowerReturn(SDValue Chain,
1984 CallingConv::ID CallConv, bool isVarArg,
1985 const SmallVectorImpl<ISD::OutputArg> &Outs,
1986 const SmallVectorImpl<SDValue> &OutVals,
1987 SDLoc dl, SelectionDAG &DAG) const {
1988 MachineFunction &MF = DAG.getMachineFunction();
1989 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1991 SmallVector<CCValAssign, 16> RVLocs;
1992 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1993 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1996 SmallVector<SDValue, 6> RetOps;
1997 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1998 // Operand #1 = Bytes To Pop
1999 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2002 // Copy the result values into the output registers.
2003 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2004 CCValAssign &VA = RVLocs[i];
2005 assert(VA.isRegLoc() && "Can only return in registers!");
2006 SDValue ValToCopy = OutVals[i];
2007 EVT ValVT = ValToCopy.getValueType();
2009 // Promote values to the appropriate types.
2010 if (VA.getLocInfo() == CCValAssign::SExt)
2011 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2012 else if (VA.getLocInfo() == CCValAssign::ZExt)
2013 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2014 else if (VA.getLocInfo() == CCValAssign::AExt)
2015 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2016 else if (VA.getLocInfo() == CCValAssign::BCvt)
2017 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2019 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2020 "Unexpected FP-extend for return value.");
2022 // If this is x86-64, and we disabled SSE, we can't return FP values,
2023 // or SSE or MMX vectors.
2024 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2025 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2026 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2027 report_fatal_error("SSE register return with SSE disabled");
2029 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2030 // llvm-gcc has never done it right and no one has noticed, so this
2031 // should be OK for now.
2032 if (ValVT == MVT::f64 &&
2033 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2034 report_fatal_error("SSE2 register return with SSE2 disabled");
2036 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2037 // the RET instruction and handled by the FP Stackifier.
2038 if (VA.getLocReg() == X86::FP0 ||
2039 VA.getLocReg() == X86::FP1) {
2040 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2041 // change the value to the FP stack register class.
2042 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2043 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2044 RetOps.push_back(ValToCopy);
2045 // Don't emit a copytoreg.
2049 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2050 // which is returned in RAX / RDX.
2051 if (Subtarget->is64Bit()) {
2052 if (ValVT == MVT::x86mmx) {
2053 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2054 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2055 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2057 // If we don't have SSE2 available, convert to v4f32 so the generated
2058 // register is legal.
2059 if (!Subtarget->hasSSE2())
2060 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2065 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2066 Flag = Chain.getValue(1);
2067 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2070 // The x86-64 ABIs require that for returning structs by value we copy
2071 // the sret argument into %rax/%eax (depending on ABI) for the return.
2072 // Win32 requires us to put the sret argument to %eax as well.
2073 // We saved the argument into a virtual register in the entry block,
2074 // so now we copy the value out and into %rax/%eax.
2075 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2076 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2077 MachineFunction &MF = DAG.getMachineFunction();
2078 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2079 unsigned Reg = FuncInfo->getSRetReturnReg();
2081 "SRetReturnReg should have been set in LowerFormalArguments().");
2082 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2085 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2086 X86::RAX : X86::EAX;
2087 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2088 Flag = Chain.getValue(1);
2090 // RAX/EAX now acts like a return value.
2091 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2094 RetOps[0] = Chain; // Update chain.
2096 // Add the flag if we have it.
2098 RetOps.push_back(Flag);
2100 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2103 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2104 if (N->getNumValues() != 1)
2106 if (!N->hasNUsesOfValue(1, 0))
2109 SDValue TCChain = Chain;
2110 SDNode *Copy = *N->use_begin();
2111 if (Copy->getOpcode() == ISD::CopyToReg) {
2112 // If the copy has a glue operand, we conservatively assume it isn't safe to
2113 // perform a tail call.
2114 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2116 TCChain = Copy->getOperand(0);
2117 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2120 bool HasRet = false;
2121 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2123 if (UI->getOpcode() != X86ISD::RET_FLAG)
2125 // If we are returning more than one value, we can definitely
2126 // not make a tail call see PR19530
2127 if (UI->getNumOperands() > 4)
2129 if (UI->getNumOperands() == 4 &&
2130 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2143 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2144 ISD::NodeType ExtendKind) const {
2146 // TODO: Is this also valid on 32-bit?
2147 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2148 ReturnMVT = MVT::i8;
2150 ReturnMVT = MVT::i32;
2152 EVT MinVT = getRegisterType(Context, ReturnMVT);
2153 return VT.bitsLT(MinVT) ? MinVT : VT;
2156 /// LowerCallResult - Lower the result values of a call into the
2157 /// appropriate copies out of appropriate physical registers.
2160 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2161 CallingConv::ID CallConv, bool isVarArg,
2162 const SmallVectorImpl<ISD::InputArg> &Ins,
2163 SDLoc dl, SelectionDAG &DAG,
2164 SmallVectorImpl<SDValue> &InVals) const {
2166 // Assign locations to each value returned by this call.
2167 SmallVector<CCValAssign, 16> RVLocs;
2168 bool Is64Bit = Subtarget->is64Bit();
2169 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2171 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2173 // Copy all of the result registers out of their specified physreg.
2174 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2175 CCValAssign &VA = RVLocs[i];
2176 EVT CopyVT = VA.getValVT();
2178 // If this is x86-64, and we disabled SSE, we can't return FP values
2179 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2180 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2181 report_fatal_error("SSE register return with SSE disabled");
2184 // If we prefer to use the value in xmm registers, copy it out as f80 and
2185 // use a truncate to move it from fp stack reg to xmm reg.
2186 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2187 isScalarFPTypeInSSEReg(VA.getValVT()))
2190 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2191 CopyVT, InFlag).getValue(1);
2192 SDValue Val = Chain.getValue(0);
2194 if (CopyVT != VA.getValVT())
2195 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2196 // This truncation won't change the value.
2197 DAG.getIntPtrConstant(1));
2199 InFlag = Chain.getValue(2);
2200 InVals.push_back(Val);
2206 //===----------------------------------------------------------------------===//
2207 // C & StdCall & Fast Calling Convention implementation
2208 //===----------------------------------------------------------------------===//
2209 // StdCall calling convention seems to be standard for many Windows' API
2210 // routines and around. It differs from C calling convention just a little:
2211 // callee should clean up the stack, not caller. Symbols should be also
2212 // decorated in some fancy way :) It doesn't support any vector arguments.
2213 // For info on fast calling convention see Fast Calling Convention (tail call)
2214 // implementation LowerX86_32FastCCCallTo.
2216 /// CallIsStructReturn - Determines whether a call uses struct return
2218 enum StructReturnType {
2223 static StructReturnType
2224 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2226 return NotStructReturn;
2228 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2229 if (!Flags.isSRet())
2230 return NotStructReturn;
2231 if (Flags.isInReg())
2232 return RegStructReturn;
2233 return StackStructReturn;
2236 /// ArgsAreStructReturn - Determines whether a function uses struct
2237 /// return semantics.
2238 static StructReturnType
2239 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2241 return NotStructReturn;
2243 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2244 if (!Flags.isSRet())
2245 return NotStructReturn;
2246 if (Flags.isInReg())
2247 return RegStructReturn;
2248 return StackStructReturn;
2251 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2252 /// by "Src" to address "Dst" with size and alignment information specified by
2253 /// the specific parameter attribute. The copy will be passed as a byval
2254 /// function parameter.
2256 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2257 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2259 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2261 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2262 /*isVolatile*/false, /*AlwaysInline=*/true,
2263 MachinePointerInfo(), MachinePointerInfo());
2266 /// IsTailCallConvention - Return true if the calling convention is one that
2267 /// supports tail call optimization.
2268 static bool IsTailCallConvention(CallingConv::ID CC) {
2269 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2270 CC == CallingConv::HiPE);
2273 /// \brief Return true if the calling convention is a C calling convention.
2274 static bool IsCCallConvention(CallingConv::ID CC) {
2275 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2276 CC == CallingConv::X86_64_SysV);
2279 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2280 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2284 CallingConv::ID CalleeCC = CS.getCallingConv();
2285 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2291 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2292 /// a tailcall target by changing its ABI.
2293 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2294 bool GuaranteedTailCallOpt) {
2295 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2299 X86TargetLowering::LowerMemArgument(SDValue Chain,
2300 CallingConv::ID CallConv,
2301 const SmallVectorImpl<ISD::InputArg> &Ins,
2302 SDLoc dl, SelectionDAG &DAG,
2303 const CCValAssign &VA,
2304 MachineFrameInfo *MFI,
2306 // Create the nodes corresponding to a load from this parameter slot.
2307 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2308 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2309 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2310 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2313 // If value is passed by pointer we have address passed instead of the value
2315 if (VA.getLocInfo() == CCValAssign::Indirect)
2316 ValVT = VA.getLocVT();
2318 ValVT = VA.getValVT();
2320 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2321 // changed with more analysis.
2322 // In case of tail call optimization mark all arguments mutable. Since they
2323 // could be overwritten by lowering of arguments in case of a tail call.
2324 if (Flags.isByVal()) {
2325 unsigned Bytes = Flags.getByValSize();
2326 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2327 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2328 return DAG.getFrameIndex(FI, getPointerTy());
2330 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2331 VA.getLocMemOffset(), isImmutable);
2332 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2333 return DAG.getLoad(ValVT, dl, Chain, FIN,
2334 MachinePointerInfo::getFixedStack(FI),
2335 false, false, false, 0);
2339 // FIXME: Get this from tablegen.
2340 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2341 const X86Subtarget *Subtarget) {
2342 assert(Subtarget->is64Bit());
2344 if (Subtarget->isCallingConvWin64(CallConv)) {
2345 static const MCPhysReg GPR64ArgRegsWin64[] = {
2346 X86::RCX, X86::RDX, X86::R8, X86::R9
2348 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2351 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2352 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2354 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2357 // FIXME: Get this from tablegen.
2358 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2359 CallingConv::ID CallConv,
2360 const X86Subtarget *Subtarget) {
2361 assert(Subtarget->is64Bit());
2362 if (Subtarget->isCallingConvWin64(CallConv)) {
2363 // The XMM registers which might contain var arg parameters are shadowed
2364 // in their paired GPR. So we only need to save the GPR to their home
2366 // TODO: __vectorcall will change this.
2370 const Function *Fn = MF.getFunction();
2371 bool NoImplicitFloatOps = Fn->getAttributes().
2372 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2373 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2374 "SSE register cannot be used when SSE is disabled!");
2375 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2376 !Subtarget->hasSSE1())
2377 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2381 static const MCPhysReg XMMArgRegs64Bit[] = {
2382 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2383 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2385 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2389 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2390 CallingConv::ID CallConv,
2392 const SmallVectorImpl<ISD::InputArg> &Ins,
2395 SmallVectorImpl<SDValue> &InVals)
2397 MachineFunction &MF = DAG.getMachineFunction();
2398 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2400 const Function* Fn = MF.getFunction();
2401 if (Fn->hasExternalLinkage() &&
2402 Subtarget->isTargetCygMing() &&
2403 Fn->getName() == "main")
2404 FuncInfo->setForceFramePointer(true);
2406 MachineFrameInfo *MFI = MF.getFrameInfo();
2407 bool Is64Bit = Subtarget->is64Bit();
2408 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2410 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2411 "Var args not supported with calling convention fastcc, ghc or hipe");
2413 // Assign locations to all of the incoming arguments.
2414 SmallVector<CCValAssign, 16> ArgLocs;
2415 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2417 // Allocate shadow area for Win64
2419 CCInfo.AllocateStack(32, 8);
2421 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2423 unsigned LastVal = ~0U;
2425 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2426 CCValAssign &VA = ArgLocs[i];
2427 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2429 assert(VA.getValNo() != LastVal &&
2430 "Don't support value assigned to multiple locs yet");
2432 LastVal = VA.getValNo();
2434 if (VA.isRegLoc()) {
2435 EVT RegVT = VA.getLocVT();
2436 const TargetRegisterClass *RC;
2437 if (RegVT == MVT::i32)
2438 RC = &X86::GR32RegClass;
2439 else if (Is64Bit && RegVT == MVT::i64)
2440 RC = &X86::GR64RegClass;
2441 else if (RegVT == MVT::f32)
2442 RC = &X86::FR32RegClass;
2443 else if (RegVT == MVT::f64)
2444 RC = &X86::FR64RegClass;
2445 else if (RegVT.is512BitVector())
2446 RC = &X86::VR512RegClass;
2447 else if (RegVT.is256BitVector())
2448 RC = &X86::VR256RegClass;
2449 else if (RegVT.is128BitVector())
2450 RC = &X86::VR128RegClass;
2451 else if (RegVT == MVT::x86mmx)
2452 RC = &X86::VR64RegClass;
2453 else if (RegVT == MVT::i1)
2454 RC = &X86::VK1RegClass;
2455 else if (RegVT == MVT::v8i1)
2456 RC = &X86::VK8RegClass;
2457 else if (RegVT == MVT::v16i1)
2458 RC = &X86::VK16RegClass;
2459 else if (RegVT == MVT::v32i1)
2460 RC = &X86::VK32RegClass;
2461 else if (RegVT == MVT::v64i1)
2462 RC = &X86::VK64RegClass;
2464 llvm_unreachable("Unknown argument type!");
2466 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2467 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2469 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2470 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2472 if (VA.getLocInfo() == CCValAssign::SExt)
2473 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2474 DAG.getValueType(VA.getValVT()));
2475 else if (VA.getLocInfo() == CCValAssign::ZExt)
2476 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2477 DAG.getValueType(VA.getValVT()));
2478 else if (VA.getLocInfo() == CCValAssign::BCvt)
2479 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2481 if (VA.isExtInLoc()) {
2482 // Handle MMX values passed in XMM regs.
2483 if (RegVT.isVector())
2484 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2486 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2489 assert(VA.isMemLoc());
2490 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2493 // If value is passed via pointer - do a load.
2494 if (VA.getLocInfo() == CCValAssign::Indirect)
2495 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2496 MachinePointerInfo(), false, false, false, 0);
2498 InVals.push_back(ArgValue);
2501 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2503 // The x86-64 ABIs require that for returning structs by value we copy
2504 // the sret argument into %rax/%eax (depending on ABI) for the return.
2505 // Win32 requires us to put the sret argument to %eax as well.
2506 // Save the argument into a virtual register so that we can access it
2507 // from the return points.
2508 if (Ins[i].Flags.isSRet()) {
2509 unsigned Reg = FuncInfo->getSRetReturnReg();
2511 MVT PtrTy = getPointerTy();
2512 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2513 FuncInfo->setSRetReturnReg(Reg);
2515 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2516 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2522 unsigned StackSize = CCInfo.getNextStackOffset();
2523 // Align stack specially for tail calls.
2524 if (FuncIsMadeTailCallSafe(CallConv,
2525 MF.getTarget().Options.GuaranteedTailCallOpt))
2526 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2528 // If the function takes variable number of arguments, make a frame index for
2529 // the start of the first vararg value... for expansion of llvm.va_start. We
2530 // can skip this if there are no va_start calls.
2531 if (MFI->hasVAStart() &&
2532 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2533 CallConv != CallingConv::X86_ThisCall))) {
2534 FuncInfo->setVarArgsFrameIndex(
2535 MFI->CreateFixedObject(1, StackSize, true));
2538 // 64-bit calling conventions support varargs and register parameters, so we
2539 // have to do extra work to spill them in the prologue or forward them to
2541 if (Is64Bit && isVarArg &&
2542 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2543 // Find the first unallocated argument registers.
2544 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2545 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2546 unsigned NumIntRegs =
2547 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2548 unsigned NumXMMRegs =
2549 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2550 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2551 "SSE register cannot be used when SSE is disabled!");
2553 // Gather all the live in physical registers.
2554 SmallVector<SDValue, 6> LiveGPRs;
2555 SmallVector<SDValue, 8> LiveXMMRegs;
2557 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2558 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2560 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2562 if (!ArgXMMs.empty()) {
2563 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2564 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2565 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2566 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2567 LiveXMMRegs.push_back(
2568 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2572 // Store them to the va_list returned by va_start.
2573 if (MFI->hasVAStart()) {
2575 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2576 // Get to the caller-allocated home save location. Add 8 to account
2577 // for the return address.
2578 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2579 FuncInfo->setRegSaveFrameIndex(
2580 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2581 // Fixup to set vararg frame on shadow area (4 x i64).
2583 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2585 // For X86-64, if there are vararg parameters that are passed via
2586 // registers, then we must store them to their spots on the stack so
2587 // they may be loaded by deferencing the result of va_next.
2588 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2589 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2590 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2591 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2594 // Store the integer parameter registers.
2595 SmallVector<SDValue, 8> MemOps;
2596 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2598 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2599 for (SDValue Val : LiveGPRs) {
2600 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2601 DAG.getIntPtrConstant(Offset));
2603 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2604 MachinePointerInfo::getFixedStack(
2605 FuncInfo->getRegSaveFrameIndex(), Offset),
2607 MemOps.push_back(Store);
2611 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2612 // Now store the XMM (fp + vector) parameter registers.
2613 SmallVector<SDValue, 12> SaveXMMOps;
2614 SaveXMMOps.push_back(Chain);
2615 SaveXMMOps.push_back(ALVal);
2616 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2617 FuncInfo->getRegSaveFrameIndex()));
2618 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2619 FuncInfo->getVarArgsFPOffset()));
2620 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2622 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2623 MVT::Other, SaveXMMOps));
2626 if (!MemOps.empty())
2627 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2629 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2630 // to the liveout set on a musttail call.
2631 assert(MFI->hasMustTailInVarArgFunc());
2632 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2633 typedef X86MachineFunctionInfo::Forward Forward;
2635 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2637 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2638 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2639 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2642 if (!ArgXMMs.empty()) {
2644 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2645 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2646 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2648 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2650 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2651 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2653 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2659 // Some CCs need callee pop.
2660 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2661 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2662 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2664 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2665 // If this is an sret function, the return should pop the hidden pointer.
2666 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2667 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2668 argsAreStructReturn(Ins) == StackStructReturn)
2669 FuncInfo->setBytesToPopOnReturn(4);
2673 // RegSaveFrameIndex is X86-64 only.
2674 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2675 if (CallConv == CallingConv::X86_FastCall ||
2676 CallConv == CallingConv::X86_ThisCall)
2677 // fastcc functions can't have varargs.
2678 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2681 FuncInfo->setArgumentStackSize(StackSize);
2687 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2688 SDValue StackPtr, SDValue Arg,
2689 SDLoc dl, SelectionDAG &DAG,
2690 const CCValAssign &VA,
2691 ISD::ArgFlagsTy Flags) const {
2692 unsigned LocMemOffset = VA.getLocMemOffset();
2693 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2694 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2695 if (Flags.isByVal())
2696 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2698 return DAG.getStore(Chain, dl, Arg, PtrOff,
2699 MachinePointerInfo::getStack(LocMemOffset),
2703 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2704 /// optimization is performed and it is required.
2706 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2707 SDValue &OutRetAddr, SDValue Chain,
2708 bool IsTailCall, bool Is64Bit,
2709 int FPDiff, SDLoc dl) const {
2710 // Adjust the Return address stack slot.
2711 EVT VT = getPointerTy();
2712 OutRetAddr = getReturnAddressFrameIndex(DAG);
2714 // Load the "old" Return address.
2715 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2716 false, false, false, 0);
2717 return SDValue(OutRetAddr.getNode(), 1);
2720 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2721 /// optimization is performed and it is required (FPDiff!=0).
2722 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2723 SDValue Chain, SDValue RetAddrFrIdx,
2724 EVT PtrVT, unsigned SlotSize,
2725 int FPDiff, SDLoc dl) {
2726 // Store the return address to the appropriate stack slot.
2727 if (!FPDiff) return Chain;
2728 // Calculate the new stack slot for the return address.
2729 int NewReturnAddrFI =
2730 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2732 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2733 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2734 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2740 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2741 SmallVectorImpl<SDValue> &InVals) const {
2742 SelectionDAG &DAG = CLI.DAG;
2744 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2745 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2746 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2747 SDValue Chain = CLI.Chain;
2748 SDValue Callee = CLI.Callee;
2749 CallingConv::ID CallConv = CLI.CallConv;
2750 bool &isTailCall = CLI.IsTailCall;
2751 bool isVarArg = CLI.IsVarArg;
2753 MachineFunction &MF = DAG.getMachineFunction();
2754 bool Is64Bit = Subtarget->is64Bit();
2755 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2756 StructReturnType SR = callIsStructReturn(Outs);
2757 bool IsSibcall = false;
2758 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2760 if (MF.getTarget().Options.DisableTailCalls)
2763 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2765 // Force this to be a tail call. The verifier rules are enough to ensure
2766 // that we can lower this successfully without moving the return address
2769 } else if (isTailCall) {
2770 // Check if it's really possible to do a tail call.
2771 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2772 isVarArg, SR != NotStructReturn,
2773 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2774 Outs, OutVals, Ins, DAG);
2776 // Sibcalls are automatically detected tailcalls which do not require
2778 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2785 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2786 "Var args not supported with calling convention fastcc, ghc or hipe");
2788 // Analyze operands of the call, assigning locations to each operand.
2789 SmallVector<CCValAssign, 16> ArgLocs;
2790 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2792 // Allocate shadow area for Win64
2794 CCInfo.AllocateStack(32, 8);
2796 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2798 // Get a count of how many bytes are to be pushed on the stack.
2799 unsigned NumBytes = CCInfo.getNextStackOffset();
2801 // This is a sibcall. The memory operands are available in caller's
2802 // own caller's stack.
2804 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2805 IsTailCallConvention(CallConv))
2806 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2809 if (isTailCall && !IsSibcall && !IsMustTail) {
2810 // Lower arguments at fp - stackoffset + fpdiff.
2811 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2813 FPDiff = NumBytesCallerPushed - NumBytes;
2815 // Set the delta of movement of the returnaddr stackslot.
2816 // But only set if delta is greater than previous delta.
2817 if (FPDiff < X86Info->getTCReturnAddrDelta())
2818 X86Info->setTCReturnAddrDelta(FPDiff);
2821 unsigned NumBytesToPush = NumBytes;
2822 unsigned NumBytesToPop = NumBytes;
2824 // If we have an inalloca argument, all stack space has already been allocated
2825 // for us and be right at the top of the stack. We don't support multiple
2826 // arguments passed in memory when using inalloca.
2827 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2829 if (!ArgLocs.back().isMemLoc())
2830 report_fatal_error("cannot use inalloca attribute on a register "
2832 if (ArgLocs.back().getLocMemOffset() != 0)
2833 report_fatal_error("any parameter with the inalloca attribute must be "
2834 "the only memory argument");
2838 Chain = DAG.getCALLSEQ_START(
2839 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2841 SDValue RetAddrFrIdx;
2842 // Load return address for tail calls.
2843 if (isTailCall && FPDiff)
2844 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2845 Is64Bit, FPDiff, dl);
2847 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2848 SmallVector<SDValue, 8> MemOpChains;
2851 // Walk the register/memloc assignments, inserting copies/loads. In the case
2852 // of tail call optimization arguments are handle later.
2853 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2854 DAG.getSubtarget().getRegisterInfo());
2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2856 // Skip inalloca arguments, they have already been written.
2857 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2858 if (Flags.isInAlloca())
2861 CCValAssign &VA = ArgLocs[i];
2862 EVT RegVT = VA.getLocVT();
2863 SDValue Arg = OutVals[i];
2864 bool isByVal = Flags.isByVal();
2866 // Promote the value if needed.
2867 switch (VA.getLocInfo()) {
2868 default: llvm_unreachable("Unknown loc info!");
2869 case CCValAssign::Full: break;
2870 case CCValAssign::SExt:
2871 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::ZExt:
2874 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::AExt:
2877 if (RegVT.is128BitVector()) {
2878 // Special case: passing MMX values in XMM registers.
2879 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2880 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2881 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2883 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2885 case CCValAssign::BCvt:
2886 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2888 case CCValAssign::Indirect: {
2889 // Store the argument.
2890 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2891 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2892 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2893 MachinePointerInfo::getFixedStack(FI),
2900 if (VA.isRegLoc()) {
2901 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2902 if (isVarArg && IsWin64) {
2903 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2904 // shadow reg if callee is a varargs function.
2905 unsigned ShadowReg = 0;
2906 switch (VA.getLocReg()) {
2907 case X86::XMM0: ShadowReg = X86::RCX; break;
2908 case X86::XMM1: ShadowReg = X86::RDX; break;
2909 case X86::XMM2: ShadowReg = X86::R8; break;
2910 case X86::XMM3: ShadowReg = X86::R9; break;
2913 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2915 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2916 assert(VA.isMemLoc());
2917 if (!StackPtr.getNode())
2918 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2920 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2921 dl, DAG, VA, Flags));
2925 if (!MemOpChains.empty())
2926 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2928 if (Subtarget->isPICStyleGOT()) {
2929 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2932 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2933 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2935 // If we are tail calling and generating PIC/GOT style code load the
2936 // address of the callee into ECX. The value in ecx is used as target of
2937 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2938 // for tail calls on PIC/GOT architectures. Normally we would just put the
2939 // address of GOT into ebx and then call target@PLT. But for tail calls
2940 // ebx would be restored (since ebx is callee saved) before jumping to the
2943 // Note: The actual moving to ECX is done further down.
2944 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2945 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2946 !G->getGlobal()->hasProtectedVisibility())
2947 Callee = LowerGlobalAddress(Callee, DAG);
2948 else if (isa<ExternalSymbolSDNode>(Callee))
2949 Callee = LowerExternalSymbol(Callee, DAG);
2953 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2954 // From AMD64 ABI document:
2955 // For calls that may call functions that use varargs or stdargs
2956 // (prototype-less calls or calls to functions containing ellipsis (...) in
2957 // the declaration) %al is used as hidden argument to specify the number
2958 // of SSE registers used. The contents of %al do not need to match exactly
2959 // the number of registers, but must be an ubound on the number of SSE
2960 // registers used and is in the range 0 - 8 inclusive.
2962 // Count the number of XMM registers allocated.
2963 static const MCPhysReg XMMArgRegs[] = {
2964 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2965 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2967 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2968 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2969 && "SSE registers cannot be used when SSE is disabled");
2971 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2972 DAG.getConstant(NumXMMRegs, MVT::i8)));
2975 if (Is64Bit && isVarArg && IsMustTail) {
2976 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2977 for (const auto &F : Forwards) {
2978 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2979 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2983 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2984 // don't need this because the eligibility check rejects calls that require
2985 // shuffling arguments passed in memory.
2986 if (!IsSibcall && isTailCall) {
2987 // Force all the incoming stack arguments to be loaded from the stack
2988 // before any new outgoing arguments are stored to the stack, because the
2989 // outgoing stack slots may alias the incoming argument stack slots, and
2990 // the alias isn't otherwise explicit. This is slightly more conservative
2991 // than necessary, because it means that each store effectively depends
2992 // on every argument instead of just those arguments it would clobber.
2993 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2995 SmallVector<SDValue, 8> MemOpChains2;
2998 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2999 CCValAssign &VA = ArgLocs[i];
3002 assert(VA.isMemLoc());
3003 SDValue Arg = OutVals[i];
3004 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3005 // Skip inalloca arguments. They don't require any work.
3006 if (Flags.isInAlloca())
3008 // Create frame index.
3009 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3010 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3011 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3012 FIN = DAG.getFrameIndex(FI, getPointerTy());
3014 if (Flags.isByVal()) {
3015 // Copy relative to framepointer.
3016 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3017 if (!StackPtr.getNode())
3018 StackPtr = DAG.getCopyFromReg(Chain, dl,
3019 RegInfo->getStackRegister(),
3021 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3023 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3027 // Store relative to framepointer.
3028 MemOpChains2.push_back(
3029 DAG.getStore(ArgChain, dl, Arg, FIN,
3030 MachinePointerInfo::getFixedStack(FI),
3035 if (!MemOpChains2.empty())
3036 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3038 // Store the return address to the appropriate stack slot.
3039 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3040 getPointerTy(), RegInfo->getSlotSize(),
3044 // Build a sequence of copy-to-reg nodes chained together with token chain
3045 // and flag operands which copy the outgoing args into registers.
3047 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3048 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3049 RegsToPass[i].second, InFlag);
3050 InFlag = Chain.getValue(1);
3053 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3054 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3055 // In the 64-bit large code model, we have to make all calls
3056 // through a register, since the call instruction's 32-bit
3057 // pc-relative offset may not be large enough to hold the whole
3059 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3060 // If the callee is a GlobalAddress node (quite common, every direct call
3061 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3064 // We should use extra load for direct calls to dllimported functions in
3066 const GlobalValue *GV = G->getGlobal();
3067 if (!GV->hasDLLImportStorageClass()) {
3068 unsigned char OpFlags = 0;
3069 bool ExtraLoad = false;
3070 unsigned WrapperKind = ISD::DELETED_NODE;
3072 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3073 // external symbols most go through the PLT in PIC mode. If the symbol
3074 // has hidden or protected visibility, or if it is static or local, then
3075 // we don't need to use the PLT - we can directly call it.
3076 if (Subtarget->isTargetELF() &&
3077 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3078 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3079 OpFlags = X86II::MO_PLT;
3080 } else if (Subtarget->isPICStyleStubAny() &&
3081 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3082 (!Subtarget->getTargetTriple().isMacOSX() ||
3083 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3084 // PC-relative references to external symbols should go through $stub,
3085 // unless we're building with the leopard linker or later, which
3086 // automatically synthesizes these stubs.
3087 OpFlags = X86II::MO_DARWIN_STUB;
3088 } else if (Subtarget->isPICStyleRIPRel() &&
3089 isa<Function>(GV) &&
3090 cast<Function>(GV)->getAttributes().
3091 hasAttribute(AttributeSet::FunctionIndex,
3092 Attribute::NonLazyBind)) {
3093 // If the function is marked as non-lazy, generate an indirect call
3094 // which loads from the GOT directly. This avoids runtime overhead
3095 // at the cost of eager binding (and one extra byte of encoding).
3096 OpFlags = X86II::MO_GOTPCREL;
3097 WrapperKind = X86ISD::WrapperRIP;
3101 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3102 G->getOffset(), OpFlags);
3104 // Add a wrapper if needed.
3105 if (WrapperKind != ISD::DELETED_NODE)
3106 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3107 // Add extra indirection if needed.
3109 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3110 MachinePointerInfo::getGOT(),
3111 false, false, false, 0);
3113 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3114 unsigned char OpFlags = 0;
3116 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3117 // external symbols should go through the PLT.
3118 if (Subtarget->isTargetELF() &&
3119 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3120 OpFlags = X86II::MO_PLT;
3121 } else if (Subtarget->isPICStyleStubAny() &&
3122 (!Subtarget->getTargetTriple().isMacOSX() ||
3123 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3124 // PC-relative references to external symbols should go through $stub,
3125 // unless we're building with the leopard linker or later, which
3126 // automatically synthesizes these stubs.
3127 OpFlags = X86II::MO_DARWIN_STUB;
3130 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3132 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3133 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3134 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3137 // Returns a chain & a flag for retval copy to use.
3138 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3139 SmallVector<SDValue, 8> Ops;
3141 if (!IsSibcall && isTailCall) {
3142 Chain = DAG.getCALLSEQ_END(Chain,
3143 DAG.getIntPtrConstant(NumBytesToPop, true),
3144 DAG.getIntPtrConstant(0, true), InFlag, dl);
3145 InFlag = Chain.getValue(1);
3148 Ops.push_back(Chain);
3149 Ops.push_back(Callee);
3152 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3154 // Add argument registers to the end of the list so that they are known live
3156 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3157 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3158 RegsToPass[i].second.getValueType()));
3160 // Add a register mask operand representing the call-preserved registers.
3161 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3162 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3163 assert(Mask && "Missing call preserved mask for calling convention");
3164 Ops.push_back(DAG.getRegisterMask(Mask));
3166 if (InFlag.getNode())
3167 Ops.push_back(InFlag);
3171 //// If this is the first return lowered for this function, add the regs
3172 //// to the liveout set for the function.
3173 // This isn't right, although it's probably harmless on x86; liveouts
3174 // should be computed from returns not tail calls. Consider a void
3175 // function making a tail call to a function returning int.
3176 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3179 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3180 InFlag = Chain.getValue(1);
3182 // Create the CALLSEQ_END node.
3183 unsigned NumBytesForCalleeToPop;
3184 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3185 DAG.getTarget().Options.GuaranteedTailCallOpt))
3186 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3187 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3188 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3189 SR == StackStructReturn)
3190 // If this is a call to a struct-return function, the callee
3191 // pops the hidden struct pointer, so we have to push it back.
3192 // This is common for Darwin/X86, Linux & Mingw32 targets.
3193 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3194 NumBytesForCalleeToPop = 4;
3196 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3198 // Returns a flag for retval copy to use.
3200 Chain = DAG.getCALLSEQ_END(Chain,
3201 DAG.getIntPtrConstant(NumBytesToPop, true),
3202 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3205 InFlag = Chain.getValue(1);
3208 // Handle result values, copying them out of physregs into vregs that we
3210 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3211 Ins, dl, DAG, InVals);
3214 //===----------------------------------------------------------------------===//
3215 // Fast Calling Convention (tail call) implementation
3216 //===----------------------------------------------------------------------===//
3218 // Like std call, callee cleans arguments, convention except that ECX is
3219 // reserved for storing the tail called function address. Only 2 registers are
3220 // free for argument passing (inreg). Tail call optimization is performed
3222 // * tailcallopt is enabled
3223 // * caller/callee are fastcc
3224 // On X86_64 architecture with GOT-style position independent code only local
3225 // (within module) calls are supported at the moment.
3226 // To keep the stack aligned according to platform abi the function
3227 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3228 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3229 // If a tail called function callee has more arguments than the caller the
3230 // caller needs to make sure that there is room to move the RETADDR to. This is
3231 // achieved by reserving an area the size of the argument delta right after the
3232 // original RETADDR, but before the saved framepointer or the spilled registers
3233 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3245 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3246 /// for a 16 byte align requirement.
3248 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3249 SelectionDAG& DAG) const {
3250 MachineFunction &MF = DAG.getMachineFunction();
3251 const TargetMachine &TM = MF.getTarget();
3252 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3253 TM.getSubtargetImpl()->getRegisterInfo());
3254 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3255 unsigned StackAlignment = TFI.getStackAlignment();
3256 uint64_t AlignMask = StackAlignment - 1;
3257 int64_t Offset = StackSize;
3258 unsigned SlotSize = RegInfo->getSlotSize();
3259 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3260 // Number smaller than 12 so just add the difference.
3261 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3263 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3264 Offset = ((~AlignMask) & Offset) + StackAlignment +
3265 (StackAlignment-SlotSize);
3270 /// MatchingStackOffset - Return true if the given stack call argument is
3271 /// already available in the same position (relatively) of the caller's
3272 /// incoming argument stack.
3274 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3275 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3276 const X86InstrInfo *TII) {
3277 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3279 if (Arg.getOpcode() == ISD::CopyFromReg) {
3280 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3281 if (!TargetRegisterInfo::isVirtualRegister(VR))
3283 MachineInstr *Def = MRI->getVRegDef(VR);
3286 if (!Flags.isByVal()) {
3287 if (!TII->isLoadFromStackSlot(Def, FI))
3290 unsigned Opcode = Def->getOpcode();
3291 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3292 Def->getOperand(1).isFI()) {
3293 FI = Def->getOperand(1).getIndex();
3294 Bytes = Flags.getByValSize();
3298 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3299 if (Flags.isByVal())
3300 // ByVal argument is passed in as a pointer but it's now being
3301 // dereferenced. e.g.
3302 // define @foo(%struct.X* %A) {
3303 // tail call @bar(%struct.X* byval %A)
3306 SDValue Ptr = Ld->getBasePtr();
3307 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3310 FI = FINode->getIndex();
3311 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3312 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3313 FI = FINode->getIndex();
3314 Bytes = Flags.getByValSize();
3318 assert(FI != INT_MAX);
3319 if (!MFI->isFixedObjectIndex(FI))
3321 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3324 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3325 /// for tail call optimization. Targets which want to do tail call
3326 /// optimization should implement this function.
3328 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3329 CallingConv::ID CalleeCC,
3331 bool isCalleeStructRet,
3332 bool isCallerStructRet,
3334 const SmallVectorImpl<ISD::OutputArg> &Outs,
3335 const SmallVectorImpl<SDValue> &OutVals,
3336 const SmallVectorImpl<ISD::InputArg> &Ins,
3337 SelectionDAG &DAG) const {
3338 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3341 // If -tailcallopt is specified, make fastcc functions tail-callable.
3342 const MachineFunction &MF = DAG.getMachineFunction();
3343 const Function *CallerF = MF.getFunction();
3345 // If the function return type is x86_fp80 and the callee return type is not,
3346 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3347 // perform a tailcall optimization here.
3348 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3351 CallingConv::ID CallerCC = CallerF->getCallingConv();
3352 bool CCMatch = CallerCC == CalleeCC;
3353 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3354 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3356 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3357 if (IsTailCallConvention(CalleeCC) && CCMatch)
3362 // Look for obvious safe cases to perform tail call optimization that do not
3363 // require ABI changes. This is what gcc calls sibcall.
3365 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3366 // emit a special epilogue.
3367 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3368 DAG.getSubtarget().getRegisterInfo());
3369 if (RegInfo->needsStackRealignment(MF))
3372 // Also avoid sibcall optimization if either caller or callee uses struct
3373 // return semantics.
3374 if (isCalleeStructRet || isCallerStructRet)
3377 // An stdcall/thiscall caller is expected to clean up its arguments; the
3378 // callee isn't going to do that.
3379 // FIXME: this is more restrictive than needed. We could produce a tailcall
3380 // when the stack adjustment matches. For example, with a thiscall that takes
3381 // only one argument.
3382 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3383 CallerCC == CallingConv::X86_ThisCall))
3386 // Do not sibcall optimize vararg calls unless all arguments are passed via
3388 if (isVarArg && !Outs.empty()) {
3390 // Optimizing for varargs on Win64 is unlikely to be safe without
3391 // additional testing.
3392 if (IsCalleeWin64 || IsCallerWin64)
3395 SmallVector<CCValAssign, 16> ArgLocs;
3396 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3399 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3400 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3401 if (!ArgLocs[i].isRegLoc())
3405 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3406 // stack. Therefore, if it's not used by the call it is not safe to optimize
3407 // this into a sibcall.
3408 bool Unused = false;
3409 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3416 SmallVector<CCValAssign, 16> RVLocs;
3417 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3419 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3420 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3421 CCValAssign &VA = RVLocs[i];
3422 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3427 // If the calling conventions do not match, then we'd better make sure the
3428 // results are returned in the same way as what the caller expects.
3430 SmallVector<CCValAssign, 16> RVLocs1;
3431 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3433 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3435 SmallVector<CCValAssign, 16> RVLocs2;
3436 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3438 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3440 if (RVLocs1.size() != RVLocs2.size())
3442 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3443 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3445 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3447 if (RVLocs1[i].isRegLoc()) {
3448 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3451 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3457 // If the callee takes no arguments then go on to check the results of the
3459 if (!Outs.empty()) {
3460 // Check if stack adjustment is needed. For now, do not do this if any
3461 // argument is passed on the stack.
3462 SmallVector<CCValAssign, 16> ArgLocs;
3463 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3466 // Allocate shadow area for Win64
3468 CCInfo.AllocateStack(32, 8);
3470 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3471 if (CCInfo.getNextStackOffset()) {
3472 MachineFunction &MF = DAG.getMachineFunction();
3473 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3476 // Check if the arguments are already laid out in the right way as
3477 // the caller's fixed stack objects.
3478 MachineFrameInfo *MFI = MF.getFrameInfo();
3479 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3480 const X86InstrInfo *TII =
3481 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3482 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3483 CCValAssign &VA = ArgLocs[i];
3484 SDValue Arg = OutVals[i];
3485 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3486 if (VA.getLocInfo() == CCValAssign::Indirect)
3488 if (!VA.isRegLoc()) {
3489 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3496 // If the tailcall address may be in a register, then make sure it's
3497 // possible to register allocate for it. In 32-bit, the call address can
3498 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3499 // callee-saved registers are restored. These happen to be the same
3500 // registers used to pass 'inreg' arguments so watch out for those.
3501 if (!Subtarget->is64Bit() &&
3502 ((!isa<GlobalAddressSDNode>(Callee) &&
3503 !isa<ExternalSymbolSDNode>(Callee)) ||
3504 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3505 unsigned NumInRegs = 0;
3506 // In PIC we need an extra register to formulate the address computation
3508 unsigned MaxInRegs =
3509 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3511 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3512 CCValAssign &VA = ArgLocs[i];
3515 unsigned Reg = VA.getLocReg();
3518 case X86::EAX: case X86::EDX: case X86::ECX:
3519 if (++NumInRegs == MaxInRegs)
3531 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3532 const TargetLibraryInfo *libInfo) const {
3533 return X86::createFastISel(funcInfo, libInfo);
3536 //===----------------------------------------------------------------------===//
3537 // Other Lowering Hooks
3538 //===----------------------------------------------------------------------===//
3540 static bool MayFoldLoad(SDValue Op) {
3541 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3544 static bool MayFoldIntoStore(SDValue Op) {
3545 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3548 static bool isTargetShuffle(unsigned Opcode) {
3550 default: return false;
3551 case X86ISD::BLENDI:
3552 case X86ISD::PSHUFB:
3553 case X86ISD::PSHUFD:
3554 case X86ISD::PSHUFHW:
3555 case X86ISD::PSHUFLW:
3557 case X86ISD::PALIGNR:
3558 case X86ISD::MOVLHPS:
3559 case X86ISD::MOVLHPD:
3560 case X86ISD::MOVHLPS:
3561 case X86ISD::MOVLPS:
3562 case X86ISD::MOVLPD:
3563 case X86ISD::MOVSHDUP:
3564 case X86ISD::MOVSLDUP:
3565 case X86ISD::MOVDDUP:
3568 case X86ISD::UNPCKL:
3569 case X86ISD::UNPCKH:
3570 case X86ISD::VPERMILPI:
3571 case X86ISD::VPERM2X128:
3572 case X86ISD::VPERMI:
3577 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3578 SDValue V1, SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::MOVSHDUP:
3582 case X86ISD::MOVSLDUP:
3583 case X86ISD::MOVDDUP:
3584 return DAG.getNode(Opc, dl, VT, V1);
3588 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3589 SDValue V1, unsigned TargetMask,
3590 SelectionDAG &DAG) {
3592 default: llvm_unreachable("Unknown x86 shuffle node");
3593 case X86ISD::PSHUFD:
3594 case X86ISD::PSHUFHW:
3595 case X86ISD::PSHUFLW:
3596 case X86ISD::VPERMILPI:
3597 case X86ISD::VPERMI:
3598 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3602 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3603 SDValue V1, SDValue V2, unsigned TargetMask,
3604 SelectionDAG &DAG) {
3606 default: llvm_unreachable("Unknown x86 shuffle node");
3607 case X86ISD::PALIGNR:
3608 case X86ISD::VALIGN:
3610 case X86ISD::VPERM2X128:
3611 return DAG.getNode(Opc, dl, VT, V1, V2,
3612 DAG.getConstant(TargetMask, MVT::i8));
3616 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3617 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::MOVLHPS:
3621 case X86ISD::MOVLHPD:
3622 case X86ISD::MOVHLPS:
3623 case X86ISD::MOVLPS:
3624 case X86ISD::MOVLPD:
3627 case X86ISD::UNPCKL:
3628 case X86ISD::UNPCKH:
3629 return DAG.getNode(Opc, dl, VT, V1, V2);
3633 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3634 MachineFunction &MF = DAG.getMachineFunction();
3635 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3636 DAG.getSubtarget().getRegisterInfo());
3637 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3638 int ReturnAddrIndex = FuncInfo->getRAIndex();
3640 if (ReturnAddrIndex == 0) {
3641 // Set up a frame object for the return address.
3642 unsigned SlotSize = RegInfo->getSlotSize();
3643 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3646 FuncInfo->setRAIndex(ReturnAddrIndex);
3649 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3652 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3653 bool hasSymbolicDisplacement) {
3654 // Offset should fit into 32 bit immediate field.
3655 if (!isInt<32>(Offset))
3658 // If we don't have a symbolic displacement - we don't have any extra
3660 if (!hasSymbolicDisplacement)
3663 // FIXME: Some tweaks might be needed for medium code model.
3664 if (M != CodeModel::Small && M != CodeModel::Kernel)
3667 // For small code model we assume that latest object is 16MB before end of 31
3668 // bits boundary. We may also accept pretty large negative constants knowing
3669 // that all objects are in the positive half of address space.
3670 if (M == CodeModel::Small && Offset < 16*1024*1024)
3673 // For kernel code model we know that all object resist in the negative half
3674 // of 32bits address space. We may not accept negative offsets, since they may
3675 // be just off and we may accept pretty large positive ones.
3676 if (M == CodeModel::Kernel && Offset > 0)
3682 /// isCalleePop - Determines whether the callee is required to pop its
3683 /// own arguments. Callee pop is necessary to support tail calls.
3684 bool X86::isCalleePop(CallingConv::ID CallingConv,
3685 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3686 switch (CallingConv) {
3689 case CallingConv::X86_StdCall:
3690 case CallingConv::X86_FastCall:
3691 case CallingConv::X86_ThisCall:
3693 case CallingConv::Fast:
3694 case CallingConv::GHC:
3695 case CallingConv::HiPE:
3702 /// \brief Return true if the condition is an unsigned comparison operation.
3703 static bool isX86CCUnsigned(unsigned X86CC) {
3705 default: llvm_unreachable("Invalid integer condition!");
3706 case X86::COND_E: return true;
3707 case X86::COND_G: return false;
3708 case X86::COND_GE: return false;
3709 case X86::COND_L: return false;
3710 case X86::COND_LE: return false;
3711 case X86::COND_NE: return true;
3712 case X86::COND_B: return true;
3713 case X86::COND_A: return true;
3714 case X86::COND_BE: return true;
3715 case X86::COND_AE: return true;
3717 llvm_unreachable("covered switch fell through?!");
3720 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3721 /// specific condition code, returning the condition code and the LHS/RHS of the
3722 /// comparison to make.
3723 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3724 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3726 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3727 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3728 // X > -1 -> X == 0, jump !sign.
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_NS;
3732 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3733 // X < 0 -> X == 0, jump on sign.
3736 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3738 RHS = DAG.getConstant(0, RHS.getValueType());
3739 return X86::COND_LE;
3743 switch (SetCCOpcode) {
3744 default: llvm_unreachable("Invalid integer condition!");
3745 case ISD::SETEQ: return X86::COND_E;
3746 case ISD::SETGT: return X86::COND_G;
3747 case ISD::SETGE: return X86::COND_GE;
3748 case ISD::SETLT: return X86::COND_L;
3749 case ISD::SETLE: return X86::COND_LE;
3750 case ISD::SETNE: return X86::COND_NE;
3751 case ISD::SETULT: return X86::COND_B;
3752 case ISD::SETUGT: return X86::COND_A;
3753 case ISD::SETULE: return X86::COND_BE;
3754 case ISD::SETUGE: return X86::COND_AE;
3758 // First determine if it is required or is profitable to flip the operands.
3760 // If LHS is a foldable load, but RHS is not, flip the condition.
3761 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3762 !ISD::isNON_EXTLoad(RHS.getNode())) {
3763 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3764 std::swap(LHS, RHS);
3767 switch (SetCCOpcode) {
3773 std::swap(LHS, RHS);
3777 // On a floating point condition, the flags are set as follows:
3779 // 0 | 0 | 0 | X > Y
3780 // 0 | 0 | 1 | X < Y
3781 // 1 | 0 | 0 | X == Y
3782 // 1 | 1 | 1 | unordered
3783 switch (SetCCOpcode) {
3784 default: llvm_unreachable("Condcode should be pre-legalized away");
3786 case ISD::SETEQ: return X86::COND_E;
3787 case ISD::SETOLT: // flipped
3789 case ISD::SETGT: return X86::COND_A;
3790 case ISD::SETOLE: // flipped
3792 case ISD::SETGE: return X86::COND_AE;
3793 case ISD::SETUGT: // flipped
3795 case ISD::SETLT: return X86::COND_B;
3796 case ISD::SETUGE: // flipped
3798 case ISD::SETLE: return X86::COND_BE;
3800 case ISD::SETNE: return X86::COND_NE;
3801 case ISD::SETUO: return X86::COND_P;
3802 case ISD::SETO: return X86::COND_NP;
3804 case ISD::SETUNE: return X86::COND_INVALID;
3808 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3809 /// code. Current x86 isa includes the following FP cmov instructions:
3810 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3811 static bool hasFPCMov(unsigned X86CC) {
3827 /// isFPImmLegal - Returns true if the target can instruction select the
3828 /// specified FP immediate natively. If false, the legalizer will
3829 /// materialize the FP immediate as a load from a constant pool.
3830 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3831 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3832 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3838 /// \brief Returns true if it is beneficial to convert a load of a constant
3839 /// to just the constant itself.
3840 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3842 assert(Ty->isIntegerTy());
3844 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3845 if (BitSize == 0 || BitSize > 64)
3850 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3851 /// the specified range (L, H].
3852 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3853 return (Val < 0) || (Val >= Low && Val < Hi);
3856 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3857 /// specified value.
3858 static bool isUndefOrEqual(int Val, int CmpVal) {
3859 return (Val < 0 || Val == CmpVal);
3862 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3863 /// from position Pos and ending in Pos+Size, falls within the specified
3864 /// sequential range (L, L+Pos]. or is undef.
3865 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3866 unsigned Pos, unsigned Size, int Low) {
3867 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3868 if (!isUndefOrEqual(Mask[i], Low))
3873 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3874 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3875 /// operand - by default will match for first operand.
3876 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3877 bool TestSecondOperand = false) {
3878 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3879 VT != MVT::v2f64 && VT != MVT::v2i64)
3882 unsigned NumElems = VT.getVectorNumElements();
3883 unsigned Lo = TestSecondOperand ? NumElems : 0;
3884 unsigned Hi = Lo + NumElems;
3886 for (unsigned i = 0; i < NumElems; ++i)
3887 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3893 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3894 /// is suitable for input to PSHUFHW.
3895 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3896 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3899 // Lower quadword copied in order or undef.
3900 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3903 // Upper quadword shuffled.
3904 for (unsigned i = 4; i != 8; ++i)
3905 if (!isUndefOrInRange(Mask[i], 4, 8))
3908 if (VT == MVT::v16i16) {
3909 // Lower quadword copied in order or undef.
3910 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3913 // Upper quadword shuffled.
3914 for (unsigned i = 12; i != 16; ++i)
3915 if (!isUndefOrInRange(Mask[i], 12, 16))
3922 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3923 /// is suitable for input to PSHUFLW.
3924 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3925 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3928 // Upper quadword copied in order.
3929 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3932 // Lower quadword shuffled.
3933 for (unsigned i = 0; i != 4; ++i)
3934 if (!isUndefOrInRange(Mask[i], 0, 4))
3937 if (VT == MVT::v16i16) {
3938 // Upper quadword copied in order.
3939 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3942 // Lower quadword shuffled.
3943 for (unsigned i = 8; i != 12; ++i)
3944 if (!isUndefOrInRange(Mask[i], 8, 12))
3951 /// \brief Return true if the mask specifies a shuffle of elements that is
3952 /// suitable for input to intralane (palignr) or interlane (valign) vector
3954 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3955 unsigned NumElts = VT.getVectorNumElements();
3956 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3957 unsigned NumLaneElts = NumElts/NumLanes;
3959 // Do not handle 64-bit element shuffles with palignr.
3960 if (NumLaneElts == 2)
3963 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3965 for (i = 0; i != NumLaneElts; ++i) {
3970 // Lane is all undef, go to next lane
3971 if (i == NumLaneElts)
3974 int Start = Mask[i+l];
3976 // Make sure its in this lane in one of the sources
3977 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3978 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3981 // If not lane 0, then we must match lane 0
3982 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3985 // Correct second source to be contiguous with first source
3986 if (Start >= (int)NumElts)
3987 Start -= NumElts - NumLaneElts;
3989 // Make sure we're shifting in the right direction.
3990 if (Start <= (int)(i+l))
3995 // Check the rest of the elements to see if they are consecutive.
3996 for (++i; i != NumLaneElts; ++i) {
3997 int Idx = Mask[i+l];
3999 // Make sure its in this lane
4000 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4001 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4004 // If not lane 0, then we must match lane 0
4005 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4008 if (Idx >= (int)NumElts)
4009 Idx -= NumElts - NumLaneElts;
4011 if (!isUndefOrEqual(Idx, Start+i))
4020 /// \brief Return true if the node specifies a shuffle of elements that is
4021 /// suitable for input to PALIGNR.
4022 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4023 const X86Subtarget *Subtarget) {
4024 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4025 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4026 VT.is512BitVector())
4027 // FIXME: Add AVX512BW.
4030 return isAlignrMask(Mask, VT, false);
4033 /// \brief Return true if the node specifies a shuffle of elements that is
4034 /// suitable for input to VALIGN.
4035 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4036 const X86Subtarget *Subtarget) {
4037 // FIXME: Add AVX512VL.
4038 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4040 return isAlignrMask(Mask, VT, true);
4043 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4044 /// the two vector operands have swapped position.
4045 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4046 unsigned NumElems) {
4047 for (unsigned i = 0; i != NumElems; ++i) {
4051 else if (idx < (int)NumElems)
4052 Mask[i] = idx + NumElems;
4054 Mask[i] = idx - NumElems;
4058 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4059 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4060 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4061 /// reverse of what x86 shuffles want.
4062 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4064 unsigned NumElems = VT.getVectorNumElements();
4065 unsigned NumLanes = VT.getSizeInBits()/128;
4066 unsigned NumLaneElems = NumElems/NumLanes;
4068 if (NumLaneElems != 2 && NumLaneElems != 4)
4071 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4072 bool symetricMaskRequired =
4073 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4075 // VSHUFPSY divides the resulting vector into 4 chunks.
4076 // The sources are also splitted into 4 chunks, and each destination
4077 // chunk must come from a different source chunk.
4079 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4080 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4082 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4083 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4085 // VSHUFPDY divides the resulting vector into 4 chunks.
4086 // The sources are also splitted into 4 chunks, and each destination
4087 // chunk must come from a different source chunk.
4089 // SRC1 => X3 X2 X1 X0
4090 // SRC2 => Y3 Y2 Y1 Y0
4092 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4094 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4095 unsigned HalfLaneElems = NumLaneElems/2;
4096 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4097 for (unsigned i = 0; i != NumLaneElems; ++i) {
4098 int Idx = Mask[i+l];
4099 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4100 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4102 // For VSHUFPSY, the mask of the second half must be the same as the
4103 // first but with the appropriate offsets. This works in the same way as
4104 // VPERMILPS works with masks.
4105 if (!symetricMaskRequired || Idx < 0)
4107 if (MaskVal[i] < 0) {
4108 MaskVal[i] = Idx - l;
4111 if ((signed)(Idx - l) != MaskVal[i])
4119 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4120 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4121 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4131 return isUndefOrEqual(Mask[0], 6) &&
4132 isUndefOrEqual(Mask[1], 7) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4138 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4140 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4149 return isUndefOrEqual(Mask[0], 2) &&
4150 isUndefOrEqual(Mask[1], 3) &&
4151 isUndefOrEqual(Mask[2], 2) &&
4152 isUndefOrEqual(Mask[3], 3);
4155 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4156 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4157 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4158 if (!VT.is128BitVector())
4161 unsigned NumElems = VT.getVectorNumElements();
4163 if (NumElems != 2 && NumElems != 4)
4166 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4167 if (!isUndefOrEqual(Mask[i], i + NumElems))
4170 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4177 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4178 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4179 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4180 if (!VT.is128BitVector())
4183 unsigned NumElems = VT.getVectorNumElements();
4185 if (NumElems != 2 && NumElems != 4)
4188 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4189 if (!isUndefOrEqual(Mask[i], i))
4192 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4193 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4199 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4200 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4201 /// i. e: If all but one element come from the same vector.
4202 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4203 // TODO: Deal with AVX's VINSERTPS
4204 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4207 unsigned CorrectPosV1 = 0;
4208 unsigned CorrectPosV2 = 0;
4209 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4210 if (Mask[i] == -1) {
4218 else if (Mask[i] == i + 4)
4222 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4223 // We have 3 elements (undefs count as elements from any vector) from one
4224 // vector, and one from another.
4231 // Some special combinations that can be optimized.
4234 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4235 SelectionDAG &DAG) {
4236 MVT VT = SVOp->getSimpleValueType(0);
4239 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4242 ArrayRef<int> Mask = SVOp->getMask();
4244 // These are the special masks that may be optimized.
4245 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4246 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4247 bool MatchEvenMask = true;
4248 bool MatchOddMask = true;
4249 for (int i=0; i<8; ++i) {
4250 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4251 MatchEvenMask = false;
4252 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4253 MatchOddMask = false;
4256 if (!MatchEvenMask && !MatchOddMask)
4259 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4261 SDValue Op0 = SVOp->getOperand(0);
4262 SDValue Op1 = SVOp->getOperand(1);
4264 if (MatchEvenMask) {
4265 // Shift the second operand right to 32 bits.
4266 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4267 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4269 // Shift the first operand left to 32 bits.
4270 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4271 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4273 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4274 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4277 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4278 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4279 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4280 bool HasInt256, bool V2IsSplat = false) {
4282 assert(VT.getSizeInBits() >= 128 &&
4283 "Unsupported vector type for unpckl");
4285 unsigned NumElts = VT.getVectorNumElements();
4286 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4287 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4290 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4291 "Unsupported vector type for unpckh");
4293 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4294 unsigned NumLanes = VT.getSizeInBits()/128;
4295 unsigned NumLaneElts = NumElts/NumLanes;
4297 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4298 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4299 int BitI = Mask[l+i];
4300 int BitI1 = Mask[l+i+1];
4301 if (!isUndefOrEqual(BitI, j))
4304 if (!isUndefOrEqual(BitI1, NumElts))
4307 if (!isUndefOrEqual(BitI1, j + NumElts))
4316 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4317 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4318 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4319 bool HasInt256, bool V2IsSplat = false) {
4320 assert(VT.getSizeInBits() >= 128 &&
4321 "Unsupported vector type for unpckh");
4323 unsigned NumElts = VT.getVectorNumElements();
4324 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4325 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4328 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4329 "Unsupported vector type for unpckh");
4331 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4332 unsigned NumLanes = VT.getSizeInBits()/128;
4333 unsigned NumLaneElts = NumElts/NumLanes;
4335 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4336 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4337 int BitI = Mask[l+i];
4338 int BitI1 = Mask[l+i+1];
4339 if (!isUndefOrEqual(BitI, j))
4342 if (isUndefOrEqual(BitI1, NumElts))
4345 if (!isUndefOrEqual(BitI1, j+NumElts))
4353 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4354 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4356 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4357 unsigned NumElts = VT.getVectorNumElements();
4358 bool Is256BitVec = VT.is256BitVector();
4360 if (VT.is512BitVector())
4362 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4363 "Unsupported vector type for unpckh");
4365 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4366 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4369 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4370 // FIXME: Need a better way to get rid of this, there's no latency difference
4371 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4372 // the former later. We should also remove the "_undef" special mask.
4373 if (NumElts == 4 && Is256BitVec)
4376 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4377 // independently on 128-bit lanes.
4378 unsigned NumLanes = VT.getSizeInBits()/128;
4379 unsigned NumLaneElts = NumElts/NumLanes;
4381 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4382 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4383 int BitI = Mask[l+i];
4384 int BitI1 = Mask[l+i+1];
4386 if (!isUndefOrEqual(BitI, j))
4388 if (!isUndefOrEqual(BitI1, j))
4396 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4397 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4399 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4400 unsigned NumElts = VT.getVectorNumElements();
4402 if (VT.is512BitVector())
4405 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4406 "Unsupported vector type for unpckh");
4408 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4409 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4412 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4413 // independently on 128-bit lanes.
4414 unsigned NumLanes = VT.getSizeInBits()/128;
4415 unsigned NumLaneElts = NumElts/NumLanes;
4417 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4418 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4419 int BitI = Mask[l+i];
4420 int BitI1 = Mask[l+i+1];
4421 if (!isUndefOrEqual(BitI, j))
4423 if (!isUndefOrEqual(BitI1, j))
4430 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4431 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4432 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4433 if (!VT.is512BitVector())
4436 unsigned NumElts = VT.getVectorNumElements();
4437 unsigned HalfSize = NumElts/2;
4438 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4439 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4444 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4445 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4453 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4454 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4455 /// MOVSD, and MOVD, i.e. setting the lowest element.
4456 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4457 if (VT.getVectorElementType().getSizeInBits() < 32)
4459 if (!VT.is128BitVector())
4462 unsigned NumElts = VT.getVectorNumElements();
4464 if (!isUndefOrEqual(Mask[0], NumElts))
4467 for (unsigned i = 1; i != NumElts; ++i)
4468 if (!isUndefOrEqual(Mask[i], i))
4474 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4475 /// as permutations between 128-bit chunks or halves. As an example: this
4477 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4478 /// The first half comes from the second half of V1 and the second half from the
4479 /// the second half of V2.
4480 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4481 if (!HasFp256 || !VT.is256BitVector())
4484 // The shuffle result is divided into half A and half B. In total the two
4485 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4486 // B must come from C, D, E or F.
4487 unsigned HalfSize = VT.getVectorNumElements()/2;
4488 bool MatchA = false, MatchB = false;
4490 // Check if A comes from one of C, D, E, F.
4491 for (unsigned Half = 0; Half != 4; ++Half) {
4492 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4498 // Check if B comes from one of C, D, E, F.
4499 for (unsigned Half = 0; Half != 4; ++Half) {
4500 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4506 return MatchA && MatchB;
4509 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4510 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4511 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4512 MVT VT = SVOp->getSimpleValueType(0);
4514 unsigned HalfSize = VT.getVectorNumElements()/2;
4516 unsigned FstHalf = 0, SndHalf = 0;
4517 for (unsigned i = 0; i < HalfSize; ++i) {
4518 if (SVOp->getMaskElt(i) > 0) {
4519 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4523 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4524 if (SVOp->getMaskElt(i) > 0) {
4525 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4530 return (FstHalf | (SndHalf << 4));
4533 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4534 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4535 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4539 unsigned NumElts = VT.getVectorNumElements();
4541 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4542 for (unsigned i = 0; i != NumElts; ++i) {
4545 Imm8 |= Mask[i] << (i*2);
4550 unsigned LaneSize = 4;
4551 SmallVector<int, 4> MaskVal(LaneSize, -1);
4553 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4554 for (unsigned i = 0; i != LaneSize; ++i) {
4555 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4559 if (MaskVal[i] < 0) {
4560 MaskVal[i] = Mask[i+l] - l;
4561 Imm8 |= MaskVal[i] << (i*2);
4564 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4571 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4572 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4573 /// Note that VPERMIL mask matching is different depending whether theunderlying
4574 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4575 /// to the same elements of the low, but to the higher half of the source.
4576 /// In VPERMILPD the two lanes could be shuffled independently of each other
4577 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4578 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4579 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4580 if (VT.getSizeInBits() < 256 || EltSize < 32)
4582 bool symetricMaskRequired = (EltSize == 32);
4583 unsigned NumElts = VT.getVectorNumElements();
4585 unsigned NumLanes = VT.getSizeInBits()/128;
4586 unsigned LaneSize = NumElts/NumLanes;
4587 // 2 or 4 elements in one lane
4589 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4590 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4591 for (unsigned i = 0; i != LaneSize; ++i) {
4592 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4594 if (symetricMaskRequired) {
4595 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4596 ExpectedMaskVal[i] = Mask[i+l] - l;
4599 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4607 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4608 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4609 /// element of vector 2 and the other elements to come from vector 1 in order.
4610 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4611 bool V2IsSplat = false, bool V2IsUndef = false) {
4612 if (!VT.is128BitVector())
4615 unsigned NumOps = VT.getVectorNumElements();
4616 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4619 if (!isUndefOrEqual(Mask[0], 0))
4622 for (unsigned i = 1; i != NumOps; ++i)
4623 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4624 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4625 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4631 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4632 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4633 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4634 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4635 const X86Subtarget *Subtarget) {
4636 if (!Subtarget->hasSSE3())
4639 unsigned NumElems = VT.getVectorNumElements();
4641 if ((VT.is128BitVector() && NumElems != 4) ||
4642 (VT.is256BitVector() && NumElems != 8) ||
4643 (VT.is512BitVector() && NumElems != 16))
4646 // "i+1" is the value the indexed mask element must have
4647 for (unsigned i = 0; i != NumElems; i += 2)
4648 if (!isUndefOrEqual(Mask[i], i+1) ||
4649 !isUndefOrEqual(Mask[i+1], i+1))
4655 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4656 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4657 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4658 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4659 const X86Subtarget *Subtarget) {
4660 if (!Subtarget->hasSSE3())
4663 unsigned NumElems = VT.getVectorNumElements();
4665 if ((VT.is128BitVector() && NumElems != 4) ||
4666 (VT.is256BitVector() && NumElems != 8) ||
4667 (VT.is512BitVector() && NumElems != 16))
4670 // "i" is the value the indexed mask element must have
4671 for (unsigned i = 0; i != NumElems; i += 2)
4672 if (!isUndefOrEqual(Mask[i], i) ||
4673 !isUndefOrEqual(Mask[i+1], i))
4679 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4680 /// specifies a shuffle of elements that is suitable for input to 256-bit
4681 /// version of MOVDDUP.
4682 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4683 if (!HasFp256 || !VT.is256BitVector())
4686 unsigned NumElts = VT.getVectorNumElements();
4690 for (unsigned i = 0; i != NumElts/2; ++i)
4691 if (!isUndefOrEqual(Mask[i], 0))
4693 for (unsigned i = NumElts/2; i != NumElts; ++i)
4694 if (!isUndefOrEqual(Mask[i], NumElts/2))
4699 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4700 /// specifies a shuffle of elements that is suitable for input to 128-bit
4701 /// version of MOVDDUP.
4702 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4703 if (!VT.is128BitVector())
4706 unsigned e = VT.getVectorNumElements() / 2;
4707 for (unsigned i = 0; i != e; ++i)
4708 if (!isUndefOrEqual(Mask[i], i))
4710 for (unsigned i = 0; i != e; ++i)
4711 if (!isUndefOrEqual(Mask[e+i], i))
4716 /// isVEXTRACTIndex - Return true if the specified
4717 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4718 /// suitable for instruction that extract 128 or 256 bit vectors
4719 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4736 /// operand specifies a subvector insert that is suitable for input to
4737 /// insertion of 128 or 256-bit subvectors
4738 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4739 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4740 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4742 // The index should be aligned on a vecWidth-bit boundary.
4744 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4746 MVT VT = N->getSimpleValueType(0);
4747 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4748 bool Result = (Index * ElSize) % vecWidth == 0;
4753 bool X86::isVINSERT128Index(SDNode *N) {
4754 return isVINSERTIndex(N, 128);
4757 bool X86::isVINSERT256Index(SDNode *N) {
4758 return isVINSERTIndex(N, 256);
4761 bool X86::isVEXTRACT128Index(SDNode *N) {
4762 return isVEXTRACTIndex(N, 128);
4765 bool X86::isVEXTRACT256Index(SDNode *N) {
4766 return isVEXTRACTIndex(N, 256);
4769 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4770 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4771 /// Handles 128-bit and 256-bit.
4772 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4773 MVT VT = N->getSimpleValueType(0);
4775 assert((VT.getSizeInBits() >= 128) &&
4776 "Unsupported vector type for PSHUF/SHUFP");
4778 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4779 // independently on 128-bit lanes.
4780 unsigned NumElts = VT.getVectorNumElements();
4781 unsigned NumLanes = VT.getSizeInBits()/128;
4782 unsigned NumLaneElts = NumElts/NumLanes;
4784 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4785 "Only supports 2, 4 or 8 elements per lane");
4787 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4789 for (unsigned i = 0; i != NumElts; ++i) {
4790 int Elt = N->getMaskElt(i);
4791 if (Elt < 0) continue;
4792 Elt &= NumLaneElts - 1;
4793 unsigned ShAmt = (i << Shift) % 8;
4794 Mask |= Elt << ShAmt;
4800 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4801 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4802 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4803 MVT VT = N->getSimpleValueType(0);
4805 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4806 "Unsupported vector type for PSHUFHW");
4808 unsigned NumElts = VT.getVectorNumElements();
4811 for (unsigned l = 0; l != NumElts; l += 8) {
4812 // 8 nodes per lane, but we only care about the last 4.
4813 for (unsigned i = 0; i < 4; ++i) {
4814 int Elt = N->getMaskElt(l+i+4);
4815 if (Elt < 0) continue;
4816 Elt &= 0x3; // only 2-bits.
4817 Mask |= Elt << (i * 2);
4824 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4825 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4826 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4827 MVT VT = N->getSimpleValueType(0);
4829 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4830 "Unsupported vector type for PSHUFHW");
4832 unsigned NumElts = VT.getVectorNumElements();
4835 for (unsigned l = 0; l != NumElts; l += 8) {
4836 // 8 nodes per lane, but we only care about the first 4.
4837 for (unsigned i = 0; i < 4; ++i) {
4838 int Elt = N->getMaskElt(l+i);
4839 if (Elt < 0) continue;
4840 Elt &= 0x3; // only 2-bits
4841 Mask |= Elt << (i * 2);
4848 /// \brief Return the appropriate immediate to shuffle the specified
4849 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4850 /// VALIGN (if Interlane is true) instructions.
4851 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4853 MVT VT = SVOp->getSimpleValueType(0);
4854 unsigned EltSize = InterLane ? 1 :
4855 VT.getVectorElementType().getSizeInBits() >> 3;
4857 unsigned NumElts = VT.getVectorNumElements();
4858 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4859 unsigned NumLaneElts = NumElts/NumLanes;
4863 for (i = 0; i != NumElts; ++i) {
4864 Val = SVOp->getMaskElt(i);
4868 if (Val >= (int)NumElts)
4869 Val -= NumElts - NumLaneElts;
4871 assert(Val - i > 0 && "PALIGNR imm should be positive");
4872 return (Val - i) * EltSize;
4875 /// \brief Return the appropriate immediate to shuffle the specified
4876 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4877 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4878 return getShuffleAlignrImmediate(SVOp, false);
4881 /// \brief Return the appropriate immediate to shuffle the specified
4882 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4883 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4884 return getShuffleAlignrImmediate(SVOp, true);
4888 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4889 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4890 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4891 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4894 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4896 MVT VecVT = N->getOperand(0).getSimpleValueType();
4897 MVT ElVT = VecVT.getVectorElementType();
4899 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4900 return Index / NumElemsPerChunk;
4903 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4904 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4905 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4906 llvm_unreachable("Illegal insert subvector for VINSERT");
4909 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4911 MVT VecVT = N->getSimpleValueType(0);
4912 MVT ElVT = VecVT.getVectorElementType();
4914 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4915 return Index / NumElemsPerChunk;
4918 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4919 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4920 /// and VINSERTI128 instructions.
4921 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4922 return getExtractVEXTRACTImmediate(N, 128);
4925 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4926 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4927 /// and VINSERTI64x4 instructions.
4928 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4929 return getExtractVEXTRACTImmediate(N, 256);
4932 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4933 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4934 /// and VINSERTI128 instructions.
4935 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4936 return getInsertVINSERTImmediate(N, 128);
4939 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4940 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4941 /// and VINSERTI64x4 instructions.
4942 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4943 return getInsertVINSERTImmediate(N, 256);
4946 /// isZero - Returns true if Elt is a constant integer zero
4947 static bool isZero(SDValue V) {
4948 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4949 return C && C->isNullValue();
4952 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4954 bool X86::isZeroNode(SDValue Elt) {
4957 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4958 return CFP->getValueAPF().isPosZero();
4962 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4963 /// match movhlps. The lower half elements should come from upper half of
4964 /// V1 (and in order), and the upper half elements should come from the upper
4965 /// half of V2 (and in order).
4966 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4967 if (!VT.is128BitVector())
4969 if (VT.getVectorNumElements() != 4)
4971 for (unsigned i = 0, e = 2; i != e; ++i)
4972 if (!isUndefOrEqual(Mask[i], i+2))
4974 for (unsigned i = 2; i != 4; ++i)
4975 if (!isUndefOrEqual(Mask[i], i+4))
4980 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4981 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4983 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4984 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4986 N = N->getOperand(0).getNode();
4987 if (!ISD::isNON_EXTLoad(N))
4990 *LD = cast<LoadSDNode>(N);
4994 // Test whether the given value is a vector value which will be legalized
4996 static bool WillBeConstantPoolLoad(SDNode *N) {
4997 if (N->getOpcode() != ISD::BUILD_VECTOR)
5000 // Check for any non-constant elements.
5001 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5002 switch (N->getOperand(i).getNode()->getOpcode()) {
5004 case ISD::ConstantFP:
5011 // Vectors of all-zeros and all-ones are materialized with special
5012 // instructions rather than being loaded.
5013 return !ISD::isBuildVectorAllZeros(N) &&
5014 !ISD::isBuildVectorAllOnes(N);
5017 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5018 /// match movlp{s|d}. The lower half elements should come from lower half of
5019 /// V1 (and in order), and the upper half elements should come from the upper
5020 /// half of V2 (and in order). And since V1 will become the source of the
5021 /// MOVLP, it must be either a vector load or a scalar load to vector.
5022 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5023 ArrayRef<int> Mask, MVT VT) {
5024 if (!VT.is128BitVector())
5027 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5029 // Is V2 is a vector load, don't do this transformation. We will try to use
5030 // load folding shufps op.
5031 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5034 unsigned NumElems = VT.getVectorNumElements();
5036 if (NumElems != 2 && NumElems != 4)
5038 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5039 if (!isUndefOrEqual(Mask[i], i))
5041 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5042 if (!isUndefOrEqual(Mask[i], i+NumElems))
5047 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5048 /// to an zero vector.
5049 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5050 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5051 SDValue V1 = N->getOperand(0);
5052 SDValue V2 = N->getOperand(1);
5053 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5054 for (unsigned i = 0; i != NumElems; ++i) {
5055 int Idx = N->getMaskElt(i);
5056 if (Idx >= (int)NumElems) {
5057 unsigned Opc = V2.getOpcode();
5058 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5060 if (Opc != ISD::BUILD_VECTOR ||
5061 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5063 } else if (Idx >= 0) {
5064 unsigned Opc = V1.getOpcode();
5065 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5067 if (Opc != ISD::BUILD_VECTOR ||
5068 !X86::isZeroNode(V1.getOperand(Idx)))
5075 /// getZeroVector - Returns a vector of specified type with all zero elements.
5077 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5078 SelectionDAG &DAG, SDLoc dl) {
5079 assert(VT.isVector() && "Expected a vector type");
5081 // Always build SSE zero vectors as <4 x i32> bitcasted
5082 // to their dest type. This ensures they get CSE'd.
5084 if (VT.is128BitVector()) { // SSE
5085 if (Subtarget->hasSSE2()) { // SSE2
5086 SDValue Cst = DAG.getConstant(0, MVT::i32);
5087 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5089 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5092 } else if (VT.is256BitVector()) { // AVX
5093 if (Subtarget->hasInt256()) { // AVX2
5094 SDValue Cst = DAG.getConstant(0, MVT::i32);
5095 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5096 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5098 // 256-bit logic and arithmetic instructions in AVX are all
5099 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5100 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5101 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5102 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5104 } else if (VT.is512BitVector()) { // AVX-512
5105 SDValue Cst = DAG.getConstant(0, MVT::i32);
5106 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5107 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5108 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5109 } else if (VT.getScalarType() == MVT::i1) {
5110 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5111 SDValue Cst = DAG.getConstant(0, MVT::i1);
5112 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5113 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5115 llvm_unreachable("Unexpected vector type");
5117 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5120 /// getOnesVector - Returns a vector of specified type with all bits set.
5121 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5122 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5123 /// Then bitcast to their original type, ensuring they get CSE'd.
5124 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5126 assert(VT.isVector() && "Expected a vector type");
5128 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5130 if (VT.is256BitVector()) {
5131 if (HasInt256) { // AVX2
5132 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5133 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5136 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5138 } else if (VT.is128BitVector()) {
5139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5141 llvm_unreachable("Unexpected vector type");
5143 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5146 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5147 /// that point to V2 points to its first element.
5148 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5149 for (unsigned i = 0; i != NumElems; ++i) {
5150 if (Mask[i] > (int)NumElems) {
5156 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5157 /// operation of specified width.
5158 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5160 unsigned NumElems = VT.getVectorNumElements();
5161 SmallVector<int, 8> Mask;
5162 Mask.push_back(NumElems);
5163 for (unsigned i = 1; i != NumElems; ++i)
5165 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5168 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5169 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5171 unsigned NumElems = VT.getVectorNumElements();
5172 SmallVector<int, 8> Mask;
5173 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5175 Mask.push_back(i + NumElems);
5177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5180 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5181 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5183 unsigned NumElems = VT.getVectorNumElements();
5184 SmallVector<int, 8> Mask;
5185 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5186 Mask.push_back(i + Half);
5187 Mask.push_back(i + NumElems + Half);
5189 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5192 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5193 // a generic shuffle instruction because the target has no such instructions.
5194 // Generate shuffles which repeat i16 and i8 several times until they can be
5195 // represented by v4f32 and then be manipulated by target suported shuffles.
5196 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5197 MVT VT = V.getSimpleValueType();
5198 int NumElems = VT.getVectorNumElements();
5201 while (NumElems > 4) {
5202 if (EltNo < NumElems/2) {
5203 V = getUnpackl(DAG, dl, VT, V, V);
5205 V = getUnpackh(DAG, dl, VT, V, V);
5206 EltNo -= NumElems/2;
5213 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5214 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5215 MVT VT = V.getSimpleValueType();
5218 if (VT.is128BitVector()) {
5219 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5220 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5221 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5223 } else if (VT.is256BitVector()) {
5224 // To use VPERMILPS to splat scalars, the second half of indicies must
5225 // refer to the higher part, which is a duplication of the lower one,
5226 // because VPERMILPS can only handle in-lane permutations.
5227 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5228 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5230 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5231 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5234 llvm_unreachable("Vector size not supported");
5236 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5239 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5240 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5241 MVT SrcVT = SV->getSimpleValueType(0);
5242 SDValue V1 = SV->getOperand(0);
5245 int EltNo = SV->getSplatIndex();
5246 int NumElems = SrcVT.getVectorNumElements();
5247 bool Is256BitVec = SrcVT.is256BitVector();
5249 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5250 "Unknown how to promote splat for type");
5252 // Extract the 128-bit part containing the splat element and update
5253 // the splat element index when it refers to the higher register.
5255 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5256 if (EltNo >= NumElems/2)
5257 EltNo -= NumElems/2;
5260 // All i16 and i8 vector types can't be used directly by a generic shuffle
5261 // instruction because the target has no such instruction. Generate shuffles
5262 // which repeat i16 and i8 several times until they fit in i32, and then can
5263 // be manipulated by target suported shuffles.
5264 MVT EltVT = SrcVT.getVectorElementType();
5265 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5266 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5268 // Recreate the 256-bit vector and place the same 128-bit vector
5269 // into the low and high part. This is necessary because we want
5270 // to use VPERM* to shuffle the vectors
5272 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5275 return getLegalSplat(DAG, V1, EltNo);
5278 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5279 /// vector of zero or undef vector. This produces a shuffle where the low
5280 /// element of V2 is swizzled into the zero/undef vector, landing at element
5281 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5282 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5284 const X86Subtarget *Subtarget,
5285 SelectionDAG &DAG) {
5286 MVT VT = V2.getSimpleValueType();
5288 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5289 unsigned NumElems = VT.getVectorNumElements();
5290 SmallVector<int, 16> MaskVec;
5291 for (unsigned i = 0; i != NumElems; ++i)
5292 // If this is the insertion idx, put the low elt of V2 here.
5293 MaskVec.push_back(i == Idx ? NumElems : i);
5294 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5297 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5298 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5299 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5300 /// shuffles which use a single input multiple times, and in those cases it will
5301 /// adjust the mask to only have indices within that single input.
5302 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5303 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5304 unsigned NumElems = VT.getVectorNumElements();
5308 bool IsFakeUnary = false;
5309 switch(N->getOpcode()) {
5310 case X86ISD::BLENDI:
5311 ImmN = N->getOperand(N->getNumOperands()-1);
5312 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5315 ImmN = N->getOperand(N->getNumOperands()-1);
5316 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::UNPCKH:
5320 DecodeUNPCKHMask(VT, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::UNPCKL:
5324 DecodeUNPCKLMask(VT, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::MOVHLPS:
5328 DecodeMOVHLPSMask(NumElems, Mask);
5329 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5331 case X86ISD::MOVLHPS:
5332 DecodeMOVLHPSMask(NumElems, Mask);
5333 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5335 case X86ISD::PALIGNR:
5336 ImmN = N->getOperand(N->getNumOperands()-1);
5337 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5339 case X86ISD::PSHUFD:
5340 case X86ISD::VPERMILPI:
5341 ImmN = N->getOperand(N->getNumOperands()-1);
5342 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5345 case X86ISD::PSHUFHW:
5346 ImmN = N->getOperand(N->getNumOperands()-1);
5347 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5350 case X86ISD::PSHUFLW:
5351 ImmN = N->getOperand(N->getNumOperands()-1);
5352 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5355 case X86ISD::PSHUFB: {
5357 SDValue MaskNode = N->getOperand(1);
5358 while (MaskNode->getOpcode() == ISD::BITCAST)
5359 MaskNode = MaskNode->getOperand(0);
5361 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5362 // If we have a build-vector, then things are easy.
5363 EVT VT = MaskNode.getValueType();
5364 assert(VT.isVector() &&
5365 "Can't produce a non-vector with a build_vector!");
5366 if (!VT.isInteger())
5369 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5371 SmallVector<uint64_t, 32> RawMask;
5372 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5373 SDValue Op = MaskNode->getOperand(i);
5374 if (Op->getOpcode() == ISD::UNDEF) {
5375 RawMask.push_back((uint64_t)SM_SentinelUndef);
5378 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5381 APInt MaskElement = CN->getAPIntValue();
5383 // We now have to decode the element which could be any integer size and
5384 // extract each byte of it.
5385 for (int j = 0; j < NumBytesPerElement; ++j) {
5386 // Note that this is x86 and so always little endian: the low byte is
5387 // the first byte of the mask.
5388 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5389 MaskElement = MaskElement.lshr(8);
5392 DecodePSHUFBMask(RawMask, Mask);
5396 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5400 SDValue Ptr = MaskLoad->getBasePtr();
5401 if (Ptr->getOpcode() == X86ISD::Wrapper)
5402 Ptr = Ptr->getOperand(0);
5404 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5405 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5408 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5409 // FIXME: Support AVX-512 here.
5410 Type *Ty = C->getType();
5411 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5412 Ty->getVectorNumElements() != 32))
5415 DecodePSHUFBMask(C, Mask);
5421 case X86ISD::VPERMI:
5422 ImmN = N->getOperand(N->getNumOperands()-1);
5423 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5427 case X86ISD::MOVSD: {
5428 // The index 0 always comes from the first element of the second source,
5429 // this is why MOVSS and MOVSD are used in the first place. The other
5430 // elements come from the other positions of the first source vector
5431 Mask.push_back(NumElems);
5432 for (unsigned i = 1; i != NumElems; ++i) {
5437 case X86ISD::VPERM2X128:
5438 ImmN = N->getOperand(N->getNumOperands()-1);
5439 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5440 if (Mask.empty()) return false;
5442 case X86ISD::MOVSLDUP:
5443 DecodeMOVSLDUPMask(VT, Mask);
5445 case X86ISD::MOVSHDUP:
5446 DecodeMOVSHDUPMask(VT, Mask);
5448 case X86ISD::MOVDDUP:
5449 case X86ISD::MOVLHPD:
5450 case X86ISD::MOVLPD:
5451 case X86ISD::MOVLPS:
5452 // Not yet implemented
5454 default: llvm_unreachable("unknown target shuffle node");
5457 // If we have a fake unary shuffle, the shuffle mask is spread across two
5458 // inputs that are actually the same node. Re-map the mask to always point
5459 // into the first input.
5462 if (M >= (int)Mask.size())
5468 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5469 /// element of the result of the vector shuffle.
5470 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5473 return SDValue(); // Limit search depth.
5475 SDValue V = SDValue(N, 0);
5476 EVT VT = V.getValueType();
5477 unsigned Opcode = V.getOpcode();
5479 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5480 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5481 int Elt = SV->getMaskElt(Index);
5484 return DAG.getUNDEF(VT.getVectorElementType());
5486 unsigned NumElems = VT.getVectorNumElements();
5487 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5488 : SV->getOperand(1);
5489 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5492 // Recurse into target specific vector shuffles to find scalars.
5493 if (isTargetShuffle(Opcode)) {
5494 MVT ShufVT = V.getSimpleValueType();
5495 unsigned NumElems = ShufVT.getVectorNumElements();
5496 SmallVector<int, 16> ShuffleMask;
5499 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5502 int Elt = ShuffleMask[Index];
5504 return DAG.getUNDEF(ShufVT.getVectorElementType());
5506 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5508 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5512 // Actual nodes that may contain scalar elements
5513 if (Opcode == ISD::BITCAST) {
5514 V = V.getOperand(0);
5515 EVT SrcVT = V.getValueType();
5516 unsigned NumElems = VT.getVectorNumElements();
5518 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5522 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5523 return (Index == 0) ? V.getOperand(0)
5524 : DAG.getUNDEF(VT.getVectorElementType());
5526 if (V.getOpcode() == ISD::BUILD_VECTOR)
5527 return V.getOperand(Index);
5532 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5533 /// shuffle operation which come from a consecutively from a zero. The
5534 /// search can start in two different directions, from left or right.
5535 /// We count undefs as zeros until PreferredNum is reached.
5536 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5537 unsigned NumElems, bool ZerosFromLeft,
5539 unsigned PreferredNum = -1U) {
5540 unsigned NumZeros = 0;
5541 for (unsigned i = 0; i != NumElems; ++i) {
5542 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5543 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5547 if (X86::isZeroNode(Elt))
5549 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5550 NumZeros = std::min(NumZeros + 1, PreferredNum);
5558 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5559 /// correspond consecutively to elements from one of the vector operands,
5560 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5562 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5563 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5564 unsigned NumElems, unsigned &OpNum) {
5565 bool SeenV1 = false;
5566 bool SeenV2 = false;
5568 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5569 int Idx = SVOp->getMaskElt(i);
5570 // Ignore undef indicies
5574 if (Idx < (int)NumElems)
5579 // Only accept consecutive elements from the same vector
5580 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5584 OpNum = SeenV1 ? 0 : 1;
5588 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5589 /// logical left shift of a vector.
5590 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5591 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5593 SVOp->getSimpleValueType(0).getVectorNumElements();
5594 unsigned NumZeros = getNumOfConsecutiveZeros(
5595 SVOp, NumElems, false /* check zeros from right */, DAG,
5596 SVOp->getMaskElt(0));
5602 // Considering the elements in the mask that are not consecutive zeros,
5603 // check if they consecutively come from only one of the source vectors.
5605 // V1 = {X, A, B, C} 0
5607 // vector_shuffle V1, V2 <1, 2, 3, X>
5609 if (!isShuffleMaskConsecutive(SVOp,
5610 0, // Mask Start Index
5611 NumElems-NumZeros, // Mask End Index(exclusive)
5612 NumZeros, // Where to start looking in the src vector
5613 NumElems, // Number of elements in vector
5614 OpSrc)) // Which source operand ?
5619 ShVal = SVOp->getOperand(OpSrc);
5623 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5624 /// logical left shift of a vector.
5625 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5626 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5628 SVOp->getSimpleValueType(0).getVectorNumElements();
5629 unsigned NumZeros = getNumOfConsecutiveZeros(
5630 SVOp, NumElems, true /* check zeros from left */, DAG,
5631 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5637 // Considering the elements in the mask that are not consecutive zeros,
5638 // check if they consecutively come from only one of the source vectors.
5640 // 0 { A, B, X, X } = V2
5642 // vector_shuffle V1, V2 <X, X, 4, 5>
5644 if (!isShuffleMaskConsecutive(SVOp,
5645 NumZeros, // Mask Start Index
5646 NumElems, // Mask End Index(exclusive)
5647 0, // Where to start looking in the src vector
5648 NumElems, // Number of elements in vector
5649 OpSrc)) // Which source operand ?
5654 ShVal = SVOp->getOperand(OpSrc);
5658 /// isVectorShift - Returns true if the shuffle can be implemented as a
5659 /// logical left or right shift of a vector.
5660 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5661 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5662 // Although the logic below support any bitwidth size, there are no
5663 // shift instructions which handle more than 128-bit vectors.
5664 if (!SVOp->getSimpleValueType(0).is128BitVector())
5667 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5668 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5674 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5676 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5677 unsigned NumNonZero, unsigned NumZero,
5679 const X86Subtarget* Subtarget,
5680 const TargetLowering &TLI) {
5687 for (unsigned i = 0; i < 16; ++i) {
5688 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5689 if (ThisIsNonZero && First) {
5691 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5693 V = DAG.getUNDEF(MVT::v8i16);
5698 SDValue ThisElt, LastElt;
5699 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5700 if (LastIsNonZero) {
5701 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5702 MVT::i16, Op.getOperand(i-1));
5704 if (ThisIsNonZero) {
5705 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5706 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5707 ThisElt, DAG.getConstant(8, MVT::i8));
5709 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5713 if (ThisElt.getNode())
5714 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5715 DAG.getIntPtrConstant(i/2));
5719 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5722 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5724 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5725 unsigned NumNonZero, unsigned NumZero,
5727 const X86Subtarget* Subtarget,
5728 const TargetLowering &TLI) {
5735 for (unsigned i = 0; i < 8; ++i) {
5736 bool isNonZero = (NonZeros & (1 << i)) != 0;
5740 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5742 V = DAG.getUNDEF(MVT::v8i16);
5745 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5746 MVT::v8i16, V, Op.getOperand(i),
5747 DAG.getIntPtrConstant(i));
5754 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5755 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5756 const X86Subtarget *Subtarget,
5757 const TargetLowering &TLI) {
5758 // Find all zeroable elements.
5760 for (int i=0; i < 4; ++i) {
5761 SDValue Elt = Op->getOperand(i);
5762 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5764 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5765 [](bool M) { return !M; }) > 1 &&
5766 "We expect at least two non-zero elements!");
5768 // We only know how to deal with build_vector nodes where elements are either
5769 // zeroable or extract_vector_elt with constant index.
5770 SDValue FirstNonZero;
5771 unsigned FirstNonZeroIdx;
5772 for (unsigned i=0; i < 4; ++i) {
5775 SDValue Elt = Op->getOperand(i);
5776 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5777 !isa<ConstantSDNode>(Elt.getOperand(1)))
5779 // Make sure that this node is extracting from a 128-bit vector.
5780 MVT VT = Elt.getOperand(0).getSimpleValueType();
5781 if (!VT.is128BitVector())
5783 if (!FirstNonZero.getNode()) {
5785 FirstNonZeroIdx = i;
5789 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5790 SDValue V1 = FirstNonZero.getOperand(0);
5791 MVT VT = V1.getSimpleValueType();
5793 // See if this build_vector can be lowered as a blend with zero.
5795 unsigned EltMaskIdx, EltIdx;
5797 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5798 if (Zeroable[EltIdx]) {
5799 // The zero vector will be on the right hand side.
5800 Mask[EltIdx] = EltIdx+4;
5804 Elt = Op->getOperand(EltIdx);
5805 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5806 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5807 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5809 Mask[EltIdx] = EltIdx;
5813 // Let the shuffle legalizer deal with blend operations.
5814 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5815 if (V1.getSimpleValueType() != VT)
5816 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5817 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5820 // See if we can lower this build_vector to a INSERTPS.
5821 if (!Subtarget->hasSSE41())
5824 SDValue V2 = Elt.getOperand(0);
5825 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5828 bool CanFold = true;
5829 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5833 SDValue Current = Op->getOperand(i);
5834 SDValue SrcVector = Current->getOperand(0);
5837 CanFold = SrcVector == V1 &&
5838 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5844 assert(V1.getNode() && "Expected at least two non-zero elements!");
5845 if (V1.getSimpleValueType() != MVT::v4f32)
5846 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5847 if (V2.getSimpleValueType() != MVT::v4f32)
5848 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5850 // Ok, we can emit an INSERTPS instruction.
5852 for (int i = 0; i < 4; ++i)
5856 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5857 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5858 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5859 DAG.getIntPtrConstant(InsertPSMask));
5860 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5863 /// getVShift - Return a vector logical shift node.
5865 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5866 unsigned NumBits, SelectionDAG &DAG,
5867 const TargetLowering &TLI, SDLoc dl) {
5868 assert(VT.is128BitVector() && "Unknown type for VShift");
5869 EVT ShVT = MVT::v2i64;
5870 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5871 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5872 return DAG.getNode(ISD::BITCAST, dl, VT,
5873 DAG.getNode(Opc, dl, ShVT, SrcOp,
5874 DAG.getConstant(NumBits,
5875 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5879 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5881 // Check if the scalar load can be widened into a vector load. And if
5882 // the address is "base + cst" see if the cst can be "absorbed" into
5883 // the shuffle mask.
5884 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5885 SDValue Ptr = LD->getBasePtr();
5886 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5888 EVT PVT = LD->getValueType(0);
5889 if (PVT != MVT::i32 && PVT != MVT::f32)
5894 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5895 FI = FINode->getIndex();
5897 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5898 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5899 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5900 Offset = Ptr.getConstantOperandVal(1);
5901 Ptr = Ptr.getOperand(0);
5906 // FIXME: 256-bit vector instructions don't require a strict alignment,
5907 // improve this code to support it better.
5908 unsigned RequiredAlign = VT.getSizeInBits()/8;
5909 SDValue Chain = LD->getChain();
5910 // Make sure the stack object alignment is at least 16 or 32.
5911 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5912 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5913 if (MFI->isFixedObjectIndex(FI)) {
5914 // Can't change the alignment. FIXME: It's possible to compute
5915 // the exact stack offset and reference FI + adjust offset instead.
5916 // If someone *really* cares about this. That's the way to implement it.
5919 MFI->setObjectAlignment(FI, RequiredAlign);
5923 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5924 // Ptr + (Offset & ~15).
5927 if ((Offset % RequiredAlign) & 3)
5929 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5931 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5932 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5934 int EltNo = (Offset - StartOffset) >> 2;
5935 unsigned NumElems = VT.getVectorNumElements();
5937 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5938 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5939 LD->getPointerInfo().getWithOffset(StartOffset),
5940 false, false, false, 0);
5942 SmallVector<int, 8> Mask;
5943 for (unsigned i = 0; i != NumElems; ++i)
5944 Mask.push_back(EltNo);
5946 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5952 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5953 /// vector of type 'VT', see if the elements can be replaced by a single large
5954 /// load which has the same value as a build_vector whose operands are 'elts'.
5956 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5958 /// FIXME: we'd also like to handle the case where the last elements are zero
5959 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5960 /// There's even a handy isZeroNode for that purpose.
5961 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5962 SDLoc &DL, SelectionDAG &DAG,
5963 bool isAfterLegalize) {
5964 EVT EltVT = VT.getVectorElementType();
5965 unsigned NumElems = Elts.size();
5967 LoadSDNode *LDBase = nullptr;
5968 unsigned LastLoadedElt = -1U;
5970 // For each element in the initializer, see if we've found a load or an undef.
5971 // If we don't find an initial load element, or later load elements are
5972 // non-consecutive, bail out.
5973 for (unsigned i = 0; i < NumElems; ++i) {
5974 SDValue Elt = Elts[i];
5976 if (!Elt.getNode() ||
5977 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5980 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5982 LDBase = cast<LoadSDNode>(Elt.getNode());
5986 if (Elt.getOpcode() == ISD::UNDEF)
5989 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5990 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5995 // If we have found an entire vector of loads and undefs, then return a large
5996 // load of the entire vector width starting at the base pointer. If we found
5997 // consecutive loads for the low half, generate a vzext_load node.
5998 if (LastLoadedElt == NumElems - 1) {
6000 if (isAfterLegalize &&
6001 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6004 SDValue NewLd = SDValue();
6006 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6007 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6008 LDBase->getPointerInfo(),
6009 LDBase->isVolatile(), LDBase->isNonTemporal(),
6010 LDBase->isInvariant(), 0);
6011 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6012 LDBase->getPointerInfo(),
6013 LDBase->isVolatile(), LDBase->isNonTemporal(),
6014 LDBase->isInvariant(), LDBase->getAlignment());
6016 if (LDBase->hasAnyUseOfValue(1)) {
6017 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6019 SDValue(NewLd.getNode(), 1));
6020 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6021 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6022 SDValue(NewLd.getNode(), 1));
6027 if (NumElems == 4 && LastLoadedElt == 1 &&
6028 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6029 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6030 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6032 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6033 LDBase->getPointerInfo(),
6034 LDBase->getAlignment(),
6035 false/*isVolatile*/, true/*ReadMem*/,
6038 // Make sure the newly-created LOAD is in the same position as LDBase in
6039 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6040 // update uses of LDBase's output chain to use the TokenFactor.
6041 if (LDBase->hasAnyUseOfValue(1)) {
6042 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6043 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6044 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6045 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6046 SDValue(ResNode.getNode(), 1));
6049 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6054 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6055 /// to generate a splat value for the following cases:
6056 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6057 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6058 /// a scalar load, or a constant.
6059 /// The VBROADCAST node is returned when a pattern is found,
6060 /// or SDValue() otherwise.
6061 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6062 SelectionDAG &DAG) {
6063 // VBROADCAST requires AVX.
6064 // TODO: Splats could be generated for non-AVX CPUs using SSE
6065 // instructions, but there's less potential gain for only 128-bit vectors.
6066 if (!Subtarget->hasAVX())
6069 MVT VT = Op.getSimpleValueType();
6072 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6073 "Unsupported vector type for broadcast.");
6078 switch (Op.getOpcode()) {
6080 // Unknown pattern found.
6083 case ISD::BUILD_VECTOR: {
6084 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6085 BitVector UndefElements;
6086 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6088 // We need a splat of a single value to use broadcast, and it doesn't
6089 // make any sense if the value is only in one element of the vector.
6090 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6094 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6095 Ld.getOpcode() == ISD::ConstantFP);
6097 // Make sure that all of the users of a non-constant load are from the
6098 // BUILD_VECTOR node.
6099 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6104 case ISD::VECTOR_SHUFFLE: {
6105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6107 // Shuffles must have a splat mask where the first element is
6109 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6112 SDValue Sc = Op.getOperand(0);
6113 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6114 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6116 if (!Subtarget->hasInt256())
6119 // Use the register form of the broadcast instruction available on AVX2.
6120 if (VT.getSizeInBits() >= 256)
6121 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6122 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6125 Ld = Sc.getOperand(0);
6126 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6127 Ld.getOpcode() == ISD::ConstantFP);
6129 // The scalar_to_vector node and the suspected
6130 // load node must have exactly one user.
6131 // Constants may have multiple users.
6133 // AVX-512 has register version of the broadcast
6134 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6135 Ld.getValueType().getSizeInBits() >= 32;
6136 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6143 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6144 bool IsGE256 = (VT.getSizeInBits() >= 256);
6146 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6147 // instruction to save 8 or more bytes of constant pool data.
6148 // TODO: If multiple splats are generated to load the same constant,
6149 // it may be detrimental to overall size. There needs to be a way to detect
6150 // that condition to know if this is truly a size win.
6151 const Function *F = DAG.getMachineFunction().getFunction();
6152 bool OptForSize = F->getAttributes().
6153 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6155 // Handle broadcasting a single constant scalar from the constant pool
6157 // On Sandybridge (no AVX2), it is still better to load a constant vector
6158 // from the constant pool and not to broadcast it from a scalar.
6159 // But override that restriction when optimizing for size.
6160 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6161 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6162 EVT CVT = Ld.getValueType();
6163 assert(!CVT.isVector() && "Must not broadcast a vector type");
6165 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6166 // For size optimization, also splat v2f64 and v2i64, and for size opt
6167 // with AVX2, also splat i8 and i16.
6168 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6169 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6170 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6171 const Constant *C = nullptr;
6172 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6173 C = CI->getConstantIntValue();
6174 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6175 C = CF->getConstantFPValue();
6177 assert(C && "Invalid constant type");
6179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6180 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6181 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6182 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6183 MachinePointerInfo::getConstantPool(),
6184 false, false, false, Alignment);
6186 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6192 // Handle AVX2 in-register broadcasts.
6193 if (!IsLoad && Subtarget->hasInt256() &&
6194 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6195 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // The scalar source must be a normal load.
6201 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6202 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6204 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6205 // double since there is no vbroadcastsd xmm
6206 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6207 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6208 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6211 // Unsupported broadcast.
6215 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6216 /// underlying vector and index.
6218 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6220 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6222 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6223 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6226 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6228 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6230 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6231 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6234 // In this case the vector is the extract_subvector expression and the index
6235 // is 2, as specified by the shuffle.
6236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6237 SDValue ShuffleVec = SVOp->getOperand(0);
6238 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6239 assert(ShuffleVecVT.getVectorElementType() ==
6240 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6242 int ShuffleIdx = SVOp->getMaskElt(Idx);
6243 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6244 ExtractedFromVec = ShuffleVec;
6250 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6251 MVT VT = Op.getSimpleValueType();
6253 // Skip if insert_vec_elt is not supported.
6254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6255 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6259 unsigned NumElems = Op.getNumOperands();
6263 SmallVector<unsigned, 4> InsertIndices;
6264 SmallVector<int, 8> Mask(NumElems, -1);
6266 for (unsigned i = 0; i != NumElems; ++i) {
6267 unsigned Opc = Op.getOperand(i).getOpcode();
6269 if (Opc == ISD::UNDEF)
6272 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6273 // Quit if more than 1 elements need inserting.
6274 if (InsertIndices.size() > 1)
6277 InsertIndices.push_back(i);
6281 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6282 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6283 // Quit if non-constant index.
6284 if (!isa<ConstantSDNode>(ExtIdx))
6286 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6288 // Quit if extracted from vector of different type.
6289 if (ExtractedFromVec.getValueType() != VT)
6292 if (!VecIn1.getNode())
6293 VecIn1 = ExtractedFromVec;
6294 else if (VecIn1 != ExtractedFromVec) {
6295 if (!VecIn2.getNode())
6296 VecIn2 = ExtractedFromVec;
6297 else if (VecIn2 != ExtractedFromVec)
6298 // Quit if more than 2 vectors to shuffle
6302 if (ExtractedFromVec == VecIn1)
6304 else if (ExtractedFromVec == VecIn2)
6305 Mask[i] = Idx + NumElems;
6308 if (!VecIn1.getNode())
6311 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6312 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6313 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6314 unsigned Idx = InsertIndices[i];
6315 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6316 DAG.getIntPtrConstant(Idx));
6322 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6324 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6326 MVT VT = Op.getSimpleValueType();
6327 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6328 "Unexpected type in LowerBUILD_VECTORvXi1!");
6331 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6332 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6333 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6334 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6337 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6338 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6339 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6340 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6343 bool AllContants = true;
6344 uint64_t Immediate = 0;
6345 int NonConstIdx = -1;
6346 bool IsSplat = true;
6347 unsigned NumNonConsts = 0;
6348 unsigned NumConsts = 0;
6349 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6350 SDValue In = Op.getOperand(idx);
6351 if (In.getOpcode() == ISD::UNDEF)
6353 if (!isa<ConstantSDNode>(In)) {
6354 AllContants = false;
6359 if (cast<ConstantSDNode>(In)->getZExtValue())
6360 Immediate |= (1ULL << idx);
6362 if (In != Op.getOperand(0))
6367 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6368 DAG.getConstant(Immediate, MVT::i16));
6369 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6370 DAG.getIntPtrConstant(0));
6373 if (NumNonConsts == 1 && NonConstIdx != 0) {
6376 SDValue VecAsImm = DAG.getConstant(Immediate,
6377 MVT::getIntegerVT(VT.getSizeInBits()));
6378 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6381 DstVec = DAG.getUNDEF(VT);
6382 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6383 Op.getOperand(NonConstIdx),
6384 DAG.getIntPtrConstant(NonConstIdx));
6386 if (!IsSplat && (NonConstIdx != 0))
6387 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6388 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6391 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6392 DAG.getConstant(-1, SelectVT),
6393 DAG.getConstant(0, SelectVT));
6395 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6396 DAG.getConstant((Immediate | 1), SelectVT),
6397 DAG.getConstant(Immediate, SelectVT));
6398 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6401 /// \brief Return true if \p N implements a horizontal binop and return the
6402 /// operands for the horizontal binop into V0 and V1.
6404 /// This is a helper function of PerformBUILD_VECTORCombine.
6405 /// This function checks that the build_vector \p N in input implements a
6406 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6407 /// operation to match.
6408 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6409 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6410 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6413 /// This function only analyzes elements of \p N whose indices are
6414 /// in range [BaseIdx, LastIdx).
6415 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6417 unsigned BaseIdx, unsigned LastIdx,
6418 SDValue &V0, SDValue &V1) {
6419 EVT VT = N->getValueType(0);
6421 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6422 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6423 "Invalid Vector in input!");
6425 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6426 bool CanFold = true;
6427 unsigned ExpectedVExtractIdx = BaseIdx;
6428 unsigned NumElts = LastIdx - BaseIdx;
6429 V0 = DAG.getUNDEF(VT);
6430 V1 = DAG.getUNDEF(VT);
6432 // Check if N implements a horizontal binop.
6433 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6434 SDValue Op = N->getOperand(i + BaseIdx);
6437 if (Op->getOpcode() == ISD::UNDEF) {
6438 // Update the expected vector extract index.
6439 if (i * 2 == NumElts)
6440 ExpectedVExtractIdx = BaseIdx;
6441 ExpectedVExtractIdx += 2;
6445 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6450 SDValue Op0 = Op.getOperand(0);
6451 SDValue Op1 = Op.getOperand(1);
6453 // Try to match the following pattern:
6454 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6455 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6456 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6457 Op0.getOperand(0) == Op1.getOperand(0) &&
6458 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6459 isa<ConstantSDNode>(Op1.getOperand(1)));
6463 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6464 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6466 if (i * 2 < NumElts) {
6467 if (V0.getOpcode() == ISD::UNDEF)
6468 V0 = Op0.getOperand(0);
6470 if (V1.getOpcode() == ISD::UNDEF)
6471 V1 = Op0.getOperand(0);
6472 if (i * 2 == NumElts)
6473 ExpectedVExtractIdx = BaseIdx;
6476 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6477 if (I0 == ExpectedVExtractIdx)
6478 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6479 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6480 // Try to match the following dag sequence:
6481 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6482 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6486 ExpectedVExtractIdx += 2;
6492 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6493 /// a concat_vector.
6495 /// This is a helper function of PerformBUILD_VECTORCombine.
6496 /// This function expects two 256-bit vectors called V0 and V1.
6497 /// At first, each vector is split into two separate 128-bit vectors.
6498 /// Then, the resulting 128-bit vectors are used to implement two
6499 /// horizontal binary operations.
6501 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6503 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6504 /// the two new horizontal binop.
6505 /// When Mode is set, the first horizontal binop dag node would take as input
6506 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6507 /// horizontal binop dag node would take as input the lower 128-bit of V1
6508 /// and the upper 128-bit of V1.
6510 /// HADD V0_LO, V0_HI
6511 /// HADD V1_LO, V1_HI
6513 /// Otherwise, the first horizontal binop dag node takes as input the lower
6514 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6515 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6517 /// HADD V0_LO, V1_LO
6518 /// HADD V0_HI, V1_HI
6520 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6521 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6522 /// the upper 128-bits of the result.
6523 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6524 SDLoc DL, SelectionDAG &DAG,
6525 unsigned X86Opcode, bool Mode,
6526 bool isUndefLO, bool isUndefHI) {
6527 EVT VT = V0.getValueType();
6528 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6529 "Invalid nodes in input!");
6531 unsigned NumElts = VT.getVectorNumElements();
6532 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6533 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6534 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6535 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6536 EVT NewVT = V0_LO.getValueType();
6538 SDValue LO = DAG.getUNDEF(NewVT);
6539 SDValue HI = DAG.getUNDEF(NewVT);
6542 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6543 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6544 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6545 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6546 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6548 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6549 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6550 V1_LO->getOpcode() != ISD::UNDEF))
6551 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6553 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6554 V1_HI->getOpcode() != ISD::UNDEF))
6555 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6558 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6561 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6562 /// sequence of 'vadd + vsub + blendi'.
6563 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6564 const X86Subtarget *Subtarget) {
6566 EVT VT = BV->getValueType(0);
6567 unsigned NumElts = VT.getVectorNumElements();
6568 SDValue InVec0 = DAG.getUNDEF(VT);
6569 SDValue InVec1 = DAG.getUNDEF(VT);
6571 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6572 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6574 // Odd-numbered elements in the input build vector are obtained from
6575 // adding two integer/float elements.
6576 // Even-numbered elements in the input build vector are obtained from
6577 // subtracting two integer/float elements.
6578 unsigned ExpectedOpcode = ISD::FSUB;
6579 unsigned NextExpectedOpcode = ISD::FADD;
6580 bool AddFound = false;
6581 bool SubFound = false;
6583 for (unsigned i = 0, e = NumElts; i != e; i++) {
6584 SDValue Op = BV->getOperand(i);
6586 // Skip 'undef' values.
6587 unsigned Opcode = Op.getOpcode();
6588 if (Opcode == ISD::UNDEF) {
6589 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Early exit if we found an unexpected opcode.
6594 if (Opcode != ExpectedOpcode)
6597 SDValue Op0 = Op.getOperand(0);
6598 SDValue Op1 = Op.getOperand(1);
6600 // Try to match the following pattern:
6601 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6602 // Early exit if we cannot match that sequence.
6603 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6604 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6605 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6606 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6607 Op0.getOperand(1) != Op1.getOperand(1))
6610 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6614 // We found a valid add/sub node. Update the information accordingly.
6620 // Update InVec0 and InVec1.
6621 if (InVec0.getOpcode() == ISD::UNDEF)
6622 InVec0 = Op0.getOperand(0);
6623 if (InVec1.getOpcode() == ISD::UNDEF)
6624 InVec1 = Op1.getOperand(0);
6626 // Make sure that operands in input to each add/sub node always
6627 // come from a same pair of vectors.
6628 if (InVec0 != Op0.getOperand(0)) {
6629 if (ExpectedOpcode == ISD::FSUB)
6632 // FADD is commutable. Try to commute the operands
6633 // and then test again.
6634 std::swap(Op0, Op1);
6635 if (InVec0 != Op0.getOperand(0))
6639 if (InVec1 != Op1.getOperand(0))
6642 // Update the pair of expected opcodes.
6643 std::swap(ExpectedOpcode, NextExpectedOpcode);
6646 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6647 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6648 InVec1.getOpcode() != ISD::UNDEF)
6649 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6654 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6655 const X86Subtarget *Subtarget) {
6657 EVT VT = N->getValueType(0);
6658 unsigned NumElts = VT.getVectorNumElements();
6659 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6660 SDValue InVec0, InVec1;
6662 // Try to match an ADDSUB.
6663 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6664 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6665 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6666 if (Value.getNode())
6670 // Try to match horizontal ADD/SUB.
6671 unsigned NumUndefsLO = 0;
6672 unsigned NumUndefsHI = 0;
6673 unsigned Half = NumElts/2;
6675 // Count the number of UNDEF operands in the build_vector in input.
6676 for (unsigned i = 0, e = Half; i != e; ++i)
6677 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6680 for (unsigned i = Half, e = NumElts; i != e; ++i)
6681 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6684 // Early exit if this is either a build_vector of all UNDEFs or all the
6685 // operands but one are UNDEF.
6686 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6689 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6690 // Try to match an SSE3 float HADD/HSUB.
6691 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6692 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6694 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6695 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6696 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6697 // Try to match an SSSE3 integer HADD/HSUB.
6698 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6699 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6701 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6702 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6705 if (!Subtarget->hasAVX())
6708 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6709 // Try to match an AVX horizontal add/sub of packed single/double
6710 // precision floating point values from 256-bit vectors.
6711 SDValue InVec2, InVec3;
6712 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6713 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6714 ((InVec0.getOpcode() == ISD::UNDEF ||
6715 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6716 ((InVec1.getOpcode() == ISD::UNDEF ||
6717 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6718 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6720 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6727 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6728 // Try to match an AVX2 horizontal add/sub of signed integers.
6729 SDValue InVec2, InVec3;
6731 bool CanFold = true;
6733 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6734 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6735 ((InVec0.getOpcode() == ISD::UNDEF ||
6736 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6737 ((InVec1.getOpcode() == ISD::UNDEF ||
6738 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6739 X86Opcode = X86ISD::HADD;
6740 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6741 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6742 ((InVec0.getOpcode() == ISD::UNDEF ||
6743 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6744 ((InVec1.getOpcode() == ISD::UNDEF ||
6745 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6746 X86Opcode = X86ISD::HSUB;
6751 // Fold this build_vector into a single horizontal add/sub.
6752 // Do this only if the target has AVX2.
6753 if (Subtarget->hasAVX2())
6754 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6756 // Do not try to expand this build_vector into a pair of horizontal
6757 // add/sub if we can emit a pair of scalar add/sub.
6758 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6761 // Convert this build_vector into a pair of horizontal binop followed by
6763 bool isUndefLO = NumUndefsLO == Half;
6764 bool isUndefHI = NumUndefsHI == Half;
6765 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6766 isUndefLO, isUndefHI);
6770 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6771 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6773 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6774 X86Opcode = X86ISD::HADD;
6775 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6776 X86Opcode = X86ISD::HSUB;
6777 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6778 X86Opcode = X86ISD::FHADD;
6779 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6780 X86Opcode = X86ISD::FHSUB;
6784 // Don't try to expand this build_vector into a pair of horizontal add/sub
6785 // if we can simply emit a pair of scalar add/sub.
6786 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6789 // Convert this build_vector into two horizontal add/sub followed by
6791 bool isUndefLO = NumUndefsLO == Half;
6792 bool isUndefHI = NumUndefsHI == Half;
6793 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6794 isUndefLO, isUndefHI);
6801 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6804 MVT VT = Op.getSimpleValueType();
6805 MVT ExtVT = VT.getVectorElementType();
6806 unsigned NumElems = Op.getNumOperands();
6808 // Generate vectors for predicate vectors.
6809 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6810 return LowerBUILD_VECTORvXi1(Op, DAG);
6812 // Vectors containing all zeros can be matched by pxor and xorps later
6813 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6814 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6815 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6816 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6819 return getZeroVector(VT, Subtarget, DAG, dl);
6822 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6823 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6824 // vpcmpeqd on 256-bit vectors.
6825 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6826 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6829 if (!VT.is512BitVector())
6830 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6833 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6834 if (Broadcast.getNode())
6837 unsigned EVTBits = ExtVT.getSizeInBits();
6839 unsigned NumZero = 0;
6840 unsigned NumNonZero = 0;
6841 unsigned NonZeros = 0;
6842 bool IsAllConstants = true;
6843 SmallSet<SDValue, 8> Values;
6844 for (unsigned i = 0; i < NumElems; ++i) {
6845 SDValue Elt = Op.getOperand(i);
6846 if (Elt.getOpcode() == ISD::UNDEF)
6849 if (Elt.getOpcode() != ISD::Constant &&
6850 Elt.getOpcode() != ISD::ConstantFP)
6851 IsAllConstants = false;
6852 if (X86::isZeroNode(Elt))
6855 NonZeros |= (1 << i);
6860 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6861 if (NumNonZero == 0)
6862 return DAG.getUNDEF(VT);
6864 // Special case for single non-zero, non-undef, element.
6865 if (NumNonZero == 1) {
6866 unsigned Idx = countTrailingZeros(NonZeros);
6867 SDValue Item = Op.getOperand(Idx);
6869 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6870 // the value are obviously zero, truncate the value to i32 and do the
6871 // insertion that way. Only do this if the value is non-constant or if the
6872 // value is a constant being inserted into element 0. It is cheaper to do
6873 // a constant pool load than it is to do a movd + shuffle.
6874 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6875 (!IsAllConstants || Idx == 0)) {
6876 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6878 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6879 EVT VecVT = MVT::v4i32;
6880 unsigned VecElts = 4;
6882 // Truncate the value (which may itself be a constant) to i32, and
6883 // convert it to a vector with movd (S2V+shuffle to zero extend).
6884 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6885 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6887 // If using the new shuffle lowering, just directly insert this.
6888 if (ExperimentalVectorShuffleLowering)
6890 ISD::BITCAST, dl, VT,
6891 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6893 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6895 // Now we have our 32-bit value zero extended in the low element of
6896 // a vector. If Idx != 0, swizzle it into place.
6898 SmallVector<int, 4> Mask;
6899 Mask.push_back(Idx);
6900 for (unsigned i = 1; i != VecElts; ++i)
6902 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6905 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6909 // If we have a constant or non-constant insertion into the low element of
6910 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6911 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6912 // depending on what the source datatype is.
6915 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6917 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6918 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6919 if (VT.is256BitVector() || VT.is512BitVector()) {
6920 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6921 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6922 Item, DAG.getIntPtrConstant(0));
6924 assert(VT.is128BitVector() && "Expected an SSE value type!");
6925 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6926 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6927 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6930 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6931 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6932 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6933 if (VT.is256BitVector()) {
6934 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6935 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6937 assert(VT.is128BitVector() && "Expected an SSE value type!");
6938 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6940 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6944 // Is it a vector logical left shift?
6945 if (NumElems == 2 && Idx == 1 &&
6946 X86::isZeroNode(Op.getOperand(0)) &&
6947 !X86::isZeroNode(Op.getOperand(1))) {
6948 unsigned NumBits = VT.getSizeInBits();
6949 return getVShift(true, VT,
6950 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6951 VT, Op.getOperand(1)),
6952 NumBits/2, DAG, *this, dl);
6955 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6958 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6959 // is a non-constant being inserted into an element other than the low one,
6960 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6961 // movd/movss) to move this into the low element, then shuffle it into
6963 if (EVTBits == 32) {
6964 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6966 // If using the new shuffle lowering, just directly insert this.
6967 if (ExperimentalVectorShuffleLowering)
6968 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6970 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6971 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6972 SmallVector<int, 8> MaskVec;
6973 for (unsigned i = 0; i != NumElems; ++i)
6974 MaskVec.push_back(i == Idx ? 0 : 1);
6975 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6979 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6980 if (Values.size() == 1) {
6981 if (EVTBits == 32) {
6982 // Instead of a shuffle like this:
6983 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6984 // Check if it's possible to issue this instead.
6985 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6986 unsigned Idx = countTrailingZeros(NonZeros);
6987 SDValue Item = Op.getOperand(Idx);
6988 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6989 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6994 // A vector full of immediates; various special cases are already
6995 // handled, so this is best done with a single constant-pool load.
6999 // For AVX-length vectors, build the individual 128-bit pieces and use
7000 // shuffles to put them in place.
7001 if (VT.is256BitVector() || VT.is512BitVector()) {
7002 SmallVector<SDValue, 64> V;
7003 for (unsigned i = 0; i != NumElems; ++i)
7004 V.push_back(Op.getOperand(i));
7006 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7008 // Build both the lower and upper subvector.
7009 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7010 makeArrayRef(&V[0], NumElems/2));
7011 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7012 makeArrayRef(&V[NumElems / 2], NumElems/2));
7014 // Recreate the wider vector with the lower and upper part.
7015 if (VT.is256BitVector())
7016 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7017 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7020 // Let legalizer expand 2-wide build_vectors.
7021 if (EVTBits == 64) {
7022 if (NumNonZero == 1) {
7023 // One half is zero or undef.
7024 unsigned Idx = countTrailingZeros(NonZeros);
7025 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7026 Op.getOperand(Idx));
7027 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7032 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7033 if (EVTBits == 8 && NumElems == 16) {
7034 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7036 if (V.getNode()) return V;
7039 if (EVTBits == 16 && NumElems == 8) {
7040 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7042 if (V.getNode()) return V;
7045 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7046 if (EVTBits == 32 && NumElems == 4) {
7047 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7052 // If element VT is == 32 bits, turn it into a number of shuffles.
7053 SmallVector<SDValue, 8> V(NumElems);
7054 if (NumElems == 4 && NumZero > 0) {
7055 for (unsigned i = 0; i < 4; ++i) {
7056 bool isZero = !(NonZeros & (1 << i));
7058 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7060 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7063 for (unsigned i = 0; i < 2; ++i) {
7064 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7067 V[i] = V[i*2]; // Must be a zero vector.
7070 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7073 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7076 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7081 bool Reverse1 = (NonZeros & 0x3) == 2;
7082 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7086 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7087 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7089 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7092 if (Values.size() > 1 && VT.is128BitVector()) {
7093 // Check for a build vector of consecutive loads.
7094 for (unsigned i = 0; i < NumElems; ++i)
7095 V[i] = Op.getOperand(i);
7097 // Check for elements which are consecutive loads.
7098 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7102 // Check for a build vector from mostly shuffle plus few inserting.
7103 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7107 // For SSE 4.1, use insertps to put the high elements into the low element.
7108 if (getSubtarget()->hasSSE41()) {
7110 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7111 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7113 Result = DAG.getUNDEF(VT);
7115 for (unsigned i = 1; i < NumElems; ++i) {
7116 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7117 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7118 Op.getOperand(i), DAG.getIntPtrConstant(i));
7123 // Otherwise, expand into a number of unpckl*, start by extending each of
7124 // our (non-undef) elements to the full vector width with the element in the
7125 // bottom slot of the vector (which generates no code for SSE).
7126 for (unsigned i = 0; i < NumElems; ++i) {
7127 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7128 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7130 V[i] = DAG.getUNDEF(VT);
7133 // Next, we iteratively mix elements, e.g. for v4f32:
7134 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7135 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7136 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7137 unsigned EltStride = NumElems >> 1;
7138 while (EltStride != 0) {
7139 for (unsigned i = 0; i < EltStride; ++i) {
7140 // If V[i+EltStride] is undef and this is the first round of mixing,
7141 // then it is safe to just drop this shuffle: V[i] is already in the
7142 // right place, the one element (since it's the first round) being
7143 // inserted as undef can be dropped. This isn't safe for successive
7144 // rounds because they will permute elements within both vectors.
7145 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7146 EltStride == NumElems/2)
7149 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7158 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7159 // to create 256-bit vectors from two other 128-bit ones.
7160 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7162 MVT ResVT = Op.getSimpleValueType();
7164 assert((ResVT.is256BitVector() ||
7165 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7167 SDValue V1 = Op.getOperand(0);
7168 SDValue V2 = Op.getOperand(1);
7169 unsigned NumElems = ResVT.getVectorNumElements();
7170 if(ResVT.is256BitVector())
7171 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7173 if (Op.getNumOperands() == 4) {
7174 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7175 ResVT.getVectorNumElements()/2);
7176 SDValue V3 = Op.getOperand(2);
7177 SDValue V4 = Op.getOperand(3);
7178 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7179 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7181 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7184 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7185 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7186 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7187 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7188 Op.getNumOperands() == 4)));
7190 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7191 // from two other 128-bit ones.
7193 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7194 return LowerAVXCONCAT_VECTORS(Op, DAG);
7198 //===----------------------------------------------------------------------===//
7199 // Vector shuffle lowering
7201 // This is an experimental code path for lowering vector shuffles on x86. It is
7202 // designed to handle arbitrary vector shuffles and blends, gracefully
7203 // degrading performance as necessary. It works hard to recognize idiomatic
7204 // shuffles and lower them to optimal instruction patterns without leaving
7205 // a framework that allows reasonably efficient handling of all vector shuffle
7207 //===----------------------------------------------------------------------===//
7209 /// \brief Tiny helper function to identify a no-op mask.
7211 /// This is a somewhat boring predicate function. It checks whether the mask
7212 /// array input, which is assumed to be a single-input shuffle mask of the kind
7213 /// used by the X86 shuffle instructions (not a fully general
7214 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7215 /// in-place shuffle are 'no-op's.
7216 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7217 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7218 if (Mask[i] != -1 && Mask[i] != i)
7223 /// \brief Helper function to classify a mask as a single-input mask.
7225 /// This isn't a generic single-input test because in the vector shuffle
7226 /// lowering we canonicalize single inputs to be the first input operand. This
7227 /// means we can more quickly test for a single input by only checking whether
7228 /// an input from the second operand exists. We also assume that the size of
7229 /// mask corresponds to the size of the input vectors which isn't true in the
7230 /// fully general case.
7231 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7233 if (M >= (int)Mask.size())
7238 /// \brief Test whether there are elements crossing 128-bit lanes in this
7241 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7242 /// and we routinely test for these.
7243 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7244 int LaneSize = 128 / VT.getScalarSizeInBits();
7245 int Size = Mask.size();
7246 for (int i = 0; i < Size; ++i)
7247 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7252 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7254 /// This checks a shuffle mask to see if it is performing the same
7255 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7256 /// that it is also not lane-crossing. It may however involve a blend from the
7257 /// same lane of a second vector.
7259 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7260 /// non-trivial to compute in the face of undef lanes. The representation is
7261 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7262 /// entries from both V1 and V2 inputs to the wider mask.
7264 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7265 SmallVectorImpl<int> &RepeatedMask) {
7266 int LaneSize = 128 / VT.getScalarSizeInBits();
7267 RepeatedMask.resize(LaneSize, -1);
7268 int Size = Mask.size();
7269 for (int i = 0; i < Size; ++i) {
7272 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7273 // This entry crosses lanes, so there is no way to model this shuffle.
7276 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7277 if (RepeatedMask[i % LaneSize] == -1)
7278 // This is the first non-undef entry in this slot of a 128-bit lane.
7279 RepeatedMask[i % LaneSize] =
7280 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7281 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7282 // Found a mismatch with the repeated mask.
7288 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7289 // 2013 will allow us to use it as a non-type template parameter.
7292 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7294 /// See its documentation for details.
7295 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7296 if (Mask.size() != Args.size())
7298 for (int i = 0, e = Mask.size(); i < e; ++i) {
7299 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7300 if (Mask[i] != -1 && Mask[i] != *Args[i])
7308 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7311 /// This is a fast way to test a shuffle mask against a fixed pattern:
7313 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7315 /// It returns true if the mask is exactly as wide as the argument list, and
7316 /// each element of the mask is either -1 (signifying undef) or the value given
7317 /// in the argument.
7318 static const VariadicFunction1<
7319 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7321 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7323 /// This helper function produces an 8-bit shuffle immediate corresponding to
7324 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7325 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7328 /// NB: We rely heavily on "undef" masks preserving the input lane.
7329 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7330 SelectionDAG &DAG) {
7331 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7332 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7333 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7334 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7335 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7338 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7339 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7340 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7341 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7342 return DAG.getConstant(Imm, MVT::i8);
7345 /// \brief Try to emit a blend instruction for a shuffle.
7347 /// This doesn't do any checks for the availability of instructions for blending
7348 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7349 /// be matched in the backend with the type given. What it does check for is
7350 /// that the shuffle mask is in fact a blend.
7351 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7352 SDValue V2, ArrayRef<int> Mask,
7353 const X86Subtarget *Subtarget,
7354 SelectionDAG &DAG) {
7356 unsigned BlendMask = 0;
7357 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7358 if (Mask[i] >= Size) {
7359 if (Mask[i] != i + Size)
7360 return SDValue(); // Shuffled V2 input!
7361 BlendMask |= 1u << i;
7364 if (Mask[i] >= 0 && Mask[i] != i)
7365 return SDValue(); // Shuffled V1 input!
7367 switch (VT.SimpleTy) {
7372 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7373 DAG.getConstant(BlendMask, MVT::i8));
7377 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7381 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7382 // that instruction.
7383 if (Subtarget->hasAVX2()) {
7384 // Scale the blend by the number of 32-bit dwords per element.
7385 int Scale = VT.getScalarSizeInBits() / 32;
7387 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7388 if (Mask[i] >= Size)
7389 for (int j = 0; j < Scale; ++j)
7390 BlendMask |= 1u << (i * Scale + j);
7392 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7393 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7394 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7395 return DAG.getNode(ISD::BITCAST, DL, VT,
7396 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7397 DAG.getConstant(BlendMask, MVT::i8)));
7401 // For integer shuffles we need to expand the mask and cast the inputs to
7402 // v8i16s prior to blending.
7403 int Scale = 8 / VT.getVectorNumElements();
7405 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7406 if (Mask[i] >= Size)
7407 for (int j = 0; j < Scale; ++j)
7408 BlendMask |= 1u << (i * Scale + j);
7410 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7411 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7412 return DAG.getNode(ISD::BITCAST, DL, VT,
7413 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7414 DAG.getConstant(BlendMask, MVT::i8)));
7418 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7419 SmallVector<int, 8> RepeatedMask;
7420 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7421 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7422 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7424 for (int i = 0; i < 8; ++i)
7425 if (RepeatedMask[i] >= 16)
7426 BlendMask |= 1u << i;
7427 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7428 DAG.getConstant(BlendMask, MVT::i8));
7433 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7434 // Scale the blend by the number of bytes per element.
7435 int Scale = VT.getScalarSizeInBits() / 8;
7436 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7438 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7439 // mix of LLVM's code generator and the x86 backend. We tell the code
7440 // generator that boolean values in the elements of an x86 vector register
7441 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7442 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7443 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7444 // of the element (the remaining are ignored) and 0 in that high bit would
7445 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7446 // the LLVM model for boolean values in vector elements gets the relevant
7447 // bit set, it is set backwards and over constrained relative to x86's
7449 SDValue VSELECTMask[32];
7450 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7451 for (int j = 0; j < Scale; ++j)
7452 VSELECTMask[Scale * i + j] =
7453 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7454 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7456 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7457 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7459 ISD::BITCAST, DL, VT,
7460 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7461 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7466 llvm_unreachable("Not a supported integer vector type!");
7470 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7471 /// unblended shuffles followed by an unshuffled blend.
7473 /// This matches the extremely common pattern for handling combined
7474 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7476 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7480 SelectionDAG &DAG) {
7481 // Shuffle the input elements into the desired positions in V1 and V2 and
7482 // blend them together.
7483 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7484 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7485 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7486 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7487 if (Mask[i] >= 0 && Mask[i] < Size) {
7488 V1Mask[i] = Mask[i];
7490 } else if (Mask[i] >= Size) {
7491 V2Mask[i] = Mask[i] - Size;
7492 BlendMask[i] = i + Size;
7495 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7496 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7497 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7500 /// \brief Try to lower a vector shuffle as a byte rotation.
7502 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7503 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7504 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7505 /// try to generically lower a vector shuffle through such an pattern. It
7506 /// does not check for the profitability of lowering either as PALIGNR or
7507 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7508 /// This matches shuffle vectors that look like:
7510 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7512 /// Essentially it concatenates V1 and V2, shifts right by some number of
7513 /// elements, and takes the low elements as the result. Note that while this is
7514 /// specified as a *right shift* because x86 is little-endian, it is a *left
7515 /// rotate* of the vector lanes.
7517 /// Note that this only handles 128-bit vector widths currently.
7518 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7521 const X86Subtarget *Subtarget,
7522 SelectionDAG &DAG) {
7523 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7525 // We need to detect various ways of spelling a rotation:
7526 // [11, 12, 13, 14, 15, 0, 1, 2]
7527 // [-1, 12, 13, 14, -1, -1, 1, -1]
7528 // [-1, -1, -1, -1, -1, -1, 1, 2]
7529 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7530 // [-1, 4, 5, 6, -1, -1, 9, -1]
7531 // [-1, 4, 5, 6, -1, -1, -1, -1]
7534 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7537 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7539 // Based on the mod-Size value of this mask element determine where
7540 // a rotated vector would have started.
7541 int StartIdx = i - (Mask[i] % Size);
7543 // The identity rotation isn't interesting, stop.
7546 // If we found the tail of a vector the rotation must be the missing
7547 // front. If we found the head of a vector, it must be how much of the head.
7548 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7551 Rotation = CandidateRotation;
7552 else if (Rotation != CandidateRotation)
7553 // The rotations don't match, so we can't match this mask.
7556 // Compute which value this mask is pointing at.
7557 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7559 // Compute which of the two target values this index should be assigned to.
7560 // This reflects whether the high elements are remaining or the low elements
7562 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7564 // Either set up this value if we've not encountered it before, or check
7565 // that it remains consistent.
7568 else if (TargetV != MaskV)
7569 // This may be a rotation, but it pulls from the inputs in some
7570 // unsupported interleaving.
7574 // Check that we successfully analyzed the mask, and normalize the results.
7575 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7576 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7582 assert(VT.getSizeInBits() == 128 &&
7583 "Rotate-based lowering only supports 128-bit lowering!");
7584 assert(Mask.size() <= 16 &&
7585 "Can shuffle at most 16 bytes in a 128-bit vector!");
7587 // The actual rotate instruction rotates bytes, so we need to scale the
7588 // rotation based on how many bytes are in the vector.
7589 int Scale = 16 / Mask.size();
7591 // SSSE3 targets can use the palignr instruction
7592 if (Subtarget->hasSSSE3()) {
7593 // Cast the inputs to v16i8 to match PALIGNR.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7597 return DAG.getNode(ISD::BITCAST, DL, VT,
7598 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7599 DAG.getConstant(Rotation * Scale, MVT::i8)));
7602 // Default SSE2 implementation
7603 int LoByteShift = 16 - Rotation * Scale;
7604 int HiByteShift = Rotation * Scale;
7606 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7607 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7608 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7610 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7611 DAG.getConstant(8 * LoByteShift, MVT::i8));
7612 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7613 DAG.getConstant(8 * HiByteShift, MVT::i8));
7614 return DAG.getNode(ISD::BITCAST, DL, VT,
7615 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7618 /// \brief Compute whether each element of a shuffle is zeroable.
7620 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7621 /// Either it is an undef element in the shuffle mask, the element of the input
7622 /// referenced is undef, or the element of the input referenced is known to be
7623 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7624 /// as many lanes with this technique as possible to simplify the remaining
7626 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7627 SDValue V1, SDValue V2) {
7628 SmallBitVector Zeroable(Mask.size(), false);
7630 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7631 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7633 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7635 // Handle the easy cases.
7636 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7641 // If this is an index into a build_vector node, dig out the input value and
7643 SDValue V = M < Size ? V1 : V2;
7644 if (V.getOpcode() != ISD::BUILD_VECTOR)
7647 SDValue Input = V.getOperand(M % Size);
7648 // The UNDEF opcode check really should be dead code here, but not quite
7649 // worth asserting on (it isn't invalid, just unexpected).
7650 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7657 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7659 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7660 /// byte-shift instructions. The mask must consist of a shifted sequential
7661 /// shuffle from one of the input vectors and zeroable elements for the
7662 /// remaining 'shifted in' elements.
7664 /// Note that this only handles 128-bit vector widths currently.
7665 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7666 SDValue V2, ArrayRef<int> Mask,
7667 SelectionDAG &DAG) {
7668 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7670 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7672 int Size = Mask.size();
7673 int Scale = 16 / Size;
7675 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7676 ArrayRef<int> Mask) {
7677 for (int i = StartIndex; i < EndIndex; i++) {
7680 if (i + Base != Mask[i] - MaskOffset)
7686 for (int Shift = 1; Shift < Size; Shift++) {
7687 int ByteShift = Shift * Scale;
7689 // PSRLDQ : (little-endian) right byte shift
7690 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7691 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7692 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7693 bool ZeroableRight = true;
7694 for (int i = Size - Shift; i < Size; i++) {
7695 ZeroableRight &= Zeroable[i];
7698 if (ZeroableRight) {
7699 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7700 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7702 if (ValidShiftRight1 || ValidShiftRight2) {
7703 // Cast the inputs to v2i64 to match PSRLDQ.
7704 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7705 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7706 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7707 DAG.getConstant(ByteShift * 8, MVT::i8));
7708 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7712 // PSLLDQ : (little-endian) left byte shift
7713 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7714 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7715 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7716 bool ZeroableLeft = true;
7717 for (int i = 0; i < Shift; i++) {
7718 ZeroableLeft &= Zeroable[i];
7722 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7723 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7725 if (ValidShiftLeft1 || ValidShiftLeft2) {
7726 // Cast the inputs to v2i64 to match PSLLDQ.
7727 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7728 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7729 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7730 DAG.getConstant(ByteShift * 8, MVT::i8));
7731 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7739 /// \brief Lower a vector shuffle as a zero or any extension.
7741 /// Given a specific number of elements, element bit width, and extension
7742 /// stride, produce either a zero or any extension based on the available
7743 /// features of the subtarget.
7744 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7745 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7746 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7747 assert(Scale > 1 && "Need a scale to extend.");
7748 int EltBits = VT.getSizeInBits() / NumElements;
7749 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7750 "Only 8, 16, and 32 bit elements can be extended.");
7751 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7753 // Found a valid zext mask! Try various lowering strategies based on the
7754 // input type and available ISA extensions.
7755 if (Subtarget->hasSSE41()) {
7756 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7757 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7758 NumElements / Scale);
7759 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7760 return DAG.getNode(ISD::BITCAST, DL, VT,
7761 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7764 // For any extends we can cheat for larger element sizes and use shuffle
7765 // instructions that can fold with a load and/or copy.
7766 if (AnyExt && EltBits == 32) {
7767 int PSHUFDMask[4] = {0, -1, 1, -1};
7769 ISD::BITCAST, DL, VT,
7770 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7771 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7772 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7774 if (AnyExt && EltBits == 16 && Scale > 2) {
7775 int PSHUFDMask[4] = {0, -1, 0, -1};
7776 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7777 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7778 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7779 int PSHUFHWMask[4] = {1, -1, -1, -1};
7781 ISD::BITCAST, DL, VT,
7782 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7783 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7784 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7787 // If this would require more than 2 unpack instructions to expand, use
7788 // pshufb when available. We can only use more than 2 unpack instructions
7789 // when zero extending i8 elements which also makes it easier to use pshufb.
7790 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7791 assert(NumElements == 16 && "Unexpected byte vector width!");
7792 SDValue PSHUFBMask[16];
7793 for (int i = 0; i < 16; ++i)
7795 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7796 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7797 return DAG.getNode(ISD::BITCAST, DL, VT,
7798 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7799 DAG.getNode(ISD::BUILD_VECTOR, DL,
7800 MVT::v16i8, PSHUFBMask)));
7803 // Otherwise emit a sequence of unpacks.
7805 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7806 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7807 : getZeroVector(InputVT, Subtarget, DAG, DL);
7808 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7809 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7813 } while (Scale > 1);
7814 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7817 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7819 /// This routine will try to do everything in its power to cleverly lower
7820 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7821 /// check for the profitability of this lowering, it tries to aggressively
7822 /// match this pattern. It will use all of the micro-architectural details it
7823 /// can to emit an efficient lowering. It handles both blends with all-zero
7824 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7825 /// masking out later).
7827 /// The reason we have dedicated lowering for zext-style shuffles is that they
7828 /// are both incredibly common and often quite performance sensitive.
7829 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7830 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7831 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7832 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7834 int Bits = VT.getSizeInBits();
7835 int NumElements = Mask.size();
7837 // Define a helper function to check a particular ext-scale and lower to it if
7839 auto Lower = [&](int Scale) -> SDValue {
7842 for (int i = 0; i < NumElements; ++i) {
7844 continue; // Valid anywhere but doesn't tell us anything.
7845 if (i % Scale != 0) {
7846 // Each of the extend elements needs to be zeroable.
7850 // We no lorger are in the anyext case.
7855 // Each of the base elements needs to be consecutive indices into the
7856 // same input vector.
7857 SDValue V = Mask[i] < NumElements ? V1 : V2;
7860 else if (InputV != V)
7861 return SDValue(); // Flip-flopping inputs.
7863 if (Mask[i] % NumElements != i / Scale)
7864 return SDValue(); // Non-consecutive strided elemenst.
7867 // If we fail to find an input, we have a zero-shuffle which should always
7868 // have already been handled.
7869 // FIXME: Maybe handle this here in case during blending we end up with one?
7873 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7874 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7877 // The widest scale possible for extending is to a 64-bit integer.
7878 assert(Bits % 64 == 0 &&
7879 "The number of bits in a vector must be divisible by 64 on x86!");
7880 int NumExtElements = Bits / 64;
7882 // Each iteration, try extending the elements half as much, but into twice as
7884 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7885 assert(NumElements % NumExtElements == 0 &&
7886 "The input vector size must be divisble by the extended size.");
7887 if (SDValue V = Lower(NumElements / NumExtElements))
7891 // No viable ext lowering found.
7895 /// \brief Try to get a scalar value for a specific element of a vector.
7897 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7898 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7899 SelectionDAG &DAG) {
7900 MVT VT = V.getSimpleValueType();
7901 MVT EltVT = VT.getVectorElementType();
7902 while (V.getOpcode() == ISD::BITCAST)
7903 V = V.getOperand(0);
7904 // If the bitcasts shift the element size, we can't extract an equivalent
7906 MVT NewVT = V.getSimpleValueType();
7907 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7910 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7911 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7912 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7917 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7919 /// This is particularly important because the set of instructions varies
7920 /// significantly based on whether the operand is a load or not.
7921 static bool isShuffleFoldableLoad(SDValue V) {
7922 while (V.getOpcode() == ISD::BITCAST)
7923 V = V.getOperand(0);
7925 return ISD::isNON_EXTLoad(V.getNode());
7928 /// \brief Try to lower insertion of a single element into a zero vector.
7930 /// This is a common pattern that we have especially efficient patterns to lower
7931 /// across all subtarget feature sets.
7932 static SDValue lowerVectorShuffleAsElementInsertion(
7933 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7934 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7935 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7937 MVT EltVT = VT.getVectorElementType();
7939 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7940 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7942 bool IsV1Zeroable = true;
7943 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7944 if (i != V2Index && !Zeroable[i]) {
7945 IsV1Zeroable = false;
7949 // Check for a single input from a SCALAR_TO_VECTOR node.
7950 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7951 // all the smarts here sunk into that routine. However, the current
7952 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7953 // vector shuffle lowering is dead.
7954 if (SDValue V2S = getScalarValueForVectorElement(
7955 V2, Mask[V2Index] - Mask.size(), DAG)) {
7956 // We need to zext the scalar if it is smaller than an i32.
7957 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7958 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7959 // Using zext to expand a narrow element won't work for non-zero
7964 // Zero-extend directly to i32.
7966 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7968 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7969 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7970 EltVT == MVT::i16) {
7971 // Either not inserting from the low element of the input or the input
7972 // element size is too small to use VZEXT_MOVL to clear the high bits.
7976 if (!IsV1Zeroable) {
7977 // If V1 can't be treated as a zero vector we have fewer options to lower
7978 // this. We can't support integer vectors or non-zero targets cheaply, and
7979 // the V1 elements can't be permuted in any way.
7980 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7981 if (!VT.isFloatingPoint() || V2Index != 0)
7983 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7984 V1Mask[V2Index] = -1;
7985 if (!isNoopShuffleMask(V1Mask))
7987 // This is essentially a special case blend operation, but if we have
7988 // general purpose blend operations, they are always faster. Bail and let
7989 // the rest of the lowering handle these as blends.
7990 if (Subtarget->hasSSE41())
7993 // Otherwise, use MOVSD or MOVSS.
7994 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7995 "Only two types of floating point element types to handle!");
7996 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8000 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8002 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8005 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8006 // the desired position. Otherwise it is more efficient to do a vector
8007 // shift left. We know that we can do a vector shift left because all
8008 // the inputs are zero.
8009 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8010 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8011 V2Shuffle[V2Index] = 0;
8012 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8014 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8016 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8018 V2Index * EltVT.getSizeInBits(),
8019 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8020 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8026 /// \brief Try to lower broadcast of a single element.
8028 /// For convenience, this code also bundles all of the subtarget feature set
8029 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8030 /// a convenient way to factor it out.
8031 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8033 const X86Subtarget *Subtarget,
8034 SelectionDAG &DAG) {
8035 if (!Subtarget->hasAVX())
8037 if (VT.isInteger() && !Subtarget->hasAVX2())
8040 // Check that the mask is a broadcast.
8041 int BroadcastIdx = -1;
8043 if (M >= 0 && BroadcastIdx == -1)
8045 else if (M >= 0 && M != BroadcastIdx)
8048 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8049 "a sorted mask where the broadcast "
8052 // Go up the chain of (vector) values to try and find a scalar load that
8053 // we can combine with the broadcast.
8055 switch (V.getOpcode()) {
8056 case ISD::CONCAT_VECTORS: {
8057 int OperandSize = Mask.size() / V.getNumOperands();
8058 V = V.getOperand(BroadcastIdx / OperandSize);
8059 BroadcastIdx %= OperandSize;
8063 case ISD::INSERT_SUBVECTOR: {
8064 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8065 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8069 int BeginIdx = (int)ConstantIdx->getZExtValue();
8071 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8072 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8073 BroadcastIdx -= BeginIdx;
8084 // Check if this is a broadcast of a scalar. We special case lowering
8085 // for scalars so that we can more effectively fold with loads.
8086 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8087 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8088 V = V.getOperand(BroadcastIdx);
8090 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8092 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8094 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8095 // We can't broadcast from a vector register w/o AVX2, and we can only
8096 // broadcast from the zero-element of a vector register.
8100 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8103 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8105 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8106 /// support for floating point shuffles but not integer shuffles. These
8107 /// instructions will incur a domain crossing penalty on some chips though so
8108 /// it is better to avoid lowering through this for integer vectors where
8110 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8111 const X86Subtarget *Subtarget,
8112 SelectionDAG &DAG) {
8114 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8115 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8116 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8117 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8118 ArrayRef<int> Mask = SVOp->getMask();
8119 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8121 if (isSingleInputShuffleMask(Mask)) {
8122 // Straight shuffle of a single input vector. Simulate this by using the
8123 // single input as both of the "inputs" to this instruction..
8124 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8126 if (Subtarget->hasAVX()) {
8127 // If we have AVX, we can use VPERMILPS which will allow folding a load
8128 // into the shuffle.
8129 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8130 DAG.getConstant(SHUFPDMask, MVT::i8));
8133 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8134 DAG.getConstant(SHUFPDMask, MVT::i8));
8136 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8137 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8139 // Use dedicated unpack instructions for masks that match their pattern.
8140 if (isShuffleEquivalent(Mask, 0, 2))
8141 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8142 if (isShuffleEquivalent(Mask, 1, 3))
8143 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8145 // If we have a single input, insert that into V1 if we can do so cheaply.
8146 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8147 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8148 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8150 // Try inverting the insertion since for v2 masks it is easy to do and we
8151 // can't reliably sort the mask one way or the other.
8152 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8153 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8154 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8155 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8159 // Try to use one of the special instruction patterns to handle two common
8160 // blend patterns if a zero-blend above didn't work.
8161 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8162 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8163 // We can either use a special instruction to load over the low double or
8164 // to move just the low double.
8166 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8168 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8170 if (Subtarget->hasSSE41())
8171 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8175 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8176 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8177 DAG.getConstant(SHUFPDMask, MVT::i8));
8180 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8182 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8183 /// the integer unit to minimize domain crossing penalties. However, for blends
8184 /// it falls back to the floating point shuffle operation with appropriate bit
8186 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8187 const X86Subtarget *Subtarget,
8188 SelectionDAG &DAG) {
8190 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8191 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8192 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8193 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8194 ArrayRef<int> Mask = SVOp->getMask();
8195 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8197 if (isSingleInputShuffleMask(Mask)) {
8198 // Check for being able to broadcast a single element.
8199 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8200 Mask, Subtarget, DAG))
8203 // Straight shuffle of a single input vector. For everything from SSE2
8204 // onward this has a single fast instruction with no scary immediates.
8205 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8206 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8207 int WidenedMask[4] = {
8208 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8209 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8211 ISD::BITCAST, DL, MVT::v2i64,
8212 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8213 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8216 // Try to use byte shift instructions.
8217 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8218 DL, MVT::v2i64, V1, V2, Mask, DAG))
8221 // If we have a single input from V2 insert that into V1 if we can do so
8223 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8224 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8225 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8227 // Try inverting the insertion since for v2 masks it is easy to do and we
8228 // can't reliably sort the mask one way or the other.
8229 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8230 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8231 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8232 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8236 // Use dedicated unpack instructions for masks that match their pattern.
8237 if (isShuffleEquivalent(Mask, 0, 2))
8238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8239 if (isShuffleEquivalent(Mask, 1, 3))
8240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8242 if (Subtarget->hasSSE41())
8243 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8247 // Try to use byte rotation instructions.
8248 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8249 if (Subtarget->hasSSSE3())
8250 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8251 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8254 // We implement this with SHUFPD which is pretty lame because it will likely
8255 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8256 // However, all the alternatives are still more cycles and newer chips don't
8257 // have this problem. It would be really nice if x86 had better shuffles here.
8258 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8259 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8260 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8261 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8264 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8266 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8267 /// It makes no assumptions about whether this is the *best* lowering, it simply
8269 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8270 ArrayRef<int> Mask, SDValue V1,
8271 SDValue V2, SelectionDAG &DAG) {
8272 SDValue LowV = V1, HighV = V2;
8273 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8276 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8278 if (NumV2Elements == 1) {
8280 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8283 // Compute the index adjacent to V2Index and in the same half by toggling
8285 int V2AdjIndex = V2Index ^ 1;
8287 if (Mask[V2AdjIndex] == -1) {
8288 // Handles all the cases where we have a single V2 element and an undef.
8289 // This will only ever happen in the high lanes because we commute the
8290 // vector otherwise.
8292 std::swap(LowV, HighV);
8293 NewMask[V2Index] -= 4;
8295 // Handle the case where the V2 element ends up adjacent to a V1 element.
8296 // To make this work, blend them together as the first step.
8297 int V1Index = V2AdjIndex;
8298 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8299 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8300 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8302 // Now proceed to reconstruct the final blend as we have the necessary
8303 // high or low half formed.
8310 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8311 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8313 } else if (NumV2Elements == 2) {
8314 if (Mask[0] < 4 && Mask[1] < 4) {
8315 // Handle the easy case where we have V1 in the low lanes and V2 in the
8319 } else if (Mask[2] < 4 && Mask[3] < 4) {
8320 // We also handle the reversed case because this utility may get called
8321 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8322 // arrange things in the right direction.
8328 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8329 // trying to place elements directly, just blend them and set up the final
8330 // shuffle to place them.
8332 // The first two blend mask elements are for V1, the second two are for
8334 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8335 Mask[2] < 4 ? Mask[2] : Mask[3],
8336 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8337 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8338 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8339 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8341 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8344 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8345 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8346 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8347 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8350 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8351 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8354 /// \brief Lower 4-lane 32-bit floating point shuffles.
8356 /// Uses instructions exclusively from the floating point unit to minimize
8357 /// domain crossing penalties, as these are sufficient to implement all v4f32
8359 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8360 const X86Subtarget *Subtarget,
8361 SelectionDAG &DAG) {
8363 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8364 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8365 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8367 ArrayRef<int> Mask = SVOp->getMask();
8368 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8371 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8373 if (NumV2Elements == 0) {
8374 // Check for being able to broadcast a single element.
8375 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8376 Mask, Subtarget, DAG))
8379 if (Subtarget->hasAVX()) {
8380 // If we have AVX, we can use VPERMILPS which will allow folding a load
8381 // into the shuffle.
8382 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8383 getV4X86ShuffleImm8ForMask(Mask, DAG));
8386 // Otherwise, use a straight shuffle of a single input vector. We pass the
8387 // input vector to both operands to simulate this with a SHUFPS.
8388 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8389 getV4X86ShuffleImm8ForMask(Mask, DAG));
8392 // Use dedicated unpack instructions for masks that match their pattern.
8393 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8394 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8395 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8396 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8398 // There are special ways we can lower some single-element blends. However, we
8399 // have custom ways we can lower more complex single-element blends below that
8400 // we defer to if both this and BLENDPS fail to match, so restrict this to
8401 // when the V2 input is targeting element 0 of the mask -- that is the fast
8403 if (NumV2Elements == 1 && Mask[0] >= 4)
8404 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8405 Mask, Subtarget, DAG))
8408 if (Subtarget->hasSSE41())
8409 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8413 // Check for whether we can use INSERTPS to perform the blend. We only use
8414 // INSERTPS when the V1 elements are already in the correct locations
8415 // because otherwise we can just always use two SHUFPS instructions which
8416 // are much smaller to encode than a SHUFPS and an INSERTPS.
8417 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8419 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8422 // When using INSERTPS we can zero any lane of the destination. Collect
8423 // the zero inputs into a mask and drop them from the lanes of V1 which
8424 // actually need to be present as inputs to the INSERTPS.
8425 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8427 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8428 bool InsertNeedsShuffle = false;
8430 for (int i = 0; i < 4; ++i)
8434 } else if (Mask[i] != i) {
8435 InsertNeedsShuffle = true;
8440 // We don't want to use INSERTPS or other insertion techniques if it will
8441 // require shuffling anyways.
8442 if (!InsertNeedsShuffle) {
8443 // If all of V1 is zeroable, replace it with undef.
8444 if ((ZMask | 1 << V2Index) == 0xF)
8445 V1 = DAG.getUNDEF(MVT::v4f32);
8447 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8448 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8450 // Insert the V2 element into the desired position.
8451 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8452 DAG.getConstant(InsertPSMask, MVT::i8));
8456 // Otherwise fall back to a SHUFPS lowering strategy.
8457 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8460 /// \brief Lower 4-lane i32 vector shuffles.
8462 /// We try to handle these with integer-domain shuffles where we can, but for
8463 /// blends we use the floating point domain blend instructions.
8464 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8465 const X86Subtarget *Subtarget,
8466 SelectionDAG &DAG) {
8468 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8469 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8470 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8472 ArrayRef<int> Mask = SVOp->getMask();
8473 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8475 // Whenever we can lower this as a zext, that instruction is strictly faster
8476 // than any alternative. It also allows us to fold memory operands into the
8477 // shuffle in many cases.
8478 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8479 Mask, Subtarget, DAG))
8483 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8485 if (NumV2Elements == 0) {
8486 // Check for being able to broadcast a single element.
8487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8488 Mask, Subtarget, DAG))
8491 // Straight shuffle of a single input vector. For everything from SSE2
8492 // onward this has a single fast instruction with no scary immediates.
8493 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8494 // but we aren't actually going to use the UNPCK instruction because doing
8495 // so prevents folding a load into this instruction or making a copy.
8496 const int UnpackLoMask[] = {0, 0, 1, 1};
8497 const int UnpackHiMask[] = {2, 2, 3, 3};
8498 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8499 Mask = UnpackLoMask;
8500 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8501 Mask = UnpackHiMask;
8503 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8504 getV4X86ShuffleImm8ForMask(Mask, DAG));
8507 // Try to use byte shift instructions.
8508 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8509 DL, MVT::v4i32, V1, V2, Mask, DAG))
8512 // There are special ways we can lower some single-element blends.
8513 if (NumV2Elements == 1)
8514 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8515 Mask, Subtarget, DAG))
8518 // Use dedicated unpack instructions for masks that match their pattern.
8519 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8520 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8521 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8522 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8524 if (Subtarget->hasSSE41())
8525 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8529 // Try to use byte rotation instructions.
8530 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8531 if (Subtarget->hasSSSE3())
8532 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8533 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8536 // We implement this with SHUFPS because it can blend from two vectors.
8537 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8538 // up the inputs, bypassing domain shift penalties that we would encur if we
8539 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8541 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8542 DAG.getVectorShuffle(
8544 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8545 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8548 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8549 /// shuffle lowering, and the most complex part.
8551 /// The lowering strategy is to try to form pairs of input lanes which are
8552 /// targeted at the same half of the final vector, and then use a dword shuffle
8553 /// to place them onto the right half, and finally unpack the paired lanes into
8554 /// their final position.
8556 /// The exact breakdown of how to form these dword pairs and align them on the
8557 /// correct sides is really tricky. See the comments within the function for
8558 /// more of the details.
8559 static SDValue lowerV8I16SingleInputVectorShuffle(
8560 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8561 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8562 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8563 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8564 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8566 SmallVector<int, 4> LoInputs;
8567 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8568 [](int M) { return M >= 0; });
8569 std::sort(LoInputs.begin(), LoInputs.end());
8570 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8571 SmallVector<int, 4> HiInputs;
8572 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8573 [](int M) { return M >= 0; });
8574 std::sort(HiInputs.begin(), HiInputs.end());
8575 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8577 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8578 int NumHToL = LoInputs.size() - NumLToL;
8580 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8581 int NumHToH = HiInputs.size() - NumLToH;
8582 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8583 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8584 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8585 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8587 // Check for being able to broadcast a single element.
8588 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8589 Mask, Subtarget, DAG))
8592 // Try to use byte shift instructions.
8593 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8594 DL, MVT::v8i16, V, V, Mask, DAG))
8597 // Use dedicated unpack instructions for masks that match their pattern.
8598 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8599 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8600 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8601 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8603 // Try to use byte rotation instructions.
8604 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8605 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8608 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8609 // such inputs we can swap two of the dwords across the half mark and end up
8610 // with <=2 inputs to each half in each half. Once there, we can fall through
8611 // to the generic code below. For example:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8616 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8617 // and an existing 2-into-2 on the other half. In this case we may have to
8618 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8619 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8620 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8621 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8622 // half than the one we target for fixing) will be fixed when we re-enter this
8623 // path. We will also combine away any sequence of PSHUFD instructions that
8624 // result into a single instruction. Here is an example of the tricky case:
8626 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8627 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8629 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8631 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8632 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8634 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8635 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8637 // The result is fine to be handled by the generic logic.
8638 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8639 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8640 int AOffset, int BOffset) {
8641 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8642 "Must call this with A having 3 or 1 inputs from the A half.");
8643 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8644 "Must call this with B having 1 or 3 inputs from the B half.");
8645 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8646 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8648 // Compute the index of dword with only one word among the three inputs in
8649 // a half by taking the sum of the half with three inputs and subtracting
8650 // the sum of the actual three inputs. The difference is the remaining
8653 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8654 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8655 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8656 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8657 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8658 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8659 int TripleNonInputIdx =
8660 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8661 TripleDWord = TripleNonInputIdx / 2;
8663 // We use xor with one to compute the adjacent DWord to whichever one the
8665 OneInputDWord = (OneInput / 2) ^ 1;
8667 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8668 // and BToA inputs. If there is also such a problem with the BToB and AToB
8669 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8670 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8671 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8672 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8673 // Compute how many inputs will be flipped by swapping these DWords. We
8675 // to balance this to ensure we don't form a 3-1 shuffle in the other
8677 int NumFlippedAToBInputs =
8678 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8679 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8680 int NumFlippedBToBInputs =
8681 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8682 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8683 if ((NumFlippedAToBInputs == 1 &&
8684 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8685 (NumFlippedBToBInputs == 1 &&
8686 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8687 // We choose whether to fix the A half or B half based on whether that
8688 // half has zero flipped inputs. At zero, we may not be able to fix it
8689 // with that half. We also bias towards fixing the B half because that
8690 // will more commonly be the high half, and we have to bias one way.
8691 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8692 ArrayRef<int> Inputs) {
8693 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8694 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8695 PinnedIdx ^ 1) != Inputs.end();
8696 // Determine whether the free index is in the flipped dword or the
8697 // unflipped dword based on where the pinned index is. We use this bit
8698 // in an xor to conditionally select the adjacent dword.
8699 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8700 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8701 FixFreeIdx) != Inputs.end();
8702 if (IsFixIdxInput == IsFixFreeIdxInput)
8704 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8705 FixFreeIdx) != Inputs.end();
8706 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8707 "We need to be changing the number of flipped inputs!");
8708 int PSHUFHalfMask[] = {0, 1, 2, 3};
8709 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8710 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8712 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8715 if (M != -1 && M == FixIdx)
8717 else if (M != -1 && M == FixFreeIdx)
8720 if (NumFlippedBToBInputs != 0) {
8722 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8723 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8725 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8727 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8728 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8733 int PSHUFDMask[] = {0, 1, 2, 3};
8734 PSHUFDMask[ADWord] = BDWord;
8735 PSHUFDMask[BDWord] = ADWord;
8736 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8737 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8738 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8739 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8741 // Adjust the mask to match the new locations of A and B.
8743 if (M != -1 && M/2 == ADWord)
8744 M = 2 * BDWord + M % 2;
8745 else if (M != -1 && M/2 == BDWord)
8746 M = 2 * ADWord + M % 2;
8748 // Recurse back into this routine to re-compute state now that this isn't
8749 // a 3 and 1 problem.
8750 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8753 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8754 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8755 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8756 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8758 // At this point there are at most two inputs to the low and high halves from
8759 // each half. That means the inputs can always be grouped into dwords and
8760 // those dwords can then be moved to the correct half with a dword shuffle.
8761 // We use at most one low and one high word shuffle to collect these paired
8762 // inputs into dwords, and finally a dword shuffle to place them.
8763 int PSHUFLMask[4] = {-1, -1, -1, -1};
8764 int PSHUFHMask[4] = {-1, -1, -1, -1};
8765 int PSHUFDMask[4] = {-1, -1, -1, -1};
8767 // First fix the masks for all the inputs that are staying in their
8768 // original halves. This will then dictate the targets of the cross-half
8770 auto fixInPlaceInputs =
8771 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8772 MutableArrayRef<int> SourceHalfMask,
8773 MutableArrayRef<int> HalfMask, int HalfOffset) {
8774 if (InPlaceInputs.empty())
8776 if (InPlaceInputs.size() == 1) {
8777 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8778 InPlaceInputs[0] - HalfOffset;
8779 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8782 if (IncomingInputs.empty()) {
8783 // Just fix all of the in place inputs.
8784 for (int Input : InPlaceInputs) {
8785 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8786 PSHUFDMask[Input / 2] = Input / 2;
8791 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8792 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8793 InPlaceInputs[0] - HalfOffset;
8794 // Put the second input next to the first so that they are packed into
8795 // a dword. We find the adjacent index by toggling the low bit.
8796 int AdjIndex = InPlaceInputs[0] ^ 1;
8797 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8798 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8799 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8801 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8802 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8804 // Now gather the cross-half inputs and place them into a free dword of
8805 // their target half.
8806 // FIXME: This operation could almost certainly be simplified dramatically to
8807 // look more like the 3-1 fixing operation.
8808 auto moveInputsToRightHalf = [&PSHUFDMask](
8809 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8810 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8811 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8813 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8814 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8816 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8818 int LowWord = Word & ~1;
8819 int HighWord = Word | 1;
8820 return isWordClobbered(SourceHalfMask, LowWord) ||
8821 isWordClobbered(SourceHalfMask, HighWord);
8824 if (IncomingInputs.empty())
8827 if (ExistingInputs.empty()) {
8828 // Map any dwords with inputs from them into the right half.
8829 for (int Input : IncomingInputs) {
8830 // If the source half mask maps over the inputs, turn those into
8831 // swaps and use the swapped lane.
8832 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8833 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8834 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8835 Input - SourceOffset;
8836 // We have to swap the uses in our half mask in one sweep.
8837 for (int &M : HalfMask)
8838 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8840 else if (M == Input)
8841 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8843 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8844 Input - SourceOffset &&
8845 "Previous placement doesn't match!");
8847 // Note that this correctly re-maps both when we do a swap and when
8848 // we observe the other side of the swap above. We rely on that to
8849 // avoid swapping the members of the input list directly.
8850 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8853 // Map the input's dword into the correct half.
8854 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8855 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8857 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8859 "Previous placement doesn't match!");
8862 // And just directly shift any other-half mask elements to be same-half
8863 // as we will have mirrored the dword containing the element into the
8864 // same position within that half.
8865 for (int &M : HalfMask)
8866 if (M >= SourceOffset && M < SourceOffset + 4) {
8867 M = M - SourceOffset + DestOffset;
8868 assert(M >= 0 && "This should never wrap below zero!");
8873 // Ensure we have the input in a viable dword of its current half. This
8874 // is particularly tricky because the original position may be clobbered
8875 // by inputs being moved and *staying* in that half.
8876 if (IncomingInputs.size() == 1) {
8877 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8878 int InputFixed = std::find(std::begin(SourceHalfMask),
8879 std::end(SourceHalfMask), -1) -
8880 std::begin(SourceHalfMask) + SourceOffset;
8881 SourceHalfMask[InputFixed - SourceOffset] =
8882 IncomingInputs[0] - SourceOffset;
8883 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8885 IncomingInputs[0] = InputFixed;
8887 } else if (IncomingInputs.size() == 2) {
8888 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8889 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8890 // We have two non-adjacent or clobbered inputs we need to extract from
8891 // the source half. To do this, we need to map them into some adjacent
8892 // dword slot in the source mask.
8893 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8894 IncomingInputs[1] - SourceOffset};
8896 // If there is a free slot in the source half mask adjacent to one of
8897 // the inputs, place the other input in it. We use (Index XOR 1) to
8898 // compute an adjacent index.
8899 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8900 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8901 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8902 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8903 InputsFixed[1] = InputsFixed[0] ^ 1;
8904 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8905 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8906 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8907 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8908 InputsFixed[0] = InputsFixed[1] ^ 1;
8909 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8910 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8911 // The two inputs are in the same DWord but it is clobbered and the
8912 // adjacent DWord isn't used at all. Move both inputs to the free
8914 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8915 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8916 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8917 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8919 // The only way we hit this point is if there is no clobbering
8920 // (because there are no off-half inputs to this half) and there is no
8921 // free slot adjacent to one of the inputs. In this case, we have to
8922 // swap an input with a non-input.
8923 for (int i = 0; i < 4; ++i)
8924 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8925 "We can't handle any clobbers here!");
8926 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8927 "Cannot have adjacent inputs here!");
8929 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8930 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8932 // We also have to update the final source mask in this case because
8933 // it may need to undo the above swap.
8934 for (int &M : FinalSourceHalfMask)
8935 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8936 M = InputsFixed[1] + SourceOffset;
8937 else if (M == InputsFixed[1] + SourceOffset)
8938 M = (InputsFixed[0] ^ 1) + SourceOffset;
8940 InputsFixed[1] = InputsFixed[0] ^ 1;
8943 // Point everything at the fixed inputs.
8944 for (int &M : HalfMask)
8945 if (M == IncomingInputs[0])
8946 M = InputsFixed[0] + SourceOffset;
8947 else if (M == IncomingInputs[1])
8948 M = InputsFixed[1] + SourceOffset;
8950 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8951 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8954 llvm_unreachable("Unhandled input size!");
8957 // Now hoist the DWord down to the right half.
8958 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8959 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8960 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8961 for (int &M : HalfMask)
8962 for (int Input : IncomingInputs)
8964 M = FreeDWord * 2 + Input % 2;
8966 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8967 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8968 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8969 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8971 // Now enact all the shuffles we've computed to move the inputs into their
8973 if (!isNoopShuffleMask(PSHUFLMask))
8974 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8975 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8976 if (!isNoopShuffleMask(PSHUFHMask))
8977 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8978 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8979 if (!isNoopShuffleMask(PSHUFDMask))
8980 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8981 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8982 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8983 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8985 // At this point, each half should contain all its inputs, and we can then
8986 // just shuffle them into their final position.
8987 assert(std::count_if(LoMask.begin(), LoMask.end(),
8988 [](int M) { return M >= 4; }) == 0 &&
8989 "Failed to lift all the high half inputs to the low mask!");
8990 assert(std::count_if(HiMask.begin(), HiMask.end(),
8991 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8992 "Failed to lift all the low half inputs to the high mask!");
8994 // Do a half shuffle for the low mask.
8995 if (!isNoopShuffleMask(LoMask))
8996 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8997 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8999 // Do a half shuffle with the high mask after shifting its values down.
9000 for (int &M : HiMask)
9003 if (!isNoopShuffleMask(HiMask))
9004 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9005 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9010 /// \brief Detect whether the mask pattern should be lowered through
9013 /// This essentially tests whether viewing the mask as an interleaving of two
9014 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9015 /// lowering it through interleaving is a significantly better strategy.
9016 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9017 int NumEvenInputs[2] = {0, 0};
9018 int NumOddInputs[2] = {0, 0};
9019 int NumLoInputs[2] = {0, 0};
9020 int NumHiInputs[2] = {0, 0};
9021 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9025 int InputIdx = Mask[i] >= Size;
9028 ++NumLoInputs[InputIdx];
9030 ++NumHiInputs[InputIdx];
9033 ++NumEvenInputs[InputIdx];
9035 ++NumOddInputs[InputIdx];
9038 // The minimum number of cross-input results for both the interleaved and
9039 // split cases. If interleaving results in fewer cross-input results, return
9041 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9042 NumEvenInputs[0] + NumOddInputs[1]);
9043 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9044 NumLoInputs[0] + NumHiInputs[1]);
9045 return InterleavedCrosses < SplitCrosses;
9048 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9050 /// This strategy only works when the inputs from each vector fit into a single
9051 /// half of that vector, and generally there are not so many inputs as to leave
9052 /// the in-place shuffles required highly constrained (and thus expensive). It
9053 /// shifts all the inputs into a single side of both input vectors and then
9054 /// uses an unpack to interleave these inputs in a single vector. At that
9055 /// point, we will fall back on the generic single input shuffle lowering.
9056 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9058 MutableArrayRef<int> Mask,
9059 const X86Subtarget *Subtarget,
9060 SelectionDAG &DAG) {
9061 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9062 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9063 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9064 for (int i = 0; i < 8; ++i)
9065 if (Mask[i] >= 0 && Mask[i] < 4)
9066 LoV1Inputs.push_back(i);
9067 else if (Mask[i] >= 4 && Mask[i] < 8)
9068 HiV1Inputs.push_back(i);
9069 else if (Mask[i] >= 8 && Mask[i] < 12)
9070 LoV2Inputs.push_back(i);
9071 else if (Mask[i] >= 12)
9072 HiV2Inputs.push_back(i);
9074 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9075 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9078 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9079 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9080 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9082 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9083 HiV1Inputs.size() + HiV2Inputs.size();
9085 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9086 ArrayRef<int> HiInputs, bool MoveToLo,
9088 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9089 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9090 if (BadInputs.empty())
9093 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9094 int MoveOffset = MoveToLo ? 0 : 4;
9096 if (GoodInputs.empty()) {
9097 for (int BadInput : BadInputs) {
9098 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9099 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9102 if (GoodInputs.size() == 2) {
9103 // If the low inputs are spread across two dwords, pack them into
9105 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9106 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9107 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9108 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9110 // Otherwise pin the good inputs.
9111 for (int GoodInput : GoodInputs)
9112 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9115 if (BadInputs.size() == 2) {
9116 // If we have two bad inputs then there may be either one or two good
9117 // inputs fixed in place. Find a fixed input, and then find the *other*
9118 // two adjacent indices by using modular arithmetic.
9120 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9121 [](int M) { return M >= 0; }) -
9122 std::begin(MoveMask);
9124 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9125 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9126 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9127 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9128 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9129 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9130 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9132 assert(BadInputs.size() == 1 && "All sizes handled");
9133 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9134 std::end(MoveMask), -1) -
9135 std::begin(MoveMask);
9136 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9137 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9141 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9144 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9146 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9149 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9150 // cross-half traffic in the final shuffle.
9152 // Munge the mask to be a single-input mask after the unpack merges the
9156 M = 2 * (M % 4) + (M / 8);
9158 return DAG.getVectorShuffle(
9159 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9160 DL, MVT::v8i16, V1, V2),
9161 DAG.getUNDEF(MVT::v8i16), Mask);
9164 /// \brief Generic lowering of 8-lane i16 shuffles.
9166 /// This handles both single-input shuffles and combined shuffle/blends with
9167 /// two inputs. The single input shuffles are immediately delegated to
9168 /// a dedicated lowering routine.
9170 /// The blends are lowered in one of three fundamental ways. If there are few
9171 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9172 /// of the input is significantly cheaper when lowered as an interleaving of
9173 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9174 /// halves of the inputs separately (making them have relatively few inputs)
9175 /// and then concatenate them.
9176 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9177 const X86Subtarget *Subtarget,
9178 SelectionDAG &DAG) {
9180 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9181 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9182 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9184 ArrayRef<int> OrigMask = SVOp->getMask();
9185 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9186 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9187 MutableArrayRef<int> Mask(MaskStorage);
9189 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9191 // Whenever we can lower this as a zext, that instruction is strictly faster
9192 // than any alternative.
9193 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9194 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9197 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9198 auto isV2 = [](int M) { return M >= 8; };
9200 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9201 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9203 if (NumV2Inputs == 0)
9204 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9206 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9207 "to be V1-input shuffles.");
9209 // Try to use byte shift instructions.
9210 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9211 DL, MVT::v8i16, V1, V2, Mask, DAG))
9214 // There are special ways we can lower some single-element blends.
9215 if (NumV2Inputs == 1)
9216 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9217 Mask, Subtarget, DAG))
9220 // Use dedicated unpack instructions for masks that match their pattern.
9221 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9222 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9223 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9224 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9226 if (Subtarget->hasSSE41())
9227 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9231 // Try to use byte rotation instructions.
9232 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9233 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9236 if (NumV1Inputs + NumV2Inputs <= 4)
9237 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9239 // Check whether an interleaving lowering is likely to be more efficient.
9240 // This isn't perfect but it is a strong heuristic that tends to work well on
9241 // the kinds of shuffles that show up in practice.
9243 // FIXME: Handle 1x, 2x, and 4x interleaving.
9244 if (shouldLowerAsInterleaving(Mask)) {
9245 // FIXME: Figure out whether we should pack these into the low or high
9248 int EMask[8], OMask[8];
9249 for (int i = 0; i < 4; ++i) {
9250 EMask[i] = Mask[2*i];
9251 OMask[i] = Mask[2*i + 1];
9256 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9257 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9259 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9262 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9263 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9265 for (int i = 0; i < 4; ++i) {
9266 LoBlendMask[i] = Mask[i];
9267 HiBlendMask[i] = Mask[i + 4];
9270 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9271 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9272 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9273 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9275 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9276 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9279 /// \brief Check whether a compaction lowering can be done by dropping even
9280 /// elements and compute how many times even elements must be dropped.
9282 /// This handles shuffles which take every Nth element where N is a power of
9283 /// two. Example shuffle masks:
9285 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9286 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9287 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9288 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9289 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9290 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9292 /// Any of these lanes can of course be undef.
9294 /// This routine only supports N <= 3.
9295 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9298 /// \returns N above, or the number of times even elements must be dropped if
9299 /// there is such a number. Otherwise returns zero.
9300 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9301 // Figure out whether we're looping over two inputs or just one.
9302 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9304 // The modulus for the shuffle vector entries is based on whether this is
9305 // a single input or not.
9306 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9307 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9308 "We should only be called with masks with a power-of-2 size!");
9310 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9312 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9313 // and 2^3 simultaneously. This is because we may have ambiguity with
9314 // partially undef inputs.
9315 bool ViableForN[3] = {true, true, true};
9317 for (int i = 0, e = Mask.size(); i < e; ++i) {
9318 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9323 bool IsAnyViable = false;
9324 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9325 if (ViableForN[j]) {
9328 // The shuffle mask must be equal to (i * 2^N) % M.
9329 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9332 ViableForN[j] = false;
9334 // Early exit if we exhaust the possible powers of two.
9339 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9343 // Return 0 as there is no viable power of two.
9347 /// \brief Generic lowering of v16i8 shuffles.
9349 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9350 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9351 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9352 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9354 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9355 const X86Subtarget *Subtarget,
9356 SelectionDAG &DAG) {
9358 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9359 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9360 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9361 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9362 ArrayRef<int> OrigMask = SVOp->getMask();
9363 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9365 // Try to use byte shift instructions.
9366 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9367 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9370 // Try to use byte rotation instructions.
9371 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9372 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9375 // Try to use a zext lowering.
9376 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9377 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9380 int MaskStorage[16] = {
9381 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9382 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9383 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9384 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9385 MutableArrayRef<int> Mask(MaskStorage);
9386 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9387 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9390 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9392 // For single-input shuffles, there are some nicer lowering tricks we can use.
9393 if (NumV2Elements == 0) {
9394 // Check for being able to broadcast a single element.
9395 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9396 Mask, Subtarget, DAG))
9399 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9400 // Notably, this handles splat and partial-splat shuffles more efficiently.
9401 // However, it only makes sense if the pre-duplication shuffle simplifies
9402 // things significantly. Currently, this means we need to be able to
9403 // express the pre-duplication shuffle as an i16 shuffle.
9405 // FIXME: We should check for other patterns which can be widened into an
9406 // i16 shuffle as well.
9407 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9408 for (int i = 0; i < 16; i += 2)
9409 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9414 auto tryToWidenViaDuplication = [&]() -> SDValue {
9415 if (!canWidenViaDuplication(Mask))
9417 SmallVector<int, 4> LoInputs;
9418 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9419 [](int M) { return M >= 0 && M < 8; });
9420 std::sort(LoInputs.begin(), LoInputs.end());
9421 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9423 SmallVector<int, 4> HiInputs;
9424 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9425 [](int M) { return M >= 8; });
9426 std::sort(HiInputs.begin(), HiInputs.end());
9427 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9430 bool TargetLo = LoInputs.size() >= HiInputs.size();
9431 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9432 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9434 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9435 SmallDenseMap<int, int, 8> LaneMap;
9436 for (int I : InPlaceInputs) {
9437 PreDupI16Shuffle[I/2] = I/2;
9440 int j = TargetLo ? 0 : 4, je = j + 4;
9441 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9442 // Check if j is already a shuffle of this input. This happens when
9443 // there are two adjacent bytes after we move the low one.
9444 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9445 // If we haven't yet mapped the input, search for a slot into which
9447 while (j < je && PreDupI16Shuffle[j] != -1)
9451 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9454 // Map this input with the i16 shuffle.
9455 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9458 // Update the lane map based on the mapping we ended up with.
9459 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9462 ISD::BITCAST, DL, MVT::v16i8,
9463 DAG.getVectorShuffle(MVT::v8i16, DL,
9464 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9465 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9467 // Unpack the bytes to form the i16s that will be shuffled into place.
9468 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9469 MVT::v16i8, V1, V1);
9471 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9472 for (int i = 0; i < 16; ++i)
9473 if (Mask[i] != -1) {
9474 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9475 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9476 if (PostDupI16Shuffle[i / 2] == -1)
9477 PostDupI16Shuffle[i / 2] = MappedMask;
9479 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9480 "Conflicting entrties in the original shuffle!");
9483 ISD::BITCAST, DL, MVT::v16i8,
9484 DAG.getVectorShuffle(MVT::v8i16, DL,
9485 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9486 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9488 if (SDValue V = tryToWidenViaDuplication())
9492 // Check whether an interleaving lowering is likely to be more efficient.
9493 // This isn't perfect but it is a strong heuristic that tends to work well on
9494 // the kinds of shuffles that show up in practice.
9496 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9497 if (shouldLowerAsInterleaving(Mask)) {
9498 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9499 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9501 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9502 return (M >= 8 && M < 16) || M >= 24;
9504 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9505 -1, -1, -1, -1, -1, -1, -1, -1};
9506 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9507 -1, -1, -1, -1, -1, -1, -1, -1};
9508 bool UnpackLo = NumLoHalf >= NumHiHalf;
9509 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9510 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9511 for (int i = 0; i < 8; ++i) {
9512 TargetEMask[i] = Mask[2 * i];
9513 TargetOMask[i] = Mask[2 * i + 1];
9516 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9517 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9519 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9520 MVT::v16i8, Evens, Odds);
9523 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9524 // with PSHUFB. It is important to do this before we attempt to generate any
9525 // blends but after all of the single-input lowerings. If the single input
9526 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9527 // want to preserve that and we can DAG combine any longer sequences into
9528 // a PSHUFB in the end. But once we start blending from multiple inputs,
9529 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9530 // and there are *very* few patterns that would actually be faster than the
9531 // PSHUFB approach because of its ability to zero lanes.
9533 // FIXME: The only exceptions to the above are blends which are exact
9534 // interleavings with direct instructions supporting them. We currently don't
9535 // handle those well here.
9536 if (Subtarget->hasSSSE3()) {
9539 for (int i = 0; i < 16; ++i)
9540 if (Mask[i] == -1) {
9541 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9543 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9545 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9547 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9548 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9549 if (isSingleInputShuffleMask(Mask))
9550 return V1; // Single inputs are easy.
9552 // Otherwise, blend the two.
9553 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9554 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9555 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9558 // There are special ways we can lower some single-element blends.
9559 if (NumV2Elements == 1)
9560 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9561 Mask, Subtarget, DAG))
9564 // Check whether a compaction lowering can be done. This handles shuffles
9565 // which take every Nth element for some even N. See the helper function for
9568 // We special case these as they can be particularly efficiently handled with
9569 // the PACKUSB instruction on x86 and they show up in common patterns of
9570 // rearranging bytes to truncate wide elements.
9571 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9572 // NumEvenDrops is the power of two stride of the elements. Another way of
9573 // thinking about it is that we need to drop the even elements this many
9574 // times to get the original input.
9575 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9577 // First we need to zero all the dropped bytes.
9578 assert(NumEvenDrops <= 3 &&
9579 "No support for dropping even elements more than 3 times.");
9580 // We use the mask type to pick which bytes are preserved based on how many
9581 // elements are dropped.
9582 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9583 SDValue ByteClearMask =
9584 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9585 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9586 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9588 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9590 // Now pack things back together.
9591 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9592 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9593 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9594 for (int i = 1; i < NumEvenDrops; ++i) {
9595 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9596 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9602 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9603 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9604 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9605 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9607 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9608 MutableArrayRef<int> V1HalfBlendMask,
9609 MutableArrayRef<int> V2HalfBlendMask) {
9610 for (int i = 0; i < 8; ++i)
9611 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9612 V1HalfBlendMask[i] = HalfMask[i];
9614 } else if (HalfMask[i] >= 16) {
9615 V2HalfBlendMask[i] = HalfMask[i] - 16;
9616 HalfMask[i] = i + 8;
9619 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9620 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9622 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9624 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9625 MutableArrayRef<int> HiBlendMask) {
9627 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9628 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9630 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9631 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9632 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9633 [](int M) { return M >= 0 && M % 2 == 1; })) {
9634 // Use a mask to drop the high bytes.
9635 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9636 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9637 DAG.getConstant(0x00FF, MVT::v8i16));
9639 // This will be a single vector shuffle instead of a blend so nuke V2.
9640 V2 = DAG.getUNDEF(MVT::v8i16);
9642 // Squash the masks to point directly into V1.
9643 for (int &M : LoBlendMask)
9646 for (int &M : HiBlendMask)
9650 // Otherwise just unpack the low half of V into V1 and the high half into
9651 // V2 so that we can blend them as i16s.
9652 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9653 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9654 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9655 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9658 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9659 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9660 return std::make_pair(BlendedLo, BlendedHi);
9662 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9663 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9664 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9666 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9667 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9669 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9672 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9674 /// This routine breaks down the specific type of 128-bit shuffle and
9675 /// dispatches to the lowering routines accordingly.
9676 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9677 MVT VT, const X86Subtarget *Subtarget,
9678 SelectionDAG &DAG) {
9679 switch (VT.SimpleTy) {
9681 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9683 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9685 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9691 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9694 llvm_unreachable("Unimplemented!");
9698 /// \brief Helper function to test whether a shuffle mask could be
9699 /// simplified by widening the elements being shuffled.
9701 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9702 /// leaves it in an unspecified state.
9704 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9705 /// shuffle masks. The latter have the special property of a '-2' representing
9706 /// a zero-ed lane of a vector.
9707 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9708 SmallVectorImpl<int> &WidenedMask) {
9709 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9710 // If both elements are undef, its trivial.
9711 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9712 WidenedMask.push_back(SM_SentinelUndef);
9716 // Check for an undef mask and a mask value properly aligned to fit with
9717 // a pair of values. If we find such a case, use the non-undef mask's value.
9718 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9719 WidenedMask.push_back(Mask[i + 1] / 2);
9722 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9723 WidenedMask.push_back(Mask[i] / 2);
9727 // When zeroing, we need to spread the zeroing across both lanes to widen.
9728 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9729 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9730 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9731 WidenedMask.push_back(SM_SentinelZero);
9737 // Finally check if the two mask values are adjacent and aligned with
9739 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9740 WidenedMask.push_back(Mask[i] / 2);
9744 // Otherwise we can't safely widen the elements used in this shuffle.
9747 assert(WidenedMask.size() == Mask.size() / 2 &&
9748 "Incorrect size of mask after widening the elements!");
9753 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9755 /// This routine just extracts two subvectors, shuffles them independently, and
9756 /// then concatenates them back together. This should work effectively with all
9757 /// AVX vector shuffle types.
9758 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9759 SDValue V2, ArrayRef<int> Mask,
9760 SelectionDAG &DAG) {
9761 assert(VT.getSizeInBits() >= 256 &&
9762 "Only for 256-bit or wider vector shuffles!");
9763 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9764 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9766 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9767 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9769 int NumElements = VT.getVectorNumElements();
9770 int SplitNumElements = NumElements / 2;
9771 MVT ScalarVT = VT.getScalarType();
9772 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9774 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9775 DAG.getIntPtrConstant(0));
9776 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9777 DAG.getIntPtrConstant(SplitNumElements));
9778 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9779 DAG.getIntPtrConstant(0));
9780 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9781 DAG.getIntPtrConstant(SplitNumElements));
9783 // Now create two 4-way blends of these half-width vectors.
9784 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9785 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9786 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9787 for (int i = 0; i < SplitNumElements; ++i) {
9788 int M = HalfMask[i];
9789 if (M >= NumElements) {
9790 if (M >= NumElements + SplitNumElements)
9794 V2BlendMask.push_back(M - NumElements);
9795 V1BlendMask.push_back(-1);
9796 BlendMask.push_back(SplitNumElements + i);
9797 } else if (M >= 0) {
9798 if (M >= SplitNumElements)
9802 V2BlendMask.push_back(-1);
9803 V1BlendMask.push_back(M);
9804 BlendMask.push_back(i);
9806 V2BlendMask.push_back(-1);
9807 V1BlendMask.push_back(-1);
9808 BlendMask.push_back(-1);
9812 // Because the lowering happens after all combining takes place, we need to
9813 // manually combine these blend masks as much as possible so that we create
9814 // a minimal number of high-level vector shuffle nodes.
9816 // First try just blending the halves of V1 or V2.
9817 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9818 return DAG.getUNDEF(SplitVT);
9819 if (!UseLoV2 && !UseHiV2)
9820 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9821 if (!UseLoV1 && !UseHiV1)
9822 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9824 SDValue V1Blend, V2Blend;
9825 if (UseLoV1 && UseHiV1) {
9827 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9829 // We only use half of V1 so map the usage down into the final blend mask.
9830 V1Blend = UseLoV1 ? LoV1 : HiV1;
9831 for (int i = 0; i < SplitNumElements; ++i)
9832 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9833 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9835 if (UseLoV2 && UseHiV2) {
9837 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9839 // We only use half of V2 so map the usage down into the final blend mask.
9840 V2Blend = UseLoV2 ? LoV2 : HiV2;
9841 for (int i = 0; i < SplitNumElements; ++i)
9842 if (BlendMask[i] >= SplitNumElements)
9843 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9845 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9847 SDValue Lo = HalfBlend(LoMask);
9848 SDValue Hi = HalfBlend(HiMask);
9849 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9852 /// \brief Either split a vector in halves or decompose the shuffles and the
9855 /// This is provided as a good fallback for many lowerings of non-single-input
9856 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9857 /// between splitting the shuffle into 128-bit components and stitching those
9858 /// back together vs. extracting the single-input shuffles and blending those
9860 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9861 SDValue V2, ArrayRef<int> Mask,
9862 SelectionDAG &DAG) {
9863 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9864 "lower single-input shuffles as it "
9865 "could then recurse on itself.");
9866 int Size = Mask.size();
9868 // If this can be modeled as a broadcast of two elements followed by a blend,
9869 // prefer that lowering. This is especially important because broadcasts can
9870 // often fold with memory operands.
9871 auto DoBothBroadcast = [&] {
9872 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9875 if (V2BroadcastIdx == -1)
9876 V2BroadcastIdx = M - Size;
9877 else if (M - Size != V2BroadcastIdx)
9879 } else if (M >= 0) {
9880 if (V1BroadcastIdx == -1)
9882 else if (M != V1BroadcastIdx)
9887 if (DoBothBroadcast())
9888 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9891 // If the inputs all stem from a single 128-bit lane of each input, then we
9892 // split them rather than blending because the split will decompose to
9893 // unusually few instructions.
9894 int LaneCount = VT.getSizeInBits() / 128;
9895 int LaneSize = Size / LaneCount;
9896 SmallBitVector LaneInputs[2];
9897 LaneInputs[0].resize(LaneCount, false);
9898 LaneInputs[1].resize(LaneCount, false);
9899 for (int i = 0; i < Size; ++i)
9901 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9902 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9903 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9905 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9906 // that the decomposed single-input shuffles don't end up here.
9907 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9910 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9911 /// a permutation and blend of those lanes.
9913 /// This essentially blends the out-of-lane inputs to each lane into the lane
9914 /// from a permuted copy of the vector. This lowering strategy results in four
9915 /// instructions in the worst case for a single-input cross lane shuffle which
9916 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9917 /// of. Special cases for each particular shuffle pattern should be handled
9918 /// prior to trying this lowering.
9919 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9920 SDValue V1, SDValue V2,
9922 SelectionDAG &DAG) {
9923 // FIXME: This should probably be generalized for 512-bit vectors as well.
9924 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9925 int LaneSize = Mask.size() / 2;
9927 // If there are only inputs from one 128-bit lane, splitting will in fact be
9928 // less expensive. The flags track wether the given lane contains an element
9929 // that crosses to another lane.
9930 bool LaneCrossing[2] = {false, false};
9931 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9932 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9933 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9934 if (!LaneCrossing[0] || !LaneCrossing[1])
9935 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9937 if (isSingleInputShuffleMask(Mask)) {
9938 SmallVector<int, 32> FlippedBlendMask;
9939 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9940 FlippedBlendMask.push_back(
9941 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9943 : Mask[i] % LaneSize +
9944 (i / LaneSize) * LaneSize + Size));
9946 // Flip the vector, and blend the results which should now be in-lane. The
9947 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9948 // 5 for the high source. The value 3 selects the high half of source 2 and
9949 // the value 2 selects the low half of source 2. We only use source 2 to
9950 // allow folding it into a memory operand.
9951 unsigned PERMMask = 3 | 2 << 4;
9952 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9953 V1, DAG.getConstant(PERMMask, MVT::i8));
9954 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9957 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9958 // will be handled by the above logic and a blend of the results, much like
9959 // other patterns in AVX.
9960 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9963 /// \brief Handle lowering 2-lane 128-bit shuffles.
9964 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9965 SDValue V2, ArrayRef<int> Mask,
9966 const X86Subtarget *Subtarget,
9967 SelectionDAG &DAG) {
9968 // Blends are faster and handle all the non-lane-crossing cases.
9969 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9973 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9974 VT.getVectorNumElements() / 2);
9975 // Check for patterns which can be matched with a single insert of a 128-bit
9977 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9978 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9979 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9980 DAG.getIntPtrConstant(0));
9981 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9982 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9983 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9985 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9986 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9987 DAG.getIntPtrConstant(0));
9988 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9989 DAG.getIntPtrConstant(2));
9990 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9993 // Otherwise form a 128-bit permutation.
9994 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9995 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9996 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9997 DAG.getConstant(PermMask, MVT::i8));
10000 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10001 /// shuffling each lane.
10003 /// This will only succeed when the result of fixing the 128-bit lanes results
10004 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10005 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10006 /// the lane crosses early and then use simpler shuffles within each lane.
10008 /// FIXME: It might be worthwhile at some point to support this without
10009 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10010 /// in x86 only floating point has interesting non-repeating shuffles, and even
10011 /// those are still *marginally* more expensive.
10012 static SDValue lowerVectorShuffleByMerging128BitLanes(
10013 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10014 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10015 assert(!isSingleInputShuffleMask(Mask) &&
10016 "This is only useful with multiple inputs.");
10018 int Size = Mask.size();
10019 int LaneSize = 128 / VT.getScalarSizeInBits();
10020 int NumLanes = Size / LaneSize;
10021 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10023 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10024 // check whether the in-128-bit lane shuffles share a repeating pattern.
10025 SmallVector<int, 4> Lanes;
10026 Lanes.resize(NumLanes, -1);
10027 SmallVector<int, 4> InLaneMask;
10028 InLaneMask.resize(LaneSize, -1);
10029 for (int i = 0; i < Size; ++i) {
10033 int j = i / LaneSize;
10035 if (Lanes[j] < 0) {
10036 // First entry we've seen for this lane.
10037 Lanes[j] = Mask[i] / LaneSize;
10038 } else if (Lanes[j] != Mask[i] / LaneSize) {
10039 // This doesn't match the lane selected previously!
10043 // Check that within each lane we have a consistent shuffle mask.
10044 int k = i % LaneSize;
10045 if (InLaneMask[k] < 0) {
10046 InLaneMask[k] = Mask[i] % LaneSize;
10047 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10048 // This doesn't fit a repeating in-lane mask.
10053 // First shuffle the lanes into place.
10054 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10055 VT.getSizeInBits() / 64);
10056 SmallVector<int, 8> LaneMask;
10057 LaneMask.resize(NumLanes * 2, -1);
10058 for (int i = 0; i < NumLanes; ++i)
10059 if (Lanes[i] >= 0) {
10060 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10061 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10064 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10065 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10066 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10068 // Cast it back to the type we actually want.
10069 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10071 // Now do a simple shuffle that isn't lane crossing.
10072 SmallVector<int, 8> NewMask;
10073 NewMask.resize(Size, -1);
10074 for (int i = 0; i < Size; ++i)
10076 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10077 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10078 "Must not introduce lane crosses at this point!");
10080 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10083 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10086 /// This returns true if the elements from a particular input are already in the
10087 /// slot required by the given mask and require no permutation.
10088 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10089 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10090 int Size = Mask.size();
10091 for (int i = 0; i < Size; ++i)
10092 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10098 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10100 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10101 /// isn't available.
10102 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10103 const X86Subtarget *Subtarget,
10104 SelectionDAG &DAG) {
10106 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10107 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10109 ArrayRef<int> Mask = SVOp->getMask();
10110 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10112 SmallVector<int, 4> WidenedMask;
10113 if (canWidenShuffleElements(Mask, WidenedMask))
10114 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10117 if (isSingleInputShuffleMask(Mask)) {
10118 // Check for being able to broadcast a single element.
10119 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10120 Mask, Subtarget, DAG))
10123 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10124 // Non-half-crossing single input shuffles can be lowerid with an
10125 // interleaved permutation.
10126 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10127 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10128 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10129 DAG.getConstant(VPERMILPMask, MVT::i8));
10132 // With AVX2 we have direct support for this permutation.
10133 if (Subtarget->hasAVX2())
10134 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10135 getV4X86ShuffleImm8ForMask(Mask, DAG));
10137 // Otherwise, fall back.
10138 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10142 // X86 has dedicated unpack instructions that can handle specific blend
10143 // operations: UNPCKH and UNPCKL.
10144 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10145 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10146 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10147 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10149 // If we have a single input to the zero element, insert that into V1 if we
10150 // can do so cheaply.
10151 int NumV2Elements =
10152 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10153 if (NumV2Elements == 1 && Mask[0] >= 4)
10154 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10155 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10162 // Check if the blend happens to exactly fit that of SHUFPD.
10163 if ((Mask[0] == -1 || Mask[0] < 2) &&
10164 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10165 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10166 (Mask[3] == -1 || Mask[3] >= 6)) {
10167 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10168 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10169 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10170 DAG.getConstant(SHUFPDMask, MVT::i8));
10172 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10173 (Mask[1] == -1 || Mask[1] < 2) &&
10174 (Mask[2] == -1 || Mask[2] >= 6) &&
10175 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10176 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10177 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10178 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10179 DAG.getConstant(SHUFPDMask, MVT::i8));
10182 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10183 // shuffle. However, if we have AVX2 and either inputs are already in place,
10184 // we will be able to shuffle even across lanes the other input in a single
10185 // instruction so skip this pattern.
10186 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10187 isShuffleMaskInputInPlace(1, Mask))))
10188 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10189 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10192 // If we have AVX2 then we always want to lower with a blend because an v4 we
10193 // can fully permute the elements.
10194 if (Subtarget->hasAVX2())
10195 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10198 // Otherwise fall back on generic lowering.
10199 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10202 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10204 /// This routine is only called when we have AVX2 and thus a reasonable
10205 /// instruction set for v4i64 shuffling..
10206 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10207 const X86Subtarget *Subtarget,
10208 SelectionDAG &DAG) {
10210 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10211 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10212 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10213 ArrayRef<int> Mask = SVOp->getMask();
10214 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10215 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10217 SmallVector<int, 4> WidenedMask;
10218 if (canWidenShuffleElements(Mask, WidenedMask))
10219 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10222 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10226 // Check for being able to broadcast a single element.
10227 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10228 Mask, Subtarget, DAG))
10231 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10232 // use lower latency instructions that will operate on both 128-bit lanes.
10233 SmallVector<int, 2> RepeatedMask;
10234 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10235 if (isSingleInputShuffleMask(Mask)) {
10236 int PSHUFDMask[] = {-1, -1, -1, -1};
10237 for (int i = 0; i < 2; ++i)
10238 if (RepeatedMask[i] >= 0) {
10239 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10240 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10242 return DAG.getNode(
10243 ISD::BITCAST, DL, MVT::v4i64,
10244 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10245 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10246 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10249 // Use dedicated unpack instructions for masks that match their pattern.
10250 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10251 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10252 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10253 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10256 // AVX2 provides a direct instruction for permuting a single input across
10258 if (isSingleInputShuffleMask(Mask))
10259 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10260 getV4X86ShuffleImm8ForMask(Mask, DAG));
10262 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10263 // shuffle. However, if we have AVX2 and either inputs are already in place,
10264 // we will be able to shuffle even across lanes the other input in a single
10265 // instruction so skip this pattern.
10266 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10267 isShuffleMaskInputInPlace(1, Mask))))
10268 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10269 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10272 // Otherwise fall back on generic blend lowering.
10273 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10277 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10279 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10280 /// isn't available.
10281 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10282 const X86Subtarget *Subtarget,
10283 SelectionDAG &DAG) {
10285 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10286 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10288 ArrayRef<int> Mask = SVOp->getMask();
10289 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10291 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10295 // Check for being able to broadcast a single element.
10296 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10297 Mask, Subtarget, DAG))
10300 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10301 // options to efficiently lower the shuffle.
10302 SmallVector<int, 4> RepeatedMask;
10303 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10304 assert(RepeatedMask.size() == 4 &&
10305 "Repeated masks must be half the mask width!");
10306 if (isSingleInputShuffleMask(Mask))
10307 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10308 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10310 // Use dedicated unpack instructions for masks that match their pattern.
10311 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10312 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10313 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10314 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10316 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10317 // have already handled any direct blends. We also need to squash the
10318 // repeated mask into a simulated v4f32 mask.
10319 for (int i = 0; i < 4; ++i)
10320 if (RepeatedMask[i] >= 8)
10321 RepeatedMask[i] -= 4;
10322 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10325 // If we have a single input shuffle with different shuffle patterns in the
10326 // two 128-bit lanes use the variable mask to VPERMILPS.
10327 if (isSingleInputShuffleMask(Mask)) {
10328 SDValue VPermMask[8];
10329 for (int i = 0; i < 8; ++i)
10330 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10331 : DAG.getConstant(Mask[i], MVT::i32);
10332 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10333 return DAG.getNode(
10334 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10335 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10337 if (Subtarget->hasAVX2())
10338 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10339 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10340 DAG.getNode(ISD::BUILD_VECTOR, DL,
10341 MVT::v8i32, VPermMask)),
10344 // Otherwise, fall back.
10345 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10349 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10351 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10352 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10355 // If we have AVX2 then we always want to lower with a blend because at v8 we
10356 // can fully permute the elements.
10357 if (Subtarget->hasAVX2())
10358 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10361 // Otherwise fall back on generic lowering.
10362 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10365 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10367 /// This routine is only called when we have AVX2 and thus a reasonable
10368 /// instruction set for v8i32 shuffling..
10369 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10370 const X86Subtarget *Subtarget,
10371 SelectionDAG &DAG) {
10373 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10374 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10375 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10376 ArrayRef<int> Mask = SVOp->getMask();
10377 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10378 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10380 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10384 // Check for being able to broadcast a single element.
10385 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10386 Mask, Subtarget, DAG))
10389 // If the shuffle mask is repeated in each 128-bit lane we can use more
10390 // efficient instructions that mirror the shuffles across the two 128-bit
10392 SmallVector<int, 4> RepeatedMask;
10393 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10394 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10395 if (isSingleInputShuffleMask(Mask))
10396 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10397 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10399 // Use dedicated unpack instructions for masks that match their pattern.
10400 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10401 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10402 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10403 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10406 // If the shuffle patterns aren't repeated but it is a single input, directly
10407 // generate a cross-lane VPERMD instruction.
10408 if (isSingleInputShuffleMask(Mask)) {
10409 SDValue VPermMask[8];
10410 for (int i = 0; i < 8; ++i)
10411 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10412 : DAG.getConstant(Mask[i], MVT::i32);
10413 return DAG.getNode(
10414 X86ISD::VPERMV, DL, MVT::v8i32,
10415 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10418 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10420 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10421 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10424 // Otherwise fall back on generic blend lowering.
10425 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10429 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10431 /// This routine is only called when we have AVX2 and thus a reasonable
10432 /// instruction set for v16i16 shuffling..
10433 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10434 const X86Subtarget *Subtarget,
10435 SelectionDAG &DAG) {
10437 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10438 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10439 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10440 ArrayRef<int> Mask = SVOp->getMask();
10441 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10442 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10444 // Check for being able to broadcast a single element.
10445 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10446 Mask, Subtarget, DAG))
10449 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10453 // Use dedicated unpack instructions for masks that match their pattern.
10454 if (isShuffleEquivalent(Mask,
10455 // First 128-bit lane:
10456 0, 16, 1, 17, 2, 18, 3, 19,
10457 // Second 128-bit lane:
10458 8, 24, 9, 25, 10, 26, 11, 27))
10459 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10460 if (isShuffleEquivalent(Mask,
10461 // First 128-bit lane:
10462 4, 20, 5, 21, 6, 22, 7, 23,
10463 // Second 128-bit lane:
10464 12, 28, 13, 29, 14, 30, 15, 31))
10465 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10467 if (isSingleInputShuffleMask(Mask)) {
10468 // There are no generalized cross-lane shuffle operations available on i16
10470 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10471 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10474 SDValue PSHUFBMask[32];
10475 for (int i = 0; i < 16; ++i) {
10476 if (Mask[i] == -1) {
10477 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10481 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10482 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10483 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10484 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10486 return DAG.getNode(
10487 ISD::BITCAST, DL, MVT::v16i16,
10489 X86ISD::PSHUFB, DL, MVT::v32i8,
10490 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10491 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10494 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10496 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10497 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10500 // Otherwise fall back on generic lowering.
10501 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10504 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10506 /// This routine is only called when we have AVX2 and thus a reasonable
10507 /// instruction set for v32i8 shuffling..
10508 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10509 const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10512 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10513 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10515 ArrayRef<int> Mask = SVOp->getMask();
10516 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10517 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10519 // Check for being able to broadcast a single element.
10520 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10521 Mask, Subtarget, DAG))
10524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10528 // Use dedicated unpack instructions for masks that match their pattern.
10529 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10531 if (isShuffleEquivalent(
10533 // First 128-bit lane:
10534 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10535 // Second 128-bit lane:
10536 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10537 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10538 if (isShuffleEquivalent(
10540 // First 128-bit lane:
10541 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10542 // Second 128-bit lane:
10543 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10544 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10546 if (isSingleInputShuffleMask(Mask)) {
10547 // There are no generalized cross-lane shuffle operations available on i8
10549 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10550 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10553 SDValue PSHUFBMask[32];
10554 for (int i = 0; i < 32; ++i)
10557 ? DAG.getUNDEF(MVT::i8)
10558 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10560 return DAG.getNode(
10561 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10562 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10565 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10567 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10568 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10571 // Otherwise fall back on generic lowering.
10572 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10575 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10577 /// This routine either breaks down the specific type of a 256-bit x86 vector
10578 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10579 /// together based on the available instructions.
10580 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10581 MVT VT, const X86Subtarget *Subtarget,
10582 SelectionDAG &DAG) {
10584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10585 ArrayRef<int> Mask = SVOp->getMask();
10587 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10588 // check for those subtargets here and avoid much of the subtarget querying in
10589 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10590 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10591 // floating point types there eventually, just immediately cast everything to
10592 // a float and operate entirely in that domain.
10593 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10594 int ElementBits = VT.getScalarSizeInBits();
10595 if (ElementBits < 32)
10596 // No floating point type available, decompose into 128-bit vectors.
10597 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10599 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10600 VT.getVectorNumElements());
10601 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10602 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10603 return DAG.getNode(ISD::BITCAST, DL, VT,
10604 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10607 switch (VT.SimpleTy) {
10609 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10611 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10613 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10615 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10619 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10622 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10626 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10627 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10628 const X86Subtarget *Subtarget,
10629 SelectionDAG &DAG) {
10631 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10632 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10634 ArrayRef<int> Mask = SVOp->getMask();
10635 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10637 // FIXME: Implement direct support for this type!
10638 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10641 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10642 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10643 const X86Subtarget *Subtarget,
10644 SelectionDAG &DAG) {
10646 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10647 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10649 ArrayRef<int> Mask = SVOp->getMask();
10650 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10652 // FIXME: Implement direct support for this type!
10653 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10656 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10657 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10658 const X86Subtarget *Subtarget,
10659 SelectionDAG &DAG) {
10661 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10662 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10664 ArrayRef<int> Mask = SVOp->getMask();
10665 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10667 // FIXME: Implement direct support for this type!
10668 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10671 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10672 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10673 const X86Subtarget *Subtarget,
10674 SelectionDAG &DAG) {
10676 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10677 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10679 ArrayRef<int> Mask = SVOp->getMask();
10680 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10682 // FIXME: Implement direct support for this type!
10683 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10686 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10687 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10688 const X86Subtarget *Subtarget,
10689 SelectionDAG &DAG) {
10691 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10692 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10693 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10694 ArrayRef<int> Mask = SVOp->getMask();
10695 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10696 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10698 // FIXME: Implement direct support for this type!
10699 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10702 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10703 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10704 const X86Subtarget *Subtarget,
10705 SelectionDAG &DAG) {
10707 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10708 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10710 ArrayRef<int> Mask = SVOp->getMask();
10711 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10712 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10714 // FIXME: Implement direct support for this type!
10715 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10718 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10720 /// This routine either breaks down the specific type of a 512-bit x86 vector
10721 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10722 /// together based on the available instructions.
10723 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10724 MVT VT, const X86Subtarget *Subtarget,
10725 SelectionDAG &DAG) {
10727 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10728 ArrayRef<int> Mask = SVOp->getMask();
10729 assert(Subtarget->hasAVX512() &&
10730 "Cannot lower 512-bit vectors w/ basic ISA!");
10732 // Check for being able to broadcast a single element.
10733 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10734 Mask, Subtarget, DAG))
10737 // Dispatch to each element type for lowering. If we don't have supprot for
10738 // specific element type shuffles at 512 bits, immediately split them and
10739 // lower them. Each lowering routine of a given type is allowed to assume that
10740 // the requisite ISA extensions for that element type are available.
10741 switch (VT.SimpleTy) {
10743 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10745 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10747 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10749 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 if (Subtarget->hasBWI())
10752 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 if (Subtarget->hasBWI())
10756 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10760 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10763 // Otherwise fall back on splitting.
10764 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10767 /// \brief Top-level lowering for x86 vector shuffles.
10769 /// This handles decomposition, canonicalization, and lowering of all x86
10770 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10771 /// above in helper routines. The canonicalization attempts to widen shuffles
10772 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10773 /// s.t. only one of the two inputs needs to be tested, etc.
10774 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10775 SelectionDAG &DAG) {
10776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10777 ArrayRef<int> Mask = SVOp->getMask();
10778 SDValue V1 = Op.getOperand(0);
10779 SDValue V2 = Op.getOperand(1);
10780 MVT VT = Op.getSimpleValueType();
10781 int NumElements = VT.getVectorNumElements();
10784 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10786 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10787 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10788 if (V1IsUndef && V2IsUndef)
10789 return DAG.getUNDEF(VT);
10791 // When we create a shuffle node we put the UNDEF node to second operand,
10792 // but in some cases the first operand may be transformed to UNDEF.
10793 // In this case we should just commute the node.
10795 return DAG.getCommutedVectorShuffle(*SVOp);
10797 // Check for non-undef masks pointing at an undef vector and make the masks
10798 // undef as well. This makes it easier to match the shuffle based solely on
10802 if (M >= NumElements) {
10803 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10804 for (int &M : NewMask)
10805 if (M >= NumElements)
10807 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10810 // Try to collapse shuffles into using a vector type with fewer elements but
10811 // wider element types. We cap this to not form integers or floating point
10812 // elements wider than 64 bits, but it might be interesting to form i128
10813 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10814 SmallVector<int, 16> WidenedMask;
10815 if (VT.getScalarSizeInBits() < 64 &&
10816 canWidenShuffleElements(Mask, WidenedMask)) {
10817 MVT NewEltVT = VT.isFloatingPoint()
10818 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10819 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10820 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10821 // Make sure that the new vector type is legal. For example, v2f64 isn't
10823 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10824 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10825 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10826 return DAG.getNode(ISD::BITCAST, dl, VT,
10827 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10831 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10832 for (int M : SVOp->getMask())
10834 ++NumUndefElements;
10835 else if (M < NumElements)
10840 // Commute the shuffle as needed such that more elements come from V1 than
10841 // V2. This allows us to match the shuffle pattern strictly on how many
10842 // elements come from V1 without handling the symmetric cases.
10843 if (NumV2Elements > NumV1Elements)
10844 return DAG.getCommutedVectorShuffle(*SVOp);
10846 // When the number of V1 and V2 elements are the same, try to minimize the
10847 // number of uses of V2 in the low half of the vector. When that is tied,
10848 // ensure that the sum of indices for V1 is equal to or lower than the sum
10849 // indices for V2. When those are equal, try to ensure that the number of odd
10850 // indices for V1 is lower than the number of odd indices for V2.
10851 if (NumV1Elements == NumV2Elements) {
10852 int LowV1Elements = 0, LowV2Elements = 0;
10853 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10854 if (M >= NumElements)
10858 if (LowV2Elements > LowV1Elements) {
10859 return DAG.getCommutedVectorShuffle(*SVOp);
10860 } else if (LowV2Elements == LowV1Elements) {
10861 int SumV1Indices = 0, SumV2Indices = 0;
10862 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10863 if (SVOp->getMask()[i] >= NumElements)
10865 else if (SVOp->getMask()[i] >= 0)
10867 if (SumV2Indices < SumV1Indices) {
10868 return DAG.getCommutedVectorShuffle(*SVOp);
10869 } else if (SumV2Indices == SumV1Indices) {
10870 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10871 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10872 if (SVOp->getMask()[i] >= NumElements)
10873 NumV2OddIndices += i % 2;
10874 else if (SVOp->getMask()[i] >= 0)
10875 NumV1OddIndices += i % 2;
10876 if (NumV2OddIndices < NumV1OddIndices)
10877 return DAG.getCommutedVectorShuffle(*SVOp);
10882 // For each vector width, delegate to a specialized lowering routine.
10883 if (VT.getSizeInBits() == 128)
10884 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10886 if (VT.getSizeInBits() == 256)
10887 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10889 // Force AVX-512 vectors to be scalarized for now.
10890 // FIXME: Implement AVX-512 support!
10891 if (VT.getSizeInBits() == 512)
10892 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10894 llvm_unreachable("Unimplemented!");
10898 //===----------------------------------------------------------------------===//
10899 // Legacy vector shuffle lowering
10901 // This code is the legacy code handling vector shuffles until the above
10902 // replaces its functionality and performance.
10903 //===----------------------------------------------------------------------===//
10905 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10906 bool hasInt256, unsigned *MaskOut = nullptr) {
10907 MVT EltVT = VT.getVectorElementType();
10909 // There is no blend with immediate in AVX-512.
10910 if (VT.is512BitVector())
10913 if (!hasSSE41 || EltVT == MVT::i8)
10915 if (!hasInt256 && VT == MVT::v16i16)
10918 unsigned MaskValue = 0;
10919 unsigned NumElems = VT.getVectorNumElements();
10920 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10921 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10922 unsigned NumElemsInLane = NumElems / NumLanes;
10924 // Blend for v16i16 should be symetric for the both lanes.
10925 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10927 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10928 int EltIdx = MaskVals[i];
10930 if ((EltIdx < 0 || EltIdx == (int)i) &&
10931 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10934 if (((unsigned)EltIdx == (i + NumElems)) &&
10935 (SndLaneEltIdx < 0 ||
10936 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10937 MaskValue |= (1 << i);
10943 *MaskOut = MaskValue;
10947 // Try to lower a shuffle node into a simple blend instruction.
10948 // This function assumes isBlendMask returns true for this
10949 // SuffleVectorSDNode
10950 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10951 unsigned MaskValue,
10952 const X86Subtarget *Subtarget,
10953 SelectionDAG &DAG) {
10954 MVT VT = SVOp->getSimpleValueType(0);
10955 MVT EltVT = VT.getVectorElementType();
10956 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10957 Subtarget->hasInt256() && "Trying to lower a "
10958 "VECTOR_SHUFFLE to a Blend but "
10959 "with the wrong mask"));
10960 SDValue V1 = SVOp->getOperand(0);
10961 SDValue V2 = SVOp->getOperand(1);
10963 unsigned NumElems = VT.getVectorNumElements();
10965 // Convert i32 vectors to floating point if it is not AVX2.
10966 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10968 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10969 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10971 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10972 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10975 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10976 DAG.getConstant(MaskValue, MVT::i32));
10977 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10980 /// In vector type \p VT, return true if the element at index \p InputIdx
10981 /// falls on a different 128-bit lane than \p OutputIdx.
10982 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10983 unsigned OutputIdx) {
10984 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10985 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10988 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10989 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10990 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10991 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10993 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10994 SelectionDAG &DAG) {
10995 MVT VT = V1.getSimpleValueType();
10996 assert(VT.is128BitVector() || VT.is256BitVector());
10998 MVT EltVT = VT.getVectorElementType();
10999 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11000 unsigned NumElts = VT.getVectorNumElements();
11002 SmallVector<SDValue, 32> PshufbMask;
11003 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11004 int InputIdx = MaskVals[OutputIdx];
11005 unsigned InputByteIdx;
11007 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11008 InputByteIdx = 0x80;
11010 // Cross lane is not allowed.
11011 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11013 InputByteIdx = InputIdx * EltSizeInBytes;
11014 // Index is an byte offset within the 128-bit lane.
11015 InputByteIdx &= 0xf;
11018 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11019 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11020 if (InputByteIdx != 0x80)
11025 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11027 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11028 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11029 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11032 // v8i16 shuffles - Prefer shuffles in the following order:
11033 // 1. [all] pshuflw, pshufhw, optional move
11034 // 2. [ssse3] 1 x pshufb
11035 // 3. [ssse3] 2 x pshufb + 1 x por
11036 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11038 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11039 SelectionDAG &DAG) {
11040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11041 SDValue V1 = SVOp->getOperand(0);
11042 SDValue V2 = SVOp->getOperand(1);
11044 SmallVector<int, 8> MaskVals;
11046 // Determine if more than 1 of the words in each of the low and high quadwords
11047 // of the result come from the same quadword of one of the two inputs. Undef
11048 // mask values count as coming from any quadword, for better codegen.
11050 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11051 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11052 unsigned LoQuad[] = { 0, 0, 0, 0 };
11053 unsigned HiQuad[] = { 0, 0, 0, 0 };
11054 // Indices of quads used.
11055 std::bitset<4> InputQuads;
11056 for (unsigned i = 0; i < 8; ++i) {
11057 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11058 int EltIdx = SVOp->getMaskElt(i);
11059 MaskVals.push_back(EltIdx);
11067 ++Quad[EltIdx / 4];
11068 InputQuads.set(EltIdx / 4);
11071 int BestLoQuad = -1;
11072 unsigned MaxQuad = 1;
11073 for (unsigned i = 0; i < 4; ++i) {
11074 if (LoQuad[i] > MaxQuad) {
11076 MaxQuad = LoQuad[i];
11080 int BestHiQuad = -1;
11082 for (unsigned i = 0; i < 4; ++i) {
11083 if (HiQuad[i] > MaxQuad) {
11085 MaxQuad = HiQuad[i];
11089 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11090 // of the two input vectors, shuffle them into one input vector so only a
11091 // single pshufb instruction is necessary. If there are more than 2 input
11092 // quads, disable the next transformation since it does not help SSSE3.
11093 bool V1Used = InputQuads[0] || InputQuads[1];
11094 bool V2Used = InputQuads[2] || InputQuads[3];
11095 if (Subtarget->hasSSSE3()) {
11096 if (InputQuads.count() == 2 && V1Used && V2Used) {
11097 BestLoQuad = InputQuads[0] ? 0 : 1;
11098 BestHiQuad = InputQuads[2] ? 2 : 3;
11100 if (InputQuads.count() > 2) {
11106 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11107 // the shuffle mask. If a quad is scored as -1, that means that it contains
11108 // words from all 4 input quadwords.
11110 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11112 BestLoQuad < 0 ? 0 : BestLoQuad,
11113 BestHiQuad < 0 ? 1 : BestHiQuad
11115 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11116 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11117 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11118 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11120 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11121 // source words for the shuffle, to aid later transformations.
11122 bool AllWordsInNewV = true;
11123 bool InOrder[2] = { true, true };
11124 for (unsigned i = 0; i != 8; ++i) {
11125 int idx = MaskVals[i];
11127 InOrder[i/4] = false;
11128 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11130 AllWordsInNewV = false;
11134 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11135 if (AllWordsInNewV) {
11136 for (int i = 0; i != 8; ++i) {
11137 int idx = MaskVals[i];
11140 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11141 if ((idx != i) && idx < 4)
11143 if ((idx != i) && idx > 3)
11152 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11153 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11154 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11155 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11156 unsigned TargetMask = 0;
11157 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11158 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11159 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11160 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11161 getShufflePSHUFLWImmediate(SVOp);
11162 V1 = NewV.getOperand(0);
11163 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11167 // Promote splats to a larger type which usually leads to more efficient code.
11168 // FIXME: Is this true if pshufb is available?
11169 if (SVOp->isSplat())
11170 return PromoteSplat(SVOp, DAG);
11172 // If we have SSSE3, and all words of the result are from 1 input vector,
11173 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11174 // is present, fall back to case 4.
11175 if (Subtarget->hasSSSE3()) {
11176 SmallVector<SDValue,16> pshufbMask;
11178 // If we have elements from both input vectors, set the high bit of the
11179 // shuffle mask element to zero out elements that come from V2 in the V1
11180 // mask, and elements that come from V1 in the V2 mask, so that the two
11181 // results can be OR'd together.
11182 bool TwoInputs = V1Used && V2Used;
11183 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11185 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11187 // Calculate the shuffle mask for the second input, shuffle it, and
11188 // OR it with the first shuffled input.
11189 CommuteVectorShuffleMask(MaskVals, 8);
11190 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11191 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11192 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11195 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11196 // and update MaskVals with new element order.
11197 std::bitset<8> InOrder;
11198 if (BestLoQuad >= 0) {
11199 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11200 for (int i = 0; i != 4; ++i) {
11201 int idx = MaskVals[i];
11204 } else if ((idx / 4) == BestLoQuad) {
11205 MaskV[i] = idx & 3;
11209 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11212 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11214 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11215 NewV.getOperand(0),
11216 getShufflePSHUFLWImmediate(SVOp), DAG);
11220 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11221 // and update MaskVals with the new element order.
11222 if (BestHiQuad >= 0) {
11223 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11224 for (unsigned i = 4; i != 8; ++i) {
11225 int idx = MaskVals[i];
11228 } else if ((idx / 4) == BestHiQuad) {
11229 MaskV[i] = (idx & 3) + 4;
11233 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11236 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11238 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11239 NewV.getOperand(0),
11240 getShufflePSHUFHWImmediate(SVOp), DAG);
11244 // In case BestHi & BestLo were both -1, which means each quadword has a word
11245 // from each of the four input quadwords, calculate the InOrder bitvector now
11246 // before falling through to the insert/extract cleanup.
11247 if (BestLoQuad == -1 && BestHiQuad == -1) {
11249 for (int i = 0; i != 8; ++i)
11250 if (MaskVals[i] < 0 || MaskVals[i] == i)
11254 // The other elements are put in the right place using pextrw and pinsrw.
11255 for (unsigned i = 0; i != 8; ++i) {
11258 int EltIdx = MaskVals[i];
11261 SDValue ExtOp = (EltIdx < 8) ?
11262 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11263 DAG.getIntPtrConstant(EltIdx)) :
11264 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11265 DAG.getIntPtrConstant(EltIdx - 8));
11266 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11267 DAG.getIntPtrConstant(i));
11272 /// \brief v16i16 shuffles
11274 /// FIXME: We only support generation of a single pshufb currently. We can
11275 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11276 /// well (e.g 2 x pshufb + 1 x por).
11278 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11280 SDValue V1 = SVOp->getOperand(0);
11281 SDValue V2 = SVOp->getOperand(1);
11284 if (V2.getOpcode() != ISD::UNDEF)
11287 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11288 return getPSHUFB(MaskVals, V1, dl, DAG);
11291 // v16i8 shuffles - Prefer shuffles in the following order:
11292 // 1. [ssse3] 1 x pshufb
11293 // 2. [ssse3] 2 x pshufb + 1 x por
11294 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11295 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11296 const X86Subtarget* Subtarget,
11297 SelectionDAG &DAG) {
11298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11299 SDValue V1 = SVOp->getOperand(0);
11300 SDValue V2 = SVOp->getOperand(1);
11302 ArrayRef<int> MaskVals = SVOp->getMask();
11304 // Promote splats to a larger type which usually leads to more efficient code.
11305 // FIXME: Is this true if pshufb is available?
11306 if (SVOp->isSplat())
11307 return PromoteSplat(SVOp, DAG);
11309 // If we have SSSE3, case 1 is generated when all result bytes come from
11310 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11311 // present, fall back to case 3.
11313 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11314 if (Subtarget->hasSSSE3()) {
11315 SmallVector<SDValue,16> pshufbMask;
11317 // If all result elements are from one input vector, then only translate
11318 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11320 // Otherwise, we have elements from both input vectors, and must zero out
11321 // elements that come from V2 in the first mask, and V1 in the second mask
11322 // so that we can OR them together.
11323 for (unsigned i = 0; i != 16; ++i) {
11324 int EltIdx = MaskVals[i];
11325 if (EltIdx < 0 || EltIdx >= 16)
11327 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11329 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11330 DAG.getNode(ISD::BUILD_VECTOR, dl,
11331 MVT::v16i8, pshufbMask));
11333 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11334 // the 2nd operand if it's undefined or zero.
11335 if (V2.getOpcode() == ISD::UNDEF ||
11336 ISD::isBuildVectorAllZeros(V2.getNode()))
11339 // Calculate the shuffle mask for the second input, shuffle it, and
11340 // OR it with the first shuffled input.
11341 pshufbMask.clear();
11342 for (unsigned i = 0; i != 16; ++i) {
11343 int EltIdx = MaskVals[i];
11344 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11345 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11347 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11348 DAG.getNode(ISD::BUILD_VECTOR, dl,
11349 MVT::v16i8, pshufbMask));
11350 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11353 // No SSSE3 - Calculate in place words and then fix all out of place words
11354 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11355 // the 16 different words that comprise the two doublequadword input vectors.
11356 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11357 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11359 for (int i = 0; i != 8; ++i) {
11360 int Elt0 = MaskVals[i*2];
11361 int Elt1 = MaskVals[i*2+1];
11363 // This word of the result is all undef, skip it.
11364 if (Elt0 < 0 && Elt1 < 0)
11367 // This word of the result is already in the correct place, skip it.
11368 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11371 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11372 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11375 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11376 // using a single extract together, load it and store it.
11377 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11378 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11379 DAG.getIntPtrConstant(Elt1 / 2));
11380 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11381 DAG.getIntPtrConstant(i));
11385 // If Elt1 is defined, extract it from the appropriate source. If the
11386 // source byte is not also odd, shift the extracted word left 8 bits
11387 // otherwise clear the bottom 8 bits if we need to do an or.
11389 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11390 DAG.getIntPtrConstant(Elt1 / 2));
11391 if ((Elt1 & 1) == 0)
11392 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11394 TLI.getShiftAmountTy(InsElt.getValueType())));
11395 else if (Elt0 >= 0)
11396 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11397 DAG.getConstant(0xFF00, MVT::i16));
11399 // If Elt0 is defined, extract it from the appropriate source. If the
11400 // source byte is not also even, shift the extracted word right 8 bits. If
11401 // Elt1 was also defined, OR the extracted values together before
11402 // inserting them in the result.
11404 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11405 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11406 if ((Elt0 & 1) != 0)
11407 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11409 TLI.getShiftAmountTy(InsElt0.getValueType())));
11410 else if (Elt1 >= 0)
11411 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11412 DAG.getConstant(0x00FF, MVT::i16));
11413 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11416 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11417 DAG.getIntPtrConstant(i));
11419 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11422 // v32i8 shuffles - Translate to VPSHUFB if possible.
11424 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11425 const X86Subtarget *Subtarget,
11426 SelectionDAG &DAG) {
11427 MVT VT = SVOp->getSimpleValueType(0);
11428 SDValue V1 = SVOp->getOperand(0);
11429 SDValue V2 = SVOp->getOperand(1);
11431 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11433 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11434 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11435 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11437 // VPSHUFB may be generated if
11438 // (1) one of input vector is undefined or zeroinitializer.
11439 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11440 // And (2) the mask indexes don't cross the 128-bit lane.
11441 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11442 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11445 if (V1IsAllZero && !V2IsAllZero) {
11446 CommuteVectorShuffleMask(MaskVals, 32);
11449 return getPSHUFB(MaskVals, V1, dl, DAG);
11452 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11453 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11454 /// done when every pair / quad of shuffle mask elements point to elements in
11455 /// the right sequence. e.g.
11456 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11458 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11459 SelectionDAG &DAG) {
11460 MVT VT = SVOp->getSimpleValueType(0);
11462 unsigned NumElems = VT.getVectorNumElements();
11465 switch (VT.SimpleTy) {
11466 default: llvm_unreachable("Unexpected!");
11469 return SDValue(SVOp, 0);
11470 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11471 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11472 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11473 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11474 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11475 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11478 SmallVector<int, 8> MaskVec;
11479 for (unsigned i = 0; i != NumElems; i += Scale) {
11481 for (unsigned j = 0; j != Scale; ++j) {
11482 int EltIdx = SVOp->getMaskElt(i+j);
11486 StartIdx = (EltIdx / Scale);
11487 if (EltIdx != (int)(StartIdx*Scale + j))
11490 MaskVec.push_back(StartIdx);
11493 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11494 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11495 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11498 /// getVZextMovL - Return a zero-extending vector move low node.
11500 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11501 SDValue SrcOp, SelectionDAG &DAG,
11502 const X86Subtarget *Subtarget, SDLoc dl) {
11503 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11504 LoadSDNode *LD = nullptr;
11505 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11506 LD = dyn_cast<LoadSDNode>(SrcOp);
11508 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11510 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11511 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11512 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11513 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11514 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11516 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11517 return DAG.getNode(ISD::BITCAST, dl, VT,
11518 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11519 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11521 SrcOp.getOperand(0)
11527 return DAG.getNode(ISD::BITCAST, dl, VT,
11528 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11529 DAG.getNode(ISD::BITCAST, dl,
11533 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11534 /// which could not be matched by any known target speficic shuffle
11536 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11538 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11539 if (NewOp.getNode())
11542 MVT VT = SVOp->getSimpleValueType(0);
11544 unsigned NumElems = VT.getVectorNumElements();
11545 unsigned NumLaneElems = NumElems / 2;
11548 MVT EltVT = VT.getVectorElementType();
11549 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11552 SmallVector<int, 16> Mask;
11553 for (unsigned l = 0; l < 2; ++l) {
11554 // Build a shuffle mask for the output, discovering on the fly which
11555 // input vectors to use as shuffle operands (recorded in InputUsed).
11556 // If building a suitable shuffle vector proves too hard, then bail
11557 // out with UseBuildVector set.
11558 bool UseBuildVector = false;
11559 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11560 unsigned LaneStart = l * NumLaneElems;
11561 for (unsigned i = 0; i != NumLaneElems; ++i) {
11562 // The mask element. This indexes into the input.
11563 int Idx = SVOp->getMaskElt(i+LaneStart);
11565 // the mask element does not index into any input vector.
11566 Mask.push_back(-1);
11570 // The input vector this mask element indexes into.
11571 int Input = Idx / NumLaneElems;
11573 // Turn the index into an offset from the start of the input vector.
11574 Idx -= Input * NumLaneElems;
11576 // Find or create a shuffle vector operand to hold this input.
11578 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11579 if (InputUsed[OpNo] == Input)
11580 // This input vector is already an operand.
11582 if (InputUsed[OpNo] < 0) {
11583 // Create a new operand for this input vector.
11584 InputUsed[OpNo] = Input;
11589 if (OpNo >= array_lengthof(InputUsed)) {
11590 // More than two input vectors used! Give up on trying to create a
11591 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11592 UseBuildVector = true;
11596 // Add the mask index for the new shuffle vector.
11597 Mask.push_back(Idx + OpNo * NumLaneElems);
11600 if (UseBuildVector) {
11601 SmallVector<SDValue, 16> SVOps;
11602 for (unsigned i = 0; i != NumLaneElems; ++i) {
11603 // The mask element. This indexes into the input.
11604 int Idx = SVOp->getMaskElt(i+LaneStart);
11606 SVOps.push_back(DAG.getUNDEF(EltVT));
11610 // The input vector this mask element indexes into.
11611 int Input = Idx / NumElems;
11613 // Turn the index into an offset from the start of the input vector.
11614 Idx -= Input * NumElems;
11616 // Extract the vector element by hand.
11617 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11618 SVOp->getOperand(Input),
11619 DAG.getIntPtrConstant(Idx)));
11622 // Construct the output using a BUILD_VECTOR.
11623 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11624 } else if (InputUsed[0] < 0) {
11625 // No input vectors were used! The result is undefined.
11626 Output[l] = DAG.getUNDEF(NVT);
11628 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11629 (InputUsed[0] % 2) * NumLaneElems,
11631 // If only one input was used, use an undefined vector for the other.
11632 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11633 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11634 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11635 // At least one input vector was used. Create a new shuffle vector.
11636 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11642 // Concatenate the result back
11643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11646 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11647 /// 4 elements, and match them with several different shuffle types.
11649 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11650 SDValue V1 = SVOp->getOperand(0);
11651 SDValue V2 = SVOp->getOperand(1);
11653 MVT VT = SVOp->getSimpleValueType(0);
11655 assert(VT.is128BitVector() && "Unsupported vector size");
11657 std::pair<int, int> Locs[4];
11658 int Mask1[] = { -1, -1, -1, -1 };
11659 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11661 unsigned NumHi = 0;
11662 unsigned NumLo = 0;
11663 for (unsigned i = 0; i != 4; ++i) {
11664 int Idx = PermMask[i];
11666 Locs[i] = std::make_pair(-1, -1);
11668 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11670 Locs[i] = std::make_pair(0, NumLo);
11671 Mask1[NumLo] = Idx;
11674 Locs[i] = std::make_pair(1, NumHi);
11676 Mask1[2+NumHi] = Idx;
11682 if (NumLo <= 2 && NumHi <= 2) {
11683 // If no more than two elements come from either vector. This can be
11684 // implemented with two shuffles. First shuffle gather the elements.
11685 // The second shuffle, which takes the first shuffle as both of its
11686 // vector operands, put the elements into the right order.
11687 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11689 int Mask2[] = { -1, -1, -1, -1 };
11691 for (unsigned i = 0; i != 4; ++i)
11692 if (Locs[i].first != -1) {
11693 unsigned Idx = (i < 2) ? 0 : 4;
11694 Idx += Locs[i].first * 2 + Locs[i].second;
11698 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11701 if (NumLo == 3 || NumHi == 3) {
11702 // Otherwise, we must have three elements from one vector, call it X, and
11703 // one element from the other, call it Y. First, use a shufps to build an
11704 // intermediate vector with the one element from Y and the element from X
11705 // that will be in the same half in the final destination (the indexes don't
11706 // matter). Then, use a shufps to build the final vector, taking the half
11707 // containing the element from Y from the intermediate, and the other half
11710 // Normalize it so the 3 elements come from V1.
11711 CommuteVectorShuffleMask(PermMask, 4);
11715 // Find the element from V2.
11717 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11718 int Val = PermMask[HiIndex];
11725 Mask1[0] = PermMask[HiIndex];
11727 Mask1[2] = PermMask[HiIndex^1];
11729 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11731 if (HiIndex >= 2) {
11732 Mask1[0] = PermMask[0];
11733 Mask1[1] = PermMask[1];
11734 Mask1[2] = HiIndex & 1 ? 6 : 4;
11735 Mask1[3] = HiIndex & 1 ? 4 : 6;
11736 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11739 Mask1[0] = HiIndex & 1 ? 2 : 0;
11740 Mask1[1] = HiIndex & 1 ? 0 : 2;
11741 Mask1[2] = PermMask[2];
11742 Mask1[3] = PermMask[3];
11747 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11750 // Break it into (shuffle shuffle_hi, shuffle_lo).
11751 int LoMask[] = { -1, -1, -1, -1 };
11752 int HiMask[] = { -1, -1, -1, -1 };
11754 int *MaskPtr = LoMask;
11755 unsigned MaskIdx = 0;
11756 unsigned LoIdx = 0;
11757 unsigned HiIdx = 2;
11758 for (unsigned i = 0; i != 4; ++i) {
11765 int Idx = PermMask[i];
11767 Locs[i] = std::make_pair(-1, -1);
11768 } else if (Idx < 4) {
11769 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11770 MaskPtr[LoIdx] = Idx;
11773 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11774 MaskPtr[HiIdx] = Idx;
11779 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11780 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11781 int MaskOps[] = { -1, -1, -1, -1 };
11782 for (unsigned i = 0; i != 4; ++i)
11783 if (Locs[i].first != -1)
11784 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11785 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11788 static bool MayFoldVectorLoad(SDValue V) {
11789 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11790 V = V.getOperand(0);
11792 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11793 V = V.getOperand(0);
11794 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11795 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11796 // BUILD_VECTOR (load), undef
11797 V = V.getOperand(0);
11799 return MayFoldLoad(V);
11803 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11804 MVT VT = Op.getSimpleValueType();
11806 // Canonizalize to v2f64.
11807 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11808 return DAG.getNode(ISD::BITCAST, dl, VT,
11809 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11814 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11816 SDValue V1 = Op.getOperand(0);
11817 SDValue V2 = Op.getOperand(1);
11818 MVT VT = Op.getSimpleValueType();
11820 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11822 if (HasSSE2 && VT == MVT::v2f64)
11823 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11825 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11826 return DAG.getNode(ISD::BITCAST, dl, VT,
11827 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11828 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11829 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11833 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11834 SDValue V1 = Op.getOperand(0);
11835 SDValue V2 = Op.getOperand(1);
11836 MVT VT = Op.getSimpleValueType();
11838 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11839 "unsupported shuffle type");
11841 if (V2.getOpcode() == ISD::UNDEF)
11845 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11849 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11850 SDValue V1 = Op.getOperand(0);
11851 SDValue V2 = Op.getOperand(1);
11852 MVT VT = Op.getSimpleValueType();
11853 unsigned NumElems = VT.getVectorNumElements();
11855 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11856 // operand of these instructions is only memory, so check if there's a
11857 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11859 bool CanFoldLoad = false;
11861 // Trivial case, when V2 comes from a load.
11862 if (MayFoldVectorLoad(V2))
11863 CanFoldLoad = true;
11865 // When V1 is a load, it can be folded later into a store in isel, example:
11866 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11868 // (MOVLPSmr addr:$src1, VR128:$src2)
11869 // So, recognize this potential and also use MOVLPS or MOVLPD
11870 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11871 CanFoldLoad = true;
11873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11875 if (HasSSE2 && NumElems == 2)
11876 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11879 // If we don't care about the second element, proceed to use movss.
11880 if (SVOp->getMaskElt(1) != -1)
11881 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11884 // movl and movlp will both match v2i64, but v2i64 is never matched by
11885 // movl earlier because we make it strict to avoid messing with the movlp load
11886 // folding logic (see the code above getMOVLP call). Match it here then,
11887 // this is horrible, but will stay like this until we move all shuffle
11888 // matching to x86 specific nodes. Note that for the 1st condition all
11889 // types are matched with movsd.
11891 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11892 // as to remove this logic from here, as much as possible
11893 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11894 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11895 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11898 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11900 // Invert the operand order and use SHUFPS to match it.
11901 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11902 getShuffleSHUFImmediate(SVOp), DAG);
11905 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11906 SelectionDAG &DAG) {
11908 MVT VT = Load->getSimpleValueType(0);
11909 MVT EVT = VT.getVectorElementType();
11910 SDValue Addr = Load->getOperand(1);
11911 SDValue NewAddr = DAG.getNode(
11912 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11913 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11916 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11917 DAG.getMachineFunction().getMachineMemOperand(
11918 Load->getMemOperand(), 0, EVT.getStoreSize()));
11922 // It is only safe to call this function if isINSERTPSMask is true for
11923 // this shufflevector mask.
11924 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11925 SelectionDAG &DAG) {
11926 // Generate an insertps instruction when inserting an f32 from memory onto a
11927 // v4f32 or when copying a member from one v4f32 to another.
11928 // We also use it for transferring i32 from one register to another,
11929 // since it simply copies the same bits.
11930 // If we're transferring an i32 from memory to a specific element in a
11931 // register, we output a generic DAG that will match the PINSRD
11933 MVT VT = SVOp->getSimpleValueType(0);
11934 MVT EVT = VT.getVectorElementType();
11935 SDValue V1 = SVOp->getOperand(0);
11936 SDValue V2 = SVOp->getOperand(1);
11937 auto Mask = SVOp->getMask();
11938 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11939 "unsupported vector type for insertps/pinsrd");
11941 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11942 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11943 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11947 unsigned DestIndex;
11951 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11954 // If we have 1 element from each vector, we have to check if we're
11955 // changing V1's element's place. If so, we're done. Otherwise, we
11956 // should assume we're changing V2's element's place and behave
11958 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11959 assert(DestIndex <= INT32_MAX && "truncated destination index");
11960 if (FromV1 == FromV2 &&
11961 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11965 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11968 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11969 "More than one element from V1 and from V2, or no elements from one "
11970 "of the vectors. This case should not have returned true from "
11975 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11978 // Get an index into the source vector in the range [0,4) (the mask is
11979 // in the range [0,8) because it can address V1 and V2)
11980 unsigned SrcIndex = Mask[DestIndex] % 4;
11981 if (MayFoldLoad(From)) {
11982 // Trivial case, when From comes from a load and is only used by the
11983 // shuffle. Make it use insertps from the vector that we need from that
11986 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11987 if (!NewLoad.getNode())
11990 if (EVT == MVT::f32) {
11991 // Create this as a scalar to vector to match the instruction pattern.
11992 SDValue LoadScalarToVector =
11993 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11994 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11995 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11997 } else { // EVT == MVT::i32
11998 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11999 // instruction, to match the PINSRD instruction, which loads an i32 to a
12000 // certain vector element.
12001 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12002 DAG.getConstant(DestIndex, MVT::i32));
12006 // Vector-element-to-vector
12007 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12008 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12011 // Reduce a vector shuffle to zext.
12012 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12013 SelectionDAG &DAG) {
12014 // PMOVZX is only available from SSE41.
12015 if (!Subtarget->hasSSE41())
12018 MVT VT = Op.getSimpleValueType();
12020 // Only AVX2 support 256-bit vector integer extending.
12021 if (!Subtarget->hasInt256() && VT.is256BitVector())
12024 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12026 SDValue V1 = Op.getOperand(0);
12027 SDValue V2 = Op.getOperand(1);
12028 unsigned NumElems = VT.getVectorNumElements();
12030 // Extending is an unary operation and the element type of the source vector
12031 // won't be equal to or larger than i64.
12032 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12033 VT.getVectorElementType() == MVT::i64)
12036 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12037 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12038 while ((1U << Shift) < NumElems) {
12039 if (SVOp->getMaskElt(1U << Shift) == 1)
12042 // The maximal ratio is 8, i.e. from i8 to i64.
12047 // Check the shuffle mask.
12048 unsigned Mask = (1U << Shift) - 1;
12049 for (unsigned i = 0; i != NumElems; ++i) {
12050 int EltIdx = SVOp->getMaskElt(i);
12051 if ((i & Mask) != 0 && EltIdx != -1)
12053 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12057 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12058 MVT NeVT = MVT::getIntegerVT(NBits);
12059 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12061 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12064 return DAG.getNode(ISD::BITCAST, DL, VT,
12065 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12068 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12069 SelectionDAG &DAG) {
12070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12071 MVT VT = Op.getSimpleValueType();
12073 SDValue V1 = Op.getOperand(0);
12074 SDValue V2 = Op.getOperand(1);
12076 if (isZeroShuffle(SVOp))
12077 return getZeroVector(VT, Subtarget, DAG, dl);
12079 // Handle splat operations
12080 if (SVOp->isSplat()) {
12081 // Use vbroadcast whenever the splat comes from a foldable load
12082 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12083 if (Broadcast.getNode())
12087 // Check integer expanding shuffles.
12088 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12089 if (NewOp.getNode())
12092 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12094 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12095 VT == MVT::v32i8) {
12096 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12097 if (NewOp.getNode())
12098 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12099 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12100 // FIXME: Figure out a cleaner way to do this.
12101 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12102 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12103 if (NewOp.getNode()) {
12104 MVT NewVT = NewOp.getSimpleValueType();
12105 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12106 NewVT, true, false))
12107 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12110 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12111 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12112 if (NewOp.getNode()) {
12113 MVT NewVT = NewOp.getSimpleValueType();
12114 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12115 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12124 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12126 SDValue V1 = Op.getOperand(0);
12127 SDValue V2 = Op.getOperand(1);
12128 MVT VT = Op.getSimpleValueType();
12130 unsigned NumElems = VT.getVectorNumElements();
12131 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12132 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12133 bool V1IsSplat = false;
12134 bool V2IsSplat = false;
12135 bool HasSSE2 = Subtarget->hasSSE2();
12136 bool HasFp256 = Subtarget->hasFp256();
12137 bool HasInt256 = Subtarget->hasInt256();
12138 MachineFunction &MF = DAG.getMachineFunction();
12139 bool OptForSize = MF.getFunction()->getAttributes().
12140 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12142 // Check if we should use the experimental vector shuffle lowering. If so,
12143 // delegate completely to that code path.
12144 if (ExperimentalVectorShuffleLowering)
12145 return lowerVectorShuffle(Op, Subtarget, DAG);
12147 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12149 if (V1IsUndef && V2IsUndef)
12150 return DAG.getUNDEF(VT);
12152 // When we create a shuffle node we put the UNDEF node to second operand,
12153 // but in some cases the first operand may be transformed to UNDEF.
12154 // In this case we should just commute the node.
12156 return DAG.getCommutedVectorShuffle(*SVOp);
12158 // Vector shuffle lowering takes 3 steps:
12160 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12161 // narrowing and commutation of operands should be handled.
12162 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12164 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12165 // so the shuffle can be broken into other shuffles and the legalizer can
12166 // try the lowering again.
12168 // The general idea is that no vector_shuffle operation should be left to
12169 // be matched during isel, all of them must be converted to a target specific
12172 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12173 // narrowing and commutation of operands should be handled. The actual code
12174 // doesn't include all of those, work in progress...
12175 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12176 if (NewOp.getNode())
12179 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12181 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12182 // unpckh_undef). Only use pshufd if speed is more important than size.
12183 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12184 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12185 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12186 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12188 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12189 V2IsUndef && MayFoldVectorLoad(V1))
12190 return getMOVDDup(Op, dl, V1, DAG);
12192 if (isMOVHLPS_v_undef_Mask(M, VT))
12193 return getMOVHighToLow(Op, dl, DAG);
12195 // Use to match splats
12196 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12197 (VT == MVT::v2f64 || VT == MVT::v2i64))
12198 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12200 if (isPSHUFDMask(M, VT)) {
12201 // The actual implementation will match the mask in the if above and then
12202 // during isel it can match several different instructions, not only pshufd
12203 // as its name says, sad but true, emulate the behavior for now...
12204 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12205 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12207 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12209 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12210 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12212 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12213 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12216 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12220 if (isPALIGNRMask(M, VT, Subtarget))
12221 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12222 getShufflePALIGNRImmediate(SVOp),
12225 if (isVALIGNMask(M, VT, Subtarget))
12226 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12227 getShuffleVALIGNImmediate(SVOp),
12230 // Check if this can be converted into a logical shift.
12231 bool isLeft = false;
12232 unsigned ShAmt = 0;
12234 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12235 if (isShift && ShVal.hasOneUse()) {
12236 // If the shifted value has multiple uses, it may be cheaper to use
12237 // v_set0 + movlhps or movhlps, etc.
12238 MVT EltVT = VT.getVectorElementType();
12239 ShAmt *= EltVT.getSizeInBits();
12240 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12243 if (isMOVLMask(M, VT)) {
12244 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12245 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12246 if (!isMOVLPMask(M, VT)) {
12247 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12248 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12250 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12251 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12255 // FIXME: fold these into legal mask.
12256 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12257 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12259 if (isMOVHLPSMask(M, VT))
12260 return getMOVHighToLow(Op, dl, DAG);
12262 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12263 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12265 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12266 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12268 if (isMOVLPMask(M, VT))
12269 return getMOVLP(Op, dl, DAG, HasSSE2);
12271 if (ShouldXformToMOVHLPS(M, VT) ||
12272 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12273 return DAG.getCommutedVectorShuffle(*SVOp);
12276 // No better options. Use a vshldq / vsrldq.
12277 MVT EltVT = VT.getVectorElementType();
12278 ShAmt *= EltVT.getSizeInBits();
12279 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12282 bool Commuted = false;
12283 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12284 // 1,1,1,1 -> v8i16 though.
12285 BitVector UndefElements;
12286 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12287 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12289 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12290 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12293 // Canonicalize the splat or undef, if present, to be on the RHS.
12294 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12295 CommuteVectorShuffleMask(M, NumElems);
12297 std::swap(V1IsSplat, V2IsSplat);
12301 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12302 // Shuffling low element of v1 into undef, just return v1.
12305 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12306 // the instruction selector will not match, so get a canonical MOVL with
12307 // swapped operands to undo the commute.
12308 return getMOVL(DAG, dl, VT, V2, V1);
12311 if (isUNPCKLMask(M, VT, HasInt256))
12312 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12314 if (isUNPCKHMask(M, VT, HasInt256))
12315 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12318 // Normalize mask so all entries that point to V2 points to its first
12319 // element then try to match unpck{h|l} again. If match, return a
12320 // new vector_shuffle with the corrected mask.p
12321 SmallVector<int, 8> NewMask(M.begin(), M.end());
12322 NormalizeMask(NewMask, NumElems);
12323 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12324 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12325 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12326 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12330 // Commute is back and try unpck* again.
12331 // FIXME: this seems wrong.
12332 CommuteVectorShuffleMask(M, NumElems);
12334 std::swap(V1IsSplat, V2IsSplat);
12336 if (isUNPCKLMask(M, VT, HasInt256))
12337 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12339 if (isUNPCKHMask(M, VT, HasInt256))
12340 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12343 // Normalize the node to match x86 shuffle ops if needed
12344 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12345 return DAG.getCommutedVectorShuffle(*SVOp);
12347 // The checks below are all present in isShuffleMaskLegal, but they are
12348 // inlined here right now to enable us to directly emit target specific
12349 // nodes, and remove one by one until they don't return Op anymore.
12351 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12352 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12353 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12354 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12357 if (isPSHUFHWMask(M, VT, HasInt256))
12358 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12359 getShufflePSHUFHWImmediate(SVOp),
12362 if (isPSHUFLWMask(M, VT, HasInt256))
12363 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12364 getShufflePSHUFLWImmediate(SVOp),
12367 unsigned MaskValue;
12368 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12370 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12372 if (isSHUFPMask(M, VT))
12373 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12374 getShuffleSHUFImmediate(SVOp), DAG);
12376 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12377 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12378 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12379 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12381 //===--------------------------------------------------------------------===//
12382 // Generate target specific nodes for 128 or 256-bit shuffles only
12383 // supported in the AVX instruction set.
12386 // Handle VMOVDDUPY permutations
12387 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12388 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12390 // Handle VPERMILPS/D* permutations
12391 if (isVPERMILPMask(M, VT)) {
12392 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12393 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12394 getShuffleSHUFImmediate(SVOp), DAG);
12395 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12396 getShuffleSHUFImmediate(SVOp), DAG);
12400 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12401 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12402 Idx*(NumElems/2), DAG, dl);
12404 // Handle VPERM2F128/VPERM2I128 permutations
12405 if (isVPERM2X128Mask(M, VT, HasFp256))
12406 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12407 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12409 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12410 return getINSERTPS(SVOp, dl, DAG);
12413 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12414 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12416 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12417 VT.is512BitVector()) {
12418 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12419 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12420 SmallVector<SDValue, 16> permclMask;
12421 for (unsigned i = 0; i != NumElems; ++i) {
12422 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12425 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12427 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12428 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12429 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12430 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12431 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12434 //===--------------------------------------------------------------------===//
12435 // Since no target specific shuffle was selected for this generic one,
12436 // lower it into other known shuffles. FIXME: this isn't true yet, but
12437 // this is the plan.
12440 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12441 if (VT == MVT::v8i16) {
12442 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12443 if (NewOp.getNode())
12447 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12448 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12449 if (NewOp.getNode())
12453 if (VT == MVT::v16i8) {
12454 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12455 if (NewOp.getNode())
12459 if (VT == MVT::v32i8) {
12460 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12461 if (NewOp.getNode())
12465 // Handle all 128-bit wide vectors with 4 elements, and match them with
12466 // several different shuffle types.
12467 if (NumElems == 4 && VT.is128BitVector())
12468 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12470 // Handle general 256-bit shuffles
12471 if (VT.is256BitVector())
12472 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12477 // This function assumes its argument is a BUILD_VECTOR of constants or
12478 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12480 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12481 unsigned &MaskValue) {
12483 unsigned NumElems = BuildVector->getNumOperands();
12484 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12485 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12486 unsigned NumElemsInLane = NumElems / NumLanes;
12488 // Blend for v16i16 should be symetric for the both lanes.
12489 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12490 SDValue EltCond = BuildVector->getOperand(i);
12491 SDValue SndLaneEltCond =
12492 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12494 int Lane1Cond = -1, Lane2Cond = -1;
12495 if (isa<ConstantSDNode>(EltCond))
12496 Lane1Cond = !isZero(EltCond);
12497 if (isa<ConstantSDNode>(SndLaneEltCond))
12498 Lane2Cond = !isZero(SndLaneEltCond);
12500 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12501 // Lane1Cond != 0, means we want the first argument.
12502 // Lane1Cond == 0, means we want the second argument.
12503 // The encoding of this argument is 0 for the first argument, 1
12504 // for the second. Therefore, invert the condition.
12505 MaskValue |= !Lane1Cond << i;
12506 else if (Lane1Cond < 0)
12507 MaskValue |= !Lane2Cond << i;
12514 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12516 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12517 SelectionDAG &DAG) {
12518 SDValue Cond = Op.getOperand(0);
12519 SDValue LHS = Op.getOperand(1);
12520 SDValue RHS = Op.getOperand(2);
12522 MVT VT = Op.getSimpleValueType();
12523 MVT EltVT = VT.getVectorElementType();
12524 unsigned NumElems = VT.getVectorNumElements();
12526 // There is no blend with immediate in AVX-512.
12527 if (VT.is512BitVector())
12530 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12532 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12535 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12538 // Check the mask for BLEND and build the value.
12539 unsigned MaskValue = 0;
12540 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12543 // Convert i32 vectors to floating point if it is not AVX2.
12544 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12546 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12547 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12549 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12550 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12553 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12554 DAG.getConstant(MaskValue, MVT::i32));
12555 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12558 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12559 // A vselect where all conditions and data are constants can be optimized into
12560 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12561 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12562 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12563 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12566 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12567 if (BlendOp.getNode())
12570 // Some types for vselect were previously set to Expand, not Legal or
12571 // Custom. Return an empty SDValue so we fall-through to Expand, after
12572 // the Custom lowering phase.
12573 MVT VT = Op.getSimpleValueType();
12574 switch (VT.SimpleTy) {
12579 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12584 // We couldn't create a "Blend with immediate" node.
12585 // This node should still be legal, but we'll have to emit a blendv*
12590 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12591 MVT VT = Op.getSimpleValueType();
12594 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12597 if (VT.getSizeInBits() == 8) {
12598 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12599 Op.getOperand(0), Op.getOperand(1));
12600 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12601 DAG.getValueType(VT));
12602 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12605 if (VT.getSizeInBits() == 16) {
12606 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12607 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12609 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12610 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12611 DAG.getNode(ISD::BITCAST, dl,
12614 Op.getOperand(1)));
12615 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12616 Op.getOperand(0), Op.getOperand(1));
12617 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12618 DAG.getValueType(VT));
12619 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12622 if (VT == MVT::f32) {
12623 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12624 // the result back to FR32 register. It's only worth matching if the
12625 // result has a single use which is a store or a bitcast to i32. And in
12626 // the case of a store, it's not worth it if the index is a constant 0,
12627 // because a MOVSSmr can be used instead, which is smaller and faster.
12628 if (!Op.hasOneUse())
12630 SDNode *User = *Op.getNode()->use_begin();
12631 if ((User->getOpcode() != ISD::STORE ||
12632 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12633 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12634 (User->getOpcode() != ISD::BITCAST ||
12635 User->getValueType(0) != MVT::i32))
12637 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12638 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12641 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12644 if (VT == MVT::i32 || VT == MVT::i64) {
12645 // ExtractPS/pextrq works with constant index.
12646 if (isa<ConstantSDNode>(Op.getOperand(1)))
12652 /// Extract one bit from mask vector, like v16i1 or v8i1.
12653 /// AVX-512 feature.
12655 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12656 SDValue Vec = Op.getOperand(0);
12658 MVT VecVT = Vec.getSimpleValueType();
12659 SDValue Idx = Op.getOperand(1);
12660 MVT EltVT = Op.getSimpleValueType();
12662 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12664 // variable index can't be handled in mask registers,
12665 // extend vector to VR512
12666 if (!isa<ConstantSDNode>(Idx)) {
12667 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12668 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12669 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12670 ExtVT.getVectorElementType(), Ext, Idx);
12671 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12674 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12675 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12676 unsigned MaxSift = rc->getSize()*8 - 1;
12677 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12678 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12679 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12680 DAG.getConstant(MaxSift, MVT::i8));
12681 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12682 DAG.getIntPtrConstant(0));
12686 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12687 SelectionDAG &DAG) const {
12689 SDValue Vec = Op.getOperand(0);
12690 MVT VecVT = Vec.getSimpleValueType();
12691 SDValue Idx = Op.getOperand(1);
12693 if (Op.getSimpleValueType() == MVT::i1)
12694 return ExtractBitFromMaskVector(Op, DAG);
12696 if (!isa<ConstantSDNode>(Idx)) {
12697 if (VecVT.is512BitVector() ||
12698 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12699 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12702 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12703 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12704 MaskEltVT.getSizeInBits());
12706 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12707 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12708 getZeroVector(MaskVT, Subtarget, DAG, dl),
12709 Idx, DAG.getConstant(0, getPointerTy()));
12710 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12711 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12712 Perm, DAG.getConstant(0, getPointerTy()));
12717 // If this is a 256-bit vector result, first extract the 128-bit vector and
12718 // then extract the element from the 128-bit vector.
12719 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12721 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12722 // Get the 128-bit vector.
12723 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12724 MVT EltVT = VecVT.getVectorElementType();
12726 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12728 //if (IdxVal >= NumElems/2)
12729 // IdxVal -= NumElems/2;
12730 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12731 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12732 DAG.getConstant(IdxVal, MVT::i32));
12735 assert(VecVT.is128BitVector() && "Unexpected vector length");
12737 if (Subtarget->hasSSE41()) {
12738 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12743 MVT VT = Op.getSimpleValueType();
12744 // TODO: handle v16i8.
12745 if (VT.getSizeInBits() == 16) {
12746 SDValue Vec = Op.getOperand(0);
12747 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12749 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12750 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12751 DAG.getNode(ISD::BITCAST, dl,
12753 Op.getOperand(1)));
12754 // Transform it so it match pextrw which produces a 32-bit result.
12755 MVT EltVT = MVT::i32;
12756 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12757 Op.getOperand(0), Op.getOperand(1));
12758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12759 DAG.getValueType(VT));
12760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12763 if (VT.getSizeInBits() == 32) {
12764 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12768 // SHUFPS the element to the lowest double word, then movss.
12769 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12770 MVT VVT = Op.getOperand(0).getSimpleValueType();
12771 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12772 DAG.getUNDEF(VVT), Mask);
12773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12774 DAG.getIntPtrConstant(0));
12777 if (VT.getSizeInBits() == 64) {
12778 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12779 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12780 // to match extract_elt for f64.
12781 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12785 // UNPCKHPD the element to the lowest double word, then movsd.
12786 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12787 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12788 int Mask[2] = { 1, -1 };
12789 MVT VVT = Op.getOperand(0).getSimpleValueType();
12790 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12791 DAG.getUNDEF(VVT), Mask);
12792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12793 DAG.getIntPtrConstant(0));
12799 /// Insert one bit to mask vector, like v16i1 or v8i1.
12800 /// AVX-512 feature.
12802 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12804 SDValue Vec = Op.getOperand(0);
12805 SDValue Elt = Op.getOperand(1);
12806 SDValue Idx = Op.getOperand(2);
12807 MVT VecVT = Vec.getSimpleValueType();
12809 if (!isa<ConstantSDNode>(Idx)) {
12810 // Non constant index. Extend source and destination,
12811 // insert element and then truncate the result.
12812 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12813 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12814 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12815 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12816 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12817 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12820 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12821 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12822 if (Vec.getOpcode() == ISD::UNDEF)
12823 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12824 DAG.getConstant(IdxVal, MVT::i8));
12825 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12826 unsigned MaxSift = rc->getSize()*8 - 1;
12827 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12828 DAG.getConstant(MaxSift, MVT::i8));
12829 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12830 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12831 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12834 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12835 SelectionDAG &DAG) const {
12836 MVT VT = Op.getSimpleValueType();
12837 MVT EltVT = VT.getVectorElementType();
12839 if (EltVT == MVT::i1)
12840 return InsertBitToMaskVector(Op, DAG);
12843 SDValue N0 = Op.getOperand(0);
12844 SDValue N1 = Op.getOperand(1);
12845 SDValue N2 = Op.getOperand(2);
12846 if (!isa<ConstantSDNode>(N2))
12848 auto *N2C = cast<ConstantSDNode>(N2);
12849 unsigned IdxVal = N2C->getZExtValue();
12851 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12852 // into that, and then insert the subvector back into the result.
12853 if (VT.is256BitVector() || VT.is512BitVector()) {
12854 // Get the desired 128-bit vector half.
12855 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12857 // Insert the element into the desired half.
12858 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12859 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12861 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12862 DAG.getConstant(IdxIn128, MVT::i32));
12864 // Insert the changed part back to the 256-bit vector
12865 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12867 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12869 if (Subtarget->hasSSE41()) {
12870 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12872 if (VT == MVT::v8i16) {
12873 Opc = X86ISD::PINSRW;
12875 assert(VT == MVT::v16i8);
12876 Opc = X86ISD::PINSRB;
12879 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12881 if (N1.getValueType() != MVT::i32)
12882 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12883 if (N2.getValueType() != MVT::i32)
12884 N2 = DAG.getIntPtrConstant(IdxVal);
12885 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12888 if (EltVT == MVT::f32) {
12889 // Bits [7:6] of the constant are the source select. This will always be
12890 // zero here. The DAG Combiner may combine an extract_elt index into
12892 // bits. For example (insert (extract, 3), 2) could be matched by
12894 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12895 // Bits [5:4] of the constant are the destination select. This is the
12896 // value of the incoming immediate.
12897 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12898 // combine either bitwise AND or insert of float 0.0 to set these bits.
12899 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12900 // Create this as a scalar to vector..
12901 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12902 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12905 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12906 // PINSR* works with constant index.
12911 if (EltVT == MVT::i8)
12914 if (EltVT.getSizeInBits() == 16) {
12915 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12916 // as its second argument.
12917 if (N1.getValueType() != MVT::i32)
12918 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12919 if (N2.getValueType() != MVT::i32)
12920 N2 = DAG.getIntPtrConstant(IdxVal);
12921 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12926 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12928 MVT OpVT = Op.getSimpleValueType();
12930 // If this is a 256-bit vector result, first insert into a 128-bit
12931 // vector and then insert into the 256-bit vector.
12932 if (!OpVT.is128BitVector()) {
12933 // Insert into a 128-bit vector.
12934 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12935 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12936 OpVT.getVectorNumElements() / SizeFactor);
12938 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12940 // Insert the 128-bit vector.
12941 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12944 if (OpVT == MVT::v1i64 &&
12945 Op.getOperand(0).getValueType() == MVT::i64)
12946 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12948 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12949 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12950 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12951 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12954 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12955 // a simple subregister reference or explicit instructions to grab
12956 // upper bits of a vector.
12957 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12958 SelectionDAG &DAG) {
12960 SDValue In = Op.getOperand(0);
12961 SDValue Idx = Op.getOperand(1);
12962 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12963 MVT ResVT = Op.getSimpleValueType();
12964 MVT InVT = In.getSimpleValueType();
12966 if (Subtarget->hasFp256()) {
12967 if (ResVT.is128BitVector() &&
12968 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12969 isa<ConstantSDNode>(Idx)) {
12970 return Extract128BitVector(In, IdxVal, DAG, dl);
12972 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12973 isa<ConstantSDNode>(Idx)) {
12974 return Extract256BitVector(In, IdxVal, DAG, dl);
12980 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12981 // simple superregister reference or explicit instructions to insert
12982 // the upper bits of a vector.
12983 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12984 SelectionDAG &DAG) {
12985 if (Subtarget->hasFp256()) {
12986 SDLoc dl(Op.getNode());
12987 SDValue Vec = Op.getNode()->getOperand(0);
12988 SDValue SubVec = Op.getNode()->getOperand(1);
12989 SDValue Idx = Op.getNode()->getOperand(2);
12991 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12992 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12993 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12994 isa<ConstantSDNode>(Idx)) {
12995 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12996 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12999 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13000 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13001 isa<ConstantSDNode>(Idx)) {
13002 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13003 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13009 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13010 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13011 // one of the above mentioned nodes. It has to be wrapped because otherwise
13012 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13013 // be used to form addressing mode. These wrapped nodes will be selected
13016 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13017 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13019 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13020 // global base reg.
13021 unsigned char OpFlag = 0;
13022 unsigned WrapperKind = X86ISD::Wrapper;
13023 CodeModel::Model M = DAG.getTarget().getCodeModel();
13025 if (Subtarget->isPICStyleRIPRel() &&
13026 (M == CodeModel::Small || M == CodeModel::Kernel))
13027 WrapperKind = X86ISD::WrapperRIP;
13028 else if (Subtarget->isPICStyleGOT())
13029 OpFlag = X86II::MO_GOTOFF;
13030 else if (Subtarget->isPICStyleStubPIC())
13031 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13033 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13034 CP->getAlignment(),
13035 CP->getOffset(), OpFlag);
13037 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13038 // With PIC, the address is actually $g + Offset.
13040 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13041 DAG.getNode(X86ISD::GlobalBaseReg,
13042 SDLoc(), getPointerTy()),
13049 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13050 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13052 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13053 // global base reg.
13054 unsigned char OpFlag = 0;
13055 unsigned WrapperKind = X86ISD::Wrapper;
13056 CodeModel::Model M = DAG.getTarget().getCodeModel();
13058 if (Subtarget->isPICStyleRIPRel() &&
13059 (M == CodeModel::Small || M == CodeModel::Kernel))
13060 WrapperKind = X86ISD::WrapperRIP;
13061 else if (Subtarget->isPICStyleGOT())
13062 OpFlag = X86II::MO_GOTOFF;
13063 else if (Subtarget->isPICStyleStubPIC())
13064 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13066 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13069 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13071 // With PIC, the address is actually $g + Offset.
13073 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13074 DAG.getNode(X86ISD::GlobalBaseReg,
13075 SDLoc(), getPointerTy()),
13082 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13083 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13085 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13086 // global base reg.
13087 unsigned char OpFlag = 0;
13088 unsigned WrapperKind = X86ISD::Wrapper;
13089 CodeModel::Model M = DAG.getTarget().getCodeModel();
13091 if (Subtarget->isPICStyleRIPRel() &&
13092 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13093 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13094 OpFlag = X86II::MO_GOTPCREL;
13095 WrapperKind = X86ISD::WrapperRIP;
13096 } else if (Subtarget->isPICStyleGOT()) {
13097 OpFlag = X86II::MO_GOT;
13098 } else if (Subtarget->isPICStyleStubPIC()) {
13099 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13100 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13101 OpFlag = X86II::MO_DARWIN_NONLAZY;
13104 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13107 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13109 // With PIC, the address is actually $g + Offset.
13110 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13111 !Subtarget->is64Bit()) {
13112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13113 DAG.getNode(X86ISD::GlobalBaseReg,
13114 SDLoc(), getPointerTy()),
13118 // For symbols that require a load from a stub to get the address, emit the
13120 if (isGlobalStubReference(OpFlag))
13121 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13122 MachinePointerInfo::getGOT(), false, false, false, 0);
13128 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13129 // Create the TargetBlockAddressAddress node.
13130 unsigned char OpFlags =
13131 Subtarget->ClassifyBlockAddressReference();
13132 CodeModel::Model M = DAG.getTarget().getCodeModel();
13133 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13134 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13136 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13139 if (Subtarget->isPICStyleRIPRel() &&
13140 (M == CodeModel::Small || M == CodeModel::Kernel))
13141 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13143 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13145 // With PIC, the address is actually $g + Offset.
13146 if (isGlobalRelativeToPICBase(OpFlags)) {
13147 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13148 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13156 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13157 int64_t Offset, SelectionDAG &DAG) const {
13158 // Create the TargetGlobalAddress node, folding in the constant
13159 // offset if it is legal.
13160 unsigned char OpFlags =
13161 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13162 CodeModel::Model M = DAG.getTarget().getCodeModel();
13164 if (OpFlags == X86II::MO_NO_FLAG &&
13165 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13166 // A direct static reference to a global.
13167 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13170 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13173 if (Subtarget->isPICStyleRIPRel() &&
13174 (M == CodeModel::Small || M == CodeModel::Kernel))
13175 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13177 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13179 // With PIC, the address is actually $g + Offset.
13180 if (isGlobalRelativeToPICBase(OpFlags)) {
13181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13182 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13186 // For globals that require a load from a stub to get the address, emit the
13188 if (isGlobalStubReference(OpFlags))
13189 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13190 MachinePointerInfo::getGOT(), false, false, false, 0);
13192 // If there was a non-zero offset that we didn't fold, create an explicit
13193 // addition for it.
13195 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13196 DAG.getConstant(Offset, getPointerTy()));
13202 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13203 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13204 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13205 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13209 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13210 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13211 unsigned char OperandFlags, bool LocalDynamic = false) {
13212 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13213 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13215 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13216 GA->getValueType(0),
13220 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13224 SDValue Ops[] = { Chain, TGA, *InFlag };
13225 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13227 SDValue Ops[] = { Chain, TGA };
13228 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13231 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13232 MFI->setAdjustsStack(true);
13233 MFI->setHasCalls(true);
13235 SDValue Flag = Chain.getValue(1);
13236 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13239 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13241 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13244 SDLoc dl(GA); // ? function entry point might be better
13245 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13246 DAG.getNode(X86ISD::GlobalBaseReg,
13247 SDLoc(), PtrVT), InFlag);
13248 InFlag = Chain.getValue(1);
13250 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13253 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13255 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13257 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13258 X86::RAX, X86II::MO_TLSGD);
13261 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13267 // Get the start address of the TLS block for this module.
13268 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13269 .getInfo<X86MachineFunctionInfo>();
13270 MFI->incNumLocalDynamicTLSAccesses();
13274 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13275 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13278 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13279 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13280 InFlag = Chain.getValue(1);
13281 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13282 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13285 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13289 unsigned char OperandFlags = X86II::MO_DTPOFF;
13290 unsigned WrapperKind = X86ISD::Wrapper;
13291 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13292 GA->getValueType(0),
13293 GA->getOffset(), OperandFlags);
13294 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13296 // Add x@dtpoff with the base.
13297 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13300 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13301 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13302 const EVT PtrVT, TLSModel::Model model,
13303 bool is64Bit, bool isPIC) {
13306 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13307 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13308 is64Bit ? 257 : 256));
13310 SDValue ThreadPointer =
13311 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13312 MachinePointerInfo(Ptr), false, false, false, 0);
13314 unsigned char OperandFlags = 0;
13315 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13317 unsigned WrapperKind = X86ISD::Wrapper;
13318 if (model == TLSModel::LocalExec) {
13319 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13320 } else if (model == TLSModel::InitialExec) {
13322 OperandFlags = X86II::MO_GOTTPOFF;
13323 WrapperKind = X86ISD::WrapperRIP;
13325 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13328 llvm_unreachable("Unexpected model");
13331 // emit "addl x@ntpoff,%eax" (local exec)
13332 // or "addl x@indntpoff,%eax" (initial exec)
13333 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13335 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13336 GA->getOffset(), OperandFlags);
13337 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13339 if (model == TLSModel::InitialExec) {
13340 if (isPIC && !is64Bit) {
13341 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13342 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13346 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13347 MachinePointerInfo::getGOT(), false, false, false, 0);
13350 // The address of the thread local variable is the add of the thread
13351 // pointer with the offset of the variable.
13352 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13356 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13358 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13359 const GlobalValue *GV = GA->getGlobal();
13361 if (Subtarget->isTargetELF()) {
13362 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13365 case TLSModel::GeneralDynamic:
13366 if (Subtarget->is64Bit())
13367 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13368 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13369 case TLSModel::LocalDynamic:
13370 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13371 Subtarget->is64Bit());
13372 case TLSModel::InitialExec:
13373 case TLSModel::LocalExec:
13374 return LowerToTLSExecModel(
13375 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13376 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13378 llvm_unreachable("Unknown TLS model.");
13381 if (Subtarget->isTargetDarwin()) {
13382 // Darwin only has one model of TLS. Lower to that.
13383 unsigned char OpFlag = 0;
13384 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13385 X86ISD::WrapperRIP : X86ISD::Wrapper;
13387 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13388 // global base reg.
13389 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13390 !Subtarget->is64Bit();
13392 OpFlag = X86II::MO_TLVP_PIC_BASE;
13394 OpFlag = X86II::MO_TLVP;
13396 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13397 GA->getValueType(0),
13398 GA->getOffset(), OpFlag);
13399 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13401 // With PIC32, the address is actually $g + Offset.
13403 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13404 DAG.getNode(X86ISD::GlobalBaseReg,
13405 SDLoc(), getPointerTy()),
13408 // Lowering the machine isd will make sure everything is in the right
13410 SDValue Chain = DAG.getEntryNode();
13411 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13412 SDValue Args[] = { Chain, Offset };
13413 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13415 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13416 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13417 MFI->setAdjustsStack(true);
13419 // And our return value (tls address) is in the standard call return value
13421 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13422 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13423 Chain.getValue(1));
13426 if (Subtarget->isTargetKnownWindowsMSVC() ||
13427 Subtarget->isTargetWindowsGNU()) {
13428 // Just use the implicit TLS architecture
13429 // Need to generate someting similar to:
13430 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13432 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13433 // mov rcx, qword [rdx+rcx*8]
13434 // mov eax, .tls$:tlsvar
13435 // [rax+rcx] contains the address
13436 // Windows 64bit: gs:0x58
13437 // Windows 32bit: fs:__tls_array
13440 SDValue Chain = DAG.getEntryNode();
13442 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13443 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13444 // use its literal value of 0x2C.
13445 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13446 ? Type::getInt8PtrTy(*DAG.getContext(),
13448 : Type::getInt32PtrTy(*DAG.getContext(),
13452 Subtarget->is64Bit()
13453 ? DAG.getIntPtrConstant(0x58)
13454 : (Subtarget->isTargetWindowsGNU()
13455 ? DAG.getIntPtrConstant(0x2C)
13456 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13458 SDValue ThreadPointer =
13459 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13460 MachinePointerInfo(Ptr), false, false, false, 0);
13462 // Load the _tls_index variable
13463 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13464 if (Subtarget->is64Bit())
13465 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13466 IDX, MachinePointerInfo(), MVT::i32,
13467 false, false, false, 0);
13469 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13470 false, false, false, 0);
13472 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13474 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13476 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13477 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13478 false, false, false, 0);
13480 // Get the offset of start of .tls section
13481 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13482 GA->getValueType(0),
13483 GA->getOffset(), X86II::MO_SECREL);
13484 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13486 // The address of the thread local variable is the add of the thread
13487 // pointer with the offset of the variable.
13488 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13491 llvm_unreachable("TLS not implemented for this target.");
13494 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13495 /// and take a 2 x i32 value to shift plus a shift amount.
13496 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13497 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13498 MVT VT = Op.getSimpleValueType();
13499 unsigned VTBits = VT.getSizeInBits();
13501 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13502 SDValue ShOpLo = Op.getOperand(0);
13503 SDValue ShOpHi = Op.getOperand(1);
13504 SDValue ShAmt = Op.getOperand(2);
13505 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13506 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13508 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13509 DAG.getConstant(VTBits - 1, MVT::i8));
13510 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13511 DAG.getConstant(VTBits - 1, MVT::i8))
13512 : DAG.getConstant(0, VT);
13514 SDValue Tmp2, Tmp3;
13515 if (Op.getOpcode() == ISD::SHL_PARTS) {
13516 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13517 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13519 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13520 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13523 // If the shift amount is larger or equal than the width of a part we can't
13524 // rely on the results of shld/shrd. Insert a test and select the appropriate
13525 // values for large shift amounts.
13526 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13527 DAG.getConstant(VTBits, MVT::i8));
13528 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13529 AndNode, DAG.getConstant(0, MVT::i8));
13532 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13533 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13534 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13536 if (Op.getOpcode() == ISD::SHL_PARTS) {
13537 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13538 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13540 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13541 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13544 SDValue Ops[2] = { Lo, Hi };
13545 return DAG.getMergeValues(Ops, dl);
13548 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13549 SelectionDAG &DAG) const {
13550 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13553 if (SrcVT.isVector()) {
13554 if (SrcVT.getVectorElementType() == MVT::i1) {
13555 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13556 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13557 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13558 Op.getOperand(0)));
13563 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13564 "Unknown SINT_TO_FP to lower!");
13566 // These are really Legal; return the operand so the caller accepts it as
13568 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13570 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13571 Subtarget->is64Bit()) {
13575 unsigned Size = SrcVT.getSizeInBits()/8;
13576 MachineFunction &MF = DAG.getMachineFunction();
13577 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13578 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13579 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13581 MachinePointerInfo::getFixedStack(SSFI),
13583 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13586 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13588 SelectionDAG &DAG) const {
13592 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13594 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13596 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13598 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13600 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13601 MachineMemOperand *MMO;
13603 int SSFI = FI->getIndex();
13605 DAG.getMachineFunction()
13606 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13607 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13609 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13610 StackSlot = StackSlot.getOperand(1);
13612 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13613 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13615 Tys, Ops, SrcVT, MMO);
13618 Chain = Result.getValue(1);
13619 SDValue InFlag = Result.getValue(2);
13621 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13622 // shouldn't be necessary except that RFP cannot be live across
13623 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13624 MachineFunction &MF = DAG.getMachineFunction();
13625 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13626 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13627 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13628 Tys = DAG.getVTList(MVT::Other);
13630 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13632 MachineMemOperand *MMO =
13633 DAG.getMachineFunction()
13634 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13635 MachineMemOperand::MOStore, SSFISize, SSFISize);
13637 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13638 Ops, Op.getValueType(), MMO);
13639 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13640 MachinePointerInfo::getFixedStack(SSFI),
13641 false, false, false, 0);
13647 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13648 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13649 SelectionDAG &DAG) const {
13650 // This algorithm is not obvious. Here it is what we're trying to output:
13653 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13654 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13656 haddpd %xmm0, %xmm0
13658 pshufd $0x4e, %xmm0, %xmm1
13664 LLVMContext *Context = DAG.getContext();
13666 // Build some magic constants.
13667 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13668 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13669 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13671 SmallVector<Constant*,2> CV1;
13673 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13674 APInt(64, 0x4330000000000000ULL))));
13676 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13677 APInt(64, 0x4530000000000000ULL))));
13678 Constant *C1 = ConstantVector::get(CV1);
13679 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13681 // Load the 64-bit value into an XMM register.
13682 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13684 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13685 MachinePointerInfo::getConstantPool(),
13686 false, false, false, 16);
13687 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13688 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13691 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13692 MachinePointerInfo::getConstantPool(),
13693 false, false, false, 16);
13694 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13695 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13698 if (Subtarget->hasSSE3()) {
13699 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13700 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13702 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13703 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13705 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13706 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13710 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13711 DAG.getIntPtrConstant(0));
13714 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13715 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13716 SelectionDAG &DAG) const {
13718 // FP constant to bias correct the final result.
13719 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13722 // Load the 32-bit value into an XMM register.
13723 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13726 // Zero out the upper parts of the register.
13727 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13729 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13730 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13731 DAG.getIntPtrConstant(0));
13733 // Or the load with the bias.
13734 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13735 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13736 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13737 MVT::v2f64, Load)),
13738 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13739 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13740 MVT::v2f64, Bias)));
13741 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13743 DAG.getIntPtrConstant(0));
13745 // Subtract the bias.
13746 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13748 // Handle final rounding.
13749 EVT DestVT = Op.getValueType();
13751 if (DestVT.bitsLT(MVT::f64))
13752 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13753 DAG.getIntPtrConstant(0));
13754 if (DestVT.bitsGT(MVT::f64))
13755 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13757 // Handle final rounding.
13761 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13762 const X86Subtarget &Subtarget) {
13763 // The algorithm is the following:
13764 // #ifdef __SSE4_1__
13765 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13766 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13767 // (uint4) 0x53000000, 0xaa);
13769 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13770 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13772 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13773 // return (float4) lo + fhi;
13776 SDValue V = Op->getOperand(0);
13777 EVT VecIntVT = V.getValueType();
13778 bool Is128 = VecIntVT == MVT::v4i32;
13779 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13780 // If we convert to something else than the supported type, e.g., to v4f64,
13782 if (VecFloatVT != Op->getValueType(0))
13785 unsigned NumElts = VecIntVT.getVectorNumElements();
13786 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13787 "Unsupported custom type");
13788 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13790 // In the #idef/#else code, we have in common:
13791 // - The vector of constants:
13797 // Create the splat vector for 0x4b000000.
13798 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13799 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13800 CstLow, CstLow, CstLow, CstLow};
13801 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13802 makeArrayRef(&CstLowArray[0], NumElts));
13803 // Create the splat vector for 0x53000000.
13804 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13805 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13806 CstHigh, CstHigh, CstHigh, CstHigh};
13807 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13808 makeArrayRef(&CstHighArray[0], NumElts));
13810 // Create the right shift.
13811 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13812 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13813 CstShift, CstShift, CstShift, CstShift};
13814 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13815 makeArrayRef(&CstShiftArray[0], NumElts));
13816 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13819 if (Subtarget.hasSSE41()) {
13820 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13821 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13822 SDValue VecCstLowBitcast =
13823 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13824 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13825 // Low will be bitcasted right away, so do not bother bitcasting back to its
13827 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13828 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13829 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13830 // (uint4) 0x53000000, 0xaa);
13831 SDValue VecCstHighBitcast =
13832 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13833 SDValue VecShiftBitcast =
13834 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13835 // High will be bitcasted right away, so do not bother bitcasting back to
13836 // its original type.
13837 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13838 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13840 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13841 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13842 CstMask, CstMask, CstMask);
13843 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13844 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13845 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13847 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13848 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13851 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13852 SDValue CstFAdd = DAG.getConstantFP(
13853 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13854 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13855 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13856 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13857 makeArrayRef(&CstFAddArray[0], NumElts));
13859 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13860 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13862 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13863 // return (float4) lo + fhi;
13864 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13865 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13868 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13869 SelectionDAG &DAG) const {
13870 SDValue N0 = Op.getOperand(0);
13871 MVT SVT = N0.getSimpleValueType();
13874 switch (SVT.SimpleTy) {
13876 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13881 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13882 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13883 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13887 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13889 llvm_unreachable(nullptr);
13892 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13893 SelectionDAG &DAG) const {
13894 SDValue N0 = Op.getOperand(0);
13897 if (Op.getValueType().isVector())
13898 return lowerUINT_TO_FP_vec(Op, DAG);
13900 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13901 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13902 // the optimization here.
13903 if (DAG.SignBitIsZero(N0))
13904 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13906 MVT SrcVT = N0.getSimpleValueType();
13907 MVT DstVT = Op.getSimpleValueType();
13908 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13909 return LowerUINT_TO_FP_i64(Op, DAG);
13910 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13911 return LowerUINT_TO_FP_i32(Op, DAG);
13912 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13915 // Make a 64-bit buffer, and use it to build an FILD.
13916 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13917 if (SrcVT == MVT::i32) {
13918 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13919 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13920 getPointerTy(), StackSlot, WordOff);
13921 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13922 StackSlot, MachinePointerInfo(),
13924 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13925 OffsetSlot, MachinePointerInfo(),
13927 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13931 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13932 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13933 StackSlot, MachinePointerInfo(),
13935 // For i64 source, we need to add the appropriate power of 2 if the input
13936 // was negative. This is the same as the optimization in
13937 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13938 // we must be careful to do the computation in x87 extended precision, not
13939 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13940 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13941 MachineMemOperand *MMO =
13942 DAG.getMachineFunction()
13943 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13944 MachineMemOperand::MOLoad, 8, 8);
13946 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13947 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13948 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13951 APInt FF(32, 0x5F800000ULL);
13953 // Check whether the sign bit is set.
13954 SDValue SignSet = DAG.getSetCC(dl,
13955 getSetCCResultType(*DAG.getContext(), MVT::i64),
13956 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13959 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13960 SDValue FudgePtr = DAG.getConstantPool(
13961 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13964 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13965 SDValue Zero = DAG.getIntPtrConstant(0);
13966 SDValue Four = DAG.getIntPtrConstant(4);
13967 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13969 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13971 // Load the value out, extending it from f32 to f80.
13972 // FIXME: Avoid the extend by constructing the right constant pool?
13973 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13974 FudgePtr, MachinePointerInfo::getConstantPool(),
13975 MVT::f32, false, false, false, 4);
13976 // Extend everything to 80 bits to force it to be done on x87.
13977 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13978 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13981 std::pair<SDValue,SDValue>
13982 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13983 bool IsSigned, bool IsReplace) const {
13986 EVT DstTy = Op.getValueType();
13988 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13989 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13993 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13994 DstTy.getSimpleVT() >= MVT::i16 &&
13995 "Unknown FP_TO_INT to lower!");
13997 // These are really Legal.
13998 if (DstTy == MVT::i32 &&
13999 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14000 return std::make_pair(SDValue(), SDValue());
14001 if (Subtarget->is64Bit() &&
14002 DstTy == MVT::i64 &&
14003 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14004 return std::make_pair(SDValue(), SDValue());
14006 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14007 // stack slot, or into the FTOL runtime function.
14008 MachineFunction &MF = DAG.getMachineFunction();
14009 unsigned MemSize = DstTy.getSizeInBits()/8;
14010 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14011 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14014 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14015 Opc = X86ISD::WIN_FTOL;
14017 switch (DstTy.getSimpleVT().SimpleTy) {
14018 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14019 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14020 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14021 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14024 SDValue Chain = DAG.getEntryNode();
14025 SDValue Value = Op.getOperand(0);
14026 EVT TheVT = Op.getOperand(0).getValueType();
14027 // FIXME This causes a redundant load/store if the SSE-class value is already
14028 // in memory, such as if it is on the callstack.
14029 if (isScalarFPTypeInSSEReg(TheVT)) {
14030 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14031 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14032 MachinePointerInfo::getFixedStack(SSFI),
14034 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14036 Chain, StackSlot, DAG.getValueType(TheVT)
14039 MachineMemOperand *MMO =
14040 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14041 MachineMemOperand::MOLoad, MemSize, MemSize);
14042 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14043 Chain = Value.getValue(1);
14044 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14045 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14048 MachineMemOperand *MMO =
14049 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14050 MachineMemOperand::MOStore, MemSize, MemSize);
14052 if (Opc != X86ISD::WIN_FTOL) {
14053 // Build the FP_TO_INT*_IN_MEM
14054 SDValue Ops[] = { Chain, Value, StackSlot };
14055 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14057 return std::make_pair(FIST, StackSlot);
14059 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14060 DAG.getVTList(MVT::Other, MVT::Glue),
14062 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14063 MVT::i32, ftol.getValue(1));
14064 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14065 MVT::i32, eax.getValue(2));
14066 SDValue Ops[] = { eax, edx };
14067 SDValue pair = IsReplace
14068 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14069 : DAG.getMergeValues(Ops, DL);
14070 return std::make_pair(pair, SDValue());
14074 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14075 const X86Subtarget *Subtarget) {
14076 MVT VT = Op->getSimpleValueType(0);
14077 SDValue In = Op->getOperand(0);
14078 MVT InVT = In.getSimpleValueType();
14081 // Optimize vectors in AVX mode:
14084 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14085 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14086 // Concat upper and lower parts.
14089 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14090 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14091 // Concat upper and lower parts.
14094 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14095 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14096 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14099 if (Subtarget->hasInt256())
14100 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14102 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14103 SDValue Undef = DAG.getUNDEF(InVT);
14104 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14105 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14106 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14108 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14109 VT.getVectorNumElements()/2);
14111 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14112 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14114 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14117 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14118 SelectionDAG &DAG) {
14119 MVT VT = Op->getSimpleValueType(0);
14120 SDValue In = Op->getOperand(0);
14121 MVT InVT = In.getSimpleValueType();
14123 unsigned int NumElts = VT.getVectorNumElements();
14124 if (NumElts != 8 && NumElts != 16)
14127 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14128 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14130 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14132 // Now we have only mask extension
14133 assert(InVT.getVectorElementType() == MVT::i1);
14134 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14135 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14136 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14137 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14138 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14139 MachinePointerInfo::getConstantPool(),
14140 false, false, false, Alignment);
14142 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14143 if (VT.is512BitVector())
14145 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14148 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14149 SelectionDAG &DAG) {
14150 if (Subtarget->hasFp256()) {
14151 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14159 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14160 SelectionDAG &DAG) {
14162 MVT VT = Op.getSimpleValueType();
14163 SDValue In = Op.getOperand(0);
14164 MVT SVT = In.getSimpleValueType();
14166 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14167 return LowerZERO_EXTEND_AVX512(Op, DAG);
14169 if (Subtarget->hasFp256()) {
14170 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14175 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14176 VT.getVectorNumElements() != SVT.getVectorNumElements());
14180 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14182 MVT VT = Op.getSimpleValueType();
14183 SDValue In = Op.getOperand(0);
14184 MVT InVT = In.getSimpleValueType();
14186 if (VT == MVT::i1) {
14187 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14188 "Invalid scalar TRUNCATE operation");
14189 if (InVT.getSizeInBits() >= 32)
14191 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14192 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14194 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14195 "Invalid TRUNCATE operation");
14197 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14198 if (VT.getVectorElementType().getSizeInBits() >=8)
14199 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14201 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14202 unsigned NumElts = InVT.getVectorNumElements();
14203 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14204 if (InVT.getSizeInBits() < 512) {
14205 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14206 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14210 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14211 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14212 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14213 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14214 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14215 MachinePointerInfo::getConstantPool(),
14216 false, false, false, Alignment);
14217 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14218 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14219 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14222 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14223 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14224 if (Subtarget->hasInt256()) {
14225 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14226 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14227 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14229 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14230 DAG.getIntPtrConstant(0));
14233 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14234 DAG.getIntPtrConstant(0));
14235 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14236 DAG.getIntPtrConstant(2));
14237 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14238 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14239 static const int ShufMask[] = {0, 2, 4, 6};
14240 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14243 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14244 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14245 if (Subtarget->hasInt256()) {
14246 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14248 SmallVector<SDValue,32> pshufbMask;
14249 for (unsigned i = 0; i < 2; ++i) {
14250 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14251 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14252 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14253 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14254 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14257 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14258 for (unsigned j = 0; j < 8; ++j)
14259 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14261 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14262 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14263 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14265 static const int ShufMask[] = {0, 2, -1, -1};
14266 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14268 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14269 DAG.getIntPtrConstant(0));
14270 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14273 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14274 DAG.getIntPtrConstant(0));
14276 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14277 DAG.getIntPtrConstant(4));
14279 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14280 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14282 // The PSHUFB mask:
14283 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14284 -1, -1, -1, -1, -1, -1, -1, -1};
14286 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14287 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14288 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14290 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14291 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14293 // The MOVLHPS Mask:
14294 static const int ShufMask2[] = {0, 1, 4, 5};
14295 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14296 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14299 // Handle truncation of V256 to V128 using shuffles.
14300 if (!VT.is128BitVector() || !InVT.is256BitVector())
14303 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14305 unsigned NumElems = VT.getVectorNumElements();
14306 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14308 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14309 // Prepare truncation shuffle mask
14310 for (unsigned i = 0; i != NumElems; ++i)
14311 MaskVec[i] = i * 2;
14312 SDValue V = DAG.getVectorShuffle(NVT, DL,
14313 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14314 DAG.getUNDEF(NVT), &MaskVec[0]);
14315 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14316 DAG.getIntPtrConstant(0));
14319 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14320 SelectionDAG &DAG) const {
14321 assert(!Op.getSimpleValueType().isVector());
14323 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14324 /*IsSigned=*/ true, /*IsReplace=*/ false);
14325 SDValue FIST = Vals.first, StackSlot = Vals.second;
14326 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14327 if (!FIST.getNode()) return Op;
14329 if (StackSlot.getNode())
14330 // Load the result.
14331 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14332 FIST, StackSlot, MachinePointerInfo(),
14333 false, false, false, 0);
14335 // The node is the result.
14339 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14340 SelectionDAG &DAG) const {
14341 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14342 /*IsSigned=*/ false, /*IsReplace=*/ false);
14343 SDValue FIST = Vals.first, StackSlot = Vals.second;
14344 assert(FIST.getNode() && "Unexpected failure");
14346 if (StackSlot.getNode())
14347 // Load the result.
14348 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14349 FIST, StackSlot, MachinePointerInfo(),
14350 false, false, false, 0);
14352 // The node is the result.
14356 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14358 MVT VT = Op.getSimpleValueType();
14359 SDValue In = Op.getOperand(0);
14360 MVT SVT = In.getSimpleValueType();
14362 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14364 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14365 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14366 In, DAG.getUNDEF(SVT)));
14369 /// The only differences between FABS and FNEG are the mask and the logic op.
14370 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14371 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14372 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14373 "Wrong opcode for lowering FABS or FNEG.");
14375 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14377 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14378 // into an FNABS. We'll lower the FABS after that if it is still in use.
14380 for (SDNode *User : Op->uses())
14381 if (User->getOpcode() == ISD::FNEG)
14384 SDValue Op0 = Op.getOperand(0);
14385 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14388 MVT VT = Op.getSimpleValueType();
14389 // Assume scalar op for initialization; update for vector if needed.
14390 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14391 // generate a 16-byte vector constant and logic op even for the scalar case.
14392 // Using a 16-byte mask allows folding the load of the mask with
14393 // the logic op, so it can save (~4 bytes) on code size.
14395 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14396 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14397 // decide if we should generate a 16-byte constant mask when we only need 4 or
14398 // 8 bytes for the scalar case.
14399 if (VT.isVector()) {
14400 EltVT = VT.getVectorElementType();
14401 NumElts = VT.getVectorNumElements();
14404 unsigned EltBits = EltVT.getSizeInBits();
14405 LLVMContext *Context = DAG.getContext();
14406 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14408 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14409 Constant *C = ConstantInt::get(*Context, MaskElt);
14410 C = ConstantVector::getSplat(NumElts, C);
14411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14412 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14413 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14414 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14415 MachinePointerInfo::getConstantPool(),
14416 false, false, false, Alignment);
14418 if (VT.isVector()) {
14419 // For a vector, cast operands to a vector type, perform the logic op,
14420 // and cast the result back to the original value type.
14421 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14422 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14423 SDValue Operand = IsFNABS ?
14424 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14425 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14426 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14427 return DAG.getNode(ISD::BITCAST, dl, VT,
14428 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14431 // If not vector, then scalar.
14432 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14433 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14434 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14437 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14439 LLVMContext *Context = DAG.getContext();
14440 SDValue Op0 = Op.getOperand(0);
14441 SDValue Op1 = Op.getOperand(1);
14443 MVT VT = Op.getSimpleValueType();
14444 MVT SrcVT = Op1.getSimpleValueType();
14446 // If second operand is smaller, extend it first.
14447 if (SrcVT.bitsLT(VT)) {
14448 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14451 // And if it is bigger, shrink it first.
14452 if (SrcVT.bitsGT(VT)) {
14453 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14457 // At this point the operands and the result should have the same
14458 // type, and that won't be f80 since that is not custom lowered.
14460 // First get the sign bit of second operand.
14461 SmallVector<Constant*,4> CV;
14462 if (SrcVT == MVT::f64) {
14463 const fltSemantics &Sem = APFloat::IEEEdouble;
14464 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14465 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14467 const fltSemantics &Sem = APFloat::IEEEsingle;
14468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14470 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14471 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14473 Constant *C = ConstantVector::get(CV);
14474 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14475 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14476 MachinePointerInfo::getConstantPool(),
14477 false, false, false, 16);
14478 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14480 // Shift sign bit right or left if the two operands have different types.
14481 if (SrcVT.bitsGT(VT)) {
14482 // Op0 is MVT::f32, Op1 is MVT::f64.
14483 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14484 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14485 DAG.getConstant(32, MVT::i32));
14486 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14487 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14488 DAG.getIntPtrConstant(0));
14491 // Clear first operand sign bit.
14493 if (VT == MVT::f64) {
14494 const fltSemantics &Sem = APFloat::IEEEdouble;
14495 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14496 APInt(64, ~(1ULL << 63)))));
14497 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14499 const fltSemantics &Sem = APFloat::IEEEsingle;
14500 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14501 APInt(32, ~(1U << 31)))));
14502 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14503 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14504 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14506 C = ConstantVector::get(CV);
14507 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14508 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14509 MachinePointerInfo::getConstantPool(),
14510 false, false, false, 16);
14511 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14513 // Or the value with the sign bit.
14514 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14517 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14518 SDValue N0 = Op.getOperand(0);
14520 MVT VT = Op.getSimpleValueType();
14522 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14523 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14524 DAG.getConstant(1, VT));
14525 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14528 // Check whether an OR'd tree is PTEST-able.
14529 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14530 SelectionDAG &DAG) {
14531 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14533 if (!Subtarget->hasSSE41())
14536 if (!Op->hasOneUse())
14539 SDNode *N = Op.getNode();
14542 SmallVector<SDValue, 8> Opnds;
14543 DenseMap<SDValue, unsigned> VecInMap;
14544 SmallVector<SDValue, 8> VecIns;
14545 EVT VT = MVT::Other;
14547 // Recognize a special case where a vector is casted into wide integer to
14549 Opnds.push_back(N->getOperand(0));
14550 Opnds.push_back(N->getOperand(1));
14552 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14553 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14554 // BFS traverse all OR'd operands.
14555 if (I->getOpcode() == ISD::OR) {
14556 Opnds.push_back(I->getOperand(0));
14557 Opnds.push_back(I->getOperand(1));
14558 // Re-evaluate the number of nodes to be traversed.
14559 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14563 // Quit if a non-EXTRACT_VECTOR_ELT
14564 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14567 // Quit if without a constant index.
14568 SDValue Idx = I->getOperand(1);
14569 if (!isa<ConstantSDNode>(Idx))
14572 SDValue ExtractedFromVec = I->getOperand(0);
14573 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14574 if (M == VecInMap.end()) {
14575 VT = ExtractedFromVec.getValueType();
14576 // Quit if not 128/256-bit vector.
14577 if (!VT.is128BitVector() && !VT.is256BitVector())
14579 // Quit if not the same type.
14580 if (VecInMap.begin() != VecInMap.end() &&
14581 VT != VecInMap.begin()->first.getValueType())
14583 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14584 VecIns.push_back(ExtractedFromVec);
14586 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14589 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14590 "Not extracted from 128-/256-bit vector.");
14592 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14594 for (DenseMap<SDValue, unsigned>::const_iterator
14595 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14596 // Quit if not all elements are used.
14597 if (I->second != FullMask)
14601 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14603 // Cast all vectors into TestVT for PTEST.
14604 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14605 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14607 // If more than one full vectors are evaluated, OR them first before PTEST.
14608 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14609 // Each iteration will OR 2 nodes and append the result until there is only
14610 // 1 node left, i.e. the final OR'd value of all vectors.
14611 SDValue LHS = VecIns[Slot];
14612 SDValue RHS = VecIns[Slot + 1];
14613 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14616 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14617 VecIns.back(), VecIns.back());
14620 /// \brief return true if \c Op has a use that doesn't just read flags.
14621 static bool hasNonFlagsUse(SDValue Op) {
14622 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14624 SDNode *User = *UI;
14625 unsigned UOpNo = UI.getOperandNo();
14626 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14627 // Look pass truncate.
14628 UOpNo = User->use_begin().getOperandNo();
14629 User = *User->use_begin();
14632 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14633 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14639 /// Emit nodes that will be selected as "test Op0,Op0", or something
14641 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14642 SelectionDAG &DAG) const {
14643 if (Op.getValueType() == MVT::i1)
14644 // KORTEST instruction should be selected
14645 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14646 DAG.getConstant(0, Op.getValueType()));
14648 // CF and OF aren't always set the way we want. Determine which
14649 // of these we need.
14650 bool NeedCF = false;
14651 bool NeedOF = false;
14654 case X86::COND_A: case X86::COND_AE:
14655 case X86::COND_B: case X86::COND_BE:
14658 case X86::COND_G: case X86::COND_GE:
14659 case X86::COND_L: case X86::COND_LE:
14660 case X86::COND_O: case X86::COND_NO: {
14661 // Check if we really need to set the
14662 // Overflow flag. If NoSignedWrap is present
14663 // that is not actually needed.
14664 switch (Op->getOpcode()) {
14669 const BinaryWithFlagsSDNode *BinNode =
14670 cast<BinaryWithFlagsSDNode>(Op.getNode());
14671 if (BinNode->hasNoSignedWrap())
14681 // See if we can use the EFLAGS value from the operand instead of
14682 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14683 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14684 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14685 // Emit a CMP with 0, which is the TEST pattern.
14686 //if (Op.getValueType() == MVT::i1)
14687 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14688 // DAG.getConstant(0, MVT::i1));
14689 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14690 DAG.getConstant(0, Op.getValueType()));
14692 unsigned Opcode = 0;
14693 unsigned NumOperands = 0;
14695 // Truncate operations may prevent the merge of the SETCC instruction
14696 // and the arithmetic instruction before it. Attempt to truncate the operands
14697 // of the arithmetic instruction and use a reduced bit-width instruction.
14698 bool NeedTruncation = false;
14699 SDValue ArithOp = Op;
14700 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14701 SDValue Arith = Op->getOperand(0);
14702 // Both the trunc and the arithmetic op need to have one user each.
14703 if (Arith->hasOneUse())
14704 switch (Arith.getOpcode()) {
14711 NeedTruncation = true;
14717 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14718 // which may be the result of a CAST. We use the variable 'Op', which is the
14719 // non-casted variable when we check for possible users.
14720 switch (ArithOp.getOpcode()) {
14722 // Due to an isel shortcoming, be conservative if this add is likely to be
14723 // selected as part of a load-modify-store instruction. When the root node
14724 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14725 // uses of other nodes in the match, such as the ADD in this case. This
14726 // leads to the ADD being left around and reselected, with the result being
14727 // two adds in the output. Alas, even if none our users are stores, that
14728 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14729 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14730 // climbing the DAG back to the root, and it doesn't seem to be worth the
14732 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14733 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14734 if (UI->getOpcode() != ISD::CopyToReg &&
14735 UI->getOpcode() != ISD::SETCC &&
14736 UI->getOpcode() != ISD::STORE)
14739 if (ConstantSDNode *C =
14740 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14741 // An add of one will be selected as an INC.
14742 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14743 Opcode = X86ISD::INC;
14748 // An add of negative one (subtract of one) will be selected as a DEC.
14749 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14750 Opcode = X86ISD::DEC;
14756 // Otherwise use a regular EFLAGS-setting add.
14757 Opcode = X86ISD::ADD;
14762 // If we have a constant logical shift that's only used in a comparison
14763 // against zero turn it into an equivalent AND. This allows turning it into
14764 // a TEST instruction later.
14765 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14766 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14767 EVT VT = Op.getValueType();
14768 unsigned BitWidth = VT.getSizeInBits();
14769 unsigned ShAmt = Op->getConstantOperandVal(1);
14770 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14772 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14773 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14774 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14775 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14777 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14778 DAG.getConstant(Mask, VT));
14779 DAG.ReplaceAllUsesWith(Op, New);
14785 // If the primary and result isn't used, don't bother using X86ISD::AND,
14786 // because a TEST instruction will be better.
14787 if (!hasNonFlagsUse(Op))
14793 // Due to the ISEL shortcoming noted above, be conservative if this op is
14794 // likely to be selected as part of a load-modify-store instruction.
14795 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14796 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14797 if (UI->getOpcode() == ISD::STORE)
14800 // Otherwise use a regular EFLAGS-setting instruction.
14801 switch (ArithOp.getOpcode()) {
14802 default: llvm_unreachable("unexpected operator!");
14803 case ISD::SUB: Opcode = X86ISD::SUB; break;
14804 case ISD::XOR: Opcode = X86ISD::XOR; break;
14805 case ISD::AND: Opcode = X86ISD::AND; break;
14807 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14808 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14809 if (EFLAGS.getNode())
14812 Opcode = X86ISD::OR;
14826 return SDValue(Op.getNode(), 1);
14832 // If we found that truncation is beneficial, perform the truncation and
14834 if (NeedTruncation) {
14835 EVT VT = Op.getValueType();
14836 SDValue WideVal = Op->getOperand(0);
14837 EVT WideVT = WideVal.getValueType();
14838 unsigned ConvertedOp = 0;
14839 // Use a target machine opcode to prevent further DAGCombine
14840 // optimizations that may separate the arithmetic operations
14841 // from the setcc node.
14842 switch (WideVal.getOpcode()) {
14844 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14845 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14846 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14847 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14848 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14853 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14854 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14855 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14856 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14862 // Emit a CMP with 0, which is the TEST pattern.
14863 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14864 DAG.getConstant(0, Op.getValueType()));
14866 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14867 SmallVector<SDValue, 4> Ops;
14868 for (unsigned i = 0; i != NumOperands; ++i)
14869 Ops.push_back(Op.getOperand(i));
14871 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14872 DAG.ReplaceAllUsesWith(Op, New);
14873 return SDValue(New.getNode(), 1);
14876 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14878 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14879 SDLoc dl, SelectionDAG &DAG) const {
14880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14881 if (C->getAPIntValue() == 0)
14882 return EmitTest(Op0, X86CC, dl, DAG);
14884 if (Op0.getValueType() == MVT::i1)
14885 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14888 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14889 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14890 // Do the comparison at i32 if it's smaller, besides the Atom case.
14891 // This avoids subregister aliasing issues. Keep the smaller reference
14892 // if we're optimizing for size, however, as that'll allow better folding
14893 // of memory operations.
14894 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14895 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14896 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14897 !Subtarget->isAtom()) {
14898 unsigned ExtendOp =
14899 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14900 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14901 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14903 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14904 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14905 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14907 return SDValue(Sub.getNode(), 1);
14909 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14912 /// Convert a comparison if required by the subtarget.
14913 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14914 SelectionDAG &DAG) const {
14915 // If the subtarget does not support the FUCOMI instruction, floating-point
14916 // comparisons have to be converted.
14917 if (Subtarget->hasCMov() ||
14918 Cmp.getOpcode() != X86ISD::CMP ||
14919 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14920 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14923 // The instruction selector will select an FUCOM instruction instead of
14924 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14925 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14926 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14928 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14929 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14930 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14931 DAG.getConstant(8, MVT::i8));
14932 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14933 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14936 /// The minimum architected relative accuracy is 2^-12. We need one
14937 /// Newton-Raphson step to have a good float result (24 bits of precision).
14938 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14939 DAGCombinerInfo &DCI,
14940 unsigned &RefinementSteps,
14941 bool &UseOneConstNR) const {
14942 // FIXME: We should use instruction latency models to calculate the cost of
14943 // each potential sequence, but this is very hard to do reliably because
14944 // at least Intel's Core* chips have variable timing based on the number of
14945 // significant digits in the divisor and/or sqrt operand.
14946 if (!Subtarget->useSqrtEst())
14949 EVT VT = Op.getValueType();
14951 // SSE1 has rsqrtss and rsqrtps.
14952 // TODO: Add support for AVX512 (v16f32).
14953 // It is likely not profitable to do this for f64 because a double-precision
14954 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14955 // instructions: convert to single, rsqrtss, convert back to double, refine
14956 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14957 // along with FMA, this could be a throughput win.
14958 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14959 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14960 RefinementSteps = 1;
14961 UseOneConstNR = false;
14962 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14967 /// The minimum architected relative accuracy is 2^-12. We need one
14968 /// Newton-Raphson step to have a good float result (24 bits of precision).
14969 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14970 DAGCombinerInfo &DCI,
14971 unsigned &RefinementSteps) const {
14972 // FIXME: We should use instruction latency models to calculate the cost of
14973 // each potential sequence, but this is very hard to do reliably because
14974 // at least Intel's Core* chips have variable timing based on the number of
14975 // significant digits in the divisor.
14976 if (!Subtarget->useReciprocalEst())
14979 EVT VT = Op.getValueType();
14981 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14982 // TODO: Add support for AVX512 (v16f32).
14983 // It is likely not profitable to do this for f64 because a double-precision
14984 // reciprocal estimate with refinement on x86 prior to FMA requires
14985 // 15 instructions: convert to single, rcpss, convert back to double, refine
14986 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14987 // along with FMA, this could be a throughput win.
14988 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14989 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14990 RefinementSteps = ReciprocalEstimateRefinementSteps;
14991 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14996 static bool isAllOnes(SDValue V) {
14997 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14998 return C && C->isAllOnesValue();
15001 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15002 /// if it's possible.
15003 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15004 SDLoc dl, SelectionDAG &DAG) const {
15005 SDValue Op0 = And.getOperand(0);
15006 SDValue Op1 = And.getOperand(1);
15007 if (Op0.getOpcode() == ISD::TRUNCATE)
15008 Op0 = Op0.getOperand(0);
15009 if (Op1.getOpcode() == ISD::TRUNCATE)
15010 Op1 = Op1.getOperand(0);
15013 if (Op1.getOpcode() == ISD::SHL)
15014 std::swap(Op0, Op1);
15015 if (Op0.getOpcode() == ISD::SHL) {
15016 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15017 if (And00C->getZExtValue() == 1) {
15018 // If we looked past a truncate, check that it's only truncating away
15020 unsigned BitWidth = Op0.getValueSizeInBits();
15021 unsigned AndBitWidth = And.getValueSizeInBits();
15022 if (BitWidth > AndBitWidth) {
15024 DAG.computeKnownBits(Op0, Zeros, Ones);
15025 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15029 RHS = Op0.getOperand(1);
15031 } else if (Op1.getOpcode() == ISD::Constant) {
15032 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15033 uint64_t AndRHSVal = AndRHS->getZExtValue();
15034 SDValue AndLHS = Op0;
15036 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15037 LHS = AndLHS.getOperand(0);
15038 RHS = AndLHS.getOperand(1);
15041 // Use BT if the immediate can't be encoded in a TEST instruction.
15042 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15044 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15048 if (LHS.getNode()) {
15049 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15050 // instruction. Since the shift amount is in-range-or-undefined, we know
15051 // that doing a bittest on the i32 value is ok. We extend to i32 because
15052 // the encoding for the i16 version is larger than the i32 version.
15053 // Also promote i16 to i32 for performance / code size reason.
15054 if (LHS.getValueType() == MVT::i8 ||
15055 LHS.getValueType() == MVT::i16)
15056 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15058 // If the operand types disagree, extend the shift amount to match. Since
15059 // BT ignores high bits (like shifts) we can use anyextend.
15060 if (LHS.getValueType() != RHS.getValueType())
15061 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15063 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15064 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15065 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15066 DAG.getConstant(Cond, MVT::i8), BT);
15072 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15074 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15079 // SSE Condition code mapping:
15088 switch (SetCCOpcode) {
15089 default: llvm_unreachable("Unexpected SETCC condition");
15091 case ISD::SETEQ: SSECC = 0; break;
15093 case ISD::SETGT: Swap = true; // Fallthrough
15095 case ISD::SETOLT: SSECC = 1; break;
15097 case ISD::SETGE: Swap = true; // Fallthrough
15099 case ISD::SETOLE: SSECC = 2; break;
15100 case ISD::SETUO: SSECC = 3; break;
15102 case ISD::SETNE: SSECC = 4; break;
15103 case ISD::SETULE: Swap = true; // Fallthrough
15104 case ISD::SETUGE: SSECC = 5; break;
15105 case ISD::SETULT: Swap = true; // Fallthrough
15106 case ISD::SETUGT: SSECC = 6; break;
15107 case ISD::SETO: SSECC = 7; break;
15109 case ISD::SETONE: SSECC = 8; break;
15112 std::swap(Op0, Op1);
15117 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15118 // ones, and then concatenate the result back.
15119 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15120 MVT VT = Op.getSimpleValueType();
15122 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15123 "Unsupported value type for operation");
15125 unsigned NumElems = VT.getVectorNumElements();
15127 SDValue CC = Op.getOperand(2);
15129 // Extract the LHS vectors
15130 SDValue LHS = Op.getOperand(0);
15131 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15132 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15134 // Extract the RHS vectors
15135 SDValue RHS = Op.getOperand(1);
15136 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15137 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15139 // Issue the operation on the smaller types and concatenate the result back
15140 MVT EltVT = VT.getVectorElementType();
15141 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15142 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15143 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15144 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15147 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15148 const X86Subtarget *Subtarget) {
15149 SDValue Op0 = Op.getOperand(0);
15150 SDValue Op1 = Op.getOperand(1);
15151 SDValue CC = Op.getOperand(2);
15152 MVT VT = Op.getSimpleValueType();
15155 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15156 Op.getValueType().getScalarType() == MVT::i1 &&
15157 "Cannot set masked compare for this operation");
15159 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15161 bool Unsigned = false;
15164 switch (SetCCOpcode) {
15165 default: llvm_unreachable("Unexpected SETCC condition");
15166 case ISD::SETNE: SSECC = 4; break;
15167 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15168 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15169 case ISD::SETLT: Swap = true; //fall-through
15170 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15171 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15172 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15173 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15174 case ISD::SETULE: Unsigned = true; //fall-through
15175 case ISD::SETLE: SSECC = 2; break;
15179 std::swap(Op0, Op1);
15181 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15182 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15183 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15184 DAG.getConstant(SSECC, MVT::i8));
15187 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15188 /// operand \p Op1. If non-trivial (for example because it's not constant)
15189 /// return an empty value.
15190 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15192 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15196 MVT VT = Op1.getSimpleValueType();
15197 MVT EVT = VT.getVectorElementType();
15198 unsigned n = VT.getVectorNumElements();
15199 SmallVector<SDValue, 8> ULTOp1;
15201 for (unsigned i = 0; i < n; ++i) {
15202 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15203 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15206 // Avoid underflow.
15207 APInt Val = Elt->getAPIntValue();
15211 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15214 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15217 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15218 SelectionDAG &DAG) {
15219 SDValue Op0 = Op.getOperand(0);
15220 SDValue Op1 = Op.getOperand(1);
15221 SDValue CC = Op.getOperand(2);
15222 MVT VT = Op.getSimpleValueType();
15223 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15224 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15229 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15230 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15233 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15234 unsigned Opc = X86ISD::CMPP;
15235 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15236 assert(VT.getVectorNumElements() <= 16);
15237 Opc = X86ISD::CMPM;
15239 // In the two special cases we can't handle, emit two comparisons.
15242 unsigned CombineOpc;
15243 if (SetCCOpcode == ISD::SETUEQ) {
15244 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15246 assert(SetCCOpcode == ISD::SETONE);
15247 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15250 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15251 DAG.getConstant(CC0, MVT::i8));
15252 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15253 DAG.getConstant(CC1, MVT::i8));
15254 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15256 // Handle all other FP comparisons here.
15257 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15258 DAG.getConstant(SSECC, MVT::i8));
15261 // Break 256-bit integer vector compare into smaller ones.
15262 if (VT.is256BitVector() && !Subtarget->hasInt256())
15263 return Lower256IntVSETCC(Op, DAG);
15265 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15266 EVT OpVT = Op1.getValueType();
15267 if (Subtarget->hasAVX512()) {
15268 if (Op1.getValueType().is512BitVector() ||
15269 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15270 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15271 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15273 // In AVX-512 architecture setcc returns mask with i1 elements,
15274 // But there is no compare instruction for i8 and i16 elements in KNL.
15275 // We are not talking about 512-bit operands in this case, these
15276 // types are illegal.
15278 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15279 OpVT.getVectorElementType().getSizeInBits() >= 8))
15280 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15281 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15284 // We are handling one of the integer comparisons here. Since SSE only has
15285 // GT and EQ comparisons for integer, swapping operands and multiple
15286 // operations may be required for some comparisons.
15288 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15289 bool Subus = false;
15291 switch (SetCCOpcode) {
15292 default: llvm_unreachable("Unexpected SETCC condition");
15293 case ISD::SETNE: Invert = true;
15294 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15295 case ISD::SETLT: Swap = true;
15296 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15297 case ISD::SETGE: Swap = true;
15298 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15299 Invert = true; break;
15300 case ISD::SETULT: Swap = true;
15301 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15302 FlipSigns = true; break;
15303 case ISD::SETUGE: Swap = true;
15304 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15305 FlipSigns = true; Invert = true; break;
15308 // Special case: Use min/max operations for SETULE/SETUGE
15309 MVT VET = VT.getVectorElementType();
15311 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15312 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15315 switch (SetCCOpcode) {
15317 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15318 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15321 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15324 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15325 if (!MinMax && hasSubus) {
15326 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15328 // t = psubus Op0, Op1
15329 // pcmpeq t, <0..0>
15330 switch (SetCCOpcode) {
15332 case ISD::SETULT: {
15333 // If the comparison is against a constant we can turn this into a
15334 // setule. With psubus, setule does not require a swap. This is
15335 // beneficial because the constant in the register is no longer
15336 // destructed as the destination so it can be hoisted out of a loop.
15337 // Only do this pre-AVX since vpcmp* is no longer destructive.
15338 if (Subtarget->hasAVX())
15340 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15341 if (ULEOp1.getNode()) {
15343 Subus = true; Invert = false; Swap = false;
15347 // Psubus is better than flip-sign because it requires no inversion.
15348 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15349 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15353 Opc = X86ISD::SUBUS;
15359 std::swap(Op0, Op1);
15361 // Check that the operation in question is available (most are plain SSE2,
15362 // but PCMPGTQ and PCMPEQQ have different requirements).
15363 if (VT == MVT::v2i64) {
15364 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15365 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15367 // First cast everything to the right type.
15368 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15369 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15371 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15372 // bits of the inputs before performing those operations. The lower
15373 // compare is always unsigned.
15376 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15378 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15379 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15380 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15381 Sign, Zero, Sign, Zero);
15383 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15384 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15386 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15387 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15388 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15390 // Create masks for only the low parts/high parts of the 64 bit integers.
15391 static const int MaskHi[] = { 1, 1, 3, 3 };
15392 static const int MaskLo[] = { 0, 0, 2, 2 };
15393 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15394 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15395 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15397 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15398 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15401 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15403 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15406 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15407 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15408 // pcmpeqd + pshufd + pand.
15409 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15411 // First cast everything to the right type.
15412 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15413 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15416 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15418 // Make sure the lower and upper halves are both all-ones.
15419 static const int Mask[] = { 1, 0, 3, 2 };
15420 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15421 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15424 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15426 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15430 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15431 // bits of the inputs before performing those operations.
15433 EVT EltVT = VT.getVectorElementType();
15434 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15435 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15436 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15439 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15441 // If the logical-not of the result is required, perform that now.
15443 Result = DAG.getNOT(dl, Result, VT);
15446 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15449 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15450 getZeroVector(VT, Subtarget, DAG, dl));
15455 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15457 MVT VT = Op.getSimpleValueType();
15459 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15461 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15462 && "SetCC type must be 8-bit or 1-bit integer");
15463 SDValue Op0 = Op.getOperand(0);
15464 SDValue Op1 = Op.getOperand(1);
15466 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15468 // Optimize to BT if possible.
15469 // Lower (X & (1 << N)) == 0 to BT(X, N).
15470 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15471 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15472 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15473 Op1.getOpcode() == ISD::Constant &&
15474 cast<ConstantSDNode>(Op1)->isNullValue() &&
15475 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15476 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15477 if (NewSetCC.getNode())
15481 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15483 if (Op1.getOpcode() == ISD::Constant &&
15484 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15485 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15486 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15488 // If the input is a setcc, then reuse the input setcc or use a new one with
15489 // the inverted condition.
15490 if (Op0.getOpcode() == X86ISD::SETCC) {
15491 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15492 bool Invert = (CC == ISD::SETNE) ^
15493 cast<ConstantSDNode>(Op1)->isNullValue();
15497 CCode = X86::GetOppositeBranchCondition(CCode);
15498 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15499 DAG.getConstant(CCode, MVT::i8),
15500 Op0.getOperand(1));
15502 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15506 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15507 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15508 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15510 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15511 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15514 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15515 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15516 if (X86CC == X86::COND_INVALID)
15519 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15520 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15521 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15522 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15524 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15528 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15529 static bool isX86LogicalCmp(SDValue Op) {
15530 unsigned Opc = Op.getNode()->getOpcode();
15531 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15532 Opc == X86ISD::SAHF)
15534 if (Op.getResNo() == 1 &&
15535 (Opc == X86ISD::ADD ||
15536 Opc == X86ISD::SUB ||
15537 Opc == X86ISD::ADC ||
15538 Opc == X86ISD::SBB ||
15539 Opc == X86ISD::SMUL ||
15540 Opc == X86ISD::UMUL ||
15541 Opc == X86ISD::INC ||
15542 Opc == X86ISD::DEC ||
15543 Opc == X86ISD::OR ||
15544 Opc == X86ISD::XOR ||
15545 Opc == X86ISD::AND))
15548 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15554 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15555 if (V.getOpcode() != ISD::TRUNCATE)
15558 SDValue VOp0 = V.getOperand(0);
15559 unsigned InBits = VOp0.getValueSizeInBits();
15560 unsigned Bits = V.getValueSizeInBits();
15561 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15564 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15565 bool addTest = true;
15566 SDValue Cond = Op.getOperand(0);
15567 SDValue Op1 = Op.getOperand(1);
15568 SDValue Op2 = Op.getOperand(2);
15570 EVT VT = Op1.getValueType();
15573 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15574 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15575 // sequence later on.
15576 if (Cond.getOpcode() == ISD::SETCC &&
15577 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15578 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15579 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15580 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15581 int SSECC = translateX86FSETCC(
15582 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15585 if (Subtarget->hasAVX512()) {
15586 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15587 DAG.getConstant(SSECC, MVT::i8));
15588 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15590 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15591 DAG.getConstant(SSECC, MVT::i8));
15592 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15593 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15594 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15598 if (Cond.getOpcode() == ISD::SETCC) {
15599 SDValue NewCond = LowerSETCC(Cond, DAG);
15600 if (NewCond.getNode())
15604 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15605 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15606 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15607 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15608 if (Cond.getOpcode() == X86ISD::SETCC &&
15609 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15610 isZero(Cond.getOperand(1).getOperand(1))) {
15611 SDValue Cmp = Cond.getOperand(1);
15613 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15615 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15616 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15617 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15619 SDValue CmpOp0 = Cmp.getOperand(0);
15620 // Apply further optimizations for special cases
15621 // (select (x != 0), -1, 0) -> neg & sbb
15622 // (select (x == 0), 0, -1) -> neg & sbb
15623 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15624 if (YC->isNullValue() &&
15625 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15626 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15627 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15628 DAG.getConstant(0, CmpOp0.getValueType()),
15630 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15631 DAG.getConstant(X86::COND_B, MVT::i8),
15632 SDValue(Neg.getNode(), 1));
15636 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15637 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15638 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15640 SDValue Res = // Res = 0 or -1.
15641 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15642 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15644 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15645 Res = DAG.getNOT(DL, Res, Res.getValueType());
15647 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15648 if (!N2C || !N2C->isNullValue())
15649 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15654 // Look past (and (setcc_carry (cmp ...)), 1).
15655 if (Cond.getOpcode() == ISD::AND &&
15656 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15657 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15658 if (C && C->getAPIntValue() == 1)
15659 Cond = Cond.getOperand(0);
15662 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15663 // setting operand in place of the X86ISD::SETCC.
15664 unsigned CondOpcode = Cond.getOpcode();
15665 if (CondOpcode == X86ISD::SETCC ||
15666 CondOpcode == X86ISD::SETCC_CARRY) {
15667 CC = Cond.getOperand(0);
15669 SDValue Cmp = Cond.getOperand(1);
15670 unsigned Opc = Cmp.getOpcode();
15671 MVT VT = Op.getSimpleValueType();
15673 bool IllegalFPCMov = false;
15674 if (VT.isFloatingPoint() && !VT.isVector() &&
15675 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15676 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15678 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15679 Opc == X86ISD::BT) { // FIXME
15683 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15684 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15685 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15686 Cond.getOperand(0).getValueType() != MVT::i8)) {
15687 SDValue LHS = Cond.getOperand(0);
15688 SDValue RHS = Cond.getOperand(1);
15689 unsigned X86Opcode;
15692 switch (CondOpcode) {
15693 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15694 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15695 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15696 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15697 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15698 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15699 default: llvm_unreachable("unexpected overflowing operator");
15701 if (CondOpcode == ISD::UMULO)
15702 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15705 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15707 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15709 if (CondOpcode == ISD::UMULO)
15710 Cond = X86Op.getValue(2);
15712 Cond = X86Op.getValue(1);
15714 CC = DAG.getConstant(X86Cond, MVT::i8);
15719 // Look pass the truncate if the high bits are known zero.
15720 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15721 Cond = Cond.getOperand(0);
15723 // We know the result of AND is compared against zero. Try to match
15725 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15726 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15727 if (NewSetCC.getNode()) {
15728 CC = NewSetCC.getOperand(0);
15729 Cond = NewSetCC.getOperand(1);
15736 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15737 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15740 // a < b ? -1 : 0 -> RES = ~setcc_carry
15741 // a < b ? 0 : -1 -> RES = setcc_carry
15742 // a >= b ? -1 : 0 -> RES = setcc_carry
15743 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15744 if (Cond.getOpcode() == X86ISD::SUB) {
15745 Cond = ConvertCmpIfNecessary(Cond, DAG);
15746 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15748 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15749 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15750 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15751 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15752 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15753 return DAG.getNOT(DL, Res, Res.getValueType());
15758 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15759 // widen the cmov and push the truncate through. This avoids introducing a new
15760 // branch during isel and doesn't add any extensions.
15761 if (Op.getValueType() == MVT::i8 &&
15762 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15763 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15764 if (T1.getValueType() == T2.getValueType() &&
15765 // Blacklist CopyFromReg to avoid partial register stalls.
15766 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15767 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15768 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15769 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15773 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15774 // condition is true.
15775 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15776 SDValue Ops[] = { Op2, Op1, CC, Cond };
15777 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15780 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15781 SelectionDAG &DAG) {
15782 MVT VT = Op->getSimpleValueType(0);
15783 SDValue In = Op->getOperand(0);
15784 MVT InVT = In.getSimpleValueType();
15785 MVT VTElt = VT.getVectorElementType();
15786 MVT InVTElt = InVT.getVectorElementType();
15790 if ((InVTElt == MVT::i1) &&
15791 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15792 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15794 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15795 VTElt.getSizeInBits() <= 16)) ||
15797 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15798 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15800 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15801 VTElt.getSizeInBits() >= 32))))
15802 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15804 unsigned int NumElts = VT.getVectorNumElements();
15806 if (NumElts != 8 && NumElts != 16)
15809 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15810 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15811 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15812 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15815 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15816 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15818 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15819 Constant *C = ConstantInt::get(*DAG.getContext(),
15820 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15822 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15823 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15824 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15825 MachinePointerInfo::getConstantPool(),
15826 false, false, false, Alignment);
15827 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15828 if (VT.is512BitVector())
15830 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15833 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15834 SelectionDAG &DAG) {
15835 MVT VT = Op->getSimpleValueType(0);
15836 SDValue In = Op->getOperand(0);
15837 MVT InVT = In.getSimpleValueType();
15840 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15841 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15843 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15844 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15845 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15848 if (Subtarget->hasInt256())
15849 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15851 // Optimize vectors in AVX mode
15852 // Sign extend v8i16 to v8i32 and
15855 // Divide input vector into two parts
15856 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15857 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15858 // concat the vectors to original VT
15860 unsigned NumElems = InVT.getVectorNumElements();
15861 SDValue Undef = DAG.getUNDEF(InVT);
15863 SmallVector<int,8> ShufMask1(NumElems, -1);
15864 for (unsigned i = 0; i != NumElems/2; ++i)
15867 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15869 SmallVector<int,8> ShufMask2(NumElems, -1);
15870 for (unsigned i = 0; i != NumElems/2; ++i)
15871 ShufMask2[i] = i + NumElems/2;
15873 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15875 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15876 VT.getVectorNumElements()/2);
15878 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15879 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15881 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15884 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15885 // may emit an illegal shuffle but the expansion is still better than scalar
15886 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15887 // we'll emit a shuffle and a arithmetic shift.
15888 // TODO: It is possible to support ZExt by zeroing the undef values during
15889 // the shuffle phase or after the shuffle.
15890 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15891 SelectionDAG &DAG) {
15892 MVT RegVT = Op.getSimpleValueType();
15893 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15894 assert(RegVT.isInteger() &&
15895 "We only custom lower integer vector sext loads.");
15897 // Nothing useful we can do without SSE2 shuffles.
15898 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15900 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15902 EVT MemVT = Ld->getMemoryVT();
15903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15904 unsigned RegSz = RegVT.getSizeInBits();
15906 ISD::LoadExtType Ext = Ld->getExtensionType();
15908 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15909 && "Only anyext and sext are currently implemented.");
15910 assert(MemVT != RegVT && "Cannot extend to the same type");
15911 assert(MemVT.isVector() && "Must load a vector from memory");
15913 unsigned NumElems = RegVT.getVectorNumElements();
15914 unsigned MemSz = MemVT.getSizeInBits();
15915 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15917 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15918 // The only way in which we have a legal 256-bit vector result but not the
15919 // integer 256-bit operations needed to directly lower a sextload is if we
15920 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15921 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15922 // correctly legalized. We do this late to allow the canonical form of
15923 // sextload to persist throughout the rest of the DAG combiner -- it wants
15924 // to fold together any extensions it can, and so will fuse a sign_extend
15925 // of an sextload into a sextload targeting a wider value.
15927 if (MemSz == 128) {
15928 // Just switch this to a normal load.
15929 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15930 "it must be a legal 128-bit vector "
15932 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15933 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15934 Ld->isInvariant(), Ld->getAlignment());
15936 assert(MemSz < 128 &&
15937 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15938 // Do an sext load to a 128-bit vector type. We want to use the same
15939 // number of elements, but elements half as wide. This will end up being
15940 // recursively lowered by this routine, but will succeed as we definitely
15941 // have all the necessary features if we're using AVX1.
15943 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15944 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15946 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15947 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15948 Ld->isNonTemporal(), Ld->isInvariant(),
15949 Ld->getAlignment());
15952 // Replace chain users with the new chain.
15953 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15954 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15956 // Finally, do a normal sign-extend to the desired register.
15957 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15960 // All sizes must be a power of two.
15961 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15962 "Non-power-of-two elements are not custom lowered!");
15964 // Attempt to load the original value using scalar loads.
15965 // Find the largest scalar type that divides the total loaded size.
15966 MVT SclrLoadTy = MVT::i8;
15967 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15968 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15969 MVT Tp = (MVT::SimpleValueType)tp;
15970 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15975 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15976 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15978 SclrLoadTy = MVT::f64;
15980 // Calculate the number of scalar loads that we need to perform
15981 // in order to load our vector from memory.
15982 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15984 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15985 "Can only lower sext loads with a single scalar load!");
15987 unsigned loadRegZize = RegSz;
15988 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15991 // Represent our vector as a sequence of elements which are the
15992 // largest scalar that we can load.
15993 EVT LoadUnitVecVT = EVT::getVectorVT(
15994 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15996 // Represent the data using the same element type that is stored in
15997 // memory. In practice, we ''widen'' MemVT.
15999 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16000 loadRegZize / MemVT.getScalarType().getSizeInBits());
16002 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16003 "Invalid vector type");
16005 // We can't shuffle using an illegal type.
16006 assert(TLI.isTypeLegal(WideVecVT) &&
16007 "We only lower types that form legal widened vector types");
16009 SmallVector<SDValue, 8> Chains;
16010 SDValue Ptr = Ld->getBasePtr();
16011 SDValue Increment =
16012 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16013 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16015 for (unsigned i = 0; i < NumLoads; ++i) {
16016 // Perform a single load.
16017 SDValue ScalarLoad =
16018 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16019 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16020 Ld->getAlignment());
16021 Chains.push_back(ScalarLoad.getValue(1));
16022 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16023 // another round of DAGCombining.
16025 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16027 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16028 ScalarLoad, DAG.getIntPtrConstant(i));
16030 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16033 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16035 // Bitcast the loaded value to a vector of the original element type, in
16036 // the size of the target vector type.
16037 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16038 unsigned SizeRatio = RegSz / MemSz;
16040 if (Ext == ISD::SEXTLOAD) {
16041 // If we have SSE4.1, we can directly emit a VSEXT node.
16042 if (Subtarget->hasSSE41()) {
16043 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16044 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16048 // Otherwise we'll shuffle the small elements in the high bits of the
16049 // larger type and perform an arithmetic shift. If the shift is not legal
16050 // it's better to scalarize.
16051 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16052 "We can't implement a sext load without an arithmetic right shift!");
16054 // Redistribute the loaded elements into the different locations.
16055 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16056 for (unsigned i = 0; i != NumElems; ++i)
16057 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16059 SDValue Shuff = DAG.getVectorShuffle(
16060 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16062 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16064 // Build the arithmetic shift.
16065 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16066 MemVT.getVectorElementType().getSizeInBits();
16068 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16070 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16074 // Redistribute the loaded elements into the different locations.
16075 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16076 for (unsigned i = 0; i != NumElems; ++i)
16077 ShuffleVec[i * SizeRatio] = i;
16079 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16080 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16082 // Bitcast to the requested type.
16083 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16084 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16088 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16089 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16090 // from the AND / OR.
16091 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16092 Opc = Op.getOpcode();
16093 if (Opc != ISD::OR && Opc != ISD::AND)
16095 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16096 Op.getOperand(0).hasOneUse() &&
16097 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16098 Op.getOperand(1).hasOneUse());
16101 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16102 // 1 and that the SETCC node has a single use.
16103 static bool isXor1OfSetCC(SDValue Op) {
16104 if (Op.getOpcode() != ISD::XOR)
16106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16107 if (N1C && N1C->getAPIntValue() == 1) {
16108 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16109 Op.getOperand(0).hasOneUse();
16114 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16115 bool addTest = true;
16116 SDValue Chain = Op.getOperand(0);
16117 SDValue Cond = Op.getOperand(1);
16118 SDValue Dest = Op.getOperand(2);
16121 bool Inverted = false;
16123 if (Cond.getOpcode() == ISD::SETCC) {
16124 // Check for setcc([su]{add,sub,mul}o == 0).
16125 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16126 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16127 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16128 Cond.getOperand(0).getResNo() == 1 &&
16129 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16130 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16131 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16132 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16133 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16134 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16136 Cond = Cond.getOperand(0);
16138 SDValue NewCond = LowerSETCC(Cond, DAG);
16139 if (NewCond.getNode())
16144 // FIXME: LowerXALUO doesn't handle these!!
16145 else if (Cond.getOpcode() == X86ISD::ADD ||
16146 Cond.getOpcode() == X86ISD::SUB ||
16147 Cond.getOpcode() == X86ISD::SMUL ||
16148 Cond.getOpcode() == X86ISD::UMUL)
16149 Cond = LowerXALUO(Cond, DAG);
16152 // Look pass (and (setcc_carry (cmp ...)), 1).
16153 if (Cond.getOpcode() == ISD::AND &&
16154 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16156 if (C && C->getAPIntValue() == 1)
16157 Cond = Cond.getOperand(0);
16160 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16161 // setting operand in place of the X86ISD::SETCC.
16162 unsigned CondOpcode = Cond.getOpcode();
16163 if (CondOpcode == X86ISD::SETCC ||
16164 CondOpcode == X86ISD::SETCC_CARRY) {
16165 CC = Cond.getOperand(0);
16167 SDValue Cmp = Cond.getOperand(1);
16168 unsigned Opc = Cmp.getOpcode();
16169 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16170 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16174 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16178 // These can only come from an arithmetic instruction with overflow,
16179 // e.g. SADDO, UADDO.
16180 Cond = Cond.getNode()->getOperand(1);
16186 CondOpcode = Cond.getOpcode();
16187 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16188 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16189 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16190 Cond.getOperand(0).getValueType() != MVT::i8)) {
16191 SDValue LHS = Cond.getOperand(0);
16192 SDValue RHS = Cond.getOperand(1);
16193 unsigned X86Opcode;
16196 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16197 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16199 switch (CondOpcode) {
16200 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16204 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16207 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16208 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16212 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16215 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16216 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16217 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16218 default: llvm_unreachable("unexpected overflowing operator");
16221 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16222 if (CondOpcode == ISD::UMULO)
16223 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16226 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16228 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16230 if (CondOpcode == ISD::UMULO)
16231 Cond = X86Op.getValue(2);
16233 Cond = X86Op.getValue(1);
16235 CC = DAG.getConstant(X86Cond, MVT::i8);
16239 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16240 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16241 if (CondOpc == ISD::OR) {
16242 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16243 // two branches instead of an explicit OR instruction with a
16245 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16246 isX86LogicalCmp(Cmp)) {
16247 CC = Cond.getOperand(0).getOperand(0);
16248 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16249 Chain, Dest, CC, Cmp);
16250 CC = Cond.getOperand(1).getOperand(0);
16254 } else { // ISD::AND
16255 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16256 // two branches instead of an explicit AND instruction with a
16257 // separate test. However, we only do this if this block doesn't
16258 // have a fall-through edge, because this requires an explicit
16259 // jmp when the condition is false.
16260 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16261 isX86LogicalCmp(Cmp) &&
16262 Op.getNode()->hasOneUse()) {
16263 X86::CondCode CCode =
16264 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16265 CCode = X86::GetOppositeBranchCondition(CCode);
16266 CC = DAG.getConstant(CCode, MVT::i8);
16267 SDNode *User = *Op.getNode()->use_begin();
16268 // Look for an unconditional branch following this conditional branch.
16269 // We need this because we need to reverse the successors in order
16270 // to implement FCMP_OEQ.
16271 if (User->getOpcode() == ISD::BR) {
16272 SDValue FalseBB = User->getOperand(1);
16274 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16275 assert(NewBR == User);
16279 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16280 Chain, Dest, CC, Cmp);
16281 X86::CondCode CCode =
16282 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16283 CCode = X86::GetOppositeBranchCondition(CCode);
16284 CC = DAG.getConstant(CCode, MVT::i8);
16290 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16291 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16292 // It should be transformed during dag combiner except when the condition
16293 // is set by a arithmetics with overflow node.
16294 X86::CondCode CCode =
16295 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16296 CCode = X86::GetOppositeBranchCondition(CCode);
16297 CC = DAG.getConstant(CCode, MVT::i8);
16298 Cond = Cond.getOperand(0).getOperand(1);
16300 } else if (Cond.getOpcode() == ISD::SETCC &&
16301 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16302 // For FCMP_OEQ, we can emit
16303 // two branches instead of an explicit AND instruction with a
16304 // separate test. However, we only do this if this block doesn't
16305 // have a fall-through edge, because this requires an explicit
16306 // jmp when the condition is false.
16307 if (Op.getNode()->hasOneUse()) {
16308 SDNode *User = *Op.getNode()->use_begin();
16309 // Look for an unconditional branch following this conditional branch.
16310 // We need this because we need to reverse the successors in order
16311 // to implement FCMP_OEQ.
16312 if (User->getOpcode() == ISD::BR) {
16313 SDValue FalseBB = User->getOperand(1);
16315 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16316 assert(NewBR == User);
16320 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16321 Cond.getOperand(0), Cond.getOperand(1));
16322 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16323 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16324 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16325 Chain, Dest, CC, Cmp);
16326 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16331 } else if (Cond.getOpcode() == ISD::SETCC &&
16332 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16333 // For FCMP_UNE, we can emit
16334 // two branches instead of an explicit AND instruction with a
16335 // separate test. However, we only do this if this block doesn't
16336 // have a fall-through edge, because this requires an explicit
16337 // jmp when the condition is false.
16338 if (Op.getNode()->hasOneUse()) {
16339 SDNode *User = *Op.getNode()->use_begin();
16340 // Look for an unconditional branch following this conditional branch.
16341 // We need this because we need to reverse the successors in order
16342 // to implement FCMP_UNE.
16343 if (User->getOpcode() == ISD::BR) {
16344 SDValue FalseBB = User->getOperand(1);
16346 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16347 assert(NewBR == User);
16350 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16351 Cond.getOperand(0), Cond.getOperand(1));
16352 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16353 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16354 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16355 Chain, Dest, CC, Cmp);
16356 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16366 // Look pass the truncate if the high bits are known zero.
16367 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16368 Cond = Cond.getOperand(0);
16370 // We know the result of AND is compared against zero. Try to match
16372 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16373 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16374 if (NewSetCC.getNode()) {
16375 CC = NewSetCC.getOperand(0);
16376 Cond = NewSetCC.getOperand(1);
16383 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16384 CC = DAG.getConstant(X86Cond, MVT::i8);
16385 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16387 Cond = ConvertCmpIfNecessary(Cond, DAG);
16388 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16389 Chain, Dest, CC, Cond);
16392 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16393 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16394 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16395 // that the guard pages used by the OS virtual memory manager are allocated in
16396 // correct sequence.
16398 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16399 SelectionDAG &DAG) const {
16400 MachineFunction &MF = DAG.getMachineFunction();
16401 bool SplitStack = MF.shouldSplitStack();
16402 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16408 SDNode* Node = Op.getNode();
16410 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16411 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16412 " not tell us which reg is the stack pointer!");
16413 EVT VT = Node->getValueType(0);
16414 SDValue Tmp1 = SDValue(Node, 0);
16415 SDValue Tmp2 = SDValue(Node, 1);
16416 SDValue Tmp3 = Node->getOperand(2);
16417 SDValue Chain = Tmp1.getOperand(0);
16419 // Chain the dynamic stack allocation so that it doesn't modify the stack
16420 // pointer when other instructions are using the stack.
16421 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16424 SDValue Size = Tmp2.getOperand(1);
16425 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16426 Chain = SP.getValue(1);
16427 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16428 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16429 unsigned StackAlign = TFI.getStackAlignment();
16430 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16431 if (Align > StackAlign)
16432 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16433 DAG.getConstant(-(uint64_t)Align, VT));
16434 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16436 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16437 DAG.getIntPtrConstant(0, true), SDValue(),
16440 SDValue Ops[2] = { Tmp1, Tmp2 };
16441 return DAG.getMergeValues(Ops, dl);
16445 SDValue Chain = Op.getOperand(0);
16446 SDValue Size = Op.getOperand(1);
16447 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16448 EVT VT = Op.getNode()->getValueType(0);
16450 bool Is64Bit = Subtarget->is64Bit();
16451 EVT SPTy = getPointerTy();
16454 MachineRegisterInfo &MRI = MF.getRegInfo();
16457 // The 64 bit implementation of segmented stacks needs to clobber both r10
16458 // r11. This makes it impossible to use it along with nested parameters.
16459 const Function *F = MF.getFunction();
16461 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16463 if (I->hasNestAttr())
16464 report_fatal_error("Cannot use segmented stacks with functions that "
16465 "have nested arguments.");
16468 const TargetRegisterClass *AddrRegClass =
16469 getRegClassFor(getPointerTy());
16470 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16471 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16472 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16473 DAG.getRegister(Vreg, SPTy));
16474 SDValue Ops1[2] = { Value, Chain };
16475 return DAG.getMergeValues(Ops1, dl);
16478 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16480 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16481 Flag = Chain.getValue(1);
16482 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16484 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16486 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16487 DAG.getSubtarget().getRegisterInfo());
16488 unsigned SPReg = RegInfo->getStackRegister();
16489 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16490 Chain = SP.getValue(1);
16493 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16494 DAG.getConstant(-(uint64_t)Align, VT));
16495 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16498 SDValue Ops1[2] = { SP, Chain };
16499 return DAG.getMergeValues(Ops1, dl);
16503 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16504 MachineFunction &MF = DAG.getMachineFunction();
16505 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16507 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16510 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16511 // vastart just stores the address of the VarArgsFrameIndex slot into the
16512 // memory location argument.
16513 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16515 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16516 MachinePointerInfo(SV), false, false, 0);
16520 // gp_offset (0 - 6 * 8)
16521 // fp_offset (48 - 48 + 8 * 16)
16522 // overflow_arg_area (point to parameters coming in memory).
16524 SmallVector<SDValue, 8> MemOps;
16525 SDValue FIN = Op.getOperand(1);
16527 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16528 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16530 FIN, MachinePointerInfo(SV), false, false, 0);
16531 MemOps.push_back(Store);
16534 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16535 FIN, DAG.getIntPtrConstant(4));
16536 Store = DAG.getStore(Op.getOperand(0), DL,
16537 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16539 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16540 MemOps.push_back(Store);
16542 // Store ptr to overflow_arg_area
16543 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16544 FIN, DAG.getIntPtrConstant(4));
16545 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16547 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16548 MachinePointerInfo(SV, 8),
16550 MemOps.push_back(Store);
16552 // Store ptr to reg_save_area.
16553 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16554 FIN, DAG.getIntPtrConstant(8));
16555 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16557 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16558 MachinePointerInfo(SV, 16), false, false, 0);
16559 MemOps.push_back(Store);
16560 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16563 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16564 assert(Subtarget->is64Bit() &&
16565 "LowerVAARG only handles 64-bit va_arg!");
16566 assert((Subtarget->isTargetLinux() ||
16567 Subtarget->isTargetDarwin()) &&
16568 "Unhandled target in LowerVAARG");
16569 assert(Op.getNode()->getNumOperands() == 4);
16570 SDValue Chain = Op.getOperand(0);
16571 SDValue SrcPtr = Op.getOperand(1);
16572 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16573 unsigned Align = Op.getConstantOperandVal(3);
16576 EVT ArgVT = Op.getNode()->getValueType(0);
16577 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16578 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16581 // Decide which area this value should be read from.
16582 // TODO: Implement the AMD64 ABI in its entirety. This simple
16583 // selection mechanism works only for the basic types.
16584 if (ArgVT == MVT::f80) {
16585 llvm_unreachable("va_arg for f80 not yet implemented");
16586 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16587 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16588 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16589 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16591 llvm_unreachable("Unhandled argument type in LowerVAARG");
16594 if (ArgMode == 2) {
16595 // Sanity Check: Make sure using fp_offset makes sense.
16596 assert(!DAG.getTarget().Options.UseSoftFloat &&
16597 !(DAG.getMachineFunction()
16598 .getFunction()->getAttributes()
16599 .hasAttribute(AttributeSet::FunctionIndex,
16600 Attribute::NoImplicitFloat)) &&
16601 Subtarget->hasSSE1());
16604 // Insert VAARG_64 node into the DAG
16605 // VAARG_64 returns two values: Variable Argument Address, Chain
16606 SmallVector<SDValue, 11> InstOps;
16607 InstOps.push_back(Chain);
16608 InstOps.push_back(SrcPtr);
16609 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16610 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16611 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16612 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16613 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16614 VTs, InstOps, MVT::i64,
16615 MachinePointerInfo(SV),
16617 /*Volatile=*/false,
16619 /*WriteMem=*/true);
16620 Chain = VAARG.getValue(1);
16622 // Load the next argument and return it
16623 return DAG.getLoad(ArgVT, dl,
16626 MachinePointerInfo(),
16627 false, false, false, 0);
16630 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16631 SelectionDAG &DAG) {
16632 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16633 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16634 SDValue Chain = Op.getOperand(0);
16635 SDValue DstPtr = Op.getOperand(1);
16636 SDValue SrcPtr = Op.getOperand(2);
16637 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16638 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16641 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16642 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16644 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16647 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16648 // amount is a constant. Takes immediate version of shift as input.
16649 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16650 SDValue SrcOp, uint64_t ShiftAmt,
16651 SelectionDAG &DAG) {
16652 MVT ElementType = VT.getVectorElementType();
16654 // Fold this packed shift into its first operand if ShiftAmt is 0.
16658 // Check for ShiftAmt >= element width
16659 if (ShiftAmt >= ElementType.getSizeInBits()) {
16660 if (Opc == X86ISD::VSRAI)
16661 ShiftAmt = ElementType.getSizeInBits() - 1;
16663 return DAG.getConstant(0, VT);
16666 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16667 && "Unknown target vector shift-by-constant node");
16669 // Fold this packed vector shift into a build vector if SrcOp is a
16670 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16671 if (VT == SrcOp.getSimpleValueType() &&
16672 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16673 SmallVector<SDValue, 8> Elts;
16674 unsigned NumElts = SrcOp->getNumOperands();
16675 ConstantSDNode *ND;
16678 default: llvm_unreachable(nullptr);
16679 case X86ISD::VSHLI:
16680 for (unsigned i=0; i!=NumElts; ++i) {
16681 SDValue CurrentOp = SrcOp->getOperand(i);
16682 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16683 Elts.push_back(CurrentOp);
16686 ND = cast<ConstantSDNode>(CurrentOp);
16687 const APInt &C = ND->getAPIntValue();
16688 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16691 case X86ISD::VSRLI:
16692 for (unsigned i=0; i!=NumElts; ++i) {
16693 SDValue CurrentOp = SrcOp->getOperand(i);
16694 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16695 Elts.push_back(CurrentOp);
16698 ND = cast<ConstantSDNode>(CurrentOp);
16699 const APInt &C = ND->getAPIntValue();
16700 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16703 case X86ISD::VSRAI:
16704 for (unsigned i=0; i!=NumElts; ++i) {
16705 SDValue CurrentOp = SrcOp->getOperand(i);
16706 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16707 Elts.push_back(CurrentOp);
16710 ND = cast<ConstantSDNode>(CurrentOp);
16711 const APInt &C = ND->getAPIntValue();
16712 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16717 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16720 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16723 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16724 // may or may not be a constant. Takes immediate version of shift as input.
16725 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16726 SDValue SrcOp, SDValue ShAmt,
16727 SelectionDAG &DAG) {
16728 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16730 // Catch shift-by-constant.
16731 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16732 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16733 CShAmt->getZExtValue(), DAG);
16735 // Change opcode to non-immediate version
16737 default: llvm_unreachable("Unknown target vector shift node");
16738 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16739 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16740 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16743 // Need to build a vector containing shift amount
16744 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16747 ShOps[1] = DAG.getConstant(0, MVT::i32);
16748 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16749 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16751 // The return type has to be a 128-bit type with the same element
16752 // type as the input type.
16753 MVT EltVT = VT.getVectorElementType();
16754 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16756 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16757 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16760 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16761 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16762 /// necessary casting for \p Mask when lowering masking intrinsics.
16763 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16764 SDValue PreservedSrc,
16765 const X86Subtarget *Subtarget,
16766 SelectionDAG &DAG) {
16767 EVT VT = Op.getValueType();
16768 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16769 MVT::i1, VT.getVectorNumElements());
16770 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16771 Mask.getValueType().getSizeInBits());
16774 assert(MaskVT.isSimple() && "invalid mask type");
16776 if (isAllOnes(Mask))
16779 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16780 // are extracted by EXTRACT_SUBVECTOR.
16781 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16782 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16783 DAG.getIntPtrConstant(0));
16785 switch (Op.getOpcode()) {
16787 case X86ISD::PCMPEQM:
16788 case X86ISD::PCMPGTM:
16790 case X86ISD::CMPMU:
16791 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16793 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16794 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16795 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16798 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16799 SDValue PreservedSrc,
16800 const X86Subtarget *Subtarget,
16801 SelectionDAG &DAG) {
16802 if (isAllOnes(Mask))
16805 EVT VT = Op.getValueType();
16807 // The mask should be of type MVT::i1
16808 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16810 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16811 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16812 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16815 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16817 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16818 case Intrinsic::x86_fma_vfmadd_ps:
16819 case Intrinsic::x86_fma_vfmadd_pd:
16820 case Intrinsic::x86_fma_vfmadd_ps_256:
16821 case Intrinsic::x86_fma_vfmadd_pd_256:
16822 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16823 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16824 return X86ISD::FMADD;
16825 case Intrinsic::x86_fma_vfmsub_ps:
16826 case Intrinsic::x86_fma_vfmsub_pd:
16827 case Intrinsic::x86_fma_vfmsub_ps_256:
16828 case Intrinsic::x86_fma_vfmsub_pd_256:
16829 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16830 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16831 return X86ISD::FMSUB;
16832 case Intrinsic::x86_fma_vfnmadd_ps:
16833 case Intrinsic::x86_fma_vfnmadd_pd:
16834 case Intrinsic::x86_fma_vfnmadd_ps_256:
16835 case Intrinsic::x86_fma_vfnmadd_pd_256:
16836 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16837 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16838 return X86ISD::FNMADD;
16839 case Intrinsic::x86_fma_vfnmsub_ps:
16840 case Intrinsic::x86_fma_vfnmsub_pd:
16841 case Intrinsic::x86_fma_vfnmsub_ps_256:
16842 case Intrinsic::x86_fma_vfnmsub_pd_256:
16843 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16844 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16845 return X86ISD::FNMSUB;
16846 case Intrinsic::x86_fma_vfmaddsub_ps:
16847 case Intrinsic::x86_fma_vfmaddsub_pd:
16848 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16849 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16850 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16851 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16852 return X86ISD::FMADDSUB;
16853 case Intrinsic::x86_fma_vfmsubadd_ps:
16854 case Intrinsic::x86_fma_vfmsubadd_pd:
16855 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16856 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16857 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16858 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16859 return X86ISD::FMSUBADD;
16863 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16864 SelectionDAG &DAG) {
16866 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16867 EVT VT = Op.getValueType();
16868 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16870 switch(IntrData->Type) {
16871 case INTR_TYPE_1OP:
16872 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16873 case INTR_TYPE_2OP:
16874 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16876 case INTR_TYPE_3OP:
16877 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16878 Op.getOperand(2), Op.getOperand(3));
16879 case INTR_TYPE_1OP_MASK_RM: {
16880 SDValue Src = Op.getOperand(1);
16881 SDValue Src0 = Op.getOperand(2);
16882 SDValue Mask = Op.getOperand(3);
16883 SDValue RoundingMode = Op.getOperand(4);
16884 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16886 Mask, Src0, Subtarget, DAG);
16888 case INTR_TYPE_SCALAR_MASK_RM: {
16889 SDValue Src1 = Op.getOperand(1);
16890 SDValue Src2 = Op.getOperand(2);
16891 SDValue Src0 = Op.getOperand(3);
16892 SDValue Mask = Op.getOperand(4);
16893 SDValue RoundingMode = Op.getOperand(5);
16894 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16896 Mask, Src0, Subtarget, DAG);
16898 case INTR_TYPE_2OP_MASK: {
16899 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16901 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16904 case CMP_MASK_CC: {
16905 // Comparison intrinsics with masks.
16906 // Example of transformation:
16907 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16908 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16910 // (v8i1 (insert_subvector undef,
16911 // (v2i1 (and (PCMPEQM %a, %b),
16912 // (extract_subvector
16913 // (v8i1 (bitcast %mask)), 0))), 0))))
16914 EVT VT = Op.getOperand(1).getValueType();
16915 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16916 VT.getVectorNumElements());
16917 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16918 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16919 Mask.getValueType().getSizeInBits());
16921 if (IntrData->Type == CMP_MASK_CC) {
16922 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16923 Op.getOperand(2), Op.getOperand(3));
16925 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16926 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16929 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16930 DAG.getTargetConstant(0, MaskVT),
16932 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16933 DAG.getUNDEF(BitcastVT), CmpMask,
16934 DAG.getIntPtrConstant(0));
16935 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16937 case COMI: { // Comparison intrinsics
16938 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16939 SDValue LHS = Op.getOperand(1);
16940 SDValue RHS = Op.getOperand(2);
16941 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16942 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16943 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16944 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16945 DAG.getConstant(X86CC, MVT::i8), Cond);
16946 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16949 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16950 Op.getOperand(1), Op.getOperand(2), DAG);
16952 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16953 Op.getOperand(1), Op.getOperand(2), DAG),
16954 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16961 default: return SDValue(); // Don't custom lower most intrinsics.
16963 // Arithmetic intrinsics.
16964 case Intrinsic::x86_sse2_pmulu_dq:
16965 case Intrinsic::x86_avx2_pmulu_dq:
16966 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16967 Op.getOperand(1), Op.getOperand(2));
16969 case Intrinsic::x86_sse41_pmuldq:
16970 case Intrinsic::x86_avx2_pmul_dq:
16971 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16972 Op.getOperand(1), Op.getOperand(2));
16974 case Intrinsic::x86_sse2_pmulhu_w:
16975 case Intrinsic::x86_avx2_pmulhu_w:
16976 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16977 Op.getOperand(1), Op.getOperand(2));
16979 case Intrinsic::x86_sse2_pmulh_w:
16980 case Intrinsic::x86_avx2_pmulh_w:
16981 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16982 Op.getOperand(1), Op.getOperand(2));
16984 // SSE/SSE2/AVX floating point max/min intrinsics.
16985 case Intrinsic::x86_sse_max_ps:
16986 case Intrinsic::x86_sse2_max_pd:
16987 case Intrinsic::x86_avx_max_ps_256:
16988 case Intrinsic::x86_avx_max_pd_256:
16989 case Intrinsic::x86_sse_min_ps:
16990 case Intrinsic::x86_sse2_min_pd:
16991 case Intrinsic::x86_avx_min_ps_256:
16992 case Intrinsic::x86_avx_min_pd_256: {
16995 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16996 case Intrinsic::x86_sse_max_ps:
16997 case Intrinsic::x86_sse2_max_pd:
16998 case Intrinsic::x86_avx_max_ps_256:
16999 case Intrinsic::x86_avx_max_pd_256:
17000 Opcode = X86ISD::FMAX;
17002 case Intrinsic::x86_sse_min_ps:
17003 case Intrinsic::x86_sse2_min_pd:
17004 case Intrinsic::x86_avx_min_ps_256:
17005 case Intrinsic::x86_avx_min_pd_256:
17006 Opcode = X86ISD::FMIN;
17009 return DAG.getNode(Opcode, dl, Op.getValueType(),
17010 Op.getOperand(1), Op.getOperand(2));
17013 // AVX2 variable shift intrinsics
17014 case Intrinsic::x86_avx2_psllv_d:
17015 case Intrinsic::x86_avx2_psllv_q:
17016 case Intrinsic::x86_avx2_psllv_d_256:
17017 case Intrinsic::x86_avx2_psllv_q_256:
17018 case Intrinsic::x86_avx2_psrlv_d:
17019 case Intrinsic::x86_avx2_psrlv_q:
17020 case Intrinsic::x86_avx2_psrlv_d_256:
17021 case Intrinsic::x86_avx2_psrlv_q_256:
17022 case Intrinsic::x86_avx2_psrav_d:
17023 case Intrinsic::x86_avx2_psrav_d_256: {
17026 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17027 case Intrinsic::x86_avx2_psllv_d:
17028 case Intrinsic::x86_avx2_psllv_q:
17029 case Intrinsic::x86_avx2_psllv_d_256:
17030 case Intrinsic::x86_avx2_psllv_q_256:
17033 case Intrinsic::x86_avx2_psrlv_d:
17034 case Intrinsic::x86_avx2_psrlv_q:
17035 case Intrinsic::x86_avx2_psrlv_d_256:
17036 case Intrinsic::x86_avx2_psrlv_q_256:
17039 case Intrinsic::x86_avx2_psrav_d:
17040 case Intrinsic::x86_avx2_psrav_d_256:
17044 return DAG.getNode(Opcode, dl, Op.getValueType(),
17045 Op.getOperand(1), Op.getOperand(2));
17048 case Intrinsic::x86_sse2_packssdw_128:
17049 case Intrinsic::x86_sse2_packsswb_128:
17050 case Intrinsic::x86_avx2_packssdw:
17051 case Intrinsic::x86_avx2_packsswb:
17052 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17053 Op.getOperand(1), Op.getOperand(2));
17055 case Intrinsic::x86_sse2_packuswb_128:
17056 case Intrinsic::x86_sse41_packusdw:
17057 case Intrinsic::x86_avx2_packuswb:
17058 case Intrinsic::x86_avx2_packusdw:
17059 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17060 Op.getOperand(1), Op.getOperand(2));
17062 case Intrinsic::x86_ssse3_pshuf_b_128:
17063 case Intrinsic::x86_avx2_pshuf_b:
17064 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17065 Op.getOperand(1), Op.getOperand(2));
17067 case Intrinsic::x86_sse2_pshuf_d:
17068 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17069 Op.getOperand(1), Op.getOperand(2));
17071 case Intrinsic::x86_sse2_pshufl_w:
17072 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17073 Op.getOperand(1), Op.getOperand(2));
17075 case Intrinsic::x86_sse2_pshufh_w:
17076 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17077 Op.getOperand(1), Op.getOperand(2));
17079 case Intrinsic::x86_ssse3_psign_b_128:
17080 case Intrinsic::x86_ssse3_psign_w_128:
17081 case Intrinsic::x86_ssse3_psign_d_128:
17082 case Intrinsic::x86_avx2_psign_b:
17083 case Intrinsic::x86_avx2_psign_w:
17084 case Intrinsic::x86_avx2_psign_d:
17085 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17086 Op.getOperand(1), Op.getOperand(2));
17088 case Intrinsic::x86_avx2_permd:
17089 case Intrinsic::x86_avx2_permps:
17090 // Operands intentionally swapped. Mask is last operand to intrinsic,
17091 // but second operand for node/instruction.
17092 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17093 Op.getOperand(2), Op.getOperand(1));
17095 case Intrinsic::x86_avx512_mask_valign_q_512:
17096 case Intrinsic::x86_avx512_mask_valign_d_512:
17097 // Vector source operands are swapped.
17098 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17099 Op.getValueType(), Op.getOperand(2),
17102 Op.getOperand(5), Op.getOperand(4),
17105 // ptest and testp intrinsics. The intrinsic these come from are designed to
17106 // return an integer value, not just an instruction so lower it to the ptest
17107 // or testp pattern and a setcc for the result.
17108 case Intrinsic::x86_sse41_ptestz:
17109 case Intrinsic::x86_sse41_ptestc:
17110 case Intrinsic::x86_sse41_ptestnzc:
17111 case Intrinsic::x86_avx_ptestz_256:
17112 case Intrinsic::x86_avx_ptestc_256:
17113 case Intrinsic::x86_avx_ptestnzc_256:
17114 case Intrinsic::x86_avx_vtestz_ps:
17115 case Intrinsic::x86_avx_vtestc_ps:
17116 case Intrinsic::x86_avx_vtestnzc_ps:
17117 case Intrinsic::x86_avx_vtestz_pd:
17118 case Intrinsic::x86_avx_vtestc_pd:
17119 case Intrinsic::x86_avx_vtestnzc_pd:
17120 case Intrinsic::x86_avx_vtestz_ps_256:
17121 case Intrinsic::x86_avx_vtestc_ps_256:
17122 case Intrinsic::x86_avx_vtestnzc_ps_256:
17123 case Intrinsic::x86_avx_vtestz_pd_256:
17124 case Intrinsic::x86_avx_vtestc_pd_256:
17125 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17126 bool IsTestPacked = false;
17129 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17130 case Intrinsic::x86_avx_vtestz_ps:
17131 case Intrinsic::x86_avx_vtestz_pd:
17132 case Intrinsic::x86_avx_vtestz_ps_256:
17133 case Intrinsic::x86_avx_vtestz_pd_256:
17134 IsTestPacked = true; // Fallthrough
17135 case Intrinsic::x86_sse41_ptestz:
17136 case Intrinsic::x86_avx_ptestz_256:
17138 X86CC = X86::COND_E;
17140 case Intrinsic::x86_avx_vtestc_ps:
17141 case Intrinsic::x86_avx_vtestc_pd:
17142 case Intrinsic::x86_avx_vtestc_ps_256:
17143 case Intrinsic::x86_avx_vtestc_pd_256:
17144 IsTestPacked = true; // Fallthrough
17145 case Intrinsic::x86_sse41_ptestc:
17146 case Intrinsic::x86_avx_ptestc_256:
17148 X86CC = X86::COND_B;
17150 case Intrinsic::x86_avx_vtestnzc_ps:
17151 case Intrinsic::x86_avx_vtestnzc_pd:
17152 case Intrinsic::x86_avx_vtestnzc_ps_256:
17153 case Intrinsic::x86_avx_vtestnzc_pd_256:
17154 IsTestPacked = true; // Fallthrough
17155 case Intrinsic::x86_sse41_ptestnzc:
17156 case Intrinsic::x86_avx_ptestnzc_256:
17158 X86CC = X86::COND_A;
17162 SDValue LHS = Op.getOperand(1);
17163 SDValue RHS = Op.getOperand(2);
17164 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17165 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17166 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17167 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17168 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17170 case Intrinsic::x86_avx512_kortestz_w:
17171 case Intrinsic::x86_avx512_kortestc_w: {
17172 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17173 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17174 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17175 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17176 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17177 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17178 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17181 case Intrinsic::x86_sse42_pcmpistria128:
17182 case Intrinsic::x86_sse42_pcmpestria128:
17183 case Intrinsic::x86_sse42_pcmpistric128:
17184 case Intrinsic::x86_sse42_pcmpestric128:
17185 case Intrinsic::x86_sse42_pcmpistrio128:
17186 case Intrinsic::x86_sse42_pcmpestrio128:
17187 case Intrinsic::x86_sse42_pcmpistris128:
17188 case Intrinsic::x86_sse42_pcmpestris128:
17189 case Intrinsic::x86_sse42_pcmpistriz128:
17190 case Intrinsic::x86_sse42_pcmpestriz128: {
17194 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17195 case Intrinsic::x86_sse42_pcmpistria128:
17196 Opcode = X86ISD::PCMPISTRI;
17197 X86CC = X86::COND_A;
17199 case Intrinsic::x86_sse42_pcmpestria128:
17200 Opcode = X86ISD::PCMPESTRI;
17201 X86CC = X86::COND_A;
17203 case Intrinsic::x86_sse42_pcmpistric128:
17204 Opcode = X86ISD::PCMPISTRI;
17205 X86CC = X86::COND_B;
17207 case Intrinsic::x86_sse42_pcmpestric128:
17208 Opcode = X86ISD::PCMPESTRI;
17209 X86CC = X86::COND_B;
17211 case Intrinsic::x86_sse42_pcmpistrio128:
17212 Opcode = X86ISD::PCMPISTRI;
17213 X86CC = X86::COND_O;
17215 case Intrinsic::x86_sse42_pcmpestrio128:
17216 Opcode = X86ISD::PCMPESTRI;
17217 X86CC = X86::COND_O;
17219 case Intrinsic::x86_sse42_pcmpistris128:
17220 Opcode = X86ISD::PCMPISTRI;
17221 X86CC = X86::COND_S;
17223 case Intrinsic::x86_sse42_pcmpestris128:
17224 Opcode = X86ISD::PCMPESTRI;
17225 X86CC = X86::COND_S;
17227 case Intrinsic::x86_sse42_pcmpistriz128:
17228 Opcode = X86ISD::PCMPISTRI;
17229 X86CC = X86::COND_E;
17231 case Intrinsic::x86_sse42_pcmpestriz128:
17232 Opcode = X86ISD::PCMPESTRI;
17233 X86CC = X86::COND_E;
17236 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17237 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17238 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17239 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17240 DAG.getConstant(X86CC, MVT::i8),
17241 SDValue(PCMP.getNode(), 1));
17242 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17245 case Intrinsic::x86_sse42_pcmpistri128:
17246 case Intrinsic::x86_sse42_pcmpestri128: {
17248 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17249 Opcode = X86ISD::PCMPISTRI;
17251 Opcode = X86ISD::PCMPESTRI;
17253 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17254 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17255 return DAG.getNode(Opcode, dl, VTs, NewOps);
17258 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17259 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17260 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17261 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17262 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17263 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17264 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17265 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17266 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17267 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17268 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17269 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17270 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17271 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17272 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17273 dl, Op.getValueType(),
17277 Op.getOperand(4), Op.getOperand(1),
17283 case Intrinsic::x86_fma_vfmadd_ps:
17284 case Intrinsic::x86_fma_vfmadd_pd:
17285 case Intrinsic::x86_fma_vfmsub_ps:
17286 case Intrinsic::x86_fma_vfmsub_pd:
17287 case Intrinsic::x86_fma_vfnmadd_ps:
17288 case Intrinsic::x86_fma_vfnmadd_pd:
17289 case Intrinsic::x86_fma_vfnmsub_ps:
17290 case Intrinsic::x86_fma_vfnmsub_pd:
17291 case Intrinsic::x86_fma_vfmaddsub_ps:
17292 case Intrinsic::x86_fma_vfmaddsub_pd:
17293 case Intrinsic::x86_fma_vfmsubadd_ps:
17294 case Intrinsic::x86_fma_vfmsubadd_pd:
17295 case Intrinsic::x86_fma_vfmadd_ps_256:
17296 case Intrinsic::x86_fma_vfmadd_pd_256:
17297 case Intrinsic::x86_fma_vfmsub_ps_256:
17298 case Intrinsic::x86_fma_vfmsub_pd_256:
17299 case Intrinsic::x86_fma_vfnmadd_ps_256:
17300 case Intrinsic::x86_fma_vfnmadd_pd_256:
17301 case Intrinsic::x86_fma_vfnmsub_ps_256:
17302 case Intrinsic::x86_fma_vfnmsub_pd_256:
17303 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17304 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17305 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17306 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17307 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17308 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17312 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17313 SDValue Src, SDValue Mask, SDValue Base,
17314 SDValue Index, SDValue ScaleOp, SDValue Chain,
17315 const X86Subtarget * Subtarget) {
17317 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17318 assert(C && "Invalid scale type");
17319 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17320 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17321 Index.getSimpleValueType().getVectorNumElements());
17323 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17325 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17327 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17328 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17329 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17330 SDValue Segment = DAG.getRegister(0, MVT::i32);
17331 if (Src.getOpcode() == ISD::UNDEF)
17332 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17333 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17334 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17335 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17336 return DAG.getMergeValues(RetOps, dl);
17339 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17340 SDValue Src, SDValue Mask, SDValue Base,
17341 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17343 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17344 assert(C && "Invalid scale type");
17345 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17346 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17347 SDValue Segment = DAG.getRegister(0, MVT::i32);
17348 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17349 Index.getSimpleValueType().getVectorNumElements());
17351 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17353 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17355 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17356 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17357 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17358 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17359 return SDValue(Res, 1);
17362 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17363 SDValue Mask, SDValue Base, SDValue Index,
17364 SDValue ScaleOp, SDValue Chain) {
17366 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17367 assert(C && "Invalid scale type");
17368 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17369 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17370 SDValue Segment = DAG.getRegister(0, MVT::i32);
17372 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17374 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17376 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17378 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17379 //SDVTList VTs = DAG.getVTList(MVT::Other);
17380 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17381 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17382 return SDValue(Res, 0);
17385 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17386 // read performance monitor counters (x86_rdpmc).
17387 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17388 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17389 SmallVectorImpl<SDValue> &Results) {
17390 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17391 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17394 // The ECX register is used to select the index of the performance counter
17396 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17398 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17400 // Reads the content of a 64-bit performance counter and returns it in the
17401 // registers EDX:EAX.
17402 if (Subtarget->is64Bit()) {
17403 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17404 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17407 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17408 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17411 Chain = HI.getValue(1);
17413 if (Subtarget->is64Bit()) {
17414 // The EAX register is loaded with the low-order 32 bits. The EDX register
17415 // is loaded with the supported high-order bits of the counter.
17416 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17417 DAG.getConstant(32, MVT::i8));
17418 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17419 Results.push_back(Chain);
17423 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17424 SDValue Ops[] = { LO, HI };
17425 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17426 Results.push_back(Pair);
17427 Results.push_back(Chain);
17430 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17431 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17432 // also used to custom lower READCYCLECOUNTER nodes.
17433 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17434 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17435 SmallVectorImpl<SDValue> &Results) {
17436 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17437 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17440 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17441 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17442 // and the EAX register is loaded with the low-order 32 bits.
17443 if (Subtarget->is64Bit()) {
17444 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17445 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17448 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17449 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17452 SDValue Chain = HI.getValue(1);
17454 if (Opcode == X86ISD::RDTSCP_DAG) {
17455 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17457 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17458 // the ECX register. Add 'ecx' explicitly to the chain.
17459 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17461 // Explicitly store the content of ECX at the location passed in input
17462 // to the 'rdtscp' intrinsic.
17463 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17464 MachinePointerInfo(), false, false, 0);
17467 if (Subtarget->is64Bit()) {
17468 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17469 // the EAX register is loaded with the low-order 32 bits.
17470 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17471 DAG.getConstant(32, MVT::i8));
17472 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17473 Results.push_back(Chain);
17477 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17478 SDValue Ops[] = { LO, HI };
17479 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17480 Results.push_back(Pair);
17481 Results.push_back(Chain);
17484 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17485 SelectionDAG &DAG) {
17486 SmallVector<SDValue, 2> Results;
17488 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17490 return DAG.getMergeValues(Results, DL);
17494 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17495 SelectionDAG &DAG) {
17496 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17498 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17503 switch(IntrData->Type) {
17505 llvm_unreachable("Unknown Intrinsic Type");
17509 // Emit the node with the right value type.
17510 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17511 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17513 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17514 // Otherwise return the value from Rand, which is always 0, casted to i32.
17515 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17516 DAG.getConstant(1, Op->getValueType(1)),
17517 DAG.getConstant(X86::COND_B, MVT::i32),
17518 SDValue(Result.getNode(), 1) };
17519 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17520 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17523 // Return { result, isValid, chain }.
17524 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17525 SDValue(Result.getNode(), 2));
17528 //gather(v1, mask, index, base, scale);
17529 SDValue Chain = Op.getOperand(0);
17530 SDValue Src = Op.getOperand(2);
17531 SDValue Base = Op.getOperand(3);
17532 SDValue Index = Op.getOperand(4);
17533 SDValue Mask = Op.getOperand(5);
17534 SDValue Scale = Op.getOperand(6);
17535 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17539 //scatter(base, mask, index, v1, scale);
17540 SDValue Chain = Op.getOperand(0);
17541 SDValue Base = Op.getOperand(2);
17542 SDValue Mask = Op.getOperand(3);
17543 SDValue Index = Op.getOperand(4);
17544 SDValue Src = Op.getOperand(5);
17545 SDValue Scale = Op.getOperand(6);
17546 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17549 SDValue Hint = Op.getOperand(6);
17551 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17552 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17553 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17554 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17555 SDValue Chain = Op.getOperand(0);
17556 SDValue Mask = Op.getOperand(2);
17557 SDValue Index = Op.getOperand(3);
17558 SDValue Base = Op.getOperand(4);
17559 SDValue Scale = Op.getOperand(5);
17560 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17562 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17564 SmallVector<SDValue, 2> Results;
17565 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17566 return DAG.getMergeValues(Results, dl);
17568 // Read Performance Monitoring Counters.
17570 SmallVector<SDValue, 2> Results;
17571 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17572 return DAG.getMergeValues(Results, dl);
17574 // XTEST intrinsics.
17576 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17577 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17578 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17579 DAG.getConstant(X86::COND_NE, MVT::i8),
17581 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17582 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17583 Ret, SDValue(InTrans.getNode(), 1));
17587 SmallVector<SDValue, 2> Results;
17588 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17589 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17590 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17591 DAG.getConstant(-1, MVT::i8));
17592 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17593 Op.getOperand(4), GenCF.getValue(1));
17594 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17595 Op.getOperand(5), MachinePointerInfo(),
17597 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17598 DAG.getConstant(X86::COND_B, MVT::i8),
17600 Results.push_back(SetCC);
17601 Results.push_back(Store);
17602 return DAG.getMergeValues(Results, dl);
17607 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17608 SelectionDAG &DAG) const {
17609 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17610 MFI->setReturnAddressIsTaken(true);
17612 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17615 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17617 EVT PtrVT = getPointerTy();
17620 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17621 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17622 DAG.getSubtarget().getRegisterInfo());
17623 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17624 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17625 DAG.getNode(ISD::ADD, dl, PtrVT,
17626 FrameAddr, Offset),
17627 MachinePointerInfo(), false, false, false, 0);
17630 // Just load the return address.
17631 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17632 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17633 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17636 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17637 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17638 MFI->setFrameAddressIsTaken(true);
17640 EVT VT = Op.getValueType();
17641 SDLoc dl(Op); // FIXME probably not meaningful
17642 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17643 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17644 DAG.getSubtarget().getRegisterInfo());
17645 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17646 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17647 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17648 "Invalid Frame Register!");
17649 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17651 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17652 MachinePointerInfo(),
17653 false, false, false, 0);
17657 // FIXME? Maybe this could be a TableGen attribute on some registers and
17658 // this table could be generated automatically from RegInfo.
17659 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17661 unsigned Reg = StringSwitch<unsigned>(RegName)
17662 .Case("esp", X86::ESP)
17663 .Case("rsp", X86::RSP)
17667 report_fatal_error("Invalid register name global variable");
17670 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17671 SelectionDAG &DAG) const {
17672 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17673 DAG.getSubtarget().getRegisterInfo());
17674 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17677 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17678 SDValue Chain = Op.getOperand(0);
17679 SDValue Offset = Op.getOperand(1);
17680 SDValue Handler = Op.getOperand(2);
17683 EVT PtrVT = getPointerTy();
17684 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17685 DAG.getSubtarget().getRegisterInfo());
17686 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17687 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17688 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17689 "Invalid Frame Register!");
17690 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17691 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17693 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17694 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17695 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17696 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17698 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17700 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17701 DAG.getRegister(StoreAddrReg, PtrVT));
17704 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17705 SelectionDAG &DAG) const {
17707 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17708 DAG.getVTList(MVT::i32, MVT::Other),
17709 Op.getOperand(0), Op.getOperand(1));
17712 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17713 SelectionDAG &DAG) const {
17715 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17716 Op.getOperand(0), Op.getOperand(1));
17719 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17720 return Op.getOperand(0);
17723 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17724 SelectionDAG &DAG) const {
17725 SDValue Root = Op.getOperand(0);
17726 SDValue Trmp = Op.getOperand(1); // trampoline
17727 SDValue FPtr = Op.getOperand(2); // nested function
17728 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17731 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17732 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17734 if (Subtarget->is64Bit()) {
17735 SDValue OutChains[6];
17737 // Large code-model.
17738 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17739 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17741 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17742 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17744 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17746 // Load the pointer to the nested function into R11.
17747 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17748 SDValue Addr = Trmp;
17749 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17750 Addr, MachinePointerInfo(TrmpAddr),
17753 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17754 DAG.getConstant(2, MVT::i64));
17755 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17756 MachinePointerInfo(TrmpAddr, 2),
17759 // Load the 'nest' parameter value into R10.
17760 // R10 is specified in X86CallingConv.td
17761 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17762 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17763 DAG.getConstant(10, MVT::i64));
17764 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17765 Addr, MachinePointerInfo(TrmpAddr, 10),
17768 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17769 DAG.getConstant(12, MVT::i64));
17770 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17771 MachinePointerInfo(TrmpAddr, 12),
17774 // Jump to the nested function.
17775 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17776 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17777 DAG.getConstant(20, MVT::i64));
17778 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17779 Addr, MachinePointerInfo(TrmpAddr, 20),
17782 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17783 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17784 DAG.getConstant(22, MVT::i64));
17785 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17786 MachinePointerInfo(TrmpAddr, 22),
17789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17791 const Function *Func =
17792 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17793 CallingConv::ID CC = Func->getCallingConv();
17798 llvm_unreachable("Unsupported calling convention");
17799 case CallingConv::C:
17800 case CallingConv::X86_StdCall: {
17801 // Pass 'nest' parameter in ECX.
17802 // Must be kept in sync with X86CallingConv.td
17803 NestReg = X86::ECX;
17805 // Check that ECX wasn't needed by an 'inreg' parameter.
17806 FunctionType *FTy = Func->getFunctionType();
17807 const AttributeSet &Attrs = Func->getAttributes();
17809 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17810 unsigned InRegCount = 0;
17813 for (FunctionType::param_iterator I = FTy->param_begin(),
17814 E = FTy->param_end(); I != E; ++I, ++Idx)
17815 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17816 // FIXME: should only count parameters that are lowered to integers.
17817 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17819 if (InRegCount > 2) {
17820 report_fatal_error("Nest register in use - reduce number of inreg"
17826 case CallingConv::X86_FastCall:
17827 case CallingConv::X86_ThisCall:
17828 case CallingConv::Fast:
17829 // Pass 'nest' parameter in EAX.
17830 // Must be kept in sync with X86CallingConv.td
17831 NestReg = X86::EAX;
17835 SDValue OutChains[4];
17836 SDValue Addr, Disp;
17838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17839 DAG.getConstant(10, MVT::i32));
17840 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17842 // This is storing the opcode for MOV32ri.
17843 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17844 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17845 OutChains[0] = DAG.getStore(Root, dl,
17846 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17847 Trmp, MachinePointerInfo(TrmpAddr),
17850 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17851 DAG.getConstant(1, MVT::i32));
17852 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17853 MachinePointerInfo(TrmpAddr, 1),
17856 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17857 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17858 DAG.getConstant(5, MVT::i32));
17859 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17860 MachinePointerInfo(TrmpAddr, 5),
17863 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17864 DAG.getConstant(6, MVT::i32));
17865 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17866 MachinePointerInfo(TrmpAddr, 6),
17869 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17873 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17874 SelectionDAG &DAG) const {
17876 The rounding mode is in bits 11:10 of FPSR, and has the following
17878 00 Round to nearest
17883 FLT_ROUNDS, on the other hand, expects the following:
17890 To perform the conversion, we do:
17891 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17894 MachineFunction &MF = DAG.getMachineFunction();
17895 const TargetMachine &TM = MF.getTarget();
17896 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17897 unsigned StackAlignment = TFI.getStackAlignment();
17898 MVT VT = Op.getSimpleValueType();
17901 // Save FP Control Word to stack slot
17902 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17903 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17905 MachineMemOperand *MMO =
17906 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17907 MachineMemOperand::MOStore, 2, 2);
17909 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17910 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17911 DAG.getVTList(MVT::Other),
17912 Ops, MVT::i16, MMO);
17914 // Load FP Control Word from stack slot
17915 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17916 MachinePointerInfo(), false, false, false, 0);
17918 // Transform as necessary
17920 DAG.getNode(ISD::SRL, DL, MVT::i16,
17921 DAG.getNode(ISD::AND, DL, MVT::i16,
17922 CWD, DAG.getConstant(0x800, MVT::i16)),
17923 DAG.getConstant(11, MVT::i8));
17925 DAG.getNode(ISD::SRL, DL, MVT::i16,
17926 DAG.getNode(ISD::AND, DL, MVT::i16,
17927 CWD, DAG.getConstant(0x400, MVT::i16)),
17928 DAG.getConstant(9, MVT::i8));
17931 DAG.getNode(ISD::AND, DL, MVT::i16,
17932 DAG.getNode(ISD::ADD, DL, MVT::i16,
17933 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17934 DAG.getConstant(1, MVT::i16)),
17935 DAG.getConstant(3, MVT::i16));
17937 return DAG.getNode((VT.getSizeInBits() < 16 ?
17938 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17941 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17942 MVT VT = Op.getSimpleValueType();
17944 unsigned NumBits = VT.getSizeInBits();
17947 Op = Op.getOperand(0);
17948 if (VT == MVT::i8) {
17949 // Zero extend to i32 since there is not an i8 bsr.
17951 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17954 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17955 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17956 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17958 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17961 DAG.getConstant(NumBits+NumBits-1, OpVT),
17962 DAG.getConstant(X86::COND_E, MVT::i8),
17965 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17967 // Finally xor with NumBits-1.
17968 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17971 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17975 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17976 MVT VT = Op.getSimpleValueType();
17978 unsigned NumBits = VT.getSizeInBits();
17981 Op = Op.getOperand(0);
17982 if (VT == MVT::i8) {
17983 // Zero extend to i32 since there is not an i8 bsr.
17985 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17988 // Issue a bsr (scan bits in reverse).
17989 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17990 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17992 // And xor with NumBits-1.
17993 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17996 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18000 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18001 MVT VT = Op.getSimpleValueType();
18002 unsigned NumBits = VT.getSizeInBits();
18004 Op = Op.getOperand(0);
18006 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18007 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18008 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18010 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18013 DAG.getConstant(NumBits, VT),
18014 DAG.getConstant(X86::COND_E, MVT::i8),
18017 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18020 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18021 // ones, and then concatenate the result back.
18022 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18023 MVT VT = Op.getSimpleValueType();
18025 assert(VT.is256BitVector() && VT.isInteger() &&
18026 "Unsupported value type for operation");
18028 unsigned NumElems = VT.getVectorNumElements();
18031 // Extract the LHS vectors
18032 SDValue LHS = Op.getOperand(0);
18033 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18034 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18036 // Extract the RHS vectors
18037 SDValue RHS = Op.getOperand(1);
18038 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18039 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18041 MVT EltVT = VT.getVectorElementType();
18042 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18044 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18045 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18046 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18049 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18050 assert(Op.getSimpleValueType().is256BitVector() &&
18051 Op.getSimpleValueType().isInteger() &&
18052 "Only handle AVX 256-bit vector integer operation");
18053 return Lower256IntArith(Op, DAG);
18056 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18057 assert(Op.getSimpleValueType().is256BitVector() &&
18058 Op.getSimpleValueType().isInteger() &&
18059 "Only handle AVX 256-bit vector integer operation");
18060 return Lower256IntArith(Op, DAG);
18063 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18064 SelectionDAG &DAG) {
18066 MVT VT = Op.getSimpleValueType();
18068 // Decompose 256-bit ops into smaller 128-bit ops.
18069 if (VT.is256BitVector() && !Subtarget->hasInt256())
18070 return Lower256IntArith(Op, DAG);
18072 SDValue A = Op.getOperand(0);
18073 SDValue B = Op.getOperand(1);
18075 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18076 if (VT == MVT::v4i32) {
18077 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18078 "Should not custom lower when pmuldq is available!");
18080 // Extract the odd parts.
18081 static const int UnpackMask[] = { 1, -1, 3, -1 };
18082 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18083 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18085 // Multiply the even parts.
18086 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18087 // Now multiply odd parts.
18088 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18090 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18091 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18093 // Merge the two vectors back together with a shuffle. This expands into 2
18095 static const int ShufMask[] = { 0, 4, 2, 6 };
18096 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18099 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18100 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18102 // Ahi = psrlqi(a, 32);
18103 // Bhi = psrlqi(b, 32);
18105 // AloBlo = pmuludq(a, b);
18106 // AloBhi = pmuludq(a, Bhi);
18107 // AhiBlo = pmuludq(Ahi, b);
18109 // AloBhi = psllqi(AloBhi, 32);
18110 // AhiBlo = psllqi(AhiBlo, 32);
18111 // return AloBlo + AloBhi + AhiBlo;
18113 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18114 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18116 // Bit cast to 32-bit vectors for MULUDQ
18117 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18118 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18119 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18120 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18121 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18122 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18124 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18125 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18126 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18128 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18129 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18131 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18132 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18135 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18136 assert(Subtarget->isTargetWin64() && "Unexpected target");
18137 EVT VT = Op.getValueType();
18138 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18139 "Unexpected return type for lowering");
18143 switch (Op->getOpcode()) {
18144 default: llvm_unreachable("Unexpected request for libcall!");
18145 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18146 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18147 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18148 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18149 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18150 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18154 SDValue InChain = DAG.getEntryNode();
18156 TargetLowering::ArgListTy Args;
18157 TargetLowering::ArgListEntry Entry;
18158 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18159 EVT ArgVT = Op->getOperand(i).getValueType();
18160 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18161 "Unexpected argument type for lowering");
18162 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18163 Entry.Node = StackPtr;
18164 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18166 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18167 Entry.Ty = PointerType::get(ArgTy,0);
18168 Entry.isSExt = false;
18169 Entry.isZExt = false;
18170 Args.push_back(Entry);
18173 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18176 TargetLowering::CallLoweringInfo CLI(DAG);
18177 CLI.setDebugLoc(dl).setChain(InChain)
18178 .setCallee(getLibcallCallingConv(LC),
18179 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18180 Callee, std::move(Args), 0)
18181 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18183 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18184 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18187 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18188 SelectionDAG &DAG) {
18189 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18190 EVT VT = Op0.getValueType();
18193 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18194 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18196 // PMULxD operations multiply each even value (starting at 0) of LHS with
18197 // the related value of RHS and produce a widen result.
18198 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18199 // => <2 x i64> <ae|cg>
18201 // In other word, to have all the results, we need to perform two PMULxD:
18202 // 1. one with the even values.
18203 // 2. one with the odd values.
18204 // To achieve #2, with need to place the odd values at an even position.
18206 // Place the odd value at an even position (basically, shift all values 1
18207 // step to the left):
18208 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18209 // <a|b|c|d> => <b|undef|d|undef>
18210 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18211 // <e|f|g|h> => <f|undef|h|undef>
18212 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18214 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18216 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18217 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18219 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18220 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18221 // => <2 x i64> <ae|cg>
18222 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18223 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18224 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18225 // => <2 x i64> <bf|dh>
18226 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18227 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18229 // Shuffle it back into the right order.
18230 SDValue Highs, Lows;
18231 if (VT == MVT::v8i32) {
18232 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18233 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18234 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18235 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18237 const int HighMask[] = {1, 5, 3, 7};
18238 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18239 const int LowMask[] = {0, 4, 2, 6};
18240 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18243 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18244 // unsigned multiply.
18245 if (IsSigned && !Subtarget->hasSSE41()) {
18247 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18248 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18249 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18250 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18251 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18253 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18254 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18257 // The first result of MUL_LOHI is actually the low value, followed by the
18259 SDValue Ops[] = {Lows, Highs};
18260 return DAG.getMergeValues(Ops, dl);
18263 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18264 const X86Subtarget *Subtarget) {
18265 MVT VT = Op.getSimpleValueType();
18267 SDValue R = Op.getOperand(0);
18268 SDValue Amt = Op.getOperand(1);
18270 // Optimize shl/srl/sra with constant shift amount.
18271 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18272 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18273 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18275 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18276 (Subtarget->hasInt256() &&
18277 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18278 (Subtarget->hasAVX512() &&
18279 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18280 if (Op.getOpcode() == ISD::SHL)
18281 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18283 if (Op.getOpcode() == ISD::SRL)
18284 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18286 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18287 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18291 if (VT == MVT::v16i8) {
18292 if (Op.getOpcode() == ISD::SHL) {
18293 // Make a large shift.
18294 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18295 MVT::v8i16, R, ShiftAmt,
18297 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18298 // Zero out the rightmost bits.
18299 SmallVector<SDValue, 16> V(16,
18300 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18302 return DAG.getNode(ISD::AND, dl, VT, SHL,
18303 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18305 if (Op.getOpcode() == ISD::SRL) {
18306 // Make a large shift.
18307 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18308 MVT::v8i16, R, ShiftAmt,
18310 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18311 // Zero out the leftmost bits.
18312 SmallVector<SDValue, 16> V(16,
18313 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18315 return DAG.getNode(ISD::AND, dl, VT, SRL,
18316 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18318 if (Op.getOpcode() == ISD::SRA) {
18319 if (ShiftAmt == 7) {
18320 // R s>> 7 === R s< 0
18321 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18322 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18325 // R s>> a === ((R u>> a) ^ m) - m
18326 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18327 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18329 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18330 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18331 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18334 llvm_unreachable("Unknown shift opcode.");
18337 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18338 if (Op.getOpcode() == ISD::SHL) {
18339 // Make a large shift.
18340 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18341 MVT::v16i16, R, ShiftAmt,
18343 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18344 // Zero out the rightmost bits.
18345 SmallVector<SDValue, 32> V(32,
18346 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18348 return DAG.getNode(ISD::AND, dl, VT, SHL,
18349 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18351 if (Op.getOpcode() == ISD::SRL) {
18352 // Make a large shift.
18353 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18354 MVT::v16i16, R, ShiftAmt,
18356 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18357 // Zero out the leftmost bits.
18358 SmallVector<SDValue, 32> V(32,
18359 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18361 return DAG.getNode(ISD::AND, dl, VT, SRL,
18362 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18364 if (Op.getOpcode() == ISD::SRA) {
18365 if (ShiftAmt == 7) {
18366 // R s>> 7 === R s< 0
18367 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18368 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18371 // R s>> a === ((R u>> a) ^ m) - m
18372 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18373 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18375 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18376 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18377 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18380 llvm_unreachable("Unknown shift opcode.");
18385 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18386 if (!Subtarget->is64Bit() &&
18387 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18388 Amt.getOpcode() == ISD::BITCAST &&
18389 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18390 Amt = Amt.getOperand(0);
18391 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18392 VT.getVectorNumElements();
18393 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18394 uint64_t ShiftAmt = 0;
18395 for (unsigned i = 0; i != Ratio; ++i) {
18396 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18400 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18402 // Check remaining shift amounts.
18403 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18404 uint64_t ShAmt = 0;
18405 for (unsigned j = 0; j != Ratio; ++j) {
18406 ConstantSDNode *C =
18407 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18411 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18413 if (ShAmt != ShiftAmt)
18416 switch (Op.getOpcode()) {
18418 llvm_unreachable("Unknown shift opcode!");
18420 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18423 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18426 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18434 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18435 const X86Subtarget* Subtarget) {
18436 MVT VT = Op.getSimpleValueType();
18438 SDValue R = Op.getOperand(0);
18439 SDValue Amt = Op.getOperand(1);
18441 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18442 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18443 (Subtarget->hasInt256() &&
18444 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18445 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18446 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18448 EVT EltVT = VT.getVectorElementType();
18450 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18451 unsigned NumElts = VT.getVectorNumElements();
18453 for (i = 0; i != NumElts; ++i) {
18454 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18458 for (j = i; j != NumElts; ++j) {
18459 SDValue Arg = Amt.getOperand(j);
18460 if (Arg.getOpcode() == ISD::UNDEF) continue;
18461 if (Arg != Amt.getOperand(i))
18464 if (i != NumElts && j == NumElts)
18465 BaseShAmt = Amt.getOperand(i);
18467 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18468 Amt = Amt.getOperand(0);
18469 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18470 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18471 SDValue InVec = Amt.getOperand(0);
18472 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18473 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18475 for (; i != NumElts; ++i) {
18476 SDValue Arg = InVec.getOperand(i);
18477 if (Arg.getOpcode() == ISD::UNDEF) continue;
18481 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18482 if (ConstantSDNode *C =
18483 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18484 unsigned SplatIdx =
18485 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18486 if (C->getZExtValue() == SplatIdx)
18487 BaseShAmt = InVec.getOperand(1);
18490 if (!BaseShAmt.getNode())
18491 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18492 DAG.getIntPtrConstant(0));
18496 if (BaseShAmt.getNode()) {
18497 if (EltVT.bitsGT(MVT::i32))
18498 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18499 else if (EltVT.bitsLT(MVT::i32))
18500 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18502 switch (Op.getOpcode()) {
18504 llvm_unreachable("Unknown shift opcode!");
18506 switch (VT.SimpleTy) {
18507 default: return SDValue();
18516 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18519 switch (VT.SimpleTy) {
18520 default: return SDValue();
18527 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18530 switch (VT.SimpleTy) {
18531 default: return SDValue();
18540 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18546 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18547 if (!Subtarget->is64Bit() &&
18548 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18549 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18550 Amt.getOpcode() == ISD::BITCAST &&
18551 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18552 Amt = Amt.getOperand(0);
18553 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18554 VT.getVectorNumElements();
18555 std::vector<SDValue> Vals(Ratio);
18556 for (unsigned i = 0; i != Ratio; ++i)
18557 Vals[i] = Amt.getOperand(i);
18558 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18559 for (unsigned j = 0; j != Ratio; ++j)
18560 if (Vals[j] != Amt.getOperand(i + j))
18563 switch (Op.getOpcode()) {
18565 llvm_unreachable("Unknown shift opcode!");
18567 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18569 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18571 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18578 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18579 SelectionDAG &DAG) {
18580 MVT VT = Op.getSimpleValueType();
18582 SDValue R = Op.getOperand(0);
18583 SDValue Amt = Op.getOperand(1);
18586 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18587 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18589 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18593 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18597 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18599 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18600 if (Subtarget->hasInt256()) {
18601 if (Op.getOpcode() == ISD::SRL &&
18602 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18603 VT == MVT::v4i64 || VT == MVT::v8i32))
18605 if (Op.getOpcode() == ISD::SHL &&
18606 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18607 VT == MVT::v4i64 || VT == MVT::v8i32))
18609 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18613 // If possible, lower this packed shift into a vector multiply instead of
18614 // expanding it into a sequence of scalar shifts.
18615 // Do this only if the vector shift count is a constant build_vector.
18616 if (Op.getOpcode() == ISD::SHL &&
18617 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18618 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18619 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18620 SmallVector<SDValue, 8> Elts;
18621 EVT SVT = VT.getScalarType();
18622 unsigned SVTBits = SVT.getSizeInBits();
18623 const APInt &One = APInt(SVTBits, 1);
18624 unsigned NumElems = VT.getVectorNumElements();
18626 for (unsigned i=0; i !=NumElems; ++i) {
18627 SDValue Op = Amt->getOperand(i);
18628 if (Op->getOpcode() == ISD::UNDEF) {
18629 Elts.push_back(Op);
18633 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18634 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18635 uint64_t ShAmt = C.getZExtValue();
18636 if (ShAmt >= SVTBits) {
18637 Elts.push_back(DAG.getUNDEF(SVT));
18640 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18642 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18643 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18646 // Lower SHL with variable shift amount.
18647 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18648 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18650 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18651 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18652 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18653 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18656 // If possible, lower this shift as a sequence of two shifts by
18657 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18659 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18661 // Could be rewritten as:
18662 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18664 // The advantage is that the two shifts from the example would be
18665 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18666 // the vector shift into four scalar shifts plus four pairs of vector
18668 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18669 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18670 unsigned TargetOpcode = X86ISD::MOVSS;
18671 bool CanBeSimplified;
18672 // The splat value for the first packed shift (the 'X' from the example).
18673 SDValue Amt1 = Amt->getOperand(0);
18674 // The splat value for the second packed shift (the 'Y' from the example).
18675 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18676 Amt->getOperand(2);
18678 // See if it is possible to replace this node with a sequence of
18679 // two shifts followed by a MOVSS/MOVSD
18680 if (VT == MVT::v4i32) {
18681 // Check if it is legal to use a MOVSS.
18682 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18683 Amt2 == Amt->getOperand(3);
18684 if (!CanBeSimplified) {
18685 // Otherwise, check if we can still simplify this node using a MOVSD.
18686 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18687 Amt->getOperand(2) == Amt->getOperand(3);
18688 TargetOpcode = X86ISD::MOVSD;
18689 Amt2 = Amt->getOperand(2);
18692 // Do similar checks for the case where the machine value type
18694 CanBeSimplified = Amt1 == Amt->getOperand(1);
18695 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18696 CanBeSimplified = Amt2 == Amt->getOperand(i);
18698 if (!CanBeSimplified) {
18699 TargetOpcode = X86ISD::MOVSD;
18700 CanBeSimplified = true;
18701 Amt2 = Amt->getOperand(4);
18702 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18703 CanBeSimplified = Amt1 == Amt->getOperand(i);
18704 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18705 CanBeSimplified = Amt2 == Amt->getOperand(j);
18709 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18710 isa<ConstantSDNode>(Amt2)) {
18711 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18712 EVT CastVT = MVT::v4i32;
18714 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18715 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18717 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18718 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18719 if (TargetOpcode == X86ISD::MOVSD)
18720 CastVT = MVT::v2i64;
18721 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18722 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18723 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18725 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18729 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18730 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18733 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18734 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18736 // Turn 'a' into a mask suitable for VSELECT
18737 SDValue VSelM = DAG.getConstant(0x80, VT);
18738 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18739 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18741 SDValue CM1 = DAG.getConstant(0x0f, VT);
18742 SDValue CM2 = DAG.getConstant(0x3f, VT);
18744 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18745 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18746 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18747 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18748 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18751 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18752 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18753 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18755 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18756 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18757 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18758 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18759 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18762 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18763 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18764 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18766 // return VSELECT(r, r+r, a);
18767 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18768 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18772 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18773 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18774 // solution better.
18775 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18776 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18778 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18779 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18780 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18781 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18782 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18785 // Decompose 256-bit shifts into smaller 128-bit shifts.
18786 if (VT.is256BitVector()) {
18787 unsigned NumElems = VT.getVectorNumElements();
18788 MVT EltVT = VT.getVectorElementType();
18789 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18791 // Extract the two vectors
18792 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18793 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18795 // Recreate the shift amount vectors
18796 SDValue Amt1, Amt2;
18797 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18798 // Constant shift amount
18799 SmallVector<SDValue, 4> Amt1Csts;
18800 SmallVector<SDValue, 4> Amt2Csts;
18801 for (unsigned i = 0; i != NumElems/2; ++i)
18802 Amt1Csts.push_back(Amt->getOperand(i));
18803 for (unsigned i = NumElems/2; i != NumElems; ++i)
18804 Amt2Csts.push_back(Amt->getOperand(i));
18806 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18807 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18809 // Variable shift amount
18810 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18811 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18814 // Issue new vector shifts for the smaller types
18815 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18816 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18818 // Concatenate the result back
18819 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18825 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18826 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18827 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18828 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18829 // has only one use.
18830 SDNode *N = Op.getNode();
18831 SDValue LHS = N->getOperand(0);
18832 SDValue RHS = N->getOperand(1);
18833 unsigned BaseOp = 0;
18836 switch (Op.getOpcode()) {
18837 default: llvm_unreachable("Unknown ovf instruction!");
18839 // A subtract of one will be selected as a INC. Note that INC doesn't
18840 // set CF, so we can't do this for UADDO.
18841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18843 BaseOp = X86ISD::INC;
18844 Cond = X86::COND_O;
18847 BaseOp = X86ISD::ADD;
18848 Cond = X86::COND_O;
18851 BaseOp = X86ISD::ADD;
18852 Cond = X86::COND_B;
18855 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18856 // set CF, so we can't do this for USUBO.
18857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18859 BaseOp = X86ISD::DEC;
18860 Cond = X86::COND_O;
18863 BaseOp = X86ISD::SUB;
18864 Cond = X86::COND_O;
18867 BaseOp = X86ISD::SUB;
18868 Cond = X86::COND_B;
18871 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18872 Cond = X86::COND_O;
18874 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18875 if (N->getValueType(0) == MVT::i8) {
18876 BaseOp = X86ISD::UMUL8;
18877 Cond = X86::COND_O;
18880 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18882 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18885 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18886 DAG.getConstant(X86::COND_O, MVT::i32),
18887 SDValue(Sum.getNode(), 2));
18889 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18893 // Also sets EFLAGS.
18894 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18895 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18898 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18899 DAG.getConstant(Cond, MVT::i32),
18900 SDValue(Sum.getNode(), 1));
18902 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18905 // Sign extension of the low part of vector elements. This may be used either
18906 // when sign extend instructions are not available or if the vector element
18907 // sizes already match the sign-extended size. If the vector elements are in
18908 // their pre-extended size and sign extend instructions are available, that will
18909 // be handled by LowerSIGN_EXTEND.
18910 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18911 SelectionDAG &DAG) const {
18913 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18914 MVT VT = Op.getSimpleValueType();
18916 if (!Subtarget->hasSSE2() || !VT.isVector())
18919 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18920 ExtraVT.getScalarType().getSizeInBits();
18922 switch (VT.SimpleTy) {
18923 default: return SDValue();
18926 if (!Subtarget->hasFp256())
18928 if (!Subtarget->hasInt256()) {
18929 // needs to be split
18930 unsigned NumElems = VT.getVectorNumElements();
18932 // Extract the LHS vectors
18933 SDValue LHS = Op.getOperand(0);
18934 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18935 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18937 MVT EltVT = VT.getVectorElementType();
18938 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18940 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18941 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18942 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18944 SDValue Extra = DAG.getValueType(ExtraVT);
18946 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18947 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18949 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18954 SDValue Op0 = Op.getOperand(0);
18956 // This is a sign extension of some low part of vector elements without
18957 // changing the size of the vector elements themselves:
18958 // Shift-Left + Shift-Right-Algebraic.
18959 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18961 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18967 /// Returns true if the operand type is exactly twice the native width, and
18968 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18969 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18970 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18971 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18972 const X86Subtarget &Subtarget =
18973 getTargetMachine().getSubtarget<X86Subtarget>();
18974 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18977 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18978 else if (OpWidth == 128)
18979 return Subtarget.hasCmpxchg16b();
18984 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18985 return needsCmpXchgNb(SI->getValueOperand()->getType());
18988 // Note: this turns large loads into lock cmpxchg8b/16b.
18989 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18990 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18991 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18992 return needsCmpXchgNb(PTy->getElementType());
18995 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18996 const X86Subtarget &Subtarget =
18997 getTargetMachine().getSubtarget<X86Subtarget>();
18998 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18999 const Type *MemType = AI->getType();
19001 // If the operand is too big, we must see if cmpxchg8/16b is available
19002 // and default to library calls otherwise.
19003 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19004 return needsCmpXchgNb(MemType);
19006 AtomicRMWInst::BinOp Op = AI->getOperation();
19009 llvm_unreachable("Unknown atomic operation");
19010 case AtomicRMWInst::Xchg:
19011 case AtomicRMWInst::Add:
19012 case AtomicRMWInst::Sub:
19013 // It's better to use xadd, xsub or xchg for these in all cases.
19015 case AtomicRMWInst::Or:
19016 case AtomicRMWInst::And:
19017 case AtomicRMWInst::Xor:
19018 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19019 // prefix to a normal instruction for these operations.
19020 return !AI->use_empty();
19021 case AtomicRMWInst::Nand:
19022 case AtomicRMWInst::Max:
19023 case AtomicRMWInst::Min:
19024 case AtomicRMWInst::UMax:
19025 case AtomicRMWInst::UMin:
19026 // These always require a non-trivial set of data operations on x86. We must
19027 // use a cmpxchg loop.
19032 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19033 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19034 // no-sse2). There isn't any reason to disable it if the target processor
19036 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19040 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19041 const X86Subtarget &Subtarget =
19042 getTargetMachine().getSubtarget<X86Subtarget>();
19043 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19044 const Type *MemType = AI->getType();
19045 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19046 // there is no benefit in turning such RMWs into loads, and it is actually
19047 // harmful as it introduces a mfence.
19048 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19051 auto Builder = IRBuilder<>(AI);
19052 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19053 auto SynchScope = AI->getSynchScope();
19054 // We must restrict the ordering to avoid generating loads with Release or
19055 // ReleaseAcquire orderings.
19056 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19057 auto Ptr = AI->getPointerOperand();
19059 // Before the load we need a fence. Here is an example lifted from
19060 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19063 // x.store(1, relaxed);
19064 // r1 = y.fetch_add(0, release);
19066 // y.fetch_add(42, acquire);
19067 // r2 = x.load(relaxed);
19068 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19069 // lowered to just a load without a fence. A mfence flushes the store buffer,
19070 // making the optimization clearly correct.
19071 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19072 // otherwise, we might be able to be more agressive on relaxed idempotent
19073 // rmw. In practice, they do not look useful, so we don't try to be
19074 // especially clever.
19075 if (SynchScope == SingleThread) {
19076 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19077 // the IR level, so we must wrap it in an intrinsic.
19079 } else if (hasMFENCE(Subtarget)) {
19080 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19081 Intrinsic::x86_sse2_mfence);
19082 Builder.CreateCall(MFence);
19084 // FIXME: it might make sense to use a locked operation here but on a
19085 // different cache-line to prevent cache-line bouncing. In practice it
19086 // is probably a small win, and x86 processors without mfence are rare
19087 // enough that we do not bother.
19091 // Finally we can emit the atomic load.
19092 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19093 AI->getType()->getPrimitiveSizeInBits());
19094 Loaded->setAtomic(Order, SynchScope);
19095 AI->replaceAllUsesWith(Loaded);
19096 AI->eraseFromParent();
19100 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19101 SelectionDAG &DAG) {
19103 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19104 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19105 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19106 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19108 // The only fence that needs an instruction is a sequentially-consistent
19109 // cross-thread fence.
19110 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19111 if (hasMFENCE(*Subtarget))
19112 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19114 SDValue Chain = Op.getOperand(0);
19115 SDValue Zero = DAG.getConstant(0, MVT::i32);
19117 DAG.getRegister(X86::ESP, MVT::i32), // Base
19118 DAG.getTargetConstant(1, MVT::i8), // Scale
19119 DAG.getRegister(0, MVT::i32), // Index
19120 DAG.getTargetConstant(0, MVT::i32), // Disp
19121 DAG.getRegister(0, MVT::i32), // Segment.
19125 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19126 return SDValue(Res, 0);
19129 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19130 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19133 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19134 SelectionDAG &DAG) {
19135 MVT T = Op.getSimpleValueType();
19139 switch(T.SimpleTy) {
19140 default: llvm_unreachable("Invalid value type!");
19141 case MVT::i8: Reg = X86::AL; size = 1; break;
19142 case MVT::i16: Reg = X86::AX; size = 2; break;
19143 case MVT::i32: Reg = X86::EAX; size = 4; break;
19145 assert(Subtarget->is64Bit() && "Node not type legal!");
19146 Reg = X86::RAX; size = 8;
19149 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19150 Op.getOperand(2), SDValue());
19151 SDValue Ops[] = { cpIn.getValue(0),
19154 DAG.getTargetConstant(size, MVT::i8),
19155 cpIn.getValue(1) };
19156 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19157 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19158 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19162 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19163 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19164 MVT::i32, cpOut.getValue(2));
19165 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19166 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19168 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19169 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19170 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19174 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19175 SelectionDAG &DAG) {
19176 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19177 MVT DstVT = Op.getSimpleValueType();
19179 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19180 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19181 if (DstVT != MVT::f64)
19182 // This conversion needs to be expanded.
19185 SDValue InVec = Op->getOperand(0);
19187 unsigned NumElts = SrcVT.getVectorNumElements();
19188 EVT SVT = SrcVT.getVectorElementType();
19190 // Widen the vector in input in the case of MVT::v2i32.
19191 // Example: from MVT::v2i32 to MVT::v4i32.
19192 SmallVector<SDValue, 16> Elts;
19193 for (unsigned i = 0, e = NumElts; i != e; ++i)
19194 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19195 DAG.getIntPtrConstant(i)));
19197 // Explicitly mark the extra elements as Undef.
19198 SDValue Undef = DAG.getUNDEF(SVT);
19199 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19200 Elts.push_back(Undef);
19202 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19203 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19204 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19205 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19206 DAG.getIntPtrConstant(0));
19209 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19210 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19211 assert((DstVT == MVT::i64 ||
19212 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19213 "Unexpected custom BITCAST");
19214 // i64 <=> MMX conversions are Legal.
19215 if (SrcVT==MVT::i64 && DstVT.isVector())
19217 if (DstVT==MVT::i64 && SrcVT.isVector())
19219 // MMX <=> MMX conversions are Legal.
19220 if (SrcVT.isVector() && DstVT.isVector())
19222 // All other conversions need to be expanded.
19226 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19227 SDNode *Node = Op.getNode();
19229 EVT T = Node->getValueType(0);
19230 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19231 DAG.getConstant(0, T), Node->getOperand(2));
19232 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19233 cast<AtomicSDNode>(Node)->getMemoryVT(),
19234 Node->getOperand(0),
19235 Node->getOperand(1), negOp,
19236 cast<AtomicSDNode>(Node)->getMemOperand(),
19237 cast<AtomicSDNode>(Node)->getOrdering(),
19238 cast<AtomicSDNode>(Node)->getSynchScope());
19241 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19242 SDNode *Node = Op.getNode();
19244 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19246 // Convert seq_cst store -> xchg
19247 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19248 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19249 // (The only way to get a 16-byte store is cmpxchg16b)
19250 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19251 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19252 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19253 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19254 cast<AtomicSDNode>(Node)->getMemoryVT(),
19255 Node->getOperand(0),
19256 Node->getOperand(1), Node->getOperand(2),
19257 cast<AtomicSDNode>(Node)->getMemOperand(),
19258 cast<AtomicSDNode>(Node)->getOrdering(),
19259 cast<AtomicSDNode>(Node)->getSynchScope());
19260 return Swap.getValue(1);
19262 // Other atomic stores have a simple pattern.
19266 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19267 EVT VT = Op.getNode()->getSimpleValueType(0);
19269 // Let legalize expand this if it isn't a legal type yet.
19270 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19273 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19276 bool ExtraOp = false;
19277 switch (Op.getOpcode()) {
19278 default: llvm_unreachable("Invalid code");
19279 case ISD::ADDC: Opc = X86ISD::ADD; break;
19280 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19281 case ISD::SUBC: Opc = X86ISD::SUB; break;
19282 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19286 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19288 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19289 Op.getOperand(1), Op.getOperand(2));
19292 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19293 SelectionDAG &DAG) {
19294 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19296 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19297 // which returns the values as { float, float } (in XMM0) or
19298 // { double, double } (which is returned in XMM0, XMM1).
19300 SDValue Arg = Op.getOperand(0);
19301 EVT ArgVT = Arg.getValueType();
19302 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19304 TargetLowering::ArgListTy Args;
19305 TargetLowering::ArgListEntry Entry;
19309 Entry.isSExt = false;
19310 Entry.isZExt = false;
19311 Args.push_back(Entry);
19313 bool isF64 = ArgVT == MVT::f64;
19314 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19315 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19316 // the results are returned via SRet in memory.
19317 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19318 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19319 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19321 Type *RetTy = isF64
19322 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19323 : (Type*)VectorType::get(ArgTy, 4);
19325 TargetLowering::CallLoweringInfo CLI(DAG);
19326 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19327 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19329 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19332 // Returned in xmm0 and xmm1.
19333 return CallResult.first;
19335 // Returned in bits 0:31 and 32:64 xmm0.
19336 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19337 CallResult.first, DAG.getIntPtrConstant(0));
19338 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19339 CallResult.first, DAG.getIntPtrConstant(1));
19340 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19341 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19344 /// LowerOperation - Provide custom lowering hooks for some operations.
19346 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19347 switch (Op.getOpcode()) {
19348 default: llvm_unreachable("Should not custom lower this!");
19349 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19350 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19351 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19352 return LowerCMP_SWAP(Op, Subtarget, DAG);
19353 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19354 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19355 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19356 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19357 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19358 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19359 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19360 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19361 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19362 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19363 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19364 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19365 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19366 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19367 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19368 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19369 case ISD::SHL_PARTS:
19370 case ISD::SRA_PARTS:
19371 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19372 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19373 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19374 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19375 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19376 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19377 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19378 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19379 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19380 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19381 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19383 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19384 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19385 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19386 case ISD::SETCC: return LowerSETCC(Op, DAG);
19387 case ISD::SELECT: return LowerSELECT(Op, DAG);
19388 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19389 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19390 case ISD::VASTART: return LowerVASTART(Op, DAG);
19391 case ISD::VAARG: return LowerVAARG(Op, DAG);
19392 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19393 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19394 case ISD::INTRINSIC_VOID:
19395 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19396 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19397 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19398 case ISD::FRAME_TO_ARGS_OFFSET:
19399 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19400 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19401 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19402 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19403 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19404 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19405 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19406 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19407 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19408 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19409 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19410 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19411 case ISD::UMUL_LOHI:
19412 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19415 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19421 case ISD::UMULO: return LowerXALUO(Op, DAG);
19422 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19423 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19427 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19428 case ISD::ADD: return LowerADD(Op, DAG);
19429 case ISD::SUB: return LowerSUB(Op, DAG);
19430 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19434 /// ReplaceNodeResults - Replace a node with an illegal result type
19435 /// with a new node built out of custom code.
19436 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19437 SmallVectorImpl<SDValue>&Results,
19438 SelectionDAG &DAG) const {
19440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19441 switch (N->getOpcode()) {
19443 llvm_unreachable("Do not know how to custom type legalize this operation!");
19444 case ISD::SIGN_EXTEND_INREG:
19449 // We don't want to expand or promote these.
19456 case ISD::UDIVREM: {
19457 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19458 Results.push_back(V);
19461 case ISD::FP_TO_SINT:
19462 case ISD::FP_TO_UINT: {
19463 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19465 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19468 std::pair<SDValue,SDValue> Vals =
19469 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19470 SDValue FIST = Vals.first, StackSlot = Vals.second;
19471 if (FIST.getNode()) {
19472 EVT VT = N->getValueType(0);
19473 // Return a load from the stack slot.
19474 if (StackSlot.getNode())
19475 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19476 MachinePointerInfo(),
19477 false, false, false, 0));
19479 Results.push_back(FIST);
19483 case ISD::UINT_TO_FP: {
19484 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19485 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19486 N->getValueType(0) != MVT::v2f32)
19488 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19490 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19492 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19493 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19494 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19495 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19496 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19497 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19500 case ISD::FP_ROUND: {
19501 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19503 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19504 Results.push_back(V);
19507 case ISD::INTRINSIC_W_CHAIN: {
19508 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19510 default : llvm_unreachable("Do not know how to custom type "
19511 "legalize this intrinsic operation!");
19512 case Intrinsic::x86_rdtsc:
19513 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19515 case Intrinsic::x86_rdtscp:
19516 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19518 case Intrinsic::x86_rdpmc:
19519 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19522 case ISD::READCYCLECOUNTER: {
19523 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19526 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19527 EVT T = N->getValueType(0);
19528 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19529 bool Regs64bit = T == MVT::i128;
19530 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19531 SDValue cpInL, cpInH;
19532 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19533 DAG.getConstant(0, HalfT));
19534 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19535 DAG.getConstant(1, HalfT));
19536 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19537 Regs64bit ? X86::RAX : X86::EAX,
19539 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19540 Regs64bit ? X86::RDX : X86::EDX,
19541 cpInH, cpInL.getValue(1));
19542 SDValue swapInL, swapInH;
19543 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19544 DAG.getConstant(0, HalfT));
19545 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19546 DAG.getConstant(1, HalfT));
19547 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19548 Regs64bit ? X86::RBX : X86::EBX,
19549 swapInL, cpInH.getValue(1));
19550 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19551 Regs64bit ? X86::RCX : X86::ECX,
19552 swapInH, swapInL.getValue(1));
19553 SDValue Ops[] = { swapInH.getValue(0),
19555 swapInH.getValue(1) };
19556 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19557 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19558 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19559 X86ISD::LCMPXCHG8_DAG;
19560 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19561 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19562 Regs64bit ? X86::RAX : X86::EAX,
19563 HalfT, Result.getValue(1));
19564 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19565 Regs64bit ? X86::RDX : X86::EDX,
19566 HalfT, cpOutL.getValue(2));
19567 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19569 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19570 MVT::i32, cpOutH.getValue(2));
19572 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19573 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19574 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19576 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19577 Results.push_back(Success);
19578 Results.push_back(EFLAGS.getValue(1));
19581 case ISD::ATOMIC_SWAP:
19582 case ISD::ATOMIC_LOAD_ADD:
19583 case ISD::ATOMIC_LOAD_SUB:
19584 case ISD::ATOMIC_LOAD_AND:
19585 case ISD::ATOMIC_LOAD_OR:
19586 case ISD::ATOMIC_LOAD_XOR:
19587 case ISD::ATOMIC_LOAD_NAND:
19588 case ISD::ATOMIC_LOAD_MIN:
19589 case ISD::ATOMIC_LOAD_MAX:
19590 case ISD::ATOMIC_LOAD_UMIN:
19591 case ISD::ATOMIC_LOAD_UMAX:
19592 case ISD::ATOMIC_LOAD: {
19593 // Delegate to generic TypeLegalization. Situations we can really handle
19594 // should have already been dealt with by AtomicExpandPass.cpp.
19597 case ISD::BITCAST: {
19598 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19599 EVT DstVT = N->getValueType(0);
19600 EVT SrcVT = N->getOperand(0)->getValueType(0);
19602 if (SrcVT != MVT::f64 ||
19603 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19606 unsigned NumElts = DstVT.getVectorNumElements();
19607 EVT SVT = DstVT.getVectorElementType();
19608 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19609 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19610 MVT::v2f64, N->getOperand(0));
19611 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19613 if (ExperimentalVectorWideningLegalization) {
19614 // If we are legalizing vectors by widening, we already have the desired
19615 // legal vector type, just return it.
19616 Results.push_back(ToVecInt);
19620 SmallVector<SDValue, 8> Elts;
19621 for (unsigned i = 0, e = NumElts; i != e; ++i)
19622 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19623 ToVecInt, DAG.getIntPtrConstant(i)));
19625 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19630 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19632 default: return nullptr;
19633 case X86ISD::BSF: return "X86ISD::BSF";
19634 case X86ISD::BSR: return "X86ISD::BSR";
19635 case X86ISD::SHLD: return "X86ISD::SHLD";
19636 case X86ISD::SHRD: return "X86ISD::SHRD";
19637 case X86ISD::FAND: return "X86ISD::FAND";
19638 case X86ISD::FANDN: return "X86ISD::FANDN";
19639 case X86ISD::FOR: return "X86ISD::FOR";
19640 case X86ISD::FXOR: return "X86ISD::FXOR";
19641 case X86ISD::FSRL: return "X86ISD::FSRL";
19642 case X86ISD::FILD: return "X86ISD::FILD";
19643 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19644 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19645 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19646 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19647 case X86ISD::FLD: return "X86ISD::FLD";
19648 case X86ISD::FST: return "X86ISD::FST";
19649 case X86ISD::CALL: return "X86ISD::CALL";
19650 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19651 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19652 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19653 case X86ISD::BT: return "X86ISD::BT";
19654 case X86ISD::CMP: return "X86ISD::CMP";
19655 case X86ISD::COMI: return "X86ISD::COMI";
19656 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19657 case X86ISD::CMPM: return "X86ISD::CMPM";
19658 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19659 case X86ISD::SETCC: return "X86ISD::SETCC";
19660 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19661 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19662 case X86ISD::CMOV: return "X86ISD::CMOV";
19663 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19664 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19665 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19666 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19667 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19668 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19669 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19670 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19671 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19672 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19673 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19674 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19675 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19676 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19677 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19678 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19679 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19680 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19681 case X86ISD::HADD: return "X86ISD::HADD";
19682 case X86ISD::HSUB: return "X86ISD::HSUB";
19683 case X86ISD::FHADD: return "X86ISD::FHADD";
19684 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19685 case X86ISD::UMAX: return "X86ISD::UMAX";
19686 case X86ISD::UMIN: return "X86ISD::UMIN";
19687 case X86ISD::SMAX: return "X86ISD::SMAX";
19688 case X86ISD::SMIN: return "X86ISD::SMIN";
19689 case X86ISD::FMAX: return "X86ISD::FMAX";
19690 case X86ISD::FMIN: return "X86ISD::FMIN";
19691 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19692 case X86ISD::FMINC: return "X86ISD::FMINC";
19693 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19694 case X86ISD::FRCP: return "X86ISD::FRCP";
19695 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19696 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19697 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19698 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19699 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19700 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19701 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19702 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19703 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19704 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19705 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19706 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19707 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19708 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19709 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19710 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19711 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19712 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19713 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19714 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19715 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19716 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19717 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19718 case X86ISD::VSHL: return "X86ISD::VSHL";
19719 case X86ISD::VSRL: return "X86ISD::VSRL";
19720 case X86ISD::VSRA: return "X86ISD::VSRA";
19721 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19722 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19723 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19724 case X86ISD::CMPP: return "X86ISD::CMPP";
19725 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19726 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19727 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19728 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19729 case X86ISD::ADD: return "X86ISD::ADD";
19730 case X86ISD::SUB: return "X86ISD::SUB";
19731 case X86ISD::ADC: return "X86ISD::ADC";
19732 case X86ISD::SBB: return "X86ISD::SBB";
19733 case X86ISD::SMUL: return "X86ISD::SMUL";
19734 case X86ISD::UMUL: return "X86ISD::UMUL";
19735 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19736 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19737 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19738 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19739 case X86ISD::INC: return "X86ISD::INC";
19740 case X86ISD::DEC: return "X86ISD::DEC";
19741 case X86ISD::OR: return "X86ISD::OR";
19742 case X86ISD::XOR: return "X86ISD::XOR";
19743 case X86ISD::AND: return "X86ISD::AND";
19744 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19745 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19746 case X86ISD::PTEST: return "X86ISD::PTEST";
19747 case X86ISD::TESTP: return "X86ISD::TESTP";
19748 case X86ISD::TESTM: return "X86ISD::TESTM";
19749 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19750 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19751 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19752 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19753 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19754 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19755 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19756 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19757 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19758 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19759 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19760 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19761 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19762 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19763 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19764 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19765 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19766 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19767 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19768 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19769 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19770 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19771 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19772 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19773 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19774 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19775 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19776 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19777 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19778 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19779 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19780 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19781 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19782 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19783 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19784 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19785 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19786 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19787 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19788 case X86ISD::SAHF: return "X86ISD::SAHF";
19789 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19790 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19791 case X86ISD::FMADD: return "X86ISD::FMADD";
19792 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19793 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19794 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19795 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19796 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19797 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19798 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19799 case X86ISD::XTEST: return "X86ISD::XTEST";
19803 // isLegalAddressingMode - Return true if the addressing mode represented
19804 // by AM is legal for this target, for a load/store of the specified type.
19805 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19807 // X86 supports extremely general addressing modes.
19808 CodeModel::Model M = getTargetMachine().getCodeModel();
19809 Reloc::Model R = getTargetMachine().getRelocationModel();
19811 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19812 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19817 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19819 // If a reference to this global requires an extra load, we can't fold it.
19820 if (isGlobalStubReference(GVFlags))
19823 // If BaseGV requires a register for the PIC base, we cannot also have a
19824 // BaseReg specified.
19825 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19828 // If lower 4G is not available, then we must use rip-relative addressing.
19829 if ((M != CodeModel::Small || R != Reloc::Static) &&
19830 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19834 switch (AM.Scale) {
19840 // These scales always work.
19845 // These scales are formed with basereg+scalereg. Only accept if there is
19850 default: // Other stuff never works.
19857 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19858 unsigned Bits = Ty->getScalarSizeInBits();
19860 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19861 // particularly cheaper than those without.
19865 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19866 // variable shifts just as cheap as scalar ones.
19867 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19870 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19871 // fully general vector.
19875 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19876 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19878 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19879 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19880 return NumBits1 > NumBits2;
19883 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19884 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19887 if (!isTypeLegal(EVT::getEVT(Ty1)))
19890 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19892 // Assuming the caller doesn't have a zeroext or signext return parameter,
19893 // truncation all the way down to i1 is valid.
19897 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19898 return isInt<32>(Imm);
19901 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19902 // Can also use sub to handle negated immediates.
19903 return isInt<32>(Imm);
19906 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19907 if (!VT1.isInteger() || !VT2.isInteger())
19909 unsigned NumBits1 = VT1.getSizeInBits();
19910 unsigned NumBits2 = VT2.getSizeInBits();
19911 return NumBits1 > NumBits2;
19914 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19915 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19916 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19919 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19920 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19921 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19924 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19925 EVT VT1 = Val.getValueType();
19926 if (isZExtFree(VT1, VT2))
19929 if (Val.getOpcode() != ISD::LOAD)
19932 if (!VT1.isSimple() || !VT1.isInteger() ||
19933 !VT2.isSimple() || !VT2.isInteger())
19936 switch (VT1.getSimpleVT().SimpleTy) {
19941 // X86 has 8, 16, and 32-bit zero-extending loads.
19949 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19950 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19953 VT = VT.getScalarType();
19955 if (!VT.isSimple())
19958 switch (VT.getSimpleVT().SimpleTy) {
19969 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19970 // i16 instructions are longer (0x66 prefix) and potentially slower.
19971 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19974 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19975 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19976 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19977 /// are assumed to be legal.
19979 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19981 if (!VT.isSimple())
19984 MVT SVT = VT.getSimpleVT();
19986 // Very little shuffling can be done for 64-bit vectors right now.
19987 if (VT.getSizeInBits() == 64)
19990 // If this is a single-input shuffle with no 128 bit lane crossings we can
19991 // lower it into pshufb.
19992 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19993 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19994 bool isLegal = true;
19995 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19996 if (M[I] >= (int)SVT.getVectorNumElements() ||
19997 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20006 // FIXME: blends, shifts.
20007 return (SVT.getVectorNumElements() == 2 ||
20008 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20009 isMOVLMask(M, SVT) ||
20010 isCommutedMOVLMask(M, SVT) ||
20011 isMOVHLPSMask(M, SVT) ||
20012 isSHUFPMask(M, SVT) ||
20013 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20014 isPSHUFDMask(M, SVT) ||
20015 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20016 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20017 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20018 isPALIGNRMask(M, SVT, Subtarget) ||
20019 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20020 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20021 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20022 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20023 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20024 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20028 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20030 if (!VT.isSimple())
20033 MVT SVT = VT.getSimpleVT();
20034 unsigned NumElts = SVT.getVectorNumElements();
20035 // FIXME: This collection of masks seems suspect.
20038 if (NumElts == 4 && SVT.is128BitVector()) {
20039 return (isMOVLMask(Mask, SVT) ||
20040 isCommutedMOVLMask(Mask, SVT, true) ||
20041 isSHUFPMask(Mask, SVT) ||
20042 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20043 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20044 Subtarget->hasInt256()));
20049 //===----------------------------------------------------------------------===//
20050 // X86 Scheduler Hooks
20051 //===----------------------------------------------------------------------===//
20053 /// Utility function to emit xbegin specifying the start of an RTM region.
20054 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20055 const TargetInstrInfo *TII) {
20056 DebugLoc DL = MI->getDebugLoc();
20058 const BasicBlock *BB = MBB->getBasicBlock();
20059 MachineFunction::iterator I = MBB;
20062 // For the v = xbegin(), we generate
20073 MachineBasicBlock *thisMBB = MBB;
20074 MachineFunction *MF = MBB->getParent();
20075 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20076 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20077 MF->insert(I, mainMBB);
20078 MF->insert(I, sinkMBB);
20080 // Transfer the remainder of BB and its successor edges to sinkMBB.
20081 sinkMBB->splice(sinkMBB->begin(), MBB,
20082 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20083 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20087 // # fallthrough to mainMBB
20088 // # abortion to sinkMBB
20089 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20090 thisMBB->addSuccessor(mainMBB);
20091 thisMBB->addSuccessor(sinkMBB);
20095 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20096 mainMBB->addSuccessor(sinkMBB);
20099 // EAX is live into the sinkMBB
20100 sinkMBB->addLiveIn(X86::EAX);
20101 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20102 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20105 MI->eraseFromParent();
20109 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20110 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20111 // in the .td file.
20112 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20113 const TargetInstrInfo *TII) {
20115 switch (MI->getOpcode()) {
20116 default: llvm_unreachable("illegal opcode!");
20117 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20118 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20119 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20120 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20121 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20122 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20123 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20124 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20127 DebugLoc dl = MI->getDebugLoc();
20128 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20130 unsigned NumArgs = MI->getNumOperands();
20131 for (unsigned i = 1; i < NumArgs; ++i) {
20132 MachineOperand &Op = MI->getOperand(i);
20133 if (!(Op.isReg() && Op.isImplicit()))
20134 MIB.addOperand(Op);
20136 if (MI->hasOneMemOperand())
20137 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20139 BuildMI(*BB, MI, dl,
20140 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20141 .addReg(X86::XMM0);
20143 MI->eraseFromParent();
20147 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20148 // defs in an instruction pattern
20149 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20150 const TargetInstrInfo *TII) {
20152 switch (MI->getOpcode()) {
20153 default: llvm_unreachable("illegal opcode!");
20154 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20155 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20156 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20157 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20158 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20159 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20160 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20161 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20164 DebugLoc dl = MI->getDebugLoc();
20165 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20167 unsigned NumArgs = MI->getNumOperands(); // remove the results
20168 for (unsigned i = 1; i < NumArgs; ++i) {
20169 MachineOperand &Op = MI->getOperand(i);
20170 if (!(Op.isReg() && Op.isImplicit()))
20171 MIB.addOperand(Op);
20173 if (MI->hasOneMemOperand())
20174 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20176 BuildMI(*BB, MI, dl,
20177 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20180 MI->eraseFromParent();
20184 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20185 const TargetInstrInfo *TII,
20186 const X86Subtarget* Subtarget) {
20187 DebugLoc dl = MI->getDebugLoc();
20189 // Address into RAX/EAX, other two args into ECX, EDX.
20190 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20191 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20192 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20193 for (int i = 0; i < X86::AddrNumOperands; ++i)
20194 MIB.addOperand(MI->getOperand(i));
20196 unsigned ValOps = X86::AddrNumOperands;
20197 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20198 .addReg(MI->getOperand(ValOps).getReg());
20199 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20200 .addReg(MI->getOperand(ValOps+1).getReg());
20202 // The instruction doesn't actually take any operands though.
20203 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20205 MI->eraseFromParent(); // The pseudo is gone now.
20209 MachineBasicBlock *
20210 X86TargetLowering::EmitVAARG64WithCustomInserter(
20212 MachineBasicBlock *MBB) const {
20213 // Emit va_arg instruction on X86-64.
20215 // Operands to this pseudo-instruction:
20216 // 0 ) Output : destination address (reg)
20217 // 1-5) Input : va_list address (addr, i64mem)
20218 // 6 ) ArgSize : Size (in bytes) of vararg type
20219 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20220 // 8 ) Align : Alignment of type
20221 // 9 ) EFLAGS (implicit-def)
20223 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20224 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20226 unsigned DestReg = MI->getOperand(0).getReg();
20227 MachineOperand &Base = MI->getOperand(1);
20228 MachineOperand &Scale = MI->getOperand(2);
20229 MachineOperand &Index = MI->getOperand(3);
20230 MachineOperand &Disp = MI->getOperand(4);
20231 MachineOperand &Segment = MI->getOperand(5);
20232 unsigned ArgSize = MI->getOperand(6).getImm();
20233 unsigned ArgMode = MI->getOperand(7).getImm();
20234 unsigned Align = MI->getOperand(8).getImm();
20236 // Memory Reference
20237 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20238 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20239 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20241 // Machine Information
20242 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20243 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20244 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20245 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20246 DebugLoc DL = MI->getDebugLoc();
20248 // struct va_list {
20251 // i64 overflow_area (address)
20252 // i64 reg_save_area (address)
20254 // sizeof(va_list) = 24
20255 // alignment(va_list) = 8
20257 unsigned TotalNumIntRegs = 6;
20258 unsigned TotalNumXMMRegs = 8;
20259 bool UseGPOffset = (ArgMode == 1);
20260 bool UseFPOffset = (ArgMode == 2);
20261 unsigned MaxOffset = TotalNumIntRegs * 8 +
20262 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20264 /* Align ArgSize to a multiple of 8 */
20265 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20266 bool NeedsAlign = (Align > 8);
20268 MachineBasicBlock *thisMBB = MBB;
20269 MachineBasicBlock *overflowMBB;
20270 MachineBasicBlock *offsetMBB;
20271 MachineBasicBlock *endMBB;
20273 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20274 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20275 unsigned OffsetReg = 0;
20277 if (!UseGPOffset && !UseFPOffset) {
20278 // If we only pull from the overflow region, we don't create a branch.
20279 // We don't need to alter control flow.
20280 OffsetDestReg = 0; // unused
20281 OverflowDestReg = DestReg;
20283 offsetMBB = nullptr;
20284 overflowMBB = thisMBB;
20287 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20288 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20289 // If not, pull from overflow_area. (branch to overflowMBB)
20294 // offsetMBB overflowMBB
20299 // Registers for the PHI in endMBB
20300 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20301 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20303 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20304 MachineFunction *MF = MBB->getParent();
20305 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20306 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20307 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20309 MachineFunction::iterator MBBIter = MBB;
20312 // Insert the new basic blocks
20313 MF->insert(MBBIter, offsetMBB);
20314 MF->insert(MBBIter, overflowMBB);
20315 MF->insert(MBBIter, endMBB);
20317 // Transfer the remainder of MBB and its successor edges to endMBB.
20318 endMBB->splice(endMBB->begin(), thisMBB,
20319 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20320 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20322 // Make offsetMBB and overflowMBB successors of thisMBB
20323 thisMBB->addSuccessor(offsetMBB);
20324 thisMBB->addSuccessor(overflowMBB);
20326 // endMBB is a successor of both offsetMBB and overflowMBB
20327 offsetMBB->addSuccessor(endMBB);
20328 overflowMBB->addSuccessor(endMBB);
20330 // Load the offset value into a register
20331 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20332 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20336 .addDisp(Disp, UseFPOffset ? 4 : 0)
20337 .addOperand(Segment)
20338 .setMemRefs(MMOBegin, MMOEnd);
20340 // Check if there is enough room left to pull this argument.
20341 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20343 .addImm(MaxOffset + 8 - ArgSizeA8);
20345 // Branch to "overflowMBB" if offset >= max
20346 // Fall through to "offsetMBB" otherwise
20347 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20348 .addMBB(overflowMBB);
20351 // In offsetMBB, emit code to use the reg_save_area.
20353 assert(OffsetReg != 0);
20355 // Read the reg_save_area address.
20356 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20357 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20362 .addOperand(Segment)
20363 .setMemRefs(MMOBegin, MMOEnd);
20365 // Zero-extend the offset
20366 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20367 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20370 .addImm(X86::sub_32bit);
20372 // Add the offset to the reg_save_area to get the final address.
20373 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20374 .addReg(OffsetReg64)
20375 .addReg(RegSaveReg);
20377 // Compute the offset for the next argument
20378 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20379 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20381 .addImm(UseFPOffset ? 16 : 8);
20383 // Store it back into the va_list.
20384 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20388 .addDisp(Disp, UseFPOffset ? 4 : 0)
20389 .addOperand(Segment)
20390 .addReg(NextOffsetReg)
20391 .setMemRefs(MMOBegin, MMOEnd);
20394 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20399 // Emit code to use overflow area
20402 // Load the overflow_area address into a register.
20403 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20404 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20409 .addOperand(Segment)
20410 .setMemRefs(MMOBegin, MMOEnd);
20412 // If we need to align it, do so. Otherwise, just copy the address
20413 // to OverflowDestReg.
20415 // Align the overflow address
20416 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20417 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20419 // aligned_addr = (addr + (align-1)) & ~(align-1)
20420 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20421 .addReg(OverflowAddrReg)
20424 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20426 .addImm(~(uint64_t)(Align-1));
20428 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20429 .addReg(OverflowAddrReg);
20432 // Compute the next overflow address after this argument.
20433 // (the overflow address should be kept 8-byte aligned)
20434 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20435 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20436 .addReg(OverflowDestReg)
20437 .addImm(ArgSizeA8);
20439 // Store the new overflow address.
20440 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20445 .addOperand(Segment)
20446 .addReg(NextAddrReg)
20447 .setMemRefs(MMOBegin, MMOEnd);
20449 // If we branched, emit the PHI to the front of endMBB.
20451 BuildMI(*endMBB, endMBB->begin(), DL,
20452 TII->get(X86::PHI), DestReg)
20453 .addReg(OffsetDestReg).addMBB(offsetMBB)
20454 .addReg(OverflowDestReg).addMBB(overflowMBB);
20457 // Erase the pseudo instruction
20458 MI->eraseFromParent();
20463 MachineBasicBlock *
20464 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20466 MachineBasicBlock *MBB) const {
20467 // Emit code to save XMM registers to the stack. The ABI says that the
20468 // number of registers to save is given in %al, so it's theoretically
20469 // possible to do an indirect jump trick to avoid saving all of them,
20470 // however this code takes a simpler approach and just executes all
20471 // of the stores if %al is non-zero. It's less code, and it's probably
20472 // easier on the hardware branch predictor, and stores aren't all that
20473 // expensive anyway.
20475 // Create the new basic blocks. One block contains all the XMM stores,
20476 // and one block is the final destination regardless of whether any
20477 // stores were performed.
20478 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20479 MachineFunction *F = MBB->getParent();
20480 MachineFunction::iterator MBBIter = MBB;
20482 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20483 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20484 F->insert(MBBIter, XMMSaveMBB);
20485 F->insert(MBBIter, EndMBB);
20487 // Transfer the remainder of MBB and its successor edges to EndMBB.
20488 EndMBB->splice(EndMBB->begin(), MBB,
20489 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20490 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20492 // The original block will now fall through to the XMM save block.
20493 MBB->addSuccessor(XMMSaveMBB);
20494 // The XMMSaveMBB will fall through to the end block.
20495 XMMSaveMBB->addSuccessor(EndMBB);
20497 // Now add the instructions.
20498 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20499 DebugLoc DL = MI->getDebugLoc();
20501 unsigned CountReg = MI->getOperand(0).getReg();
20502 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20503 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20505 if (!Subtarget->isTargetWin64()) {
20506 // If %al is 0, branch around the XMM save block.
20507 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20508 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20509 MBB->addSuccessor(EndMBB);
20512 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20513 // that was just emitted, but clearly shouldn't be "saved".
20514 assert((MI->getNumOperands() <= 3 ||
20515 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20516 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20517 && "Expected last argument to be EFLAGS");
20518 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20519 // In the XMM save block, save all the XMM argument registers.
20520 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20521 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20522 MachineMemOperand *MMO =
20523 F->getMachineMemOperand(
20524 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20525 MachineMemOperand::MOStore,
20526 /*Size=*/16, /*Align=*/16);
20527 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20528 .addFrameIndex(RegSaveFrameIndex)
20529 .addImm(/*Scale=*/1)
20530 .addReg(/*IndexReg=*/0)
20531 .addImm(/*Disp=*/Offset)
20532 .addReg(/*Segment=*/0)
20533 .addReg(MI->getOperand(i).getReg())
20534 .addMemOperand(MMO);
20537 MI->eraseFromParent(); // The pseudo instruction is gone now.
20542 // The EFLAGS operand of SelectItr might be missing a kill marker
20543 // because there were multiple uses of EFLAGS, and ISel didn't know
20544 // which to mark. Figure out whether SelectItr should have had a
20545 // kill marker, and set it if it should. Returns the correct kill
20547 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20548 MachineBasicBlock* BB,
20549 const TargetRegisterInfo* TRI) {
20550 // Scan forward through BB for a use/def of EFLAGS.
20551 MachineBasicBlock::iterator miI(std::next(SelectItr));
20552 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20553 const MachineInstr& mi = *miI;
20554 if (mi.readsRegister(X86::EFLAGS))
20556 if (mi.definesRegister(X86::EFLAGS))
20557 break; // Should have kill-flag - update below.
20560 // If we hit the end of the block, check whether EFLAGS is live into a
20562 if (miI == BB->end()) {
20563 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20564 sEnd = BB->succ_end();
20565 sItr != sEnd; ++sItr) {
20566 MachineBasicBlock* succ = *sItr;
20567 if (succ->isLiveIn(X86::EFLAGS))
20572 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20573 // out. SelectMI should have a kill flag on EFLAGS.
20574 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20578 MachineBasicBlock *
20579 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20580 MachineBasicBlock *BB) const {
20581 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20582 DebugLoc DL = MI->getDebugLoc();
20584 // To "insert" a SELECT_CC instruction, we actually have to insert the
20585 // diamond control-flow pattern. The incoming instruction knows the
20586 // destination vreg to set, the condition code register to branch on, the
20587 // true/false values to select between, and a branch opcode to use.
20588 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20589 MachineFunction::iterator It = BB;
20595 // cmpTY ccX, r1, r2
20597 // fallthrough --> copy0MBB
20598 MachineBasicBlock *thisMBB = BB;
20599 MachineFunction *F = BB->getParent();
20600 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20601 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20602 F->insert(It, copy0MBB);
20603 F->insert(It, sinkMBB);
20605 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20606 // live into the sink and copy blocks.
20607 const TargetRegisterInfo *TRI =
20608 BB->getParent()->getSubtarget().getRegisterInfo();
20609 if (!MI->killsRegister(X86::EFLAGS) &&
20610 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20611 copy0MBB->addLiveIn(X86::EFLAGS);
20612 sinkMBB->addLiveIn(X86::EFLAGS);
20615 // Transfer the remainder of BB and its successor edges to sinkMBB.
20616 sinkMBB->splice(sinkMBB->begin(), BB,
20617 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20618 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20620 // Add the true and fallthrough blocks as its successors.
20621 BB->addSuccessor(copy0MBB);
20622 BB->addSuccessor(sinkMBB);
20624 // Create the conditional branch instruction.
20626 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20627 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20630 // %FalseValue = ...
20631 // # fallthrough to sinkMBB
20632 copy0MBB->addSuccessor(sinkMBB);
20635 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20637 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20638 TII->get(X86::PHI), MI->getOperand(0).getReg())
20639 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20640 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20642 MI->eraseFromParent(); // The pseudo instruction is gone now.
20646 MachineBasicBlock *
20647 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20648 MachineBasicBlock *BB) const {
20649 MachineFunction *MF = BB->getParent();
20650 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20651 DebugLoc DL = MI->getDebugLoc();
20652 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20654 assert(MF->shouldSplitStack());
20656 const bool Is64Bit = Subtarget->is64Bit();
20657 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20659 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20660 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20663 // ... [Till the alloca]
20664 // If stacklet is not large enough, jump to mallocMBB
20667 // Allocate by subtracting from RSP
20668 // Jump to continueMBB
20671 // Allocate by call to runtime
20675 // [rest of original BB]
20678 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20679 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20680 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20682 MachineRegisterInfo &MRI = MF->getRegInfo();
20683 const TargetRegisterClass *AddrRegClass =
20684 getRegClassFor(getPointerTy());
20686 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20687 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20688 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20689 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20690 sizeVReg = MI->getOperand(1).getReg(),
20691 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20693 MachineFunction::iterator MBBIter = BB;
20696 MF->insert(MBBIter, bumpMBB);
20697 MF->insert(MBBIter, mallocMBB);
20698 MF->insert(MBBIter, continueMBB);
20700 continueMBB->splice(continueMBB->begin(), BB,
20701 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20702 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20704 // Add code to the main basic block to check if the stack limit has been hit,
20705 // and if so, jump to mallocMBB otherwise to bumpMBB.
20706 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20707 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20708 .addReg(tmpSPVReg).addReg(sizeVReg);
20709 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20710 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20711 .addReg(SPLimitVReg);
20712 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20714 // bumpMBB simply decreases the stack pointer, since we know the current
20715 // stacklet has enough space.
20716 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20717 .addReg(SPLimitVReg);
20718 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20719 .addReg(SPLimitVReg);
20720 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20722 // Calls into a routine in libgcc to allocate more space from the heap.
20723 const uint32_t *RegMask = MF->getTarget()
20724 .getSubtargetImpl()
20725 ->getRegisterInfo()
20726 ->getCallPreservedMask(CallingConv::C);
20728 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20730 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20731 .addExternalSymbol("__morestack_allocate_stack_space")
20732 .addRegMask(RegMask)
20733 .addReg(X86::RDI, RegState::Implicit)
20734 .addReg(X86::RAX, RegState::ImplicitDefine);
20735 } else if (Is64Bit) {
20736 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20738 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20739 .addExternalSymbol("__morestack_allocate_stack_space")
20740 .addRegMask(RegMask)
20741 .addReg(X86::EDI, RegState::Implicit)
20742 .addReg(X86::EAX, RegState::ImplicitDefine);
20744 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20746 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20747 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20748 .addExternalSymbol("__morestack_allocate_stack_space")
20749 .addRegMask(RegMask)
20750 .addReg(X86::EAX, RegState::ImplicitDefine);
20754 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20757 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20758 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20759 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20761 // Set up the CFG correctly.
20762 BB->addSuccessor(bumpMBB);
20763 BB->addSuccessor(mallocMBB);
20764 mallocMBB->addSuccessor(continueMBB);
20765 bumpMBB->addSuccessor(continueMBB);
20767 // Take care of the PHI nodes.
20768 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20769 MI->getOperand(0).getReg())
20770 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20771 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20773 // Delete the original pseudo instruction.
20774 MI->eraseFromParent();
20777 return continueMBB;
20780 MachineBasicBlock *
20781 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20782 MachineBasicBlock *BB) const {
20783 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20784 DebugLoc DL = MI->getDebugLoc();
20786 assert(!Subtarget->isTargetMacho());
20788 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20789 // non-trivial part is impdef of ESP.
20791 if (Subtarget->isTargetWin64()) {
20792 if (Subtarget->isTargetCygMing()) {
20793 // ___chkstk(Mingw64):
20794 // Clobbers R10, R11, RAX and EFLAGS.
20796 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20797 .addExternalSymbol("___chkstk")
20798 .addReg(X86::RAX, RegState::Implicit)
20799 .addReg(X86::RSP, RegState::Implicit)
20800 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20801 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20802 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20804 // __chkstk(MSVCRT): does not update stack pointer.
20805 // Clobbers R10, R11 and EFLAGS.
20806 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20807 .addExternalSymbol("__chkstk")
20808 .addReg(X86::RAX, RegState::Implicit)
20809 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20810 // RAX has the offset to be subtracted from RSP.
20811 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20816 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20817 Subtarget->isTargetWindowsItanium())
20821 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20822 .addExternalSymbol(StackProbeSymbol)
20823 .addReg(X86::EAX, RegState::Implicit)
20824 .addReg(X86::ESP, RegState::Implicit)
20825 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20826 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20827 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20830 MI->eraseFromParent(); // The pseudo instruction is gone now.
20834 MachineBasicBlock *
20835 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20836 MachineBasicBlock *BB) const {
20837 // This is pretty easy. We're taking the value that we received from
20838 // our load from the relocation, sticking it in either RDI (x86-64)
20839 // or EAX and doing an indirect call. The return value will then
20840 // be in the normal return register.
20841 MachineFunction *F = BB->getParent();
20842 const X86InstrInfo *TII =
20843 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20844 DebugLoc DL = MI->getDebugLoc();
20846 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20847 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20849 // Get a register mask for the lowered call.
20850 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20851 // proper register mask.
20852 const uint32_t *RegMask = F->getTarget()
20853 .getSubtargetImpl()
20854 ->getRegisterInfo()
20855 ->getCallPreservedMask(CallingConv::C);
20856 if (Subtarget->is64Bit()) {
20857 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20858 TII->get(X86::MOV64rm), X86::RDI)
20860 .addImm(0).addReg(0)
20861 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20862 MI->getOperand(3).getTargetFlags())
20864 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20865 addDirectMem(MIB, X86::RDI);
20866 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20867 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20868 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20869 TII->get(X86::MOV32rm), X86::EAX)
20871 .addImm(0).addReg(0)
20872 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20873 MI->getOperand(3).getTargetFlags())
20875 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20876 addDirectMem(MIB, X86::EAX);
20877 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20879 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20880 TII->get(X86::MOV32rm), X86::EAX)
20881 .addReg(TII->getGlobalBaseReg(F))
20882 .addImm(0).addReg(0)
20883 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20884 MI->getOperand(3).getTargetFlags())
20886 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20887 addDirectMem(MIB, X86::EAX);
20888 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20891 MI->eraseFromParent(); // The pseudo instruction is gone now.
20895 MachineBasicBlock *
20896 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20897 MachineBasicBlock *MBB) const {
20898 DebugLoc DL = MI->getDebugLoc();
20899 MachineFunction *MF = MBB->getParent();
20900 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20901 MachineRegisterInfo &MRI = MF->getRegInfo();
20903 const BasicBlock *BB = MBB->getBasicBlock();
20904 MachineFunction::iterator I = MBB;
20907 // Memory Reference
20908 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20909 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20912 unsigned MemOpndSlot = 0;
20914 unsigned CurOp = 0;
20916 DstReg = MI->getOperand(CurOp++).getReg();
20917 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20918 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20919 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20920 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20922 MemOpndSlot = CurOp;
20924 MVT PVT = getPointerTy();
20925 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20926 "Invalid Pointer Size!");
20928 // For v = setjmp(buf), we generate
20931 // buf[LabelOffset] = restoreMBB
20932 // SjLjSetup restoreMBB
20938 // v = phi(main, restore)
20941 // if base pointer being used, load it from frame
20944 MachineBasicBlock *thisMBB = MBB;
20945 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20946 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20947 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20948 MF->insert(I, mainMBB);
20949 MF->insert(I, sinkMBB);
20950 MF->push_back(restoreMBB);
20952 MachineInstrBuilder MIB;
20954 // Transfer the remainder of BB and its successor edges to sinkMBB.
20955 sinkMBB->splice(sinkMBB->begin(), MBB,
20956 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20957 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20960 unsigned PtrStoreOpc = 0;
20961 unsigned LabelReg = 0;
20962 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20963 Reloc::Model RM = MF->getTarget().getRelocationModel();
20964 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20965 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20967 // Prepare IP either in reg or imm.
20968 if (!UseImmLabel) {
20969 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20970 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20971 LabelReg = MRI.createVirtualRegister(PtrRC);
20972 if (Subtarget->is64Bit()) {
20973 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20977 .addMBB(restoreMBB)
20980 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20981 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20982 .addReg(XII->getGlobalBaseReg(MF))
20985 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20989 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20991 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20992 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20993 if (i == X86::AddrDisp)
20994 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20996 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20999 MIB.addReg(LabelReg);
21001 MIB.addMBB(restoreMBB);
21002 MIB.setMemRefs(MMOBegin, MMOEnd);
21004 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21005 .addMBB(restoreMBB);
21007 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21008 MF->getSubtarget().getRegisterInfo());
21009 MIB.addRegMask(RegInfo->getNoPreservedMask());
21010 thisMBB->addSuccessor(mainMBB);
21011 thisMBB->addSuccessor(restoreMBB);
21015 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21016 mainMBB->addSuccessor(sinkMBB);
21019 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21020 TII->get(X86::PHI), DstReg)
21021 .addReg(mainDstReg).addMBB(mainMBB)
21022 .addReg(restoreDstReg).addMBB(restoreMBB);
21025 if (RegInfo->hasBasePointer(*MF)) {
21026 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21027 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21028 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21029 X86FI->setRestoreBasePointer(MF);
21030 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21031 unsigned BasePtr = RegInfo->getBaseRegister();
21032 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21033 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21034 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21035 .setMIFlag(MachineInstr::FrameSetup);
21037 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21038 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21039 restoreMBB->addSuccessor(sinkMBB);
21041 MI->eraseFromParent();
21045 MachineBasicBlock *
21046 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21047 MachineBasicBlock *MBB) const {
21048 DebugLoc DL = MI->getDebugLoc();
21049 MachineFunction *MF = MBB->getParent();
21050 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21051 MachineRegisterInfo &MRI = MF->getRegInfo();
21053 // Memory Reference
21054 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21055 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21057 MVT PVT = getPointerTy();
21058 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21059 "Invalid Pointer Size!");
21061 const TargetRegisterClass *RC =
21062 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21063 unsigned Tmp = MRI.createVirtualRegister(RC);
21064 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21065 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21066 MF->getSubtarget().getRegisterInfo());
21067 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21068 unsigned SP = RegInfo->getStackRegister();
21070 MachineInstrBuilder MIB;
21072 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21073 const int64_t SPOffset = 2 * PVT.getStoreSize();
21075 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21076 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21079 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21080 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21081 MIB.addOperand(MI->getOperand(i));
21082 MIB.setMemRefs(MMOBegin, MMOEnd);
21084 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21085 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21086 if (i == X86::AddrDisp)
21087 MIB.addDisp(MI->getOperand(i), LabelOffset);
21089 MIB.addOperand(MI->getOperand(i));
21091 MIB.setMemRefs(MMOBegin, MMOEnd);
21093 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21094 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21095 if (i == X86::AddrDisp)
21096 MIB.addDisp(MI->getOperand(i), SPOffset);
21098 MIB.addOperand(MI->getOperand(i));
21100 MIB.setMemRefs(MMOBegin, MMOEnd);
21102 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21104 MI->eraseFromParent();
21108 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21109 // accumulator loops. Writing back to the accumulator allows the coalescer
21110 // to remove extra copies in the loop.
21111 MachineBasicBlock *
21112 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21113 MachineBasicBlock *MBB) const {
21114 MachineOperand &AddendOp = MI->getOperand(3);
21116 // Bail out early if the addend isn't a register - we can't switch these.
21117 if (!AddendOp.isReg())
21120 MachineFunction &MF = *MBB->getParent();
21121 MachineRegisterInfo &MRI = MF.getRegInfo();
21123 // Check whether the addend is defined by a PHI:
21124 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21125 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21126 if (!AddendDef.isPHI())
21129 // Look for the following pattern:
21131 // %addend = phi [%entry, 0], [%loop, %result]
21133 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21137 // %addend = phi [%entry, 0], [%loop, %result]
21139 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21141 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21142 assert(AddendDef.getOperand(i).isReg());
21143 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21144 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21145 if (&PHISrcInst == MI) {
21146 // Found a matching instruction.
21147 unsigned NewFMAOpc = 0;
21148 switch (MI->getOpcode()) {
21149 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21150 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21151 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21152 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21153 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21154 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21155 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21156 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21157 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21158 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21159 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21160 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21161 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21162 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21163 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21164 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21165 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21166 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21167 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21168 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21170 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21171 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21172 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21173 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21174 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21175 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21176 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21177 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21178 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21179 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21180 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21181 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21182 default: llvm_unreachable("Unrecognized FMA variant.");
21185 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21186 MachineInstrBuilder MIB =
21187 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21188 .addOperand(MI->getOperand(0))
21189 .addOperand(MI->getOperand(3))
21190 .addOperand(MI->getOperand(2))
21191 .addOperand(MI->getOperand(1));
21192 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21193 MI->eraseFromParent();
21200 MachineBasicBlock *
21201 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21202 MachineBasicBlock *BB) const {
21203 switch (MI->getOpcode()) {
21204 default: llvm_unreachable("Unexpected instr type to insert");
21205 case X86::TAILJMPd64:
21206 case X86::TAILJMPr64:
21207 case X86::TAILJMPm64:
21208 llvm_unreachable("TAILJMP64 would not be touched here.");
21209 case X86::TCRETURNdi64:
21210 case X86::TCRETURNri64:
21211 case X86::TCRETURNmi64:
21213 case X86::WIN_ALLOCA:
21214 return EmitLoweredWinAlloca(MI, BB);
21215 case X86::SEG_ALLOCA_32:
21216 case X86::SEG_ALLOCA_64:
21217 return EmitLoweredSegAlloca(MI, BB);
21218 case X86::TLSCall_32:
21219 case X86::TLSCall_64:
21220 return EmitLoweredTLSCall(MI, BB);
21221 case X86::CMOV_GR8:
21222 case X86::CMOV_FR32:
21223 case X86::CMOV_FR64:
21224 case X86::CMOV_V4F32:
21225 case X86::CMOV_V2F64:
21226 case X86::CMOV_V2I64:
21227 case X86::CMOV_V8F32:
21228 case X86::CMOV_V4F64:
21229 case X86::CMOV_V4I64:
21230 case X86::CMOV_V16F32:
21231 case X86::CMOV_V8F64:
21232 case X86::CMOV_V8I64:
21233 case X86::CMOV_GR16:
21234 case X86::CMOV_GR32:
21235 case X86::CMOV_RFP32:
21236 case X86::CMOV_RFP64:
21237 case X86::CMOV_RFP80:
21238 return EmitLoweredSelect(MI, BB);
21240 case X86::FP32_TO_INT16_IN_MEM:
21241 case X86::FP32_TO_INT32_IN_MEM:
21242 case X86::FP32_TO_INT64_IN_MEM:
21243 case X86::FP64_TO_INT16_IN_MEM:
21244 case X86::FP64_TO_INT32_IN_MEM:
21245 case X86::FP64_TO_INT64_IN_MEM:
21246 case X86::FP80_TO_INT16_IN_MEM:
21247 case X86::FP80_TO_INT32_IN_MEM:
21248 case X86::FP80_TO_INT64_IN_MEM: {
21249 MachineFunction *F = BB->getParent();
21250 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21251 DebugLoc DL = MI->getDebugLoc();
21253 // Change the floating point control register to use "round towards zero"
21254 // mode when truncating to an integer value.
21255 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21256 addFrameReference(BuildMI(*BB, MI, DL,
21257 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21259 // Load the old value of the high byte of the control word...
21261 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21262 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21265 // Set the high part to be round to zero...
21266 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21269 // Reload the modified control word now...
21270 addFrameReference(BuildMI(*BB, MI, DL,
21271 TII->get(X86::FLDCW16m)), CWFrameIdx);
21273 // Restore the memory image of control word to original value
21274 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21277 // Get the X86 opcode to use.
21279 switch (MI->getOpcode()) {
21280 default: llvm_unreachable("illegal opcode!");
21281 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21282 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21283 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21284 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21285 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21286 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21287 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21288 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21289 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21293 MachineOperand &Op = MI->getOperand(0);
21295 AM.BaseType = X86AddressMode::RegBase;
21296 AM.Base.Reg = Op.getReg();
21298 AM.BaseType = X86AddressMode::FrameIndexBase;
21299 AM.Base.FrameIndex = Op.getIndex();
21301 Op = MI->getOperand(1);
21303 AM.Scale = Op.getImm();
21304 Op = MI->getOperand(2);
21306 AM.IndexReg = Op.getImm();
21307 Op = MI->getOperand(3);
21308 if (Op.isGlobal()) {
21309 AM.GV = Op.getGlobal();
21311 AM.Disp = Op.getImm();
21313 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21314 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21316 // Reload the original control word now.
21317 addFrameReference(BuildMI(*BB, MI, DL,
21318 TII->get(X86::FLDCW16m)), CWFrameIdx);
21320 MI->eraseFromParent(); // The pseudo instruction is gone now.
21323 // String/text processing lowering.
21324 case X86::PCMPISTRM128REG:
21325 case X86::VPCMPISTRM128REG:
21326 case X86::PCMPISTRM128MEM:
21327 case X86::VPCMPISTRM128MEM:
21328 case X86::PCMPESTRM128REG:
21329 case X86::VPCMPESTRM128REG:
21330 case X86::PCMPESTRM128MEM:
21331 case X86::VPCMPESTRM128MEM:
21332 assert(Subtarget->hasSSE42() &&
21333 "Target must have SSE4.2 or AVX features enabled");
21334 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21336 // String/text processing lowering.
21337 case X86::PCMPISTRIREG:
21338 case X86::VPCMPISTRIREG:
21339 case X86::PCMPISTRIMEM:
21340 case X86::VPCMPISTRIMEM:
21341 case X86::PCMPESTRIREG:
21342 case X86::VPCMPESTRIREG:
21343 case X86::PCMPESTRIMEM:
21344 case X86::VPCMPESTRIMEM:
21345 assert(Subtarget->hasSSE42() &&
21346 "Target must have SSE4.2 or AVX features enabled");
21347 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21349 // Thread synchronization.
21351 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21356 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21358 case X86::VASTART_SAVE_XMM_REGS:
21359 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21361 case X86::VAARG_64:
21362 return EmitVAARG64WithCustomInserter(MI, BB);
21364 case X86::EH_SjLj_SetJmp32:
21365 case X86::EH_SjLj_SetJmp64:
21366 return emitEHSjLjSetJmp(MI, BB);
21368 case X86::EH_SjLj_LongJmp32:
21369 case X86::EH_SjLj_LongJmp64:
21370 return emitEHSjLjLongJmp(MI, BB);
21372 case TargetOpcode::STATEPOINT:
21373 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21374 // this point in the process. We diverge later.
21375 return emitPatchPoint(MI, BB);
21377 case TargetOpcode::STACKMAP:
21378 case TargetOpcode::PATCHPOINT:
21379 return emitPatchPoint(MI, BB);
21381 case X86::VFMADDPDr213r:
21382 case X86::VFMADDPSr213r:
21383 case X86::VFMADDSDr213r:
21384 case X86::VFMADDSSr213r:
21385 case X86::VFMSUBPDr213r:
21386 case X86::VFMSUBPSr213r:
21387 case X86::VFMSUBSDr213r:
21388 case X86::VFMSUBSSr213r:
21389 case X86::VFNMADDPDr213r:
21390 case X86::VFNMADDPSr213r:
21391 case X86::VFNMADDSDr213r:
21392 case X86::VFNMADDSSr213r:
21393 case X86::VFNMSUBPDr213r:
21394 case X86::VFNMSUBPSr213r:
21395 case X86::VFNMSUBSDr213r:
21396 case X86::VFNMSUBSSr213r:
21397 case X86::VFMADDSUBPDr213r:
21398 case X86::VFMADDSUBPSr213r:
21399 case X86::VFMSUBADDPDr213r:
21400 case X86::VFMSUBADDPSr213r:
21401 case X86::VFMADDPDr213rY:
21402 case X86::VFMADDPSr213rY:
21403 case X86::VFMSUBPDr213rY:
21404 case X86::VFMSUBPSr213rY:
21405 case X86::VFNMADDPDr213rY:
21406 case X86::VFNMADDPSr213rY:
21407 case X86::VFNMSUBPDr213rY:
21408 case X86::VFNMSUBPSr213rY:
21409 case X86::VFMADDSUBPDr213rY:
21410 case X86::VFMADDSUBPSr213rY:
21411 case X86::VFMSUBADDPDr213rY:
21412 case X86::VFMSUBADDPSr213rY:
21413 return emitFMA3Instr(MI, BB);
21417 //===----------------------------------------------------------------------===//
21418 // X86 Optimization Hooks
21419 //===----------------------------------------------------------------------===//
21421 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21424 const SelectionDAG &DAG,
21425 unsigned Depth) const {
21426 unsigned BitWidth = KnownZero.getBitWidth();
21427 unsigned Opc = Op.getOpcode();
21428 assert((Opc >= ISD::BUILTIN_OP_END ||
21429 Opc == ISD::INTRINSIC_WO_CHAIN ||
21430 Opc == ISD::INTRINSIC_W_CHAIN ||
21431 Opc == ISD::INTRINSIC_VOID) &&
21432 "Should use MaskedValueIsZero if you don't know whether Op"
21433 " is a target node!");
21435 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21449 // These nodes' second result is a boolean.
21450 if (Op.getResNo() == 0)
21453 case X86ISD::SETCC:
21454 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21456 case ISD::INTRINSIC_WO_CHAIN: {
21457 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21458 unsigned NumLoBits = 0;
21461 case Intrinsic::x86_sse_movmsk_ps:
21462 case Intrinsic::x86_avx_movmsk_ps_256:
21463 case Intrinsic::x86_sse2_movmsk_pd:
21464 case Intrinsic::x86_avx_movmsk_pd_256:
21465 case Intrinsic::x86_mmx_pmovmskb:
21466 case Intrinsic::x86_sse2_pmovmskb_128:
21467 case Intrinsic::x86_avx2_pmovmskb: {
21468 // High bits of movmskp{s|d}, pmovmskb are known zero.
21470 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21471 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21472 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21473 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21474 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21475 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21476 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21477 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21479 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21488 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21490 const SelectionDAG &,
21491 unsigned Depth) const {
21492 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21493 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21494 return Op.getValueType().getScalarType().getSizeInBits();
21500 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21501 /// node is a GlobalAddress + offset.
21502 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21503 const GlobalValue* &GA,
21504 int64_t &Offset) const {
21505 if (N->getOpcode() == X86ISD::Wrapper) {
21506 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21507 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21508 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21512 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21515 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21516 /// same as extracting the high 128-bit part of 256-bit vector and then
21517 /// inserting the result into the low part of a new 256-bit vector
21518 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21519 EVT VT = SVOp->getValueType(0);
21520 unsigned NumElems = VT.getVectorNumElements();
21522 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21523 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21524 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21525 SVOp->getMaskElt(j) >= 0)
21531 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21532 /// same as extracting the low 128-bit part of 256-bit vector and then
21533 /// inserting the result into the high part of a new 256-bit vector
21534 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21535 EVT VT = SVOp->getValueType(0);
21536 unsigned NumElems = VT.getVectorNumElements();
21538 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21539 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21540 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21541 SVOp->getMaskElt(j) >= 0)
21547 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21548 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21549 TargetLowering::DAGCombinerInfo &DCI,
21550 const X86Subtarget* Subtarget) {
21552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21553 SDValue V1 = SVOp->getOperand(0);
21554 SDValue V2 = SVOp->getOperand(1);
21555 EVT VT = SVOp->getValueType(0);
21556 unsigned NumElems = VT.getVectorNumElements();
21558 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21559 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21563 // V UNDEF BUILD_VECTOR UNDEF
21565 // CONCAT_VECTOR CONCAT_VECTOR
21568 // RESULT: V + zero extended
21570 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21571 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21572 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21575 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21578 // To match the shuffle mask, the first half of the mask should
21579 // be exactly the first vector, and all the rest a splat with the
21580 // first element of the second one.
21581 for (unsigned i = 0; i != NumElems/2; ++i)
21582 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21583 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21586 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21587 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21588 if (Ld->hasNUsesOfValue(1, 0)) {
21589 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21590 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21592 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21594 Ld->getPointerInfo(),
21595 Ld->getAlignment(),
21596 false/*isVolatile*/, true/*ReadMem*/,
21597 false/*WriteMem*/);
21599 // Make sure the newly-created LOAD is in the same position as Ld in
21600 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21601 // and update uses of Ld's output chain to use the TokenFactor.
21602 if (Ld->hasAnyUseOfValue(1)) {
21603 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21604 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21605 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21606 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21607 SDValue(ResNode.getNode(), 1));
21610 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21614 // Emit a zeroed vector and insert the desired subvector on its
21616 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21617 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21618 return DCI.CombineTo(N, InsV);
21621 //===--------------------------------------------------------------------===//
21622 // Combine some shuffles into subvector extracts and inserts:
21625 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21626 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21627 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21628 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21629 return DCI.CombineTo(N, InsV);
21632 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21633 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21634 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21635 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21636 return DCI.CombineTo(N, InsV);
21642 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21645 /// This is the leaf of the recursive combinine below. When we have found some
21646 /// chain of single-use x86 shuffle instructions and accumulated the combined
21647 /// shuffle mask represented by them, this will try to pattern match that mask
21648 /// into either a single instruction if there is a special purpose instruction
21649 /// for this operation, or into a PSHUFB instruction which is a fully general
21650 /// instruction but should only be used to replace chains over a certain depth.
21651 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21652 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21653 TargetLowering::DAGCombinerInfo &DCI,
21654 const X86Subtarget *Subtarget) {
21655 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21657 // Find the operand that enters the chain. Note that multiple uses are OK
21658 // here, we're not going to remove the operand we find.
21659 SDValue Input = Op.getOperand(0);
21660 while (Input.getOpcode() == ISD::BITCAST)
21661 Input = Input.getOperand(0);
21663 MVT VT = Input.getSimpleValueType();
21664 MVT RootVT = Root.getSimpleValueType();
21667 // Just remove no-op shuffle masks.
21668 if (Mask.size() == 1) {
21669 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21674 // Use the float domain if the operand type is a floating point type.
21675 bool FloatDomain = VT.isFloatingPoint();
21677 // For floating point shuffles, we don't have free copies in the shuffle
21678 // instructions or the ability to load as part of the instruction, so
21679 // canonicalize their shuffles to UNPCK or MOV variants.
21681 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21682 // vectors because it can have a load folded into it that UNPCK cannot. This
21683 // doesn't preclude something switching to the shorter encoding post-RA.
21685 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21686 bool Lo = Mask.equals(0, 0);
21689 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21690 // is no slower than UNPCKLPD but has the option to fold the input operand
21691 // into even an unaligned memory load.
21692 if (Lo && Subtarget->hasSSE3()) {
21693 Shuffle = X86ISD::MOVDDUP;
21694 ShuffleVT = MVT::v2f64;
21696 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21697 // than the UNPCK variants.
21698 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21699 ShuffleVT = MVT::v4f32;
21701 if (Depth == 1 && Root->getOpcode() == Shuffle)
21702 return false; // Nothing to do!
21703 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21704 DCI.AddToWorklist(Op.getNode());
21705 if (Shuffle == X86ISD::MOVDDUP)
21706 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21708 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21709 DCI.AddToWorklist(Op.getNode());
21710 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21714 if (Subtarget->hasSSE3() &&
21715 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21716 bool Lo = Mask.equals(0, 0, 2, 2);
21717 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21718 MVT ShuffleVT = MVT::v4f32;
21719 if (Depth == 1 && Root->getOpcode() == Shuffle)
21720 return false; // Nothing to do!
21721 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21722 DCI.AddToWorklist(Op.getNode());
21723 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21724 DCI.AddToWorklist(Op.getNode());
21725 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21729 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21730 bool Lo = Mask.equals(0, 0, 1, 1);
21731 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21732 MVT ShuffleVT = MVT::v4f32;
21733 if (Depth == 1 && Root->getOpcode() == Shuffle)
21734 return false; // Nothing to do!
21735 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21736 DCI.AddToWorklist(Op.getNode());
21737 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21738 DCI.AddToWorklist(Op.getNode());
21739 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21745 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21746 // variants as none of these have single-instruction variants that are
21747 // superior to the UNPCK formulation.
21748 if (!FloatDomain &&
21749 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21750 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21751 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21752 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21754 bool Lo = Mask[0] == 0;
21755 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21756 if (Depth == 1 && Root->getOpcode() == Shuffle)
21757 return false; // Nothing to do!
21759 switch (Mask.size()) {
21761 ShuffleVT = MVT::v8i16;
21764 ShuffleVT = MVT::v16i8;
21767 llvm_unreachable("Impossible mask size!");
21769 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21770 DCI.AddToWorklist(Op.getNode());
21771 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21772 DCI.AddToWorklist(Op.getNode());
21773 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21778 // Don't try to re-form single instruction chains under any circumstances now
21779 // that we've done encoding canonicalization for them.
21783 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21784 // can replace them with a single PSHUFB instruction profitably. Intel's
21785 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21786 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21787 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21788 SmallVector<SDValue, 16> PSHUFBMask;
21789 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21790 int Ratio = 16 / Mask.size();
21791 for (unsigned i = 0; i < 16; ++i) {
21792 if (Mask[i / Ratio] == SM_SentinelUndef) {
21793 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21796 int M = Mask[i / Ratio] != SM_SentinelZero
21797 ? Ratio * Mask[i / Ratio] + i % Ratio
21799 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21801 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21802 DCI.AddToWorklist(Op.getNode());
21803 SDValue PSHUFBMaskOp =
21804 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21805 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21806 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21807 DCI.AddToWorklist(Op.getNode());
21808 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21813 // Failed to find any combines.
21817 /// \brief Fully generic combining of x86 shuffle instructions.
21819 /// This should be the last combine run over the x86 shuffle instructions. Once
21820 /// they have been fully optimized, this will recursively consider all chains
21821 /// of single-use shuffle instructions, build a generic model of the cumulative
21822 /// shuffle operation, and check for simpler instructions which implement this
21823 /// operation. We use this primarily for two purposes:
21825 /// 1) Collapse generic shuffles to specialized single instructions when
21826 /// equivalent. In most cases, this is just an encoding size win, but
21827 /// sometimes we will collapse multiple generic shuffles into a single
21828 /// special-purpose shuffle.
21829 /// 2) Look for sequences of shuffle instructions with 3 or more total
21830 /// instructions, and replace them with the slightly more expensive SSSE3
21831 /// PSHUFB instruction if available. We do this as the last combining step
21832 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21833 /// a suitable short sequence of other instructions. The PHUFB will either
21834 /// use a register or have to read from memory and so is slightly (but only
21835 /// slightly) more expensive than the other shuffle instructions.
21837 /// Because this is inherently a quadratic operation (for each shuffle in
21838 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21839 /// This should never be an issue in practice as the shuffle lowering doesn't
21840 /// produce sequences of more than 8 instructions.
21842 /// FIXME: We will currently miss some cases where the redundant shuffling
21843 /// would simplify under the threshold for PSHUFB formation because of
21844 /// combine-ordering. To fix this, we should do the redundant instruction
21845 /// combining in this recursive walk.
21846 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21847 ArrayRef<int> RootMask,
21848 int Depth, bool HasPSHUFB,
21850 TargetLowering::DAGCombinerInfo &DCI,
21851 const X86Subtarget *Subtarget) {
21852 // Bound the depth of our recursive combine because this is ultimately
21853 // quadratic in nature.
21857 // Directly rip through bitcasts to find the underlying operand.
21858 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21859 Op = Op.getOperand(0);
21861 MVT VT = Op.getSimpleValueType();
21862 if (!VT.isVector())
21863 return false; // Bail if we hit a non-vector.
21864 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21865 // version should be added.
21866 if (VT.getSizeInBits() != 128)
21869 assert(Root.getSimpleValueType().isVector() &&
21870 "Shuffles operate on vector types!");
21871 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21872 "Can only combine shuffles of the same vector register size.");
21874 if (!isTargetShuffle(Op.getOpcode()))
21876 SmallVector<int, 16> OpMask;
21878 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21879 // We only can combine unary shuffles which we can decode the mask for.
21880 if (!HaveMask || !IsUnary)
21883 assert(VT.getVectorNumElements() == OpMask.size() &&
21884 "Different mask size from vector size!");
21885 assert(((RootMask.size() > OpMask.size() &&
21886 RootMask.size() % OpMask.size() == 0) ||
21887 (OpMask.size() > RootMask.size() &&
21888 OpMask.size() % RootMask.size() == 0) ||
21889 OpMask.size() == RootMask.size()) &&
21890 "The smaller number of elements must divide the larger.");
21891 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21892 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21893 assert(((RootRatio == 1 && OpRatio == 1) ||
21894 (RootRatio == 1) != (OpRatio == 1)) &&
21895 "Must not have a ratio for both incoming and op masks!");
21897 SmallVector<int, 16> Mask;
21898 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21900 // Merge this shuffle operation's mask into our accumulated mask. Note that
21901 // this shuffle's mask will be the first applied to the input, followed by the
21902 // root mask to get us all the way to the root value arrangement. The reason
21903 // for this order is that we are recursing up the operation chain.
21904 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21905 int RootIdx = i / RootRatio;
21906 if (RootMask[RootIdx] < 0) {
21907 // This is a zero or undef lane, we're done.
21908 Mask.push_back(RootMask[RootIdx]);
21912 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21913 int OpIdx = RootMaskedIdx / OpRatio;
21914 if (OpMask[OpIdx] < 0) {
21915 // The incoming lanes are zero or undef, it doesn't matter which ones we
21917 Mask.push_back(OpMask[OpIdx]);
21921 // Ok, we have non-zero lanes, map them through.
21922 Mask.push_back(OpMask[OpIdx] * OpRatio +
21923 RootMaskedIdx % OpRatio);
21926 // See if we can recurse into the operand to combine more things.
21927 switch (Op.getOpcode()) {
21928 case X86ISD::PSHUFB:
21930 case X86ISD::PSHUFD:
21931 case X86ISD::PSHUFHW:
21932 case X86ISD::PSHUFLW:
21933 if (Op.getOperand(0).hasOneUse() &&
21934 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21935 HasPSHUFB, DAG, DCI, Subtarget))
21939 case X86ISD::UNPCKL:
21940 case X86ISD::UNPCKH:
21941 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21942 // We can't check for single use, we have to check that this shuffle is the only user.
21943 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21944 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21945 HasPSHUFB, DAG, DCI, Subtarget))
21950 // Minor canonicalization of the accumulated shuffle mask to make it easier
21951 // to match below. All this does is detect masks with squential pairs of
21952 // elements, and shrink them to the half-width mask. It does this in a loop
21953 // so it will reduce the size of the mask to the minimal width mask which
21954 // performs an equivalent shuffle.
21955 SmallVector<int, 16> WidenedMask;
21956 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21957 Mask = std::move(WidenedMask);
21958 WidenedMask.clear();
21961 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21965 /// \brief Get the PSHUF-style mask from PSHUF node.
21967 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21968 /// PSHUF-style masks that can be reused with such instructions.
21969 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21970 SmallVector<int, 4> Mask;
21972 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21976 switch (N.getOpcode()) {
21977 case X86ISD::PSHUFD:
21979 case X86ISD::PSHUFLW:
21982 case X86ISD::PSHUFHW:
21983 Mask.erase(Mask.begin(), Mask.begin() + 4);
21984 for (int &M : Mask)
21988 llvm_unreachable("No valid shuffle instruction found!");
21992 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21994 /// We walk up the chain and look for a combinable shuffle, skipping over
21995 /// shuffles that we could hoist this shuffle's transformation past without
21996 /// altering anything.
21998 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22000 TargetLowering::DAGCombinerInfo &DCI) {
22001 assert(N.getOpcode() == X86ISD::PSHUFD &&
22002 "Called with something other than an x86 128-bit half shuffle!");
22005 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22006 // of the shuffles in the chain so that we can form a fresh chain to replace
22008 SmallVector<SDValue, 8> Chain;
22009 SDValue V = N.getOperand(0);
22010 for (; V.hasOneUse(); V = V.getOperand(0)) {
22011 switch (V.getOpcode()) {
22013 return SDValue(); // Nothing combined!
22016 // Skip bitcasts as we always know the type for the target specific
22020 case X86ISD::PSHUFD:
22021 // Found another dword shuffle.
22024 case X86ISD::PSHUFLW:
22025 // Check that the low words (being shuffled) are the identity in the
22026 // dword shuffle, and the high words are self-contained.
22027 if (Mask[0] != 0 || Mask[1] != 1 ||
22028 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22031 Chain.push_back(V);
22034 case X86ISD::PSHUFHW:
22035 // Check that the high words (being shuffled) are the identity in the
22036 // dword shuffle, and the low words are self-contained.
22037 if (Mask[2] != 2 || Mask[3] != 3 ||
22038 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22041 Chain.push_back(V);
22044 case X86ISD::UNPCKL:
22045 case X86ISD::UNPCKH:
22046 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22047 // shuffle into a preceding word shuffle.
22048 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22051 // Search for a half-shuffle which we can combine with.
22052 unsigned CombineOp =
22053 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22054 if (V.getOperand(0) != V.getOperand(1) ||
22055 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22057 Chain.push_back(V);
22058 V = V.getOperand(0);
22060 switch (V.getOpcode()) {
22062 return SDValue(); // Nothing to combine.
22064 case X86ISD::PSHUFLW:
22065 case X86ISD::PSHUFHW:
22066 if (V.getOpcode() == CombineOp)
22069 Chain.push_back(V);
22073 V = V.getOperand(0);
22077 } while (V.hasOneUse());
22080 // Break out of the loop if we break out of the switch.
22084 if (!V.hasOneUse())
22085 // We fell out of the loop without finding a viable combining instruction.
22088 // Merge this node's mask and our incoming mask.
22089 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22090 for (int &M : Mask)
22092 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22093 getV4X86ShuffleImm8ForMask(Mask, DAG));
22095 // Rebuild the chain around this new shuffle.
22096 while (!Chain.empty()) {
22097 SDValue W = Chain.pop_back_val();
22099 if (V.getValueType() != W.getOperand(0).getValueType())
22100 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22102 switch (W.getOpcode()) {
22104 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22106 case X86ISD::UNPCKL:
22107 case X86ISD::UNPCKH:
22108 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22111 case X86ISD::PSHUFD:
22112 case X86ISD::PSHUFLW:
22113 case X86ISD::PSHUFHW:
22114 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22118 if (V.getValueType() != N.getValueType())
22119 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22121 // Return the new chain to replace N.
22125 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22127 /// We walk up the chain, skipping shuffles of the other half and looking
22128 /// through shuffles which switch halves trying to find a shuffle of the same
22129 /// pair of dwords.
22130 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22132 TargetLowering::DAGCombinerInfo &DCI) {
22134 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22135 "Called with something other than an x86 128-bit half shuffle!");
22137 unsigned CombineOpcode = N.getOpcode();
22139 // Walk up a single-use chain looking for a combinable shuffle.
22140 SDValue V = N.getOperand(0);
22141 for (; V.hasOneUse(); V = V.getOperand(0)) {
22142 switch (V.getOpcode()) {
22144 return false; // Nothing combined!
22147 // Skip bitcasts as we always know the type for the target specific
22151 case X86ISD::PSHUFLW:
22152 case X86ISD::PSHUFHW:
22153 if (V.getOpcode() == CombineOpcode)
22156 // Other-half shuffles are no-ops.
22159 // Break out of the loop if we break out of the switch.
22163 if (!V.hasOneUse())
22164 // We fell out of the loop without finding a viable combining instruction.
22167 // Combine away the bottom node as its shuffle will be accumulated into
22168 // a preceding shuffle.
22169 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22171 // Record the old value.
22174 // Merge this node's mask and our incoming mask (adjusted to account for all
22175 // the pshufd instructions encountered).
22176 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22177 for (int &M : Mask)
22179 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22180 getV4X86ShuffleImm8ForMask(Mask, DAG));
22182 // Check that the shuffles didn't cancel each other out. If not, we need to
22183 // combine to the new one.
22185 // Replace the combinable shuffle with the combined one, updating all users
22186 // so that we re-evaluate the chain here.
22187 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22192 /// \brief Try to combine x86 target specific shuffles.
22193 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22194 TargetLowering::DAGCombinerInfo &DCI,
22195 const X86Subtarget *Subtarget) {
22197 MVT VT = N.getSimpleValueType();
22198 SmallVector<int, 4> Mask;
22200 switch (N.getOpcode()) {
22201 case X86ISD::PSHUFD:
22202 case X86ISD::PSHUFLW:
22203 case X86ISD::PSHUFHW:
22204 Mask = getPSHUFShuffleMask(N);
22205 assert(Mask.size() == 4);
22211 // Nuke no-op shuffles that show up after combining.
22212 if (isNoopShuffleMask(Mask))
22213 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22215 // Look for simplifications involving one or two shuffle instructions.
22216 SDValue V = N.getOperand(0);
22217 switch (N.getOpcode()) {
22220 case X86ISD::PSHUFLW:
22221 case X86ISD::PSHUFHW:
22222 assert(VT == MVT::v8i16);
22225 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22226 return SDValue(); // We combined away this shuffle, so we're done.
22228 // See if this reduces to a PSHUFD which is no more expensive and can
22229 // combine with more operations. Note that it has to at least flip the
22230 // dwords as otherwise it would have been removed as a no-op.
22231 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22232 int DMask[] = {0, 1, 2, 3};
22233 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22234 DMask[DOffset + 0] = DOffset + 1;
22235 DMask[DOffset + 1] = DOffset + 0;
22236 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22237 DCI.AddToWorklist(V.getNode());
22238 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22239 getV4X86ShuffleImm8ForMask(DMask, DAG));
22240 DCI.AddToWorklist(V.getNode());
22241 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22244 // Look for shuffle patterns which can be implemented as a single unpack.
22245 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22246 // only works when we have a PSHUFD followed by two half-shuffles.
22247 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22248 (V.getOpcode() == X86ISD::PSHUFLW ||
22249 V.getOpcode() == X86ISD::PSHUFHW) &&
22250 V.getOpcode() != N.getOpcode() &&
22252 SDValue D = V.getOperand(0);
22253 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22254 D = D.getOperand(0);
22255 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22256 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22257 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22258 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22259 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22261 for (int i = 0; i < 4; ++i) {
22262 WordMask[i + NOffset] = Mask[i] + NOffset;
22263 WordMask[i + VOffset] = VMask[i] + VOffset;
22265 // Map the word mask through the DWord mask.
22267 for (int i = 0; i < 8; ++i)
22268 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22269 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22270 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22271 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22272 std::begin(UnpackLoMask)) ||
22273 std::equal(std::begin(MappedMask), std::end(MappedMask),
22274 std::begin(UnpackHiMask))) {
22275 // We can replace all three shuffles with an unpack.
22276 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22277 DCI.AddToWorklist(V.getNode());
22278 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22280 DL, MVT::v8i16, V, V);
22287 case X86ISD::PSHUFD:
22288 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22297 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22299 /// We combine this directly on the abstract vector shuffle nodes so it is
22300 /// easier to generically match. We also insert dummy vector shuffle nodes for
22301 /// the operands which explicitly discard the lanes which are unused by this
22302 /// operation to try to flow through the rest of the combiner the fact that
22303 /// they're unused.
22304 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22306 EVT VT = N->getValueType(0);
22308 // We only handle target-independent shuffles.
22309 // FIXME: It would be easy and harmless to use the target shuffle mask
22310 // extraction tool to support more.
22311 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22314 auto *SVN = cast<ShuffleVectorSDNode>(N);
22315 ArrayRef<int> Mask = SVN->getMask();
22316 SDValue V1 = N->getOperand(0);
22317 SDValue V2 = N->getOperand(1);
22319 // We require the first shuffle operand to be the SUB node, and the second to
22320 // be the ADD node.
22321 // FIXME: We should support the commuted patterns.
22322 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22325 // If there are other uses of these operations we can't fold them.
22326 if (!V1->hasOneUse() || !V2->hasOneUse())
22329 // Ensure that both operations have the same operands. Note that we can
22330 // commute the FADD operands.
22331 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22332 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22333 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22336 // We're looking for blends between FADD and FSUB nodes. We insist on these
22337 // nodes being lined up in a specific expected pattern.
22338 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22339 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22340 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22343 // Only specific types are legal at this point, assert so we notice if and
22344 // when these change.
22345 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22346 VT == MVT::v4f64) &&
22347 "Unknown vector type encountered!");
22349 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22352 /// PerformShuffleCombine - Performs several different shuffle combines.
22353 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22354 TargetLowering::DAGCombinerInfo &DCI,
22355 const X86Subtarget *Subtarget) {
22357 SDValue N0 = N->getOperand(0);
22358 SDValue N1 = N->getOperand(1);
22359 EVT VT = N->getValueType(0);
22361 // Don't create instructions with illegal types after legalize types has run.
22362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22363 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22366 // If we have legalized the vector types, look for blends of FADD and FSUB
22367 // nodes that we can fuse into an ADDSUB node.
22368 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22369 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22372 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22373 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22374 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22375 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22377 // During Type Legalization, when promoting illegal vector types,
22378 // the backend might introduce new shuffle dag nodes and bitcasts.
22380 // This code performs the following transformation:
22381 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22382 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22384 // We do this only if both the bitcast and the BINOP dag nodes have
22385 // one use. Also, perform this transformation only if the new binary
22386 // operation is legal. This is to avoid introducing dag nodes that
22387 // potentially need to be further expanded (or custom lowered) into a
22388 // less optimal sequence of dag nodes.
22389 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22390 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22391 N0.getOpcode() == ISD::BITCAST) {
22392 SDValue BC0 = N0.getOperand(0);
22393 EVT SVT = BC0.getValueType();
22394 unsigned Opcode = BC0.getOpcode();
22395 unsigned NumElts = VT.getVectorNumElements();
22397 if (BC0.hasOneUse() && SVT.isVector() &&
22398 SVT.getVectorNumElements() * 2 == NumElts &&
22399 TLI.isOperationLegal(Opcode, VT)) {
22400 bool CanFold = false;
22412 unsigned SVTNumElts = SVT.getVectorNumElements();
22413 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22414 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22415 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22416 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22417 CanFold = SVOp->getMaskElt(i) < 0;
22420 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22421 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22422 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22423 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22428 // Only handle 128 wide vector from here on.
22429 if (!VT.is128BitVector())
22432 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22433 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22434 // consecutive, non-overlapping, and in the right order.
22435 SmallVector<SDValue, 16> Elts;
22436 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22437 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22439 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22443 if (isTargetShuffle(N->getOpcode())) {
22445 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22446 if (Shuffle.getNode())
22449 // Try recursively combining arbitrary sequences of x86 shuffle
22450 // instructions into higher-order shuffles. We do this after combining
22451 // specific PSHUF instruction sequences into their minimal form so that we
22452 // can evaluate how many specialized shuffle instructions are involved in
22453 // a particular chain.
22454 SmallVector<int, 1> NonceMask; // Just a placeholder.
22455 NonceMask.push_back(0);
22456 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22457 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22459 return SDValue(); // This routine will use CombineTo to replace N.
22465 /// PerformTruncateCombine - Converts truncate operation to
22466 /// a sequence of vector shuffle operations.
22467 /// It is possible when we truncate 256-bit vector to 128-bit vector
22468 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22469 TargetLowering::DAGCombinerInfo &DCI,
22470 const X86Subtarget *Subtarget) {
22474 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22475 /// specific shuffle of a load can be folded into a single element load.
22476 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22477 /// shuffles have been custom lowered so we need to handle those here.
22478 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22479 TargetLowering::DAGCombinerInfo &DCI) {
22480 if (DCI.isBeforeLegalizeOps())
22483 SDValue InVec = N->getOperand(0);
22484 SDValue EltNo = N->getOperand(1);
22486 if (!isa<ConstantSDNode>(EltNo))
22489 EVT OriginalVT = InVec.getValueType();
22491 if (InVec.getOpcode() == ISD::BITCAST) {
22492 // Don't duplicate a load with other uses.
22493 if (!InVec.hasOneUse())
22495 EVT BCVT = InVec.getOperand(0).getValueType();
22496 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22498 InVec = InVec.getOperand(0);
22501 EVT CurrentVT = InVec.getValueType();
22503 if (!isTargetShuffle(InVec.getOpcode()))
22506 // Don't duplicate a load with other uses.
22507 if (!InVec.hasOneUse())
22510 SmallVector<int, 16> ShuffleMask;
22512 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22513 ShuffleMask, UnaryShuffle))
22516 // Select the input vector, guarding against out of range extract vector.
22517 unsigned NumElems = CurrentVT.getVectorNumElements();
22518 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22519 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22520 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22521 : InVec.getOperand(1);
22523 // If inputs to shuffle are the same for both ops, then allow 2 uses
22524 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22526 if (LdNode.getOpcode() == ISD::BITCAST) {
22527 // Don't duplicate a load with other uses.
22528 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22531 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22532 LdNode = LdNode.getOperand(0);
22535 if (!ISD::isNormalLoad(LdNode.getNode()))
22538 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22540 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22543 EVT EltVT = N->getValueType(0);
22544 // If there's a bitcast before the shuffle, check if the load type and
22545 // alignment is valid.
22546 unsigned Align = LN0->getAlignment();
22547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22548 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22549 EltVT.getTypeForEVT(*DAG.getContext()));
22551 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22554 // All checks match so transform back to vector_shuffle so that DAG combiner
22555 // can finish the job
22558 // Create shuffle node taking into account the case that its a unary shuffle
22559 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22560 : InVec.getOperand(1);
22561 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22562 InVec.getOperand(0), Shuffle,
22564 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22565 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22569 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22570 /// generation and convert it from being a bunch of shuffles and extracts
22571 /// to a simple store and scalar loads to extract the elements.
22572 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22573 TargetLowering::DAGCombinerInfo &DCI) {
22574 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22575 if (NewOp.getNode())
22578 SDValue InputVector = N->getOperand(0);
22580 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22581 // from mmx to v2i32 has a single usage.
22582 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22583 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22584 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22585 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22586 N->getValueType(0),
22587 InputVector.getNode()->getOperand(0));
22589 // Only operate on vectors of 4 elements, where the alternative shuffling
22590 // gets to be more expensive.
22591 if (InputVector.getValueType() != MVT::v4i32)
22594 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22595 // single use which is a sign-extend or zero-extend, and all elements are
22597 SmallVector<SDNode *, 4> Uses;
22598 unsigned ExtractedElements = 0;
22599 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22600 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22601 if (UI.getUse().getResNo() != InputVector.getResNo())
22604 SDNode *Extract = *UI;
22605 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22608 if (Extract->getValueType(0) != MVT::i32)
22610 if (!Extract->hasOneUse())
22612 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22613 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22615 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22618 // Record which element was extracted.
22619 ExtractedElements |=
22620 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22622 Uses.push_back(Extract);
22625 // If not all the elements were used, this may not be worthwhile.
22626 if (ExtractedElements != 15)
22629 // Ok, we've now decided to do the transformation.
22630 SDLoc dl(InputVector);
22632 // Store the value to a temporary stack slot.
22633 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22634 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22635 MachinePointerInfo(), false, false, 0);
22637 // Replace each use (extract) with a load of the appropriate element.
22638 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22639 UE = Uses.end(); UI != UE; ++UI) {
22640 SDNode *Extract = *UI;
22642 // cOMpute the element's address.
22643 SDValue Idx = Extract->getOperand(1);
22645 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22646 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22648 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22650 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22651 StackPtr, OffsetVal);
22653 // Load the scalar.
22654 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22655 ScalarAddr, MachinePointerInfo(),
22656 false, false, false, 0);
22658 // Replace the exact with the load.
22659 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22662 // The replacement was made in place; don't return anything.
22666 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22667 static std::pair<unsigned, bool>
22668 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22669 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22670 if (!VT.isVector())
22671 return std::make_pair(0, false);
22673 bool NeedSplit = false;
22674 switch (VT.getSimpleVT().SimpleTy) {
22675 default: return std::make_pair(0, false);
22679 if (!Subtarget->hasAVX2())
22681 if (!Subtarget->hasAVX())
22682 return std::make_pair(0, false);
22687 if (!Subtarget->hasSSE2())
22688 return std::make_pair(0, false);
22691 // SSE2 has only a small subset of the operations.
22692 bool hasUnsigned = Subtarget->hasSSE41() ||
22693 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22694 bool hasSigned = Subtarget->hasSSE41() ||
22695 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22697 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22700 // Check for x CC y ? x : y.
22701 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22702 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22707 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22710 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22713 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22716 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22718 // Check for x CC y ? y : x -- a min/max with reversed arms.
22719 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22720 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22725 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22728 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22731 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22734 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22738 return std::make_pair(Opc, NeedSplit);
22742 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22743 const X86Subtarget *Subtarget) {
22745 SDValue Cond = N->getOperand(0);
22746 SDValue LHS = N->getOperand(1);
22747 SDValue RHS = N->getOperand(2);
22749 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22750 SDValue CondSrc = Cond->getOperand(0);
22751 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22752 Cond = CondSrc->getOperand(0);
22755 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22758 // A vselect where all conditions and data are constants can be optimized into
22759 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22760 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22761 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22764 unsigned MaskValue = 0;
22765 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22768 MVT VT = N->getSimpleValueType(0);
22769 unsigned NumElems = VT.getVectorNumElements();
22770 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22771 for (unsigned i = 0; i < NumElems; ++i) {
22772 // Be sure we emit undef where we can.
22773 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22774 ShuffleMask[i] = -1;
22776 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22779 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22780 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22782 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22785 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22787 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22788 TargetLowering::DAGCombinerInfo &DCI,
22789 const X86Subtarget *Subtarget) {
22791 SDValue Cond = N->getOperand(0);
22792 // Get the LHS/RHS of the select.
22793 SDValue LHS = N->getOperand(1);
22794 SDValue RHS = N->getOperand(2);
22795 EVT VT = LHS.getValueType();
22796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22798 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22799 // instructions match the semantics of the common C idiom x<y?x:y but not
22800 // x<=y?x:y, because of how they handle negative zero (which can be
22801 // ignored in unsafe-math mode).
22802 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22803 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22804 (Subtarget->hasSSE2() ||
22805 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22806 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22808 unsigned Opcode = 0;
22809 // Check for x CC y ? x : y.
22810 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22811 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22815 // Converting this to a min would handle NaNs incorrectly, and swapping
22816 // the operands would cause it to handle comparisons between positive
22817 // and negative zero incorrectly.
22818 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22819 if (!DAG.getTarget().Options.UnsafeFPMath &&
22820 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22822 std::swap(LHS, RHS);
22824 Opcode = X86ISD::FMIN;
22827 // Converting this to a min would handle comparisons between positive
22828 // and negative zero incorrectly.
22829 if (!DAG.getTarget().Options.UnsafeFPMath &&
22830 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22832 Opcode = X86ISD::FMIN;
22835 // Converting this to a min would handle both negative zeros and NaNs
22836 // incorrectly, but we can swap the operands to fix both.
22837 std::swap(LHS, RHS);
22841 Opcode = X86ISD::FMIN;
22845 // Converting this to a max would handle comparisons between positive
22846 // and negative zero incorrectly.
22847 if (!DAG.getTarget().Options.UnsafeFPMath &&
22848 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22850 Opcode = X86ISD::FMAX;
22853 // Converting this to a max would handle NaNs incorrectly, and swapping
22854 // the operands would cause it to handle comparisons between positive
22855 // and negative zero incorrectly.
22856 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22857 if (!DAG.getTarget().Options.UnsafeFPMath &&
22858 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22860 std::swap(LHS, RHS);
22862 Opcode = X86ISD::FMAX;
22865 // Converting this to a max would handle both negative zeros and NaNs
22866 // incorrectly, but we can swap the operands to fix both.
22867 std::swap(LHS, RHS);
22871 Opcode = X86ISD::FMAX;
22874 // Check for x CC y ? y : x -- a min/max with reversed arms.
22875 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22876 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22880 // Converting this to a min would handle comparisons between positive
22881 // and negative zero incorrectly, and swapping the operands would
22882 // cause it to handle NaNs incorrectly.
22883 if (!DAG.getTarget().Options.UnsafeFPMath &&
22884 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22885 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22887 std::swap(LHS, RHS);
22889 Opcode = X86ISD::FMIN;
22892 // Converting this to a min would handle NaNs incorrectly.
22893 if (!DAG.getTarget().Options.UnsafeFPMath &&
22894 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22896 Opcode = X86ISD::FMIN;
22899 // Converting this to a min would handle both negative zeros and NaNs
22900 // incorrectly, but we can swap the operands to fix both.
22901 std::swap(LHS, RHS);
22905 Opcode = X86ISD::FMIN;
22909 // Converting this to a max would handle NaNs incorrectly.
22910 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22912 Opcode = X86ISD::FMAX;
22915 // Converting this to a max would handle comparisons between positive
22916 // and negative zero incorrectly, and swapping the operands would
22917 // cause it to handle NaNs incorrectly.
22918 if (!DAG.getTarget().Options.UnsafeFPMath &&
22919 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22920 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22922 std::swap(LHS, RHS);
22924 Opcode = X86ISD::FMAX;
22927 // Converting this to a max would handle both negative zeros and NaNs
22928 // incorrectly, but we can swap the operands to fix both.
22929 std::swap(LHS, RHS);
22933 Opcode = X86ISD::FMAX;
22939 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22942 EVT CondVT = Cond.getValueType();
22943 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22944 CondVT.getVectorElementType() == MVT::i1) {
22945 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22946 // lowering on KNL. In this case we convert it to
22947 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22948 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22949 // Since SKX these selects have a proper lowering.
22950 EVT OpVT = LHS.getValueType();
22951 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22952 (OpVT.getVectorElementType() == MVT::i8 ||
22953 OpVT.getVectorElementType() == MVT::i16) &&
22954 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22955 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22956 DCI.AddToWorklist(Cond.getNode());
22957 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22960 // If this is a select between two integer constants, try to do some
22962 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22963 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22964 // Don't do this for crazy integer types.
22965 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22966 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22967 // so that TrueC (the true value) is larger than FalseC.
22968 bool NeedsCondInvert = false;
22970 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22971 // Efficiently invertible.
22972 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22973 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22974 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22975 NeedsCondInvert = true;
22976 std::swap(TrueC, FalseC);
22979 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22980 if (FalseC->getAPIntValue() == 0 &&
22981 TrueC->getAPIntValue().isPowerOf2()) {
22982 if (NeedsCondInvert) // Invert the condition if needed.
22983 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22984 DAG.getConstant(1, Cond.getValueType()));
22986 // Zero extend the condition if needed.
22987 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22989 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22990 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22991 DAG.getConstant(ShAmt, MVT::i8));
22994 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22995 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22996 if (NeedsCondInvert) // Invert the condition if needed.
22997 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22998 DAG.getConstant(1, Cond.getValueType()));
23000 // Zero extend the condition if needed.
23001 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23002 FalseC->getValueType(0), Cond);
23003 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23004 SDValue(FalseC, 0));
23007 // Optimize cases that will turn into an LEA instruction. This requires
23008 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23009 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23010 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23011 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23013 bool isFastMultiplier = false;
23015 switch ((unsigned char)Diff) {
23017 case 1: // result = add base, cond
23018 case 2: // result = lea base( , cond*2)
23019 case 3: // result = lea base(cond, cond*2)
23020 case 4: // result = lea base( , cond*4)
23021 case 5: // result = lea base(cond, cond*4)
23022 case 8: // result = lea base( , cond*8)
23023 case 9: // result = lea base(cond, cond*8)
23024 isFastMultiplier = true;
23029 if (isFastMultiplier) {
23030 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23031 if (NeedsCondInvert) // Invert the condition if needed.
23032 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23033 DAG.getConstant(1, Cond.getValueType()));
23035 // Zero extend the condition if needed.
23036 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23038 // Scale the condition by the difference.
23040 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23041 DAG.getConstant(Diff, Cond.getValueType()));
23043 // Add the base if non-zero.
23044 if (FalseC->getAPIntValue() != 0)
23045 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23046 SDValue(FalseC, 0));
23053 // Canonicalize max and min:
23054 // (x > y) ? x : y -> (x >= y) ? x : y
23055 // (x < y) ? x : y -> (x <= y) ? x : y
23056 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23057 // the need for an extra compare
23058 // against zero. e.g.
23059 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23061 // testl %edi, %edi
23063 // cmovgl %edi, %eax
23067 // cmovsl %eax, %edi
23068 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23069 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23070 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23071 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23076 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23077 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23078 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23079 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23084 // Early exit check
23085 if (!TLI.isTypeLegal(VT))
23088 // Match VSELECTs into subs with unsigned saturation.
23089 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23090 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23091 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23092 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23093 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23095 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23096 // left side invert the predicate to simplify logic below.
23098 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23100 CC = ISD::getSetCCInverse(CC, true);
23101 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23105 if (Other.getNode() && Other->getNumOperands() == 2 &&
23106 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23107 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23108 SDValue CondRHS = Cond->getOperand(1);
23110 // Look for a general sub with unsigned saturation first.
23111 // x >= y ? x-y : 0 --> subus x, y
23112 // x > y ? x-y : 0 --> subus x, y
23113 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23114 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23115 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23117 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23118 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23119 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23120 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23121 // If the RHS is a constant we have to reverse the const
23122 // canonicalization.
23123 // x > C-1 ? x+-C : 0 --> subus x, C
23124 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23125 CondRHSConst->getAPIntValue() ==
23126 (-OpRHSConst->getAPIntValue() - 1))
23127 return DAG.getNode(
23128 X86ISD::SUBUS, DL, VT, OpLHS,
23129 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23131 // Another special case: If C was a sign bit, the sub has been
23132 // canonicalized into a xor.
23133 // FIXME: Would it be better to use computeKnownBits to determine
23134 // whether it's safe to decanonicalize the xor?
23135 // x s< 0 ? x^C : 0 --> subus x, C
23136 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23137 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23138 OpRHSConst->getAPIntValue().isSignBit())
23139 // Note that we have to rebuild the RHS constant here to ensure we
23140 // don't rely on particular values of undef lanes.
23141 return DAG.getNode(
23142 X86ISD::SUBUS, DL, VT, OpLHS,
23143 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23148 // Try to match a min/max vector operation.
23149 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23150 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23151 unsigned Opc = ret.first;
23152 bool NeedSplit = ret.second;
23154 if (Opc && NeedSplit) {
23155 unsigned NumElems = VT.getVectorNumElements();
23156 // Extract the LHS vectors
23157 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23158 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23160 // Extract the RHS vectors
23161 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23162 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23164 // Create min/max for each subvector
23165 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23166 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23168 // Merge the result
23169 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23171 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23174 // Simplify vector selection if condition value type matches vselect
23176 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23177 assert(Cond.getValueType().isVector() &&
23178 "vector select expects a vector selector!");
23180 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23181 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23183 // Try invert the condition if true value is not all 1s and false value
23185 if (!TValIsAllOnes && !FValIsAllZeros &&
23186 // Check if the selector will be produced by CMPP*/PCMP*
23187 Cond.getOpcode() == ISD::SETCC &&
23188 // Check if SETCC has already been promoted
23189 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23190 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23191 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23193 if (TValIsAllZeros || FValIsAllOnes) {
23194 SDValue CC = Cond.getOperand(2);
23195 ISD::CondCode NewCC =
23196 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23197 Cond.getOperand(0).getValueType().isInteger());
23198 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23199 std::swap(LHS, RHS);
23200 TValIsAllOnes = FValIsAllOnes;
23201 FValIsAllZeros = TValIsAllZeros;
23205 if (TValIsAllOnes || FValIsAllZeros) {
23208 if (TValIsAllOnes && FValIsAllZeros)
23210 else if (TValIsAllOnes)
23211 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23212 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23213 else if (FValIsAllZeros)
23214 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23215 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23217 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23221 // If we know that this node is legal then we know that it is going to be
23222 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23223 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23224 // to simplify previous instructions.
23225 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23226 !DCI.isBeforeLegalize() &&
23227 // We explicitly check against v8i16 and v16i16 because, although
23228 // they're marked as Custom, they might only be legal when Cond is a
23229 // build_vector of constants. This will be taken care in a later
23231 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23232 VT != MVT::v8i16) &&
23233 // Don't optimize vector of constants. Those are handled by
23234 // the generic code and all the bits must be properly set for
23235 // the generic optimizer.
23236 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23237 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23239 // Don't optimize vector selects that map to mask-registers.
23243 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23244 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23246 APInt KnownZero, KnownOne;
23247 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23248 DCI.isBeforeLegalizeOps());
23249 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23250 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23252 // If we changed the computation somewhere in the DAG, this change
23253 // will affect all users of Cond.
23254 // Make sure it is fine and update all the nodes so that we do not
23255 // use the generic VSELECT anymore. Otherwise, we may perform
23256 // wrong optimizations as we messed up with the actual expectation
23257 // for the vector boolean values.
23258 if (Cond != TLO.Old) {
23259 // Check all uses of that condition operand to check whether it will be
23260 // consumed by non-BLEND instructions, which may depend on all bits are
23262 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23264 if (I->getOpcode() != ISD::VSELECT)
23265 // TODO: Add other opcodes eventually lowered into BLEND.
23268 // Update all the users of the condition, before committing the change,
23269 // so that the VSELECT optimizations that expect the correct vector
23270 // boolean value will not be triggered.
23271 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23273 DAG.ReplaceAllUsesOfValueWith(
23275 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23276 Cond, I->getOperand(1), I->getOperand(2)));
23277 DCI.CommitTargetLoweringOpt(TLO);
23280 // At this point, only Cond is changed. Change the condition
23281 // just for N to keep the opportunity to optimize all other
23282 // users their own way.
23283 DAG.ReplaceAllUsesOfValueWith(
23285 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23286 TLO.New, N->getOperand(1), N->getOperand(2)));
23291 // We should generate an X86ISD::BLENDI from a vselect if its argument
23292 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23293 // constants. This specific pattern gets generated when we split a
23294 // selector for a 512 bit vector in a machine without AVX512 (but with
23295 // 256-bit vectors), during legalization:
23297 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23299 // Iff we find this pattern and the build_vectors are built from
23300 // constants, we translate the vselect into a shuffle_vector that we
23301 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23302 if ((N->getOpcode() == ISD::VSELECT ||
23303 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23304 !DCI.isBeforeLegalize()) {
23305 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23306 if (Shuffle.getNode())
23313 // Check whether a boolean test is testing a boolean value generated by
23314 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23317 // Simplify the following patterns:
23318 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23319 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23320 // to (Op EFLAGS Cond)
23322 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23323 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23324 // to (Op EFLAGS !Cond)
23326 // where Op could be BRCOND or CMOV.
23328 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23329 // Quit if not CMP and SUB with its value result used.
23330 if (Cmp.getOpcode() != X86ISD::CMP &&
23331 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23334 // Quit if not used as a boolean value.
23335 if (CC != X86::COND_E && CC != X86::COND_NE)
23338 // Check CMP operands. One of them should be 0 or 1 and the other should be
23339 // an SetCC or extended from it.
23340 SDValue Op1 = Cmp.getOperand(0);
23341 SDValue Op2 = Cmp.getOperand(1);
23344 const ConstantSDNode* C = nullptr;
23345 bool needOppositeCond = (CC == X86::COND_E);
23346 bool checkAgainstTrue = false; // Is it a comparison against 1?
23348 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23350 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23352 else // Quit if all operands are not constants.
23355 if (C->getZExtValue() == 1) {
23356 needOppositeCond = !needOppositeCond;
23357 checkAgainstTrue = true;
23358 } else if (C->getZExtValue() != 0)
23359 // Quit if the constant is neither 0 or 1.
23362 bool truncatedToBoolWithAnd = false;
23363 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23364 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23365 SetCC.getOpcode() == ISD::TRUNCATE ||
23366 SetCC.getOpcode() == ISD::AND) {
23367 if (SetCC.getOpcode() == ISD::AND) {
23369 ConstantSDNode *CS;
23370 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23371 CS->getZExtValue() == 1)
23373 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23374 CS->getZExtValue() == 1)
23378 SetCC = SetCC.getOperand(OpIdx);
23379 truncatedToBoolWithAnd = true;
23381 SetCC = SetCC.getOperand(0);
23384 switch (SetCC.getOpcode()) {
23385 case X86ISD::SETCC_CARRY:
23386 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23387 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23388 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23389 // truncated to i1 using 'and'.
23390 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23392 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23393 "Invalid use of SETCC_CARRY!");
23395 case X86ISD::SETCC:
23396 // Set the condition code or opposite one if necessary.
23397 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23398 if (needOppositeCond)
23399 CC = X86::GetOppositeBranchCondition(CC);
23400 return SetCC.getOperand(1);
23401 case X86ISD::CMOV: {
23402 // Check whether false/true value has canonical one, i.e. 0 or 1.
23403 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23404 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23405 // Quit if true value is not a constant.
23408 // Quit if false value is not a constant.
23410 SDValue Op = SetCC.getOperand(0);
23411 // Skip 'zext' or 'trunc' node.
23412 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23413 Op.getOpcode() == ISD::TRUNCATE)
23414 Op = Op.getOperand(0);
23415 // A special case for rdrand/rdseed, where 0 is set if false cond is
23417 if ((Op.getOpcode() != X86ISD::RDRAND &&
23418 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23421 // Quit if false value is not the constant 0 or 1.
23422 bool FValIsFalse = true;
23423 if (FVal && FVal->getZExtValue() != 0) {
23424 if (FVal->getZExtValue() != 1)
23426 // If FVal is 1, opposite cond is needed.
23427 needOppositeCond = !needOppositeCond;
23428 FValIsFalse = false;
23430 // Quit if TVal is not the constant opposite of FVal.
23431 if (FValIsFalse && TVal->getZExtValue() != 1)
23433 if (!FValIsFalse && TVal->getZExtValue() != 0)
23435 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23436 if (needOppositeCond)
23437 CC = X86::GetOppositeBranchCondition(CC);
23438 return SetCC.getOperand(3);
23445 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23446 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23447 TargetLowering::DAGCombinerInfo &DCI,
23448 const X86Subtarget *Subtarget) {
23451 // If the flag operand isn't dead, don't touch this CMOV.
23452 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23455 SDValue FalseOp = N->getOperand(0);
23456 SDValue TrueOp = N->getOperand(1);
23457 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23458 SDValue Cond = N->getOperand(3);
23460 if (CC == X86::COND_E || CC == X86::COND_NE) {
23461 switch (Cond.getOpcode()) {
23465 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23466 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23467 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23473 Flags = checkBoolTestSetCCCombine(Cond, CC);
23474 if (Flags.getNode() &&
23475 // Extra check as FCMOV only supports a subset of X86 cond.
23476 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23477 SDValue Ops[] = { FalseOp, TrueOp,
23478 DAG.getConstant(CC, MVT::i8), Flags };
23479 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23482 // If this is a select between two integer constants, try to do some
23483 // optimizations. Note that the operands are ordered the opposite of SELECT
23485 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23486 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23487 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23488 // larger than FalseC (the false value).
23489 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23490 CC = X86::GetOppositeBranchCondition(CC);
23491 std::swap(TrueC, FalseC);
23492 std::swap(TrueOp, FalseOp);
23495 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23496 // This is efficient for any integer data type (including i8/i16) and
23498 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23499 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23500 DAG.getConstant(CC, MVT::i8), Cond);
23502 // Zero extend the condition if needed.
23503 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23505 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23506 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23507 DAG.getConstant(ShAmt, MVT::i8));
23508 if (N->getNumValues() == 2) // Dead flag value?
23509 return DCI.CombineTo(N, Cond, SDValue());
23513 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23514 // for any integer data type, including i8/i16.
23515 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23516 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23517 DAG.getConstant(CC, MVT::i8), Cond);
23519 // Zero extend the condition if needed.
23520 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23521 FalseC->getValueType(0), Cond);
23522 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23523 SDValue(FalseC, 0));
23525 if (N->getNumValues() == 2) // Dead flag value?
23526 return DCI.CombineTo(N, Cond, SDValue());
23530 // Optimize cases that will turn into an LEA instruction. This requires
23531 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23532 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23533 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23534 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23536 bool isFastMultiplier = false;
23538 switch ((unsigned char)Diff) {
23540 case 1: // result = add base, cond
23541 case 2: // result = lea base( , cond*2)
23542 case 3: // result = lea base(cond, cond*2)
23543 case 4: // result = lea base( , cond*4)
23544 case 5: // result = lea base(cond, cond*4)
23545 case 8: // result = lea base( , cond*8)
23546 case 9: // result = lea base(cond, cond*8)
23547 isFastMultiplier = true;
23552 if (isFastMultiplier) {
23553 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23554 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23555 DAG.getConstant(CC, MVT::i8), Cond);
23556 // Zero extend the condition if needed.
23557 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23559 // Scale the condition by the difference.
23561 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23562 DAG.getConstant(Diff, Cond.getValueType()));
23564 // Add the base if non-zero.
23565 if (FalseC->getAPIntValue() != 0)
23566 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23567 SDValue(FalseC, 0));
23568 if (N->getNumValues() == 2) // Dead flag value?
23569 return DCI.CombineTo(N, Cond, SDValue());
23576 // Handle these cases:
23577 // (select (x != c), e, c) -> select (x != c), e, x),
23578 // (select (x == c), c, e) -> select (x == c), x, e)
23579 // where the c is an integer constant, and the "select" is the combination
23580 // of CMOV and CMP.
23582 // The rationale for this change is that the conditional-move from a constant
23583 // needs two instructions, however, conditional-move from a register needs
23584 // only one instruction.
23586 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23587 // some instruction-combining opportunities. This opt needs to be
23588 // postponed as late as possible.
23590 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23591 // the DCI.xxxx conditions are provided to postpone the optimization as
23592 // late as possible.
23594 ConstantSDNode *CmpAgainst = nullptr;
23595 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23596 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23597 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23599 if (CC == X86::COND_NE &&
23600 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23601 CC = X86::GetOppositeBranchCondition(CC);
23602 std::swap(TrueOp, FalseOp);
23605 if (CC == X86::COND_E &&
23606 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23607 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23608 DAG.getConstant(CC, MVT::i8), Cond };
23609 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23617 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23618 const X86Subtarget *Subtarget) {
23619 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23621 default: return SDValue();
23622 // SSE/AVX/AVX2 blend intrinsics.
23623 case Intrinsic::x86_avx2_pblendvb:
23624 case Intrinsic::x86_avx2_pblendw:
23625 case Intrinsic::x86_avx2_pblendd_128:
23626 case Intrinsic::x86_avx2_pblendd_256:
23627 // Don't try to simplify this intrinsic if we don't have AVX2.
23628 if (!Subtarget->hasAVX2())
23631 case Intrinsic::x86_avx_blend_pd_256:
23632 case Intrinsic::x86_avx_blend_ps_256:
23633 case Intrinsic::x86_avx_blendv_pd_256:
23634 case Intrinsic::x86_avx_blendv_ps_256:
23635 // Don't try to simplify this intrinsic if we don't have AVX.
23636 if (!Subtarget->hasAVX())
23639 case Intrinsic::x86_sse41_pblendw:
23640 case Intrinsic::x86_sse41_blendpd:
23641 case Intrinsic::x86_sse41_blendps:
23642 case Intrinsic::x86_sse41_blendvps:
23643 case Intrinsic::x86_sse41_blendvpd:
23644 case Intrinsic::x86_sse41_pblendvb: {
23645 SDValue Op0 = N->getOperand(1);
23646 SDValue Op1 = N->getOperand(2);
23647 SDValue Mask = N->getOperand(3);
23649 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23650 if (!Subtarget->hasSSE41())
23653 // fold (blend A, A, Mask) -> A
23656 // fold (blend A, B, allZeros) -> A
23657 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23659 // fold (blend A, B, allOnes) -> B
23660 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23663 // Simplify the case where the mask is a constant i32 value.
23664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23665 if (C->isNullValue())
23667 if (C->isAllOnesValue())
23674 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23675 case Intrinsic::x86_sse2_psrai_w:
23676 case Intrinsic::x86_sse2_psrai_d:
23677 case Intrinsic::x86_avx2_psrai_w:
23678 case Intrinsic::x86_avx2_psrai_d:
23679 case Intrinsic::x86_sse2_psra_w:
23680 case Intrinsic::x86_sse2_psra_d:
23681 case Intrinsic::x86_avx2_psra_w:
23682 case Intrinsic::x86_avx2_psra_d: {
23683 SDValue Op0 = N->getOperand(1);
23684 SDValue Op1 = N->getOperand(2);
23685 EVT VT = Op0.getValueType();
23686 assert(VT.isVector() && "Expected a vector type!");
23688 if (isa<BuildVectorSDNode>(Op1))
23689 Op1 = Op1.getOperand(0);
23691 if (!isa<ConstantSDNode>(Op1))
23694 EVT SVT = VT.getVectorElementType();
23695 unsigned SVTBits = SVT.getSizeInBits();
23697 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23698 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23699 uint64_t ShAmt = C.getZExtValue();
23701 // Don't try to convert this shift into a ISD::SRA if the shift
23702 // count is bigger than or equal to the element size.
23703 if (ShAmt >= SVTBits)
23706 // Trivial case: if the shift count is zero, then fold this
23707 // into the first operand.
23711 // Replace this packed shift intrinsic with a target independent
23713 SDValue Splat = DAG.getConstant(C, VT);
23714 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23719 /// PerformMulCombine - Optimize a single multiply with constant into two
23720 /// in order to implement it with two cheaper instructions, e.g.
23721 /// LEA + SHL, LEA + LEA.
23722 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23723 TargetLowering::DAGCombinerInfo &DCI) {
23724 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23727 EVT VT = N->getValueType(0);
23728 if (VT != MVT::i64)
23731 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23734 uint64_t MulAmt = C->getZExtValue();
23735 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23738 uint64_t MulAmt1 = 0;
23739 uint64_t MulAmt2 = 0;
23740 if ((MulAmt % 9) == 0) {
23742 MulAmt2 = MulAmt / 9;
23743 } else if ((MulAmt % 5) == 0) {
23745 MulAmt2 = MulAmt / 5;
23746 } else if ((MulAmt % 3) == 0) {
23748 MulAmt2 = MulAmt / 3;
23751 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23754 if (isPowerOf2_64(MulAmt2) &&
23755 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23756 // If second multiplifer is pow2, issue it first. We want the multiply by
23757 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23759 std::swap(MulAmt1, MulAmt2);
23762 if (isPowerOf2_64(MulAmt1))
23763 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23764 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23766 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23767 DAG.getConstant(MulAmt1, VT));
23769 if (isPowerOf2_64(MulAmt2))
23770 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23771 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23773 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23774 DAG.getConstant(MulAmt2, VT));
23776 // Do not add new nodes to DAG combiner worklist.
23777 DCI.CombineTo(N, NewMul, false);
23782 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23783 SDValue N0 = N->getOperand(0);
23784 SDValue N1 = N->getOperand(1);
23785 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23786 EVT VT = N0.getValueType();
23788 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23789 // since the result of setcc_c is all zero's or all ones.
23790 if (VT.isInteger() && !VT.isVector() &&
23791 N1C && N0.getOpcode() == ISD::AND &&
23792 N0.getOperand(1).getOpcode() == ISD::Constant) {
23793 SDValue N00 = N0.getOperand(0);
23794 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23795 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23796 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23797 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23798 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23799 APInt ShAmt = N1C->getAPIntValue();
23800 Mask = Mask.shl(ShAmt);
23802 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23803 N00, DAG.getConstant(Mask, VT));
23807 // Hardware support for vector shifts is sparse which makes us scalarize the
23808 // vector operations in many cases. Also, on sandybridge ADD is faster than
23810 // (shl V, 1) -> add V,V
23811 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23812 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23813 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23814 // We shift all of the values by one. In many cases we do not have
23815 // hardware support for this operation. This is better expressed as an ADD
23817 if (N1SplatC->getZExtValue() == 1)
23818 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23824 /// \brief Returns a vector of 0s if the node in input is a vector logical
23825 /// shift by a constant amount which is known to be bigger than or equal
23826 /// to the vector element size in bits.
23827 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23828 const X86Subtarget *Subtarget) {
23829 EVT VT = N->getValueType(0);
23831 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23832 (!Subtarget->hasInt256() ||
23833 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23836 SDValue Amt = N->getOperand(1);
23838 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23839 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23840 APInt ShiftAmt = AmtSplat->getAPIntValue();
23841 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23843 // SSE2/AVX2 logical shifts always return a vector of 0s
23844 // if the shift amount is bigger than or equal to
23845 // the element size. The constant shift amount will be
23846 // encoded as a 8-bit immediate.
23847 if (ShiftAmt.trunc(8).uge(MaxAmount))
23848 return getZeroVector(VT, Subtarget, DAG, DL);
23854 /// PerformShiftCombine - Combine shifts.
23855 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23856 TargetLowering::DAGCombinerInfo &DCI,
23857 const X86Subtarget *Subtarget) {
23858 if (N->getOpcode() == ISD::SHL) {
23859 SDValue V = PerformSHLCombine(N, DAG);
23860 if (V.getNode()) return V;
23863 if (N->getOpcode() != ISD::SRA) {
23864 // Try to fold this logical shift into a zero vector.
23865 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23866 if (V.getNode()) return V;
23872 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23873 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23874 // and friends. Likewise for OR -> CMPNEQSS.
23875 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23876 TargetLowering::DAGCombinerInfo &DCI,
23877 const X86Subtarget *Subtarget) {
23880 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23881 // we're requiring SSE2 for both.
23882 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23883 SDValue N0 = N->getOperand(0);
23884 SDValue N1 = N->getOperand(1);
23885 SDValue CMP0 = N0->getOperand(1);
23886 SDValue CMP1 = N1->getOperand(1);
23889 // The SETCCs should both refer to the same CMP.
23890 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23893 SDValue CMP00 = CMP0->getOperand(0);
23894 SDValue CMP01 = CMP0->getOperand(1);
23895 EVT VT = CMP00.getValueType();
23897 if (VT == MVT::f32 || VT == MVT::f64) {
23898 bool ExpectingFlags = false;
23899 // Check for any users that want flags:
23900 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23901 !ExpectingFlags && UI != UE; ++UI)
23902 switch (UI->getOpcode()) {
23907 ExpectingFlags = true;
23909 case ISD::CopyToReg:
23910 case ISD::SIGN_EXTEND:
23911 case ISD::ZERO_EXTEND:
23912 case ISD::ANY_EXTEND:
23916 if (!ExpectingFlags) {
23917 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23918 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23920 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23921 X86::CondCode tmp = cc0;
23926 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23927 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23928 // FIXME: need symbolic constants for these magic numbers.
23929 // See X86ATTInstPrinter.cpp:printSSECC().
23930 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23931 if (Subtarget->hasAVX512()) {
23932 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23933 CMP01, DAG.getConstant(x86cc, MVT::i8));
23934 if (N->getValueType(0) != MVT::i1)
23935 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23939 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23940 CMP00.getValueType(), CMP00, CMP01,
23941 DAG.getConstant(x86cc, MVT::i8));
23943 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23944 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23946 if (is64BitFP && !Subtarget->is64Bit()) {
23947 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23948 // 64-bit integer, since that's not a legal type. Since
23949 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23950 // bits, but can do this little dance to extract the lowest 32 bits
23951 // and work with those going forward.
23952 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23954 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23956 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23957 Vector32, DAG.getIntPtrConstant(0));
23961 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23962 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23963 DAG.getConstant(1, IntVT));
23964 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23965 return OneBitOfTruth;
23973 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23974 /// so it can be folded inside ANDNP.
23975 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23976 EVT VT = N->getValueType(0);
23978 // Match direct AllOnes for 128 and 256-bit vectors
23979 if (ISD::isBuildVectorAllOnes(N))
23982 // Look through a bit convert.
23983 if (N->getOpcode() == ISD::BITCAST)
23984 N = N->getOperand(0).getNode();
23986 // Sometimes the operand may come from a insert_subvector building a 256-bit
23988 if (VT.is256BitVector() &&
23989 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23990 SDValue V1 = N->getOperand(0);
23991 SDValue V2 = N->getOperand(1);
23993 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23994 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23995 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23996 ISD::isBuildVectorAllOnes(V2.getNode()))
24003 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24004 // register. In most cases we actually compare or select YMM-sized registers
24005 // and mixing the two types creates horrible code. This method optimizes
24006 // some of the transition sequences.
24007 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24008 TargetLowering::DAGCombinerInfo &DCI,
24009 const X86Subtarget *Subtarget) {
24010 EVT VT = N->getValueType(0);
24011 if (!VT.is256BitVector())
24014 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24015 N->getOpcode() == ISD::ZERO_EXTEND ||
24016 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24018 SDValue Narrow = N->getOperand(0);
24019 EVT NarrowVT = Narrow->getValueType(0);
24020 if (!NarrowVT.is128BitVector())
24023 if (Narrow->getOpcode() != ISD::XOR &&
24024 Narrow->getOpcode() != ISD::AND &&
24025 Narrow->getOpcode() != ISD::OR)
24028 SDValue N0 = Narrow->getOperand(0);
24029 SDValue N1 = Narrow->getOperand(1);
24032 // The Left side has to be a trunc.
24033 if (N0.getOpcode() != ISD::TRUNCATE)
24036 // The type of the truncated inputs.
24037 EVT WideVT = N0->getOperand(0)->getValueType(0);
24041 // The right side has to be a 'trunc' or a constant vector.
24042 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24043 ConstantSDNode *RHSConstSplat = nullptr;
24044 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24045 RHSConstSplat = RHSBV->getConstantSplatNode();
24046 if (!RHSTrunc && !RHSConstSplat)
24049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24051 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24054 // Set N0 and N1 to hold the inputs to the new wide operation.
24055 N0 = N0->getOperand(0);
24056 if (RHSConstSplat) {
24057 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24058 SDValue(RHSConstSplat, 0));
24059 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24060 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24061 } else if (RHSTrunc) {
24062 N1 = N1->getOperand(0);
24065 // Generate the wide operation.
24066 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24067 unsigned Opcode = N->getOpcode();
24069 case ISD::ANY_EXTEND:
24071 case ISD::ZERO_EXTEND: {
24072 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24073 APInt Mask = APInt::getAllOnesValue(InBits);
24074 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24075 return DAG.getNode(ISD::AND, DL, VT,
24076 Op, DAG.getConstant(Mask, VT));
24078 case ISD::SIGN_EXTEND:
24079 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24080 Op, DAG.getValueType(NarrowVT));
24082 llvm_unreachable("Unexpected opcode");
24086 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24087 TargetLowering::DAGCombinerInfo &DCI,
24088 const X86Subtarget *Subtarget) {
24089 EVT VT = N->getValueType(0);
24090 if (DCI.isBeforeLegalizeOps())
24093 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24097 // Create BEXTR instructions
24098 // BEXTR is ((X >> imm) & (2**size-1))
24099 if (VT == MVT::i32 || VT == MVT::i64) {
24100 SDValue N0 = N->getOperand(0);
24101 SDValue N1 = N->getOperand(1);
24104 // Check for BEXTR.
24105 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24106 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24107 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24108 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24109 if (MaskNode && ShiftNode) {
24110 uint64_t Mask = MaskNode->getZExtValue();
24111 uint64_t Shift = ShiftNode->getZExtValue();
24112 if (isMask_64(Mask)) {
24113 uint64_t MaskSize = CountPopulation_64(Mask);
24114 if (Shift + MaskSize <= VT.getSizeInBits())
24115 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24116 DAG.getConstant(Shift | (MaskSize << 8), VT));
24124 // Want to form ANDNP nodes:
24125 // 1) In the hopes of then easily combining them with OR and AND nodes
24126 // to form PBLEND/PSIGN.
24127 // 2) To match ANDN packed intrinsics
24128 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24131 SDValue N0 = N->getOperand(0);
24132 SDValue N1 = N->getOperand(1);
24135 // Check LHS for vnot
24136 if (N0.getOpcode() == ISD::XOR &&
24137 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24138 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24139 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24141 // Check RHS for vnot
24142 if (N1.getOpcode() == ISD::XOR &&
24143 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24144 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24145 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24150 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24151 TargetLowering::DAGCombinerInfo &DCI,
24152 const X86Subtarget *Subtarget) {
24153 if (DCI.isBeforeLegalizeOps())
24156 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24160 SDValue N0 = N->getOperand(0);
24161 SDValue N1 = N->getOperand(1);
24162 EVT VT = N->getValueType(0);
24164 // look for psign/blend
24165 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24166 if (!Subtarget->hasSSSE3() ||
24167 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24170 // Canonicalize pandn to RHS
24171 if (N0.getOpcode() == X86ISD::ANDNP)
24173 // or (and (m, y), (pandn m, x))
24174 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24175 SDValue Mask = N1.getOperand(0);
24176 SDValue X = N1.getOperand(1);
24178 if (N0.getOperand(0) == Mask)
24179 Y = N0.getOperand(1);
24180 if (N0.getOperand(1) == Mask)
24181 Y = N0.getOperand(0);
24183 // Check to see if the mask appeared in both the AND and ANDNP and
24187 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24188 // Look through mask bitcast.
24189 if (Mask.getOpcode() == ISD::BITCAST)
24190 Mask = Mask.getOperand(0);
24191 if (X.getOpcode() == ISD::BITCAST)
24192 X = X.getOperand(0);
24193 if (Y.getOpcode() == ISD::BITCAST)
24194 Y = Y.getOperand(0);
24196 EVT MaskVT = Mask.getValueType();
24198 // Validate that the Mask operand is a vector sra node.
24199 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24200 // there is no psrai.b
24201 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24202 unsigned SraAmt = ~0;
24203 if (Mask.getOpcode() == ISD::SRA) {
24204 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24205 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24206 SraAmt = AmtConst->getZExtValue();
24207 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24208 SDValue SraC = Mask.getOperand(1);
24209 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24211 if ((SraAmt + 1) != EltBits)
24216 // Now we know we at least have a plendvb with the mask val. See if
24217 // we can form a psignb/w/d.
24218 // psign = x.type == y.type == mask.type && y = sub(0, x);
24219 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24220 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24221 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24222 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24223 "Unsupported VT for PSIGN");
24224 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24225 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24227 // PBLENDVB only available on SSE 4.1
24228 if (!Subtarget->hasSSE41())
24231 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24233 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24234 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24235 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24236 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24237 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24241 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24244 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24245 MachineFunction &MF = DAG.getMachineFunction();
24246 bool OptForSize = MF.getFunction()->getAttributes().
24247 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24249 // SHLD/SHRD instructions have lower register pressure, but on some
24250 // platforms they have higher latency than the equivalent
24251 // series of shifts/or that would otherwise be generated.
24252 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24253 // have higher latencies and we are not optimizing for size.
24254 if (!OptForSize && Subtarget->isSHLDSlow())
24257 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24259 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24261 if (!N0.hasOneUse() || !N1.hasOneUse())
24264 SDValue ShAmt0 = N0.getOperand(1);
24265 if (ShAmt0.getValueType() != MVT::i8)
24267 SDValue ShAmt1 = N1.getOperand(1);
24268 if (ShAmt1.getValueType() != MVT::i8)
24270 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24271 ShAmt0 = ShAmt0.getOperand(0);
24272 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24273 ShAmt1 = ShAmt1.getOperand(0);
24276 unsigned Opc = X86ISD::SHLD;
24277 SDValue Op0 = N0.getOperand(0);
24278 SDValue Op1 = N1.getOperand(0);
24279 if (ShAmt0.getOpcode() == ISD::SUB) {
24280 Opc = X86ISD::SHRD;
24281 std::swap(Op0, Op1);
24282 std::swap(ShAmt0, ShAmt1);
24285 unsigned Bits = VT.getSizeInBits();
24286 if (ShAmt1.getOpcode() == ISD::SUB) {
24287 SDValue Sum = ShAmt1.getOperand(0);
24288 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24289 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24290 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24291 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24292 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24293 return DAG.getNode(Opc, DL, VT,
24295 DAG.getNode(ISD::TRUNCATE, DL,
24298 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24299 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24301 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24302 return DAG.getNode(Opc, DL, VT,
24303 N0.getOperand(0), N1.getOperand(0),
24304 DAG.getNode(ISD::TRUNCATE, DL,
24311 // Generate NEG and CMOV for integer abs.
24312 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24313 EVT VT = N->getValueType(0);
24315 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24316 // 8-bit integer abs to NEG and CMOV.
24317 if (VT.isInteger() && VT.getSizeInBits() == 8)
24320 SDValue N0 = N->getOperand(0);
24321 SDValue N1 = N->getOperand(1);
24324 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24325 // and change it to SUB and CMOV.
24326 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24327 N0.getOpcode() == ISD::ADD &&
24328 N0.getOperand(1) == N1 &&
24329 N1.getOpcode() == ISD::SRA &&
24330 N1.getOperand(0) == N0.getOperand(0))
24331 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24332 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24333 // Generate SUB & CMOV.
24334 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24335 DAG.getConstant(0, VT), N0.getOperand(0));
24337 SDValue Ops[] = { N0.getOperand(0), Neg,
24338 DAG.getConstant(X86::COND_GE, MVT::i8),
24339 SDValue(Neg.getNode(), 1) };
24340 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24345 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24346 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24347 TargetLowering::DAGCombinerInfo &DCI,
24348 const X86Subtarget *Subtarget) {
24349 if (DCI.isBeforeLegalizeOps())
24352 if (Subtarget->hasCMov()) {
24353 SDValue RV = performIntegerAbsCombine(N, DAG);
24361 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24362 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24363 TargetLowering::DAGCombinerInfo &DCI,
24364 const X86Subtarget *Subtarget) {
24365 LoadSDNode *Ld = cast<LoadSDNode>(N);
24366 EVT RegVT = Ld->getValueType(0);
24367 EVT MemVT = Ld->getMemoryVT();
24369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24371 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24372 // into two 16-byte operations.
24373 ISD::LoadExtType Ext = Ld->getExtensionType();
24374 unsigned Alignment = Ld->getAlignment();
24375 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24376 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24377 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24378 unsigned NumElems = RegVT.getVectorNumElements();
24382 SDValue Ptr = Ld->getBasePtr();
24383 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24385 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24387 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24388 Ld->getPointerInfo(), Ld->isVolatile(),
24389 Ld->isNonTemporal(), Ld->isInvariant(),
24391 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24392 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24393 Ld->getPointerInfo(), Ld->isVolatile(),
24394 Ld->isNonTemporal(), Ld->isInvariant(),
24395 std::min(16U, Alignment));
24396 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24398 Load2.getValue(1));
24400 SDValue NewVec = DAG.getUNDEF(RegVT);
24401 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24402 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24403 return DCI.CombineTo(N, NewVec, TF, true);
24409 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24410 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24411 const X86Subtarget *Subtarget) {
24412 StoreSDNode *St = cast<StoreSDNode>(N);
24413 EVT VT = St->getValue().getValueType();
24414 EVT StVT = St->getMemoryVT();
24416 SDValue StoredVal = St->getOperand(1);
24417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24419 // If we are saving a concatenation of two XMM registers and 32-byte stores
24420 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24421 unsigned Alignment = St->getAlignment();
24422 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24423 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24424 StVT == VT && !IsAligned) {
24425 unsigned NumElems = VT.getVectorNumElements();
24429 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24430 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24432 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24433 SDValue Ptr0 = St->getBasePtr();
24434 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24436 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24437 St->getPointerInfo(), St->isVolatile(),
24438 St->isNonTemporal(), Alignment);
24439 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24440 St->getPointerInfo(), St->isVolatile(),
24441 St->isNonTemporal(),
24442 std::min(16U, Alignment));
24443 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24446 // Optimize trunc store (of multiple scalars) to shuffle and store.
24447 // First, pack all of the elements in one place. Next, store to memory
24448 // in fewer chunks.
24449 if (St->isTruncatingStore() && VT.isVector()) {
24450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24451 unsigned NumElems = VT.getVectorNumElements();
24452 assert(StVT != VT && "Cannot truncate to the same type");
24453 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24454 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24456 // From, To sizes and ElemCount must be pow of two
24457 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24458 // We are going to use the original vector elt for storing.
24459 // Accumulated smaller vector elements must be a multiple of the store size.
24460 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24462 unsigned SizeRatio = FromSz / ToSz;
24464 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24466 // Create a type on which we perform the shuffle
24467 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24468 StVT.getScalarType(), NumElems*SizeRatio);
24470 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24472 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24473 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24474 for (unsigned i = 0; i != NumElems; ++i)
24475 ShuffleVec[i] = i * SizeRatio;
24477 // Can't shuffle using an illegal type.
24478 if (!TLI.isTypeLegal(WideVecVT))
24481 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24482 DAG.getUNDEF(WideVecVT),
24484 // At this point all of the data is stored at the bottom of the
24485 // register. We now need to save it to mem.
24487 // Find the largest store unit
24488 MVT StoreType = MVT::i8;
24489 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24490 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24491 MVT Tp = (MVT::SimpleValueType)tp;
24492 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24496 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24497 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24498 (64 <= NumElems * ToSz))
24499 StoreType = MVT::f64;
24501 // Bitcast the original vector into a vector of store-size units
24502 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24503 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24504 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24505 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24506 SmallVector<SDValue, 8> Chains;
24507 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24508 TLI.getPointerTy());
24509 SDValue Ptr = St->getBasePtr();
24511 // Perform one or more big stores into memory.
24512 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24513 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24514 StoreType, ShuffWide,
24515 DAG.getIntPtrConstant(i));
24516 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24517 St->getPointerInfo(), St->isVolatile(),
24518 St->isNonTemporal(), St->getAlignment());
24519 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24520 Chains.push_back(Ch);
24523 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24526 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24527 // the FP state in cases where an emms may be missing.
24528 // A preferable solution to the general problem is to figure out the right
24529 // places to insert EMMS. This qualifies as a quick hack.
24531 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24532 if (VT.getSizeInBits() != 64)
24535 const Function *F = DAG.getMachineFunction().getFunction();
24536 bool NoImplicitFloatOps = F->getAttributes().
24537 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24538 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24539 && Subtarget->hasSSE2();
24540 if ((VT.isVector() ||
24541 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24542 isa<LoadSDNode>(St->getValue()) &&
24543 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24544 St->getChain().hasOneUse() && !St->isVolatile()) {
24545 SDNode* LdVal = St->getValue().getNode();
24546 LoadSDNode *Ld = nullptr;
24547 int TokenFactorIndex = -1;
24548 SmallVector<SDValue, 8> Ops;
24549 SDNode* ChainVal = St->getChain().getNode();
24550 // Must be a store of a load. We currently handle two cases: the load
24551 // is a direct child, and it's under an intervening TokenFactor. It is
24552 // possible to dig deeper under nested TokenFactors.
24553 if (ChainVal == LdVal)
24554 Ld = cast<LoadSDNode>(St->getChain());
24555 else if (St->getValue().hasOneUse() &&
24556 ChainVal->getOpcode() == ISD::TokenFactor) {
24557 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24558 if (ChainVal->getOperand(i).getNode() == LdVal) {
24559 TokenFactorIndex = i;
24560 Ld = cast<LoadSDNode>(St->getValue());
24562 Ops.push_back(ChainVal->getOperand(i));
24566 if (!Ld || !ISD::isNormalLoad(Ld))
24569 // If this is not the MMX case, i.e. we are just turning i64 load/store
24570 // into f64 load/store, avoid the transformation if there are multiple
24571 // uses of the loaded value.
24572 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24577 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24578 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24580 if (Subtarget->is64Bit() || F64IsLegal) {
24581 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24582 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24583 Ld->getPointerInfo(), Ld->isVolatile(),
24584 Ld->isNonTemporal(), Ld->isInvariant(),
24585 Ld->getAlignment());
24586 SDValue NewChain = NewLd.getValue(1);
24587 if (TokenFactorIndex != -1) {
24588 Ops.push_back(NewChain);
24589 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24591 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24592 St->getPointerInfo(),
24593 St->isVolatile(), St->isNonTemporal(),
24594 St->getAlignment());
24597 // Otherwise, lower to two pairs of 32-bit loads / stores.
24598 SDValue LoAddr = Ld->getBasePtr();
24599 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24600 DAG.getConstant(4, MVT::i32));
24602 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24603 Ld->getPointerInfo(),
24604 Ld->isVolatile(), Ld->isNonTemporal(),
24605 Ld->isInvariant(), Ld->getAlignment());
24606 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24607 Ld->getPointerInfo().getWithOffset(4),
24608 Ld->isVolatile(), Ld->isNonTemporal(),
24610 MinAlign(Ld->getAlignment(), 4));
24612 SDValue NewChain = LoLd.getValue(1);
24613 if (TokenFactorIndex != -1) {
24614 Ops.push_back(LoLd);
24615 Ops.push_back(HiLd);
24616 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24619 LoAddr = St->getBasePtr();
24620 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24621 DAG.getConstant(4, MVT::i32));
24623 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24624 St->getPointerInfo(),
24625 St->isVolatile(), St->isNonTemporal(),
24626 St->getAlignment());
24627 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24628 St->getPointerInfo().getWithOffset(4),
24630 St->isNonTemporal(),
24631 MinAlign(St->getAlignment(), 4));
24632 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24637 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24638 /// and return the operands for the horizontal operation in LHS and RHS. A
24639 /// horizontal operation performs the binary operation on successive elements
24640 /// of its first operand, then on successive elements of its second operand,
24641 /// returning the resulting values in a vector. For example, if
24642 /// A = < float a0, float a1, float a2, float a3 >
24644 /// B = < float b0, float b1, float b2, float b3 >
24645 /// then the result of doing a horizontal operation on A and B is
24646 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24647 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24648 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24649 /// set to A, RHS to B, and the routine returns 'true'.
24650 /// Note that the binary operation should have the property that if one of the
24651 /// operands is UNDEF then the result is UNDEF.
24652 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24653 // Look for the following pattern: if
24654 // A = < float a0, float a1, float a2, float a3 >
24655 // B = < float b0, float b1, float b2, float b3 >
24657 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24658 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24659 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24660 // which is A horizontal-op B.
24662 // At least one of the operands should be a vector shuffle.
24663 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24664 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24667 MVT VT = LHS.getSimpleValueType();
24669 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24670 "Unsupported vector type for horizontal add/sub");
24672 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24673 // operate independently on 128-bit lanes.
24674 unsigned NumElts = VT.getVectorNumElements();
24675 unsigned NumLanes = VT.getSizeInBits()/128;
24676 unsigned NumLaneElts = NumElts / NumLanes;
24677 assert((NumLaneElts % 2 == 0) &&
24678 "Vector type should have an even number of elements in each lane");
24679 unsigned HalfLaneElts = NumLaneElts/2;
24681 // View LHS in the form
24682 // LHS = VECTOR_SHUFFLE A, B, LMask
24683 // If LHS is not a shuffle then pretend it is the shuffle
24684 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24685 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24688 SmallVector<int, 16> LMask(NumElts);
24689 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24690 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24691 A = LHS.getOperand(0);
24692 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24693 B = LHS.getOperand(1);
24694 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24695 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24697 if (LHS.getOpcode() != ISD::UNDEF)
24699 for (unsigned i = 0; i != NumElts; ++i)
24703 // Likewise, view RHS in the form
24704 // RHS = VECTOR_SHUFFLE C, D, RMask
24706 SmallVector<int, 16> RMask(NumElts);
24707 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24708 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24709 C = RHS.getOperand(0);
24710 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24711 D = RHS.getOperand(1);
24712 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24713 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24715 if (RHS.getOpcode() != ISD::UNDEF)
24717 for (unsigned i = 0; i != NumElts; ++i)
24721 // Check that the shuffles are both shuffling the same vectors.
24722 if (!(A == C && B == D) && !(A == D && B == C))
24725 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24726 if (!A.getNode() && !B.getNode())
24729 // If A and B occur in reverse order in RHS, then "swap" them (which means
24730 // rewriting the mask).
24732 CommuteVectorShuffleMask(RMask, NumElts);
24734 // At this point LHS and RHS are equivalent to
24735 // LHS = VECTOR_SHUFFLE A, B, LMask
24736 // RHS = VECTOR_SHUFFLE A, B, RMask
24737 // Check that the masks correspond to performing a horizontal operation.
24738 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24739 for (unsigned i = 0; i != NumLaneElts; ++i) {
24740 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24742 // Ignore any UNDEF components.
24743 if (LIdx < 0 || RIdx < 0 ||
24744 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24745 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24748 // Check that successive elements are being operated on. If not, this is
24749 // not a horizontal operation.
24750 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24751 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24752 if (!(LIdx == Index && RIdx == Index + 1) &&
24753 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24758 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24759 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24763 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24764 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24765 const X86Subtarget *Subtarget) {
24766 EVT VT = N->getValueType(0);
24767 SDValue LHS = N->getOperand(0);
24768 SDValue RHS = N->getOperand(1);
24770 // Try to synthesize horizontal adds from adds of shuffles.
24771 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24772 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24773 isHorizontalBinOp(LHS, RHS, true))
24774 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24778 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24779 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24780 const X86Subtarget *Subtarget) {
24781 EVT VT = N->getValueType(0);
24782 SDValue LHS = N->getOperand(0);
24783 SDValue RHS = N->getOperand(1);
24785 // Try to synthesize horizontal subs from subs of shuffles.
24786 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24787 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24788 isHorizontalBinOp(LHS, RHS, false))
24789 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24793 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24794 /// X86ISD::FXOR nodes.
24795 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24796 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24797 // F[X]OR(0.0, x) -> x
24798 // F[X]OR(x, 0.0) -> x
24799 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24800 if (C->getValueAPF().isPosZero())
24801 return N->getOperand(1);
24802 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24803 if (C->getValueAPF().isPosZero())
24804 return N->getOperand(0);
24808 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24809 /// X86ISD::FMAX nodes.
24810 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24811 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24813 // Only perform optimizations if UnsafeMath is used.
24814 if (!DAG.getTarget().Options.UnsafeFPMath)
24817 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24818 // into FMINC and FMAXC, which are Commutative operations.
24819 unsigned NewOp = 0;
24820 switch (N->getOpcode()) {
24821 default: llvm_unreachable("unknown opcode");
24822 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24823 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24826 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24827 N->getOperand(0), N->getOperand(1));
24830 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24831 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24832 // FAND(0.0, x) -> 0.0
24833 // FAND(x, 0.0) -> 0.0
24834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24835 if (C->getValueAPF().isPosZero())
24836 return N->getOperand(0);
24837 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24838 if (C->getValueAPF().isPosZero())
24839 return N->getOperand(1);
24843 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24844 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24845 // FANDN(x, 0.0) -> 0.0
24846 // FANDN(0.0, x) -> x
24847 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24848 if (C->getValueAPF().isPosZero())
24849 return N->getOperand(1);
24850 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24851 if (C->getValueAPF().isPosZero())
24852 return N->getOperand(1);
24856 static SDValue PerformBTCombine(SDNode *N,
24858 TargetLowering::DAGCombinerInfo &DCI) {
24859 // BT ignores high bits in the bit index operand.
24860 SDValue Op1 = N->getOperand(1);
24861 if (Op1.hasOneUse()) {
24862 unsigned BitWidth = Op1.getValueSizeInBits();
24863 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24864 APInt KnownZero, KnownOne;
24865 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24866 !DCI.isBeforeLegalizeOps());
24867 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24868 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24869 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24870 DCI.CommitTargetLoweringOpt(TLO);
24875 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24876 SDValue Op = N->getOperand(0);
24877 if (Op.getOpcode() == ISD::BITCAST)
24878 Op = Op.getOperand(0);
24879 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24880 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24881 VT.getVectorElementType().getSizeInBits() ==
24882 OpVT.getVectorElementType().getSizeInBits()) {
24883 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24888 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24889 const X86Subtarget *Subtarget) {
24890 EVT VT = N->getValueType(0);
24891 if (!VT.isVector())
24894 SDValue N0 = N->getOperand(0);
24895 SDValue N1 = N->getOperand(1);
24896 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24899 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24900 // both SSE and AVX2 since there is no sign-extended shift right
24901 // operation on a vector with 64-bit elements.
24902 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24903 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24904 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24905 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24906 SDValue N00 = N0.getOperand(0);
24908 // EXTLOAD has a better solution on AVX2,
24909 // it may be replaced with X86ISD::VSEXT node.
24910 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24911 if (!ISD::isNormalLoad(N00.getNode()))
24914 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24915 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24917 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24923 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24924 TargetLowering::DAGCombinerInfo &DCI,
24925 const X86Subtarget *Subtarget) {
24926 SDValue N0 = N->getOperand(0);
24927 EVT VT = N->getValueType(0);
24929 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24930 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24931 // This exposes the sext to the sdivrem lowering, so that it directly extends
24932 // from AH (which we otherwise need to do contortions to access).
24933 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24934 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24936 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24937 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24938 N0.getOperand(0), N0.getOperand(1));
24939 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24940 return R.getValue(1);
24943 if (!DCI.isBeforeLegalizeOps())
24946 if (!Subtarget->hasFp256())
24949 if (VT.isVector() && VT.getSizeInBits() == 256) {
24950 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24958 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24959 const X86Subtarget* Subtarget) {
24961 EVT VT = N->getValueType(0);
24963 // Let legalize expand this if it isn't a legal type yet.
24964 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24967 EVT ScalarVT = VT.getScalarType();
24968 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24969 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24972 SDValue A = N->getOperand(0);
24973 SDValue B = N->getOperand(1);
24974 SDValue C = N->getOperand(2);
24976 bool NegA = (A.getOpcode() == ISD::FNEG);
24977 bool NegB = (B.getOpcode() == ISD::FNEG);
24978 bool NegC = (C.getOpcode() == ISD::FNEG);
24980 // Negative multiplication when NegA xor NegB
24981 bool NegMul = (NegA != NegB);
24983 A = A.getOperand(0);
24985 B = B.getOperand(0);
24987 C = C.getOperand(0);
24991 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24993 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24995 return DAG.getNode(Opcode, dl, VT, A, B, C);
24998 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24999 TargetLowering::DAGCombinerInfo &DCI,
25000 const X86Subtarget *Subtarget) {
25001 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25002 // (and (i32 x86isd::setcc_carry), 1)
25003 // This eliminates the zext. This transformation is necessary because
25004 // ISD::SETCC is always legalized to i8.
25006 SDValue N0 = N->getOperand(0);
25007 EVT VT = N->getValueType(0);
25009 if (N0.getOpcode() == ISD::AND &&
25011 N0.getOperand(0).hasOneUse()) {
25012 SDValue N00 = N0.getOperand(0);
25013 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25015 if (!C || C->getZExtValue() != 1)
25017 return DAG.getNode(ISD::AND, dl, VT,
25018 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25019 N00.getOperand(0), N00.getOperand(1)),
25020 DAG.getConstant(1, VT));
25024 if (N0.getOpcode() == ISD::TRUNCATE &&
25026 N0.getOperand(0).hasOneUse()) {
25027 SDValue N00 = N0.getOperand(0);
25028 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25029 return DAG.getNode(ISD::AND, dl, VT,
25030 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25031 N00.getOperand(0), N00.getOperand(1)),
25032 DAG.getConstant(1, VT));
25035 if (VT.is256BitVector()) {
25036 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25041 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25042 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25043 // This exposes the zext to the udivrem lowering, so that it directly extends
25044 // from AH (which we otherwise need to do contortions to access).
25045 if (N0.getOpcode() == ISD::UDIVREM &&
25046 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25047 (VT == MVT::i32 || VT == MVT::i64)) {
25048 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25049 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25050 N0.getOperand(0), N0.getOperand(1));
25051 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25052 return R.getValue(1);
25058 // Optimize x == -y --> x+y == 0
25059 // x != -y --> x+y != 0
25060 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25061 const X86Subtarget* Subtarget) {
25062 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25063 SDValue LHS = N->getOperand(0);
25064 SDValue RHS = N->getOperand(1);
25065 EVT VT = N->getValueType(0);
25068 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25070 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25071 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25072 LHS.getValueType(), RHS, LHS.getOperand(1));
25073 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25074 addV, DAG.getConstant(0, addV.getValueType()), CC);
25076 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25078 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25079 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25080 RHS.getValueType(), LHS, RHS.getOperand(1));
25081 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25082 addV, DAG.getConstant(0, addV.getValueType()), CC);
25085 if (VT.getScalarType() == MVT::i1) {
25086 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25087 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25088 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25089 if (!IsSEXT0 && !IsVZero0)
25091 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25092 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25093 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25095 if (!IsSEXT1 && !IsVZero1)
25098 if (IsSEXT0 && IsVZero1) {
25099 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25100 if (CC == ISD::SETEQ)
25101 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25102 return LHS.getOperand(0);
25104 if (IsSEXT1 && IsVZero0) {
25105 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25106 if (CC == ISD::SETEQ)
25107 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25108 return RHS.getOperand(0);
25115 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25116 const X86Subtarget *Subtarget) {
25118 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25119 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25120 "X86insertps is only defined for v4x32");
25122 SDValue Ld = N->getOperand(1);
25123 if (MayFoldLoad(Ld)) {
25124 // Extract the countS bits from the immediate so we can get the proper
25125 // address when narrowing the vector load to a specific element.
25126 // When the second source op is a memory address, interps doesn't use
25127 // countS and just gets an f32 from that address.
25128 unsigned DestIndex =
25129 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25130 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25134 // Create this as a scalar to vector to match the instruction pattern.
25135 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25136 // countS bits are ignored when loading from memory on insertps, which
25137 // means we don't need to explicitly set them to 0.
25138 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25139 LoadScalarToVector, N->getOperand(2));
25142 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25143 // as "sbb reg,reg", since it can be extended without zext and produces
25144 // an all-ones bit which is more useful than 0/1 in some cases.
25145 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25148 return DAG.getNode(ISD::AND, DL, VT,
25149 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25150 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25151 DAG.getConstant(1, VT));
25152 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25153 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25154 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25155 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25158 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25159 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25160 TargetLowering::DAGCombinerInfo &DCI,
25161 const X86Subtarget *Subtarget) {
25163 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25164 SDValue EFLAGS = N->getOperand(1);
25166 if (CC == X86::COND_A) {
25167 // Try to convert COND_A into COND_B in an attempt to facilitate
25168 // materializing "setb reg".
25170 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25171 // cannot take an immediate as its first operand.
25173 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25174 EFLAGS.getValueType().isInteger() &&
25175 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25176 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25177 EFLAGS.getNode()->getVTList(),
25178 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25179 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25180 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25184 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25185 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25187 if (CC == X86::COND_B)
25188 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25192 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25193 if (Flags.getNode()) {
25194 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25195 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25201 // Optimize branch condition evaluation.
25203 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25204 TargetLowering::DAGCombinerInfo &DCI,
25205 const X86Subtarget *Subtarget) {
25207 SDValue Chain = N->getOperand(0);
25208 SDValue Dest = N->getOperand(1);
25209 SDValue EFLAGS = N->getOperand(3);
25210 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25214 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25215 if (Flags.getNode()) {
25216 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25217 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25224 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25225 SelectionDAG &DAG) {
25226 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25227 // optimize away operation when it's from a constant.
25229 // The general transformation is:
25230 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25231 // AND(VECTOR_CMP(x,y), constant2)
25232 // constant2 = UNARYOP(constant)
25234 // Early exit if this isn't a vector operation, the operand of the
25235 // unary operation isn't a bitwise AND, or if the sizes of the operations
25236 // aren't the same.
25237 EVT VT = N->getValueType(0);
25238 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25239 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25240 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25243 // Now check that the other operand of the AND is a constant. We could
25244 // make the transformation for non-constant splats as well, but it's unclear
25245 // that would be a benefit as it would not eliminate any operations, just
25246 // perform one more step in scalar code before moving to the vector unit.
25247 if (BuildVectorSDNode *BV =
25248 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25249 // Bail out if the vector isn't a constant.
25250 if (!BV->isConstant())
25253 // Everything checks out. Build up the new and improved node.
25255 EVT IntVT = BV->getValueType(0);
25256 // Create a new constant of the appropriate type for the transformed
25258 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25259 // The AND node needs bitcasts to/from an integer vector type around it.
25260 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25261 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25262 N->getOperand(0)->getOperand(0), MaskConst);
25263 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25270 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25271 const X86TargetLowering *XTLI) {
25272 // First try to optimize away the conversion entirely when it's
25273 // conditionally from a constant. Vectors only.
25274 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25275 if (Res != SDValue())
25278 // Now move on to more general possibilities.
25279 SDValue Op0 = N->getOperand(0);
25280 EVT InVT = Op0->getValueType(0);
25282 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25283 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25285 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25286 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25287 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25290 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25291 // a 32-bit target where SSE doesn't support i64->FP operations.
25292 if (Op0.getOpcode() == ISD::LOAD) {
25293 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25294 EVT VT = Ld->getValueType(0);
25295 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25296 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25297 !XTLI->getSubtarget()->is64Bit() &&
25299 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25300 Ld->getChain(), Op0, DAG);
25301 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25308 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25309 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25310 X86TargetLowering::DAGCombinerInfo &DCI) {
25311 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25312 // the result is either zero or one (depending on the input carry bit).
25313 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25314 if (X86::isZeroNode(N->getOperand(0)) &&
25315 X86::isZeroNode(N->getOperand(1)) &&
25316 // We don't have a good way to replace an EFLAGS use, so only do this when
25318 SDValue(N, 1).use_empty()) {
25320 EVT VT = N->getValueType(0);
25321 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25322 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25323 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25324 DAG.getConstant(X86::COND_B,MVT::i8),
25326 DAG.getConstant(1, VT));
25327 return DCI.CombineTo(N, Res1, CarryOut);
25333 // fold (add Y, (sete X, 0)) -> adc 0, Y
25334 // (add Y, (setne X, 0)) -> sbb -1, Y
25335 // (sub (sete X, 0), Y) -> sbb 0, Y
25336 // (sub (setne X, 0), Y) -> adc -1, Y
25337 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25340 // Look through ZExts.
25341 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25342 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25345 SDValue SetCC = Ext.getOperand(0);
25346 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25349 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25350 if (CC != X86::COND_E && CC != X86::COND_NE)
25353 SDValue Cmp = SetCC.getOperand(1);
25354 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25355 !X86::isZeroNode(Cmp.getOperand(1)) ||
25356 !Cmp.getOperand(0).getValueType().isInteger())
25359 SDValue CmpOp0 = Cmp.getOperand(0);
25360 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25361 DAG.getConstant(1, CmpOp0.getValueType()));
25363 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25364 if (CC == X86::COND_NE)
25365 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25366 DL, OtherVal.getValueType(), OtherVal,
25367 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25368 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25369 DL, OtherVal.getValueType(), OtherVal,
25370 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25373 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25374 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25375 const X86Subtarget *Subtarget) {
25376 EVT VT = N->getValueType(0);
25377 SDValue Op0 = N->getOperand(0);
25378 SDValue Op1 = N->getOperand(1);
25380 // Try to synthesize horizontal adds from adds of shuffles.
25381 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25382 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25383 isHorizontalBinOp(Op0, Op1, true))
25384 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25386 return OptimizeConditionalInDecrement(N, DAG);
25389 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25390 const X86Subtarget *Subtarget) {
25391 SDValue Op0 = N->getOperand(0);
25392 SDValue Op1 = N->getOperand(1);
25394 // X86 can't encode an immediate LHS of a sub. See if we can push the
25395 // negation into a preceding instruction.
25396 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25397 // If the RHS of the sub is a XOR with one use and a constant, invert the
25398 // immediate. Then add one to the LHS of the sub so we can turn
25399 // X-Y -> X+~Y+1, saving one register.
25400 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25401 isa<ConstantSDNode>(Op1.getOperand(1))) {
25402 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25403 EVT VT = Op0.getValueType();
25404 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25406 DAG.getConstant(~XorC, VT));
25407 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25408 DAG.getConstant(C->getAPIntValue()+1, VT));
25412 // Try to synthesize horizontal adds from adds of shuffles.
25413 EVT VT = N->getValueType(0);
25414 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25415 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25416 isHorizontalBinOp(Op0, Op1, true))
25417 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25419 return OptimizeConditionalInDecrement(N, DAG);
25422 /// performVZEXTCombine - Performs build vector combines
25423 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25424 TargetLowering::DAGCombinerInfo &DCI,
25425 const X86Subtarget *Subtarget) {
25427 MVT VT = N->getSimpleValueType(0);
25428 SDValue Op = N->getOperand(0);
25429 MVT OpVT = Op.getSimpleValueType();
25430 MVT OpEltVT = OpVT.getVectorElementType();
25431 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25433 // (vzext (bitcast (vzext (x)) -> (vzext x)
25435 while (V.getOpcode() == ISD::BITCAST)
25436 V = V.getOperand(0);
25438 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25439 MVT InnerVT = V.getSimpleValueType();
25440 MVT InnerEltVT = InnerVT.getVectorElementType();
25442 // If the element sizes match exactly, we can just do one larger vzext. This
25443 // is always an exact type match as vzext operates on integer types.
25444 if (OpEltVT == InnerEltVT) {
25445 assert(OpVT == InnerVT && "Types must match for vzext!");
25446 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25449 // The only other way we can combine them is if only a single element of the
25450 // inner vzext is used in the input to the outer vzext.
25451 if (InnerEltVT.getSizeInBits() < InputBits)
25454 // In this case, the inner vzext is completely dead because we're going to
25455 // only look at bits inside of the low element. Just do the outer vzext on
25456 // a bitcast of the input to the inner.
25457 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25458 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25461 // Check if we can bypass extracting and re-inserting an element of an input
25462 // vector. Essentialy:
25463 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25464 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25465 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25466 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25467 SDValue ExtractedV = V.getOperand(0);
25468 SDValue OrigV = ExtractedV.getOperand(0);
25469 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25470 if (ExtractIdx->getZExtValue() == 0) {
25471 MVT OrigVT = OrigV.getSimpleValueType();
25472 // Extract a subvector if necessary...
25473 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25474 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25475 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25476 OrigVT.getVectorNumElements() / Ratio);
25477 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25478 DAG.getIntPtrConstant(0));
25480 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25481 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25488 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25489 DAGCombinerInfo &DCI) const {
25490 SelectionDAG &DAG = DCI.DAG;
25491 switch (N->getOpcode()) {
25493 case ISD::EXTRACT_VECTOR_ELT:
25494 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25497 case X86ISD::SHRUNKBLEND:
25498 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25499 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25500 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25501 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25502 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25503 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25506 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25507 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25508 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25509 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25510 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25511 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25512 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25513 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25514 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25516 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25518 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25519 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25520 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25521 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25522 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25523 case ISD::ANY_EXTEND:
25524 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25525 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25526 case ISD::SIGN_EXTEND_INREG:
25527 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25528 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25529 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25530 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25531 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25532 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25533 case X86ISD::SHUFP: // Handle all target specific shuffles
25534 case X86ISD::PALIGNR:
25535 case X86ISD::UNPCKH:
25536 case X86ISD::UNPCKL:
25537 case X86ISD::MOVHLPS:
25538 case X86ISD::MOVLHPS:
25539 case X86ISD::PSHUFB:
25540 case X86ISD::PSHUFD:
25541 case X86ISD::PSHUFHW:
25542 case X86ISD::PSHUFLW:
25543 case X86ISD::MOVSS:
25544 case X86ISD::MOVSD:
25545 case X86ISD::VPERMILPI:
25546 case X86ISD::VPERM2X128:
25547 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25548 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25549 case ISD::INTRINSIC_WO_CHAIN:
25550 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25551 case X86ISD::INSERTPS:
25552 return PerformINSERTPSCombine(N, DAG, Subtarget);
25553 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25559 /// isTypeDesirableForOp - Return true if the target has native support for
25560 /// the specified value type and it is 'desirable' to use the type for the
25561 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25562 /// instruction encodings are longer and some i16 instructions are slow.
25563 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25564 if (!isTypeLegal(VT))
25566 if (VT != MVT::i16)
25573 case ISD::SIGN_EXTEND:
25574 case ISD::ZERO_EXTEND:
25575 case ISD::ANY_EXTEND:
25588 /// IsDesirableToPromoteOp - This method query the target whether it is
25589 /// beneficial for dag combiner to promote the specified node. If true, it
25590 /// should return the desired promotion type by reference.
25591 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25592 EVT VT = Op.getValueType();
25593 if (VT != MVT::i16)
25596 bool Promote = false;
25597 bool Commute = false;
25598 switch (Op.getOpcode()) {
25601 LoadSDNode *LD = cast<LoadSDNode>(Op);
25602 // If the non-extending load has a single use and it's not live out, then it
25603 // might be folded.
25604 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25605 Op.hasOneUse()*/) {
25606 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25607 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25608 // The only case where we'd want to promote LOAD (rather then it being
25609 // promoted as an operand is when it's only use is liveout.
25610 if (UI->getOpcode() != ISD::CopyToReg)
25617 case ISD::SIGN_EXTEND:
25618 case ISD::ZERO_EXTEND:
25619 case ISD::ANY_EXTEND:
25624 SDValue N0 = Op.getOperand(0);
25625 // Look out for (store (shl (load), x)).
25626 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25639 SDValue N0 = Op.getOperand(0);
25640 SDValue N1 = Op.getOperand(1);
25641 if (!Commute && MayFoldLoad(N1))
25643 // Avoid disabling potential load folding opportunities.
25644 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25646 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25656 //===----------------------------------------------------------------------===//
25657 // X86 Inline Assembly Support
25658 //===----------------------------------------------------------------------===//
25661 // Helper to match a string separated by whitespace.
25662 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25663 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25665 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25666 StringRef piece(*args[i]);
25667 if (!s.startswith(piece)) // Check if the piece matches.
25670 s = s.substr(piece.size());
25671 StringRef::size_type pos = s.find_first_not_of(" \t");
25672 if (pos == 0) // We matched a prefix.
25680 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25683 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25685 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25686 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25687 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25688 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25690 if (AsmPieces.size() == 3)
25692 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25699 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25700 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25702 std::string AsmStr = IA->getAsmString();
25704 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25705 if (!Ty || Ty->getBitWidth() % 16 != 0)
25708 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25709 SmallVector<StringRef, 4> AsmPieces;
25710 SplitString(AsmStr, AsmPieces, ";\n");
25712 switch (AsmPieces.size()) {
25713 default: return false;
25715 // FIXME: this should verify that we are targeting a 486 or better. If not,
25716 // we will turn this bswap into something that will be lowered to logical
25717 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25718 // lower so don't worry about this.
25720 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25721 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25722 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25723 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25724 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25725 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25726 // No need to check constraints, nothing other than the equivalent of
25727 // "=r,0" would be valid here.
25728 return IntrinsicLowering::LowerToByteSwap(CI);
25731 // rorw $$8, ${0:w} --> llvm.bswap.i16
25732 if (CI->getType()->isIntegerTy(16) &&
25733 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25734 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25735 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25737 const std::string &ConstraintsStr = IA->getConstraintString();
25738 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25739 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25740 if (clobbersFlagRegisters(AsmPieces))
25741 return IntrinsicLowering::LowerToByteSwap(CI);
25745 if (CI->getType()->isIntegerTy(32) &&
25746 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25747 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25748 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25749 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25751 const std::string &ConstraintsStr = IA->getConstraintString();
25752 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25753 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25754 if (clobbersFlagRegisters(AsmPieces))
25755 return IntrinsicLowering::LowerToByteSwap(CI);
25758 if (CI->getType()->isIntegerTy(64)) {
25759 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25760 if (Constraints.size() >= 2 &&
25761 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25762 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25763 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25764 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25765 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25766 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25767 return IntrinsicLowering::LowerToByteSwap(CI);
25775 /// getConstraintType - Given a constraint letter, return the type of
25776 /// constraint it is for this target.
25777 X86TargetLowering::ConstraintType
25778 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25779 if (Constraint.size() == 1) {
25780 switch (Constraint[0]) {
25791 return C_RegisterClass;
25815 return TargetLowering::getConstraintType(Constraint);
25818 /// Examine constraint type and operand type and determine a weight value.
25819 /// This object must already have been set up with the operand type
25820 /// and the current alternative constraint selected.
25821 TargetLowering::ConstraintWeight
25822 X86TargetLowering::getSingleConstraintMatchWeight(
25823 AsmOperandInfo &info, const char *constraint) const {
25824 ConstraintWeight weight = CW_Invalid;
25825 Value *CallOperandVal = info.CallOperandVal;
25826 // If we don't have a value, we can't do a match,
25827 // but allow it at the lowest weight.
25828 if (!CallOperandVal)
25830 Type *type = CallOperandVal->getType();
25831 // Look at the constraint type.
25832 switch (*constraint) {
25834 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25845 if (CallOperandVal->getType()->isIntegerTy())
25846 weight = CW_SpecificReg;
25851 if (type->isFloatingPointTy())
25852 weight = CW_SpecificReg;
25855 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25856 weight = CW_SpecificReg;
25860 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25861 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25862 weight = CW_Register;
25865 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25866 if (C->getZExtValue() <= 31)
25867 weight = CW_Constant;
25871 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25872 if (C->getZExtValue() <= 63)
25873 weight = CW_Constant;
25877 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25878 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25879 weight = CW_Constant;
25883 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25884 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25885 weight = CW_Constant;
25889 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25890 if (C->getZExtValue() <= 3)
25891 weight = CW_Constant;
25895 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25896 if (C->getZExtValue() <= 0xff)
25897 weight = CW_Constant;
25902 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25903 weight = CW_Constant;
25907 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25908 if ((C->getSExtValue() >= -0x80000000LL) &&
25909 (C->getSExtValue() <= 0x7fffffffLL))
25910 weight = CW_Constant;
25914 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25915 if (C->getZExtValue() <= 0xffffffff)
25916 weight = CW_Constant;
25923 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25924 /// with another that has more specific requirements based on the type of the
25925 /// corresponding operand.
25926 const char *X86TargetLowering::
25927 LowerXConstraint(EVT ConstraintVT) const {
25928 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25929 // 'f' like normal targets.
25930 if (ConstraintVT.isFloatingPoint()) {
25931 if (Subtarget->hasSSE2())
25933 if (Subtarget->hasSSE1())
25937 return TargetLowering::LowerXConstraint(ConstraintVT);
25940 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25941 /// vector. If it is invalid, don't add anything to Ops.
25942 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25943 std::string &Constraint,
25944 std::vector<SDValue>&Ops,
25945 SelectionDAG &DAG) const {
25948 // Only support length 1 constraints for now.
25949 if (Constraint.length() > 1) return;
25951 char ConstraintLetter = Constraint[0];
25952 switch (ConstraintLetter) {
25955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25956 if (C->getZExtValue() <= 31) {
25957 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25963 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25964 if (C->getZExtValue() <= 63) {
25965 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25971 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25972 if (isInt<8>(C->getSExtValue())) {
25973 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25980 if (C->getZExtValue() <= 255) {
25981 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25987 // 32-bit signed value
25988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25989 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25990 C->getSExtValue())) {
25991 // Widen to 64 bits here to get it sign extended.
25992 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25995 // FIXME gcc accepts some relocatable values here too, but only in certain
25996 // memory models; it's complicated.
26001 // 32-bit unsigned value
26002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26003 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26004 C->getZExtValue())) {
26005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26009 // FIXME gcc accepts some relocatable values here too, but only in certain
26010 // memory models; it's complicated.
26014 // Literal immediates are always ok.
26015 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26016 // Widen to 64 bits here to get it sign extended.
26017 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26021 // In any sort of PIC mode addresses need to be computed at runtime by
26022 // adding in a register or some sort of table lookup. These can't
26023 // be used as immediates.
26024 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26027 // If we are in non-pic codegen mode, we allow the address of a global (with
26028 // an optional displacement) to be used with 'i'.
26029 GlobalAddressSDNode *GA = nullptr;
26030 int64_t Offset = 0;
26032 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26034 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26035 Offset += GA->getOffset();
26037 } else if (Op.getOpcode() == ISD::ADD) {
26038 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26039 Offset += C->getZExtValue();
26040 Op = Op.getOperand(0);
26043 } else if (Op.getOpcode() == ISD::SUB) {
26044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26045 Offset += -C->getZExtValue();
26046 Op = Op.getOperand(0);
26051 // Otherwise, this isn't something we can handle, reject it.
26055 const GlobalValue *GV = GA->getGlobal();
26056 // If we require an extra load to get this address, as in PIC mode, we
26057 // can't accept it.
26058 if (isGlobalStubReference(
26059 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26062 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26063 GA->getValueType(0), Offset);
26068 if (Result.getNode()) {
26069 Ops.push_back(Result);
26072 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26075 std::pair<unsigned, const TargetRegisterClass*>
26076 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26078 // First, see if this is a constraint that directly corresponds to an LLVM
26080 if (Constraint.size() == 1) {
26081 // GCC Constraint Letters
26082 switch (Constraint[0]) {
26084 // TODO: Slight differences here in allocation order and leaving
26085 // RIP in the class. Do they matter any more here than they do
26086 // in the normal allocation?
26087 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26088 if (Subtarget->is64Bit()) {
26089 if (VT == MVT::i32 || VT == MVT::f32)
26090 return std::make_pair(0U, &X86::GR32RegClass);
26091 if (VT == MVT::i16)
26092 return std::make_pair(0U, &X86::GR16RegClass);
26093 if (VT == MVT::i8 || VT == MVT::i1)
26094 return std::make_pair(0U, &X86::GR8RegClass);
26095 if (VT == MVT::i64 || VT == MVT::f64)
26096 return std::make_pair(0U, &X86::GR64RegClass);
26099 // 32-bit fallthrough
26100 case 'Q': // Q_REGS
26101 if (VT == MVT::i32 || VT == MVT::f32)
26102 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26103 if (VT == MVT::i16)
26104 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26105 if (VT == MVT::i8 || VT == MVT::i1)
26106 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26107 if (VT == MVT::i64)
26108 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26110 case 'r': // GENERAL_REGS
26111 case 'l': // INDEX_REGS
26112 if (VT == MVT::i8 || VT == MVT::i1)
26113 return std::make_pair(0U, &X86::GR8RegClass);
26114 if (VT == MVT::i16)
26115 return std::make_pair(0U, &X86::GR16RegClass);
26116 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26117 return std::make_pair(0U, &X86::GR32RegClass);
26118 return std::make_pair(0U, &X86::GR64RegClass);
26119 case 'R': // LEGACY_REGS
26120 if (VT == MVT::i8 || VT == MVT::i1)
26121 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26122 if (VT == MVT::i16)
26123 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26124 if (VT == MVT::i32 || !Subtarget->is64Bit())
26125 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26126 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26127 case 'f': // FP Stack registers.
26128 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26129 // value to the correct fpstack register class.
26130 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26131 return std::make_pair(0U, &X86::RFP32RegClass);
26132 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26133 return std::make_pair(0U, &X86::RFP64RegClass);
26134 return std::make_pair(0U, &X86::RFP80RegClass);
26135 case 'y': // MMX_REGS if MMX allowed.
26136 if (!Subtarget->hasMMX()) break;
26137 return std::make_pair(0U, &X86::VR64RegClass);
26138 case 'Y': // SSE_REGS if SSE2 allowed
26139 if (!Subtarget->hasSSE2()) break;
26141 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26142 if (!Subtarget->hasSSE1()) break;
26144 switch (VT.SimpleTy) {
26146 // Scalar SSE types.
26149 return std::make_pair(0U, &X86::FR32RegClass);
26152 return std::make_pair(0U, &X86::FR64RegClass);
26160 return std::make_pair(0U, &X86::VR128RegClass);
26168 return std::make_pair(0U, &X86::VR256RegClass);
26173 return std::make_pair(0U, &X86::VR512RegClass);
26179 // Use the default implementation in TargetLowering to convert the register
26180 // constraint into a member of a register class.
26181 std::pair<unsigned, const TargetRegisterClass*> Res;
26182 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26184 // Not found as a standard register?
26186 // Map st(0) -> st(7) -> ST0
26187 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26188 tolower(Constraint[1]) == 's' &&
26189 tolower(Constraint[2]) == 't' &&
26190 Constraint[3] == '(' &&
26191 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26192 Constraint[5] == ')' &&
26193 Constraint[6] == '}') {
26195 Res.first = X86::FP0+Constraint[4]-'0';
26196 Res.second = &X86::RFP80RegClass;
26200 // GCC allows "st(0)" to be called just plain "st".
26201 if (StringRef("{st}").equals_lower(Constraint)) {
26202 Res.first = X86::FP0;
26203 Res.second = &X86::RFP80RegClass;
26208 if (StringRef("{flags}").equals_lower(Constraint)) {
26209 Res.first = X86::EFLAGS;
26210 Res.second = &X86::CCRRegClass;
26214 // 'A' means EAX + EDX.
26215 if (Constraint == "A") {
26216 Res.first = X86::EAX;
26217 Res.second = &X86::GR32_ADRegClass;
26223 // Otherwise, check to see if this is a register class of the wrong value
26224 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26225 // turn into {ax},{dx}.
26226 if (Res.second->hasType(VT))
26227 return Res; // Correct type already, nothing to do.
26229 // All of the single-register GCC register classes map their values onto
26230 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26231 // really want an 8-bit or 32-bit register, map to the appropriate register
26232 // class and return the appropriate register.
26233 if (Res.second == &X86::GR16RegClass) {
26234 if (VT == MVT::i8 || VT == MVT::i1) {
26235 unsigned DestReg = 0;
26236 switch (Res.first) {
26238 case X86::AX: DestReg = X86::AL; break;
26239 case X86::DX: DestReg = X86::DL; break;
26240 case X86::CX: DestReg = X86::CL; break;
26241 case X86::BX: DestReg = X86::BL; break;
26244 Res.first = DestReg;
26245 Res.second = &X86::GR8RegClass;
26247 } else if (VT == MVT::i32 || VT == MVT::f32) {
26248 unsigned DestReg = 0;
26249 switch (Res.first) {
26251 case X86::AX: DestReg = X86::EAX; break;
26252 case X86::DX: DestReg = X86::EDX; break;
26253 case X86::CX: DestReg = X86::ECX; break;
26254 case X86::BX: DestReg = X86::EBX; break;
26255 case X86::SI: DestReg = X86::ESI; break;
26256 case X86::DI: DestReg = X86::EDI; break;
26257 case X86::BP: DestReg = X86::EBP; break;
26258 case X86::SP: DestReg = X86::ESP; break;
26261 Res.first = DestReg;
26262 Res.second = &X86::GR32RegClass;
26264 } else if (VT == MVT::i64 || VT == MVT::f64) {
26265 unsigned DestReg = 0;
26266 switch (Res.first) {
26268 case X86::AX: DestReg = X86::RAX; break;
26269 case X86::DX: DestReg = X86::RDX; break;
26270 case X86::CX: DestReg = X86::RCX; break;
26271 case X86::BX: DestReg = X86::RBX; break;
26272 case X86::SI: DestReg = X86::RSI; break;
26273 case X86::DI: DestReg = X86::RDI; break;
26274 case X86::BP: DestReg = X86::RBP; break;
26275 case X86::SP: DestReg = X86::RSP; break;
26278 Res.first = DestReg;
26279 Res.second = &X86::GR64RegClass;
26282 } else if (Res.second == &X86::FR32RegClass ||
26283 Res.second == &X86::FR64RegClass ||
26284 Res.second == &X86::VR128RegClass ||
26285 Res.second == &X86::VR256RegClass ||
26286 Res.second == &X86::FR32XRegClass ||
26287 Res.second == &X86::FR64XRegClass ||
26288 Res.second == &X86::VR128XRegClass ||
26289 Res.second == &X86::VR256XRegClass ||
26290 Res.second == &X86::VR512RegClass) {
26291 // Handle references to XMM physical registers that got mapped into the
26292 // wrong class. This can happen with constraints like {xmm0} where the
26293 // target independent register mapper will just pick the first match it can
26294 // find, ignoring the required type.
26296 if (VT == MVT::f32 || VT == MVT::i32)
26297 Res.second = &X86::FR32RegClass;
26298 else if (VT == MVT::f64 || VT == MVT::i64)
26299 Res.second = &X86::FR64RegClass;
26300 else if (X86::VR128RegClass.hasType(VT))
26301 Res.second = &X86::VR128RegClass;
26302 else if (X86::VR256RegClass.hasType(VT))
26303 Res.second = &X86::VR256RegClass;
26304 else if (X86::VR512RegClass.hasType(VT))
26305 Res.second = &X86::VR512RegClass;
26311 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26313 // Scaling factors are not free at all.
26314 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26315 // will take 2 allocations in the out of order engine instead of 1
26316 // for plain addressing mode, i.e. inst (reg1).
26318 // vaddps (%rsi,%drx), %ymm0, %ymm1
26319 // Requires two allocations (one for the load, one for the computation)
26321 // vaddps (%rsi), %ymm0, %ymm1
26322 // Requires just 1 allocation, i.e., freeing allocations for other operations
26323 // and having less micro operations to execute.
26325 // For some X86 architectures, this is even worse because for instance for
26326 // stores, the complex addressing mode forces the instruction to use the
26327 // "load" ports instead of the dedicated "store" port.
26328 // E.g., on Haswell:
26329 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26330 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26331 if (isLegalAddressingMode(AM, Ty))
26332 // Scale represents reg2 * scale, thus account for 1
26333 // as soon as we use a second register.
26334 return AM.Scale != 0;
26338 bool X86TargetLowering::isTargetFTOL() const {
26339 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();