1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 SDValue PBLENDVMask[32];
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7387 for (int j = 0; j < Scale; ++j)
7388 PBLENDVMask[Scale * i + j] =
7389 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7390 : DAG.getConstant(Mask[i] < Size ? 0 : 0x80, MVT::i8);
7392 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7393 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7395 ISD::BITCAST, DL, VT,
7396 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7397 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask),
7402 llvm_unreachable("Not a supported integer vector type!");
7406 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7407 /// unblended shuffles followed by an unshuffled blend.
7409 /// This matches the extremely common pattern for handling combined
7410 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7412 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7416 SelectionDAG &DAG) {
7417 // Shuffle the input elements into the desired positions in V1 and V2 and
7418 // blend them together.
7419 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7420 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7421 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7422 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7423 if (Mask[i] >= 0 && Mask[i] < Size) {
7424 V1Mask[i] = Mask[i];
7426 } else if (Mask[i] >= Size) {
7427 V2Mask[i] = Mask[i] - Size;
7428 BlendMask[i] = i + Size;
7431 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7432 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7433 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7436 /// \brief Try to lower a vector shuffle as a byte rotation.
7438 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7439 /// byte-rotation of a the concatentation of two vectors. This routine will
7440 /// try to generically lower a vector shuffle through such an instruction. It
7441 /// does not check for the availability of PALIGNR-based lowerings, only the
7442 /// applicability of this strategy to the given mask. This matches shuffle
7443 /// vectors that look like:
7445 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7447 /// Essentially it concatenates V1 and V2, shifts right by some number of
7448 /// elements, and takes the low elements as the result. Note that while this is
7449 /// specified as a *right shift* because x86 is little-endian, it is a *left
7450 /// rotate* of the vector lanes.
7452 /// Note that this only handles 128-bit vector widths currently.
7453 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7456 SelectionDAG &DAG) {
7457 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7459 // We need to detect various ways of spelling a rotation:
7460 // [11, 12, 13, 14, 15, 0, 1, 2]
7461 // [-1, 12, 13, 14, -1, -1, 1, -1]
7462 // [-1, -1, -1, -1, -1, -1, 1, 2]
7463 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7464 // [-1, 4, 5, 6, -1, -1, 9, -1]
7465 // [-1, 4, 5, 6, -1, -1, -1, -1]
7468 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7471 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7473 // Based on the mod-Size value of this mask element determine where
7474 // a rotated vector would have started.
7475 int StartIdx = i - (Mask[i] % Size);
7477 // The identity rotation isn't interesting, stop.
7480 // If we found the tail of a vector the rotation must be the missing
7481 // front. If we found the head of a vector, it must be how much of the head.
7482 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7485 Rotation = CandidateRotation;
7486 else if (Rotation != CandidateRotation)
7487 // The rotations don't match, so we can't match this mask.
7490 // Compute which value this mask is pointing at.
7491 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7493 // Compute which of the two target values this index should be assigned to.
7494 // This reflects whether the high elements are remaining or the low elements
7496 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7498 // Either set up this value if we've not encountered it before, or check
7499 // that it remains consistent.
7502 else if (TargetV != MaskV)
7503 // This may be a rotation, but it pulls from the inputs in some
7504 // unsupported interleaving.
7508 // Check that we successfully analyzed the mask, and normalize the results.
7509 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7510 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7516 // Cast the inputs to v16i8 to match PALIGNR.
7517 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7518 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7520 assert(VT.getSizeInBits() == 128 &&
7521 "Rotate-based lowering only supports 128-bit lowering!");
7522 assert(Mask.size() <= 16 &&
7523 "Can shuffle at most 16 bytes in a 128-bit vector!");
7524 // The actual rotate instruction rotates bytes, so we need to scale the
7525 // rotation based on how many bytes are in the vector.
7526 int Scale = 16 / Mask.size();
7528 return DAG.getNode(ISD::BITCAST, DL, VT,
7529 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7530 DAG.getConstant(Rotation * Scale, MVT::i8)));
7533 /// \brief Compute whether each element of a shuffle is zeroable.
7535 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7536 /// Either it is an undef element in the shuffle mask, the element of the input
7537 /// referenced is undef, or the element of the input referenced is known to be
7538 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7539 /// as many lanes with this technique as possible to simplify the remaining
7541 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7542 SDValue V1, SDValue V2) {
7543 SmallBitVector Zeroable(Mask.size(), false);
7545 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7546 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7548 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7550 // Handle the easy cases.
7551 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7556 // If this is an index into a build_vector node, dig out the input value and
7558 SDValue V = M < Size ? V1 : V2;
7559 if (V.getOpcode() != ISD::BUILD_VECTOR)
7562 SDValue Input = V.getOperand(M % Size);
7563 // The UNDEF opcode check really should be dead code here, but not quite
7564 // worth asserting on (it isn't invalid, just unexpected).
7565 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7572 /// \brief Lower a vector shuffle as a zero or any extension.
7574 /// Given a specific number of elements, element bit width, and extension
7575 /// stride, produce either a zero or any extension based on the available
7576 /// features of the subtarget.
7577 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7578 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7579 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7580 assert(Scale > 1 && "Need a scale to extend.");
7581 int EltBits = VT.getSizeInBits() / NumElements;
7582 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7583 "Only 8, 16, and 32 bit elements can be extended.");
7584 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7586 // Found a valid zext mask! Try various lowering strategies based on the
7587 // input type and available ISA extensions.
7588 if (Subtarget->hasSSE41()) {
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7591 NumElements / Scale);
7592 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7593 return DAG.getNode(ISD::BITCAST, DL, VT,
7594 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7597 // For any extends we can cheat for larger element sizes and use shuffle
7598 // instructions that can fold with a load and/or copy.
7599 if (AnyExt && EltBits == 32) {
7600 int PSHUFDMask[4] = {0, -1, 1, -1};
7602 ISD::BITCAST, DL, VT,
7603 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7604 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7605 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7607 if (AnyExt && EltBits == 16 && Scale > 2) {
7608 int PSHUFDMask[4] = {0, -1, 0, -1};
7609 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7610 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7611 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7612 int PSHUFHWMask[4] = {1, -1, -1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7620 // If this would require more than 2 unpack instructions to expand, use
7621 // pshufb when available. We can only use more than 2 unpack instructions
7622 // when zero extending i8 elements which also makes it easier to use pshufb.
7623 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7624 assert(NumElements == 16 && "Unexpected byte vector width!");
7625 SDValue PSHUFBMask[16];
7626 for (int i = 0; i < 16; ++i)
7628 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7629 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7630 return DAG.getNode(ISD::BITCAST, DL, VT,
7631 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7632 DAG.getNode(ISD::BUILD_VECTOR, DL,
7633 MVT::v16i8, PSHUFBMask)));
7636 // Otherwise emit a sequence of unpacks.
7638 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7639 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7640 : getZeroVector(InputVT, Subtarget, DAG, DL);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7642 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7646 } while (Scale > 1);
7647 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7650 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7652 /// This routine will try to do everything in its power to cleverly lower
7653 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7654 /// check for the profitability of this lowering, it tries to aggressively
7655 /// match this pattern. It will use all of the micro-architectural details it
7656 /// can to emit an efficient lowering. It handles both blends with all-zero
7657 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7658 /// masking out later).
7660 /// The reason we have dedicated lowering for zext-style shuffles is that they
7661 /// are both incredibly common and often quite performance sensitive.
7662 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7663 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7664 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7665 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7667 int Bits = VT.getSizeInBits();
7668 int NumElements = Mask.size();
7670 // Define a helper function to check a particular ext-scale and lower to it if
7672 auto Lower = [&](int Scale) -> SDValue {
7675 for (int i = 0; i < NumElements; ++i) {
7677 continue; // Valid anywhere but doesn't tell us anything.
7678 if (i % Scale != 0) {
7679 // Each of the extend elements needs to be zeroable.
7683 // We no lorger are in the anyext case.
7688 // Each of the base elements needs to be consecutive indices into the
7689 // same input vector.
7690 SDValue V = Mask[i] < NumElements ? V1 : V2;
7693 else if (InputV != V)
7694 return SDValue(); // Flip-flopping inputs.
7696 if (Mask[i] % NumElements != i / Scale)
7697 return SDValue(); // Non-consecutive strided elemenst.
7700 // If we fail to find an input, we have a zero-shuffle which should always
7701 // have already been handled.
7702 // FIXME: Maybe handle this here in case during blending we end up with one?
7706 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7707 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7710 // The widest scale possible for extending is to a 64-bit integer.
7711 assert(Bits % 64 == 0 &&
7712 "The number of bits in a vector must be divisible by 64 on x86!");
7713 int NumExtElements = Bits / 64;
7715 // Each iteration, try extending the elements half as much, but into twice as
7717 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7718 assert(NumElements % NumExtElements == 0 &&
7719 "The input vector size must be divisble by the extended size.");
7720 if (SDValue V = Lower(NumElements / NumExtElements))
7724 // No viable ext lowering found.
7728 /// \brief Try to lower insertion of a single element into a zero vector.
7730 /// This is a common pattern that we have especially efficient patterns to lower
7731 /// across all subtarget feature sets.
7732 static SDValue lowerVectorShuffleAsElementInsertion(
7733 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7734 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7735 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7737 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7738 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7740 if (Mask.size() == 2) {
7741 if (!Zeroable[V2Index ^ 1]) {
7742 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7743 // with 2 to flip from {2,3} to {0,1} and vice versa.
7744 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7745 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7746 if (Zeroable[V2Index])
7747 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7753 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7754 if (i != V2Index && !Zeroable[i])
7755 return SDValue(); // Not inserting into a zero vector.
7758 // Step over any bitcasts on either input so we can scan the actual
7759 // BUILD_VECTOR nodes.
7760 while (V1.getOpcode() == ISD::BITCAST)
7761 V1 = V1.getOperand(0);
7762 while (V2.getOpcode() == ISD::BITCAST)
7763 V2 = V2.getOperand(0);
7765 // Check for a single input from a SCALAR_TO_VECTOR node.
7766 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7767 // all the smarts here sunk into that routine. However, the current
7768 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7769 // vector shuffle lowering is dead.
7770 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7771 Mask[V2Index] == (int)Mask.size()) ||
7772 V2.getOpcode() == ISD::BUILD_VECTOR))
7775 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7777 // First, we need to zext the scalar if it is smaller than an i32.
7779 MVT EltVT = VT.getVectorElementType();
7780 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7781 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7782 // Zero-extend directly to i32.
7784 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7787 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7788 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7790 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7793 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7794 // the desired position. Otherwise it is more efficient to do a vector
7795 // shift left. We know that we can do a vector shift left because all
7796 // the inputs are zero.
7797 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7798 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7799 V2Shuffle[V2Index] = 0;
7800 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7802 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7804 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7806 V2Index * EltVT.getSizeInBits(),
7807 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7808 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7814 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7816 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7817 /// support for floating point shuffles but not integer shuffles. These
7818 /// instructions will incur a domain crossing penalty on some chips though so
7819 /// it is better to avoid lowering through this for integer vectors where
7821 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7822 const X86Subtarget *Subtarget,
7823 SelectionDAG &DAG) {
7825 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7826 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7827 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7829 ArrayRef<int> Mask = SVOp->getMask();
7830 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7832 if (isSingleInputShuffleMask(Mask)) {
7833 // Straight shuffle of a single input vector. Simulate this by using the
7834 // single input as both of the "inputs" to this instruction..
7835 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7837 if (Subtarget->hasAVX()) {
7838 // If we have AVX, we can use VPERMILPS which will allow folding a load
7839 // into the shuffle.
7840 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7841 DAG.getConstant(SHUFPDMask, MVT::i8));
7844 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7845 DAG.getConstant(SHUFPDMask, MVT::i8));
7847 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7848 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7850 // Use dedicated unpack instructions for masks that match their pattern.
7851 if (isShuffleEquivalent(Mask, 0, 2))
7852 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7853 if (isShuffleEquivalent(Mask, 1, 3))
7854 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7856 // If we have a single input, insert that into V1 if we can do so cheaply.
7857 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7858 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7859 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7862 if (Subtarget->hasSSE41())
7863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7867 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7868 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7869 DAG.getConstant(SHUFPDMask, MVT::i8));
7872 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7874 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7875 /// the integer unit to minimize domain crossing penalties. However, for blends
7876 /// it falls back to the floating point shuffle operation with appropriate bit
7878 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7882 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7883 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7884 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7886 ArrayRef<int> Mask = SVOp->getMask();
7887 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7889 if (isSingleInputShuffleMask(Mask)) {
7890 // Straight shuffle of a single input vector. For everything from SSE2
7891 // onward this has a single fast instruction with no scary immediates.
7892 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7893 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7894 int WidenedMask[4] = {
7895 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7896 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7898 ISD::BITCAST, DL, MVT::v2i64,
7899 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7900 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7903 // Use dedicated unpack instructions for masks that match their pattern.
7904 if (isShuffleEquivalent(Mask, 0, 2))
7905 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7906 if (isShuffleEquivalent(Mask, 1, 3))
7907 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7909 // If we have a single input from V2 insert that into V1 if we can do so
7911 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7912 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7913 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7916 if (Subtarget->hasSSE41())
7917 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7921 // Try to use rotation instructions if available.
7922 if (Subtarget->hasSSSE3())
7923 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7924 DL, MVT::v2i64, V1, V2, Mask, DAG))
7927 // We implement this with SHUFPD which is pretty lame because it will likely
7928 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7929 // However, all the alternatives are still more cycles and newer chips don't
7930 // have this problem. It would be really nice if x86 had better shuffles here.
7931 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7932 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7933 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7934 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7937 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7939 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7940 /// It makes no assumptions about whether this is the *best* lowering, it simply
7942 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7943 ArrayRef<int> Mask, SDValue V1,
7944 SDValue V2, SelectionDAG &DAG) {
7945 SDValue LowV = V1, HighV = V2;
7946 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7949 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7951 if (NumV2Elements == 1) {
7953 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7956 // Compute the index adjacent to V2Index and in the same half by toggling
7958 int V2AdjIndex = V2Index ^ 1;
7960 if (Mask[V2AdjIndex] == -1) {
7961 // Handles all the cases where we have a single V2 element and an undef.
7962 // This will only ever happen in the high lanes because we commute the
7963 // vector otherwise.
7965 std::swap(LowV, HighV);
7966 NewMask[V2Index] -= 4;
7968 // Handle the case where the V2 element ends up adjacent to a V1 element.
7969 // To make this work, blend them together as the first step.
7970 int V1Index = V2AdjIndex;
7971 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7972 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7973 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7975 // Now proceed to reconstruct the final blend as we have the necessary
7976 // high or low half formed.
7983 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7984 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7986 } else if (NumV2Elements == 2) {
7987 if (Mask[0] < 4 && Mask[1] < 4) {
7988 // Handle the easy case where we have V1 in the low lanes and V2 in the
7992 } else if (Mask[2] < 4 && Mask[3] < 4) {
7993 // We also handle the reversed case because this utility may get called
7994 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7995 // arrange things in the right direction.
8001 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8002 // trying to place elements directly, just blend them and set up the final
8003 // shuffle to place them.
8005 // The first two blend mask elements are for V1, the second two are for
8007 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8008 Mask[2] < 4 ? Mask[2] : Mask[3],
8009 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8010 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8011 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8012 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8014 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8017 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8018 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8019 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8020 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8023 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8024 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8027 /// \brief Lower 4-lane 32-bit floating point shuffles.
8029 /// Uses instructions exclusively from the floating point unit to minimize
8030 /// domain crossing penalties, as these are sufficient to implement all v4f32
8032 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8033 const X86Subtarget *Subtarget,
8034 SelectionDAG &DAG) {
8036 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8037 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8038 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8040 ArrayRef<int> Mask = SVOp->getMask();
8041 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8044 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8046 if (NumV2Elements == 0) {
8047 if (Subtarget->hasAVX()) {
8048 // If we have AVX, we can use VPERMILPS which will allow folding a load
8049 // into the shuffle.
8050 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8051 getV4X86ShuffleImm8ForMask(Mask, DAG));
8054 // Otherwise, use a straight shuffle of a single input vector. We pass the
8055 // input vector to both operands to simulate this with a SHUFPS.
8056 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8057 getV4X86ShuffleImm8ForMask(Mask, DAG));
8060 // Use dedicated unpack instructions for masks that match their pattern.
8061 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8062 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8063 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8064 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8066 // There are special ways we can lower some single-element blends. However, we
8067 // have custom ways we can lower more complex single-element blends below that
8068 // we defer to if both this and BLENDPS fail to match, so restrict this to
8069 // when the V2 input is targeting element 0 of the mask -- that is the fast
8071 if (NumV2Elements == 1 && Mask[0] >= 4)
8072 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8073 Mask, Subtarget, DAG))
8076 if (Subtarget->hasSSE41())
8077 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8081 // Check for whether we can use INSERTPS to perform the blend. We only use
8082 // INSERTPS when the V1 elements are already in the correct locations
8083 // because otherwise we can just always use two SHUFPS instructions which
8084 // are much smaller to encode than a SHUFPS and an INSERTPS.
8085 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8087 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8090 // When using INSERTPS we can zero any lane of the destination. Collect
8091 // the zero inputs into a mask and drop them from the lanes of V1 which
8092 // actually need to be present as inputs to the INSERTPS.
8093 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8095 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8096 bool InsertNeedsShuffle = false;
8098 for (int i = 0; i < 4; ++i)
8102 } else if (Mask[i] != i) {
8103 InsertNeedsShuffle = true;
8108 // We don't want to use INSERTPS or other insertion techniques if it will
8109 // require shuffling anyways.
8110 if (!InsertNeedsShuffle) {
8111 // If all of V1 is zeroable, replace it with undef.
8112 if ((ZMask | 1 << V2Index) == 0xF)
8113 V1 = DAG.getUNDEF(MVT::v4f32);
8115 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8116 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8118 // Insert the V2 element into the desired position.
8119 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8120 DAG.getConstant(InsertPSMask, MVT::i8));
8124 // Otherwise fall back to a SHUFPS lowering strategy.
8125 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8128 /// \brief Lower 4-lane i32 vector shuffles.
8130 /// We try to handle these with integer-domain shuffles where we can, but for
8131 /// blends we use the floating point domain blend instructions.
8132 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8133 const X86Subtarget *Subtarget,
8134 SelectionDAG &DAG) {
8136 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8137 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8138 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8140 ArrayRef<int> Mask = SVOp->getMask();
8141 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8144 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8146 if (NumV2Elements == 0) {
8147 // Straight shuffle of a single input vector. For everything from SSE2
8148 // onward this has a single fast instruction with no scary immediates.
8149 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8150 // but we aren't actually going to use the UNPCK instruction because doing
8151 // so prevents folding a load into this instruction or making a copy.
8152 const int UnpackLoMask[] = {0, 0, 1, 1};
8153 const int UnpackHiMask[] = {2, 2, 3, 3};
8154 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8155 Mask = UnpackLoMask;
8156 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8157 Mask = UnpackHiMask;
8159 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8160 getV4X86ShuffleImm8ForMask(Mask, DAG));
8163 // Whenever we can lower this as a zext, that instruction is strictly faster
8164 // than any alternative.
8165 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8166 Mask, Subtarget, DAG))
8169 // Use dedicated unpack instructions for masks that match their pattern.
8170 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8171 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8172 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8173 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8175 // There are special ways we can lower some single-element blends.
8176 if (NumV2Elements == 1)
8177 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8178 Mask, Subtarget, DAG))
8181 if (Subtarget->hasSSE41())
8182 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8186 // Try to use rotation instructions if available.
8187 if (Subtarget->hasSSSE3())
8188 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8189 DL, MVT::v4i32, V1, V2, Mask, DAG))
8192 // We implement this with SHUFPS because it can blend from two vectors.
8193 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8194 // up the inputs, bypassing domain shift penalties that we would encur if we
8195 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8197 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8198 DAG.getVectorShuffle(
8200 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8201 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8204 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8205 /// shuffle lowering, and the most complex part.
8207 /// The lowering strategy is to try to form pairs of input lanes which are
8208 /// targeted at the same half of the final vector, and then use a dword shuffle
8209 /// to place them onto the right half, and finally unpack the paired lanes into
8210 /// their final position.
8212 /// The exact breakdown of how to form these dword pairs and align them on the
8213 /// correct sides is really tricky. See the comments within the function for
8214 /// more of the details.
8215 static SDValue lowerV8I16SingleInputVectorShuffle(
8216 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8217 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8218 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8219 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8220 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8222 SmallVector<int, 4> LoInputs;
8223 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8224 [](int M) { return M >= 0; });
8225 std::sort(LoInputs.begin(), LoInputs.end());
8226 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8227 SmallVector<int, 4> HiInputs;
8228 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8229 [](int M) { return M >= 0; });
8230 std::sort(HiInputs.begin(), HiInputs.end());
8231 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8233 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8234 int NumHToL = LoInputs.size() - NumLToL;
8236 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8237 int NumHToH = HiInputs.size() - NumLToH;
8238 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8239 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8240 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8241 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8243 // Use dedicated unpack instructions for masks that match their pattern.
8244 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8246 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8247 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8249 // Try to use rotation instructions if available.
8250 if (Subtarget->hasSSSE3())
8251 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8252 DL, MVT::v8i16, V, V, Mask, DAG))
8255 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8256 // such inputs we can swap two of the dwords across the half mark and end up
8257 // with <=2 inputs to each half in each half. Once there, we can fall through
8258 // to the generic code below. For example:
8260 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8261 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8263 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8264 // and an existing 2-into-2 on the other half. In this case we may have to
8265 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8266 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8267 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8268 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8269 // half than the one we target for fixing) will be fixed when we re-enter this
8270 // path. We will also combine away any sequence of PSHUFD instructions that
8271 // result into a single instruction. Here is an example of the tricky case:
8273 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8274 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8276 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8278 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8279 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8281 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8282 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8284 // The result is fine to be handled by the generic logic.
8285 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8286 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8287 int AOffset, int BOffset) {
8288 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8289 "Must call this with A having 3 or 1 inputs from the A half.");
8290 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8291 "Must call this with B having 1 or 3 inputs from the B half.");
8292 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8293 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8295 // Compute the index of dword with only one word among the three inputs in
8296 // a half by taking the sum of the half with three inputs and subtracting
8297 // the sum of the actual three inputs. The difference is the remaining
8300 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8301 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8302 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8303 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8304 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8305 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8306 int TripleNonInputIdx =
8307 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8308 TripleDWord = TripleNonInputIdx / 2;
8310 // We use xor with one to compute the adjacent DWord to whichever one the
8312 OneInputDWord = (OneInput / 2) ^ 1;
8314 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8315 // and BToA inputs. If there is also such a problem with the BToB and AToB
8316 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8317 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8318 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8319 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8320 // Compute how many inputs will be flipped by swapping these DWords. We
8322 // to balance this to ensure we don't form a 3-1 shuffle in the other
8324 int NumFlippedAToBInputs =
8325 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8326 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8327 int NumFlippedBToBInputs =
8328 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8329 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8330 if ((NumFlippedAToBInputs == 1 &&
8331 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8332 (NumFlippedBToBInputs == 1 &&
8333 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8334 // We choose whether to fix the A half or B half based on whether that
8335 // half has zero flipped inputs. At zero, we may not be able to fix it
8336 // with that half. We also bias towards fixing the B half because that
8337 // will more commonly be the high half, and we have to bias one way.
8338 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8339 ArrayRef<int> Inputs) {
8340 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8341 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8342 PinnedIdx ^ 1) != Inputs.end();
8343 // Determine whether the free index is in the flipped dword or the
8344 // unflipped dword based on where the pinned index is. We use this bit
8345 // in an xor to conditionally select the adjacent dword.
8346 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8347 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8348 FixFreeIdx) != Inputs.end();
8349 if (IsFixIdxInput == IsFixFreeIdxInput)
8351 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8352 FixFreeIdx) != Inputs.end();
8353 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8354 "We need to be changing the number of flipped inputs!");
8355 int PSHUFHalfMask[] = {0, 1, 2, 3};
8356 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8357 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8359 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8362 if (M != -1 && M == FixIdx)
8364 else if (M != -1 && M == FixFreeIdx)
8367 if (NumFlippedBToBInputs != 0) {
8369 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8370 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8372 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8374 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8375 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8380 int PSHUFDMask[] = {0, 1, 2, 3};
8381 PSHUFDMask[ADWord] = BDWord;
8382 PSHUFDMask[BDWord] = ADWord;
8383 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8384 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8385 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8386 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8388 // Adjust the mask to match the new locations of A and B.
8390 if (M != -1 && M/2 == ADWord)
8391 M = 2 * BDWord + M % 2;
8392 else if (M != -1 && M/2 == BDWord)
8393 M = 2 * ADWord + M % 2;
8395 // Recurse back into this routine to re-compute state now that this isn't
8396 // a 3 and 1 problem.
8397 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8400 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8401 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8402 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8403 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8405 // At this point there are at most two inputs to the low and high halves from
8406 // each half. That means the inputs can always be grouped into dwords and
8407 // those dwords can then be moved to the correct half with a dword shuffle.
8408 // We use at most one low and one high word shuffle to collect these paired
8409 // inputs into dwords, and finally a dword shuffle to place them.
8410 int PSHUFLMask[4] = {-1, -1, -1, -1};
8411 int PSHUFHMask[4] = {-1, -1, -1, -1};
8412 int PSHUFDMask[4] = {-1, -1, -1, -1};
8414 // First fix the masks for all the inputs that are staying in their
8415 // original halves. This will then dictate the targets of the cross-half
8417 auto fixInPlaceInputs =
8418 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8419 MutableArrayRef<int> SourceHalfMask,
8420 MutableArrayRef<int> HalfMask, int HalfOffset) {
8421 if (InPlaceInputs.empty())
8423 if (InPlaceInputs.size() == 1) {
8424 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8425 InPlaceInputs[0] - HalfOffset;
8426 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8429 if (IncomingInputs.empty()) {
8430 // Just fix all of the in place inputs.
8431 for (int Input : InPlaceInputs) {
8432 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8433 PSHUFDMask[Input / 2] = Input / 2;
8438 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8439 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8440 InPlaceInputs[0] - HalfOffset;
8441 // Put the second input next to the first so that they are packed into
8442 // a dword. We find the adjacent index by toggling the low bit.
8443 int AdjIndex = InPlaceInputs[0] ^ 1;
8444 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8445 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8446 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8448 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8449 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8451 // Now gather the cross-half inputs and place them into a free dword of
8452 // their target half.
8453 // FIXME: This operation could almost certainly be simplified dramatically to
8454 // look more like the 3-1 fixing operation.
8455 auto moveInputsToRightHalf = [&PSHUFDMask](
8456 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8457 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8458 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8460 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8461 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8463 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8465 int LowWord = Word & ~1;
8466 int HighWord = Word | 1;
8467 return isWordClobbered(SourceHalfMask, LowWord) ||
8468 isWordClobbered(SourceHalfMask, HighWord);
8471 if (IncomingInputs.empty())
8474 if (ExistingInputs.empty()) {
8475 // Map any dwords with inputs from them into the right half.
8476 for (int Input : IncomingInputs) {
8477 // If the source half mask maps over the inputs, turn those into
8478 // swaps and use the swapped lane.
8479 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8480 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8481 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8482 Input - SourceOffset;
8483 // We have to swap the uses in our half mask in one sweep.
8484 for (int &M : HalfMask)
8485 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8487 else if (M == Input)
8488 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8490 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8491 Input - SourceOffset &&
8492 "Previous placement doesn't match!");
8494 // Note that this correctly re-maps both when we do a swap and when
8495 // we observe the other side of the swap above. We rely on that to
8496 // avoid swapping the members of the input list directly.
8497 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8500 // Map the input's dword into the correct half.
8501 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8502 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8504 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8506 "Previous placement doesn't match!");
8509 // And just directly shift any other-half mask elements to be same-half
8510 // as we will have mirrored the dword containing the element into the
8511 // same position within that half.
8512 for (int &M : HalfMask)
8513 if (M >= SourceOffset && M < SourceOffset + 4) {
8514 M = M - SourceOffset + DestOffset;
8515 assert(M >= 0 && "This should never wrap below zero!");
8520 // Ensure we have the input in a viable dword of its current half. This
8521 // is particularly tricky because the original position may be clobbered
8522 // by inputs being moved and *staying* in that half.
8523 if (IncomingInputs.size() == 1) {
8524 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8525 int InputFixed = std::find(std::begin(SourceHalfMask),
8526 std::end(SourceHalfMask), -1) -
8527 std::begin(SourceHalfMask) + SourceOffset;
8528 SourceHalfMask[InputFixed - SourceOffset] =
8529 IncomingInputs[0] - SourceOffset;
8530 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8532 IncomingInputs[0] = InputFixed;
8534 } else if (IncomingInputs.size() == 2) {
8535 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8536 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8537 // We have two non-adjacent or clobbered inputs we need to extract from
8538 // the source half. To do this, we need to map them into some adjacent
8539 // dword slot in the source mask.
8540 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8541 IncomingInputs[1] - SourceOffset};
8543 // If there is a free slot in the source half mask adjacent to one of
8544 // the inputs, place the other input in it. We use (Index XOR 1) to
8545 // compute an adjacent index.
8546 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8547 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8548 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8549 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8550 InputsFixed[1] = InputsFixed[0] ^ 1;
8551 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8552 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8553 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8554 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8555 InputsFixed[0] = InputsFixed[1] ^ 1;
8556 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8557 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8558 // The two inputs are in the same DWord but it is clobbered and the
8559 // adjacent DWord isn't used at all. Move both inputs to the free
8561 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8562 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8563 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8564 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8566 // The only way we hit this point is if there is no clobbering
8567 // (because there are no off-half inputs to this half) and there is no
8568 // free slot adjacent to one of the inputs. In this case, we have to
8569 // swap an input with a non-input.
8570 for (int i = 0; i < 4; ++i)
8571 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8572 "We can't handle any clobbers here!");
8573 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8574 "Cannot have adjacent inputs here!");
8576 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8577 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8579 // We also have to update the final source mask in this case because
8580 // it may need to undo the above swap.
8581 for (int &M : FinalSourceHalfMask)
8582 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8583 M = InputsFixed[1] + SourceOffset;
8584 else if (M == InputsFixed[1] + SourceOffset)
8585 M = (InputsFixed[0] ^ 1) + SourceOffset;
8587 InputsFixed[1] = InputsFixed[0] ^ 1;
8590 // Point everything at the fixed inputs.
8591 for (int &M : HalfMask)
8592 if (M == IncomingInputs[0])
8593 M = InputsFixed[0] + SourceOffset;
8594 else if (M == IncomingInputs[1])
8595 M = InputsFixed[1] + SourceOffset;
8597 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8598 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8601 llvm_unreachable("Unhandled input size!");
8604 // Now hoist the DWord down to the right half.
8605 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8606 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8607 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8608 for (int &M : HalfMask)
8609 for (int Input : IncomingInputs)
8611 M = FreeDWord * 2 + Input % 2;
8613 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8614 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8615 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8616 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8618 // Now enact all the shuffles we've computed to move the inputs into their
8620 if (!isNoopShuffleMask(PSHUFLMask))
8621 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8622 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8623 if (!isNoopShuffleMask(PSHUFHMask))
8624 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8625 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8626 if (!isNoopShuffleMask(PSHUFDMask))
8627 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8628 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8629 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8630 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8632 // At this point, each half should contain all its inputs, and we can then
8633 // just shuffle them into their final position.
8634 assert(std::count_if(LoMask.begin(), LoMask.end(),
8635 [](int M) { return M >= 4; }) == 0 &&
8636 "Failed to lift all the high half inputs to the low mask!");
8637 assert(std::count_if(HiMask.begin(), HiMask.end(),
8638 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8639 "Failed to lift all the low half inputs to the high mask!");
8641 // Do a half shuffle for the low mask.
8642 if (!isNoopShuffleMask(LoMask))
8643 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8644 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8646 // Do a half shuffle with the high mask after shifting its values down.
8647 for (int &M : HiMask)
8650 if (!isNoopShuffleMask(HiMask))
8651 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8652 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8657 /// \brief Detect whether the mask pattern should be lowered through
8660 /// This essentially tests whether viewing the mask as an interleaving of two
8661 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8662 /// lowering it through interleaving is a significantly better strategy.
8663 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8664 int NumEvenInputs[2] = {0, 0};
8665 int NumOddInputs[2] = {0, 0};
8666 int NumLoInputs[2] = {0, 0};
8667 int NumHiInputs[2] = {0, 0};
8668 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8672 int InputIdx = Mask[i] >= Size;
8675 ++NumLoInputs[InputIdx];
8677 ++NumHiInputs[InputIdx];
8680 ++NumEvenInputs[InputIdx];
8682 ++NumOddInputs[InputIdx];
8685 // The minimum number of cross-input results for both the interleaved and
8686 // split cases. If interleaving results in fewer cross-input results, return
8688 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8689 NumEvenInputs[0] + NumOddInputs[1]);
8690 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8691 NumLoInputs[0] + NumHiInputs[1]);
8692 return InterleavedCrosses < SplitCrosses;
8695 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8697 /// This strategy only works when the inputs from each vector fit into a single
8698 /// half of that vector, and generally there are not so many inputs as to leave
8699 /// the in-place shuffles required highly constrained (and thus expensive). It
8700 /// shifts all the inputs into a single side of both input vectors and then
8701 /// uses an unpack to interleave these inputs in a single vector. At that
8702 /// point, we will fall back on the generic single input shuffle lowering.
8703 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8705 MutableArrayRef<int> Mask,
8706 const X86Subtarget *Subtarget,
8707 SelectionDAG &DAG) {
8708 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8709 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8710 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8711 for (int i = 0; i < 8; ++i)
8712 if (Mask[i] >= 0 && Mask[i] < 4)
8713 LoV1Inputs.push_back(i);
8714 else if (Mask[i] >= 4 && Mask[i] < 8)
8715 HiV1Inputs.push_back(i);
8716 else if (Mask[i] >= 8 && Mask[i] < 12)
8717 LoV2Inputs.push_back(i);
8718 else if (Mask[i] >= 12)
8719 HiV2Inputs.push_back(i);
8721 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8722 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8725 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8726 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8727 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8729 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8730 HiV1Inputs.size() + HiV2Inputs.size();
8732 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8733 ArrayRef<int> HiInputs, bool MoveToLo,
8735 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8736 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8737 if (BadInputs.empty())
8740 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8741 int MoveOffset = MoveToLo ? 0 : 4;
8743 if (GoodInputs.empty()) {
8744 for (int BadInput : BadInputs) {
8745 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8746 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8749 if (GoodInputs.size() == 2) {
8750 // If the low inputs are spread across two dwords, pack them into
8752 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8753 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8754 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8755 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8757 // Otherwise pin the good inputs.
8758 for (int GoodInput : GoodInputs)
8759 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8762 if (BadInputs.size() == 2) {
8763 // If we have two bad inputs then there may be either one or two good
8764 // inputs fixed in place. Find a fixed input, and then find the *other*
8765 // two adjacent indices by using modular arithmetic.
8767 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8768 [](int M) { return M >= 0; }) -
8769 std::begin(MoveMask);
8771 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8772 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8773 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8774 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8775 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8776 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8777 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8779 assert(BadInputs.size() == 1 && "All sizes handled");
8780 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8781 std::end(MoveMask), -1) -
8782 std::begin(MoveMask);
8783 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8784 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8788 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8791 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8793 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8796 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8797 // cross-half traffic in the final shuffle.
8799 // Munge the mask to be a single-input mask after the unpack merges the
8803 M = 2 * (M % 4) + (M / 8);
8805 return DAG.getVectorShuffle(
8806 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8807 DL, MVT::v8i16, V1, V2),
8808 DAG.getUNDEF(MVT::v8i16), Mask);
8811 /// \brief Generic lowering of 8-lane i16 shuffles.
8813 /// This handles both single-input shuffles and combined shuffle/blends with
8814 /// two inputs. The single input shuffles are immediately delegated to
8815 /// a dedicated lowering routine.
8817 /// The blends are lowered in one of three fundamental ways. If there are few
8818 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8819 /// of the input is significantly cheaper when lowered as an interleaving of
8820 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8821 /// halves of the inputs separately (making them have relatively few inputs)
8822 /// and then concatenate them.
8823 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8824 const X86Subtarget *Subtarget,
8825 SelectionDAG &DAG) {
8827 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8828 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8829 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8831 ArrayRef<int> OrigMask = SVOp->getMask();
8832 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8833 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8834 MutableArrayRef<int> Mask(MaskStorage);
8836 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8838 // Whenever we can lower this as a zext, that instruction is strictly faster
8839 // than any alternative.
8840 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8841 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8844 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8845 auto isV2 = [](int M) { return M >= 8; };
8847 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8848 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8850 if (NumV2Inputs == 0)
8851 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8853 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8854 "to be V1-input shuffles.");
8856 // There are special ways we can lower some single-element blends.
8857 if (NumV2Inputs == 1)
8858 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8859 Mask, Subtarget, DAG))
8862 if (Subtarget->hasSSE41())
8863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8867 // Try to use rotation instructions if available.
8868 if (Subtarget->hasSSSE3())
8869 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8872 if (NumV1Inputs + NumV2Inputs <= 4)
8873 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8875 // Check whether an interleaving lowering is likely to be more efficient.
8876 // This isn't perfect but it is a strong heuristic that tends to work well on
8877 // the kinds of shuffles that show up in practice.
8879 // FIXME: Handle 1x, 2x, and 4x interleaving.
8880 if (shouldLowerAsInterleaving(Mask)) {
8881 // FIXME: Figure out whether we should pack these into the low or high
8884 int EMask[8], OMask[8];
8885 for (int i = 0; i < 4; ++i) {
8886 EMask[i] = Mask[2*i];
8887 OMask[i] = Mask[2*i + 1];
8892 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8893 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8895 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8898 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8899 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8901 for (int i = 0; i < 4; ++i) {
8902 LoBlendMask[i] = Mask[i];
8903 HiBlendMask[i] = Mask[i + 4];
8906 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8907 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8908 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8909 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8911 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8912 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8915 /// \brief Check whether a compaction lowering can be done by dropping even
8916 /// elements and compute how many times even elements must be dropped.
8918 /// This handles shuffles which take every Nth element where N is a power of
8919 /// two. Example shuffle masks:
8921 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8922 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8923 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8924 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8925 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8926 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8928 /// Any of these lanes can of course be undef.
8930 /// This routine only supports N <= 3.
8931 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8934 /// \returns N above, or the number of times even elements must be dropped if
8935 /// there is such a number. Otherwise returns zero.
8936 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8937 // Figure out whether we're looping over two inputs or just one.
8938 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8940 // The modulus for the shuffle vector entries is based on whether this is
8941 // a single input or not.
8942 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8943 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8944 "We should only be called with masks with a power-of-2 size!");
8946 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8948 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8949 // and 2^3 simultaneously. This is because we may have ambiguity with
8950 // partially undef inputs.
8951 bool ViableForN[3] = {true, true, true};
8953 for (int i = 0, e = Mask.size(); i < e; ++i) {
8954 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8959 bool IsAnyViable = false;
8960 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8961 if (ViableForN[j]) {
8964 // The shuffle mask must be equal to (i * 2^N) % M.
8965 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8968 ViableForN[j] = false;
8970 // Early exit if we exhaust the possible powers of two.
8975 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8979 // Return 0 as there is no viable power of two.
8983 /// \brief Generic lowering of v16i8 shuffles.
8985 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8986 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8987 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8988 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8990 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8991 const X86Subtarget *Subtarget,
8992 SelectionDAG &DAG) {
8994 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8995 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8996 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8998 ArrayRef<int> OrigMask = SVOp->getMask();
8999 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9001 // Try to use rotation instructions if available.
9002 if (Subtarget->hasSSSE3())
9003 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9007 // Try to use a zext lowering.
9008 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9009 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9012 int MaskStorage[16] = {
9013 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9014 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9015 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9016 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9017 MutableArrayRef<int> Mask(MaskStorage);
9018 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9019 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9022 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9024 // For single-input shuffles, there are some nicer lowering tricks we can use.
9025 if (NumV2Elements == 0) {
9026 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9027 // Notably, this handles splat and partial-splat shuffles more efficiently.
9028 // However, it only makes sense if the pre-duplication shuffle simplifies
9029 // things significantly. Currently, this means we need to be able to
9030 // express the pre-duplication shuffle as an i16 shuffle.
9032 // FIXME: We should check for other patterns which can be widened into an
9033 // i16 shuffle as well.
9034 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9035 for (int i = 0; i < 16; i += 2)
9036 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9041 auto tryToWidenViaDuplication = [&]() -> SDValue {
9042 if (!canWidenViaDuplication(Mask))
9044 SmallVector<int, 4> LoInputs;
9045 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9046 [](int M) { return M >= 0 && M < 8; });
9047 std::sort(LoInputs.begin(), LoInputs.end());
9048 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9050 SmallVector<int, 4> HiInputs;
9051 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9052 [](int M) { return M >= 8; });
9053 std::sort(HiInputs.begin(), HiInputs.end());
9054 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9057 bool TargetLo = LoInputs.size() >= HiInputs.size();
9058 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9059 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9061 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9062 SmallDenseMap<int, int, 8> LaneMap;
9063 for (int I : InPlaceInputs) {
9064 PreDupI16Shuffle[I/2] = I/2;
9067 int j = TargetLo ? 0 : 4, je = j + 4;
9068 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9069 // Check if j is already a shuffle of this input. This happens when
9070 // there are two adjacent bytes after we move the low one.
9071 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9072 // If we haven't yet mapped the input, search for a slot into which
9074 while (j < je && PreDupI16Shuffle[j] != -1)
9078 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9081 // Map this input with the i16 shuffle.
9082 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9085 // Update the lane map based on the mapping we ended up with.
9086 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9089 ISD::BITCAST, DL, MVT::v16i8,
9090 DAG.getVectorShuffle(MVT::v8i16, DL,
9091 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9092 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9094 // Unpack the bytes to form the i16s that will be shuffled into place.
9095 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9096 MVT::v16i8, V1, V1);
9098 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9099 for (int i = 0; i < 16; i += 2) {
9101 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9102 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
9105 ISD::BITCAST, DL, MVT::v16i8,
9106 DAG.getVectorShuffle(MVT::v8i16, DL,
9107 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9108 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9110 if (SDValue V = tryToWidenViaDuplication())
9114 // Check whether an interleaving lowering is likely to be more efficient.
9115 // This isn't perfect but it is a strong heuristic that tends to work well on
9116 // the kinds of shuffles that show up in practice.
9118 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9119 if (shouldLowerAsInterleaving(Mask)) {
9120 // FIXME: Figure out whether we should pack these into the low or high
9123 int EMask[16], OMask[16];
9124 for (int i = 0; i < 8; ++i) {
9125 EMask[i] = Mask[2*i];
9126 OMask[i] = Mask[2*i + 1];
9131 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9132 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9134 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9137 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9138 // with PSHUFB. It is important to do this before we attempt to generate any
9139 // blends but after all of the single-input lowerings. If the single input
9140 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9141 // want to preserve that and we can DAG combine any longer sequences into
9142 // a PSHUFB in the end. But once we start blending from multiple inputs,
9143 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9144 // and there are *very* few patterns that would actually be faster than the
9145 // PSHUFB approach because of its ability to zero lanes.
9147 // FIXME: The only exceptions to the above are blends which are exact
9148 // interleavings with direct instructions supporting them. We currently don't
9149 // handle those well here.
9150 if (Subtarget->hasSSSE3()) {
9153 for (int i = 0; i < 16; ++i)
9154 if (Mask[i] == -1) {
9155 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9157 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9159 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9161 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9162 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9163 if (isSingleInputShuffleMask(Mask))
9164 return V1; // Single inputs are easy.
9166 // Otherwise, blend the two.
9167 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9168 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9169 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9172 // There are special ways we can lower some single-element blends.
9173 if (NumV2Elements == 1)
9174 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9175 Mask, Subtarget, DAG))
9178 // Check whether a compaction lowering can be done. This handles shuffles
9179 // which take every Nth element for some even N. See the helper function for
9182 // We special case these as they can be particularly efficiently handled with
9183 // the PACKUSB instruction on x86 and they show up in common patterns of
9184 // rearranging bytes to truncate wide elements.
9185 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9186 // NumEvenDrops is the power of two stride of the elements. Another way of
9187 // thinking about it is that we need to drop the even elements this many
9188 // times to get the original input.
9189 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9191 // First we need to zero all the dropped bytes.
9192 assert(NumEvenDrops <= 3 &&
9193 "No support for dropping even elements more than 3 times.");
9194 // We use the mask type to pick which bytes are preserved based on how many
9195 // elements are dropped.
9196 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9197 SDValue ByteClearMask =
9198 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9199 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9200 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9202 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9204 // Now pack things back together.
9205 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9206 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9207 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9208 for (int i = 1; i < NumEvenDrops; ++i) {
9209 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9210 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9216 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9217 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9218 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9219 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9221 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9222 MutableArrayRef<int> V1HalfBlendMask,
9223 MutableArrayRef<int> V2HalfBlendMask) {
9224 for (int i = 0; i < 8; ++i)
9225 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9226 V1HalfBlendMask[i] = HalfMask[i];
9228 } else if (HalfMask[i] >= 16) {
9229 V2HalfBlendMask[i] = HalfMask[i] - 16;
9230 HalfMask[i] = i + 8;
9233 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9234 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9236 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9238 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9239 MutableArrayRef<int> HiBlendMask) {
9241 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9242 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9244 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9245 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9246 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9247 [](int M) { return M >= 0 && M % 2 == 1; })) {
9248 // Use a mask to drop the high bytes.
9249 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9250 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9251 DAG.getConstant(0x00FF, MVT::v8i16));
9253 // This will be a single vector shuffle instead of a blend so nuke V2.
9254 V2 = DAG.getUNDEF(MVT::v8i16);
9256 // Squash the masks to point directly into V1.
9257 for (int &M : LoBlendMask)
9260 for (int &M : HiBlendMask)
9264 // Otherwise just unpack the low half of V into V1 and the high half into
9265 // V2 so that we can blend them as i16s.
9266 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9267 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9268 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9269 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9272 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9273 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9274 return std::make_pair(BlendedLo, BlendedHi);
9276 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9277 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9278 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9280 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9281 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9283 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9286 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9288 /// This routine breaks down the specific type of 128-bit shuffle and
9289 /// dispatches to the lowering routines accordingly.
9290 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9291 MVT VT, const X86Subtarget *Subtarget,
9292 SelectionDAG &DAG) {
9293 switch (VT.SimpleTy) {
9295 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9297 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9299 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9301 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9303 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9305 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9308 llvm_unreachable("Unimplemented!");
9312 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9315 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9316 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9317 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9318 /// we encode the logic here for specific shuffle lowering routines to bail to
9319 /// when they exhaust the features avaible to more directly handle the shuffle.
9320 static SDValue splitAndLower256BitVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9321 SDValue V2, ArrayRef<int> Mask,
9322 SelectionDAG &DAG) {
9323 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9324 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9325 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9327 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9328 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9330 int NumElements = VT.getVectorNumElements();
9331 int SplitNumElements = NumElements / 2;
9332 MVT ScalarVT = VT.getScalarType();
9333 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9335 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9336 DAG.getIntPtrConstant(0));
9337 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9338 DAG.getIntPtrConstant(SplitNumElements));
9339 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9340 DAG.getIntPtrConstant(0));
9341 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9342 DAG.getIntPtrConstant(SplitNumElements));
9344 // Now create two 4-way blends of these half-width vectors.
9345 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9346 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9347 for (int i = 0; i < SplitNumElements; ++i) {
9348 int M = HalfMask[i];
9349 if (M >= NumElements) {
9350 V2BlendMask.push_back(M - NumElements);
9351 V1BlendMask.push_back(-1);
9352 BlendMask.push_back(SplitNumElements + i);
9353 } else if (M >= 0) {
9354 V2BlendMask.push_back(-1);
9355 V1BlendMask.push_back(M);
9356 BlendMask.push_back(i);
9358 V2BlendMask.push_back(-1);
9359 V1BlendMask.push_back(-1);
9360 BlendMask.push_back(-1);
9363 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9364 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9365 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9367 SDValue Lo = HalfBlend(LoMask);
9368 SDValue Hi = HalfBlend(HiMask);
9369 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9372 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9373 /// a permutation and blend of those lanes.
9375 /// This essentially blends the out-of-lane inputs to each lane into the lane
9376 /// from a permuted copy of the vector. This lowering strategy results in four
9377 /// instructions in the worst case for a single-input cross lane shuffle which
9378 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9379 /// of. Special cases for each particular shuffle pattern should be handled
9380 /// prior to trying this lowering.
9381 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9382 SDValue V1, SDValue V2,
9384 SelectionDAG &DAG) {
9385 // FIXME: This should probably be generalized for 512-bit vectors as well.
9386 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9387 int LaneSize = Mask.size() / 2;
9389 // If there are only inputs from one 128-bit lane, splitting will in fact be
9390 // less expensive. The flags track wether the given lane contains an element
9391 // that crosses to another lane.
9392 bool LaneCrossing[2] = {false, false};
9393 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9394 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9395 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9396 if (!LaneCrossing[0] || !LaneCrossing[1])
9397 return splitAndLower256BitVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9399 if (isSingleInputShuffleMask(Mask)) {
9400 SmallVector<int, 32> FlippedBlendMask;
9401 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9402 FlippedBlendMask.push_back(
9403 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9405 : Mask[i] % LaneSize +
9406 (i / LaneSize) * LaneSize + Size));
9408 // Flip the vector, and blend the results which should now be in-lane. The
9409 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9410 // 5 for the high source. The value 3 selects the high half of source 2 and
9411 // the value 2 selects the low half of source 2. We only use source 2 to
9412 // allow folding it into a memory operand.
9413 unsigned PERMMask = 3 | 2 << 4;
9414 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9415 V1, DAG.getConstant(PERMMask, MVT::i8));
9416 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9419 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9420 // will be handled by the above logic and a blend of the results, much like
9421 // other patterns in AVX.
9422 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9425 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9427 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9428 /// isn't available.
9429 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9430 const X86Subtarget *Subtarget,
9431 SelectionDAG &DAG) {
9433 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9434 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9435 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9436 ArrayRef<int> Mask = SVOp->getMask();
9437 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9439 if (isSingleInputShuffleMask(Mask)) {
9440 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9441 // Non-half-crossing single input shuffles can be lowerid with an
9442 // interleaved permutation.
9443 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9444 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9445 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9446 DAG.getConstant(VPERMILPMask, MVT::i8));
9449 // With AVX2 we have direct support for this permutation.
9450 if (Subtarget->hasAVX2())
9451 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9452 getV4X86ShuffleImm8ForMask(Mask, DAG));
9454 // Otherwise, fall back.
9455 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9459 // X86 has dedicated unpack instructions that can handle specific blend
9460 // operations: UNPCKH and UNPCKL.
9461 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9462 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9463 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9464 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9466 // If we have a single input to the zero element, insert that into V1 if we
9467 // can do so cheaply.
9469 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9470 if (NumV2Elements == 1 && Mask[0] >= 4)
9471 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9472 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9475 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9479 // Check if the blend happens to exactly fit that of SHUFPD.
9480 if ((Mask[0] == -1 || Mask[0] < 2) &&
9481 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9482 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9483 (Mask[3] == -1 || Mask[3] >= 6)) {
9484 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9485 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9486 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9487 DAG.getConstant(SHUFPDMask, MVT::i8));
9489 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9490 (Mask[1] == -1 || Mask[1] < 2) &&
9491 (Mask[2] == -1 || Mask[2] >= 6) &&
9492 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9493 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9494 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9495 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9496 DAG.getConstant(SHUFPDMask, MVT::i8));
9499 // Otherwise fall back on generic blend lowering.
9500 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9504 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9506 /// This routine is only called when we have AVX2 and thus a reasonable
9507 /// instruction set for v4i64 shuffling..
9508 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9509 const X86Subtarget *Subtarget,
9510 SelectionDAG &DAG) {
9512 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9513 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9515 ArrayRef<int> Mask = SVOp->getMask();
9516 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9517 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9519 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9523 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9524 // use lower latency instructions that will operate on both 128-bit lanes.
9525 SmallVector<int, 2> RepeatedMask;
9526 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9527 if (isSingleInputShuffleMask(Mask)) {
9528 int PSHUFDMask[] = {-1, -1, -1, -1};
9529 for (int i = 0; i < 2; ++i)
9530 if (RepeatedMask[i] >= 0) {
9531 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9532 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9535 ISD::BITCAST, DL, MVT::v4i64,
9536 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9537 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9538 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9541 // Use dedicated unpack instructions for masks that match their pattern.
9542 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9544 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9548 // AVX2 provides a direct instruction for permuting a single input across
9550 if (isSingleInputShuffleMask(Mask))
9551 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9552 getV4X86ShuffleImm8ForMask(Mask, DAG));
9554 // Otherwise fall back on generic blend lowering.
9555 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9559 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9561 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9562 /// isn't available.
9563 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9564 const X86Subtarget *Subtarget,
9565 SelectionDAG &DAG) {
9567 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9568 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9569 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9570 ArrayRef<int> Mask = SVOp->getMask();
9571 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9577 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9578 // options to efficiently lower the shuffle.
9579 SmallVector<int, 4> RepeatedMask;
9580 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9581 assert(RepeatedMask.size() == 4 &&
9582 "Repeated masks must be half the mask width!");
9583 if (isSingleInputShuffleMask(Mask))
9584 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9585 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9587 // Use dedicated unpack instructions for masks that match their pattern.
9588 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9589 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9590 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9591 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9593 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9594 // have already handled any direct blends. We also need to squash the
9595 // repeated mask into a simulated v4f32 mask.
9596 for (int i = 0; i < 4; ++i)
9597 if (RepeatedMask[i] >= 8)
9598 RepeatedMask[i] -= 4;
9599 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9602 // If we have a single input shuffle with different shuffle patterns in the
9603 // two 128-bit lanes use the variable mask to VPERMILPS.
9604 if (isSingleInputShuffleMask(Mask)) {
9605 SDValue VPermMask[8];
9606 for (int i = 0; i < 8; ++i)
9607 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9608 : DAG.getConstant(Mask[i], MVT::i32);
9609 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9611 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9612 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9614 if (Subtarget->hasAVX2())
9615 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9616 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9617 DAG.getNode(ISD::BUILD_VECTOR, DL,
9618 MVT::v8i32, VPermMask)),
9621 // Otherwise, fall back.
9622 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9626 // Otherwise fall back on generic blend lowering.
9627 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9631 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9633 /// This routine is only called when we have AVX2 and thus a reasonable
9634 /// instruction set for v8i32 shuffling..
9635 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9636 const X86Subtarget *Subtarget,
9637 SelectionDAG &DAG) {
9639 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9640 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9642 ArrayRef<int> Mask = SVOp->getMask();
9643 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9644 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9646 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9650 // If the shuffle mask is repeated in each 128-bit lane we can use more
9651 // efficient instructions that mirror the shuffles across the two 128-bit
9653 SmallVector<int, 4> RepeatedMask;
9654 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9655 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9656 if (isSingleInputShuffleMask(Mask))
9657 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9658 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9660 // Use dedicated unpack instructions for masks that match their pattern.
9661 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9662 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9663 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9664 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9667 // If the shuffle patterns aren't repeated but it is a single input, directly
9668 // generate a cross-lane VPERMD instruction.
9669 if (isSingleInputShuffleMask(Mask)) {
9670 SDValue VPermMask[8];
9671 for (int i = 0; i < 8; ++i)
9672 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9673 : DAG.getConstant(Mask[i], MVT::i32);
9675 X86ISD::VPERMV, DL, MVT::v8i32,
9676 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9679 // Otherwise fall back on generic blend lowering.
9680 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9684 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9686 /// This routine is only called when we have AVX2 and thus a reasonable
9687 /// instruction set for v16i16 shuffling..
9688 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9689 const X86Subtarget *Subtarget,
9690 SelectionDAG &DAG) {
9692 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9693 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9694 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9695 ArrayRef<int> Mask = SVOp->getMask();
9696 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9697 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9699 // There are no generalized cross-lane shuffle operations available on i16
9701 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9702 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9705 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9709 // Use dedicated unpack instructions for masks that match their pattern.
9710 if (isShuffleEquivalent(Mask,
9711 // First 128-bit lane:
9712 0, 16, 1, 17, 2, 18, 3, 19,
9713 // Second 128-bit lane:
9714 8, 24, 9, 25, 10, 26, 11, 27))
9715 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9716 if (isShuffleEquivalent(Mask,
9717 // First 128-bit lane:
9718 4, 20, 5, 21, 6, 22, 7, 23,
9719 // Second 128-bit lane:
9720 12, 28, 13, 29, 14, 30, 15, 31))
9721 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9723 if (isSingleInputShuffleMask(Mask)) {
9724 SDValue PSHUFBMask[32];
9725 for (int i = 0; i < 16; ++i) {
9726 if (Mask[i] == -1) {
9727 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9731 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9732 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9733 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9734 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9737 ISD::BITCAST, DL, MVT::v16i16,
9739 X86ISD::PSHUFB, DL, MVT::v32i8,
9740 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9741 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9744 // Otherwise fall back on generic blend lowering.
9745 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9749 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9751 /// This routine is only called when we have AVX2 and thus a reasonable
9752 /// instruction set for v32i8 shuffling..
9753 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9754 const X86Subtarget *Subtarget,
9755 SelectionDAG &DAG) {
9757 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9758 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9760 ArrayRef<int> Mask = SVOp->getMask();
9761 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9762 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9764 // There are no generalized cross-lane shuffle operations available on i8
9766 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9767 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9770 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9774 // Use dedicated unpack instructions for masks that match their pattern.
9775 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9777 if (isShuffleEquivalent(
9779 // First 128-bit lane:
9780 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9781 // Second 128-bit lane:
9782 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9783 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9784 if (isShuffleEquivalent(
9786 // First 128-bit lane:
9787 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9788 // Second 128-bit lane:
9789 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9790 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9792 if (isSingleInputShuffleMask(Mask)) {
9793 SDValue PSHUFBMask[32];
9794 for (int i = 0; i < 32; ++i)
9797 ? DAG.getUNDEF(MVT::i8)
9798 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9801 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9802 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9805 // Otherwise fall back on generic blend lowering.
9806 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9810 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9812 /// This routine either breaks down the specific type of a 256-bit x86 vector
9813 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9814 /// together based on the available instructions.
9815 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9816 MVT VT, const X86Subtarget *Subtarget,
9817 SelectionDAG &DAG) {
9819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9820 ArrayRef<int> Mask = SVOp->getMask();
9822 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9823 // check for those subtargets here and avoid much of the subtarget querying in
9824 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9825 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9826 // floating point types there eventually, just immediately cast everything to
9827 // a float and operate entirely in that domain.
9828 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9829 int ElementBits = VT.getScalarSizeInBits();
9830 if (ElementBits < 32)
9831 // No floating point type available, decompose into 128-bit vectors.
9832 return splitAndLower256BitVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9834 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9835 VT.getVectorNumElements());
9836 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9837 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9838 return DAG.getNode(ISD::BITCAST, DL, VT,
9839 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9842 switch (VT.SimpleTy) {
9844 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9846 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9848 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9850 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9852 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9854 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9857 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9861 /// \brief Tiny helper function to test whether a shuffle mask could be
9862 /// simplified by widening the elements being shuffled.
9863 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9864 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9865 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9866 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9867 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9873 /// \brief Top-level lowering for x86 vector shuffles.
9875 /// This handles decomposition, canonicalization, and lowering of all x86
9876 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9877 /// above in helper routines. The canonicalization attempts to widen shuffles
9878 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9879 /// s.t. only one of the two inputs needs to be tested, etc.
9880 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9881 SelectionDAG &DAG) {
9882 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9883 ArrayRef<int> Mask = SVOp->getMask();
9884 SDValue V1 = Op.getOperand(0);
9885 SDValue V2 = Op.getOperand(1);
9886 MVT VT = Op.getSimpleValueType();
9887 int NumElements = VT.getVectorNumElements();
9890 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9892 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9893 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9894 if (V1IsUndef && V2IsUndef)
9895 return DAG.getUNDEF(VT);
9897 // When we create a shuffle node we put the UNDEF node to second operand,
9898 // but in some cases the first operand may be transformed to UNDEF.
9899 // In this case we should just commute the node.
9901 return DAG.getCommutedVectorShuffle(*SVOp);
9903 // Check for non-undef masks pointing at an undef vector and make the masks
9904 // undef as well. This makes it easier to match the shuffle based solely on
9908 if (M >= NumElements) {
9909 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9910 for (int &M : NewMask)
9911 if (M >= NumElements)
9913 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9916 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9917 // lanes but wider integers. We cap this to not form integers larger than i64
9918 // but it might be interesting to form i128 integers to handle flipping the
9919 // low and high halves of AVX 256-bit vectors.
9920 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9921 canWidenShuffleElements(Mask)) {
9922 SmallVector<int, 8> NewMask;
9923 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9924 NewMask.push_back(Mask[i] != -1
9926 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9928 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9929 VT.getVectorNumElements() / 2);
9930 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9931 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9932 return DAG.getNode(ISD::BITCAST, dl, VT,
9933 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9936 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9937 for (int M : SVOp->getMask())
9940 else if (M < NumElements)
9945 // Commute the shuffle as needed such that more elements come from V1 than
9946 // V2. This allows us to match the shuffle pattern strictly on how many
9947 // elements come from V1 without handling the symmetric cases.
9948 if (NumV2Elements > NumV1Elements)
9949 return DAG.getCommutedVectorShuffle(*SVOp);
9951 // When the number of V1 and V2 elements are the same, try to minimize the
9952 // number of uses of V2 in the low half of the vector. When that is tied,
9953 // ensure that the sum of indices for V1 is equal to or lower than the sum
9955 if (NumV1Elements == NumV2Elements) {
9956 int LowV1Elements = 0, LowV2Elements = 0;
9957 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9958 if (M >= NumElements)
9962 if (LowV2Elements > LowV1Elements) {
9963 return DAG.getCommutedVectorShuffle(*SVOp);
9964 } else if (LowV2Elements == LowV1Elements) {
9965 int SumV1Indices = 0, SumV2Indices = 0;
9966 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9967 if (SVOp->getMask()[i] >= NumElements)
9969 else if (SVOp->getMask()[i] >= 0)
9971 if (SumV2Indices < SumV1Indices)
9972 return DAG.getCommutedVectorShuffle(*SVOp);
9976 // For each vector width, delegate to a specialized lowering routine.
9977 if (VT.getSizeInBits() == 128)
9978 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9980 if (VT.getSizeInBits() == 256)
9981 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9983 llvm_unreachable("Unimplemented!");
9987 //===----------------------------------------------------------------------===//
9988 // Legacy vector shuffle lowering
9990 // This code is the legacy code handling vector shuffles until the above
9991 // replaces its functionality and performance.
9992 //===----------------------------------------------------------------------===//
9994 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9995 bool hasInt256, unsigned *MaskOut = nullptr) {
9996 MVT EltVT = VT.getVectorElementType();
9998 // There is no blend with immediate in AVX-512.
9999 if (VT.is512BitVector())
10002 if (!hasSSE41 || EltVT == MVT::i8)
10004 if (!hasInt256 && VT == MVT::v16i16)
10007 unsigned MaskValue = 0;
10008 unsigned NumElems = VT.getVectorNumElements();
10009 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10010 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10011 unsigned NumElemsInLane = NumElems / NumLanes;
10013 // Blend for v16i16 should be symetric for the both lanes.
10014 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10016 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10017 int EltIdx = MaskVals[i];
10019 if ((EltIdx < 0 || EltIdx == (int)i) &&
10020 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10023 if (((unsigned)EltIdx == (i + NumElems)) &&
10024 (SndLaneEltIdx < 0 ||
10025 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10026 MaskValue |= (1 << i);
10032 *MaskOut = MaskValue;
10036 // Try to lower a shuffle node into a simple blend instruction.
10037 // This function assumes isBlendMask returns true for this
10038 // SuffleVectorSDNode
10039 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10040 unsigned MaskValue,
10041 const X86Subtarget *Subtarget,
10042 SelectionDAG &DAG) {
10043 MVT VT = SVOp->getSimpleValueType(0);
10044 MVT EltVT = VT.getVectorElementType();
10045 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10046 Subtarget->hasInt256() && "Trying to lower a "
10047 "VECTOR_SHUFFLE to a Blend but "
10048 "with the wrong mask"));
10049 SDValue V1 = SVOp->getOperand(0);
10050 SDValue V2 = SVOp->getOperand(1);
10052 unsigned NumElems = VT.getVectorNumElements();
10054 // Convert i32 vectors to floating point if it is not AVX2.
10055 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10057 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10058 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10060 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10061 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10064 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10065 DAG.getConstant(MaskValue, MVT::i32));
10066 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10069 /// In vector type \p VT, return true if the element at index \p InputIdx
10070 /// falls on a different 128-bit lane than \p OutputIdx.
10071 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10072 unsigned OutputIdx) {
10073 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10074 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10077 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10078 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10079 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10080 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10082 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10083 SelectionDAG &DAG) {
10084 MVT VT = V1.getSimpleValueType();
10085 assert(VT.is128BitVector() || VT.is256BitVector());
10087 MVT EltVT = VT.getVectorElementType();
10088 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10089 unsigned NumElts = VT.getVectorNumElements();
10091 SmallVector<SDValue, 32> PshufbMask;
10092 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10093 int InputIdx = MaskVals[OutputIdx];
10094 unsigned InputByteIdx;
10096 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10097 InputByteIdx = 0x80;
10099 // Cross lane is not allowed.
10100 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10102 InputByteIdx = InputIdx * EltSizeInBytes;
10103 // Index is an byte offset within the 128-bit lane.
10104 InputByteIdx &= 0xf;
10107 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10108 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10109 if (InputByteIdx != 0x80)
10114 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10116 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10117 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10118 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10121 // v8i16 shuffles - Prefer shuffles in the following order:
10122 // 1. [all] pshuflw, pshufhw, optional move
10123 // 2. [ssse3] 1 x pshufb
10124 // 3. [ssse3] 2 x pshufb + 1 x por
10125 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10127 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10128 SelectionDAG &DAG) {
10129 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10130 SDValue V1 = SVOp->getOperand(0);
10131 SDValue V2 = SVOp->getOperand(1);
10133 SmallVector<int, 8> MaskVals;
10135 // Determine if more than 1 of the words in each of the low and high quadwords
10136 // of the result come from the same quadword of one of the two inputs. Undef
10137 // mask values count as coming from any quadword, for better codegen.
10139 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10140 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10141 unsigned LoQuad[] = { 0, 0, 0, 0 };
10142 unsigned HiQuad[] = { 0, 0, 0, 0 };
10143 // Indices of quads used.
10144 std::bitset<4> InputQuads;
10145 for (unsigned i = 0; i < 8; ++i) {
10146 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10147 int EltIdx = SVOp->getMaskElt(i);
10148 MaskVals.push_back(EltIdx);
10156 ++Quad[EltIdx / 4];
10157 InputQuads.set(EltIdx / 4);
10160 int BestLoQuad = -1;
10161 unsigned MaxQuad = 1;
10162 for (unsigned i = 0; i < 4; ++i) {
10163 if (LoQuad[i] > MaxQuad) {
10165 MaxQuad = LoQuad[i];
10169 int BestHiQuad = -1;
10171 for (unsigned i = 0; i < 4; ++i) {
10172 if (HiQuad[i] > MaxQuad) {
10174 MaxQuad = HiQuad[i];
10178 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10179 // of the two input vectors, shuffle them into one input vector so only a
10180 // single pshufb instruction is necessary. If there are more than 2 input
10181 // quads, disable the next transformation since it does not help SSSE3.
10182 bool V1Used = InputQuads[0] || InputQuads[1];
10183 bool V2Used = InputQuads[2] || InputQuads[3];
10184 if (Subtarget->hasSSSE3()) {
10185 if (InputQuads.count() == 2 && V1Used && V2Used) {
10186 BestLoQuad = InputQuads[0] ? 0 : 1;
10187 BestHiQuad = InputQuads[2] ? 2 : 3;
10189 if (InputQuads.count() > 2) {
10195 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10196 // the shuffle mask. If a quad is scored as -1, that means that it contains
10197 // words from all 4 input quadwords.
10199 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10201 BestLoQuad < 0 ? 0 : BestLoQuad,
10202 BestHiQuad < 0 ? 1 : BestHiQuad
10204 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10205 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10206 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10207 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10209 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10210 // source words for the shuffle, to aid later transformations.
10211 bool AllWordsInNewV = true;
10212 bool InOrder[2] = { true, true };
10213 for (unsigned i = 0; i != 8; ++i) {
10214 int idx = MaskVals[i];
10216 InOrder[i/4] = false;
10217 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10219 AllWordsInNewV = false;
10223 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10224 if (AllWordsInNewV) {
10225 for (int i = 0; i != 8; ++i) {
10226 int idx = MaskVals[i];
10229 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10230 if ((idx != i) && idx < 4)
10232 if ((idx != i) && idx > 3)
10241 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10242 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10243 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10244 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10245 unsigned TargetMask = 0;
10246 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10247 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10248 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10249 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10250 getShufflePSHUFLWImmediate(SVOp);
10251 V1 = NewV.getOperand(0);
10252 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10256 // Promote splats to a larger type which usually leads to more efficient code.
10257 // FIXME: Is this true if pshufb is available?
10258 if (SVOp->isSplat())
10259 return PromoteSplat(SVOp, DAG);
10261 // If we have SSSE3, and all words of the result are from 1 input vector,
10262 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10263 // is present, fall back to case 4.
10264 if (Subtarget->hasSSSE3()) {
10265 SmallVector<SDValue,16> pshufbMask;
10267 // If we have elements from both input vectors, set the high bit of the
10268 // shuffle mask element to zero out elements that come from V2 in the V1
10269 // mask, and elements that come from V1 in the V2 mask, so that the two
10270 // results can be OR'd together.
10271 bool TwoInputs = V1Used && V2Used;
10272 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10274 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10276 // Calculate the shuffle mask for the second input, shuffle it, and
10277 // OR it with the first shuffled input.
10278 CommuteVectorShuffleMask(MaskVals, 8);
10279 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10280 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10281 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10284 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10285 // and update MaskVals with new element order.
10286 std::bitset<8> InOrder;
10287 if (BestLoQuad >= 0) {
10288 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10289 for (int i = 0; i != 4; ++i) {
10290 int idx = MaskVals[i];
10293 } else if ((idx / 4) == BestLoQuad) {
10294 MaskV[i] = idx & 3;
10298 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10301 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10302 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10303 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10304 NewV.getOperand(0),
10305 getShufflePSHUFLWImmediate(SVOp), DAG);
10309 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10310 // and update MaskVals with the new element order.
10311 if (BestHiQuad >= 0) {
10312 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10313 for (unsigned i = 4; i != 8; ++i) {
10314 int idx = MaskVals[i];
10317 } else if ((idx / 4) == BestHiQuad) {
10318 MaskV[i] = (idx & 3) + 4;
10322 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10325 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10327 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10328 NewV.getOperand(0),
10329 getShufflePSHUFHWImmediate(SVOp), DAG);
10333 // In case BestHi & BestLo were both -1, which means each quadword has a word
10334 // from each of the four input quadwords, calculate the InOrder bitvector now
10335 // before falling through to the insert/extract cleanup.
10336 if (BestLoQuad == -1 && BestHiQuad == -1) {
10338 for (int i = 0; i != 8; ++i)
10339 if (MaskVals[i] < 0 || MaskVals[i] == i)
10343 // The other elements are put in the right place using pextrw and pinsrw.
10344 for (unsigned i = 0; i != 8; ++i) {
10347 int EltIdx = MaskVals[i];
10350 SDValue ExtOp = (EltIdx < 8) ?
10351 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10352 DAG.getIntPtrConstant(EltIdx)) :
10353 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10354 DAG.getIntPtrConstant(EltIdx - 8));
10355 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10356 DAG.getIntPtrConstant(i));
10361 /// \brief v16i16 shuffles
10363 /// FIXME: We only support generation of a single pshufb currently. We can
10364 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10365 /// well (e.g 2 x pshufb + 1 x por).
10367 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10369 SDValue V1 = SVOp->getOperand(0);
10370 SDValue V2 = SVOp->getOperand(1);
10373 if (V2.getOpcode() != ISD::UNDEF)
10376 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10377 return getPSHUFB(MaskVals, V1, dl, DAG);
10380 // v16i8 shuffles - Prefer shuffles in the following order:
10381 // 1. [ssse3] 1 x pshufb
10382 // 2. [ssse3] 2 x pshufb + 1 x por
10383 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10384 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10385 const X86Subtarget* Subtarget,
10386 SelectionDAG &DAG) {
10387 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10388 SDValue V1 = SVOp->getOperand(0);
10389 SDValue V2 = SVOp->getOperand(1);
10391 ArrayRef<int> MaskVals = SVOp->getMask();
10393 // Promote splats to a larger type which usually leads to more efficient code.
10394 // FIXME: Is this true if pshufb is available?
10395 if (SVOp->isSplat())
10396 return PromoteSplat(SVOp, DAG);
10398 // If we have SSSE3, case 1 is generated when all result bytes come from
10399 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10400 // present, fall back to case 3.
10402 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10403 if (Subtarget->hasSSSE3()) {
10404 SmallVector<SDValue,16> pshufbMask;
10406 // If all result elements are from one input vector, then only translate
10407 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10409 // Otherwise, we have elements from both input vectors, and must zero out
10410 // elements that come from V2 in the first mask, and V1 in the second mask
10411 // so that we can OR them together.
10412 for (unsigned i = 0; i != 16; ++i) {
10413 int EltIdx = MaskVals[i];
10414 if (EltIdx < 0 || EltIdx >= 16)
10416 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10418 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10419 DAG.getNode(ISD::BUILD_VECTOR, dl,
10420 MVT::v16i8, pshufbMask));
10422 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10423 // the 2nd operand if it's undefined or zero.
10424 if (V2.getOpcode() == ISD::UNDEF ||
10425 ISD::isBuildVectorAllZeros(V2.getNode()))
10428 // Calculate the shuffle mask for the second input, shuffle it, and
10429 // OR it with the first shuffled input.
10430 pshufbMask.clear();
10431 for (unsigned i = 0; i != 16; ++i) {
10432 int EltIdx = MaskVals[i];
10433 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10434 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10436 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10437 DAG.getNode(ISD::BUILD_VECTOR, dl,
10438 MVT::v16i8, pshufbMask));
10439 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10442 // No SSSE3 - Calculate in place words and then fix all out of place words
10443 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10444 // the 16 different words that comprise the two doublequadword input vectors.
10445 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10446 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10448 for (int i = 0; i != 8; ++i) {
10449 int Elt0 = MaskVals[i*2];
10450 int Elt1 = MaskVals[i*2+1];
10452 // This word of the result is all undef, skip it.
10453 if (Elt0 < 0 && Elt1 < 0)
10456 // This word of the result is already in the correct place, skip it.
10457 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10460 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10461 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10464 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10465 // using a single extract together, load it and store it.
10466 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10467 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10468 DAG.getIntPtrConstant(Elt1 / 2));
10469 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10470 DAG.getIntPtrConstant(i));
10474 // If Elt1 is defined, extract it from the appropriate source. If the
10475 // source byte is not also odd, shift the extracted word left 8 bits
10476 // otherwise clear the bottom 8 bits if we need to do an or.
10478 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10479 DAG.getIntPtrConstant(Elt1 / 2));
10480 if ((Elt1 & 1) == 0)
10481 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10483 TLI.getShiftAmountTy(InsElt.getValueType())));
10484 else if (Elt0 >= 0)
10485 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10486 DAG.getConstant(0xFF00, MVT::i16));
10488 // If Elt0 is defined, extract it from the appropriate source. If the
10489 // source byte is not also even, shift the extracted word right 8 bits. If
10490 // Elt1 was also defined, OR the extracted values together before
10491 // inserting them in the result.
10493 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10494 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10495 if ((Elt0 & 1) != 0)
10496 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10498 TLI.getShiftAmountTy(InsElt0.getValueType())));
10499 else if (Elt1 >= 0)
10500 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10501 DAG.getConstant(0x00FF, MVT::i16));
10502 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10505 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10506 DAG.getIntPtrConstant(i));
10508 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10511 // v32i8 shuffles - Translate to VPSHUFB if possible.
10513 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10514 const X86Subtarget *Subtarget,
10515 SelectionDAG &DAG) {
10516 MVT VT = SVOp->getSimpleValueType(0);
10517 SDValue V1 = SVOp->getOperand(0);
10518 SDValue V2 = SVOp->getOperand(1);
10520 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10522 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10523 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10524 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10526 // VPSHUFB may be generated if
10527 // (1) one of input vector is undefined or zeroinitializer.
10528 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10529 // And (2) the mask indexes don't cross the 128-bit lane.
10530 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10531 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10534 if (V1IsAllZero && !V2IsAllZero) {
10535 CommuteVectorShuffleMask(MaskVals, 32);
10538 return getPSHUFB(MaskVals, V1, dl, DAG);
10541 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10542 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10543 /// done when every pair / quad of shuffle mask elements point to elements in
10544 /// the right sequence. e.g.
10545 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10547 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10548 SelectionDAG &DAG) {
10549 MVT VT = SVOp->getSimpleValueType(0);
10551 unsigned NumElems = VT.getVectorNumElements();
10554 switch (VT.SimpleTy) {
10555 default: llvm_unreachable("Unexpected!");
10558 return SDValue(SVOp, 0);
10559 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10560 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10561 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10562 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10563 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10564 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10567 SmallVector<int, 8> MaskVec;
10568 for (unsigned i = 0; i != NumElems; i += Scale) {
10570 for (unsigned j = 0; j != Scale; ++j) {
10571 int EltIdx = SVOp->getMaskElt(i+j);
10575 StartIdx = (EltIdx / Scale);
10576 if (EltIdx != (int)(StartIdx*Scale + j))
10579 MaskVec.push_back(StartIdx);
10582 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10583 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10584 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10587 /// getVZextMovL - Return a zero-extending vector move low node.
10589 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10590 SDValue SrcOp, SelectionDAG &DAG,
10591 const X86Subtarget *Subtarget, SDLoc dl) {
10592 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10593 LoadSDNode *LD = nullptr;
10594 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10595 LD = dyn_cast<LoadSDNode>(SrcOp);
10597 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10599 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10600 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10601 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10602 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10603 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10605 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10606 return DAG.getNode(ISD::BITCAST, dl, VT,
10607 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10608 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10610 SrcOp.getOperand(0)
10616 return DAG.getNode(ISD::BITCAST, dl, VT,
10617 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10618 DAG.getNode(ISD::BITCAST, dl,
10622 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10623 /// which could not be matched by any known target speficic shuffle
10625 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10627 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10628 if (NewOp.getNode())
10631 MVT VT = SVOp->getSimpleValueType(0);
10633 unsigned NumElems = VT.getVectorNumElements();
10634 unsigned NumLaneElems = NumElems / 2;
10637 MVT EltVT = VT.getVectorElementType();
10638 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10641 SmallVector<int, 16> Mask;
10642 for (unsigned l = 0; l < 2; ++l) {
10643 // Build a shuffle mask for the output, discovering on the fly which
10644 // input vectors to use as shuffle operands (recorded in InputUsed).
10645 // If building a suitable shuffle vector proves too hard, then bail
10646 // out with UseBuildVector set.
10647 bool UseBuildVector = false;
10648 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10649 unsigned LaneStart = l * NumLaneElems;
10650 for (unsigned i = 0; i != NumLaneElems; ++i) {
10651 // The mask element. This indexes into the input.
10652 int Idx = SVOp->getMaskElt(i+LaneStart);
10654 // the mask element does not index into any input vector.
10655 Mask.push_back(-1);
10659 // The input vector this mask element indexes into.
10660 int Input = Idx / NumLaneElems;
10662 // Turn the index into an offset from the start of the input vector.
10663 Idx -= Input * NumLaneElems;
10665 // Find or create a shuffle vector operand to hold this input.
10667 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10668 if (InputUsed[OpNo] == Input)
10669 // This input vector is already an operand.
10671 if (InputUsed[OpNo] < 0) {
10672 // Create a new operand for this input vector.
10673 InputUsed[OpNo] = Input;
10678 if (OpNo >= array_lengthof(InputUsed)) {
10679 // More than two input vectors used! Give up on trying to create a
10680 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10681 UseBuildVector = true;
10685 // Add the mask index for the new shuffle vector.
10686 Mask.push_back(Idx + OpNo * NumLaneElems);
10689 if (UseBuildVector) {
10690 SmallVector<SDValue, 16> SVOps;
10691 for (unsigned i = 0; i != NumLaneElems; ++i) {
10692 // The mask element. This indexes into the input.
10693 int Idx = SVOp->getMaskElt(i+LaneStart);
10695 SVOps.push_back(DAG.getUNDEF(EltVT));
10699 // The input vector this mask element indexes into.
10700 int Input = Idx / NumElems;
10702 // Turn the index into an offset from the start of the input vector.
10703 Idx -= Input * NumElems;
10705 // Extract the vector element by hand.
10706 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10707 SVOp->getOperand(Input),
10708 DAG.getIntPtrConstant(Idx)));
10711 // Construct the output using a BUILD_VECTOR.
10712 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10713 } else if (InputUsed[0] < 0) {
10714 // No input vectors were used! The result is undefined.
10715 Output[l] = DAG.getUNDEF(NVT);
10717 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10718 (InputUsed[0] % 2) * NumLaneElems,
10720 // If only one input was used, use an undefined vector for the other.
10721 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10722 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10723 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10724 // At least one input vector was used. Create a new shuffle vector.
10725 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10731 // Concatenate the result back
10732 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10735 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10736 /// 4 elements, and match them with several different shuffle types.
10738 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10739 SDValue V1 = SVOp->getOperand(0);
10740 SDValue V2 = SVOp->getOperand(1);
10742 MVT VT = SVOp->getSimpleValueType(0);
10744 assert(VT.is128BitVector() && "Unsupported vector size");
10746 std::pair<int, int> Locs[4];
10747 int Mask1[] = { -1, -1, -1, -1 };
10748 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10750 unsigned NumHi = 0;
10751 unsigned NumLo = 0;
10752 for (unsigned i = 0; i != 4; ++i) {
10753 int Idx = PermMask[i];
10755 Locs[i] = std::make_pair(-1, -1);
10757 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10759 Locs[i] = std::make_pair(0, NumLo);
10760 Mask1[NumLo] = Idx;
10763 Locs[i] = std::make_pair(1, NumHi);
10765 Mask1[2+NumHi] = Idx;
10771 if (NumLo <= 2 && NumHi <= 2) {
10772 // If no more than two elements come from either vector. This can be
10773 // implemented with two shuffles. First shuffle gather the elements.
10774 // The second shuffle, which takes the first shuffle as both of its
10775 // vector operands, put the elements into the right order.
10776 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10778 int Mask2[] = { -1, -1, -1, -1 };
10780 for (unsigned i = 0; i != 4; ++i)
10781 if (Locs[i].first != -1) {
10782 unsigned Idx = (i < 2) ? 0 : 4;
10783 Idx += Locs[i].first * 2 + Locs[i].second;
10787 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10790 if (NumLo == 3 || NumHi == 3) {
10791 // Otherwise, we must have three elements from one vector, call it X, and
10792 // one element from the other, call it Y. First, use a shufps to build an
10793 // intermediate vector with the one element from Y and the element from X
10794 // that will be in the same half in the final destination (the indexes don't
10795 // matter). Then, use a shufps to build the final vector, taking the half
10796 // containing the element from Y from the intermediate, and the other half
10799 // Normalize it so the 3 elements come from V1.
10800 CommuteVectorShuffleMask(PermMask, 4);
10804 // Find the element from V2.
10806 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10807 int Val = PermMask[HiIndex];
10814 Mask1[0] = PermMask[HiIndex];
10816 Mask1[2] = PermMask[HiIndex^1];
10818 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10820 if (HiIndex >= 2) {
10821 Mask1[0] = PermMask[0];
10822 Mask1[1] = PermMask[1];
10823 Mask1[2] = HiIndex & 1 ? 6 : 4;
10824 Mask1[3] = HiIndex & 1 ? 4 : 6;
10825 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10828 Mask1[0] = HiIndex & 1 ? 2 : 0;
10829 Mask1[1] = HiIndex & 1 ? 0 : 2;
10830 Mask1[2] = PermMask[2];
10831 Mask1[3] = PermMask[3];
10836 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10839 // Break it into (shuffle shuffle_hi, shuffle_lo).
10840 int LoMask[] = { -1, -1, -1, -1 };
10841 int HiMask[] = { -1, -1, -1, -1 };
10843 int *MaskPtr = LoMask;
10844 unsigned MaskIdx = 0;
10845 unsigned LoIdx = 0;
10846 unsigned HiIdx = 2;
10847 for (unsigned i = 0; i != 4; ++i) {
10854 int Idx = PermMask[i];
10856 Locs[i] = std::make_pair(-1, -1);
10857 } else if (Idx < 4) {
10858 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10859 MaskPtr[LoIdx] = Idx;
10862 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10863 MaskPtr[HiIdx] = Idx;
10868 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10869 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10870 int MaskOps[] = { -1, -1, -1, -1 };
10871 for (unsigned i = 0; i != 4; ++i)
10872 if (Locs[i].first != -1)
10873 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10874 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10877 static bool MayFoldVectorLoad(SDValue V) {
10878 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10879 V = V.getOperand(0);
10881 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10882 V = V.getOperand(0);
10883 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10884 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10885 // BUILD_VECTOR (load), undef
10886 V = V.getOperand(0);
10888 return MayFoldLoad(V);
10892 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10893 MVT VT = Op.getSimpleValueType();
10895 // Canonizalize to v2f64.
10896 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10897 return DAG.getNode(ISD::BITCAST, dl, VT,
10898 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10903 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10905 SDValue V1 = Op.getOperand(0);
10906 SDValue V2 = Op.getOperand(1);
10907 MVT VT = Op.getSimpleValueType();
10909 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10911 if (HasSSE2 && VT == MVT::v2f64)
10912 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10914 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10915 return DAG.getNode(ISD::BITCAST, dl, VT,
10916 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10917 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10918 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10922 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10923 SDValue V1 = Op.getOperand(0);
10924 SDValue V2 = Op.getOperand(1);
10925 MVT VT = Op.getSimpleValueType();
10927 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10928 "unsupported shuffle type");
10930 if (V2.getOpcode() == ISD::UNDEF)
10934 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10938 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10939 SDValue V1 = Op.getOperand(0);
10940 SDValue V2 = Op.getOperand(1);
10941 MVT VT = Op.getSimpleValueType();
10942 unsigned NumElems = VT.getVectorNumElements();
10944 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10945 // operand of these instructions is only memory, so check if there's a
10946 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10948 bool CanFoldLoad = false;
10950 // Trivial case, when V2 comes from a load.
10951 if (MayFoldVectorLoad(V2))
10952 CanFoldLoad = true;
10954 // When V1 is a load, it can be folded later into a store in isel, example:
10955 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10957 // (MOVLPSmr addr:$src1, VR128:$src2)
10958 // So, recognize this potential and also use MOVLPS or MOVLPD
10959 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10960 CanFoldLoad = true;
10962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10964 if (HasSSE2 && NumElems == 2)
10965 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10968 // If we don't care about the second element, proceed to use movss.
10969 if (SVOp->getMaskElt(1) != -1)
10970 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10973 // movl and movlp will both match v2i64, but v2i64 is never matched by
10974 // movl earlier because we make it strict to avoid messing with the movlp load
10975 // folding logic (see the code above getMOVLP call). Match it here then,
10976 // this is horrible, but will stay like this until we move all shuffle
10977 // matching to x86 specific nodes. Note that for the 1st condition all
10978 // types are matched with movsd.
10980 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10981 // as to remove this logic from here, as much as possible
10982 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10983 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10984 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10987 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10989 // Invert the operand order and use SHUFPS to match it.
10990 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10991 getShuffleSHUFImmediate(SVOp), DAG);
10994 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10995 SelectionDAG &DAG) {
10997 MVT VT = Load->getSimpleValueType(0);
10998 MVT EVT = VT.getVectorElementType();
10999 SDValue Addr = Load->getOperand(1);
11000 SDValue NewAddr = DAG.getNode(
11001 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11002 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11005 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11006 DAG.getMachineFunction().getMachineMemOperand(
11007 Load->getMemOperand(), 0, EVT.getStoreSize()));
11011 // It is only safe to call this function if isINSERTPSMask is true for
11012 // this shufflevector mask.
11013 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11014 SelectionDAG &DAG) {
11015 // Generate an insertps instruction when inserting an f32 from memory onto a
11016 // v4f32 or when copying a member from one v4f32 to another.
11017 // We also use it for transferring i32 from one register to another,
11018 // since it simply copies the same bits.
11019 // If we're transferring an i32 from memory to a specific element in a
11020 // register, we output a generic DAG that will match the PINSRD
11022 MVT VT = SVOp->getSimpleValueType(0);
11023 MVT EVT = VT.getVectorElementType();
11024 SDValue V1 = SVOp->getOperand(0);
11025 SDValue V2 = SVOp->getOperand(1);
11026 auto Mask = SVOp->getMask();
11027 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11028 "unsupported vector type for insertps/pinsrd");
11030 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11031 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11032 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11036 unsigned DestIndex;
11040 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11043 // If we have 1 element from each vector, we have to check if we're
11044 // changing V1's element's place. If so, we're done. Otherwise, we
11045 // should assume we're changing V2's element's place and behave
11047 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11048 assert(DestIndex <= INT32_MAX && "truncated destination index");
11049 if (FromV1 == FromV2 &&
11050 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11054 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11057 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11058 "More than one element from V1 and from V2, or no elements from one "
11059 "of the vectors. This case should not have returned true from "
11064 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11067 // Get an index into the source vector in the range [0,4) (the mask is
11068 // in the range [0,8) because it can address V1 and V2)
11069 unsigned SrcIndex = Mask[DestIndex] % 4;
11070 if (MayFoldLoad(From)) {
11071 // Trivial case, when From comes from a load and is only used by the
11072 // shuffle. Make it use insertps from the vector that we need from that
11075 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11076 if (!NewLoad.getNode())
11079 if (EVT == MVT::f32) {
11080 // Create this as a scalar to vector to match the instruction pattern.
11081 SDValue LoadScalarToVector =
11082 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11083 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11084 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11086 } else { // EVT == MVT::i32
11087 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11088 // instruction, to match the PINSRD instruction, which loads an i32 to a
11089 // certain vector element.
11090 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11091 DAG.getConstant(DestIndex, MVT::i32));
11095 // Vector-element-to-vector
11096 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11097 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11100 // Reduce a vector shuffle to zext.
11101 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11102 SelectionDAG &DAG) {
11103 // PMOVZX is only available from SSE41.
11104 if (!Subtarget->hasSSE41())
11107 MVT VT = Op.getSimpleValueType();
11109 // Only AVX2 support 256-bit vector integer extending.
11110 if (!Subtarget->hasInt256() && VT.is256BitVector())
11113 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11115 SDValue V1 = Op.getOperand(0);
11116 SDValue V2 = Op.getOperand(1);
11117 unsigned NumElems = VT.getVectorNumElements();
11119 // Extending is an unary operation and the element type of the source vector
11120 // won't be equal to or larger than i64.
11121 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11122 VT.getVectorElementType() == MVT::i64)
11125 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11126 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11127 while ((1U << Shift) < NumElems) {
11128 if (SVOp->getMaskElt(1U << Shift) == 1)
11131 // The maximal ratio is 8, i.e. from i8 to i64.
11136 // Check the shuffle mask.
11137 unsigned Mask = (1U << Shift) - 1;
11138 for (unsigned i = 0; i != NumElems; ++i) {
11139 int EltIdx = SVOp->getMaskElt(i);
11140 if ((i & Mask) != 0 && EltIdx != -1)
11142 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11146 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11147 MVT NeVT = MVT::getIntegerVT(NBits);
11148 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11150 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11153 // Simplify the operand as it's prepared to be fed into shuffle.
11154 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11155 if (V1.getOpcode() == ISD::BITCAST &&
11156 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11157 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11158 V1.getOperand(0).getOperand(0)
11159 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11160 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11161 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11162 ConstantSDNode *CIdx =
11163 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11164 // If it's foldable, i.e. normal load with single use, we will let code
11165 // selection to fold it. Otherwise, we will short the conversion sequence.
11166 if (CIdx && CIdx->getZExtValue() == 0 &&
11167 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11168 MVT FullVT = V.getSimpleValueType();
11169 MVT V1VT = V1.getSimpleValueType();
11170 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11171 // The "ext_vec_elt" node is wider than the result node.
11172 // In this case we should extract subvector from V.
11173 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11174 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11175 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11176 FullVT.getVectorNumElements()/Ratio);
11177 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11178 DAG.getIntPtrConstant(0));
11180 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11184 return DAG.getNode(ISD::BITCAST, DL, VT,
11185 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11188 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11189 SelectionDAG &DAG) {
11190 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11191 MVT VT = Op.getSimpleValueType();
11193 SDValue V1 = Op.getOperand(0);
11194 SDValue V2 = Op.getOperand(1);
11196 if (isZeroShuffle(SVOp))
11197 return getZeroVector(VT, Subtarget, DAG, dl);
11199 // Handle splat operations
11200 if (SVOp->isSplat()) {
11201 // Use vbroadcast whenever the splat comes from a foldable load
11202 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11203 if (Broadcast.getNode())
11207 // Check integer expanding shuffles.
11208 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11209 if (NewOp.getNode())
11212 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11214 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11215 VT == MVT::v32i8) {
11216 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11217 if (NewOp.getNode())
11218 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11219 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11220 // FIXME: Figure out a cleaner way to do this.
11221 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11222 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11223 if (NewOp.getNode()) {
11224 MVT NewVT = NewOp.getSimpleValueType();
11225 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11226 NewVT, true, false))
11227 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11230 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11231 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11232 if (NewOp.getNode()) {
11233 MVT NewVT = NewOp.getSimpleValueType();
11234 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11235 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11244 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11245 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11246 SDValue V1 = Op.getOperand(0);
11247 SDValue V2 = Op.getOperand(1);
11248 MVT VT = Op.getSimpleValueType();
11250 unsigned NumElems = VT.getVectorNumElements();
11251 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11252 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11253 bool V1IsSplat = false;
11254 bool V2IsSplat = false;
11255 bool HasSSE2 = Subtarget->hasSSE2();
11256 bool HasFp256 = Subtarget->hasFp256();
11257 bool HasInt256 = Subtarget->hasInt256();
11258 MachineFunction &MF = DAG.getMachineFunction();
11259 bool OptForSize = MF.getFunction()->getAttributes().
11260 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11262 // Check if we should use the experimental vector shuffle lowering. If so,
11263 // delegate completely to that code path.
11264 if (ExperimentalVectorShuffleLowering)
11265 return lowerVectorShuffle(Op, Subtarget, DAG);
11267 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11269 if (V1IsUndef && V2IsUndef)
11270 return DAG.getUNDEF(VT);
11272 // When we create a shuffle node we put the UNDEF node to second operand,
11273 // but in some cases the first operand may be transformed to UNDEF.
11274 // In this case we should just commute the node.
11276 return DAG.getCommutedVectorShuffle(*SVOp);
11278 // Vector shuffle lowering takes 3 steps:
11280 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11281 // narrowing and commutation of operands should be handled.
11282 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11284 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11285 // so the shuffle can be broken into other shuffles and the legalizer can
11286 // try the lowering again.
11288 // The general idea is that no vector_shuffle operation should be left to
11289 // be matched during isel, all of them must be converted to a target specific
11292 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11293 // narrowing and commutation of operands should be handled. The actual code
11294 // doesn't include all of those, work in progress...
11295 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11296 if (NewOp.getNode())
11299 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11301 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11302 // unpckh_undef). Only use pshufd if speed is more important than size.
11303 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11304 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11305 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11306 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11308 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11309 V2IsUndef && MayFoldVectorLoad(V1))
11310 return getMOVDDup(Op, dl, V1, DAG);
11312 if (isMOVHLPS_v_undef_Mask(M, VT))
11313 return getMOVHighToLow(Op, dl, DAG);
11315 // Use to match splats
11316 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11317 (VT == MVT::v2f64 || VT == MVT::v2i64))
11318 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11320 if (isPSHUFDMask(M, VT)) {
11321 // The actual implementation will match the mask in the if above and then
11322 // during isel it can match several different instructions, not only pshufd
11323 // as its name says, sad but true, emulate the behavior for now...
11324 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11325 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11327 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11329 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11330 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11332 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11333 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11336 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11340 if (isPALIGNRMask(M, VT, Subtarget))
11341 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11342 getShufflePALIGNRImmediate(SVOp),
11345 if (isVALIGNMask(M, VT, Subtarget))
11346 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11347 getShuffleVALIGNImmediate(SVOp),
11350 // Check if this can be converted into a logical shift.
11351 bool isLeft = false;
11352 unsigned ShAmt = 0;
11354 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11355 if (isShift && ShVal.hasOneUse()) {
11356 // If the shifted value has multiple uses, it may be cheaper to use
11357 // v_set0 + movlhps or movhlps, etc.
11358 MVT EltVT = VT.getVectorElementType();
11359 ShAmt *= EltVT.getSizeInBits();
11360 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11363 if (isMOVLMask(M, VT)) {
11364 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11365 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11366 if (!isMOVLPMask(M, VT)) {
11367 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11368 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11370 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11371 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11375 // FIXME: fold these into legal mask.
11376 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11377 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11379 if (isMOVHLPSMask(M, VT))
11380 return getMOVHighToLow(Op, dl, DAG);
11382 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11383 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11385 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11386 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11388 if (isMOVLPMask(M, VT))
11389 return getMOVLP(Op, dl, DAG, HasSSE2);
11391 if (ShouldXformToMOVHLPS(M, VT) ||
11392 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11393 return DAG.getCommutedVectorShuffle(*SVOp);
11396 // No better options. Use a vshldq / vsrldq.
11397 MVT EltVT = VT.getVectorElementType();
11398 ShAmt *= EltVT.getSizeInBits();
11399 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11402 bool Commuted = false;
11403 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11404 // 1,1,1,1 -> v8i16 though.
11405 BitVector UndefElements;
11406 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11407 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11409 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11410 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11413 // Canonicalize the splat or undef, if present, to be on the RHS.
11414 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11415 CommuteVectorShuffleMask(M, NumElems);
11417 std::swap(V1IsSplat, V2IsSplat);
11421 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11422 // Shuffling low element of v1 into undef, just return v1.
11425 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11426 // the instruction selector will not match, so get a canonical MOVL with
11427 // swapped operands to undo the commute.
11428 return getMOVL(DAG, dl, VT, V2, V1);
11431 if (isUNPCKLMask(M, VT, HasInt256))
11432 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11434 if (isUNPCKHMask(M, VT, HasInt256))
11435 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11438 // Normalize mask so all entries that point to V2 points to its first
11439 // element then try to match unpck{h|l} again. If match, return a
11440 // new vector_shuffle with the corrected mask.p
11441 SmallVector<int, 8> NewMask(M.begin(), M.end());
11442 NormalizeMask(NewMask, NumElems);
11443 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11444 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11445 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11446 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11450 // Commute is back and try unpck* again.
11451 // FIXME: this seems wrong.
11452 CommuteVectorShuffleMask(M, NumElems);
11454 std::swap(V1IsSplat, V2IsSplat);
11456 if (isUNPCKLMask(M, VT, HasInt256))
11457 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11459 if (isUNPCKHMask(M, VT, HasInt256))
11460 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11463 // Normalize the node to match x86 shuffle ops if needed
11464 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11465 return DAG.getCommutedVectorShuffle(*SVOp);
11467 // The checks below are all present in isShuffleMaskLegal, but they are
11468 // inlined here right now to enable us to directly emit target specific
11469 // nodes, and remove one by one until they don't return Op anymore.
11471 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11472 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11473 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11474 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11477 if (isPSHUFHWMask(M, VT, HasInt256))
11478 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11479 getShufflePSHUFHWImmediate(SVOp),
11482 if (isPSHUFLWMask(M, VT, HasInt256))
11483 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11484 getShufflePSHUFLWImmediate(SVOp),
11487 unsigned MaskValue;
11488 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11490 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11492 if (isSHUFPMask(M, VT))
11493 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11494 getShuffleSHUFImmediate(SVOp), DAG);
11496 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11497 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11498 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11499 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11501 //===--------------------------------------------------------------------===//
11502 // Generate target specific nodes for 128 or 256-bit shuffles only
11503 // supported in the AVX instruction set.
11506 // Handle VMOVDDUPY permutations
11507 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11508 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11510 // Handle VPERMILPS/D* permutations
11511 if (isVPERMILPMask(M, VT)) {
11512 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11513 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11514 getShuffleSHUFImmediate(SVOp), DAG);
11515 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11516 getShuffleSHUFImmediate(SVOp), DAG);
11520 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11521 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11522 Idx*(NumElems/2), DAG, dl);
11524 // Handle VPERM2F128/VPERM2I128 permutations
11525 if (isVPERM2X128Mask(M, VT, HasFp256))
11526 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11527 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11529 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11530 return getINSERTPS(SVOp, dl, DAG);
11533 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11534 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11536 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11537 VT.is512BitVector()) {
11538 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11539 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11540 SmallVector<SDValue, 16> permclMask;
11541 for (unsigned i = 0; i != NumElems; ++i) {
11542 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11545 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11547 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11548 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11549 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11550 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11551 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11554 //===--------------------------------------------------------------------===//
11555 // Since no target specific shuffle was selected for this generic one,
11556 // lower it into other known shuffles. FIXME: this isn't true yet, but
11557 // this is the plan.
11560 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11561 if (VT == MVT::v8i16) {
11562 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11563 if (NewOp.getNode())
11567 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11568 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11569 if (NewOp.getNode())
11573 if (VT == MVT::v16i8) {
11574 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11575 if (NewOp.getNode())
11579 if (VT == MVT::v32i8) {
11580 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11581 if (NewOp.getNode())
11585 // Handle all 128-bit wide vectors with 4 elements, and match them with
11586 // several different shuffle types.
11587 if (NumElems == 4 && VT.is128BitVector())
11588 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11590 // Handle general 256-bit shuffles
11591 if (VT.is256BitVector())
11592 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11597 // This function assumes its argument is a BUILD_VECTOR of constants or
11598 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11600 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11601 unsigned &MaskValue) {
11603 unsigned NumElems = BuildVector->getNumOperands();
11604 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11605 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11606 unsigned NumElemsInLane = NumElems / NumLanes;
11608 // Blend for v16i16 should be symetric for the both lanes.
11609 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11610 SDValue EltCond = BuildVector->getOperand(i);
11611 SDValue SndLaneEltCond =
11612 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11614 int Lane1Cond = -1, Lane2Cond = -1;
11615 if (isa<ConstantSDNode>(EltCond))
11616 Lane1Cond = !isZero(EltCond);
11617 if (isa<ConstantSDNode>(SndLaneEltCond))
11618 Lane2Cond = !isZero(SndLaneEltCond);
11620 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11621 // Lane1Cond != 0, means we want the first argument.
11622 // Lane1Cond == 0, means we want the second argument.
11623 // The encoding of this argument is 0 for the first argument, 1
11624 // for the second. Therefore, invert the condition.
11625 MaskValue |= !Lane1Cond << i;
11626 else if (Lane1Cond < 0)
11627 MaskValue |= !Lane2Cond << i;
11634 // Try to lower a vselect node into a simple blend instruction.
11635 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11636 SelectionDAG &DAG) {
11637 SDValue Cond = Op.getOperand(0);
11638 SDValue LHS = Op.getOperand(1);
11639 SDValue RHS = Op.getOperand(2);
11641 MVT VT = Op.getSimpleValueType();
11642 MVT EltVT = VT.getVectorElementType();
11643 unsigned NumElems = VT.getVectorNumElements();
11645 // There is no blend with immediate in AVX-512.
11646 if (VT.is512BitVector())
11649 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11651 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11654 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11657 // Check the mask for BLEND and build the value.
11658 unsigned MaskValue = 0;
11659 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11662 // Convert i32 vectors to floating point if it is not AVX2.
11663 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11665 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11666 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11668 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11669 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11672 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11673 DAG.getConstant(MaskValue, MVT::i32));
11674 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11677 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11678 // A vselect where all conditions and data are constants can be optimized into
11679 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11680 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11681 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11682 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11685 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11686 if (BlendOp.getNode())
11689 // Some types for vselect were previously set to Expand, not Legal or
11690 // Custom. Return an empty SDValue so we fall-through to Expand, after
11691 // the Custom lowering phase.
11692 MVT VT = Op.getSimpleValueType();
11693 switch (VT.SimpleTy) {
11698 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11703 // We couldn't create a "Blend with immediate" node.
11704 // This node should still be legal, but we'll have to emit a blendv*
11709 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11710 MVT VT = Op.getSimpleValueType();
11713 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11716 if (VT.getSizeInBits() == 8) {
11717 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11718 Op.getOperand(0), Op.getOperand(1));
11719 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11720 DAG.getValueType(VT));
11721 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11724 if (VT.getSizeInBits() == 16) {
11725 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11726 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11729 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11730 DAG.getNode(ISD::BITCAST, dl,
11733 Op.getOperand(1)));
11734 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11735 Op.getOperand(0), Op.getOperand(1));
11736 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11737 DAG.getValueType(VT));
11738 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11741 if (VT == MVT::f32) {
11742 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11743 // the result back to FR32 register. It's only worth matching if the
11744 // result has a single use which is a store or a bitcast to i32. And in
11745 // the case of a store, it's not worth it if the index is a constant 0,
11746 // because a MOVSSmr can be used instead, which is smaller and faster.
11747 if (!Op.hasOneUse())
11749 SDNode *User = *Op.getNode()->use_begin();
11750 if ((User->getOpcode() != ISD::STORE ||
11751 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11752 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11753 (User->getOpcode() != ISD::BITCAST ||
11754 User->getValueType(0) != MVT::i32))
11756 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11757 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11760 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11763 if (VT == MVT::i32 || VT == MVT::i64) {
11764 // ExtractPS/pextrq works with constant index.
11765 if (isa<ConstantSDNode>(Op.getOperand(1)))
11771 /// Extract one bit from mask vector, like v16i1 or v8i1.
11772 /// AVX-512 feature.
11774 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11775 SDValue Vec = Op.getOperand(0);
11777 MVT VecVT = Vec.getSimpleValueType();
11778 SDValue Idx = Op.getOperand(1);
11779 MVT EltVT = Op.getSimpleValueType();
11781 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11783 // variable index can't be handled in mask registers,
11784 // extend vector to VR512
11785 if (!isa<ConstantSDNode>(Idx)) {
11786 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11787 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11788 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11789 ExtVT.getVectorElementType(), Ext, Idx);
11790 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11793 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11794 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11795 unsigned MaxSift = rc->getSize()*8 - 1;
11796 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11797 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11798 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11799 DAG.getConstant(MaxSift, MVT::i8));
11800 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11801 DAG.getIntPtrConstant(0));
11805 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11806 SelectionDAG &DAG) const {
11808 SDValue Vec = Op.getOperand(0);
11809 MVT VecVT = Vec.getSimpleValueType();
11810 SDValue Idx = Op.getOperand(1);
11812 if (Op.getSimpleValueType() == MVT::i1)
11813 return ExtractBitFromMaskVector(Op, DAG);
11815 if (!isa<ConstantSDNode>(Idx)) {
11816 if (VecVT.is512BitVector() ||
11817 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11818 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11821 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11822 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11823 MaskEltVT.getSizeInBits());
11825 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11826 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11827 getZeroVector(MaskVT, Subtarget, DAG, dl),
11828 Idx, DAG.getConstant(0, getPointerTy()));
11829 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11830 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11831 Perm, DAG.getConstant(0, getPointerTy()));
11836 // If this is a 256-bit vector result, first extract the 128-bit vector and
11837 // then extract the element from the 128-bit vector.
11838 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11840 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11841 // Get the 128-bit vector.
11842 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11843 MVT EltVT = VecVT.getVectorElementType();
11845 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11847 //if (IdxVal >= NumElems/2)
11848 // IdxVal -= NumElems/2;
11849 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11850 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11851 DAG.getConstant(IdxVal, MVT::i32));
11854 assert(VecVT.is128BitVector() && "Unexpected vector length");
11856 if (Subtarget->hasSSE41()) {
11857 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11862 MVT VT = Op.getSimpleValueType();
11863 // TODO: handle v16i8.
11864 if (VT.getSizeInBits() == 16) {
11865 SDValue Vec = Op.getOperand(0);
11866 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11868 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11869 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11870 DAG.getNode(ISD::BITCAST, dl,
11872 Op.getOperand(1)));
11873 // Transform it so it match pextrw which produces a 32-bit result.
11874 MVT EltVT = MVT::i32;
11875 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11876 Op.getOperand(0), Op.getOperand(1));
11877 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11878 DAG.getValueType(VT));
11879 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11882 if (VT.getSizeInBits() == 32) {
11883 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11887 // SHUFPS the element to the lowest double word, then movss.
11888 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11889 MVT VVT = Op.getOperand(0).getSimpleValueType();
11890 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11891 DAG.getUNDEF(VVT), Mask);
11892 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11893 DAG.getIntPtrConstant(0));
11896 if (VT.getSizeInBits() == 64) {
11897 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11898 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11899 // to match extract_elt for f64.
11900 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11904 // UNPCKHPD the element to the lowest double word, then movsd.
11905 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11906 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11907 int Mask[2] = { 1, -1 };
11908 MVT VVT = Op.getOperand(0).getSimpleValueType();
11909 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11910 DAG.getUNDEF(VVT), Mask);
11911 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11912 DAG.getIntPtrConstant(0));
11918 /// Insert one bit to mask vector, like v16i1 or v8i1.
11919 /// AVX-512 feature.
11921 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11923 SDValue Vec = Op.getOperand(0);
11924 SDValue Elt = Op.getOperand(1);
11925 SDValue Idx = Op.getOperand(2);
11926 MVT VecVT = Vec.getSimpleValueType();
11928 if (!isa<ConstantSDNode>(Idx)) {
11929 // Non constant index. Extend source and destination,
11930 // insert element and then truncate the result.
11931 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11932 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11933 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11934 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11935 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11936 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11939 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11940 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11941 if (Vec.getOpcode() == ISD::UNDEF)
11942 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11943 DAG.getConstant(IdxVal, MVT::i8));
11944 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11945 unsigned MaxSift = rc->getSize()*8 - 1;
11946 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11947 DAG.getConstant(MaxSift, MVT::i8));
11948 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11949 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11950 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11953 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11954 SelectionDAG &DAG) const {
11955 MVT VT = Op.getSimpleValueType();
11956 MVT EltVT = VT.getVectorElementType();
11958 if (EltVT == MVT::i1)
11959 return InsertBitToMaskVector(Op, DAG);
11962 SDValue N0 = Op.getOperand(0);
11963 SDValue N1 = Op.getOperand(1);
11964 SDValue N2 = Op.getOperand(2);
11965 if (!isa<ConstantSDNode>(N2))
11967 auto *N2C = cast<ConstantSDNode>(N2);
11968 unsigned IdxVal = N2C->getZExtValue();
11970 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11971 // into that, and then insert the subvector back into the result.
11972 if (VT.is256BitVector() || VT.is512BitVector()) {
11973 // Get the desired 128-bit vector half.
11974 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11976 // Insert the element into the desired half.
11977 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11978 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11980 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11981 DAG.getConstant(IdxIn128, MVT::i32));
11983 // Insert the changed part back to the 256-bit vector
11984 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11986 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11988 if (Subtarget->hasSSE41()) {
11989 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11991 if (VT == MVT::v8i16) {
11992 Opc = X86ISD::PINSRW;
11994 assert(VT == MVT::v16i8);
11995 Opc = X86ISD::PINSRB;
11998 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12000 if (N1.getValueType() != MVT::i32)
12001 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12002 if (N2.getValueType() != MVT::i32)
12003 N2 = DAG.getIntPtrConstant(IdxVal);
12004 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12007 if (EltVT == MVT::f32) {
12008 // Bits [7:6] of the constant are the source select. This will always be
12009 // zero here. The DAG Combiner may combine an extract_elt index into
12011 // bits. For example (insert (extract, 3), 2) could be matched by
12013 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12014 // Bits [5:4] of the constant are the destination select. This is the
12015 // value of the incoming immediate.
12016 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12017 // combine either bitwise AND or insert of float 0.0 to set these bits.
12018 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12019 // Create this as a scalar to vector..
12020 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12021 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12024 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12025 // PINSR* works with constant index.
12030 if (EltVT == MVT::i8)
12033 if (EltVT.getSizeInBits() == 16) {
12034 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12035 // as its second argument.
12036 if (N1.getValueType() != MVT::i32)
12037 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12038 if (N2.getValueType() != MVT::i32)
12039 N2 = DAG.getIntPtrConstant(IdxVal);
12040 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12045 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12047 MVT OpVT = Op.getSimpleValueType();
12049 // If this is a 256-bit vector result, first insert into a 128-bit
12050 // vector and then insert into the 256-bit vector.
12051 if (!OpVT.is128BitVector()) {
12052 // Insert into a 128-bit vector.
12053 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12054 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12055 OpVT.getVectorNumElements() / SizeFactor);
12057 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12059 // Insert the 128-bit vector.
12060 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12063 if (OpVT == MVT::v1i64 &&
12064 Op.getOperand(0).getValueType() == MVT::i64)
12065 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12067 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12068 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12069 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12070 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12073 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12074 // a simple subregister reference or explicit instructions to grab
12075 // upper bits of a vector.
12076 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12077 SelectionDAG &DAG) {
12079 SDValue In = Op.getOperand(0);
12080 SDValue Idx = Op.getOperand(1);
12081 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12082 MVT ResVT = Op.getSimpleValueType();
12083 MVT InVT = In.getSimpleValueType();
12085 if (Subtarget->hasFp256()) {
12086 if (ResVT.is128BitVector() &&
12087 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12088 isa<ConstantSDNode>(Idx)) {
12089 return Extract128BitVector(In, IdxVal, DAG, dl);
12091 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12092 isa<ConstantSDNode>(Idx)) {
12093 return Extract256BitVector(In, IdxVal, DAG, dl);
12099 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12100 // simple superregister reference or explicit instructions to insert
12101 // the upper bits of a vector.
12102 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12103 SelectionDAG &DAG) {
12104 if (Subtarget->hasFp256()) {
12105 SDLoc dl(Op.getNode());
12106 SDValue Vec = Op.getNode()->getOperand(0);
12107 SDValue SubVec = Op.getNode()->getOperand(1);
12108 SDValue Idx = Op.getNode()->getOperand(2);
12110 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12111 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12112 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12113 isa<ConstantSDNode>(Idx)) {
12114 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12115 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12118 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12119 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12120 isa<ConstantSDNode>(Idx)) {
12121 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12122 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12128 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12129 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12130 // one of the above mentioned nodes. It has to be wrapped because otherwise
12131 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12132 // be used to form addressing mode. These wrapped nodes will be selected
12135 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12136 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12139 // global base reg.
12140 unsigned char OpFlag = 0;
12141 unsigned WrapperKind = X86ISD::Wrapper;
12142 CodeModel::Model M = DAG.getTarget().getCodeModel();
12144 if (Subtarget->isPICStyleRIPRel() &&
12145 (M == CodeModel::Small || M == CodeModel::Kernel))
12146 WrapperKind = X86ISD::WrapperRIP;
12147 else if (Subtarget->isPICStyleGOT())
12148 OpFlag = X86II::MO_GOTOFF;
12149 else if (Subtarget->isPICStyleStubPIC())
12150 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12152 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12153 CP->getAlignment(),
12154 CP->getOffset(), OpFlag);
12156 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12157 // With PIC, the address is actually $g + Offset.
12159 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12160 DAG.getNode(X86ISD::GlobalBaseReg,
12161 SDLoc(), getPointerTy()),
12168 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12169 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12172 // global base reg.
12173 unsigned char OpFlag = 0;
12174 unsigned WrapperKind = X86ISD::Wrapper;
12175 CodeModel::Model M = DAG.getTarget().getCodeModel();
12177 if (Subtarget->isPICStyleRIPRel() &&
12178 (M == CodeModel::Small || M == CodeModel::Kernel))
12179 WrapperKind = X86ISD::WrapperRIP;
12180 else if (Subtarget->isPICStyleGOT())
12181 OpFlag = X86II::MO_GOTOFF;
12182 else if (Subtarget->isPICStyleStubPIC())
12183 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12185 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12188 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12190 // With PIC, the address is actually $g + Offset.
12192 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12193 DAG.getNode(X86ISD::GlobalBaseReg,
12194 SDLoc(), getPointerTy()),
12201 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12202 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12204 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12205 // global base reg.
12206 unsigned char OpFlag = 0;
12207 unsigned WrapperKind = X86ISD::Wrapper;
12208 CodeModel::Model M = DAG.getTarget().getCodeModel();
12210 if (Subtarget->isPICStyleRIPRel() &&
12211 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12212 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12213 OpFlag = X86II::MO_GOTPCREL;
12214 WrapperKind = X86ISD::WrapperRIP;
12215 } else if (Subtarget->isPICStyleGOT()) {
12216 OpFlag = X86II::MO_GOT;
12217 } else if (Subtarget->isPICStyleStubPIC()) {
12218 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12219 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12220 OpFlag = X86II::MO_DARWIN_NONLAZY;
12223 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12226 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12228 // With PIC, the address is actually $g + Offset.
12229 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12230 !Subtarget->is64Bit()) {
12231 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12232 DAG.getNode(X86ISD::GlobalBaseReg,
12233 SDLoc(), getPointerTy()),
12237 // For symbols that require a load from a stub to get the address, emit the
12239 if (isGlobalStubReference(OpFlag))
12240 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12241 MachinePointerInfo::getGOT(), false, false, false, 0);
12247 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12248 // Create the TargetBlockAddressAddress node.
12249 unsigned char OpFlags =
12250 Subtarget->ClassifyBlockAddressReference();
12251 CodeModel::Model M = DAG.getTarget().getCodeModel();
12252 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12253 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12255 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12258 if (Subtarget->isPICStyleRIPRel() &&
12259 (M == CodeModel::Small || M == CodeModel::Kernel))
12260 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12262 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12264 // With PIC, the address is actually $g + Offset.
12265 if (isGlobalRelativeToPICBase(OpFlags)) {
12266 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12267 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12275 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12276 int64_t Offset, SelectionDAG &DAG) const {
12277 // Create the TargetGlobalAddress node, folding in the constant
12278 // offset if it is legal.
12279 unsigned char OpFlags =
12280 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12281 CodeModel::Model M = DAG.getTarget().getCodeModel();
12283 if (OpFlags == X86II::MO_NO_FLAG &&
12284 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12285 // A direct static reference to a global.
12286 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12289 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12292 if (Subtarget->isPICStyleRIPRel() &&
12293 (M == CodeModel::Small || M == CodeModel::Kernel))
12294 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12296 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12298 // With PIC, the address is actually $g + Offset.
12299 if (isGlobalRelativeToPICBase(OpFlags)) {
12300 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12301 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12305 // For globals that require a load from a stub to get the address, emit the
12307 if (isGlobalStubReference(OpFlags))
12308 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12309 MachinePointerInfo::getGOT(), false, false, false, 0);
12311 // If there was a non-zero offset that we didn't fold, create an explicit
12312 // addition for it.
12314 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12315 DAG.getConstant(Offset, getPointerTy()));
12321 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12322 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12323 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12324 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12328 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12329 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12330 unsigned char OperandFlags, bool LocalDynamic = false) {
12331 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12332 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12334 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12335 GA->getValueType(0),
12339 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12343 SDValue Ops[] = { Chain, TGA, *InFlag };
12344 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12346 SDValue Ops[] = { Chain, TGA };
12347 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12350 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12351 MFI->setAdjustsStack(true);
12353 SDValue Flag = Chain.getValue(1);
12354 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12357 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12359 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12362 SDLoc dl(GA); // ? function entry point might be better
12363 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12364 DAG.getNode(X86ISD::GlobalBaseReg,
12365 SDLoc(), PtrVT), InFlag);
12366 InFlag = Chain.getValue(1);
12368 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12371 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12373 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12375 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12376 X86::RAX, X86II::MO_TLSGD);
12379 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12385 // Get the start address of the TLS block for this module.
12386 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12387 .getInfo<X86MachineFunctionInfo>();
12388 MFI->incNumLocalDynamicTLSAccesses();
12392 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12393 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12396 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12397 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12398 InFlag = Chain.getValue(1);
12399 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12400 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12403 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12407 unsigned char OperandFlags = X86II::MO_DTPOFF;
12408 unsigned WrapperKind = X86ISD::Wrapper;
12409 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12410 GA->getValueType(0),
12411 GA->getOffset(), OperandFlags);
12412 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12414 // Add x@dtpoff with the base.
12415 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12418 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12419 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12420 const EVT PtrVT, TLSModel::Model model,
12421 bool is64Bit, bool isPIC) {
12424 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12425 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12426 is64Bit ? 257 : 256));
12428 SDValue ThreadPointer =
12429 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12430 MachinePointerInfo(Ptr), false, false, false, 0);
12432 unsigned char OperandFlags = 0;
12433 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12435 unsigned WrapperKind = X86ISD::Wrapper;
12436 if (model == TLSModel::LocalExec) {
12437 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12438 } else if (model == TLSModel::InitialExec) {
12440 OperandFlags = X86II::MO_GOTTPOFF;
12441 WrapperKind = X86ISD::WrapperRIP;
12443 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12446 llvm_unreachable("Unexpected model");
12449 // emit "addl x@ntpoff,%eax" (local exec)
12450 // or "addl x@indntpoff,%eax" (initial exec)
12451 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12453 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12454 GA->getOffset(), OperandFlags);
12455 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12457 if (model == TLSModel::InitialExec) {
12458 if (isPIC && !is64Bit) {
12459 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12460 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12464 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12465 MachinePointerInfo::getGOT(), false, false, false, 0);
12468 // The address of the thread local variable is the add of the thread
12469 // pointer with the offset of the variable.
12470 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12474 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12476 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12477 const GlobalValue *GV = GA->getGlobal();
12479 if (Subtarget->isTargetELF()) {
12480 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12483 case TLSModel::GeneralDynamic:
12484 if (Subtarget->is64Bit())
12485 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12486 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12487 case TLSModel::LocalDynamic:
12488 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12489 Subtarget->is64Bit());
12490 case TLSModel::InitialExec:
12491 case TLSModel::LocalExec:
12492 return LowerToTLSExecModel(
12493 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12494 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12496 llvm_unreachable("Unknown TLS model.");
12499 if (Subtarget->isTargetDarwin()) {
12500 // Darwin only has one model of TLS. Lower to that.
12501 unsigned char OpFlag = 0;
12502 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12503 X86ISD::WrapperRIP : X86ISD::Wrapper;
12505 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12506 // global base reg.
12507 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12508 !Subtarget->is64Bit();
12510 OpFlag = X86II::MO_TLVP_PIC_BASE;
12512 OpFlag = X86II::MO_TLVP;
12514 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12515 GA->getValueType(0),
12516 GA->getOffset(), OpFlag);
12517 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12519 // With PIC32, the address is actually $g + Offset.
12521 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12522 DAG.getNode(X86ISD::GlobalBaseReg,
12523 SDLoc(), getPointerTy()),
12526 // Lowering the machine isd will make sure everything is in the right
12528 SDValue Chain = DAG.getEntryNode();
12529 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12530 SDValue Args[] = { Chain, Offset };
12531 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12533 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12534 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12535 MFI->setAdjustsStack(true);
12537 // And our return value (tls address) is in the standard call return value
12539 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12540 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12541 Chain.getValue(1));
12544 if (Subtarget->isTargetKnownWindowsMSVC() ||
12545 Subtarget->isTargetWindowsGNU()) {
12546 // Just use the implicit TLS architecture
12547 // Need to generate someting similar to:
12548 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12550 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12551 // mov rcx, qword [rdx+rcx*8]
12552 // mov eax, .tls$:tlsvar
12553 // [rax+rcx] contains the address
12554 // Windows 64bit: gs:0x58
12555 // Windows 32bit: fs:__tls_array
12558 SDValue Chain = DAG.getEntryNode();
12560 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12561 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12562 // use its literal value of 0x2C.
12563 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12564 ? Type::getInt8PtrTy(*DAG.getContext(),
12566 : Type::getInt32PtrTy(*DAG.getContext(),
12570 Subtarget->is64Bit()
12571 ? DAG.getIntPtrConstant(0x58)
12572 : (Subtarget->isTargetWindowsGNU()
12573 ? DAG.getIntPtrConstant(0x2C)
12574 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12576 SDValue ThreadPointer =
12577 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12578 MachinePointerInfo(Ptr), false, false, false, 0);
12580 // Load the _tls_index variable
12581 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12582 if (Subtarget->is64Bit())
12583 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12584 IDX, MachinePointerInfo(), MVT::i32,
12585 false, false, false, 0);
12587 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12588 false, false, false, 0);
12590 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12592 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12594 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12595 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12596 false, false, false, 0);
12598 // Get the offset of start of .tls section
12599 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12600 GA->getValueType(0),
12601 GA->getOffset(), X86II::MO_SECREL);
12602 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12604 // The address of the thread local variable is the add of the thread
12605 // pointer with the offset of the variable.
12606 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12609 llvm_unreachable("TLS not implemented for this target.");
12612 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12613 /// and take a 2 x i32 value to shift plus a shift amount.
12614 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12615 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12616 MVT VT = Op.getSimpleValueType();
12617 unsigned VTBits = VT.getSizeInBits();
12619 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12620 SDValue ShOpLo = Op.getOperand(0);
12621 SDValue ShOpHi = Op.getOperand(1);
12622 SDValue ShAmt = Op.getOperand(2);
12623 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12624 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12626 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12627 DAG.getConstant(VTBits - 1, MVT::i8));
12628 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12629 DAG.getConstant(VTBits - 1, MVT::i8))
12630 : DAG.getConstant(0, VT);
12632 SDValue Tmp2, Tmp3;
12633 if (Op.getOpcode() == ISD::SHL_PARTS) {
12634 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12635 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12637 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12638 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12641 // If the shift amount is larger or equal than the width of a part we can't
12642 // rely on the results of shld/shrd. Insert a test and select the appropriate
12643 // values for large shift amounts.
12644 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12645 DAG.getConstant(VTBits, MVT::i8));
12646 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12647 AndNode, DAG.getConstant(0, MVT::i8));
12650 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12651 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12652 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12654 if (Op.getOpcode() == ISD::SHL_PARTS) {
12655 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12656 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12658 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12659 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12662 SDValue Ops[2] = { Lo, Hi };
12663 return DAG.getMergeValues(Ops, dl);
12666 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12667 SelectionDAG &DAG) const {
12668 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12670 if (SrcVT.isVector())
12673 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12674 "Unknown SINT_TO_FP to lower!");
12676 // These are really Legal; return the operand so the caller accepts it as
12678 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12680 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12681 Subtarget->is64Bit()) {
12686 unsigned Size = SrcVT.getSizeInBits()/8;
12687 MachineFunction &MF = DAG.getMachineFunction();
12688 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12689 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12690 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12692 MachinePointerInfo::getFixedStack(SSFI),
12694 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12697 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12699 SelectionDAG &DAG) const {
12703 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12705 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12707 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12709 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12711 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12712 MachineMemOperand *MMO;
12714 int SSFI = FI->getIndex();
12716 DAG.getMachineFunction()
12717 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12718 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12720 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12721 StackSlot = StackSlot.getOperand(1);
12723 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12724 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12726 Tys, Ops, SrcVT, MMO);
12729 Chain = Result.getValue(1);
12730 SDValue InFlag = Result.getValue(2);
12732 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12733 // shouldn't be necessary except that RFP cannot be live across
12734 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12735 MachineFunction &MF = DAG.getMachineFunction();
12736 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12737 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12738 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12739 Tys = DAG.getVTList(MVT::Other);
12741 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12743 MachineMemOperand *MMO =
12744 DAG.getMachineFunction()
12745 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12746 MachineMemOperand::MOStore, SSFISize, SSFISize);
12748 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12749 Ops, Op.getValueType(), MMO);
12750 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12751 MachinePointerInfo::getFixedStack(SSFI),
12752 false, false, false, 0);
12758 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12759 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12760 SelectionDAG &DAG) const {
12761 // This algorithm is not obvious. Here it is what we're trying to output:
12764 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12765 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12767 haddpd %xmm0, %xmm0
12769 pshufd $0x4e, %xmm0, %xmm1
12775 LLVMContext *Context = DAG.getContext();
12777 // Build some magic constants.
12778 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12779 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12780 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12782 SmallVector<Constant*,2> CV1;
12784 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12785 APInt(64, 0x4330000000000000ULL))));
12787 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12788 APInt(64, 0x4530000000000000ULL))));
12789 Constant *C1 = ConstantVector::get(CV1);
12790 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12792 // Load the 64-bit value into an XMM register.
12793 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12795 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12796 MachinePointerInfo::getConstantPool(),
12797 false, false, false, 16);
12798 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12799 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12802 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12803 MachinePointerInfo::getConstantPool(),
12804 false, false, false, 16);
12805 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12806 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12809 if (Subtarget->hasSSE3()) {
12810 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12811 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12813 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12814 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12816 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12817 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12822 DAG.getIntPtrConstant(0));
12825 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12826 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12827 SelectionDAG &DAG) const {
12829 // FP constant to bias correct the final result.
12830 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12833 // Load the 32-bit value into an XMM register.
12834 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12837 // Zero out the upper parts of the register.
12838 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12840 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12841 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12842 DAG.getIntPtrConstant(0));
12844 // Or the load with the bias.
12845 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12846 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12847 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12848 MVT::v2f64, Load)),
12849 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12850 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12851 MVT::v2f64, Bias)));
12852 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12853 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12854 DAG.getIntPtrConstant(0));
12856 // Subtract the bias.
12857 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12859 // Handle final rounding.
12860 EVT DestVT = Op.getValueType();
12862 if (DestVT.bitsLT(MVT::f64))
12863 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12864 DAG.getIntPtrConstant(0));
12865 if (DestVT.bitsGT(MVT::f64))
12866 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12868 // Handle final rounding.
12872 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12873 SelectionDAG &DAG) const {
12874 SDValue N0 = Op.getOperand(0);
12875 MVT SVT = N0.getSimpleValueType();
12878 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12879 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12880 "Custom UINT_TO_FP is not supported!");
12882 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12883 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12884 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12887 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12888 SelectionDAG &DAG) const {
12889 SDValue N0 = Op.getOperand(0);
12892 if (Op.getValueType().isVector())
12893 return lowerUINT_TO_FP_vec(Op, DAG);
12895 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12896 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12897 // the optimization here.
12898 if (DAG.SignBitIsZero(N0))
12899 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12901 MVT SrcVT = N0.getSimpleValueType();
12902 MVT DstVT = Op.getSimpleValueType();
12903 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12904 return LowerUINT_TO_FP_i64(Op, DAG);
12905 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12906 return LowerUINT_TO_FP_i32(Op, DAG);
12907 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12910 // Make a 64-bit buffer, and use it to build an FILD.
12911 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12912 if (SrcVT == MVT::i32) {
12913 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12914 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12915 getPointerTy(), StackSlot, WordOff);
12916 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12917 StackSlot, MachinePointerInfo(),
12919 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12920 OffsetSlot, MachinePointerInfo(),
12922 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12926 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12927 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12928 StackSlot, MachinePointerInfo(),
12930 // For i64 source, we need to add the appropriate power of 2 if the input
12931 // was negative. This is the same as the optimization in
12932 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12933 // we must be careful to do the computation in x87 extended precision, not
12934 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12935 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12936 MachineMemOperand *MMO =
12937 DAG.getMachineFunction()
12938 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12939 MachineMemOperand::MOLoad, 8, 8);
12941 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12942 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12943 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12946 APInt FF(32, 0x5F800000ULL);
12948 // Check whether the sign bit is set.
12949 SDValue SignSet = DAG.getSetCC(dl,
12950 getSetCCResultType(*DAG.getContext(), MVT::i64),
12951 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12954 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12955 SDValue FudgePtr = DAG.getConstantPool(
12956 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12959 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12960 SDValue Zero = DAG.getIntPtrConstant(0);
12961 SDValue Four = DAG.getIntPtrConstant(4);
12962 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12964 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12966 // Load the value out, extending it from f32 to f80.
12967 // FIXME: Avoid the extend by constructing the right constant pool?
12968 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12969 FudgePtr, MachinePointerInfo::getConstantPool(),
12970 MVT::f32, false, false, false, 4);
12971 // Extend everything to 80 bits to force it to be done on x87.
12972 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12973 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12976 std::pair<SDValue,SDValue>
12977 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12978 bool IsSigned, bool IsReplace) const {
12981 EVT DstTy = Op.getValueType();
12983 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12984 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12988 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12989 DstTy.getSimpleVT() >= MVT::i16 &&
12990 "Unknown FP_TO_INT to lower!");
12992 // These are really Legal.
12993 if (DstTy == MVT::i32 &&
12994 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12995 return std::make_pair(SDValue(), SDValue());
12996 if (Subtarget->is64Bit() &&
12997 DstTy == MVT::i64 &&
12998 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12999 return std::make_pair(SDValue(), SDValue());
13001 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13002 // stack slot, or into the FTOL runtime function.
13003 MachineFunction &MF = DAG.getMachineFunction();
13004 unsigned MemSize = DstTy.getSizeInBits()/8;
13005 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13006 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13009 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13010 Opc = X86ISD::WIN_FTOL;
13012 switch (DstTy.getSimpleVT().SimpleTy) {
13013 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13014 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13015 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13016 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13019 SDValue Chain = DAG.getEntryNode();
13020 SDValue Value = Op.getOperand(0);
13021 EVT TheVT = Op.getOperand(0).getValueType();
13022 // FIXME This causes a redundant load/store if the SSE-class value is already
13023 // in memory, such as if it is on the callstack.
13024 if (isScalarFPTypeInSSEReg(TheVT)) {
13025 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13026 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13027 MachinePointerInfo::getFixedStack(SSFI),
13029 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13031 Chain, StackSlot, DAG.getValueType(TheVT)
13034 MachineMemOperand *MMO =
13035 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13036 MachineMemOperand::MOLoad, MemSize, MemSize);
13037 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13038 Chain = Value.getValue(1);
13039 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13040 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13043 MachineMemOperand *MMO =
13044 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13045 MachineMemOperand::MOStore, MemSize, MemSize);
13047 if (Opc != X86ISD::WIN_FTOL) {
13048 // Build the FP_TO_INT*_IN_MEM
13049 SDValue Ops[] = { Chain, Value, StackSlot };
13050 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13052 return std::make_pair(FIST, StackSlot);
13054 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13055 DAG.getVTList(MVT::Other, MVT::Glue),
13057 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13058 MVT::i32, ftol.getValue(1));
13059 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13060 MVT::i32, eax.getValue(2));
13061 SDValue Ops[] = { eax, edx };
13062 SDValue pair = IsReplace
13063 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13064 : DAG.getMergeValues(Ops, DL);
13065 return std::make_pair(pair, SDValue());
13069 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13070 const X86Subtarget *Subtarget) {
13071 MVT VT = Op->getSimpleValueType(0);
13072 SDValue In = Op->getOperand(0);
13073 MVT InVT = In.getSimpleValueType();
13076 // Optimize vectors in AVX mode:
13079 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13080 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13081 // Concat upper and lower parts.
13084 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13085 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13086 // Concat upper and lower parts.
13089 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13090 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13091 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13094 if (Subtarget->hasInt256())
13095 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13097 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13098 SDValue Undef = DAG.getUNDEF(InVT);
13099 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13100 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13101 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13103 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13104 VT.getVectorNumElements()/2);
13106 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13107 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13109 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13112 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13113 SelectionDAG &DAG) {
13114 MVT VT = Op->getSimpleValueType(0);
13115 SDValue In = Op->getOperand(0);
13116 MVT InVT = In.getSimpleValueType();
13118 unsigned int NumElts = VT.getVectorNumElements();
13119 if (NumElts != 8 && NumElts != 16)
13122 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13123 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13125 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13127 // Now we have only mask extension
13128 assert(InVT.getVectorElementType() == MVT::i1);
13129 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13130 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13131 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13132 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13133 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13134 MachinePointerInfo::getConstantPool(),
13135 false, false, false, Alignment);
13137 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13138 if (VT.is512BitVector())
13140 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13143 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13144 SelectionDAG &DAG) {
13145 if (Subtarget->hasFp256()) {
13146 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13154 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13155 SelectionDAG &DAG) {
13157 MVT VT = Op.getSimpleValueType();
13158 SDValue In = Op.getOperand(0);
13159 MVT SVT = In.getSimpleValueType();
13161 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13162 return LowerZERO_EXTEND_AVX512(Op, DAG);
13164 if (Subtarget->hasFp256()) {
13165 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13170 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13171 VT.getVectorNumElements() != SVT.getVectorNumElements());
13175 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13177 MVT VT = Op.getSimpleValueType();
13178 SDValue In = Op.getOperand(0);
13179 MVT InVT = In.getSimpleValueType();
13181 if (VT == MVT::i1) {
13182 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13183 "Invalid scalar TRUNCATE operation");
13184 if (InVT.getSizeInBits() >= 32)
13186 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13187 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13189 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13190 "Invalid TRUNCATE operation");
13192 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13193 if (VT.getVectorElementType().getSizeInBits() >=8)
13194 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13196 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13197 unsigned NumElts = InVT.getVectorNumElements();
13198 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13199 if (InVT.getSizeInBits() < 512) {
13200 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13201 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13205 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13206 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13207 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13208 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13209 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13210 MachinePointerInfo::getConstantPool(),
13211 false, false, false, Alignment);
13212 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13213 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13214 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13217 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13218 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13219 if (Subtarget->hasInt256()) {
13220 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13221 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13222 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13224 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13225 DAG.getIntPtrConstant(0));
13228 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13229 DAG.getIntPtrConstant(0));
13230 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13231 DAG.getIntPtrConstant(2));
13232 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13233 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13234 static const int ShufMask[] = {0, 2, 4, 6};
13235 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13238 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13239 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13240 if (Subtarget->hasInt256()) {
13241 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13243 SmallVector<SDValue,32> pshufbMask;
13244 for (unsigned i = 0; i < 2; ++i) {
13245 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13246 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13247 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13248 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13249 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13250 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13251 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13252 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13253 for (unsigned j = 0; j < 8; ++j)
13254 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13256 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13257 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13258 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13260 static const int ShufMask[] = {0, 2, -1, -1};
13261 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13263 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13264 DAG.getIntPtrConstant(0));
13265 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13268 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13269 DAG.getIntPtrConstant(0));
13271 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13272 DAG.getIntPtrConstant(4));
13274 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13275 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13277 // The PSHUFB mask:
13278 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13279 -1, -1, -1, -1, -1, -1, -1, -1};
13281 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13282 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13283 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13285 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13286 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13288 // The MOVLHPS Mask:
13289 static const int ShufMask2[] = {0, 1, 4, 5};
13290 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13291 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13294 // Handle truncation of V256 to V128 using shuffles.
13295 if (!VT.is128BitVector() || !InVT.is256BitVector())
13298 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13300 unsigned NumElems = VT.getVectorNumElements();
13301 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13303 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13304 // Prepare truncation shuffle mask
13305 for (unsigned i = 0; i != NumElems; ++i)
13306 MaskVec[i] = i * 2;
13307 SDValue V = DAG.getVectorShuffle(NVT, DL,
13308 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13309 DAG.getUNDEF(NVT), &MaskVec[0]);
13310 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13311 DAG.getIntPtrConstant(0));
13314 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13315 SelectionDAG &DAG) const {
13316 assert(!Op.getSimpleValueType().isVector());
13318 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13319 /*IsSigned=*/ true, /*IsReplace=*/ false);
13320 SDValue FIST = Vals.first, StackSlot = Vals.second;
13321 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13322 if (!FIST.getNode()) return Op;
13324 if (StackSlot.getNode())
13325 // Load the result.
13326 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13327 FIST, StackSlot, MachinePointerInfo(),
13328 false, false, false, 0);
13330 // The node is the result.
13334 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13335 SelectionDAG &DAG) const {
13336 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13337 /*IsSigned=*/ false, /*IsReplace=*/ false);
13338 SDValue FIST = Vals.first, StackSlot = Vals.second;
13339 assert(FIST.getNode() && "Unexpected failure");
13341 if (StackSlot.getNode())
13342 // Load the result.
13343 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13344 FIST, StackSlot, MachinePointerInfo(),
13345 false, false, false, 0);
13347 // The node is the result.
13351 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13353 MVT VT = Op.getSimpleValueType();
13354 SDValue In = Op.getOperand(0);
13355 MVT SVT = In.getSimpleValueType();
13357 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13359 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13360 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13361 In, DAG.getUNDEF(SVT)));
13364 // The only differences between FABS and FNEG are the mask and the logic op.
13365 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13366 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13367 "Wrong opcode for lowering FABS or FNEG.");
13369 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13371 MVT VT = Op.getSimpleValueType();
13372 // Assume scalar op for initialization; update for vector if needed.
13373 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13374 // generate a 16-byte vector constant and logic op even for the scalar case.
13375 // Using a 16-byte mask allows folding the load of the mask with
13376 // the logic op, so it can save (~4 bytes) on code size.
13378 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13379 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13380 // decide if we should generate a 16-byte constant mask when we only need 4 or
13381 // 8 bytes for the scalar case.
13382 if (VT.isVector()) {
13383 EltVT = VT.getVectorElementType();
13384 NumElts = VT.getVectorNumElements();
13387 unsigned EltBits = EltVT.getSizeInBits();
13388 LLVMContext *Context = DAG.getContext();
13389 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13391 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13392 Constant *C = ConstantInt::get(*Context, MaskElt);
13393 C = ConstantVector::getSplat(NumElts, C);
13394 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13395 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13396 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13397 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13398 MachinePointerInfo::getConstantPool(),
13399 false, false, false, Alignment);
13401 if (VT.isVector()) {
13402 // For a vector, cast operands to a vector type, perform the logic op,
13403 // and cast the result back to the original value type.
13404 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13405 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13406 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13407 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13408 return DAG.getNode(ISD::BITCAST, dl, VT,
13409 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13411 // If not vector, then scalar.
13412 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13413 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13416 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13418 LLVMContext *Context = DAG.getContext();
13419 SDValue Op0 = Op.getOperand(0);
13420 SDValue Op1 = Op.getOperand(1);
13422 MVT VT = Op.getSimpleValueType();
13423 MVT SrcVT = Op1.getSimpleValueType();
13425 // If second operand is smaller, extend it first.
13426 if (SrcVT.bitsLT(VT)) {
13427 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13430 // And if it is bigger, shrink it first.
13431 if (SrcVT.bitsGT(VT)) {
13432 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13436 // At this point the operands and the result should have the same
13437 // type, and that won't be f80 since that is not custom lowered.
13439 // First get the sign bit of second operand.
13440 SmallVector<Constant*,4> CV;
13441 if (SrcVT == MVT::f64) {
13442 const fltSemantics &Sem = APFloat::IEEEdouble;
13443 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13444 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13446 const fltSemantics &Sem = APFloat::IEEEsingle;
13447 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13448 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13449 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13450 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13452 Constant *C = ConstantVector::get(CV);
13453 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13454 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13455 MachinePointerInfo::getConstantPool(),
13456 false, false, false, 16);
13457 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13459 // Shift sign bit right or left if the two operands have different types.
13460 if (SrcVT.bitsGT(VT)) {
13461 // Op0 is MVT::f32, Op1 is MVT::f64.
13462 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13463 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13464 DAG.getConstant(32, MVT::i32));
13465 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13466 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13467 DAG.getIntPtrConstant(0));
13470 // Clear first operand sign bit.
13472 if (VT == MVT::f64) {
13473 const fltSemantics &Sem = APFloat::IEEEdouble;
13474 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13475 APInt(64, ~(1ULL << 63)))));
13476 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13478 const fltSemantics &Sem = APFloat::IEEEsingle;
13479 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13480 APInt(32, ~(1U << 31)))));
13481 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13482 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13483 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13485 C = ConstantVector::get(CV);
13486 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13487 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13488 MachinePointerInfo::getConstantPool(),
13489 false, false, false, 16);
13490 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13492 // Or the value with the sign bit.
13493 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13496 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13497 SDValue N0 = Op.getOperand(0);
13499 MVT VT = Op.getSimpleValueType();
13501 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13502 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13503 DAG.getConstant(1, VT));
13504 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13507 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13509 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13510 SelectionDAG &DAG) {
13511 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13513 if (!Subtarget->hasSSE41())
13516 if (!Op->hasOneUse())
13519 SDNode *N = Op.getNode();
13522 SmallVector<SDValue, 8> Opnds;
13523 DenseMap<SDValue, unsigned> VecInMap;
13524 SmallVector<SDValue, 8> VecIns;
13525 EVT VT = MVT::Other;
13527 // Recognize a special case where a vector is casted into wide integer to
13529 Opnds.push_back(N->getOperand(0));
13530 Opnds.push_back(N->getOperand(1));
13532 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13533 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13534 // BFS traverse all OR'd operands.
13535 if (I->getOpcode() == ISD::OR) {
13536 Opnds.push_back(I->getOperand(0));
13537 Opnds.push_back(I->getOperand(1));
13538 // Re-evaluate the number of nodes to be traversed.
13539 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13543 // Quit if a non-EXTRACT_VECTOR_ELT
13544 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13547 // Quit if without a constant index.
13548 SDValue Idx = I->getOperand(1);
13549 if (!isa<ConstantSDNode>(Idx))
13552 SDValue ExtractedFromVec = I->getOperand(0);
13553 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13554 if (M == VecInMap.end()) {
13555 VT = ExtractedFromVec.getValueType();
13556 // Quit if not 128/256-bit vector.
13557 if (!VT.is128BitVector() && !VT.is256BitVector())
13559 // Quit if not the same type.
13560 if (VecInMap.begin() != VecInMap.end() &&
13561 VT != VecInMap.begin()->first.getValueType())
13563 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13564 VecIns.push_back(ExtractedFromVec);
13566 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13569 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13570 "Not extracted from 128-/256-bit vector.");
13572 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13574 for (DenseMap<SDValue, unsigned>::const_iterator
13575 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13576 // Quit if not all elements are used.
13577 if (I->second != FullMask)
13581 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13583 // Cast all vectors into TestVT for PTEST.
13584 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13585 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13587 // If more than one full vectors are evaluated, OR them first before PTEST.
13588 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13589 // Each iteration will OR 2 nodes and append the result until there is only
13590 // 1 node left, i.e. the final OR'd value of all vectors.
13591 SDValue LHS = VecIns[Slot];
13592 SDValue RHS = VecIns[Slot + 1];
13593 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13596 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13597 VecIns.back(), VecIns.back());
13600 /// \brief return true if \c Op has a use that doesn't just read flags.
13601 static bool hasNonFlagsUse(SDValue Op) {
13602 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13604 SDNode *User = *UI;
13605 unsigned UOpNo = UI.getOperandNo();
13606 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13607 // Look pass truncate.
13608 UOpNo = User->use_begin().getOperandNo();
13609 User = *User->use_begin();
13612 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13613 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13619 /// Emit nodes that will be selected as "test Op0,Op0", or something
13621 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13622 SelectionDAG &DAG) const {
13623 if (Op.getValueType() == MVT::i1)
13624 // KORTEST instruction should be selected
13625 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13626 DAG.getConstant(0, Op.getValueType()));
13628 // CF and OF aren't always set the way we want. Determine which
13629 // of these we need.
13630 bool NeedCF = false;
13631 bool NeedOF = false;
13634 case X86::COND_A: case X86::COND_AE:
13635 case X86::COND_B: case X86::COND_BE:
13638 case X86::COND_G: case X86::COND_GE:
13639 case X86::COND_L: case X86::COND_LE:
13640 case X86::COND_O: case X86::COND_NO: {
13641 // Check if we really need to set the
13642 // Overflow flag. If NoSignedWrap is present
13643 // that is not actually needed.
13644 switch (Op->getOpcode()) {
13649 const BinaryWithFlagsSDNode *BinNode =
13650 cast<BinaryWithFlagsSDNode>(Op.getNode());
13651 if (BinNode->hasNoSignedWrap())
13661 // See if we can use the EFLAGS value from the operand instead of
13662 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13663 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13664 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13665 // Emit a CMP with 0, which is the TEST pattern.
13666 //if (Op.getValueType() == MVT::i1)
13667 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13668 // DAG.getConstant(0, MVT::i1));
13669 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13670 DAG.getConstant(0, Op.getValueType()));
13672 unsigned Opcode = 0;
13673 unsigned NumOperands = 0;
13675 // Truncate operations may prevent the merge of the SETCC instruction
13676 // and the arithmetic instruction before it. Attempt to truncate the operands
13677 // of the arithmetic instruction and use a reduced bit-width instruction.
13678 bool NeedTruncation = false;
13679 SDValue ArithOp = Op;
13680 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13681 SDValue Arith = Op->getOperand(0);
13682 // Both the trunc and the arithmetic op need to have one user each.
13683 if (Arith->hasOneUse())
13684 switch (Arith.getOpcode()) {
13691 NeedTruncation = true;
13697 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13698 // which may be the result of a CAST. We use the variable 'Op', which is the
13699 // non-casted variable when we check for possible users.
13700 switch (ArithOp.getOpcode()) {
13702 // Due to an isel shortcoming, be conservative if this add is likely to be
13703 // selected as part of a load-modify-store instruction. When the root node
13704 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13705 // uses of other nodes in the match, such as the ADD in this case. This
13706 // leads to the ADD being left around and reselected, with the result being
13707 // two adds in the output. Alas, even if none our users are stores, that
13708 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13709 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13710 // climbing the DAG back to the root, and it doesn't seem to be worth the
13712 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13713 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13714 if (UI->getOpcode() != ISD::CopyToReg &&
13715 UI->getOpcode() != ISD::SETCC &&
13716 UI->getOpcode() != ISD::STORE)
13719 if (ConstantSDNode *C =
13720 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13721 // An add of one will be selected as an INC.
13722 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13723 Opcode = X86ISD::INC;
13728 // An add of negative one (subtract of one) will be selected as a DEC.
13729 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13730 Opcode = X86ISD::DEC;
13736 // Otherwise use a regular EFLAGS-setting add.
13737 Opcode = X86ISD::ADD;
13742 // If we have a constant logical shift that's only used in a comparison
13743 // against zero turn it into an equivalent AND. This allows turning it into
13744 // a TEST instruction later.
13745 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13746 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13747 EVT VT = Op.getValueType();
13748 unsigned BitWidth = VT.getSizeInBits();
13749 unsigned ShAmt = Op->getConstantOperandVal(1);
13750 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13752 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13753 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13754 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13755 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13757 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13758 DAG.getConstant(Mask, VT));
13759 DAG.ReplaceAllUsesWith(Op, New);
13765 // If the primary and result isn't used, don't bother using X86ISD::AND,
13766 // because a TEST instruction will be better.
13767 if (!hasNonFlagsUse(Op))
13773 // Due to the ISEL shortcoming noted above, be conservative if this op is
13774 // likely to be selected as part of a load-modify-store instruction.
13775 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13776 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13777 if (UI->getOpcode() == ISD::STORE)
13780 // Otherwise use a regular EFLAGS-setting instruction.
13781 switch (ArithOp.getOpcode()) {
13782 default: llvm_unreachable("unexpected operator!");
13783 case ISD::SUB: Opcode = X86ISD::SUB; break;
13784 case ISD::XOR: Opcode = X86ISD::XOR; break;
13785 case ISD::AND: Opcode = X86ISD::AND; break;
13787 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13788 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13789 if (EFLAGS.getNode())
13792 Opcode = X86ISD::OR;
13806 return SDValue(Op.getNode(), 1);
13812 // If we found that truncation is beneficial, perform the truncation and
13814 if (NeedTruncation) {
13815 EVT VT = Op.getValueType();
13816 SDValue WideVal = Op->getOperand(0);
13817 EVT WideVT = WideVal.getValueType();
13818 unsigned ConvertedOp = 0;
13819 // Use a target machine opcode to prevent further DAGCombine
13820 // optimizations that may separate the arithmetic operations
13821 // from the setcc node.
13822 switch (WideVal.getOpcode()) {
13824 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13825 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13826 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13827 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13828 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13833 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13834 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13835 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13836 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13842 // Emit a CMP with 0, which is the TEST pattern.
13843 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13844 DAG.getConstant(0, Op.getValueType()));
13846 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13847 SmallVector<SDValue, 4> Ops;
13848 for (unsigned i = 0; i != NumOperands; ++i)
13849 Ops.push_back(Op.getOperand(i));
13851 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13852 DAG.ReplaceAllUsesWith(Op, New);
13853 return SDValue(New.getNode(), 1);
13856 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13858 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13859 SDLoc dl, SelectionDAG &DAG) const {
13860 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13861 if (C->getAPIntValue() == 0)
13862 return EmitTest(Op0, X86CC, dl, DAG);
13864 if (Op0.getValueType() == MVT::i1)
13865 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13868 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13869 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13870 // Do the comparison at i32 if it's smaller, besides the Atom case.
13871 // This avoids subregister aliasing issues. Keep the smaller reference
13872 // if we're optimizing for size, however, as that'll allow better folding
13873 // of memory operations.
13874 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13875 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13876 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13877 !Subtarget->isAtom()) {
13878 unsigned ExtendOp =
13879 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13880 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13881 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13883 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13884 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13885 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13887 return SDValue(Sub.getNode(), 1);
13889 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13892 /// Convert a comparison if required by the subtarget.
13893 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13894 SelectionDAG &DAG) const {
13895 // If the subtarget does not support the FUCOMI instruction, floating-point
13896 // comparisons have to be converted.
13897 if (Subtarget->hasCMov() ||
13898 Cmp.getOpcode() != X86ISD::CMP ||
13899 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13900 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13903 // The instruction selector will select an FUCOM instruction instead of
13904 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13905 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13906 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13908 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13909 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13910 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13911 DAG.getConstant(8, MVT::i8));
13912 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13913 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13916 static bool isAllOnes(SDValue V) {
13917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13918 return C && C->isAllOnesValue();
13921 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13922 /// if it's possible.
13923 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13924 SDLoc dl, SelectionDAG &DAG) const {
13925 SDValue Op0 = And.getOperand(0);
13926 SDValue Op1 = And.getOperand(1);
13927 if (Op0.getOpcode() == ISD::TRUNCATE)
13928 Op0 = Op0.getOperand(0);
13929 if (Op1.getOpcode() == ISD::TRUNCATE)
13930 Op1 = Op1.getOperand(0);
13933 if (Op1.getOpcode() == ISD::SHL)
13934 std::swap(Op0, Op1);
13935 if (Op0.getOpcode() == ISD::SHL) {
13936 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13937 if (And00C->getZExtValue() == 1) {
13938 // If we looked past a truncate, check that it's only truncating away
13940 unsigned BitWidth = Op0.getValueSizeInBits();
13941 unsigned AndBitWidth = And.getValueSizeInBits();
13942 if (BitWidth > AndBitWidth) {
13944 DAG.computeKnownBits(Op0, Zeros, Ones);
13945 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13949 RHS = Op0.getOperand(1);
13951 } else if (Op1.getOpcode() == ISD::Constant) {
13952 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13953 uint64_t AndRHSVal = AndRHS->getZExtValue();
13954 SDValue AndLHS = Op0;
13956 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13957 LHS = AndLHS.getOperand(0);
13958 RHS = AndLHS.getOperand(1);
13961 // Use BT if the immediate can't be encoded in a TEST instruction.
13962 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13964 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13968 if (LHS.getNode()) {
13969 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13970 // instruction. Since the shift amount is in-range-or-undefined, we know
13971 // that doing a bittest on the i32 value is ok. We extend to i32 because
13972 // the encoding for the i16 version is larger than the i32 version.
13973 // Also promote i16 to i32 for performance / code size reason.
13974 if (LHS.getValueType() == MVT::i8 ||
13975 LHS.getValueType() == MVT::i16)
13976 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13978 // If the operand types disagree, extend the shift amount to match. Since
13979 // BT ignores high bits (like shifts) we can use anyextend.
13980 if (LHS.getValueType() != RHS.getValueType())
13981 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13983 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13984 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13985 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13986 DAG.getConstant(Cond, MVT::i8), BT);
13992 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13994 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13999 // SSE Condition code mapping:
14008 switch (SetCCOpcode) {
14009 default: llvm_unreachable("Unexpected SETCC condition");
14011 case ISD::SETEQ: SSECC = 0; break;
14013 case ISD::SETGT: Swap = true; // Fallthrough
14015 case ISD::SETOLT: SSECC = 1; break;
14017 case ISD::SETGE: Swap = true; // Fallthrough
14019 case ISD::SETOLE: SSECC = 2; break;
14020 case ISD::SETUO: SSECC = 3; break;
14022 case ISD::SETNE: SSECC = 4; break;
14023 case ISD::SETULE: Swap = true; // Fallthrough
14024 case ISD::SETUGE: SSECC = 5; break;
14025 case ISD::SETULT: Swap = true; // Fallthrough
14026 case ISD::SETUGT: SSECC = 6; break;
14027 case ISD::SETO: SSECC = 7; break;
14029 case ISD::SETONE: SSECC = 8; break;
14032 std::swap(Op0, Op1);
14037 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14038 // ones, and then concatenate the result back.
14039 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14040 MVT VT = Op.getSimpleValueType();
14042 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14043 "Unsupported value type for operation");
14045 unsigned NumElems = VT.getVectorNumElements();
14047 SDValue CC = Op.getOperand(2);
14049 // Extract the LHS vectors
14050 SDValue LHS = Op.getOperand(0);
14051 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14052 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14054 // Extract the RHS vectors
14055 SDValue RHS = Op.getOperand(1);
14056 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14057 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14059 // Issue the operation on the smaller types and concatenate the result back
14060 MVT EltVT = VT.getVectorElementType();
14061 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14062 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14063 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14064 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14067 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14068 const X86Subtarget *Subtarget) {
14069 SDValue Op0 = Op.getOperand(0);
14070 SDValue Op1 = Op.getOperand(1);
14071 SDValue CC = Op.getOperand(2);
14072 MVT VT = Op.getSimpleValueType();
14075 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14076 Op.getValueType().getScalarType() == MVT::i1 &&
14077 "Cannot set masked compare for this operation");
14079 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14081 bool Unsigned = false;
14084 switch (SetCCOpcode) {
14085 default: llvm_unreachable("Unexpected SETCC condition");
14086 case ISD::SETNE: SSECC = 4; break;
14087 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14088 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14089 case ISD::SETLT: Swap = true; //fall-through
14090 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14091 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14092 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14093 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14094 case ISD::SETULE: Unsigned = true; //fall-through
14095 case ISD::SETLE: SSECC = 2; break;
14099 std::swap(Op0, Op1);
14101 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14102 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14103 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14104 DAG.getConstant(SSECC, MVT::i8));
14107 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14108 /// operand \p Op1. If non-trivial (for example because it's not constant)
14109 /// return an empty value.
14110 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14112 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14116 MVT VT = Op1.getSimpleValueType();
14117 MVT EVT = VT.getVectorElementType();
14118 unsigned n = VT.getVectorNumElements();
14119 SmallVector<SDValue, 8> ULTOp1;
14121 for (unsigned i = 0; i < n; ++i) {
14122 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14123 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14126 // Avoid underflow.
14127 APInt Val = Elt->getAPIntValue();
14131 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14134 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14137 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14138 SelectionDAG &DAG) {
14139 SDValue Op0 = Op.getOperand(0);
14140 SDValue Op1 = Op.getOperand(1);
14141 SDValue CC = Op.getOperand(2);
14142 MVT VT = Op.getSimpleValueType();
14143 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14144 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14149 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14150 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14153 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14154 unsigned Opc = X86ISD::CMPP;
14155 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14156 assert(VT.getVectorNumElements() <= 16);
14157 Opc = X86ISD::CMPM;
14159 // In the two special cases we can't handle, emit two comparisons.
14162 unsigned CombineOpc;
14163 if (SetCCOpcode == ISD::SETUEQ) {
14164 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14166 assert(SetCCOpcode == ISD::SETONE);
14167 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14170 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14171 DAG.getConstant(CC0, MVT::i8));
14172 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14173 DAG.getConstant(CC1, MVT::i8));
14174 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14176 // Handle all other FP comparisons here.
14177 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14178 DAG.getConstant(SSECC, MVT::i8));
14181 // Break 256-bit integer vector compare into smaller ones.
14182 if (VT.is256BitVector() && !Subtarget->hasInt256())
14183 return Lower256IntVSETCC(Op, DAG);
14185 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14186 EVT OpVT = Op1.getValueType();
14187 if (Subtarget->hasAVX512()) {
14188 if (Op1.getValueType().is512BitVector() ||
14189 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14190 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14191 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14193 // In AVX-512 architecture setcc returns mask with i1 elements,
14194 // But there is no compare instruction for i8 and i16 elements in KNL.
14195 // We are not talking about 512-bit operands in this case, these
14196 // types are illegal.
14198 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14199 OpVT.getVectorElementType().getSizeInBits() >= 8))
14200 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14201 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14204 // We are handling one of the integer comparisons here. Since SSE only has
14205 // GT and EQ comparisons for integer, swapping operands and multiple
14206 // operations may be required for some comparisons.
14208 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14209 bool Subus = false;
14211 switch (SetCCOpcode) {
14212 default: llvm_unreachable("Unexpected SETCC condition");
14213 case ISD::SETNE: Invert = true;
14214 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14215 case ISD::SETLT: Swap = true;
14216 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14217 case ISD::SETGE: Swap = true;
14218 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14219 Invert = true; break;
14220 case ISD::SETULT: Swap = true;
14221 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14222 FlipSigns = true; break;
14223 case ISD::SETUGE: Swap = true;
14224 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14225 FlipSigns = true; Invert = true; break;
14228 // Special case: Use min/max operations for SETULE/SETUGE
14229 MVT VET = VT.getVectorElementType();
14231 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14232 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14235 switch (SetCCOpcode) {
14237 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14238 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14241 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14244 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14245 if (!MinMax && hasSubus) {
14246 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14248 // t = psubus Op0, Op1
14249 // pcmpeq t, <0..0>
14250 switch (SetCCOpcode) {
14252 case ISD::SETULT: {
14253 // If the comparison is against a constant we can turn this into a
14254 // setule. With psubus, setule does not require a swap. This is
14255 // beneficial because the constant in the register is no longer
14256 // destructed as the destination so it can be hoisted out of a loop.
14257 // Only do this pre-AVX since vpcmp* is no longer destructive.
14258 if (Subtarget->hasAVX())
14260 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14261 if (ULEOp1.getNode()) {
14263 Subus = true; Invert = false; Swap = false;
14267 // Psubus is better than flip-sign because it requires no inversion.
14268 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14269 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14273 Opc = X86ISD::SUBUS;
14279 std::swap(Op0, Op1);
14281 // Check that the operation in question is available (most are plain SSE2,
14282 // but PCMPGTQ and PCMPEQQ have different requirements).
14283 if (VT == MVT::v2i64) {
14284 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14285 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14287 // First cast everything to the right type.
14288 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14289 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14291 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14292 // bits of the inputs before performing those operations. The lower
14293 // compare is always unsigned.
14296 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14298 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14299 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14300 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14301 Sign, Zero, Sign, Zero);
14303 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14304 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14306 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14307 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14308 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14310 // Create masks for only the low parts/high parts of the 64 bit integers.
14311 static const int MaskHi[] = { 1, 1, 3, 3 };
14312 static const int MaskLo[] = { 0, 0, 2, 2 };
14313 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14314 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14315 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14317 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14318 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14321 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14323 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14326 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14327 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14328 // pcmpeqd + pshufd + pand.
14329 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14331 // First cast everything to the right type.
14332 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14333 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14336 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14338 // Make sure the lower and upper halves are both all-ones.
14339 static const int Mask[] = { 1, 0, 3, 2 };
14340 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14341 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14344 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14346 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14350 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14351 // bits of the inputs before performing those operations.
14353 EVT EltVT = VT.getVectorElementType();
14354 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14355 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14356 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14359 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14361 // If the logical-not of the result is required, perform that now.
14363 Result = DAG.getNOT(dl, Result, VT);
14366 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14369 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14370 getZeroVector(VT, Subtarget, DAG, dl));
14375 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14377 MVT VT = Op.getSimpleValueType();
14379 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14381 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14382 && "SetCC type must be 8-bit or 1-bit integer");
14383 SDValue Op0 = Op.getOperand(0);
14384 SDValue Op1 = Op.getOperand(1);
14386 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14388 // Optimize to BT if possible.
14389 // Lower (X & (1 << N)) == 0 to BT(X, N).
14390 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14391 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14392 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14393 Op1.getOpcode() == ISD::Constant &&
14394 cast<ConstantSDNode>(Op1)->isNullValue() &&
14395 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14396 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14397 if (NewSetCC.getNode())
14401 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14403 if (Op1.getOpcode() == ISD::Constant &&
14404 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14405 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14406 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14408 // If the input is a setcc, then reuse the input setcc or use a new one with
14409 // the inverted condition.
14410 if (Op0.getOpcode() == X86ISD::SETCC) {
14411 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14412 bool Invert = (CC == ISD::SETNE) ^
14413 cast<ConstantSDNode>(Op1)->isNullValue();
14417 CCode = X86::GetOppositeBranchCondition(CCode);
14418 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14419 DAG.getConstant(CCode, MVT::i8),
14420 Op0.getOperand(1));
14422 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14426 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14427 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14428 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14430 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14431 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14434 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14435 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14436 if (X86CC == X86::COND_INVALID)
14439 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14440 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14441 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14442 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14444 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14448 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14449 static bool isX86LogicalCmp(SDValue Op) {
14450 unsigned Opc = Op.getNode()->getOpcode();
14451 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14452 Opc == X86ISD::SAHF)
14454 if (Op.getResNo() == 1 &&
14455 (Opc == X86ISD::ADD ||
14456 Opc == X86ISD::SUB ||
14457 Opc == X86ISD::ADC ||
14458 Opc == X86ISD::SBB ||
14459 Opc == X86ISD::SMUL ||
14460 Opc == X86ISD::UMUL ||
14461 Opc == X86ISD::INC ||
14462 Opc == X86ISD::DEC ||
14463 Opc == X86ISD::OR ||
14464 Opc == X86ISD::XOR ||
14465 Opc == X86ISD::AND))
14468 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14474 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14475 if (V.getOpcode() != ISD::TRUNCATE)
14478 SDValue VOp0 = V.getOperand(0);
14479 unsigned InBits = VOp0.getValueSizeInBits();
14480 unsigned Bits = V.getValueSizeInBits();
14481 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14484 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14485 bool addTest = true;
14486 SDValue Cond = Op.getOperand(0);
14487 SDValue Op1 = Op.getOperand(1);
14488 SDValue Op2 = Op.getOperand(2);
14490 EVT VT = Op1.getValueType();
14493 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14494 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14495 // sequence later on.
14496 if (Cond.getOpcode() == ISD::SETCC &&
14497 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14498 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14499 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14500 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14501 int SSECC = translateX86FSETCC(
14502 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14505 if (Subtarget->hasAVX512()) {
14506 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14507 DAG.getConstant(SSECC, MVT::i8));
14508 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14510 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14511 DAG.getConstant(SSECC, MVT::i8));
14512 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14513 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14514 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14518 if (Cond.getOpcode() == ISD::SETCC) {
14519 SDValue NewCond = LowerSETCC(Cond, DAG);
14520 if (NewCond.getNode())
14524 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14525 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14526 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14527 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14528 if (Cond.getOpcode() == X86ISD::SETCC &&
14529 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14530 isZero(Cond.getOperand(1).getOperand(1))) {
14531 SDValue Cmp = Cond.getOperand(1);
14533 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14535 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14536 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14537 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14539 SDValue CmpOp0 = Cmp.getOperand(0);
14540 // Apply further optimizations for special cases
14541 // (select (x != 0), -1, 0) -> neg & sbb
14542 // (select (x == 0), 0, -1) -> neg & sbb
14543 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14544 if (YC->isNullValue() &&
14545 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14546 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14547 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14548 DAG.getConstant(0, CmpOp0.getValueType()),
14550 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14551 DAG.getConstant(X86::COND_B, MVT::i8),
14552 SDValue(Neg.getNode(), 1));
14556 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14557 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14558 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14560 SDValue Res = // Res = 0 or -1.
14561 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14562 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14564 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14565 Res = DAG.getNOT(DL, Res, Res.getValueType());
14567 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14568 if (!N2C || !N2C->isNullValue())
14569 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14574 // Look past (and (setcc_carry (cmp ...)), 1).
14575 if (Cond.getOpcode() == ISD::AND &&
14576 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14577 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14578 if (C && C->getAPIntValue() == 1)
14579 Cond = Cond.getOperand(0);
14582 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14583 // setting operand in place of the X86ISD::SETCC.
14584 unsigned CondOpcode = Cond.getOpcode();
14585 if (CondOpcode == X86ISD::SETCC ||
14586 CondOpcode == X86ISD::SETCC_CARRY) {
14587 CC = Cond.getOperand(0);
14589 SDValue Cmp = Cond.getOperand(1);
14590 unsigned Opc = Cmp.getOpcode();
14591 MVT VT = Op.getSimpleValueType();
14593 bool IllegalFPCMov = false;
14594 if (VT.isFloatingPoint() && !VT.isVector() &&
14595 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14596 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14598 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14599 Opc == X86ISD::BT) { // FIXME
14603 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14604 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14605 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14606 Cond.getOperand(0).getValueType() != MVT::i8)) {
14607 SDValue LHS = Cond.getOperand(0);
14608 SDValue RHS = Cond.getOperand(1);
14609 unsigned X86Opcode;
14612 switch (CondOpcode) {
14613 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14614 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14615 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14616 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14617 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14618 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14619 default: llvm_unreachable("unexpected overflowing operator");
14621 if (CondOpcode == ISD::UMULO)
14622 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14625 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14627 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14629 if (CondOpcode == ISD::UMULO)
14630 Cond = X86Op.getValue(2);
14632 Cond = X86Op.getValue(1);
14634 CC = DAG.getConstant(X86Cond, MVT::i8);
14639 // Look pass the truncate if the high bits are known zero.
14640 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14641 Cond = Cond.getOperand(0);
14643 // We know the result of AND is compared against zero. Try to match
14645 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14646 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14647 if (NewSetCC.getNode()) {
14648 CC = NewSetCC.getOperand(0);
14649 Cond = NewSetCC.getOperand(1);
14656 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14657 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14660 // a < b ? -1 : 0 -> RES = ~setcc_carry
14661 // a < b ? 0 : -1 -> RES = setcc_carry
14662 // a >= b ? -1 : 0 -> RES = setcc_carry
14663 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14664 if (Cond.getOpcode() == X86ISD::SUB) {
14665 Cond = ConvertCmpIfNecessary(Cond, DAG);
14666 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14668 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14669 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14670 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14671 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14672 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14673 return DAG.getNOT(DL, Res, Res.getValueType());
14678 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14679 // widen the cmov and push the truncate through. This avoids introducing a new
14680 // branch during isel and doesn't add any extensions.
14681 if (Op.getValueType() == MVT::i8 &&
14682 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14683 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14684 if (T1.getValueType() == T2.getValueType() &&
14685 // Blacklist CopyFromReg to avoid partial register stalls.
14686 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14687 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14688 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14689 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14693 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14694 // condition is true.
14695 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14696 SDValue Ops[] = { Op2, Op1, CC, Cond };
14697 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14700 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14701 MVT VT = Op->getSimpleValueType(0);
14702 SDValue In = Op->getOperand(0);
14703 MVT InVT = In.getSimpleValueType();
14706 unsigned int NumElts = VT.getVectorNumElements();
14707 if (NumElts != 8 && NumElts != 16)
14710 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14711 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14714 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14716 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14717 Constant *C = ConstantInt::get(*DAG.getContext(),
14718 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14720 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14721 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14722 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14723 MachinePointerInfo::getConstantPool(),
14724 false, false, false, Alignment);
14725 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14726 if (VT.is512BitVector())
14728 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14731 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14732 SelectionDAG &DAG) {
14733 MVT VT = Op->getSimpleValueType(0);
14734 SDValue In = Op->getOperand(0);
14735 MVT InVT = In.getSimpleValueType();
14738 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14739 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14741 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14742 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14743 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14746 if (Subtarget->hasInt256())
14747 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14749 // Optimize vectors in AVX mode
14750 // Sign extend v8i16 to v8i32 and
14753 // Divide input vector into two parts
14754 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14755 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14756 // concat the vectors to original VT
14758 unsigned NumElems = InVT.getVectorNumElements();
14759 SDValue Undef = DAG.getUNDEF(InVT);
14761 SmallVector<int,8> ShufMask1(NumElems, -1);
14762 for (unsigned i = 0; i != NumElems/2; ++i)
14765 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14767 SmallVector<int,8> ShufMask2(NumElems, -1);
14768 for (unsigned i = 0; i != NumElems/2; ++i)
14769 ShufMask2[i] = i + NumElems/2;
14771 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14773 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14774 VT.getVectorNumElements()/2);
14776 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14777 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14779 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14782 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14783 // may emit an illegal shuffle but the expansion is still better than scalar
14784 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14785 // we'll emit a shuffle and a arithmetic shift.
14786 // TODO: It is possible to support ZExt by zeroing the undef values during
14787 // the shuffle phase or after the shuffle.
14788 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14789 SelectionDAG &DAG) {
14790 MVT RegVT = Op.getSimpleValueType();
14791 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14792 assert(RegVT.isInteger() &&
14793 "We only custom lower integer vector sext loads.");
14795 // Nothing useful we can do without SSE2 shuffles.
14796 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14798 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14800 EVT MemVT = Ld->getMemoryVT();
14801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14802 unsigned RegSz = RegVT.getSizeInBits();
14804 ISD::LoadExtType Ext = Ld->getExtensionType();
14806 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14807 && "Only anyext and sext are currently implemented.");
14808 assert(MemVT != RegVT && "Cannot extend to the same type");
14809 assert(MemVT.isVector() && "Must load a vector from memory");
14811 unsigned NumElems = RegVT.getVectorNumElements();
14812 unsigned MemSz = MemVT.getSizeInBits();
14813 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14815 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14816 // The only way in which we have a legal 256-bit vector result but not the
14817 // integer 256-bit operations needed to directly lower a sextload is if we
14818 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14819 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14820 // correctly legalized. We do this late to allow the canonical form of
14821 // sextload to persist throughout the rest of the DAG combiner -- it wants
14822 // to fold together any extensions it can, and so will fuse a sign_extend
14823 // of an sextload into a sextload targeting a wider value.
14825 if (MemSz == 128) {
14826 // Just switch this to a normal load.
14827 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14828 "it must be a legal 128-bit vector "
14830 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14831 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14832 Ld->isInvariant(), Ld->getAlignment());
14834 assert(MemSz < 128 &&
14835 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14836 // Do an sext load to a 128-bit vector type. We want to use the same
14837 // number of elements, but elements half as wide. This will end up being
14838 // recursively lowered by this routine, but will succeed as we definitely
14839 // have all the necessary features if we're using AVX1.
14841 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14842 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14844 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14845 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14846 Ld->isNonTemporal(), Ld->isInvariant(),
14847 Ld->getAlignment());
14850 // Replace chain users with the new chain.
14851 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14852 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14854 // Finally, do a normal sign-extend to the desired register.
14855 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14858 // All sizes must be a power of two.
14859 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14860 "Non-power-of-two elements are not custom lowered!");
14862 // Attempt to load the original value using scalar loads.
14863 // Find the largest scalar type that divides the total loaded size.
14864 MVT SclrLoadTy = MVT::i8;
14865 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14866 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14867 MVT Tp = (MVT::SimpleValueType)tp;
14868 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14873 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14874 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14876 SclrLoadTy = MVT::f64;
14878 // Calculate the number of scalar loads that we need to perform
14879 // in order to load our vector from memory.
14880 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14882 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14883 "Can only lower sext loads with a single scalar load!");
14885 unsigned loadRegZize = RegSz;
14886 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14889 // Represent our vector as a sequence of elements which are the
14890 // largest scalar that we can load.
14891 EVT LoadUnitVecVT = EVT::getVectorVT(
14892 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14894 // Represent the data using the same element type that is stored in
14895 // memory. In practice, we ''widen'' MemVT.
14897 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14898 loadRegZize / MemVT.getScalarType().getSizeInBits());
14900 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14901 "Invalid vector type");
14903 // We can't shuffle using an illegal type.
14904 assert(TLI.isTypeLegal(WideVecVT) &&
14905 "We only lower types that form legal widened vector types");
14907 SmallVector<SDValue, 8> Chains;
14908 SDValue Ptr = Ld->getBasePtr();
14909 SDValue Increment =
14910 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14911 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14913 for (unsigned i = 0; i < NumLoads; ++i) {
14914 // Perform a single load.
14915 SDValue ScalarLoad =
14916 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14917 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14918 Ld->getAlignment());
14919 Chains.push_back(ScalarLoad.getValue(1));
14920 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14921 // another round of DAGCombining.
14923 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14925 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14926 ScalarLoad, DAG.getIntPtrConstant(i));
14928 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14931 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14933 // Bitcast the loaded value to a vector of the original element type, in
14934 // the size of the target vector type.
14935 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14936 unsigned SizeRatio = RegSz / MemSz;
14938 if (Ext == ISD::SEXTLOAD) {
14939 // If we have SSE4.1, we can directly emit a VSEXT node.
14940 if (Subtarget->hasSSE41()) {
14941 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14942 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14946 // Otherwise we'll shuffle the small elements in the high bits of the
14947 // larger type and perform an arithmetic shift. If the shift is not legal
14948 // it's better to scalarize.
14949 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14950 "We can't implement a sext load without an arithmetic right shift!");
14952 // Redistribute the loaded elements into the different locations.
14953 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14954 for (unsigned i = 0; i != NumElems; ++i)
14955 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14957 SDValue Shuff = DAG.getVectorShuffle(
14958 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14960 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14962 // Build the arithmetic shift.
14963 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14964 MemVT.getVectorElementType().getSizeInBits();
14966 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14968 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14972 // Redistribute the loaded elements into the different locations.
14973 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14974 for (unsigned i = 0; i != NumElems; ++i)
14975 ShuffleVec[i * SizeRatio] = i;
14977 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14978 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14980 // Bitcast to the requested type.
14981 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14982 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14986 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14987 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14988 // from the AND / OR.
14989 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14990 Opc = Op.getOpcode();
14991 if (Opc != ISD::OR && Opc != ISD::AND)
14993 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14994 Op.getOperand(0).hasOneUse() &&
14995 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14996 Op.getOperand(1).hasOneUse());
14999 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15000 // 1 and that the SETCC node has a single use.
15001 static bool isXor1OfSetCC(SDValue Op) {
15002 if (Op.getOpcode() != ISD::XOR)
15004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15005 if (N1C && N1C->getAPIntValue() == 1) {
15006 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15007 Op.getOperand(0).hasOneUse();
15012 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15013 bool addTest = true;
15014 SDValue Chain = Op.getOperand(0);
15015 SDValue Cond = Op.getOperand(1);
15016 SDValue Dest = Op.getOperand(2);
15019 bool Inverted = false;
15021 if (Cond.getOpcode() == ISD::SETCC) {
15022 // Check for setcc([su]{add,sub,mul}o == 0).
15023 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15024 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15025 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15026 Cond.getOperand(0).getResNo() == 1 &&
15027 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15028 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15029 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15030 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15031 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15032 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15034 Cond = Cond.getOperand(0);
15036 SDValue NewCond = LowerSETCC(Cond, DAG);
15037 if (NewCond.getNode())
15042 // FIXME: LowerXALUO doesn't handle these!!
15043 else if (Cond.getOpcode() == X86ISD::ADD ||
15044 Cond.getOpcode() == X86ISD::SUB ||
15045 Cond.getOpcode() == X86ISD::SMUL ||
15046 Cond.getOpcode() == X86ISD::UMUL)
15047 Cond = LowerXALUO(Cond, DAG);
15050 // Look pass (and (setcc_carry (cmp ...)), 1).
15051 if (Cond.getOpcode() == ISD::AND &&
15052 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15054 if (C && C->getAPIntValue() == 1)
15055 Cond = Cond.getOperand(0);
15058 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15059 // setting operand in place of the X86ISD::SETCC.
15060 unsigned CondOpcode = Cond.getOpcode();
15061 if (CondOpcode == X86ISD::SETCC ||
15062 CondOpcode == X86ISD::SETCC_CARRY) {
15063 CC = Cond.getOperand(0);
15065 SDValue Cmp = Cond.getOperand(1);
15066 unsigned Opc = Cmp.getOpcode();
15067 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15068 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15072 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15076 // These can only come from an arithmetic instruction with overflow,
15077 // e.g. SADDO, UADDO.
15078 Cond = Cond.getNode()->getOperand(1);
15084 CondOpcode = Cond.getOpcode();
15085 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15086 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15087 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15088 Cond.getOperand(0).getValueType() != MVT::i8)) {
15089 SDValue LHS = Cond.getOperand(0);
15090 SDValue RHS = Cond.getOperand(1);
15091 unsigned X86Opcode;
15094 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15095 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15097 switch (CondOpcode) {
15098 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15102 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15105 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15106 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15110 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15113 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15114 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15115 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15116 default: llvm_unreachable("unexpected overflowing operator");
15119 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15120 if (CondOpcode == ISD::UMULO)
15121 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15124 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15126 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15128 if (CondOpcode == ISD::UMULO)
15129 Cond = X86Op.getValue(2);
15131 Cond = X86Op.getValue(1);
15133 CC = DAG.getConstant(X86Cond, MVT::i8);
15137 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15138 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15139 if (CondOpc == ISD::OR) {
15140 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15141 // two branches instead of an explicit OR instruction with a
15143 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15144 isX86LogicalCmp(Cmp)) {
15145 CC = Cond.getOperand(0).getOperand(0);
15146 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15147 Chain, Dest, CC, Cmp);
15148 CC = Cond.getOperand(1).getOperand(0);
15152 } else { // ISD::AND
15153 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15154 // two branches instead of an explicit AND instruction with a
15155 // separate test. However, we only do this if this block doesn't
15156 // have a fall-through edge, because this requires an explicit
15157 // jmp when the condition is false.
15158 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15159 isX86LogicalCmp(Cmp) &&
15160 Op.getNode()->hasOneUse()) {
15161 X86::CondCode CCode =
15162 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15163 CCode = X86::GetOppositeBranchCondition(CCode);
15164 CC = DAG.getConstant(CCode, MVT::i8);
15165 SDNode *User = *Op.getNode()->use_begin();
15166 // Look for an unconditional branch following this conditional branch.
15167 // We need this because we need to reverse the successors in order
15168 // to implement FCMP_OEQ.
15169 if (User->getOpcode() == ISD::BR) {
15170 SDValue FalseBB = User->getOperand(1);
15172 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15173 assert(NewBR == User);
15177 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15178 Chain, Dest, CC, Cmp);
15179 X86::CondCode CCode =
15180 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15181 CCode = X86::GetOppositeBranchCondition(CCode);
15182 CC = DAG.getConstant(CCode, MVT::i8);
15188 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15189 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15190 // It should be transformed during dag combiner except when the condition
15191 // is set by a arithmetics with overflow node.
15192 X86::CondCode CCode =
15193 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15194 CCode = X86::GetOppositeBranchCondition(CCode);
15195 CC = DAG.getConstant(CCode, MVT::i8);
15196 Cond = Cond.getOperand(0).getOperand(1);
15198 } else if (Cond.getOpcode() == ISD::SETCC &&
15199 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15200 // For FCMP_OEQ, we can emit
15201 // two branches instead of an explicit AND instruction with a
15202 // separate test. However, we only do this if this block doesn't
15203 // have a fall-through edge, because this requires an explicit
15204 // jmp when the condition is false.
15205 if (Op.getNode()->hasOneUse()) {
15206 SDNode *User = *Op.getNode()->use_begin();
15207 // Look for an unconditional branch following this conditional branch.
15208 // We need this because we need to reverse the successors in order
15209 // to implement FCMP_OEQ.
15210 if (User->getOpcode() == ISD::BR) {
15211 SDValue FalseBB = User->getOperand(1);
15213 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15214 assert(NewBR == User);
15218 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15219 Cond.getOperand(0), Cond.getOperand(1));
15220 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15221 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15222 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15223 Chain, Dest, CC, Cmp);
15224 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15229 } else if (Cond.getOpcode() == ISD::SETCC &&
15230 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15231 // For FCMP_UNE, we can emit
15232 // two branches instead of an explicit AND instruction with a
15233 // separate test. However, we only do this if this block doesn't
15234 // have a fall-through edge, because this requires an explicit
15235 // jmp when the condition is false.
15236 if (Op.getNode()->hasOneUse()) {
15237 SDNode *User = *Op.getNode()->use_begin();
15238 // Look for an unconditional branch following this conditional branch.
15239 // We need this because we need to reverse the successors in order
15240 // to implement FCMP_UNE.
15241 if (User->getOpcode() == ISD::BR) {
15242 SDValue FalseBB = User->getOperand(1);
15244 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15245 assert(NewBR == User);
15248 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15249 Cond.getOperand(0), Cond.getOperand(1));
15250 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15251 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15252 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15253 Chain, Dest, CC, Cmp);
15254 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15264 // Look pass the truncate if the high bits are known zero.
15265 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15266 Cond = Cond.getOperand(0);
15268 // We know the result of AND is compared against zero. Try to match
15270 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15271 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15272 if (NewSetCC.getNode()) {
15273 CC = NewSetCC.getOperand(0);
15274 Cond = NewSetCC.getOperand(1);
15281 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15282 CC = DAG.getConstant(X86Cond, MVT::i8);
15283 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15285 Cond = ConvertCmpIfNecessary(Cond, DAG);
15286 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15287 Chain, Dest, CC, Cond);
15290 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15291 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15292 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15293 // that the guard pages used by the OS virtual memory manager are allocated in
15294 // correct sequence.
15296 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15297 SelectionDAG &DAG) const {
15298 MachineFunction &MF = DAG.getMachineFunction();
15299 bool SplitStack = MF.shouldSplitStack();
15300 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15306 SDNode* Node = Op.getNode();
15308 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15309 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15310 " not tell us which reg is the stack pointer!");
15311 EVT VT = Node->getValueType(0);
15312 SDValue Tmp1 = SDValue(Node, 0);
15313 SDValue Tmp2 = SDValue(Node, 1);
15314 SDValue Tmp3 = Node->getOperand(2);
15315 SDValue Chain = Tmp1.getOperand(0);
15317 // Chain the dynamic stack allocation so that it doesn't modify the stack
15318 // pointer when other instructions are using the stack.
15319 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15322 SDValue Size = Tmp2.getOperand(1);
15323 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15324 Chain = SP.getValue(1);
15325 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15326 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15327 unsigned StackAlign = TFI.getStackAlignment();
15328 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15329 if (Align > StackAlign)
15330 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15331 DAG.getConstant(-(uint64_t)Align, VT));
15332 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15334 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15335 DAG.getIntPtrConstant(0, true), SDValue(),
15338 SDValue Ops[2] = { Tmp1, Tmp2 };
15339 return DAG.getMergeValues(Ops, dl);
15343 SDValue Chain = Op.getOperand(0);
15344 SDValue Size = Op.getOperand(1);
15345 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15346 EVT VT = Op.getNode()->getValueType(0);
15348 bool Is64Bit = Subtarget->is64Bit();
15349 EVT SPTy = getPointerTy();
15352 MachineRegisterInfo &MRI = MF.getRegInfo();
15355 // The 64 bit implementation of segmented stacks needs to clobber both r10
15356 // r11. This makes it impossible to use it along with nested parameters.
15357 const Function *F = MF.getFunction();
15359 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15361 if (I->hasNestAttr())
15362 report_fatal_error("Cannot use segmented stacks with functions that "
15363 "have nested arguments.");
15366 const TargetRegisterClass *AddrRegClass =
15367 getRegClassFor(getPointerTy());
15368 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15369 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15370 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15371 DAG.getRegister(Vreg, SPTy));
15372 SDValue Ops1[2] = { Value, Chain };
15373 return DAG.getMergeValues(Ops1, dl);
15376 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15378 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15379 Flag = Chain.getValue(1);
15380 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15382 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15384 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15385 DAG.getSubtarget().getRegisterInfo());
15386 unsigned SPReg = RegInfo->getStackRegister();
15387 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15388 Chain = SP.getValue(1);
15391 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15392 DAG.getConstant(-(uint64_t)Align, VT));
15393 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15396 SDValue Ops1[2] = { SP, Chain };
15397 return DAG.getMergeValues(Ops1, dl);
15401 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15402 MachineFunction &MF = DAG.getMachineFunction();
15403 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15408 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15409 // vastart just stores the address of the VarArgsFrameIndex slot into the
15410 // memory location argument.
15411 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15413 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15414 MachinePointerInfo(SV), false, false, 0);
15418 // gp_offset (0 - 6 * 8)
15419 // fp_offset (48 - 48 + 8 * 16)
15420 // overflow_arg_area (point to parameters coming in memory).
15422 SmallVector<SDValue, 8> MemOps;
15423 SDValue FIN = Op.getOperand(1);
15425 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15426 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15428 FIN, MachinePointerInfo(SV), false, false, 0);
15429 MemOps.push_back(Store);
15432 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15433 FIN, DAG.getIntPtrConstant(4));
15434 Store = DAG.getStore(Op.getOperand(0), DL,
15435 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15437 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15438 MemOps.push_back(Store);
15440 // Store ptr to overflow_arg_area
15441 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15442 FIN, DAG.getIntPtrConstant(4));
15443 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15445 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15446 MachinePointerInfo(SV, 8),
15448 MemOps.push_back(Store);
15450 // Store ptr to reg_save_area.
15451 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15452 FIN, DAG.getIntPtrConstant(8));
15453 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15455 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15456 MachinePointerInfo(SV, 16), false, false, 0);
15457 MemOps.push_back(Store);
15458 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15461 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15462 assert(Subtarget->is64Bit() &&
15463 "LowerVAARG only handles 64-bit va_arg!");
15464 assert((Subtarget->isTargetLinux() ||
15465 Subtarget->isTargetDarwin()) &&
15466 "Unhandled target in LowerVAARG");
15467 assert(Op.getNode()->getNumOperands() == 4);
15468 SDValue Chain = Op.getOperand(0);
15469 SDValue SrcPtr = Op.getOperand(1);
15470 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15471 unsigned Align = Op.getConstantOperandVal(3);
15474 EVT ArgVT = Op.getNode()->getValueType(0);
15475 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15476 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15479 // Decide which area this value should be read from.
15480 // TODO: Implement the AMD64 ABI in its entirety. This simple
15481 // selection mechanism works only for the basic types.
15482 if (ArgVT == MVT::f80) {
15483 llvm_unreachable("va_arg for f80 not yet implemented");
15484 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15485 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15486 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15487 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15489 llvm_unreachable("Unhandled argument type in LowerVAARG");
15492 if (ArgMode == 2) {
15493 // Sanity Check: Make sure using fp_offset makes sense.
15494 assert(!DAG.getTarget().Options.UseSoftFloat &&
15495 !(DAG.getMachineFunction()
15496 .getFunction()->getAttributes()
15497 .hasAttribute(AttributeSet::FunctionIndex,
15498 Attribute::NoImplicitFloat)) &&
15499 Subtarget->hasSSE1());
15502 // Insert VAARG_64 node into the DAG
15503 // VAARG_64 returns two values: Variable Argument Address, Chain
15504 SmallVector<SDValue, 11> InstOps;
15505 InstOps.push_back(Chain);
15506 InstOps.push_back(SrcPtr);
15507 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15508 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15509 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15510 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15511 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15512 VTs, InstOps, MVT::i64,
15513 MachinePointerInfo(SV),
15515 /*Volatile=*/false,
15517 /*WriteMem=*/true);
15518 Chain = VAARG.getValue(1);
15520 // Load the next argument and return it
15521 return DAG.getLoad(ArgVT, dl,
15524 MachinePointerInfo(),
15525 false, false, false, 0);
15528 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15529 SelectionDAG &DAG) {
15530 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15531 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15532 SDValue Chain = Op.getOperand(0);
15533 SDValue DstPtr = Op.getOperand(1);
15534 SDValue SrcPtr = Op.getOperand(2);
15535 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15536 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15539 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15540 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15542 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15545 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15546 // amount is a constant. Takes immediate version of shift as input.
15547 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15548 SDValue SrcOp, uint64_t ShiftAmt,
15549 SelectionDAG &DAG) {
15550 MVT ElementType = VT.getVectorElementType();
15552 // Fold this packed shift into its first operand if ShiftAmt is 0.
15556 // Check for ShiftAmt >= element width
15557 if (ShiftAmt >= ElementType.getSizeInBits()) {
15558 if (Opc == X86ISD::VSRAI)
15559 ShiftAmt = ElementType.getSizeInBits() - 1;
15561 return DAG.getConstant(0, VT);
15564 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15565 && "Unknown target vector shift-by-constant node");
15567 // Fold this packed vector shift into a build vector if SrcOp is a
15568 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15569 if (VT == SrcOp.getSimpleValueType() &&
15570 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15571 SmallVector<SDValue, 8> Elts;
15572 unsigned NumElts = SrcOp->getNumOperands();
15573 ConstantSDNode *ND;
15576 default: llvm_unreachable(nullptr);
15577 case X86ISD::VSHLI:
15578 for (unsigned i=0; i!=NumElts; ++i) {
15579 SDValue CurrentOp = SrcOp->getOperand(i);
15580 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15581 Elts.push_back(CurrentOp);
15584 ND = cast<ConstantSDNode>(CurrentOp);
15585 const APInt &C = ND->getAPIntValue();
15586 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15589 case X86ISD::VSRLI:
15590 for (unsigned i=0; i!=NumElts; ++i) {
15591 SDValue CurrentOp = SrcOp->getOperand(i);
15592 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15593 Elts.push_back(CurrentOp);
15596 ND = cast<ConstantSDNode>(CurrentOp);
15597 const APInt &C = ND->getAPIntValue();
15598 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15601 case X86ISD::VSRAI:
15602 for (unsigned i=0; i!=NumElts; ++i) {
15603 SDValue CurrentOp = SrcOp->getOperand(i);
15604 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15605 Elts.push_back(CurrentOp);
15608 ND = cast<ConstantSDNode>(CurrentOp);
15609 const APInt &C = ND->getAPIntValue();
15610 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15615 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15618 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15621 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15622 // may or may not be a constant. Takes immediate version of shift as input.
15623 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15624 SDValue SrcOp, SDValue ShAmt,
15625 SelectionDAG &DAG) {
15626 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15628 // Catch shift-by-constant.
15629 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15630 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15631 CShAmt->getZExtValue(), DAG);
15633 // Change opcode to non-immediate version
15635 default: llvm_unreachable("Unknown target vector shift node");
15636 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15637 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15638 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15641 // Need to build a vector containing shift amount
15642 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15645 ShOps[1] = DAG.getConstant(0, MVT::i32);
15646 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15647 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15649 // The return type has to be a 128-bit type with the same element
15650 // type as the input type.
15651 MVT EltVT = VT.getVectorElementType();
15652 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15654 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15655 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15658 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15659 /// necessary casting for \p Mask when lowering masking intrinsics.
15660 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15661 SDValue PreservedSrc, SelectionDAG &DAG) {
15662 EVT VT = Op.getValueType();
15663 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15664 MVT::i1, VT.getVectorNumElements());
15667 assert(MaskVT.isSimple() && "invalid mask type");
15668 return DAG.getNode(ISD::VSELECT, dl, VT,
15669 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15673 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15675 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15676 case Intrinsic::x86_fma_vfmadd_ps:
15677 case Intrinsic::x86_fma_vfmadd_pd:
15678 case Intrinsic::x86_fma_vfmadd_ps_256:
15679 case Intrinsic::x86_fma_vfmadd_pd_256:
15680 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15681 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15682 return X86ISD::FMADD;
15683 case Intrinsic::x86_fma_vfmsub_ps:
15684 case Intrinsic::x86_fma_vfmsub_pd:
15685 case Intrinsic::x86_fma_vfmsub_ps_256:
15686 case Intrinsic::x86_fma_vfmsub_pd_256:
15687 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15688 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15689 return X86ISD::FMSUB;
15690 case Intrinsic::x86_fma_vfnmadd_ps:
15691 case Intrinsic::x86_fma_vfnmadd_pd:
15692 case Intrinsic::x86_fma_vfnmadd_ps_256:
15693 case Intrinsic::x86_fma_vfnmadd_pd_256:
15694 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15695 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15696 return X86ISD::FNMADD;
15697 case Intrinsic::x86_fma_vfnmsub_ps:
15698 case Intrinsic::x86_fma_vfnmsub_pd:
15699 case Intrinsic::x86_fma_vfnmsub_ps_256:
15700 case Intrinsic::x86_fma_vfnmsub_pd_256:
15701 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15702 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15703 return X86ISD::FNMSUB;
15704 case Intrinsic::x86_fma_vfmaddsub_ps:
15705 case Intrinsic::x86_fma_vfmaddsub_pd:
15706 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15707 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15708 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15709 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15710 return X86ISD::FMADDSUB;
15711 case Intrinsic::x86_fma_vfmsubadd_ps:
15712 case Intrinsic::x86_fma_vfmsubadd_pd:
15713 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15714 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15715 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15716 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15717 return X86ISD::FMSUBADD;
15721 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15723 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15725 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15727 switch(IntrData->Type) {
15728 case INTR_TYPE_1OP:
15729 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15730 case INTR_TYPE_2OP:
15731 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15733 case INTR_TYPE_3OP:
15734 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15735 Op.getOperand(2), Op.getOperand(3));
15736 case COMI: { // Comparison intrinsics
15737 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15738 SDValue LHS = Op.getOperand(1);
15739 SDValue RHS = Op.getOperand(2);
15740 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15741 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15742 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15743 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15744 DAG.getConstant(X86CC, MVT::i8), Cond);
15745 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15748 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15749 Op.getOperand(1), Op.getOperand(2), DAG);
15756 default: return SDValue(); // Don't custom lower most intrinsics.
15758 // Arithmetic intrinsics.
15759 case Intrinsic::x86_sse2_pmulu_dq:
15760 case Intrinsic::x86_avx2_pmulu_dq:
15761 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15762 Op.getOperand(1), Op.getOperand(2));
15764 case Intrinsic::x86_sse41_pmuldq:
15765 case Intrinsic::x86_avx2_pmul_dq:
15766 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15767 Op.getOperand(1), Op.getOperand(2));
15769 case Intrinsic::x86_sse2_pmulhu_w:
15770 case Intrinsic::x86_avx2_pmulhu_w:
15771 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15772 Op.getOperand(1), Op.getOperand(2));
15774 case Intrinsic::x86_sse2_pmulh_w:
15775 case Intrinsic::x86_avx2_pmulh_w:
15776 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15777 Op.getOperand(1), Op.getOperand(2));
15779 // SSE/SSE2/AVX floating point max/min intrinsics.
15780 case Intrinsic::x86_sse_max_ps:
15781 case Intrinsic::x86_sse2_max_pd:
15782 case Intrinsic::x86_avx_max_ps_256:
15783 case Intrinsic::x86_avx_max_pd_256:
15784 case Intrinsic::x86_sse_min_ps:
15785 case Intrinsic::x86_sse2_min_pd:
15786 case Intrinsic::x86_avx_min_ps_256:
15787 case Intrinsic::x86_avx_min_pd_256: {
15790 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15791 case Intrinsic::x86_sse_max_ps:
15792 case Intrinsic::x86_sse2_max_pd:
15793 case Intrinsic::x86_avx_max_ps_256:
15794 case Intrinsic::x86_avx_max_pd_256:
15795 Opcode = X86ISD::FMAX;
15797 case Intrinsic::x86_sse_min_ps:
15798 case Intrinsic::x86_sse2_min_pd:
15799 case Intrinsic::x86_avx_min_ps_256:
15800 case Intrinsic::x86_avx_min_pd_256:
15801 Opcode = X86ISD::FMIN;
15804 return DAG.getNode(Opcode, dl, Op.getValueType(),
15805 Op.getOperand(1), Op.getOperand(2));
15808 // AVX2 variable shift intrinsics
15809 case Intrinsic::x86_avx2_psllv_d:
15810 case Intrinsic::x86_avx2_psllv_q:
15811 case Intrinsic::x86_avx2_psllv_d_256:
15812 case Intrinsic::x86_avx2_psllv_q_256:
15813 case Intrinsic::x86_avx2_psrlv_d:
15814 case Intrinsic::x86_avx2_psrlv_q:
15815 case Intrinsic::x86_avx2_psrlv_d_256:
15816 case Intrinsic::x86_avx2_psrlv_q_256:
15817 case Intrinsic::x86_avx2_psrav_d:
15818 case Intrinsic::x86_avx2_psrav_d_256: {
15821 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15822 case Intrinsic::x86_avx2_psllv_d:
15823 case Intrinsic::x86_avx2_psllv_q:
15824 case Intrinsic::x86_avx2_psllv_d_256:
15825 case Intrinsic::x86_avx2_psllv_q_256:
15828 case Intrinsic::x86_avx2_psrlv_d:
15829 case Intrinsic::x86_avx2_psrlv_q:
15830 case Intrinsic::x86_avx2_psrlv_d_256:
15831 case Intrinsic::x86_avx2_psrlv_q_256:
15834 case Intrinsic::x86_avx2_psrav_d:
15835 case Intrinsic::x86_avx2_psrav_d_256:
15839 return DAG.getNode(Opcode, dl, Op.getValueType(),
15840 Op.getOperand(1), Op.getOperand(2));
15843 case Intrinsic::x86_sse2_packssdw_128:
15844 case Intrinsic::x86_sse2_packsswb_128:
15845 case Intrinsic::x86_avx2_packssdw:
15846 case Intrinsic::x86_avx2_packsswb:
15847 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15848 Op.getOperand(1), Op.getOperand(2));
15850 case Intrinsic::x86_sse2_packuswb_128:
15851 case Intrinsic::x86_sse41_packusdw:
15852 case Intrinsic::x86_avx2_packuswb:
15853 case Intrinsic::x86_avx2_packusdw:
15854 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15855 Op.getOperand(1), Op.getOperand(2));
15857 case Intrinsic::x86_ssse3_pshuf_b_128:
15858 case Intrinsic::x86_avx2_pshuf_b:
15859 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15860 Op.getOperand(1), Op.getOperand(2));
15862 case Intrinsic::x86_sse2_pshuf_d:
15863 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15864 Op.getOperand(1), Op.getOperand(2));
15866 case Intrinsic::x86_sse2_pshufl_w:
15867 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15868 Op.getOperand(1), Op.getOperand(2));
15870 case Intrinsic::x86_sse2_pshufh_w:
15871 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15872 Op.getOperand(1), Op.getOperand(2));
15874 case Intrinsic::x86_ssse3_psign_b_128:
15875 case Intrinsic::x86_ssse3_psign_w_128:
15876 case Intrinsic::x86_ssse3_psign_d_128:
15877 case Intrinsic::x86_avx2_psign_b:
15878 case Intrinsic::x86_avx2_psign_w:
15879 case Intrinsic::x86_avx2_psign_d:
15880 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15881 Op.getOperand(1), Op.getOperand(2));
15883 case Intrinsic::x86_avx2_permd:
15884 case Intrinsic::x86_avx2_permps:
15885 // Operands intentionally swapped. Mask is last operand to intrinsic,
15886 // but second operand for node/instruction.
15887 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15888 Op.getOperand(2), Op.getOperand(1));
15890 case Intrinsic::x86_avx512_mask_valign_q_512:
15891 case Intrinsic::x86_avx512_mask_valign_d_512:
15892 // Vector source operands are swapped.
15893 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15894 Op.getValueType(), Op.getOperand(2),
15897 Op.getOperand(5), Op.getOperand(4), DAG);
15899 // ptest and testp intrinsics. The intrinsic these come from are designed to
15900 // return an integer value, not just an instruction so lower it to the ptest
15901 // or testp pattern and a setcc for the result.
15902 case Intrinsic::x86_sse41_ptestz:
15903 case Intrinsic::x86_sse41_ptestc:
15904 case Intrinsic::x86_sse41_ptestnzc:
15905 case Intrinsic::x86_avx_ptestz_256:
15906 case Intrinsic::x86_avx_ptestc_256:
15907 case Intrinsic::x86_avx_ptestnzc_256:
15908 case Intrinsic::x86_avx_vtestz_ps:
15909 case Intrinsic::x86_avx_vtestc_ps:
15910 case Intrinsic::x86_avx_vtestnzc_ps:
15911 case Intrinsic::x86_avx_vtestz_pd:
15912 case Intrinsic::x86_avx_vtestc_pd:
15913 case Intrinsic::x86_avx_vtestnzc_pd:
15914 case Intrinsic::x86_avx_vtestz_ps_256:
15915 case Intrinsic::x86_avx_vtestc_ps_256:
15916 case Intrinsic::x86_avx_vtestnzc_ps_256:
15917 case Intrinsic::x86_avx_vtestz_pd_256:
15918 case Intrinsic::x86_avx_vtestc_pd_256:
15919 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15920 bool IsTestPacked = false;
15923 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15924 case Intrinsic::x86_avx_vtestz_ps:
15925 case Intrinsic::x86_avx_vtestz_pd:
15926 case Intrinsic::x86_avx_vtestz_ps_256:
15927 case Intrinsic::x86_avx_vtestz_pd_256:
15928 IsTestPacked = true; // Fallthrough
15929 case Intrinsic::x86_sse41_ptestz:
15930 case Intrinsic::x86_avx_ptestz_256:
15932 X86CC = X86::COND_E;
15934 case Intrinsic::x86_avx_vtestc_ps:
15935 case Intrinsic::x86_avx_vtestc_pd:
15936 case Intrinsic::x86_avx_vtestc_ps_256:
15937 case Intrinsic::x86_avx_vtestc_pd_256:
15938 IsTestPacked = true; // Fallthrough
15939 case Intrinsic::x86_sse41_ptestc:
15940 case Intrinsic::x86_avx_ptestc_256:
15942 X86CC = X86::COND_B;
15944 case Intrinsic::x86_avx_vtestnzc_ps:
15945 case Intrinsic::x86_avx_vtestnzc_pd:
15946 case Intrinsic::x86_avx_vtestnzc_ps_256:
15947 case Intrinsic::x86_avx_vtestnzc_pd_256:
15948 IsTestPacked = true; // Fallthrough
15949 case Intrinsic::x86_sse41_ptestnzc:
15950 case Intrinsic::x86_avx_ptestnzc_256:
15952 X86CC = X86::COND_A;
15956 SDValue LHS = Op.getOperand(1);
15957 SDValue RHS = Op.getOperand(2);
15958 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15959 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15960 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15961 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15962 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15964 case Intrinsic::x86_avx512_kortestz_w:
15965 case Intrinsic::x86_avx512_kortestc_w: {
15966 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15967 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15968 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15969 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15970 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15971 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15972 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15975 case Intrinsic::x86_sse42_pcmpistria128:
15976 case Intrinsic::x86_sse42_pcmpestria128:
15977 case Intrinsic::x86_sse42_pcmpistric128:
15978 case Intrinsic::x86_sse42_pcmpestric128:
15979 case Intrinsic::x86_sse42_pcmpistrio128:
15980 case Intrinsic::x86_sse42_pcmpestrio128:
15981 case Intrinsic::x86_sse42_pcmpistris128:
15982 case Intrinsic::x86_sse42_pcmpestris128:
15983 case Intrinsic::x86_sse42_pcmpistriz128:
15984 case Intrinsic::x86_sse42_pcmpestriz128: {
15988 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15989 case Intrinsic::x86_sse42_pcmpistria128:
15990 Opcode = X86ISD::PCMPISTRI;
15991 X86CC = X86::COND_A;
15993 case Intrinsic::x86_sse42_pcmpestria128:
15994 Opcode = X86ISD::PCMPESTRI;
15995 X86CC = X86::COND_A;
15997 case Intrinsic::x86_sse42_pcmpistric128:
15998 Opcode = X86ISD::PCMPISTRI;
15999 X86CC = X86::COND_B;
16001 case Intrinsic::x86_sse42_pcmpestric128:
16002 Opcode = X86ISD::PCMPESTRI;
16003 X86CC = X86::COND_B;
16005 case Intrinsic::x86_sse42_pcmpistrio128:
16006 Opcode = X86ISD::PCMPISTRI;
16007 X86CC = X86::COND_O;
16009 case Intrinsic::x86_sse42_pcmpestrio128:
16010 Opcode = X86ISD::PCMPESTRI;
16011 X86CC = X86::COND_O;
16013 case Intrinsic::x86_sse42_pcmpistris128:
16014 Opcode = X86ISD::PCMPISTRI;
16015 X86CC = X86::COND_S;
16017 case Intrinsic::x86_sse42_pcmpestris128:
16018 Opcode = X86ISD::PCMPESTRI;
16019 X86CC = X86::COND_S;
16021 case Intrinsic::x86_sse42_pcmpistriz128:
16022 Opcode = X86ISD::PCMPISTRI;
16023 X86CC = X86::COND_E;
16025 case Intrinsic::x86_sse42_pcmpestriz128:
16026 Opcode = X86ISD::PCMPESTRI;
16027 X86CC = X86::COND_E;
16030 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16031 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16032 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16033 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16034 DAG.getConstant(X86CC, MVT::i8),
16035 SDValue(PCMP.getNode(), 1));
16036 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16039 case Intrinsic::x86_sse42_pcmpistri128:
16040 case Intrinsic::x86_sse42_pcmpestri128: {
16042 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16043 Opcode = X86ISD::PCMPISTRI;
16045 Opcode = X86ISD::PCMPESTRI;
16047 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16048 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16049 return DAG.getNode(Opcode, dl, VTs, NewOps);
16052 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16053 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16054 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16055 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16056 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16057 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16058 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16059 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16060 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16061 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16062 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16063 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16064 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16065 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16066 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16067 dl, Op.getValueType(),
16071 Op.getOperand(4), Op.getOperand(1), DAG);
16076 case Intrinsic::x86_fma_vfmadd_ps:
16077 case Intrinsic::x86_fma_vfmadd_pd:
16078 case Intrinsic::x86_fma_vfmsub_ps:
16079 case Intrinsic::x86_fma_vfmsub_pd:
16080 case Intrinsic::x86_fma_vfnmadd_ps:
16081 case Intrinsic::x86_fma_vfnmadd_pd:
16082 case Intrinsic::x86_fma_vfnmsub_ps:
16083 case Intrinsic::x86_fma_vfnmsub_pd:
16084 case Intrinsic::x86_fma_vfmaddsub_ps:
16085 case Intrinsic::x86_fma_vfmaddsub_pd:
16086 case Intrinsic::x86_fma_vfmsubadd_ps:
16087 case Intrinsic::x86_fma_vfmsubadd_pd:
16088 case Intrinsic::x86_fma_vfmadd_ps_256:
16089 case Intrinsic::x86_fma_vfmadd_pd_256:
16090 case Intrinsic::x86_fma_vfmsub_ps_256:
16091 case Intrinsic::x86_fma_vfmsub_pd_256:
16092 case Intrinsic::x86_fma_vfnmadd_ps_256:
16093 case Intrinsic::x86_fma_vfnmadd_pd_256:
16094 case Intrinsic::x86_fma_vfnmsub_ps_256:
16095 case Intrinsic::x86_fma_vfnmsub_pd_256:
16096 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16097 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16098 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16099 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16100 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16101 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16105 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16106 SDValue Src, SDValue Mask, SDValue Base,
16107 SDValue Index, SDValue ScaleOp, SDValue Chain,
16108 const X86Subtarget * Subtarget) {
16110 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16111 assert(C && "Invalid scale type");
16112 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16113 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16114 Index.getSimpleValueType().getVectorNumElements());
16116 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16118 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16120 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16121 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16122 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16123 SDValue Segment = DAG.getRegister(0, MVT::i32);
16124 if (Src.getOpcode() == ISD::UNDEF)
16125 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16126 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16127 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16128 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16129 return DAG.getMergeValues(RetOps, dl);
16132 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16133 SDValue Src, SDValue Mask, SDValue Base,
16134 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16137 assert(C && "Invalid scale type");
16138 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16139 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16140 SDValue Segment = DAG.getRegister(0, MVT::i32);
16141 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16142 Index.getSimpleValueType().getVectorNumElements());
16144 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16146 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16148 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16149 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16150 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16151 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16152 return SDValue(Res, 1);
16155 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16156 SDValue Mask, SDValue Base, SDValue Index,
16157 SDValue ScaleOp, SDValue Chain) {
16159 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16160 assert(C && "Invalid scale type");
16161 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16162 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16163 SDValue Segment = DAG.getRegister(0, MVT::i32);
16165 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16167 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16169 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16171 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16172 //SDVTList VTs = DAG.getVTList(MVT::Other);
16173 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16174 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16175 return SDValue(Res, 0);
16178 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16179 // read performance monitor counters (x86_rdpmc).
16180 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16181 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16182 SmallVectorImpl<SDValue> &Results) {
16183 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16184 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16187 // The ECX register is used to select the index of the performance counter
16189 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16191 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16193 // Reads the content of a 64-bit performance counter and returns it in the
16194 // registers EDX:EAX.
16195 if (Subtarget->is64Bit()) {
16196 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16197 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16200 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16201 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16204 Chain = HI.getValue(1);
16206 if (Subtarget->is64Bit()) {
16207 // The EAX register is loaded with the low-order 32 bits. The EDX register
16208 // is loaded with the supported high-order bits of the counter.
16209 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16210 DAG.getConstant(32, MVT::i8));
16211 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16212 Results.push_back(Chain);
16216 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16217 SDValue Ops[] = { LO, HI };
16218 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16219 Results.push_back(Pair);
16220 Results.push_back(Chain);
16223 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16224 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16225 // also used to custom lower READCYCLECOUNTER nodes.
16226 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16227 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16228 SmallVectorImpl<SDValue> &Results) {
16229 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16230 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16233 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16234 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16235 // and the EAX register is loaded with the low-order 32 bits.
16236 if (Subtarget->is64Bit()) {
16237 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16238 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16241 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16242 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16245 SDValue Chain = HI.getValue(1);
16247 if (Opcode == X86ISD::RDTSCP_DAG) {
16248 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16250 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16251 // the ECX register. Add 'ecx' explicitly to the chain.
16252 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16254 // Explicitly store the content of ECX at the location passed in input
16255 // to the 'rdtscp' intrinsic.
16256 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16257 MachinePointerInfo(), false, false, 0);
16260 if (Subtarget->is64Bit()) {
16261 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16262 // the EAX register is loaded with the low-order 32 bits.
16263 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16264 DAG.getConstant(32, MVT::i8));
16265 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16266 Results.push_back(Chain);
16270 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16271 SDValue Ops[] = { LO, HI };
16272 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16273 Results.push_back(Pair);
16274 Results.push_back(Chain);
16277 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16278 SelectionDAG &DAG) {
16279 SmallVector<SDValue, 2> Results;
16281 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16283 return DAG.getMergeValues(Results, DL);
16287 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16288 SelectionDAG &DAG) {
16289 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16291 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16296 switch(IntrData->Type) {
16298 llvm_unreachable("Unknown Intrinsic Type");
16302 // Emit the node with the right value type.
16303 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16304 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16306 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16307 // Otherwise return the value from Rand, which is always 0, casted to i32.
16308 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16309 DAG.getConstant(1, Op->getValueType(1)),
16310 DAG.getConstant(X86::COND_B, MVT::i32),
16311 SDValue(Result.getNode(), 1) };
16312 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16313 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16316 // Return { result, isValid, chain }.
16317 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16318 SDValue(Result.getNode(), 2));
16321 //gather(v1, mask, index, base, scale);
16322 SDValue Chain = Op.getOperand(0);
16323 SDValue Src = Op.getOperand(2);
16324 SDValue Base = Op.getOperand(3);
16325 SDValue Index = Op.getOperand(4);
16326 SDValue Mask = Op.getOperand(5);
16327 SDValue Scale = Op.getOperand(6);
16328 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16332 //scatter(base, mask, index, v1, scale);
16333 SDValue Chain = Op.getOperand(0);
16334 SDValue Base = Op.getOperand(2);
16335 SDValue Mask = Op.getOperand(3);
16336 SDValue Index = Op.getOperand(4);
16337 SDValue Src = Op.getOperand(5);
16338 SDValue Scale = Op.getOperand(6);
16339 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16342 SDValue Hint = Op.getOperand(6);
16344 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16345 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16346 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16347 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16348 SDValue Chain = Op.getOperand(0);
16349 SDValue Mask = Op.getOperand(2);
16350 SDValue Index = Op.getOperand(3);
16351 SDValue Base = Op.getOperand(4);
16352 SDValue Scale = Op.getOperand(5);
16353 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16355 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16357 SmallVector<SDValue, 2> Results;
16358 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16359 return DAG.getMergeValues(Results, dl);
16361 // Read Performance Monitoring Counters.
16363 SmallVector<SDValue, 2> Results;
16364 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16365 return DAG.getMergeValues(Results, dl);
16367 // XTEST intrinsics.
16369 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16370 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16371 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16372 DAG.getConstant(X86::COND_NE, MVT::i8),
16374 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16375 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16376 Ret, SDValue(InTrans.getNode(), 1));
16380 SmallVector<SDValue, 2> Results;
16381 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16382 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16383 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16384 DAG.getConstant(-1, MVT::i8));
16385 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16386 Op.getOperand(4), GenCF.getValue(1));
16387 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16388 Op.getOperand(5), MachinePointerInfo(),
16390 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16391 DAG.getConstant(X86::COND_B, MVT::i8),
16393 Results.push_back(SetCC);
16394 Results.push_back(Store);
16395 return DAG.getMergeValues(Results, dl);
16400 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16401 SelectionDAG &DAG) const {
16402 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16403 MFI->setReturnAddressIsTaken(true);
16405 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16408 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16410 EVT PtrVT = getPointerTy();
16413 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16414 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16415 DAG.getSubtarget().getRegisterInfo());
16416 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16417 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16418 DAG.getNode(ISD::ADD, dl, PtrVT,
16419 FrameAddr, Offset),
16420 MachinePointerInfo(), false, false, false, 0);
16423 // Just load the return address.
16424 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16425 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16426 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16429 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16430 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16431 MFI->setFrameAddressIsTaken(true);
16433 EVT VT = Op.getValueType();
16434 SDLoc dl(Op); // FIXME probably not meaningful
16435 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16436 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16437 DAG.getSubtarget().getRegisterInfo());
16438 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16439 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16440 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16441 "Invalid Frame Register!");
16442 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16444 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16445 MachinePointerInfo(),
16446 false, false, false, 0);
16450 // FIXME? Maybe this could be a TableGen attribute on some registers and
16451 // this table could be generated automatically from RegInfo.
16452 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16454 unsigned Reg = StringSwitch<unsigned>(RegName)
16455 .Case("esp", X86::ESP)
16456 .Case("rsp", X86::RSP)
16460 report_fatal_error("Invalid register name global variable");
16463 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16464 SelectionDAG &DAG) const {
16465 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16466 DAG.getSubtarget().getRegisterInfo());
16467 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16470 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16471 SDValue Chain = Op.getOperand(0);
16472 SDValue Offset = Op.getOperand(1);
16473 SDValue Handler = Op.getOperand(2);
16476 EVT PtrVT = getPointerTy();
16477 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16478 DAG.getSubtarget().getRegisterInfo());
16479 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16480 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16481 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16482 "Invalid Frame Register!");
16483 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16484 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16486 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16487 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16488 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16489 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16491 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16493 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16494 DAG.getRegister(StoreAddrReg, PtrVT));
16497 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16498 SelectionDAG &DAG) const {
16500 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16501 DAG.getVTList(MVT::i32, MVT::Other),
16502 Op.getOperand(0), Op.getOperand(1));
16505 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16506 SelectionDAG &DAG) const {
16508 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16509 Op.getOperand(0), Op.getOperand(1));
16512 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16513 return Op.getOperand(0);
16516 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16517 SelectionDAG &DAG) const {
16518 SDValue Root = Op.getOperand(0);
16519 SDValue Trmp = Op.getOperand(1); // trampoline
16520 SDValue FPtr = Op.getOperand(2); // nested function
16521 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16524 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16525 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16527 if (Subtarget->is64Bit()) {
16528 SDValue OutChains[6];
16530 // Large code-model.
16531 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16532 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16534 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16535 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16537 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16539 // Load the pointer to the nested function into R11.
16540 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16541 SDValue Addr = Trmp;
16542 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16543 Addr, MachinePointerInfo(TrmpAddr),
16546 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16547 DAG.getConstant(2, MVT::i64));
16548 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16549 MachinePointerInfo(TrmpAddr, 2),
16552 // Load the 'nest' parameter value into R10.
16553 // R10 is specified in X86CallingConv.td
16554 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16555 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16556 DAG.getConstant(10, MVT::i64));
16557 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16558 Addr, MachinePointerInfo(TrmpAddr, 10),
16561 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16562 DAG.getConstant(12, MVT::i64));
16563 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16564 MachinePointerInfo(TrmpAddr, 12),
16567 // Jump to the nested function.
16568 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16570 DAG.getConstant(20, MVT::i64));
16571 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16572 Addr, MachinePointerInfo(TrmpAddr, 20),
16575 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16576 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16577 DAG.getConstant(22, MVT::i64));
16578 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16579 MachinePointerInfo(TrmpAddr, 22),
16582 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16584 const Function *Func =
16585 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16586 CallingConv::ID CC = Func->getCallingConv();
16591 llvm_unreachable("Unsupported calling convention");
16592 case CallingConv::C:
16593 case CallingConv::X86_StdCall: {
16594 // Pass 'nest' parameter in ECX.
16595 // Must be kept in sync with X86CallingConv.td
16596 NestReg = X86::ECX;
16598 // Check that ECX wasn't needed by an 'inreg' parameter.
16599 FunctionType *FTy = Func->getFunctionType();
16600 const AttributeSet &Attrs = Func->getAttributes();
16602 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16603 unsigned InRegCount = 0;
16606 for (FunctionType::param_iterator I = FTy->param_begin(),
16607 E = FTy->param_end(); I != E; ++I, ++Idx)
16608 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16609 // FIXME: should only count parameters that are lowered to integers.
16610 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16612 if (InRegCount > 2) {
16613 report_fatal_error("Nest register in use - reduce number of inreg"
16619 case CallingConv::X86_FastCall:
16620 case CallingConv::X86_ThisCall:
16621 case CallingConv::Fast:
16622 // Pass 'nest' parameter in EAX.
16623 // Must be kept in sync with X86CallingConv.td
16624 NestReg = X86::EAX;
16628 SDValue OutChains[4];
16629 SDValue Addr, Disp;
16631 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16632 DAG.getConstant(10, MVT::i32));
16633 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16635 // This is storing the opcode for MOV32ri.
16636 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16637 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16638 OutChains[0] = DAG.getStore(Root, dl,
16639 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16640 Trmp, MachinePointerInfo(TrmpAddr),
16643 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16644 DAG.getConstant(1, MVT::i32));
16645 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16646 MachinePointerInfo(TrmpAddr, 1),
16649 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16650 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16651 DAG.getConstant(5, MVT::i32));
16652 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16653 MachinePointerInfo(TrmpAddr, 5),
16656 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16657 DAG.getConstant(6, MVT::i32));
16658 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16659 MachinePointerInfo(TrmpAddr, 6),
16662 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16666 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16667 SelectionDAG &DAG) const {
16669 The rounding mode is in bits 11:10 of FPSR, and has the following
16671 00 Round to nearest
16676 FLT_ROUNDS, on the other hand, expects the following:
16683 To perform the conversion, we do:
16684 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16687 MachineFunction &MF = DAG.getMachineFunction();
16688 const TargetMachine &TM = MF.getTarget();
16689 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16690 unsigned StackAlignment = TFI.getStackAlignment();
16691 MVT VT = Op.getSimpleValueType();
16694 // Save FP Control Word to stack slot
16695 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16696 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16698 MachineMemOperand *MMO =
16699 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16700 MachineMemOperand::MOStore, 2, 2);
16702 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16703 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16704 DAG.getVTList(MVT::Other),
16705 Ops, MVT::i16, MMO);
16707 // Load FP Control Word from stack slot
16708 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16709 MachinePointerInfo(), false, false, false, 0);
16711 // Transform as necessary
16713 DAG.getNode(ISD::SRL, DL, MVT::i16,
16714 DAG.getNode(ISD::AND, DL, MVT::i16,
16715 CWD, DAG.getConstant(0x800, MVT::i16)),
16716 DAG.getConstant(11, MVT::i8));
16718 DAG.getNode(ISD::SRL, DL, MVT::i16,
16719 DAG.getNode(ISD::AND, DL, MVT::i16,
16720 CWD, DAG.getConstant(0x400, MVT::i16)),
16721 DAG.getConstant(9, MVT::i8));
16724 DAG.getNode(ISD::AND, DL, MVT::i16,
16725 DAG.getNode(ISD::ADD, DL, MVT::i16,
16726 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16727 DAG.getConstant(1, MVT::i16)),
16728 DAG.getConstant(3, MVT::i16));
16730 return DAG.getNode((VT.getSizeInBits() < 16 ?
16731 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16734 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16735 MVT VT = Op.getSimpleValueType();
16737 unsigned NumBits = VT.getSizeInBits();
16740 Op = Op.getOperand(0);
16741 if (VT == MVT::i8) {
16742 // Zero extend to i32 since there is not an i8 bsr.
16744 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16747 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16748 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16749 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16751 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16754 DAG.getConstant(NumBits+NumBits-1, OpVT),
16755 DAG.getConstant(X86::COND_E, MVT::i8),
16758 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16760 // Finally xor with NumBits-1.
16761 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16764 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16768 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16769 MVT VT = Op.getSimpleValueType();
16771 unsigned NumBits = VT.getSizeInBits();
16774 Op = Op.getOperand(0);
16775 if (VT == MVT::i8) {
16776 // Zero extend to i32 since there is not an i8 bsr.
16778 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16781 // Issue a bsr (scan bits in reverse).
16782 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16783 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16785 // And xor with NumBits-1.
16786 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16789 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16793 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16794 MVT VT = Op.getSimpleValueType();
16795 unsigned NumBits = VT.getSizeInBits();
16797 Op = Op.getOperand(0);
16799 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16800 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16801 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16803 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16806 DAG.getConstant(NumBits, VT),
16807 DAG.getConstant(X86::COND_E, MVT::i8),
16810 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16813 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16814 // ones, and then concatenate the result back.
16815 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16816 MVT VT = Op.getSimpleValueType();
16818 assert(VT.is256BitVector() && VT.isInteger() &&
16819 "Unsupported value type for operation");
16821 unsigned NumElems = VT.getVectorNumElements();
16824 // Extract the LHS vectors
16825 SDValue LHS = Op.getOperand(0);
16826 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16827 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16829 // Extract the RHS vectors
16830 SDValue RHS = Op.getOperand(1);
16831 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16832 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16834 MVT EltVT = VT.getVectorElementType();
16835 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16837 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16838 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16839 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16842 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16843 assert(Op.getSimpleValueType().is256BitVector() &&
16844 Op.getSimpleValueType().isInteger() &&
16845 "Only handle AVX 256-bit vector integer operation");
16846 return Lower256IntArith(Op, DAG);
16849 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16850 assert(Op.getSimpleValueType().is256BitVector() &&
16851 Op.getSimpleValueType().isInteger() &&
16852 "Only handle AVX 256-bit vector integer operation");
16853 return Lower256IntArith(Op, DAG);
16856 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16857 SelectionDAG &DAG) {
16859 MVT VT = Op.getSimpleValueType();
16861 // Decompose 256-bit ops into smaller 128-bit ops.
16862 if (VT.is256BitVector() && !Subtarget->hasInt256())
16863 return Lower256IntArith(Op, DAG);
16865 SDValue A = Op.getOperand(0);
16866 SDValue B = Op.getOperand(1);
16868 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16869 if (VT == MVT::v4i32) {
16870 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16871 "Should not custom lower when pmuldq is available!");
16873 // Extract the odd parts.
16874 static const int UnpackMask[] = { 1, -1, 3, -1 };
16875 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16876 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16878 // Multiply the even parts.
16879 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16880 // Now multiply odd parts.
16881 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16883 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16884 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16886 // Merge the two vectors back together with a shuffle. This expands into 2
16888 static const int ShufMask[] = { 0, 4, 2, 6 };
16889 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16892 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16893 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16895 // Ahi = psrlqi(a, 32);
16896 // Bhi = psrlqi(b, 32);
16898 // AloBlo = pmuludq(a, b);
16899 // AloBhi = pmuludq(a, Bhi);
16900 // AhiBlo = pmuludq(Ahi, b);
16902 // AloBhi = psllqi(AloBhi, 32);
16903 // AhiBlo = psllqi(AhiBlo, 32);
16904 // return AloBlo + AloBhi + AhiBlo;
16906 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16907 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16909 // Bit cast to 32-bit vectors for MULUDQ
16910 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16911 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16912 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16913 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16914 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16915 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16917 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16918 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16919 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16921 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16922 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16924 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16925 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16928 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16929 assert(Subtarget->isTargetWin64() && "Unexpected target");
16930 EVT VT = Op.getValueType();
16931 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16932 "Unexpected return type for lowering");
16936 switch (Op->getOpcode()) {
16937 default: llvm_unreachable("Unexpected request for libcall!");
16938 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16939 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16940 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16941 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16942 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16943 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16947 SDValue InChain = DAG.getEntryNode();
16949 TargetLowering::ArgListTy Args;
16950 TargetLowering::ArgListEntry Entry;
16951 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16952 EVT ArgVT = Op->getOperand(i).getValueType();
16953 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16954 "Unexpected argument type for lowering");
16955 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16956 Entry.Node = StackPtr;
16957 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16959 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16960 Entry.Ty = PointerType::get(ArgTy,0);
16961 Entry.isSExt = false;
16962 Entry.isZExt = false;
16963 Args.push_back(Entry);
16966 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16969 TargetLowering::CallLoweringInfo CLI(DAG);
16970 CLI.setDebugLoc(dl).setChain(InChain)
16971 .setCallee(getLibcallCallingConv(LC),
16972 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16973 Callee, std::move(Args), 0)
16974 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16976 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16977 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16980 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16981 SelectionDAG &DAG) {
16982 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16983 EVT VT = Op0.getValueType();
16986 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16987 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16989 // PMULxD operations multiply each even value (starting at 0) of LHS with
16990 // the related value of RHS and produce a widen result.
16991 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16992 // => <2 x i64> <ae|cg>
16994 // In other word, to have all the results, we need to perform two PMULxD:
16995 // 1. one with the even values.
16996 // 2. one with the odd values.
16997 // To achieve #2, with need to place the odd values at an even position.
16999 // Place the odd value at an even position (basically, shift all values 1
17000 // step to the left):
17001 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17002 // <a|b|c|d> => <b|undef|d|undef>
17003 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17004 // <e|f|g|h> => <f|undef|h|undef>
17005 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17007 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17009 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17010 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17012 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17013 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17014 // => <2 x i64> <ae|cg>
17015 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17016 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17017 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17018 // => <2 x i64> <bf|dh>
17019 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17020 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17022 // Shuffle it back into the right order.
17023 SDValue Highs, Lows;
17024 if (VT == MVT::v8i32) {
17025 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17026 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17027 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17028 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17030 const int HighMask[] = {1, 5, 3, 7};
17031 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17032 const int LowMask[] = {0, 4, 2, 6};
17033 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17036 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17037 // unsigned multiply.
17038 if (IsSigned && !Subtarget->hasSSE41()) {
17040 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17041 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17042 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17043 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17044 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17046 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17047 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17050 // The first result of MUL_LOHI is actually the low value, followed by the
17052 SDValue Ops[] = {Lows, Highs};
17053 return DAG.getMergeValues(Ops, dl);
17056 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17057 const X86Subtarget *Subtarget) {
17058 MVT VT = Op.getSimpleValueType();
17060 SDValue R = Op.getOperand(0);
17061 SDValue Amt = Op.getOperand(1);
17063 // Optimize shl/srl/sra with constant shift amount.
17064 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17065 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17066 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17068 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17069 (Subtarget->hasInt256() &&
17070 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17071 (Subtarget->hasAVX512() &&
17072 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17073 if (Op.getOpcode() == ISD::SHL)
17074 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17076 if (Op.getOpcode() == ISD::SRL)
17077 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17079 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17080 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17084 if (VT == MVT::v16i8) {
17085 if (Op.getOpcode() == ISD::SHL) {
17086 // Make a large shift.
17087 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17088 MVT::v8i16, R, ShiftAmt,
17090 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17091 // Zero out the rightmost bits.
17092 SmallVector<SDValue, 16> V(16,
17093 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17095 return DAG.getNode(ISD::AND, dl, VT, SHL,
17096 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17098 if (Op.getOpcode() == ISD::SRL) {
17099 // Make a large shift.
17100 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17101 MVT::v8i16, R, ShiftAmt,
17103 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17104 // Zero out the leftmost bits.
17105 SmallVector<SDValue, 16> V(16,
17106 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17108 return DAG.getNode(ISD::AND, dl, VT, SRL,
17109 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17111 if (Op.getOpcode() == ISD::SRA) {
17112 if (ShiftAmt == 7) {
17113 // R s>> 7 === R s< 0
17114 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17115 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17118 // R s>> a === ((R u>> a) ^ m) - m
17119 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17120 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17122 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17123 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17124 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17127 llvm_unreachable("Unknown shift opcode.");
17130 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17131 if (Op.getOpcode() == ISD::SHL) {
17132 // Make a large shift.
17133 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17134 MVT::v16i16, R, ShiftAmt,
17136 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17137 // Zero out the rightmost bits.
17138 SmallVector<SDValue, 32> V(32,
17139 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17141 return DAG.getNode(ISD::AND, dl, VT, SHL,
17142 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17144 if (Op.getOpcode() == ISD::SRL) {
17145 // Make a large shift.
17146 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17147 MVT::v16i16, R, ShiftAmt,
17149 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17150 // Zero out the leftmost bits.
17151 SmallVector<SDValue, 32> V(32,
17152 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17154 return DAG.getNode(ISD::AND, dl, VT, SRL,
17155 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17157 if (Op.getOpcode() == ISD::SRA) {
17158 if (ShiftAmt == 7) {
17159 // R s>> 7 === R s< 0
17160 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17161 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17164 // R s>> a === ((R u>> a) ^ m) - m
17165 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17166 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17168 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17169 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17170 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17173 llvm_unreachable("Unknown shift opcode.");
17178 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17179 if (!Subtarget->is64Bit() &&
17180 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17181 Amt.getOpcode() == ISD::BITCAST &&
17182 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17183 Amt = Amt.getOperand(0);
17184 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17185 VT.getVectorNumElements();
17186 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17187 uint64_t ShiftAmt = 0;
17188 for (unsigned i = 0; i != Ratio; ++i) {
17189 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17193 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17195 // Check remaining shift amounts.
17196 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17197 uint64_t ShAmt = 0;
17198 for (unsigned j = 0; j != Ratio; ++j) {
17199 ConstantSDNode *C =
17200 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17204 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17206 if (ShAmt != ShiftAmt)
17209 switch (Op.getOpcode()) {
17211 llvm_unreachable("Unknown shift opcode!");
17213 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17216 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17219 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17227 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17228 const X86Subtarget* Subtarget) {
17229 MVT VT = Op.getSimpleValueType();
17231 SDValue R = Op.getOperand(0);
17232 SDValue Amt = Op.getOperand(1);
17234 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17235 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17236 (Subtarget->hasInt256() &&
17237 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17238 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17239 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17241 EVT EltVT = VT.getVectorElementType();
17243 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17244 unsigned NumElts = VT.getVectorNumElements();
17246 for (i = 0; i != NumElts; ++i) {
17247 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17251 for (j = i; j != NumElts; ++j) {
17252 SDValue Arg = Amt.getOperand(j);
17253 if (Arg.getOpcode() == ISD::UNDEF) continue;
17254 if (Arg != Amt.getOperand(i))
17257 if (i != NumElts && j == NumElts)
17258 BaseShAmt = Amt.getOperand(i);
17260 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17261 Amt = Amt.getOperand(0);
17262 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17263 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17264 SDValue InVec = Amt.getOperand(0);
17265 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17266 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17268 for (; i != NumElts; ++i) {
17269 SDValue Arg = InVec.getOperand(i);
17270 if (Arg.getOpcode() == ISD::UNDEF) continue;
17274 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17275 if (ConstantSDNode *C =
17276 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17277 unsigned SplatIdx =
17278 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17279 if (C->getZExtValue() == SplatIdx)
17280 BaseShAmt = InVec.getOperand(1);
17283 if (!BaseShAmt.getNode())
17284 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17285 DAG.getIntPtrConstant(0));
17289 if (BaseShAmt.getNode()) {
17290 if (EltVT.bitsGT(MVT::i32))
17291 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17292 else if (EltVT.bitsLT(MVT::i32))
17293 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17295 switch (Op.getOpcode()) {
17297 llvm_unreachable("Unknown shift opcode!");
17299 switch (VT.SimpleTy) {
17300 default: return SDValue();
17309 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17312 switch (VT.SimpleTy) {
17313 default: return SDValue();
17320 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17323 switch (VT.SimpleTy) {
17324 default: return SDValue();
17333 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17339 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17340 if (!Subtarget->is64Bit() &&
17341 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17342 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17343 Amt.getOpcode() == ISD::BITCAST &&
17344 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17345 Amt = Amt.getOperand(0);
17346 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17347 VT.getVectorNumElements();
17348 std::vector<SDValue> Vals(Ratio);
17349 for (unsigned i = 0; i != Ratio; ++i)
17350 Vals[i] = Amt.getOperand(i);
17351 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17352 for (unsigned j = 0; j != Ratio; ++j)
17353 if (Vals[j] != Amt.getOperand(i + j))
17356 switch (Op.getOpcode()) {
17358 llvm_unreachable("Unknown shift opcode!");
17360 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17362 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17364 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17371 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17372 SelectionDAG &DAG) {
17373 MVT VT = Op.getSimpleValueType();
17375 SDValue R = Op.getOperand(0);
17376 SDValue Amt = Op.getOperand(1);
17379 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17380 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17382 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17386 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17390 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17392 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17393 if (Subtarget->hasInt256()) {
17394 if (Op.getOpcode() == ISD::SRL &&
17395 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17396 VT == MVT::v4i64 || VT == MVT::v8i32))
17398 if (Op.getOpcode() == ISD::SHL &&
17399 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17400 VT == MVT::v4i64 || VT == MVT::v8i32))
17402 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17406 // If possible, lower this packed shift into a vector multiply instead of
17407 // expanding it into a sequence of scalar shifts.
17408 // Do this only if the vector shift count is a constant build_vector.
17409 if (Op.getOpcode() == ISD::SHL &&
17410 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17411 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17412 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17413 SmallVector<SDValue, 8> Elts;
17414 EVT SVT = VT.getScalarType();
17415 unsigned SVTBits = SVT.getSizeInBits();
17416 const APInt &One = APInt(SVTBits, 1);
17417 unsigned NumElems = VT.getVectorNumElements();
17419 for (unsigned i=0; i !=NumElems; ++i) {
17420 SDValue Op = Amt->getOperand(i);
17421 if (Op->getOpcode() == ISD::UNDEF) {
17422 Elts.push_back(Op);
17426 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17427 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17428 uint64_t ShAmt = C.getZExtValue();
17429 if (ShAmt >= SVTBits) {
17430 Elts.push_back(DAG.getUNDEF(SVT));
17433 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17435 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17436 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17439 // Lower SHL with variable shift amount.
17440 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17441 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17443 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17444 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17445 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17446 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17449 // If possible, lower this shift as a sequence of two shifts by
17450 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17452 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17454 // Could be rewritten as:
17455 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17457 // The advantage is that the two shifts from the example would be
17458 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17459 // the vector shift into four scalar shifts plus four pairs of vector
17461 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17462 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17463 unsigned TargetOpcode = X86ISD::MOVSS;
17464 bool CanBeSimplified;
17465 // The splat value for the first packed shift (the 'X' from the example).
17466 SDValue Amt1 = Amt->getOperand(0);
17467 // The splat value for the second packed shift (the 'Y' from the example).
17468 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17469 Amt->getOperand(2);
17471 // See if it is possible to replace this node with a sequence of
17472 // two shifts followed by a MOVSS/MOVSD
17473 if (VT == MVT::v4i32) {
17474 // Check if it is legal to use a MOVSS.
17475 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17476 Amt2 == Amt->getOperand(3);
17477 if (!CanBeSimplified) {
17478 // Otherwise, check if we can still simplify this node using a MOVSD.
17479 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17480 Amt->getOperand(2) == Amt->getOperand(3);
17481 TargetOpcode = X86ISD::MOVSD;
17482 Amt2 = Amt->getOperand(2);
17485 // Do similar checks for the case where the machine value type
17487 CanBeSimplified = Amt1 == Amt->getOperand(1);
17488 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17489 CanBeSimplified = Amt2 == Amt->getOperand(i);
17491 if (!CanBeSimplified) {
17492 TargetOpcode = X86ISD::MOVSD;
17493 CanBeSimplified = true;
17494 Amt2 = Amt->getOperand(4);
17495 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17496 CanBeSimplified = Amt1 == Amt->getOperand(i);
17497 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17498 CanBeSimplified = Amt2 == Amt->getOperand(j);
17502 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17503 isa<ConstantSDNode>(Amt2)) {
17504 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17505 EVT CastVT = MVT::v4i32;
17507 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17508 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17510 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17511 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17512 if (TargetOpcode == X86ISD::MOVSD)
17513 CastVT = MVT::v2i64;
17514 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17515 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17516 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17518 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17522 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17523 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17526 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17527 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17529 // Turn 'a' into a mask suitable for VSELECT
17530 SDValue VSelM = DAG.getConstant(0x80, VT);
17531 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17532 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17534 SDValue CM1 = DAG.getConstant(0x0f, VT);
17535 SDValue CM2 = DAG.getConstant(0x3f, VT);
17537 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17538 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17539 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17540 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17541 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17544 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17545 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17546 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17548 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17549 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17550 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17551 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17552 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17555 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17556 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17557 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17559 // return VSELECT(r, r+r, a);
17560 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17561 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17565 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17566 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17567 // solution better.
17568 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17569 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17571 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17572 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17573 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17574 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17575 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17578 // Decompose 256-bit shifts into smaller 128-bit shifts.
17579 if (VT.is256BitVector()) {
17580 unsigned NumElems = VT.getVectorNumElements();
17581 MVT EltVT = VT.getVectorElementType();
17582 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17584 // Extract the two vectors
17585 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17586 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17588 // Recreate the shift amount vectors
17589 SDValue Amt1, Amt2;
17590 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17591 // Constant shift amount
17592 SmallVector<SDValue, 4> Amt1Csts;
17593 SmallVector<SDValue, 4> Amt2Csts;
17594 for (unsigned i = 0; i != NumElems/2; ++i)
17595 Amt1Csts.push_back(Amt->getOperand(i));
17596 for (unsigned i = NumElems/2; i != NumElems; ++i)
17597 Amt2Csts.push_back(Amt->getOperand(i));
17599 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17600 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17602 // Variable shift amount
17603 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17604 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17607 // Issue new vector shifts for the smaller types
17608 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17609 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17611 // Concatenate the result back
17612 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17618 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17619 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17620 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17621 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17622 // has only one use.
17623 SDNode *N = Op.getNode();
17624 SDValue LHS = N->getOperand(0);
17625 SDValue RHS = N->getOperand(1);
17626 unsigned BaseOp = 0;
17629 switch (Op.getOpcode()) {
17630 default: llvm_unreachable("Unknown ovf instruction!");
17632 // A subtract of one will be selected as a INC. Note that INC doesn't
17633 // set CF, so we can't do this for UADDO.
17634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17636 BaseOp = X86ISD::INC;
17637 Cond = X86::COND_O;
17640 BaseOp = X86ISD::ADD;
17641 Cond = X86::COND_O;
17644 BaseOp = X86ISD::ADD;
17645 Cond = X86::COND_B;
17648 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17649 // set CF, so we can't do this for USUBO.
17650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17652 BaseOp = X86ISD::DEC;
17653 Cond = X86::COND_O;
17656 BaseOp = X86ISD::SUB;
17657 Cond = X86::COND_O;
17660 BaseOp = X86ISD::SUB;
17661 Cond = X86::COND_B;
17664 BaseOp = X86ISD::SMUL;
17665 Cond = X86::COND_O;
17667 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17668 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17670 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17673 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17674 DAG.getConstant(X86::COND_O, MVT::i32),
17675 SDValue(Sum.getNode(), 2));
17677 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17681 // Also sets EFLAGS.
17682 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17683 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17686 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17687 DAG.getConstant(Cond, MVT::i32),
17688 SDValue(Sum.getNode(), 1));
17690 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17693 // Sign extension of the low part of vector elements. This may be used either
17694 // when sign extend instructions are not available or if the vector element
17695 // sizes already match the sign-extended size. If the vector elements are in
17696 // their pre-extended size and sign extend instructions are available, that will
17697 // be handled by LowerSIGN_EXTEND.
17698 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17699 SelectionDAG &DAG) const {
17701 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17702 MVT VT = Op.getSimpleValueType();
17704 if (!Subtarget->hasSSE2() || !VT.isVector())
17707 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17708 ExtraVT.getScalarType().getSizeInBits();
17710 switch (VT.SimpleTy) {
17711 default: return SDValue();
17714 if (!Subtarget->hasFp256())
17716 if (!Subtarget->hasInt256()) {
17717 // needs to be split
17718 unsigned NumElems = VT.getVectorNumElements();
17720 // Extract the LHS vectors
17721 SDValue LHS = Op.getOperand(0);
17722 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17723 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17725 MVT EltVT = VT.getVectorElementType();
17726 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17728 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17729 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17730 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17732 SDValue Extra = DAG.getValueType(ExtraVT);
17734 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17735 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17737 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17742 SDValue Op0 = Op.getOperand(0);
17744 // This is a sign extension of some low part of vector elements without
17745 // changing the size of the vector elements themselves:
17746 // Shift-Left + Shift-Right-Algebraic.
17747 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17749 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17755 /// Returns true if the operand type is exactly twice the native width, and
17756 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17757 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17758 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17759 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17760 const X86Subtarget &Subtarget =
17761 getTargetMachine().getSubtarget<X86Subtarget>();
17762 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17765 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17766 else if (OpWidth == 128)
17767 return Subtarget.hasCmpxchg16b();
17772 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17773 return needsCmpXchgNb(SI->getValueOperand()->getType());
17776 // Note: this turns large loads into lock cmpxchg8b/16b.
17777 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17778 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17779 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17780 return needsCmpXchgNb(PTy->getElementType());
17783 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17784 const X86Subtarget &Subtarget =
17785 getTargetMachine().getSubtarget<X86Subtarget>();
17786 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17787 const Type *MemType = AI->getType();
17789 // If the operand is too big, we must see if cmpxchg8/16b is available
17790 // and default to library calls otherwise.
17791 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17792 return needsCmpXchgNb(MemType);
17794 AtomicRMWInst::BinOp Op = AI->getOperation();
17797 llvm_unreachable("Unknown atomic operation");
17798 case AtomicRMWInst::Xchg:
17799 case AtomicRMWInst::Add:
17800 case AtomicRMWInst::Sub:
17801 // It's better to use xadd, xsub or xchg for these in all cases.
17803 case AtomicRMWInst::Or:
17804 case AtomicRMWInst::And:
17805 case AtomicRMWInst::Xor:
17806 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17807 // prefix to a normal instruction for these operations.
17808 return !AI->use_empty();
17809 case AtomicRMWInst::Nand:
17810 case AtomicRMWInst::Max:
17811 case AtomicRMWInst::Min:
17812 case AtomicRMWInst::UMax:
17813 case AtomicRMWInst::UMin:
17814 // These always require a non-trivial set of data operations on x86. We must
17815 // use a cmpxchg loop.
17820 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17821 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17822 // no-sse2). There isn't any reason to disable it if the target processor
17824 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17828 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17829 const X86Subtarget &Subtarget =
17830 getTargetMachine().getSubtarget<X86Subtarget>();
17831 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17832 const Type *MemType = AI->getType();
17833 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17834 // there is no benefit in turning such RMWs into loads, and it is actually
17835 // harmful as it introduces a mfence.
17836 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17839 auto Builder = IRBuilder<>(AI);
17840 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17841 auto SynchScope = AI->getSynchScope();
17842 // We must restrict the ordering to avoid generating loads with Release or
17843 // ReleaseAcquire orderings.
17844 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17845 auto Ptr = AI->getPointerOperand();
17847 // Before the load we need a fence. Here is an example lifted from
17848 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17851 // x.store(1, relaxed);
17852 // r1 = y.fetch_add(0, release);
17854 // y.fetch_add(42, acquire);
17855 // r2 = x.load(relaxed);
17856 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17857 // lowered to just a load without a fence. A mfence flushes the store buffer,
17858 // making the optimization clearly correct.
17859 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17860 // otherwise, we might be able to be more agressive on relaxed idempotent
17861 // rmw. In practice, they do not look useful, so we don't try to be
17862 // especially clever.
17863 if (SynchScope == SingleThread) {
17864 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17865 // the IR level, so we must wrap it in an intrinsic.
17867 } else if (hasMFENCE(Subtarget)) {
17868 Function *MFence = llvm::Intrinsic::getDeclaration(M,
17869 Intrinsic::x86_sse2_mfence);
17870 Builder.CreateCall(MFence);
17872 // FIXME: it might make sense to use a locked operation here but on a
17873 // different cache-line to prevent cache-line bouncing. In practice it
17874 // is probably a small win, and x86 processors without mfence are rare
17875 // enough that we do not bother.
17879 // Finally we can emit the atomic load.
17880 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17881 AI->getType()->getPrimitiveSizeInBits());
17882 Loaded->setAtomic(Order, SynchScope);
17883 AI->replaceAllUsesWith(Loaded);
17884 AI->eraseFromParent();
17888 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17889 SelectionDAG &DAG) {
17891 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17892 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17893 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17894 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17896 // The only fence that needs an instruction is a sequentially-consistent
17897 // cross-thread fence.
17898 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17899 if (hasMFENCE(*Subtarget))
17900 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17902 SDValue Chain = Op.getOperand(0);
17903 SDValue Zero = DAG.getConstant(0, MVT::i32);
17905 DAG.getRegister(X86::ESP, MVT::i32), // Base
17906 DAG.getTargetConstant(1, MVT::i8), // Scale
17907 DAG.getRegister(0, MVT::i32), // Index
17908 DAG.getTargetConstant(0, MVT::i32), // Disp
17909 DAG.getRegister(0, MVT::i32), // Segment.
17913 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17914 return SDValue(Res, 0);
17917 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17918 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17921 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17922 SelectionDAG &DAG) {
17923 MVT T = Op.getSimpleValueType();
17927 switch(T.SimpleTy) {
17928 default: llvm_unreachable("Invalid value type!");
17929 case MVT::i8: Reg = X86::AL; size = 1; break;
17930 case MVT::i16: Reg = X86::AX; size = 2; break;
17931 case MVT::i32: Reg = X86::EAX; size = 4; break;
17933 assert(Subtarget->is64Bit() && "Node not type legal!");
17934 Reg = X86::RAX; size = 8;
17937 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17938 Op.getOperand(2), SDValue());
17939 SDValue Ops[] = { cpIn.getValue(0),
17942 DAG.getTargetConstant(size, MVT::i8),
17943 cpIn.getValue(1) };
17944 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17945 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17946 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17950 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17951 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17952 MVT::i32, cpOut.getValue(2));
17953 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17954 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17956 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17957 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17958 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17962 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17963 SelectionDAG &DAG) {
17964 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17965 MVT DstVT = Op.getSimpleValueType();
17967 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17968 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17969 if (DstVT != MVT::f64)
17970 // This conversion needs to be expanded.
17973 SDValue InVec = Op->getOperand(0);
17975 unsigned NumElts = SrcVT.getVectorNumElements();
17976 EVT SVT = SrcVT.getVectorElementType();
17978 // Widen the vector in input in the case of MVT::v2i32.
17979 // Example: from MVT::v2i32 to MVT::v4i32.
17980 SmallVector<SDValue, 16> Elts;
17981 for (unsigned i = 0, e = NumElts; i != e; ++i)
17982 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17983 DAG.getIntPtrConstant(i)));
17985 // Explicitly mark the extra elements as Undef.
17986 SDValue Undef = DAG.getUNDEF(SVT);
17987 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17988 Elts.push_back(Undef);
17990 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17991 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17992 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17993 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17994 DAG.getIntPtrConstant(0));
17997 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17998 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17999 assert((DstVT == MVT::i64 ||
18000 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18001 "Unexpected custom BITCAST");
18002 // i64 <=> MMX conversions are Legal.
18003 if (SrcVT==MVT::i64 && DstVT.isVector())
18005 if (DstVT==MVT::i64 && SrcVT.isVector())
18007 // MMX <=> MMX conversions are Legal.
18008 if (SrcVT.isVector() && DstVT.isVector())
18010 // All other conversions need to be expanded.
18014 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18015 SDNode *Node = Op.getNode();
18017 EVT T = Node->getValueType(0);
18018 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18019 DAG.getConstant(0, T), Node->getOperand(2));
18020 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18021 cast<AtomicSDNode>(Node)->getMemoryVT(),
18022 Node->getOperand(0),
18023 Node->getOperand(1), negOp,
18024 cast<AtomicSDNode>(Node)->getMemOperand(),
18025 cast<AtomicSDNode>(Node)->getOrdering(),
18026 cast<AtomicSDNode>(Node)->getSynchScope());
18029 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18030 SDNode *Node = Op.getNode();
18032 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18034 // Convert seq_cst store -> xchg
18035 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18036 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18037 // (The only way to get a 16-byte store is cmpxchg16b)
18038 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18039 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18040 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18041 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18042 cast<AtomicSDNode>(Node)->getMemoryVT(),
18043 Node->getOperand(0),
18044 Node->getOperand(1), Node->getOperand(2),
18045 cast<AtomicSDNode>(Node)->getMemOperand(),
18046 cast<AtomicSDNode>(Node)->getOrdering(),
18047 cast<AtomicSDNode>(Node)->getSynchScope());
18048 return Swap.getValue(1);
18050 // Other atomic stores have a simple pattern.
18054 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18055 EVT VT = Op.getNode()->getSimpleValueType(0);
18057 // Let legalize expand this if it isn't a legal type yet.
18058 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18061 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18064 bool ExtraOp = false;
18065 switch (Op.getOpcode()) {
18066 default: llvm_unreachable("Invalid code");
18067 case ISD::ADDC: Opc = X86ISD::ADD; break;
18068 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18069 case ISD::SUBC: Opc = X86ISD::SUB; break;
18070 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18074 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18076 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18077 Op.getOperand(1), Op.getOperand(2));
18080 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18081 SelectionDAG &DAG) {
18082 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18084 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18085 // which returns the values as { float, float } (in XMM0) or
18086 // { double, double } (which is returned in XMM0, XMM1).
18088 SDValue Arg = Op.getOperand(0);
18089 EVT ArgVT = Arg.getValueType();
18090 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18092 TargetLowering::ArgListTy Args;
18093 TargetLowering::ArgListEntry Entry;
18097 Entry.isSExt = false;
18098 Entry.isZExt = false;
18099 Args.push_back(Entry);
18101 bool isF64 = ArgVT == MVT::f64;
18102 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18103 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18104 // the results are returned via SRet in memory.
18105 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18107 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18109 Type *RetTy = isF64
18110 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18111 : (Type*)VectorType::get(ArgTy, 4);
18113 TargetLowering::CallLoweringInfo CLI(DAG);
18114 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18115 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18117 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18120 // Returned in xmm0 and xmm1.
18121 return CallResult.first;
18123 // Returned in bits 0:31 and 32:64 xmm0.
18124 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18125 CallResult.first, DAG.getIntPtrConstant(0));
18126 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18127 CallResult.first, DAG.getIntPtrConstant(1));
18128 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18129 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18132 /// LowerOperation - Provide custom lowering hooks for some operations.
18134 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18135 switch (Op.getOpcode()) {
18136 default: llvm_unreachable("Should not custom lower this!");
18137 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18138 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18139 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18140 return LowerCMP_SWAP(Op, Subtarget, DAG);
18141 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18142 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18143 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18144 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18145 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18146 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18147 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18148 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18149 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18150 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18151 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18152 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18153 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18154 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18155 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18156 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18157 case ISD::SHL_PARTS:
18158 case ISD::SRA_PARTS:
18159 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18160 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18161 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18162 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18163 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18164 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18165 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18166 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18167 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18168 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18169 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18171 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18172 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18173 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18174 case ISD::SETCC: return LowerSETCC(Op, DAG);
18175 case ISD::SELECT: return LowerSELECT(Op, DAG);
18176 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18177 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18178 case ISD::VASTART: return LowerVASTART(Op, DAG);
18179 case ISD::VAARG: return LowerVAARG(Op, DAG);
18180 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18181 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18182 case ISD::INTRINSIC_VOID:
18183 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18184 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18185 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18186 case ISD::FRAME_TO_ARGS_OFFSET:
18187 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18188 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18189 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18190 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18191 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18192 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18193 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18194 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18195 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18196 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18197 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18198 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18199 case ISD::UMUL_LOHI:
18200 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18203 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18209 case ISD::UMULO: return LowerXALUO(Op, DAG);
18210 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18211 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18215 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18216 case ISD::ADD: return LowerADD(Op, DAG);
18217 case ISD::SUB: return LowerSUB(Op, DAG);
18218 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18222 /// ReplaceNodeResults - Replace a node with an illegal result type
18223 /// with a new node built out of custom code.
18224 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18225 SmallVectorImpl<SDValue>&Results,
18226 SelectionDAG &DAG) const {
18228 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18229 switch (N->getOpcode()) {
18231 llvm_unreachable("Do not know how to custom type legalize this operation!");
18232 case ISD::SIGN_EXTEND_INREG:
18237 // We don't want to expand or promote these.
18244 case ISD::UDIVREM: {
18245 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18246 Results.push_back(V);
18249 case ISD::FP_TO_SINT:
18250 case ISD::FP_TO_UINT: {
18251 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18253 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18256 std::pair<SDValue,SDValue> Vals =
18257 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18258 SDValue FIST = Vals.first, StackSlot = Vals.second;
18259 if (FIST.getNode()) {
18260 EVT VT = N->getValueType(0);
18261 // Return a load from the stack slot.
18262 if (StackSlot.getNode())
18263 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18264 MachinePointerInfo(),
18265 false, false, false, 0));
18267 Results.push_back(FIST);
18271 case ISD::UINT_TO_FP: {
18272 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18273 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18274 N->getValueType(0) != MVT::v2f32)
18276 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18278 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18280 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18281 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18282 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18283 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18284 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18285 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18288 case ISD::FP_ROUND: {
18289 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18291 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18292 Results.push_back(V);
18295 case ISD::INTRINSIC_W_CHAIN: {
18296 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18298 default : llvm_unreachable("Do not know how to custom type "
18299 "legalize this intrinsic operation!");
18300 case Intrinsic::x86_rdtsc:
18301 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18303 case Intrinsic::x86_rdtscp:
18304 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18306 case Intrinsic::x86_rdpmc:
18307 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18310 case ISD::READCYCLECOUNTER: {
18311 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18314 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18315 EVT T = N->getValueType(0);
18316 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18317 bool Regs64bit = T == MVT::i128;
18318 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18319 SDValue cpInL, cpInH;
18320 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18321 DAG.getConstant(0, HalfT));
18322 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18323 DAG.getConstant(1, HalfT));
18324 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18325 Regs64bit ? X86::RAX : X86::EAX,
18327 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18328 Regs64bit ? X86::RDX : X86::EDX,
18329 cpInH, cpInL.getValue(1));
18330 SDValue swapInL, swapInH;
18331 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18332 DAG.getConstant(0, HalfT));
18333 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18334 DAG.getConstant(1, HalfT));
18335 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18336 Regs64bit ? X86::RBX : X86::EBX,
18337 swapInL, cpInH.getValue(1));
18338 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18339 Regs64bit ? X86::RCX : X86::ECX,
18340 swapInH, swapInL.getValue(1));
18341 SDValue Ops[] = { swapInH.getValue(0),
18343 swapInH.getValue(1) };
18344 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18345 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18346 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18347 X86ISD::LCMPXCHG8_DAG;
18348 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18349 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18350 Regs64bit ? X86::RAX : X86::EAX,
18351 HalfT, Result.getValue(1));
18352 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18353 Regs64bit ? X86::RDX : X86::EDX,
18354 HalfT, cpOutL.getValue(2));
18355 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18357 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18358 MVT::i32, cpOutH.getValue(2));
18360 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18361 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18362 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18364 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18365 Results.push_back(Success);
18366 Results.push_back(EFLAGS.getValue(1));
18369 case ISD::ATOMIC_SWAP:
18370 case ISD::ATOMIC_LOAD_ADD:
18371 case ISD::ATOMIC_LOAD_SUB:
18372 case ISD::ATOMIC_LOAD_AND:
18373 case ISD::ATOMIC_LOAD_OR:
18374 case ISD::ATOMIC_LOAD_XOR:
18375 case ISD::ATOMIC_LOAD_NAND:
18376 case ISD::ATOMIC_LOAD_MIN:
18377 case ISD::ATOMIC_LOAD_MAX:
18378 case ISD::ATOMIC_LOAD_UMIN:
18379 case ISD::ATOMIC_LOAD_UMAX:
18380 case ISD::ATOMIC_LOAD: {
18381 // Delegate to generic TypeLegalization. Situations we can really handle
18382 // should have already been dealt with by AtomicExpandPass.cpp.
18385 case ISD::BITCAST: {
18386 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18387 EVT DstVT = N->getValueType(0);
18388 EVT SrcVT = N->getOperand(0)->getValueType(0);
18390 if (SrcVT != MVT::f64 ||
18391 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18394 unsigned NumElts = DstVT.getVectorNumElements();
18395 EVT SVT = DstVT.getVectorElementType();
18396 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18397 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18398 MVT::v2f64, N->getOperand(0));
18399 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18401 if (ExperimentalVectorWideningLegalization) {
18402 // If we are legalizing vectors by widening, we already have the desired
18403 // legal vector type, just return it.
18404 Results.push_back(ToVecInt);
18408 SmallVector<SDValue, 8> Elts;
18409 for (unsigned i = 0, e = NumElts; i != e; ++i)
18410 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18411 ToVecInt, DAG.getIntPtrConstant(i)));
18413 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18418 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18420 default: return nullptr;
18421 case X86ISD::BSF: return "X86ISD::BSF";
18422 case X86ISD::BSR: return "X86ISD::BSR";
18423 case X86ISD::SHLD: return "X86ISD::SHLD";
18424 case X86ISD::SHRD: return "X86ISD::SHRD";
18425 case X86ISD::FAND: return "X86ISD::FAND";
18426 case X86ISD::FANDN: return "X86ISD::FANDN";
18427 case X86ISD::FOR: return "X86ISD::FOR";
18428 case X86ISD::FXOR: return "X86ISD::FXOR";
18429 case X86ISD::FSRL: return "X86ISD::FSRL";
18430 case X86ISD::FILD: return "X86ISD::FILD";
18431 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18432 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18433 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18434 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18435 case X86ISD::FLD: return "X86ISD::FLD";
18436 case X86ISD::FST: return "X86ISD::FST";
18437 case X86ISD::CALL: return "X86ISD::CALL";
18438 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18439 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18440 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18441 case X86ISD::BT: return "X86ISD::BT";
18442 case X86ISD::CMP: return "X86ISD::CMP";
18443 case X86ISD::COMI: return "X86ISD::COMI";
18444 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18445 case X86ISD::CMPM: return "X86ISD::CMPM";
18446 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18447 case X86ISD::SETCC: return "X86ISD::SETCC";
18448 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18449 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18450 case X86ISD::CMOV: return "X86ISD::CMOV";
18451 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18452 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18453 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18454 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18455 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18456 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18457 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18458 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18459 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18460 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18461 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18462 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18463 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18464 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18465 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18466 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18467 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18468 case X86ISD::HADD: return "X86ISD::HADD";
18469 case X86ISD::HSUB: return "X86ISD::HSUB";
18470 case X86ISD::FHADD: return "X86ISD::FHADD";
18471 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18472 case X86ISD::UMAX: return "X86ISD::UMAX";
18473 case X86ISD::UMIN: return "X86ISD::UMIN";
18474 case X86ISD::SMAX: return "X86ISD::SMAX";
18475 case X86ISD::SMIN: return "X86ISD::SMIN";
18476 case X86ISD::FMAX: return "X86ISD::FMAX";
18477 case X86ISD::FMIN: return "X86ISD::FMIN";
18478 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18479 case X86ISD::FMINC: return "X86ISD::FMINC";
18480 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18481 case X86ISD::FRCP: return "X86ISD::FRCP";
18482 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18483 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18484 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18485 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18486 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18487 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18488 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18489 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18490 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18491 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18492 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18493 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18494 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18495 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18496 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18497 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18498 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18499 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18500 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18501 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18502 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18503 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18504 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18505 case X86ISD::VSHL: return "X86ISD::VSHL";
18506 case X86ISD::VSRL: return "X86ISD::VSRL";
18507 case X86ISD::VSRA: return "X86ISD::VSRA";
18508 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18509 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18510 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18511 case X86ISD::CMPP: return "X86ISD::CMPP";
18512 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18513 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18514 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18515 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18516 case X86ISD::ADD: return "X86ISD::ADD";
18517 case X86ISD::SUB: return "X86ISD::SUB";
18518 case X86ISD::ADC: return "X86ISD::ADC";
18519 case X86ISD::SBB: return "X86ISD::SBB";
18520 case X86ISD::SMUL: return "X86ISD::SMUL";
18521 case X86ISD::UMUL: return "X86ISD::UMUL";
18522 case X86ISD::INC: return "X86ISD::INC";
18523 case X86ISD::DEC: return "X86ISD::DEC";
18524 case X86ISD::OR: return "X86ISD::OR";
18525 case X86ISD::XOR: return "X86ISD::XOR";
18526 case X86ISD::AND: return "X86ISD::AND";
18527 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18528 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18529 case X86ISD::PTEST: return "X86ISD::PTEST";
18530 case X86ISD::TESTP: return "X86ISD::TESTP";
18531 case X86ISD::TESTM: return "X86ISD::TESTM";
18532 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18533 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18534 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18535 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18536 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18537 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18538 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18539 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18540 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18541 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18542 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18543 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18544 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18545 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18546 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18547 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18548 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18549 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18550 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18551 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18552 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18553 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18554 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18555 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18556 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18557 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18558 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18559 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18560 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18561 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18562 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18563 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18564 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18565 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18566 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18567 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18568 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18569 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18570 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18571 case X86ISD::SAHF: return "X86ISD::SAHF";
18572 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18573 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18574 case X86ISD::FMADD: return "X86ISD::FMADD";
18575 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18576 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18577 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18578 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18579 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18580 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18581 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18582 case X86ISD::XTEST: return "X86ISD::XTEST";
18586 // isLegalAddressingMode - Return true if the addressing mode represented
18587 // by AM is legal for this target, for a load/store of the specified type.
18588 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18590 // X86 supports extremely general addressing modes.
18591 CodeModel::Model M = getTargetMachine().getCodeModel();
18592 Reloc::Model R = getTargetMachine().getRelocationModel();
18594 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18595 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18600 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18602 // If a reference to this global requires an extra load, we can't fold it.
18603 if (isGlobalStubReference(GVFlags))
18606 // If BaseGV requires a register for the PIC base, we cannot also have a
18607 // BaseReg specified.
18608 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18611 // If lower 4G is not available, then we must use rip-relative addressing.
18612 if ((M != CodeModel::Small || R != Reloc::Static) &&
18613 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18617 switch (AM.Scale) {
18623 // These scales always work.
18628 // These scales are formed with basereg+scalereg. Only accept if there is
18633 default: // Other stuff never works.
18640 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18641 unsigned Bits = Ty->getScalarSizeInBits();
18643 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18644 // particularly cheaper than those without.
18648 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18649 // variable shifts just as cheap as scalar ones.
18650 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18653 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18654 // fully general vector.
18658 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18659 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18661 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18662 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18663 return NumBits1 > NumBits2;
18666 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18667 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18670 if (!isTypeLegal(EVT::getEVT(Ty1)))
18673 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18675 // Assuming the caller doesn't have a zeroext or signext return parameter,
18676 // truncation all the way down to i1 is valid.
18680 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18681 return isInt<32>(Imm);
18684 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18685 // Can also use sub to handle negated immediates.
18686 return isInt<32>(Imm);
18689 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18690 if (!VT1.isInteger() || !VT2.isInteger())
18692 unsigned NumBits1 = VT1.getSizeInBits();
18693 unsigned NumBits2 = VT2.getSizeInBits();
18694 return NumBits1 > NumBits2;
18697 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18698 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18699 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18702 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18703 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18704 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18707 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18708 EVT VT1 = Val.getValueType();
18709 if (isZExtFree(VT1, VT2))
18712 if (Val.getOpcode() != ISD::LOAD)
18715 if (!VT1.isSimple() || !VT1.isInteger() ||
18716 !VT2.isSimple() || !VT2.isInteger())
18719 switch (VT1.getSimpleVT().SimpleTy) {
18724 // X86 has 8, 16, and 32-bit zero-extending loads.
18732 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18733 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18736 VT = VT.getScalarType();
18738 if (!VT.isSimple())
18741 switch (VT.getSimpleVT().SimpleTy) {
18752 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18753 // i16 instructions are longer (0x66 prefix) and potentially slower.
18754 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18757 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18758 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18759 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18760 /// are assumed to be legal.
18762 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18764 if (!VT.isSimple())
18767 MVT SVT = VT.getSimpleVT();
18769 // Very little shuffling can be done for 64-bit vectors right now.
18770 if (VT.getSizeInBits() == 64)
18773 // If this is a single-input shuffle with no 128 bit lane crossings we can
18774 // lower it into pshufb.
18775 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18776 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18777 bool isLegal = true;
18778 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18779 if (M[I] >= (int)SVT.getVectorNumElements() ||
18780 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18789 // FIXME: blends, shifts.
18790 return (SVT.getVectorNumElements() == 2 ||
18791 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18792 isMOVLMask(M, SVT) ||
18793 isMOVHLPSMask(M, SVT) ||
18794 isSHUFPMask(M, SVT) ||
18795 isPSHUFDMask(M, SVT) ||
18796 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18797 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18798 isPALIGNRMask(M, SVT, Subtarget) ||
18799 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18800 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18801 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18802 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18803 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18807 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18809 if (!VT.isSimple())
18812 MVT SVT = VT.getSimpleVT();
18813 unsigned NumElts = SVT.getVectorNumElements();
18814 // FIXME: This collection of masks seems suspect.
18817 if (NumElts == 4 && SVT.is128BitVector()) {
18818 return (isMOVLMask(Mask, SVT) ||
18819 isCommutedMOVLMask(Mask, SVT, true) ||
18820 isSHUFPMask(Mask, SVT) ||
18821 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18826 //===----------------------------------------------------------------------===//
18827 // X86 Scheduler Hooks
18828 //===----------------------------------------------------------------------===//
18830 /// Utility function to emit xbegin specifying the start of an RTM region.
18831 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18832 const TargetInstrInfo *TII) {
18833 DebugLoc DL = MI->getDebugLoc();
18835 const BasicBlock *BB = MBB->getBasicBlock();
18836 MachineFunction::iterator I = MBB;
18839 // For the v = xbegin(), we generate
18850 MachineBasicBlock *thisMBB = MBB;
18851 MachineFunction *MF = MBB->getParent();
18852 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18853 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18854 MF->insert(I, mainMBB);
18855 MF->insert(I, sinkMBB);
18857 // Transfer the remainder of BB and its successor edges to sinkMBB.
18858 sinkMBB->splice(sinkMBB->begin(), MBB,
18859 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18860 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18864 // # fallthrough to mainMBB
18865 // # abortion to sinkMBB
18866 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18867 thisMBB->addSuccessor(mainMBB);
18868 thisMBB->addSuccessor(sinkMBB);
18872 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18873 mainMBB->addSuccessor(sinkMBB);
18876 // EAX is live into the sinkMBB
18877 sinkMBB->addLiveIn(X86::EAX);
18878 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18879 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18882 MI->eraseFromParent();
18886 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18887 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18888 // in the .td file.
18889 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18890 const TargetInstrInfo *TII) {
18892 switch (MI->getOpcode()) {
18893 default: llvm_unreachable("illegal opcode!");
18894 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18895 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18896 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18897 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18898 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18899 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18900 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18901 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18904 DebugLoc dl = MI->getDebugLoc();
18905 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18907 unsigned NumArgs = MI->getNumOperands();
18908 for (unsigned i = 1; i < NumArgs; ++i) {
18909 MachineOperand &Op = MI->getOperand(i);
18910 if (!(Op.isReg() && Op.isImplicit()))
18911 MIB.addOperand(Op);
18913 if (MI->hasOneMemOperand())
18914 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18916 BuildMI(*BB, MI, dl,
18917 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18918 .addReg(X86::XMM0);
18920 MI->eraseFromParent();
18924 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18925 // defs in an instruction pattern
18926 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18927 const TargetInstrInfo *TII) {
18929 switch (MI->getOpcode()) {
18930 default: llvm_unreachable("illegal opcode!");
18931 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18932 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18933 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18934 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18935 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18936 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18937 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18938 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18941 DebugLoc dl = MI->getDebugLoc();
18942 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18944 unsigned NumArgs = MI->getNumOperands(); // remove the results
18945 for (unsigned i = 1; i < NumArgs; ++i) {
18946 MachineOperand &Op = MI->getOperand(i);
18947 if (!(Op.isReg() && Op.isImplicit()))
18948 MIB.addOperand(Op);
18950 if (MI->hasOneMemOperand())
18951 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18953 BuildMI(*BB, MI, dl,
18954 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18957 MI->eraseFromParent();
18961 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18962 const TargetInstrInfo *TII,
18963 const X86Subtarget* Subtarget) {
18964 DebugLoc dl = MI->getDebugLoc();
18966 // Address into RAX/EAX, other two args into ECX, EDX.
18967 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18968 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18969 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18970 for (int i = 0; i < X86::AddrNumOperands; ++i)
18971 MIB.addOperand(MI->getOperand(i));
18973 unsigned ValOps = X86::AddrNumOperands;
18974 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18975 .addReg(MI->getOperand(ValOps).getReg());
18976 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18977 .addReg(MI->getOperand(ValOps+1).getReg());
18979 // The instruction doesn't actually take any operands though.
18980 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18982 MI->eraseFromParent(); // The pseudo is gone now.
18986 MachineBasicBlock *
18987 X86TargetLowering::EmitVAARG64WithCustomInserter(
18989 MachineBasicBlock *MBB) const {
18990 // Emit va_arg instruction on X86-64.
18992 // Operands to this pseudo-instruction:
18993 // 0 ) Output : destination address (reg)
18994 // 1-5) Input : va_list address (addr, i64mem)
18995 // 6 ) ArgSize : Size (in bytes) of vararg type
18996 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18997 // 8 ) Align : Alignment of type
18998 // 9 ) EFLAGS (implicit-def)
19000 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19001 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19003 unsigned DestReg = MI->getOperand(0).getReg();
19004 MachineOperand &Base = MI->getOperand(1);
19005 MachineOperand &Scale = MI->getOperand(2);
19006 MachineOperand &Index = MI->getOperand(3);
19007 MachineOperand &Disp = MI->getOperand(4);
19008 MachineOperand &Segment = MI->getOperand(5);
19009 unsigned ArgSize = MI->getOperand(6).getImm();
19010 unsigned ArgMode = MI->getOperand(7).getImm();
19011 unsigned Align = MI->getOperand(8).getImm();
19013 // Memory Reference
19014 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19015 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19016 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19018 // Machine Information
19019 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19020 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19021 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19022 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19023 DebugLoc DL = MI->getDebugLoc();
19025 // struct va_list {
19028 // i64 overflow_area (address)
19029 // i64 reg_save_area (address)
19031 // sizeof(va_list) = 24
19032 // alignment(va_list) = 8
19034 unsigned TotalNumIntRegs = 6;
19035 unsigned TotalNumXMMRegs = 8;
19036 bool UseGPOffset = (ArgMode == 1);
19037 bool UseFPOffset = (ArgMode == 2);
19038 unsigned MaxOffset = TotalNumIntRegs * 8 +
19039 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19041 /* Align ArgSize to a multiple of 8 */
19042 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19043 bool NeedsAlign = (Align > 8);
19045 MachineBasicBlock *thisMBB = MBB;
19046 MachineBasicBlock *overflowMBB;
19047 MachineBasicBlock *offsetMBB;
19048 MachineBasicBlock *endMBB;
19050 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19051 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19052 unsigned OffsetReg = 0;
19054 if (!UseGPOffset && !UseFPOffset) {
19055 // If we only pull from the overflow region, we don't create a branch.
19056 // We don't need to alter control flow.
19057 OffsetDestReg = 0; // unused
19058 OverflowDestReg = DestReg;
19060 offsetMBB = nullptr;
19061 overflowMBB = thisMBB;
19064 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19065 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19066 // If not, pull from overflow_area. (branch to overflowMBB)
19071 // offsetMBB overflowMBB
19076 // Registers for the PHI in endMBB
19077 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19078 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19080 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19081 MachineFunction *MF = MBB->getParent();
19082 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19083 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19084 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19086 MachineFunction::iterator MBBIter = MBB;
19089 // Insert the new basic blocks
19090 MF->insert(MBBIter, offsetMBB);
19091 MF->insert(MBBIter, overflowMBB);
19092 MF->insert(MBBIter, endMBB);
19094 // Transfer the remainder of MBB and its successor edges to endMBB.
19095 endMBB->splice(endMBB->begin(), thisMBB,
19096 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19097 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19099 // Make offsetMBB and overflowMBB successors of thisMBB
19100 thisMBB->addSuccessor(offsetMBB);
19101 thisMBB->addSuccessor(overflowMBB);
19103 // endMBB is a successor of both offsetMBB and overflowMBB
19104 offsetMBB->addSuccessor(endMBB);
19105 overflowMBB->addSuccessor(endMBB);
19107 // Load the offset value into a register
19108 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19109 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19113 .addDisp(Disp, UseFPOffset ? 4 : 0)
19114 .addOperand(Segment)
19115 .setMemRefs(MMOBegin, MMOEnd);
19117 // Check if there is enough room left to pull this argument.
19118 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19120 .addImm(MaxOffset + 8 - ArgSizeA8);
19122 // Branch to "overflowMBB" if offset >= max
19123 // Fall through to "offsetMBB" otherwise
19124 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19125 .addMBB(overflowMBB);
19128 // In offsetMBB, emit code to use the reg_save_area.
19130 assert(OffsetReg != 0);
19132 // Read the reg_save_area address.
19133 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19134 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19139 .addOperand(Segment)
19140 .setMemRefs(MMOBegin, MMOEnd);
19142 // Zero-extend the offset
19143 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19144 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19147 .addImm(X86::sub_32bit);
19149 // Add the offset to the reg_save_area to get the final address.
19150 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19151 .addReg(OffsetReg64)
19152 .addReg(RegSaveReg);
19154 // Compute the offset for the next argument
19155 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19156 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19158 .addImm(UseFPOffset ? 16 : 8);
19160 // Store it back into the va_list.
19161 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19165 .addDisp(Disp, UseFPOffset ? 4 : 0)
19166 .addOperand(Segment)
19167 .addReg(NextOffsetReg)
19168 .setMemRefs(MMOBegin, MMOEnd);
19171 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19176 // Emit code to use overflow area
19179 // Load the overflow_area address into a register.
19180 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19181 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19186 .addOperand(Segment)
19187 .setMemRefs(MMOBegin, MMOEnd);
19189 // If we need to align it, do so. Otherwise, just copy the address
19190 // to OverflowDestReg.
19192 // Align the overflow address
19193 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19194 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19196 // aligned_addr = (addr + (align-1)) & ~(align-1)
19197 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19198 .addReg(OverflowAddrReg)
19201 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19203 .addImm(~(uint64_t)(Align-1));
19205 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19206 .addReg(OverflowAddrReg);
19209 // Compute the next overflow address after this argument.
19210 // (the overflow address should be kept 8-byte aligned)
19211 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19212 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19213 .addReg(OverflowDestReg)
19214 .addImm(ArgSizeA8);
19216 // Store the new overflow address.
19217 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19222 .addOperand(Segment)
19223 .addReg(NextAddrReg)
19224 .setMemRefs(MMOBegin, MMOEnd);
19226 // If we branched, emit the PHI to the front of endMBB.
19228 BuildMI(*endMBB, endMBB->begin(), DL,
19229 TII->get(X86::PHI), DestReg)
19230 .addReg(OffsetDestReg).addMBB(offsetMBB)
19231 .addReg(OverflowDestReg).addMBB(overflowMBB);
19234 // Erase the pseudo instruction
19235 MI->eraseFromParent();
19240 MachineBasicBlock *
19241 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19243 MachineBasicBlock *MBB) const {
19244 // Emit code to save XMM registers to the stack. The ABI says that the
19245 // number of registers to save is given in %al, so it's theoretically
19246 // possible to do an indirect jump trick to avoid saving all of them,
19247 // however this code takes a simpler approach and just executes all
19248 // of the stores if %al is non-zero. It's less code, and it's probably
19249 // easier on the hardware branch predictor, and stores aren't all that
19250 // expensive anyway.
19252 // Create the new basic blocks. One block contains all the XMM stores,
19253 // and one block is the final destination regardless of whether any
19254 // stores were performed.
19255 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19256 MachineFunction *F = MBB->getParent();
19257 MachineFunction::iterator MBBIter = MBB;
19259 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19260 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19261 F->insert(MBBIter, XMMSaveMBB);
19262 F->insert(MBBIter, EndMBB);
19264 // Transfer the remainder of MBB and its successor edges to EndMBB.
19265 EndMBB->splice(EndMBB->begin(), MBB,
19266 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19267 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19269 // The original block will now fall through to the XMM save block.
19270 MBB->addSuccessor(XMMSaveMBB);
19271 // The XMMSaveMBB will fall through to the end block.
19272 XMMSaveMBB->addSuccessor(EndMBB);
19274 // Now add the instructions.
19275 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19276 DebugLoc DL = MI->getDebugLoc();
19278 unsigned CountReg = MI->getOperand(0).getReg();
19279 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19280 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19282 if (!Subtarget->isTargetWin64()) {
19283 // If %al is 0, branch around the XMM save block.
19284 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19285 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19286 MBB->addSuccessor(EndMBB);
19289 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19290 // that was just emitted, but clearly shouldn't be "saved".
19291 assert((MI->getNumOperands() <= 3 ||
19292 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19293 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19294 && "Expected last argument to be EFLAGS");
19295 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19296 // In the XMM save block, save all the XMM argument registers.
19297 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19298 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19299 MachineMemOperand *MMO =
19300 F->getMachineMemOperand(
19301 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19302 MachineMemOperand::MOStore,
19303 /*Size=*/16, /*Align=*/16);
19304 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19305 .addFrameIndex(RegSaveFrameIndex)
19306 .addImm(/*Scale=*/1)
19307 .addReg(/*IndexReg=*/0)
19308 .addImm(/*Disp=*/Offset)
19309 .addReg(/*Segment=*/0)
19310 .addReg(MI->getOperand(i).getReg())
19311 .addMemOperand(MMO);
19314 MI->eraseFromParent(); // The pseudo instruction is gone now.
19319 // The EFLAGS operand of SelectItr might be missing a kill marker
19320 // because there were multiple uses of EFLAGS, and ISel didn't know
19321 // which to mark. Figure out whether SelectItr should have had a
19322 // kill marker, and set it if it should. Returns the correct kill
19324 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19325 MachineBasicBlock* BB,
19326 const TargetRegisterInfo* TRI) {
19327 // Scan forward through BB for a use/def of EFLAGS.
19328 MachineBasicBlock::iterator miI(std::next(SelectItr));
19329 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19330 const MachineInstr& mi = *miI;
19331 if (mi.readsRegister(X86::EFLAGS))
19333 if (mi.definesRegister(X86::EFLAGS))
19334 break; // Should have kill-flag - update below.
19337 // If we hit the end of the block, check whether EFLAGS is live into a
19339 if (miI == BB->end()) {
19340 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19341 sEnd = BB->succ_end();
19342 sItr != sEnd; ++sItr) {
19343 MachineBasicBlock* succ = *sItr;
19344 if (succ->isLiveIn(X86::EFLAGS))
19349 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19350 // out. SelectMI should have a kill flag on EFLAGS.
19351 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19355 MachineBasicBlock *
19356 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19357 MachineBasicBlock *BB) const {
19358 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19359 DebugLoc DL = MI->getDebugLoc();
19361 // To "insert" a SELECT_CC instruction, we actually have to insert the
19362 // diamond control-flow pattern. The incoming instruction knows the
19363 // destination vreg to set, the condition code register to branch on, the
19364 // true/false values to select between, and a branch opcode to use.
19365 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19366 MachineFunction::iterator It = BB;
19372 // cmpTY ccX, r1, r2
19374 // fallthrough --> copy0MBB
19375 MachineBasicBlock *thisMBB = BB;
19376 MachineFunction *F = BB->getParent();
19377 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19378 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19379 F->insert(It, copy0MBB);
19380 F->insert(It, sinkMBB);
19382 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19383 // live into the sink and copy blocks.
19384 const TargetRegisterInfo *TRI =
19385 BB->getParent()->getSubtarget().getRegisterInfo();
19386 if (!MI->killsRegister(X86::EFLAGS) &&
19387 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19388 copy0MBB->addLiveIn(X86::EFLAGS);
19389 sinkMBB->addLiveIn(X86::EFLAGS);
19392 // Transfer the remainder of BB and its successor edges to sinkMBB.
19393 sinkMBB->splice(sinkMBB->begin(), BB,
19394 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19395 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19397 // Add the true and fallthrough blocks as its successors.
19398 BB->addSuccessor(copy0MBB);
19399 BB->addSuccessor(sinkMBB);
19401 // Create the conditional branch instruction.
19403 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19404 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19407 // %FalseValue = ...
19408 // # fallthrough to sinkMBB
19409 copy0MBB->addSuccessor(sinkMBB);
19412 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19414 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19415 TII->get(X86::PHI), MI->getOperand(0).getReg())
19416 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19417 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19419 MI->eraseFromParent(); // The pseudo instruction is gone now.
19423 MachineBasicBlock *
19424 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19425 MachineBasicBlock *BB) const {
19426 MachineFunction *MF = BB->getParent();
19427 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19428 DebugLoc DL = MI->getDebugLoc();
19429 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19431 assert(MF->shouldSplitStack());
19433 const bool Is64Bit = Subtarget->is64Bit();
19434 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19436 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19437 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19440 // ... [Till the alloca]
19441 // If stacklet is not large enough, jump to mallocMBB
19444 // Allocate by subtracting from RSP
19445 // Jump to continueMBB
19448 // Allocate by call to runtime
19452 // [rest of original BB]
19455 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19456 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19457 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19459 MachineRegisterInfo &MRI = MF->getRegInfo();
19460 const TargetRegisterClass *AddrRegClass =
19461 getRegClassFor(getPointerTy());
19463 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19464 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19465 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19466 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19467 sizeVReg = MI->getOperand(1).getReg(),
19468 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19470 MachineFunction::iterator MBBIter = BB;
19473 MF->insert(MBBIter, bumpMBB);
19474 MF->insert(MBBIter, mallocMBB);
19475 MF->insert(MBBIter, continueMBB);
19477 continueMBB->splice(continueMBB->begin(), BB,
19478 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19479 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19481 // Add code to the main basic block to check if the stack limit has been hit,
19482 // and if so, jump to mallocMBB otherwise to bumpMBB.
19483 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19484 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19485 .addReg(tmpSPVReg).addReg(sizeVReg);
19486 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19487 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19488 .addReg(SPLimitVReg);
19489 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19491 // bumpMBB simply decreases the stack pointer, since we know the current
19492 // stacklet has enough space.
19493 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19494 .addReg(SPLimitVReg);
19495 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19496 .addReg(SPLimitVReg);
19497 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19499 // Calls into a routine in libgcc to allocate more space from the heap.
19500 const uint32_t *RegMask = MF->getTarget()
19501 .getSubtargetImpl()
19502 ->getRegisterInfo()
19503 ->getCallPreservedMask(CallingConv::C);
19505 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19507 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19508 .addExternalSymbol("__morestack_allocate_stack_space")
19509 .addRegMask(RegMask)
19510 .addReg(X86::RDI, RegState::Implicit)
19511 .addReg(X86::RAX, RegState::ImplicitDefine);
19512 } else if (Is64Bit) {
19513 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19515 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19516 .addExternalSymbol("__morestack_allocate_stack_space")
19517 .addRegMask(RegMask)
19518 .addReg(X86::EDI, RegState::Implicit)
19519 .addReg(X86::EAX, RegState::ImplicitDefine);
19521 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19523 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19524 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19525 .addExternalSymbol("__morestack_allocate_stack_space")
19526 .addRegMask(RegMask)
19527 .addReg(X86::EAX, RegState::ImplicitDefine);
19531 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19534 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19535 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19536 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19538 // Set up the CFG correctly.
19539 BB->addSuccessor(bumpMBB);
19540 BB->addSuccessor(mallocMBB);
19541 mallocMBB->addSuccessor(continueMBB);
19542 bumpMBB->addSuccessor(continueMBB);
19544 // Take care of the PHI nodes.
19545 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19546 MI->getOperand(0).getReg())
19547 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19548 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19550 // Delete the original pseudo instruction.
19551 MI->eraseFromParent();
19554 return continueMBB;
19557 MachineBasicBlock *
19558 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19559 MachineBasicBlock *BB) const {
19560 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19561 DebugLoc DL = MI->getDebugLoc();
19563 assert(!Subtarget->isTargetMacho());
19565 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19566 // non-trivial part is impdef of ESP.
19568 if (Subtarget->isTargetWin64()) {
19569 if (Subtarget->isTargetCygMing()) {
19570 // ___chkstk(Mingw64):
19571 // Clobbers R10, R11, RAX and EFLAGS.
19573 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19574 .addExternalSymbol("___chkstk")
19575 .addReg(X86::RAX, RegState::Implicit)
19576 .addReg(X86::RSP, RegState::Implicit)
19577 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19578 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19579 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19581 // __chkstk(MSVCRT): does not update stack pointer.
19582 // Clobbers R10, R11 and EFLAGS.
19583 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19584 .addExternalSymbol("__chkstk")
19585 .addReg(X86::RAX, RegState::Implicit)
19586 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19587 // RAX has the offset to be subtracted from RSP.
19588 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19593 const char *StackProbeSymbol =
19594 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19596 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19597 .addExternalSymbol(StackProbeSymbol)
19598 .addReg(X86::EAX, RegState::Implicit)
19599 .addReg(X86::ESP, RegState::Implicit)
19600 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19601 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19602 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19605 MI->eraseFromParent(); // The pseudo instruction is gone now.
19609 MachineBasicBlock *
19610 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19611 MachineBasicBlock *BB) const {
19612 // This is pretty easy. We're taking the value that we received from
19613 // our load from the relocation, sticking it in either RDI (x86-64)
19614 // or EAX and doing an indirect call. The return value will then
19615 // be in the normal return register.
19616 MachineFunction *F = BB->getParent();
19617 const X86InstrInfo *TII =
19618 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19619 DebugLoc DL = MI->getDebugLoc();
19621 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19622 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19624 // Get a register mask for the lowered call.
19625 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19626 // proper register mask.
19627 const uint32_t *RegMask = F->getTarget()
19628 .getSubtargetImpl()
19629 ->getRegisterInfo()
19630 ->getCallPreservedMask(CallingConv::C);
19631 if (Subtarget->is64Bit()) {
19632 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19633 TII->get(X86::MOV64rm), X86::RDI)
19635 .addImm(0).addReg(0)
19636 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19637 MI->getOperand(3).getTargetFlags())
19639 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19640 addDirectMem(MIB, X86::RDI);
19641 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19642 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19643 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19644 TII->get(X86::MOV32rm), X86::EAX)
19646 .addImm(0).addReg(0)
19647 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19648 MI->getOperand(3).getTargetFlags())
19650 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19651 addDirectMem(MIB, X86::EAX);
19652 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19654 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19655 TII->get(X86::MOV32rm), X86::EAX)
19656 .addReg(TII->getGlobalBaseReg(F))
19657 .addImm(0).addReg(0)
19658 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19659 MI->getOperand(3).getTargetFlags())
19661 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19662 addDirectMem(MIB, X86::EAX);
19663 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19666 MI->eraseFromParent(); // The pseudo instruction is gone now.
19670 MachineBasicBlock *
19671 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19672 MachineBasicBlock *MBB) const {
19673 DebugLoc DL = MI->getDebugLoc();
19674 MachineFunction *MF = MBB->getParent();
19675 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19676 MachineRegisterInfo &MRI = MF->getRegInfo();
19678 const BasicBlock *BB = MBB->getBasicBlock();
19679 MachineFunction::iterator I = MBB;
19682 // Memory Reference
19683 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19684 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19687 unsigned MemOpndSlot = 0;
19689 unsigned CurOp = 0;
19691 DstReg = MI->getOperand(CurOp++).getReg();
19692 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19693 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19694 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19695 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19697 MemOpndSlot = CurOp;
19699 MVT PVT = getPointerTy();
19700 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19701 "Invalid Pointer Size!");
19703 // For v = setjmp(buf), we generate
19706 // buf[LabelOffset] = restoreMBB
19707 // SjLjSetup restoreMBB
19713 // v = phi(main, restore)
19718 MachineBasicBlock *thisMBB = MBB;
19719 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19720 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19721 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19722 MF->insert(I, mainMBB);
19723 MF->insert(I, sinkMBB);
19724 MF->push_back(restoreMBB);
19726 MachineInstrBuilder MIB;
19728 // Transfer the remainder of BB and its successor edges to sinkMBB.
19729 sinkMBB->splice(sinkMBB->begin(), MBB,
19730 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19731 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19734 unsigned PtrStoreOpc = 0;
19735 unsigned LabelReg = 0;
19736 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19737 Reloc::Model RM = MF->getTarget().getRelocationModel();
19738 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19739 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19741 // Prepare IP either in reg or imm.
19742 if (!UseImmLabel) {
19743 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19744 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19745 LabelReg = MRI.createVirtualRegister(PtrRC);
19746 if (Subtarget->is64Bit()) {
19747 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19751 .addMBB(restoreMBB)
19754 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19755 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19756 .addReg(XII->getGlobalBaseReg(MF))
19759 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19763 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19765 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19766 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19767 if (i == X86::AddrDisp)
19768 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19770 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19773 MIB.addReg(LabelReg);
19775 MIB.addMBB(restoreMBB);
19776 MIB.setMemRefs(MMOBegin, MMOEnd);
19778 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19779 .addMBB(restoreMBB);
19781 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19782 MF->getSubtarget().getRegisterInfo());
19783 MIB.addRegMask(RegInfo->getNoPreservedMask());
19784 thisMBB->addSuccessor(mainMBB);
19785 thisMBB->addSuccessor(restoreMBB);
19789 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19790 mainMBB->addSuccessor(sinkMBB);
19793 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19794 TII->get(X86::PHI), DstReg)
19795 .addReg(mainDstReg).addMBB(mainMBB)
19796 .addReg(restoreDstReg).addMBB(restoreMBB);
19799 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19800 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19801 restoreMBB->addSuccessor(sinkMBB);
19803 MI->eraseFromParent();
19807 MachineBasicBlock *
19808 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19809 MachineBasicBlock *MBB) const {
19810 DebugLoc DL = MI->getDebugLoc();
19811 MachineFunction *MF = MBB->getParent();
19812 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19813 MachineRegisterInfo &MRI = MF->getRegInfo();
19815 // Memory Reference
19816 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19817 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19819 MVT PVT = getPointerTy();
19820 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19821 "Invalid Pointer Size!");
19823 const TargetRegisterClass *RC =
19824 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19825 unsigned Tmp = MRI.createVirtualRegister(RC);
19826 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19827 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19828 MF->getSubtarget().getRegisterInfo());
19829 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19830 unsigned SP = RegInfo->getStackRegister();
19832 MachineInstrBuilder MIB;
19834 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19835 const int64_t SPOffset = 2 * PVT.getStoreSize();
19837 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19838 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19841 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19842 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19843 MIB.addOperand(MI->getOperand(i));
19844 MIB.setMemRefs(MMOBegin, MMOEnd);
19846 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19847 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19848 if (i == X86::AddrDisp)
19849 MIB.addDisp(MI->getOperand(i), LabelOffset);
19851 MIB.addOperand(MI->getOperand(i));
19853 MIB.setMemRefs(MMOBegin, MMOEnd);
19855 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19856 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19857 if (i == X86::AddrDisp)
19858 MIB.addDisp(MI->getOperand(i), SPOffset);
19860 MIB.addOperand(MI->getOperand(i));
19862 MIB.setMemRefs(MMOBegin, MMOEnd);
19864 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19866 MI->eraseFromParent();
19870 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19871 // accumulator loops. Writing back to the accumulator allows the coalescer
19872 // to remove extra copies in the loop.
19873 MachineBasicBlock *
19874 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19875 MachineBasicBlock *MBB) const {
19876 MachineOperand &AddendOp = MI->getOperand(3);
19878 // Bail out early if the addend isn't a register - we can't switch these.
19879 if (!AddendOp.isReg())
19882 MachineFunction &MF = *MBB->getParent();
19883 MachineRegisterInfo &MRI = MF.getRegInfo();
19885 // Check whether the addend is defined by a PHI:
19886 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19887 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19888 if (!AddendDef.isPHI())
19891 // Look for the following pattern:
19893 // %addend = phi [%entry, 0], [%loop, %result]
19895 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19899 // %addend = phi [%entry, 0], [%loop, %result]
19901 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19903 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19904 assert(AddendDef.getOperand(i).isReg());
19905 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19906 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19907 if (&PHISrcInst == MI) {
19908 // Found a matching instruction.
19909 unsigned NewFMAOpc = 0;
19910 switch (MI->getOpcode()) {
19911 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19912 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19913 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19914 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19915 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19916 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19917 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19918 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19919 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19920 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19921 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19922 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19923 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19924 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19925 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19926 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19927 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19928 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19929 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19930 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19931 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19932 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19933 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19934 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19935 default: llvm_unreachable("Unrecognized FMA variant.");
19938 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19939 MachineInstrBuilder MIB =
19940 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19941 .addOperand(MI->getOperand(0))
19942 .addOperand(MI->getOperand(3))
19943 .addOperand(MI->getOperand(2))
19944 .addOperand(MI->getOperand(1));
19945 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19946 MI->eraseFromParent();
19953 MachineBasicBlock *
19954 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19955 MachineBasicBlock *BB) const {
19956 switch (MI->getOpcode()) {
19957 default: llvm_unreachable("Unexpected instr type to insert");
19958 case X86::TAILJMPd64:
19959 case X86::TAILJMPr64:
19960 case X86::TAILJMPm64:
19961 llvm_unreachable("TAILJMP64 would not be touched here.");
19962 case X86::TCRETURNdi64:
19963 case X86::TCRETURNri64:
19964 case X86::TCRETURNmi64:
19966 case X86::WIN_ALLOCA:
19967 return EmitLoweredWinAlloca(MI, BB);
19968 case X86::SEG_ALLOCA_32:
19969 case X86::SEG_ALLOCA_64:
19970 return EmitLoweredSegAlloca(MI, BB);
19971 case X86::TLSCall_32:
19972 case X86::TLSCall_64:
19973 return EmitLoweredTLSCall(MI, BB);
19974 case X86::CMOV_GR8:
19975 case X86::CMOV_FR32:
19976 case X86::CMOV_FR64:
19977 case X86::CMOV_V4F32:
19978 case X86::CMOV_V2F64:
19979 case X86::CMOV_V2I64:
19980 case X86::CMOV_V8F32:
19981 case X86::CMOV_V4F64:
19982 case X86::CMOV_V4I64:
19983 case X86::CMOV_V16F32:
19984 case X86::CMOV_V8F64:
19985 case X86::CMOV_V8I64:
19986 case X86::CMOV_GR16:
19987 case X86::CMOV_GR32:
19988 case X86::CMOV_RFP32:
19989 case X86::CMOV_RFP64:
19990 case X86::CMOV_RFP80:
19991 return EmitLoweredSelect(MI, BB);
19993 case X86::FP32_TO_INT16_IN_MEM:
19994 case X86::FP32_TO_INT32_IN_MEM:
19995 case X86::FP32_TO_INT64_IN_MEM:
19996 case X86::FP64_TO_INT16_IN_MEM:
19997 case X86::FP64_TO_INT32_IN_MEM:
19998 case X86::FP64_TO_INT64_IN_MEM:
19999 case X86::FP80_TO_INT16_IN_MEM:
20000 case X86::FP80_TO_INT32_IN_MEM:
20001 case X86::FP80_TO_INT64_IN_MEM: {
20002 MachineFunction *F = BB->getParent();
20003 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20004 DebugLoc DL = MI->getDebugLoc();
20006 // Change the floating point control register to use "round towards zero"
20007 // mode when truncating to an integer value.
20008 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20009 addFrameReference(BuildMI(*BB, MI, DL,
20010 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20012 // Load the old value of the high byte of the control word...
20014 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20015 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20018 // Set the high part to be round to zero...
20019 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20022 // Reload the modified control word now...
20023 addFrameReference(BuildMI(*BB, MI, DL,
20024 TII->get(X86::FLDCW16m)), CWFrameIdx);
20026 // Restore the memory image of control word to original value
20027 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20030 // Get the X86 opcode to use.
20032 switch (MI->getOpcode()) {
20033 default: llvm_unreachable("illegal opcode!");
20034 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20035 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20036 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20037 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20038 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20039 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20040 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20041 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20042 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20046 MachineOperand &Op = MI->getOperand(0);
20048 AM.BaseType = X86AddressMode::RegBase;
20049 AM.Base.Reg = Op.getReg();
20051 AM.BaseType = X86AddressMode::FrameIndexBase;
20052 AM.Base.FrameIndex = Op.getIndex();
20054 Op = MI->getOperand(1);
20056 AM.Scale = Op.getImm();
20057 Op = MI->getOperand(2);
20059 AM.IndexReg = Op.getImm();
20060 Op = MI->getOperand(3);
20061 if (Op.isGlobal()) {
20062 AM.GV = Op.getGlobal();
20064 AM.Disp = Op.getImm();
20066 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20067 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20069 // Reload the original control word now.
20070 addFrameReference(BuildMI(*BB, MI, DL,
20071 TII->get(X86::FLDCW16m)), CWFrameIdx);
20073 MI->eraseFromParent(); // The pseudo instruction is gone now.
20076 // String/text processing lowering.
20077 case X86::PCMPISTRM128REG:
20078 case X86::VPCMPISTRM128REG:
20079 case X86::PCMPISTRM128MEM:
20080 case X86::VPCMPISTRM128MEM:
20081 case X86::PCMPESTRM128REG:
20082 case X86::VPCMPESTRM128REG:
20083 case X86::PCMPESTRM128MEM:
20084 case X86::VPCMPESTRM128MEM:
20085 assert(Subtarget->hasSSE42() &&
20086 "Target must have SSE4.2 or AVX features enabled");
20087 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20089 // String/text processing lowering.
20090 case X86::PCMPISTRIREG:
20091 case X86::VPCMPISTRIREG:
20092 case X86::PCMPISTRIMEM:
20093 case X86::VPCMPISTRIMEM:
20094 case X86::PCMPESTRIREG:
20095 case X86::VPCMPESTRIREG:
20096 case X86::PCMPESTRIMEM:
20097 case X86::VPCMPESTRIMEM:
20098 assert(Subtarget->hasSSE42() &&
20099 "Target must have SSE4.2 or AVX features enabled");
20100 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20102 // Thread synchronization.
20104 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20109 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20111 case X86::VASTART_SAVE_XMM_REGS:
20112 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20114 case X86::VAARG_64:
20115 return EmitVAARG64WithCustomInserter(MI, BB);
20117 case X86::EH_SjLj_SetJmp32:
20118 case X86::EH_SjLj_SetJmp64:
20119 return emitEHSjLjSetJmp(MI, BB);
20121 case X86::EH_SjLj_LongJmp32:
20122 case X86::EH_SjLj_LongJmp64:
20123 return emitEHSjLjLongJmp(MI, BB);
20125 case TargetOpcode::STACKMAP:
20126 case TargetOpcode::PATCHPOINT:
20127 return emitPatchPoint(MI, BB);
20129 case X86::VFMADDPDr213r:
20130 case X86::VFMADDPSr213r:
20131 case X86::VFMADDSDr213r:
20132 case X86::VFMADDSSr213r:
20133 case X86::VFMSUBPDr213r:
20134 case X86::VFMSUBPSr213r:
20135 case X86::VFMSUBSDr213r:
20136 case X86::VFMSUBSSr213r:
20137 case X86::VFNMADDPDr213r:
20138 case X86::VFNMADDPSr213r:
20139 case X86::VFNMADDSDr213r:
20140 case X86::VFNMADDSSr213r:
20141 case X86::VFNMSUBPDr213r:
20142 case X86::VFNMSUBPSr213r:
20143 case X86::VFNMSUBSDr213r:
20144 case X86::VFNMSUBSSr213r:
20145 case X86::VFMADDPDr213rY:
20146 case X86::VFMADDPSr213rY:
20147 case X86::VFMSUBPDr213rY:
20148 case X86::VFMSUBPSr213rY:
20149 case X86::VFNMADDPDr213rY:
20150 case X86::VFNMADDPSr213rY:
20151 case X86::VFNMSUBPDr213rY:
20152 case X86::VFNMSUBPSr213rY:
20153 return emitFMA3Instr(MI, BB);
20157 //===----------------------------------------------------------------------===//
20158 // X86 Optimization Hooks
20159 //===----------------------------------------------------------------------===//
20161 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20164 const SelectionDAG &DAG,
20165 unsigned Depth) const {
20166 unsigned BitWidth = KnownZero.getBitWidth();
20167 unsigned Opc = Op.getOpcode();
20168 assert((Opc >= ISD::BUILTIN_OP_END ||
20169 Opc == ISD::INTRINSIC_WO_CHAIN ||
20170 Opc == ISD::INTRINSIC_W_CHAIN ||
20171 Opc == ISD::INTRINSIC_VOID) &&
20172 "Should use MaskedValueIsZero if you don't know whether Op"
20173 " is a target node!");
20175 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20189 // These nodes' second result is a boolean.
20190 if (Op.getResNo() == 0)
20193 case X86ISD::SETCC:
20194 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20196 case ISD::INTRINSIC_WO_CHAIN: {
20197 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20198 unsigned NumLoBits = 0;
20201 case Intrinsic::x86_sse_movmsk_ps:
20202 case Intrinsic::x86_avx_movmsk_ps_256:
20203 case Intrinsic::x86_sse2_movmsk_pd:
20204 case Intrinsic::x86_avx_movmsk_pd_256:
20205 case Intrinsic::x86_mmx_pmovmskb:
20206 case Intrinsic::x86_sse2_pmovmskb_128:
20207 case Intrinsic::x86_avx2_pmovmskb: {
20208 // High bits of movmskp{s|d}, pmovmskb are known zero.
20210 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20211 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20212 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20213 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20214 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20215 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20216 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20217 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20219 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20228 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20230 const SelectionDAG &,
20231 unsigned Depth) const {
20232 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20233 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20234 return Op.getValueType().getScalarType().getSizeInBits();
20240 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20241 /// node is a GlobalAddress + offset.
20242 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20243 const GlobalValue* &GA,
20244 int64_t &Offset) const {
20245 if (N->getOpcode() == X86ISD::Wrapper) {
20246 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20247 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20248 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20252 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20255 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20256 /// same as extracting the high 128-bit part of 256-bit vector and then
20257 /// inserting the result into the low part of a new 256-bit vector
20258 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20259 EVT VT = SVOp->getValueType(0);
20260 unsigned NumElems = VT.getVectorNumElements();
20262 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20263 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20264 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20265 SVOp->getMaskElt(j) >= 0)
20271 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20272 /// same as extracting the low 128-bit part of 256-bit vector and then
20273 /// inserting the result into the high part of a new 256-bit vector
20274 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20275 EVT VT = SVOp->getValueType(0);
20276 unsigned NumElems = VT.getVectorNumElements();
20278 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20279 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20280 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20281 SVOp->getMaskElt(j) >= 0)
20287 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20288 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20289 TargetLowering::DAGCombinerInfo &DCI,
20290 const X86Subtarget* Subtarget) {
20292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20293 SDValue V1 = SVOp->getOperand(0);
20294 SDValue V2 = SVOp->getOperand(1);
20295 EVT VT = SVOp->getValueType(0);
20296 unsigned NumElems = VT.getVectorNumElements();
20298 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20299 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20303 // V UNDEF BUILD_VECTOR UNDEF
20305 // CONCAT_VECTOR CONCAT_VECTOR
20308 // RESULT: V + zero extended
20310 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20311 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20312 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20315 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20318 // To match the shuffle mask, the first half of the mask should
20319 // be exactly the first vector, and all the rest a splat with the
20320 // first element of the second one.
20321 for (unsigned i = 0; i != NumElems/2; ++i)
20322 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20323 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20326 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20327 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20328 if (Ld->hasNUsesOfValue(1, 0)) {
20329 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20330 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20332 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20334 Ld->getPointerInfo(),
20335 Ld->getAlignment(),
20336 false/*isVolatile*/, true/*ReadMem*/,
20337 false/*WriteMem*/);
20339 // Make sure the newly-created LOAD is in the same position as Ld in
20340 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20341 // and update uses of Ld's output chain to use the TokenFactor.
20342 if (Ld->hasAnyUseOfValue(1)) {
20343 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20344 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20345 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20346 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20347 SDValue(ResNode.getNode(), 1));
20350 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20354 // Emit a zeroed vector and insert the desired subvector on its
20356 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20357 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20358 return DCI.CombineTo(N, InsV);
20361 //===--------------------------------------------------------------------===//
20362 // Combine some shuffles into subvector extracts and inserts:
20365 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20366 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20367 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20368 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20369 return DCI.CombineTo(N, InsV);
20372 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20373 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20374 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20375 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20376 return DCI.CombineTo(N, InsV);
20382 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20385 /// This is the leaf of the recursive combinine below. When we have found some
20386 /// chain of single-use x86 shuffle instructions and accumulated the combined
20387 /// shuffle mask represented by them, this will try to pattern match that mask
20388 /// into either a single instruction if there is a special purpose instruction
20389 /// for this operation, or into a PSHUFB instruction which is a fully general
20390 /// instruction but should only be used to replace chains over a certain depth.
20391 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20392 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20393 TargetLowering::DAGCombinerInfo &DCI,
20394 const X86Subtarget *Subtarget) {
20395 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20397 // Find the operand that enters the chain. Note that multiple uses are OK
20398 // here, we're not going to remove the operand we find.
20399 SDValue Input = Op.getOperand(0);
20400 while (Input.getOpcode() == ISD::BITCAST)
20401 Input = Input.getOperand(0);
20403 MVT VT = Input.getSimpleValueType();
20404 MVT RootVT = Root.getSimpleValueType();
20407 // Just remove no-op shuffle masks.
20408 if (Mask.size() == 1) {
20409 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20414 // Use the float domain if the operand type is a floating point type.
20415 bool FloatDomain = VT.isFloatingPoint();
20417 // For floating point shuffles, we don't have free copies in the shuffle
20418 // instructions or the ability to load as part of the instruction, so
20419 // canonicalize their shuffles to UNPCK or MOV variants.
20421 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20422 // vectors because it can have a load folded into it that UNPCK cannot. This
20423 // doesn't preclude something switching to the shorter encoding post-RA.
20425 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20426 bool Lo = Mask.equals(0, 0);
20429 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20430 // is no slower than UNPCKLPD but has the option to fold the input operand
20431 // into even an unaligned memory load.
20432 if (Lo && Subtarget->hasSSE3()) {
20433 Shuffle = X86ISD::MOVDDUP;
20434 ShuffleVT = MVT::v2f64;
20436 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20437 // than the UNPCK variants.
20438 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20439 ShuffleVT = MVT::v4f32;
20441 if (Depth == 1 && Root->getOpcode() == Shuffle)
20442 return false; // Nothing to do!
20443 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20444 DCI.AddToWorklist(Op.getNode());
20445 if (Shuffle == X86ISD::MOVDDUP)
20446 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20448 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20449 DCI.AddToWorklist(Op.getNode());
20450 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20454 if (Subtarget->hasSSE3() &&
20455 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20456 bool Lo = Mask.equals(0, 0, 2, 2);
20457 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20458 MVT ShuffleVT = MVT::v4f32;
20459 if (Depth == 1 && Root->getOpcode() == Shuffle)
20460 return false; // Nothing to do!
20461 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20462 DCI.AddToWorklist(Op.getNode());
20463 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20464 DCI.AddToWorklist(Op.getNode());
20465 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20469 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20470 bool Lo = Mask.equals(0, 0, 1, 1);
20471 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20472 MVT ShuffleVT = MVT::v4f32;
20473 if (Depth == 1 && Root->getOpcode() == Shuffle)
20474 return false; // Nothing to do!
20475 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20476 DCI.AddToWorklist(Op.getNode());
20477 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20478 DCI.AddToWorklist(Op.getNode());
20479 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20485 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20486 // variants as none of these have single-instruction variants that are
20487 // superior to the UNPCK formulation.
20488 if (!FloatDomain &&
20489 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20490 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20491 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20492 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20494 bool Lo = Mask[0] == 0;
20495 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20496 if (Depth == 1 && Root->getOpcode() == Shuffle)
20497 return false; // Nothing to do!
20499 switch (Mask.size()) {
20501 ShuffleVT = MVT::v8i16;
20504 ShuffleVT = MVT::v16i8;
20507 llvm_unreachable("Impossible mask size!");
20509 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20510 DCI.AddToWorklist(Op.getNode());
20511 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20512 DCI.AddToWorklist(Op.getNode());
20513 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20518 // Don't try to re-form single instruction chains under any circumstances now
20519 // that we've done encoding canonicalization for them.
20523 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20524 // can replace them with a single PSHUFB instruction profitably. Intel's
20525 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20526 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20527 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20528 SmallVector<SDValue, 16> PSHUFBMask;
20529 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20530 int Ratio = 16 / Mask.size();
20531 for (unsigned i = 0; i < 16; ++i) {
20532 if (Mask[i / Ratio] == SM_SentinelUndef) {
20533 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20536 int M = Mask[i / Ratio] != SM_SentinelZero
20537 ? Ratio * Mask[i / Ratio] + i % Ratio
20539 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20541 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20542 DCI.AddToWorklist(Op.getNode());
20543 SDValue PSHUFBMaskOp =
20544 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20545 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20546 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20547 DCI.AddToWorklist(Op.getNode());
20548 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20553 // Failed to find any combines.
20557 /// \brief Fully generic combining of x86 shuffle instructions.
20559 /// This should be the last combine run over the x86 shuffle instructions. Once
20560 /// they have been fully optimized, this will recursively consider all chains
20561 /// of single-use shuffle instructions, build a generic model of the cumulative
20562 /// shuffle operation, and check for simpler instructions which implement this
20563 /// operation. We use this primarily for two purposes:
20565 /// 1) Collapse generic shuffles to specialized single instructions when
20566 /// equivalent. In most cases, this is just an encoding size win, but
20567 /// sometimes we will collapse multiple generic shuffles into a single
20568 /// special-purpose shuffle.
20569 /// 2) Look for sequences of shuffle instructions with 3 or more total
20570 /// instructions, and replace them with the slightly more expensive SSSE3
20571 /// PSHUFB instruction if available. We do this as the last combining step
20572 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20573 /// a suitable short sequence of other instructions. The PHUFB will either
20574 /// use a register or have to read from memory and so is slightly (but only
20575 /// slightly) more expensive than the other shuffle instructions.
20577 /// Because this is inherently a quadratic operation (for each shuffle in
20578 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20579 /// This should never be an issue in practice as the shuffle lowering doesn't
20580 /// produce sequences of more than 8 instructions.
20582 /// FIXME: We will currently miss some cases where the redundant shuffling
20583 /// would simplify under the threshold for PSHUFB formation because of
20584 /// combine-ordering. To fix this, we should do the redundant instruction
20585 /// combining in this recursive walk.
20586 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20587 ArrayRef<int> RootMask,
20588 int Depth, bool HasPSHUFB,
20590 TargetLowering::DAGCombinerInfo &DCI,
20591 const X86Subtarget *Subtarget) {
20592 // Bound the depth of our recursive combine because this is ultimately
20593 // quadratic in nature.
20597 // Directly rip through bitcasts to find the underlying operand.
20598 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20599 Op = Op.getOperand(0);
20601 MVT VT = Op.getSimpleValueType();
20602 if (!VT.isVector())
20603 return false; // Bail if we hit a non-vector.
20604 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20605 // version should be added.
20606 if (VT.getSizeInBits() != 128)
20609 assert(Root.getSimpleValueType().isVector() &&
20610 "Shuffles operate on vector types!");
20611 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20612 "Can only combine shuffles of the same vector register size.");
20614 if (!isTargetShuffle(Op.getOpcode()))
20616 SmallVector<int, 16> OpMask;
20618 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20619 // We only can combine unary shuffles which we can decode the mask for.
20620 if (!HaveMask || !IsUnary)
20623 assert(VT.getVectorNumElements() == OpMask.size() &&
20624 "Different mask size from vector size!");
20625 assert(((RootMask.size() > OpMask.size() &&
20626 RootMask.size() % OpMask.size() == 0) ||
20627 (OpMask.size() > RootMask.size() &&
20628 OpMask.size() % RootMask.size() == 0) ||
20629 OpMask.size() == RootMask.size()) &&
20630 "The smaller number of elements must divide the larger.");
20631 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20632 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20633 assert(((RootRatio == 1 && OpRatio == 1) ||
20634 (RootRatio == 1) != (OpRatio == 1)) &&
20635 "Must not have a ratio for both incoming and op masks!");
20637 SmallVector<int, 16> Mask;
20638 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20640 // Merge this shuffle operation's mask into our accumulated mask. Note that
20641 // this shuffle's mask will be the first applied to the input, followed by the
20642 // root mask to get us all the way to the root value arrangement. The reason
20643 // for this order is that we are recursing up the operation chain.
20644 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20645 int RootIdx = i / RootRatio;
20646 if (RootMask[RootIdx] < 0) {
20647 // This is a zero or undef lane, we're done.
20648 Mask.push_back(RootMask[RootIdx]);
20652 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20653 int OpIdx = RootMaskedIdx / OpRatio;
20654 if (OpMask[OpIdx] < 0) {
20655 // The incoming lanes are zero or undef, it doesn't matter which ones we
20657 Mask.push_back(OpMask[OpIdx]);
20661 // Ok, we have non-zero lanes, map them through.
20662 Mask.push_back(OpMask[OpIdx] * OpRatio +
20663 RootMaskedIdx % OpRatio);
20666 // See if we can recurse into the operand to combine more things.
20667 switch (Op.getOpcode()) {
20668 case X86ISD::PSHUFB:
20670 case X86ISD::PSHUFD:
20671 case X86ISD::PSHUFHW:
20672 case X86ISD::PSHUFLW:
20673 if (Op.getOperand(0).hasOneUse() &&
20674 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20675 HasPSHUFB, DAG, DCI, Subtarget))
20679 case X86ISD::UNPCKL:
20680 case X86ISD::UNPCKH:
20681 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20682 // We can't check for single use, we have to check that this shuffle is the only user.
20683 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20684 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20685 HasPSHUFB, DAG, DCI, Subtarget))
20690 // Minor canonicalization of the accumulated shuffle mask to make it easier
20691 // to match below. All this does is detect masks with squential pairs of
20692 // elements, and shrink them to the half-width mask. It does this in a loop
20693 // so it will reduce the size of the mask to the minimal width mask which
20694 // performs an equivalent shuffle.
20695 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20696 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20697 Mask[i] = Mask[2 * i] / 2;
20698 Mask.resize(Mask.size() / 2);
20701 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20705 /// \brief Get the PSHUF-style mask from PSHUF node.
20707 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20708 /// PSHUF-style masks that can be reused with such instructions.
20709 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20710 SmallVector<int, 4> Mask;
20712 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20716 switch (N.getOpcode()) {
20717 case X86ISD::PSHUFD:
20719 case X86ISD::PSHUFLW:
20722 case X86ISD::PSHUFHW:
20723 Mask.erase(Mask.begin(), Mask.begin() + 4);
20724 for (int &M : Mask)
20728 llvm_unreachable("No valid shuffle instruction found!");
20732 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20734 /// We walk up the chain and look for a combinable shuffle, skipping over
20735 /// shuffles that we could hoist this shuffle's transformation past without
20736 /// altering anything.
20738 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20740 TargetLowering::DAGCombinerInfo &DCI) {
20741 assert(N.getOpcode() == X86ISD::PSHUFD &&
20742 "Called with something other than an x86 128-bit half shuffle!");
20745 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20746 // of the shuffles in the chain so that we can form a fresh chain to replace
20748 SmallVector<SDValue, 8> Chain;
20749 SDValue V = N.getOperand(0);
20750 for (; V.hasOneUse(); V = V.getOperand(0)) {
20751 switch (V.getOpcode()) {
20753 return SDValue(); // Nothing combined!
20756 // Skip bitcasts as we always know the type for the target specific
20760 case X86ISD::PSHUFD:
20761 // Found another dword shuffle.
20764 case X86ISD::PSHUFLW:
20765 // Check that the low words (being shuffled) are the identity in the
20766 // dword shuffle, and the high words are self-contained.
20767 if (Mask[0] != 0 || Mask[1] != 1 ||
20768 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20771 Chain.push_back(V);
20774 case X86ISD::PSHUFHW:
20775 // Check that the high words (being shuffled) are the identity in the
20776 // dword shuffle, and the low words are self-contained.
20777 if (Mask[2] != 2 || Mask[3] != 3 ||
20778 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20781 Chain.push_back(V);
20784 case X86ISD::UNPCKL:
20785 case X86ISD::UNPCKH:
20786 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20787 // shuffle into a preceding word shuffle.
20788 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20791 // Search for a half-shuffle which we can combine with.
20792 unsigned CombineOp =
20793 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20794 if (V.getOperand(0) != V.getOperand(1) ||
20795 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20797 Chain.push_back(V);
20798 V = V.getOperand(0);
20800 switch (V.getOpcode()) {
20802 return SDValue(); // Nothing to combine.
20804 case X86ISD::PSHUFLW:
20805 case X86ISD::PSHUFHW:
20806 if (V.getOpcode() == CombineOp)
20809 Chain.push_back(V);
20813 V = V.getOperand(0);
20817 } while (V.hasOneUse());
20820 // Break out of the loop if we break out of the switch.
20824 if (!V.hasOneUse())
20825 // We fell out of the loop without finding a viable combining instruction.
20828 // Merge this node's mask and our incoming mask.
20829 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20830 for (int &M : Mask)
20832 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20833 getV4X86ShuffleImm8ForMask(Mask, DAG));
20835 // Rebuild the chain around this new shuffle.
20836 while (!Chain.empty()) {
20837 SDValue W = Chain.pop_back_val();
20839 if (V.getValueType() != W.getOperand(0).getValueType())
20840 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20842 switch (W.getOpcode()) {
20844 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20846 case X86ISD::UNPCKL:
20847 case X86ISD::UNPCKH:
20848 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20851 case X86ISD::PSHUFD:
20852 case X86ISD::PSHUFLW:
20853 case X86ISD::PSHUFHW:
20854 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20858 if (V.getValueType() != N.getValueType())
20859 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20861 // Return the new chain to replace N.
20865 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20867 /// We walk up the chain, skipping shuffles of the other half and looking
20868 /// through shuffles which switch halves trying to find a shuffle of the same
20869 /// pair of dwords.
20870 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20872 TargetLowering::DAGCombinerInfo &DCI) {
20874 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20875 "Called with something other than an x86 128-bit half shuffle!");
20877 unsigned CombineOpcode = N.getOpcode();
20879 // Walk up a single-use chain looking for a combinable shuffle.
20880 SDValue V = N.getOperand(0);
20881 for (; V.hasOneUse(); V = V.getOperand(0)) {
20882 switch (V.getOpcode()) {
20884 return false; // Nothing combined!
20887 // Skip bitcasts as we always know the type for the target specific
20891 case X86ISD::PSHUFLW:
20892 case X86ISD::PSHUFHW:
20893 if (V.getOpcode() == CombineOpcode)
20896 // Other-half shuffles are no-ops.
20899 // Break out of the loop if we break out of the switch.
20903 if (!V.hasOneUse())
20904 // We fell out of the loop without finding a viable combining instruction.
20907 // Combine away the bottom node as its shuffle will be accumulated into
20908 // a preceding shuffle.
20909 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20911 // Record the old value.
20914 // Merge this node's mask and our incoming mask (adjusted to account for all
20915 // the pshufd instructions encountered).
20916 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20917 for (int &M : Mask)
20919 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20920 getV4X86ShuffleImm8ForMask(Mask, DAG));
20922 // Check that the shuffles didn't cancel each other out. If not, we need to
20923 // combine to the new one.
20925 // Replace the combinable shuffle with the combined one, updating all users
20926 // so that we re-evaluate the chain here.
20927 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20932 /// \brief Try to combine x86 target specific shuffles.
20933 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20934 TargetLowering::DAGCombinerInfo &DCI,
20935 const X86Subtarget *Subtarget) {
20937 MVT VT = N.getSimpleValueType();
20938 SmallVector<int, 4> Mask;
20940 switch (N.getOpcode()) {
20941 case X86ISD::PSHUFD:
20942 case X86ISD::PSHUFLW:
20943 case X86ISD::PSHUFHW:
20944 Mask = getPSHUFShuffleMask(N);
20945 assert(Mask.size() == 4);
20951 // Nuke no-op shuffles that show up after combining.
20952 if (isNoopShuffleMask(Mask))
20953 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20955 // Look for simplifications involving one or two shuffle instructions.
20956 SDValue V = N.getOperand(0);
20957 switch (N.getOpcode()) {
20960 case X86ISD::PSHUFLW:
20961 case X86ISD::PSHUFHW:
20962 assert(VT == MVT::v8i16);
20965 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20966 return SDValue(); // We combined away this shuffle, so we're done.
20968 // See if this reduces to a PSHUFD which is no more expensive and can
20969 // combine with more operations.
20970 if (canWidenShuffleElements(Mask)) {
20971 int DMask[] = {-1, -1, -1, -1};
20972 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20973 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20974 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20975 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20976 DCI.AddToWorklist(V.getNode());
20977 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20978 getV4X86ShuffleImm8ForMask(DMask, DAG));
20979 DCI.AddToWorklist(V.getNode());
20980 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20983 // Look for shuffle patterns which can be implemented as a single unpack.
20984 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20985 // only works when we have a PSHUFD followed by two half-shuffles.
20986 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20987 (V.getOpcode() == X86ISD::PSHUFLW ||
20988 V.getOpcode() == X86ISD::PSHUFHW) &&
20989 V.getOpcode() != N.getOpcode() &&
20991 SDValue D = V.getOperand(0);
20992 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20993 D = D.getOperand(0);
20994 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20995 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20996 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20997 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20998 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21000 for (int i = 0; i < 4; ++i) {
21001 WordMask[i + NOffset] = Mask[i] + NOffset;
21002 WordMask[i + VOffset] = VMask[i] + VOffset;
21004 // Map the word mask through the DWord mask.
21006 for (int i = 0; i < 8; ++i)
21007 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21008 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21009 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21010 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21011 std::begin(UnpackLoMask)) ||
21012 std::equal(std::begin(MappedMask), std::end(MappedMask),
21013 std::begin(UnpackHiMask))) {
21014 // We can replace all three shuffles with an unpack.
21015 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21016 DCI.AddToWorklist(V.getNode());
21017 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21019 DL, MVT::v8i16, V, V);
21026 case X86ISD::PSHUFD:
21027 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21036 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21038 /// We combine this directly on the abstract vector shuffle nodes so it is
21039 /// easier to generically match. We also insert dummy vector shuffle nodes for
21040 /// the operands which explicitly discard the lanes which are unused by this
21041 /// operation to try to flow through the rest of the combiner the fact that
21042 /// they're unused.
21043 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21045 EVT VT = N->getValueType(0);
21047 // We only handle target-independent shuffles.
21048 // FIXME: It would be easy and harmless to use the target shuffle mask
21049 // extraction tool to support more.
21050 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21053 auto *SVN = cast<ShuffleVectorSDNode>(N);
21054 ArrayRef<int> Mask = SVN->getMask();
21055 SDValue V1 = N->getOperand(0);
21056 SDValue V2 = N->getOperand(1);
21058 // We require the first shuffle operand to be the SUB node, and the second to
21059 // be the ADD node.
21060 // FIXME: We should support the commuted patterns.
21061 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21064 // If there are other uses of these operations we can't fold them.
21065 if (!V1->hasOneUse() || !V2->hasOneUse())
21068 // Ensure that both operations have the same operands. Note that we can
21069 // commute the FADD operands.
21070 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21071 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21072 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21075 // We're looking for blends between FADD and FSUB nodes. We insist on these
21076 // nodes being lined up in a specific expected pattern.
21077 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21078 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21079 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21082 // Only specific types are legal at this point, assert so we notice if and
21083 // when these change.
21084 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21085 VT == MVT::v4f64) &&
21086 "Unknown vector type encountered!");
21088 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21091 /// PerformShuffleCombine - Performs several different shuffle combines.
21092 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21093 TargetLowering::DAGCombinerInfo &DCI,
21094 const X86Subtarget *Subtarget) {
21096 SDValue N0 = N->getOperand(0);
21097 SDValue N1 = N->getOperand(1);
21098 EVT VT = N->getValueType(0);
21100 // Don't create instructions with illegal types after legalize types has run.
21101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21102 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21105 // If we have legalized the vector types, look for blends of FADD and FSUB
21106 // nodes that we can fuse into an ADDSUB node.
21107 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21108 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21111 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21112 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21113 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21114 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21116 // During Type Legalization, when promoting illegal vector types,
21117 // the backend might introduce new shuffle dag nodes and bitcasts.
21119 // This code performs the following transformation:
21120 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21121 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21123 // We do this only if both the bitcast and the BINOP dag nodes have
21124 // one use. Also, perform this transformation only if the new binary
21125 // operation is legal. This is to avoid introducing dag nodes that
21126 // potentially need to be further expanded (or custom lowered) into a
21127 // less optimal sequence of dag nodes.
21128 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21129 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21130 N0.getOpcode() == ISD::BITCAST) {
21131 SDValue BC0 = N0.getOperand(0);
21132 EVT SVT = BC0.getValueType();
21133 unsigned Opcode = BC0.getOpcode();
21134 unsigned NumElts = VT.getVectorNumElements();
21136 if (BC0.hasOneUse() && SVT.isVector() &&
21137 SVT.getVectorNumElements() * 2 == NumElts &&
21138 TLI.isOperationLegal(Opcode, VT)) {
21139 bool CanFold = false;
21151 unsigned SVTNumElts = SVT.getVectorNumElements();
21152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21153 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21154 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21155 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21156 CanFold = SVOp->getMaskElt(i) < 0;
21159 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21160 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21161 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21162 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21167 // Only handle 128 wide vector from here on.
21168 if (!VT.is128BitVector())
21171 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21172 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21173 // consecutive, non-overlapping, and in the right order.
21174 SmallVector<SDValue, 16> Elts;
21175 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21176 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21178 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21182 if (isTargetShuffle(N->getOpcode())) {
21184 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21185 if (Shuffle.getNode())
21188 // Try recursively combining arbitrary sequences of x86 shuffle
21189 // instructions into higher-order shuffles. We do this after combining
21190 // specific PSHUF instruction sequences into their minimal form so that we
21191 // can evaluate how many specialized shuffle instructions are involved in
21192 // a particular chain.
21193 SmallVector<int, 1> NonceMask; // Just a placeholder.
21194 NonceMask.push_back(0);
21195 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21196 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21198 return SDValue(); // This routine will use CombineTo to replace N.
21204 /// PerformTruncateCombine - Converts truncate operation to
21205 /// a sequence of vector shuffle operations.
21206 /// It is possible when we truncate 256-bit vector to 128-bit vector
21207 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21208 TargetLowering::DAGCombinerInfo &DCI,
21209 const X86Subtarget *Subtarget) {
21213 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21214 /// specific shuffle of a load can be folded into a single element load.
21215 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21216 /// shuffles have been customed lowered so we need to handle those here.
21217 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21218 TargetLowering::DAGCombinerInfo &DCI) {
21219 if (DCI.isBeforeLegalizeOps())
21222 SDValue InVec = N->getOperand(0);
21223 SDValue EltNo = N->getOperand(1);
21225 if (!isa<ConstantSDNode>(EltNo))
21228 EVT VT = InVec.getValueType();
21230 if (InVec.getOpcode() == ISD::BITCAST) {
21231 // Don't duplicate a load with other uses.
21232 if (!InVec.hasOneUse())
21234 EVT BCVT = InVec.getOperand(0).getValueType();
21235 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21237 InVec = InVec.getOperand(0);
21240 if (!isTargetShuffle(InVec.getOpcode()))
21243 // Don't duplicate a load with other uses.
21244 if (!InVec.hasOneUse())
21247 SmallVector<int, 16> ShuffleMask;
21249 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21253 // Select the input vector, guarding against out of range extract vector.
21254 unsigned NumElems = VT.getVectorNumElements();
21255 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21256 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21257 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21258 : InVec.getOperand(1);
21260 // If inputs to shuffle are the same for both ops, then allow 2 uses
21261 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21263 if (LdNode.getOpcode() == ISD::BITCAST) {
21264 // Don't duplicate a load with other uses.
21265 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21268 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21269 LdNode = LdNode.getOperand(0);
21272 if (!ISD::isNormalLoad(LdNode.getNode()))
21275 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21277 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21280 EVT EltVT = N->getValueType(0);
21281 // If there's a bitcast before the shuffle, check if the load type and
21282 // alignment is valid.
21283 unsigned Align = LN0->getAlignment();
21284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21285 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21286 EltVT.getTypeForEVT(*DAG.getContext()));
21288 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21291 // All checks match so transform back to vector_shuffle so that DAG combiner
21292 // can finish the job
21295 // Create shuffle node taking into account the case that its a unary shuffle
21296 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21297 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21298 InVec.getOperand(0), Shuffle,
21300 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21301 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21305 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21306 /// generation and convert it from being a bunch of shuffles and extracts
21307 /// to a simple store and scalar loads to extract the elements.
21308 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21309 TargetLowering::DAGCombinerInfo &DCI) {
21310 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21311 if (NewOp.getNode())
21314 SDValue InputVector = N->getOperand(0);
21316 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21317 // from mmx to v2i32 has a single usage.
21318 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21319 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21320 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21321 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21322 N->getValueType(0),
21323 InputVector.getNode()->getOperand(0));
21325 // Only operate on vectors of 4 elements, where the alternative shuffling
21326 // gets to be more expensive.
21327 if (InputVector.getValueType() != MVT::v4i32)
21330 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21331 // single use which is a sign-extend or zero-extend, and all elements are
21333 SmallVector<SDNode *, 4> Uses;
21334 unsigned ExtractedElements = 0;
21335 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21336 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21337 if (UI.getUse().getResNo() != InputVector.getResNo())
21340 SDNode *Extract = *UI;
21341 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21344 if (Extract->getValueType(0) != MVT::i32)
21346 if (!Extract->hasOneUse())
21348 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21349 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21351 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21354 // Record which element was extracted.
21355 ExtractedElements |=
21356 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21358 Uses.push_back(Extract);
21361 // If not all the elements were used, this may not be worthwhile.
21362 if (ExtractedElements != 15)
21365 // Ok, we've now decided to do the transformation.
21366 SDLoc dl(InputVector);
21368 // Store the value to a temporary stack slot.
21369 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21370 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21371 MachinePointerInfo(), false, false, 0);
21373 // Replace each use (extract) with a load of the appropriate element.
21374 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21375 UE = Uses.end(); UI != UE; ++UI) {
21376 SDNode *Extract = *UI;
21378 // cOMpute the element's address.
21379 SDValue Idx = Extract->getOperand(1);
21381 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21382 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21384 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21386 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21387 StackPtr, OffsetVal);
21389 // Load the scalar.
21390 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21391 ScalarAddr, MachinePointerInfo(),
21392 false, false, false, 0);
21394 // Replace the exact with the load.
21395 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21398 // The replacement was made in place; don't return anything.
21402 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21403 static std::pair<unsigned, bool>
21404 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21405 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21406 if (!VT.isVector())
21407 return std::make_pair(0, false);
21409 bool NeedSplit = false;
21410 switch (VT.getSimpleVT().SimpleTy) {
21411 default: return std::make_pair(0, false);
21415 if (!Subtarget->hasAVX2())
21417 if (!Subtarget->hasAVX())
21418 return std::make_pair(0, false);
21423 if (!Subtarget->hasSSE2())
21424 return std::make_pair(0, false);
21427 // SSE2 has only a small subset of the operations.
21428 bool hasUnsigned = Subtarget->hasSSE41() ||
21429 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21430 bool hasSigned = Subtarget->hasSSE41() ||
21431 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21433 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21436 // Check for x CC y ? x : y.
21437 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21438 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21443 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21446 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21449 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21452 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21454 // Check for x CC y ? y : x -- a min/max with reversed arms.
21455 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21456 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21461 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21464 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21467 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21470 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21474 return std::make_pair(Opc, NeedSplit);
21478 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21479 const X86Subtarget *Subtarget) {
21481 SDValue Cond = N->getOperand(0);
21482 SDValue LHS = N->getOperand(1);
21483 SDValue RHS = N->getOperand(2);
21485 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21486 SDValue CondSrc = Cond->getOperand(0);
21487 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21488 Cond = CondSrc->getOperand(0);
21491 MVT VT = N->getSimpleValueType(0);
21492 MVT EltVT = VT.getVectorElementType();
21493 unsigned NumElems = VT.getVectorNumElements();
21494 // There is no blend with immediate in AVX-512.
21495 if (VT.is512BitVector())
21498 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21500 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21503 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21506 // A vselect where all conditions and data are constants can be optimized into
21507 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21508 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21509 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21512 unsigned MaskValue = 0;
21513 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21516 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21517 for (unsigned i = 0; i < NumElems; ++i) {
21518 // Be sure we emit undef where we can.
21519 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21520 ShuffleMask[i] = -1;
21522 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21525 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21528 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21530 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21531 TargetLowering::DAGCombinerInfo &DCI,
21532 const X86Subtarget *Subtarget) {
21534 SDValue Cond = N->getOperand(0);
21535 // Get the LHS/RHS of the select.
21536 SDValue LHS = N->getOperand(1);
21537 SDValue RHS = N->getOperand(2);
21538 EVT VT = LHS.getValueType();
21539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21541 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21542 // instructions match the semantics of the common C idiom x<y?x:y but not
21543 // x<=y?x:y, because of how they handle negative zero (which can be
21544 // ignored in unsafe-math mode).
21545 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21546 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21547 (Subtarget->hasSSE2() ||
21548 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21549 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21551 unsigned Opcode = 0;
21552 // Check for x CC y ? x : y.
21553 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21554 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21558 // Converting this to a min would handle NaNs incorrectly, and swapping
21559 // the operands would cause it to handle comparisons between positive
21560 // and negative zero incorrectly.
21561 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21562 if (!DAG.getTarget().Options.UnsafeFPMath &&
21563 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21565 std::swap(LHS, RHS);
21567 Opcode = X86ISD::FMIN;
21570 // Converting this to a min would handle comparisons between positive
21571 // and negative zero incorrectly.
21572 if (!DAG.getTarget().Options.UnsafeFPMath &&
21573 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21575 Opcode = X86ISD::FMIN;
21578 // Converting this to a min would handle both negative zeros and NaNs
21579 // incorrectly, but we can swap the operands to fix both.
21580 std::swap(LHS, RHS);
21584 Opcode = X86ISD::FMIN;
21588 // Converting this to a max would handle comparisons between positive
21589 // and negative zero incorrectly.
21590 if (!DAG.getTarget().Options.UnsafeFPMath &&
21591 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21593 Opcode = X86ISD::FMAX;
21596 // Converting this to a max would handle NaNs incorrectly, and swapping
21597 // the operands would cause it to handle comparisons between positive
21598 // and negative zero incorrectly.
21599 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21600 if (!DAG.getTarget().Options.UnsafeFPMath &&
21601 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21603 std::swap(LHS, RHS);
21605 Opcode = X86ISD::FMAX;
21608 // Converting this to a max would handle both negative zeros and NaNs
21609 // incorrectly, but we can swap the operands to fix both.
21610 std::swap(LHS, RHS);
21614 Opcode = X86ISD::FMAX;
21617 // Check for x CC y ? y : x -- a min/max with reversed arms.
21618 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21619 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21623 // Converting this to a min would handle comparisons between positive
21624 // and negative zero incorrectly, and swapping the operands would
21625 // cause it to handle NaNs incorrectly.
21626 if (!DAG.getTarget().Options.UnsafeFPMath &&
21627 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21628 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21630 std::swap(LHS, RHS);
21632 Opcode = X86ISD::FMIN;
21635 // Converting this to a min would handle NaNs incorrectly.
21636 if (!DAG.getTarget().Options.UnsafeFPMath &&
21637 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21639 Opcode = X86ISD::FMIN;
21642 // Converting this to a min would handle both negative zeros and NaNs
21643 // incorrectly, but we can swap the operands to fix both.
21644 std::swap(LHS, RHS);
21648 Opcode = X86ISD::FMIN;
21652 // Converting this to a max would handle NaNs incorrectly.
21653 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21655 Opcode = X86ISD::FMAX;
21658 // Converting this to a max would handle comparisons between positive
21659 // and negative zero incorrectly, and swapping the operands would
21660 // cause it to handle NaNs incorrectly.
21661 if (!DAG.getTarget().Options.UnsafeFPMath &&
21662 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21663 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21665 std::swap(LHS, RHS);
21667 Opcode = X86ISD::FMAX;
21670 // Converting this to a max would handle both negative zeros and NaNs
21671 // incorrectly, but we can swap the operands to fix both.
21672 std::swap(LHS, RHS);
21676 Opcode = X86ISD::FMAX;
21682 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21685 EVT CondVT = Cond.getValueType();
21686 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21687 CondVT.getVectorElementType() == MVT::i1) {
21688 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21689 // lowering on KNL. In this case we convert it to
21690 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21691 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21692 // Since SKX these selects have a proper lowering.
21693 EVT OpVT = LHS.getValueType();
21694 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21695 (OpVT.getVectorElementType() == MVT::i8 ||
21696 OpVT.getVectorElementType() == MVT::i16) &&
21697 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21698 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21699 DCI.AddToWorklist(Cond.getNode());
21700 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21703 // If this is a select between two integer constants, try to do some
21705 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21706 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21707 // Don't do this for crazy integer types.
21708 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21709 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21710 // so that TrueC (the true value) is larger than FalseC.
21711 bool NeedsCondInvert = false;
21713 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21714 // Efficiently invertible.
21715 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21716 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21717 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21718 NeedsCondInvert = true;
21719 std::swap(TrueC, FalseC);
21722 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21723 if (FalseC->getAPIntValue() == 0 &&
21724 TrueC->getAPIntValue().isPowerOf2()) {
21725 if (NeedsCondInvert) // Invert the condition if needed.
21726 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21727 DAG.getConstant(1, Cond.getValueType()));
21729 // Zero extend the condition if needed.
21730 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21732 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21733 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21734 DAG.getConstant(ShAmt, MVT::i8));
21737 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21738 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21739 if (NeedsCondInvert) // Invert the condition if needed.
21740 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21741 DAG.getConstant(1, Cond.getValueType()));
21743 // Zero extend the condition if needed.
21744 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21745 FalseC->getValueType(0), Cond);
21746 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21747 SDValue(FalseC, 0));
21750 // Optimize cases that will turn into an LEA instruction. This requires
21751 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21752 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21753 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21754 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21756 bool isFastMultiplier = false;
21758 switch ((unsigned char)Diff) {
21760 case 1: // result = add base, cond
21761 case 2: // result = lea base( , cond*2)
21762 case 3: // result = lea base(cond, cond*2)
21763 case 4: // result = lea base( , cond*4)
21764 case 5: // result = lea base(cond, cond*4)
21765 case 8: // result = lea base( , cond*8)
21766 case 9: // result = lea base(cond, cond*8)
21767 isFastMultiplier = true;
21772 if (isFastMultiplier) {
21773 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21774 if (NeedsCondInvert) // Invert the condition if needed.
21775 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21776 DAG.getConstant(1, Cond.getValueType()));
21778 // Zero extend the condition if needed.
21779 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21781 // Scale the condition by the difference.
21783 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21784 DAG.getConstant(Diff, Cond.getValueType()));
21786 // Add the base if non-zero.
21787 if (FalseC->getAPIntValue() != 0)
21788 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21789 SDValue(FalseC, 0));
21796 // Canonicalize max and min:
21797 // (x > y) ? x : y -> (x >= y) ? x : y
21798 // (x < y) ? x : y -> (x <= y) ? x : y
21799 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21800 // the need for an extra compare
21801 // against zero. e.g.
21802 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21804 // testl %edi, %edi
21806 // cmovgl %edi, %eax
21810 // cmovsl %eax, %edi
21811 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21812 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21813 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21814 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21819 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21820 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21821 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21822 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21827 // Early exit check
21828 if (!TLI.isTypeLegal(VT))
21831 // Match VSELECTs into subs with unsigned saturation.
21832 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21833 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21834 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21835 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21836 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21838 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21839 // left side invert the predicate to simplify logic below.
21841 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21843 CC = ISD::getSetCCInverse(CC, true);
21844 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21848 if (Other.getNode() && Other->getNumOperands() == 2 &&
21849 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21850 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21851 SDValue CondRHS = Cond->getOperand(1);
21853 // Look for a general sub with unsigned saturation first.
21854 // x >= y ? x-y : 0 --> subus x, y
21855 // x > y ? x-y : 0 --> subus x, y
21856 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21857 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21858 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21860 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21861 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21862 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21863 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21864 // If the RHS is a constant we have to reverse the const
21865 // canonicalization.
21866 // x > C-1 ? x+-C : 0 --> subus x, C
21867 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21868 CondRHSConst->getAPIntValue() ==
21869 (-OpRHSConst->getAPIntValue() - 1))
21870 return DAG.getNode(
21871 X86ISD::SUBUS, DL, VT, OpLHS,
21872 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21874 // Another special case: If C was a sign bit, the sub has been
21875 // canonicalized into a xor.
21876 // FIXME: Would it be better to use computeKnownBits to determine
21877 // whether it's safe to decanonicalize the xor?
21878 // x s< 0 ? x^C : 0 --> subus x, C
21879 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21880 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21881 OpRHSConst->getAPIntValue().isSignBit())
21882 // Note that we have to rebuild the RHS constant here to ensure we
21883 // don't rely on particular values of undef lanes.
21884 return DAG.getNode(
21885 X86ISD::SUBUS, DL, VT, OpLHS,
21886 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21891 // Try to match a min/max vector operation.
21892 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21893 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21894 unsigned Opc = ret.first;
21895 bool NeedSplit = ret.second;
21897 if (Opc && NeedSplit) {
21898 unsigned NumElems = VT.getVectorNumElements();
21899 // Extract the LHS vectors
21900 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21901 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21903 // Extract the RHS vectors
21904 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21905 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21907 // Create min/max for each subvector
21908 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21909 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21911 // Merge the result
21912 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21914 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21917 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21918 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21919 // Check if SETCC has already been promoted
21920 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21921 // Check that condition value type matches vselect operand type
21924 assert(Cond.getValueType().isVector() &&
21925 "vector select expects a vector selector!");
21927 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21928 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21930 if (!TValIsAllOnes && !FValIsAllZeros) {
21931 // Try invert the condition if true value is not all 1s and false value
21933 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21934 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21936 if (TValIsAllZeros || FValIsAllOnes) {
21937 SDValue CC = Cond.getOperand(2);
21938 ISD::CondCode NewCC =
21939 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21940 Cond.getOperand(0).getValueType().isInteger());
21941 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21942 std::swap(LHS, RHS);
21943 TValIsAllOnes = FValIsAllOnes;
21944 FValIsAllZeros = TValIsAllZeros;
21948 if (TValIsAllOnes || FValIsAllZeros) {
21951 if (TValIsAllOnes && FValIsAllZeros)
21953 else if (TValIsAllOnes)
21954 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21955 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21956 else if (FValIsAllZeros)
21957 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21958 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21960 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21964 // Try to fold this VSELECT into a MOVSS/MOVSD
21965 if (N->getOpcode() == ISD::VSELECT &&
21966 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21967 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21968 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21969 bool CanFold = false;
21970 unsigned NumElems = Cond.getNumOperands();
21974 if (isZero(Cond.getOperand(0))) {
21977 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21978 // fold (vselect <0,-1> -> (movsd A, B)
21979 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21980 CanFold = isAllOnes(Cond.getOperand(i));
21981 } else if (isAllOnes(Cond.getOperand(0))) {
21985 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21986 // fold (vselect <-1,0> -> (movsd B, A)
21987 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21988 CanFold = isZero(Cond.getOperand(i));
21992 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21993 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21994 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21997 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21998 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21999 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22000 // (v2i64 (bitcast B)))))
22002 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22003 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22004 // (v2f64 (bitcast B)))))
22006 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22007 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22008 // (v2i64 (bitcast A)))))
22010 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22011 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22012 // (v2f64 (bitcast A)))))
22014 CanFold = (isZero(Cond.getOperand(0)) &&
22015 isZero(Cond.getOperand(1)) &&
22016 isAllOnes(Cond.getOperand(2)) &&
22017 isAllOnes(Cond.getOperand(3)));
22019 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22020 isAllOnes(Cond.getOperand(1)) &&
22021 isZero(Cond.getOperand(2)) &&
22022 isZero(Cond.getOperand(3))) {
22024 std::swap(LHS, RHS);
22028 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22029 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22030 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22031 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22033 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22039 // If we know that this node is legal then we know that it is going to be
22040 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22041 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22042 // to simplify previous instructions.
22043 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22044 !DCI.isBeforeLegalize() &&
22045 // We explicitly check against v8i16 and v16i16 because, although
22046 // they're marked as Custom, they might only be legal when Cond is a
22047 // build_vector of constants. This will be taken care in a later
22049 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22050 VT != MVT::v8i16)) {
22051 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22053 // Don't optimize vector selects that map to mask-registers.
22057 // Check all uses of that condition operand to check whether it will be
22058 // consumed by non-BLEND instructions, which may depend on all bits are set
22060 for (SDNode::use_iterator I = Cond->use_begin(),
22061 E = Cond->use_end(); I != E; ++I)
22062 if (I->getOpcode() != ISD::VSELECT)
22063 // TODO: Add other opcodes eventually lowered into BLEND.
22066 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22067 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22069 APInt KnownZero, KnownOne;
22070 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22071 DCI.isBeforeLegalizeOps());
22072 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22073 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22074 DCI.CommitTargetLoweringOpt(TLO);
22077 // We should generate an X86ISD::BLENDI from a vselect if its argument
22078 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22079 // constants. This specific pattern gets generated when we split a
22080 // selector for a 512 bit vector in a machine without AVX512 (but with
22081 // 256-bit vectors), during legalization:
22083 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22085 // Iff we find this pattern and the build_vectors are built from
22086 // constants, we translate the vselect into a shuffle_vector that we
22087 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22088 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22089 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22090 if (Shuffle.getNode())
22097 // Check whether a boolean test is testing a boolean value generated by
22098 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22101 // Simplify the following patterns:
22102 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22103 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22104 // to (Op EFLAGS Cond)
22106 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22107 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22108 // to (Op EFLAGS !Cond)
22110 // where Op could be BRCOND or CMOV.
22112 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22113 // Quit if not CMP and SUB with its value result used.
22114 if (Cmp.getOpcode() != X86ISD::CMP &&
22115 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22118 // Quit if not used as a boolean value.
22119 if (CC != X86::COND_E && CC != X86::COND_NE)
22122 // Check CMP operands. One of them should be 0 or 1 and the other should be
22123 // an SetCC or extended from it.
22124 SDValue Op1 = Cmp.getOperand(0);
22125 SDValue Op2 = Cmp.getOperand(1);
22128 const ConstantSDNode* C = nullptr;
22129 bool needOppositeCond = (CC == X86::COND_E);
22130 bool checkAgainstTrue = false; // Is it a comparison against 1?
22132 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22134 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22136 else // Quit if all operands are not constants.
22139 if (C->getZExtValue() == 1) {
22140 needOppositeCond = !needOppositeCond;
22141 checkAgainstTrue = true;
22142 } else if (C->getZExtValue() != 0)
22143 // Quit if the constant is neither 0 or 1.
22146 bool truncatedToBoolWithAnd = false;
22147 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22148 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22149 SetCC.getOpcode() == ISD::TRUNCATE ||
22150 SetCC.getOpcode() == ISD::AND) {
22151 if (SetCC.getOpcode() == ISD::AND) {
22153 ConstantSDNode *CS;
22154 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22155 CS->getZExtValue() == 1)
22157 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22158 CS->getZExtValue() == 1)
22162 SetCC = SetCC.getOperand(OpIdx);
22163 truncatedToBoolWithAnd = true;
22165 SetCC = SetCC.getOperand(0);
22168 switch (SetCC.getOpcode()) {
22169 case X86ISD::SETCC_CARRY:
22170 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22171 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22172 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22173 // truncated to i1 using 'and'.
22174 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22176 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22177 "Invalid use of SETCC_CARRY!");
22179 case X86ISD::SETCC:
22180 // Set the condition code or opposite one if necessary.
22181 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22182 if (needOppositeCond)
22183 CC = X86::GetOppositeBranchCondition(CC);
22184 return SetCC.getOperand(1);
22185 case X86ISD::CMOV: {
22186 // Check whether false/true value has canonical one, i.e. 0 or 1.
22187 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22188 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22189 // Quit if true value is not a constant.
22192 // Quit if false value is not a constant.
22194 SDValue Op = SetCC.getOperand(0);
22195 // Skip 'zext' or 'trunc' node.
22196 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22197 Op.getOpcode() == ISD::TRUNCATE)
22198 Op = Op.getOperand(0);
22199 // A special case for rdrand/rdseed, where 0 is set if false cond is
22201 if ((Op.getOpcode() != X86ISD::RDRAND &&
22202 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22205 // Quit if false value is not the constant 0 or 1.
22206 bool FValIsFalse = true;
22207 if (FVal && FVal->getZExtValue() != 0) {
22208 if (FVal->getZExtValue() != 1)
22210 // If FVal is 1, opposite cond is needed.
22211 needOppositeCond = !needOppositeCond;
22212 FValIsFalse = false;
22214 // Quit if TVal is not the constant opposite of FVal.
22215 if (FValIsFalse && TVal->getZExtValue() != 1)
22217 if (!FValIsFalse && TVal->getZExtValue() != 0)
22219 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22220 if (needOppositeCond)
22221 CC = X86::GetOppositeBranchCondition(CC);
22222 return SetCC.getOperand(3);
22229 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22230 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22231 TargetLowering::DAGCombinerInfo &DCI,
22232 const X86Subtarget *Subtarget) {
22235 // If the flag operand isn't dead, don't touch this CMOV.
22236 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22239 SDValue FalseOp = N->getOperand(0);
22240 SDValue TrueOp = N->getOperand(1);
22241 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22242 SDValue Cond = N->getOperand(3);
22244 if (CC == X86::COND_E || CC == X86::COND_NE) {
22245 switch (Cond.getOpcode()) {
22249 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22250 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22251 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22257 Flags = checkBoolTestSetCCCombine(Cond, CC);
22258 if (Flags.getNode() &&
22259 // Extra check as FCMOV only supports a subset of X86 cond.
22260 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22261 SDValue Ops[] = { FalseOp, TrueOp,
22262 DAG.getConstant(CC, MVT::i8), Flags };
22263 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22266 // If this is a select between two integer constants, try to do some
22267 // optimizations. Note that the operands are ordered the opposite of SELECT
22269 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22270 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22271 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22272 // larger than FalseC (the false value).
22273 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22274 CC = X86::GetOppositeBranchCondition(CC);
22275 std::swap(TrueC, FalseC);
22276 std::swap(TrueOp, FalseOp);
22279 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22280 // This is efficient for any integer data type (including i8/i16) and
22282 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22283 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22284 DAG.getConstant(CC, MVT::i8), Cond);
22286 // Zero extend the condition if needed.
22287 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22289 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22290 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22291 DAG.getConstant(ShAmt, MVT::i8));
22292 if (N->getNumValues() == 2) // Dead flag value?
22293 return DCI.CombineTo(N, Cond, SDValue());
22297 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22298 // for any integer data type, including i8/i16.
22299 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22300 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22301 DAG.getConstant(CC, MVT::i8), Cond);
22303 // Zero extend the condition if needed.
22304 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22305 FalseC->getValueType(0), Cond);
22306 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22307 SDValue(FalseC, 0));
22309 if (N->getNumValues() == 2) // Dead flag value?
22310 return DCI.CombineTo(N, Cond, SDValue());
22314 // Optimize cases that will turn into an LEA instruction. This requires
22315 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22316 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22317 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22318 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22320 bool isFastMultiplier = false;
22322 switch ((unsigned char)Diff) {
22324 case 1: // result = add base, cond
22325 case 2: // result = lea base( , cond*2)
22326 case 3: // result = lea base(cond, cond*2)
22327 case 4: // result = lea base( , cond*4)
22328 case 5: // result = lea base(cond, cond*4)
22329 case 8: // result = lea base( , cond*8)
22330 case 9: // result = lea base(cond, cond*8)
22331 isFastMultiplier = true;
22336 if (isFastMultiplier) {
22337 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22338 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22339 DAG.getConstant(CC, MVT::i8), Cond);
22340 // Zero extend the condition if needed.
22341 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22343 // Scale the condition by the difference.
22345 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22346 DAG.getConstant(Diff, Cond.getValueType()));
22348 // Add the base if non-zero.
22349 if (FalseC->getAPIntValue() != 0)
22350 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22351 SDValue(FalseC, 0));
22352 if (N->getNumValues() == 2) // Dead flag value?
22353 return DCI.CombineTo(N, Cond, SDValue());
22360 // Handle these cases:
22361 // (select (x != c), e, c) -> select (x != c), e, x),
22362 // (select (x == c), c, e) -> select (x == c), x, e)
22363 // where the c is an integer constant, and the "select" is the combination
22364 // of CMOV and CMP.
22366 // The rationale for this change is that the conditional-move from a constant
22367 // needs two instructions, however, conditional-move from a register needs
22368 // only one instruction.
22370 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22371 // some instruction-combining opportunities. This opt needs to be
22372 // postponed as late as possible.
22374 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22375 // the DCI.xxxx conditions are provided to postpone the optimization as
22376 // late as possible.
22378 ConstantSDNode *CmpAgainst = nullptr;
22379 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22380 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22381 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22383 if (CC == X86::COND_NE &&
22384 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22385 CC = X86::GetOppositeBranchCondition(CC);
22386 std::swap(TrueOp, FalseOp);
22389 if (CC == X86::COND_E &&
22390 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22391 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22392 DAG.getConstant(CC, MVT::i8), Cond };
22393 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22401 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22402 const X86Subtarget *Subtarget) {
22403 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22405 default: return SDValue();
22406 // SSE/AVX/AVX2 blend intrinsics.
22407 case Intrinsic::x86_avx2_pblendvb:
22408 case Intrinsic::x86_avx2_pblendw:
22409 case Intrinsic::x86_avx2_pblendd_128:
22410 case Intrinsic::x86_avx2_pblendd_256:
22411 // Don't try to simplify this intrinsic if we don't have AVX2.
22412 if (!Subtarget->hasAVX2())
22415 case Intrinsic::x86_avx_blend_pd_256:
22416 case Intrinsic::x86_avx_blend_ps_256:
22417 case Intrinsic::x86_avx_blendv_pd_256:
22418 case Intrinsic::x86_avx_blendv_ps_256:
22419 // Don't try to simplify this intrinsic if we don't have AVX.
22420 if (!Subtarget->hasAVX())
22423 case Intrinsic::x86_sse41_pblendw:
22424 case Intrinsic::x86_sse41_blendpd:
22425 case Intrinsic::x86_sse41_blendps:
22426 case Intrinsic::x86_sse41_blendvps:
22427 case Intrinsic::x86_sse41_blendvpd:
22428 case Intrinsic::x86_sse41_pblendvb: {
22429 SDValue Op0 = N->getOperand(1);
22430 SDValue Op1 = N->getOperand(2);
22431 SDValue Mask = N->getOperand(3);
22433 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22434 if (!Subtarget->hasSSE41())
22437 // fold (blend A, A, Mask) -> A
22440 // fold (blend A, B, allZeros) -> A
22441 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22443 // fold (blend A, B, allOnes) -> B
22444 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22447 // Simplify the case where the mask is a constant i32 value.
22448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22449 if (C->isNullValue())
22451 if (C->isAllOnesValue())
22458 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22459 case Intrinsic::x86_sse2_psrai_w:
22460 case Intrinsic::x86_sse2_psrai_d:
22461 case Intrinsic::x86_avx2_psrai_w:
22462 case Intrinsic::x86_avx2_psrai_d:
22463 case Intrinsic::x86_sse2_psra_w:
22464 case Intrinsic::x86_sse2_psra_d:
22465 case Intrinsic::x86_avx2_psra_w:
22466 case Intrinsic::x86_avx2_psra_d: {
22467 SDValue Op0 = N->getOperand(1);
22468 SDValue Op1 = N->getOperand(2);
22469 EVT VT = Op0.getValueType();
22470 assert(VT.isVector() && "Expected a vector type!");
22472 if (isa<BuildVectorSDNode>(Op1))
22473 Op1 = Op1.getOperand(0);
22475 if (!isa<ConstantSDNode>(Op1))
22478 EVT SVT = VT.getVectorElementType();
22479 unsigned SVTBits = SVT.getSizeInBits();
22481 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22482 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22483 uint64_t ShAmt = C.getZExtValue();
22485 // Don't try to convert this shift into a ISD::SRA if the shift
22486 // count is bigger than or equal to the element size.
22487 if (ShAmt >= SVTBits)
22490 // Trivial case: if the shift count is zero, then fold this
22491 // into the first operand.
22495 // Replace this packed shift intrinsic with a target independent
22497 SDValue Splat = DAG.getConstant(C, VT);
22498 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22503 /// PerformMulCombine - Optimize a single multiply with constant into two
22504 /// in order to implement it with two cheaper instructions, e.g.
22505 /// LEA + SHL, LEA + LEA.
22506 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22507 TargetLowering::DAGCombinerInfo &DCI) {
22508 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22511 EVT VT = N->getValueType(0);
22512 if (VT != MVT::i64)
22515 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22518 uint64_t MulAmt = C->getZExtValue();
22519 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22522 uint64_t MulAmt1 = 0;
22523 uint64_t MulAmt2 = 0;
22524 if ((MulAmt % 9) == 0) {
22526 MulAmt2 = MulAmt / 9;
22527 } else if ((MulAmt % 5) == 0) {
22529 MulAmt2 = MulAmt / 5;
22530 } else if ((MulAmt % 3) == 0) {
22532 MulAmt2 = MulAmt / 3;
22535 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22538 if (isPowerOf2_64(MulAmt2) &&
22539 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22540 // If second multiplifer is pow2, issue it first. We want the multiply by
22541 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22543 std::swap(MulAmt1, MulAmt2);
22546 if (isPowerOf2_64(MulAmt1))
22547 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22548 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22550 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22551 DAG.getConstant(MulAmt1, VT));
22553 if (isPowerOf2_64(MulAmt2))
22554 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22555 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22557 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22558 DAG.getConstant(MulAmt2, VT));
22560 // Do not add new nodes to DAG combiner worklist.
22561 DCI.CombineTo(N, NewMul, false);
22566 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22567 SDValue N0 = N->getOperand(0);
22568 SDValue N1 = N->getOperand(1);
22569 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22570 EVT VT = N0.getValueType();
22572 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22573 // since the result of setcc_c is all zero's or all ones.
22574 if (VT.isInteger() && !VT.isVector() &&
22575 N1C && N0.getOpcode() == ISD::AND &&
22576 N0.getOperand(1).getOpcode() == ISD::Constant) {
22577 SDValue N00 = N0.getOperand(0);
22578 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22579 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22580 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22581 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22582 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22583 APInt ShAmt = N1C->getAPIntValue();
22584 Mask = Mask.shl(ShAmt);
22586 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22587 N00, DAG.getConstant(Mask, VT));
22591 // Hardware support for vector shifts is sparse which makes us scalarize the
22592 // vector operations in many cases. Also, on sandybridge ADD is faster than
22594 // (shl V, 1) -> add V,V
22595 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22596 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22597 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22598 // We shift all of the values by one. In many cases we do not have
22599 // hardware support for this operation. This is better expressed as an ADD
22601 if (N1SplatC->getZExtValue() == 1)
22602 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22608 /// \brief Returns a vector of 0s if the node in input is a vector logical
22609 /// shift by a constant amount which is known to be bigger than or equal
22610 /// to the vector element size in bits.
22611 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22612 const X86Subtarget *Subtarget) {
22613 EVT VT = N->getValueType(0);
22615 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22616 (!Subtarget->hasInt256() ||
22617 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22620 SDValue Amt = N->getOperand(1);
22622 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22623 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22624 APInt ShiftAmt = AmtSplat->getAPIntValue();
22625 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22627 // SSE2/AVX2 logical shifts always return a vector of 0s
22628 // if the shift amount is bigger than or equal to
22629 // the element size. The constant shift amount will be
22630 // encoded as a 8-bit immediate.
22631 if (ShiftAmt.trunc(8).uge(MaxAmount))
22632 return getZeroVector(VT, Subtarget, DAG, DL);
22638 /// PerformShiftCombine - Combine shifts.
22639 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22640 TargetLowering::DAGCombinerInfo &DCI,
22641 const X86Subtarget *Subtarget) {
22642 if (N->getOpcode() == ISD::SHL) {
22643 SDValue V = PerformSHLCombine(N, DAG);
22644 if (V.getNode()) return V;
22647 if (N->getOpcode() != ISD::SRA) {
22648 // Try to fold this logical shift into a zero vector.
22649 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22650 if (V.getNode()) return V;
22656 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22657 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22658 // and friends. Likewise for OR -> CMPNEQSS.
22659 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22660 TargetLowering::DAGCombinerInfo &DCI,
22661 const X86Subtarget *Subtarget) {
22664 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22665 // we're requiring SSE2 for both.
22666 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22667 SDValue N0 = N->getOperand(0);
22668 SDValue N1 = N->getOperand(1);
22669 SDValue CMP0 = N0->getOperand(1);
22670 SDValue CMP1 = N1->getOperand(1);
22673 // The SETCCs should both refer to the same CMP.
22674 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22677 SDValue CMP00 = CMP0->getOperand(0);
22678 SDValue CMP01 = CMP0->getOperand(1);
22679 EVT VT = CMP00.getValueType();
22681 if (VT == MVT::f32 || VT == MVT::f64) {
22682 bool ExpectingFlags = false;
22683 // Check for any users that want flags:
22684 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22685 !ExpectingFlags && UI != UE; ++UI)
22686 switch (UI->getOpcode()) {
22691 ExpectingFlags = true;
22693 case ISD::CopyToReg:
22694 case ISD::SIGN_EXTEND:
22695 case ISD::ZERO_EXTEND:
22696 case ISD::ANY_EXTEND:
22700 if (!ExpectingFlags) {
22701 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22702 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22704 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22705 X86::CondCode tmp = cc0;
22710 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22711 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22712 // FIXME: need symbolic constants for these magic numbers.
22713 // See X86ATTInstPrinter.cpp:printSSECC().
22714 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22715 if (Subtarget->hasAVX512()) {
22716 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22717 CMP01, DAG.getConstant(x86cc, MVT::i8));
22718 if (N->getValueType(0) != MVT::i1)
22719 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22723 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22724 CMP00.getValueType(), CMP00, CMP01,
22725 DAG.getConstant(x86cc, MVT::i8));
22727 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22728 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22730 if (is64BitFP && !Subtarget->is64Bit()) {
22731 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22732 // 64-bit integer, since that's not a legal type. Since
22733 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22734 // bits, but can do this little dance to extract the lowest 32 bits
22735 // and work with those going forward.
22736 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22738 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22740 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22741 Vector32, DAG.getIntPtrConstant(0));
22745 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22746 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22747 DAG.getConstant(1, IntVT));
22748 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22749 return OneBitOfTruth;
22757 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22758 /// so it can be folded inside ANDNP.
22759 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22760 EVT VT = N->getValueType(0);
22762 // Match direct AllOnes for 128 and 256-bit vectors
22763 if (ISD::isBuildVectorAllOnes(N))
22766 // Look through a bit convert.
22767 if (N->getOpcode() == ISD::BITCAST)
22768 N = N->getOperand(0).getNode();
22770 // Sometimes the operand may come from a insert_subvector building a 256-bit
22772 if (VT.is256BitVector() &&
22773 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22774 SDValue V1 = N->getOperand(0);
22775 SDValue V2 = N->getOperand(1);
22777 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22778 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22779 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22780 ISD::isBuildVectorAllOnes(V2.getNode()))
22787 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22788 // register. In most cases we actually compare or select YMM-sized registers
22789 // and mixing the two types creates horrible code. This method optimizes
22790 // some of the transition sequences.
22791 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22792 TargetLowering::DAGCombinerInfo &DCI,
22793 const X86Subtarget *Subtarget) {
22794 EVT VT = N->getValueType(0);
22795 if (!VT.is256BitVector())
22798 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22799 N->getOpcode() == ISD::ZERO_EXTEND ||
22800 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22802 SDValue Narrow = N->getOperand(0);
22803 EVT NarrowVT = Narrow->getValueType(0);
22804 if (!NarrowVT.is128BitVector())
22807 if (Narrow->getOpcode() != ISD::XOR &&
22808 Narrow->getOpcode() != ISD::AND &&
22809 Narrow->getOpcode() != ISD::OR)
22812 SDValue N0 = Narrow->getOperand(0);
22813 SDValue N1 = Narrow->getOperand(1);
22816 // The Left side has to be a trunc.
22817 if (N0.getOpcode() != ISD::TRUNCATE)
22820 // The type of the truncated inputs.
22821 EVT WideVT = N0->getOperand(0)->getValueType(0);
22825 // The right side has to be a 'trunc' or a constant vector.
22826 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22827 ConstantSDNode *RHSConstSplat = nullptr;
22828 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22829 RHSConstSplat = RHSBV->getConstantSplatNode();
22830 if (!RHSTrunc && !RHSConstSplat)
22833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22835 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22838 // Set N0 and N1 to hold the inputs to the new wide operation.
22839 N0 = N0->getOperand(0);
22840 if (RHSConstSplat) {
22841 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22842 SDValue(RHSConstSplat, 0));
22843 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22844 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22845 } else if (RHSTrunc) {
22846 N1 = N1->getOperand(0);
22849 // Generate the wide operation.
22850 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22851 unsigned Opcode = N->getOpcode();
22853 case ISD::ANY_EXTEND:
22855 case ISD::ZERO_EXTEND: {
22856 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22857 APInt Mask = APInt::getAllOnesValue(InBits);
22858 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22859 return DAG.getNode(ISD::AND, DL, VT,
22860 Op, DAG.getConstant(Mask, VT));
22862 case ISD::SIGN_EXTEND:
22863 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22864 Op, DAG.getValueType(NarrowVT));
22866 llvm_unreachable("Unexpected opcode");
22870 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22871 TargetLowering::DAGCombinerInfo &DCI,
22872 const X86Subtarget *Subtarget) {
22873 EVT VT = N->getValueType(0);
22874 if (DCI.isBeforeLegalizeOps())
22877 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22881 // Create BEXTR instructions
22882 // BEXTR is ((X >> imm) & (2**size-1))
22883 if (VT == MVT::i32 || VT == MVT::i64) {
22884 SDValue N0 = N->getOperand(0);
22885 SDValue N1 = N->getOperand(1);
22888 // Check for BEXTR.
22889 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22890 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22891 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22892 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22893 if (MaskNode && ShiftNode) {
22894 uint64_t Mask = MaskNode->getZExtValue();
22895 uint64_t Shift = ShiftNode->getZExtValue();
22896 if (isMask_64(Mask)) {
22897 uint64_t MaskSize = CountPopulation_64(Mask);
22898 if (Shift + MaskSize <= VT.getSizeInBits())
22899 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22900 DAG.getConstant(Shift | (MaskSize << 8), VT));
22908 // Want to form ANDNP nodes:
22909 // 1) In the hopes of then easily combining them with OR and AND nodes
22910 // to form PBLEND/PSIGN.
22911 // 2) To match ANDN packed intrinsics
22912 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22915 SDValue N0 = N->getOperand(0);
22916 SDValue N1 = N->getOperand(1);
22919 // Check LHS for vnot
22920 if (N0.getOpcode() == ISD::XOR &&
22921 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22922 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22923 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22925 // Check RHS for vnot
22926 if (N1.getOpcode() == ISD::XOR &&
22927 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22928 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22929 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22934 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22935 TargetLowering::DAGCombinerInfo &DCI,
22936 const X86Subtarget *Subtarget) {
22937 if (DCI.isBeforeLegalizeOps())
22940 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22944 SDValue N0 = N->getOperand(0);
22945 SDValue N1 = N->getOperand(1);
22946 EVT VT = N->getValueType(0);
22948 // look for psign/blend
22949 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22950 if (!Subtarget->hasSSSE3() ||
22951 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22954 // Canonicalize pandn to RHS
22955 if (N0.getOpcode() == X86ISD::ANDNP)
22957 // or (and (m, y), (pandn m, x))
22958 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22959 SDValue Mask = N1.getOperand(0);
22960 SDValue X = N1.getOperand(1);
22962 if (N0.getOperand(0) == Mask)
22963 Y = N0.getOperand(1);
22964 if (N0.getOperand(1) == Mask)
22965 Y = N0.getOperand(0);
22967 // Check to see if the mask appeared in both the AND and ANDNP and
22971 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22972 // Look through mask bitcast.
22973 if (Mask.getOpcode() == ISD::BITCAST)
22974 Mask = Mask.getOperand(0);
22975 if (X.getOpcode() == ISD::BITCAST)
22976 X = X.getOperand(0);
22977 if (Y.getOpcode() == ISD::BITCAST)
22978 Y = Y.getOperand(0);
22980 EVT MaskVT = Mask.getValueType();
22982 // Validate that the Mask operand is a vector sra node.
22983 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22984 // there is no psrai.b
22985 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22986 unsigned SraAmt = ~0;
22987 if (Mask.getOpcode() == ISD::SRA) {
22988 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22989 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22990 SraAmt = AmtConst->getZExtValue();
22991 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22992 SDValue SraC = Mask.getOperand(1);
22993 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22995 if ((SraAmt + 1) != EltBits)
23000 // Now we know we at least have a plendvb with the mask val. See if
23001 // we can form a psignb/w/d.
23002 // psign = x.type == y.type == mask.type && y = sub(0, x);
23003 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23004 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23005 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23006 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23007 "Unsupported VT for PSIGN");
23008 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23009 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23011 // PBLENDVB only available on SSE 4.1
23012 if (!Subtarget->hasSSE41())
23015 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23017 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23018 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23019 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23020 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23021 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23025 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23028 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23029 MachineFunction &MF = DAG.getMachineFunction();
23030 bool OptForSize = MF.getFunction()->getAttributes().
23031 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23033 // SHLD/SHRD instructions have lower register pressure, but on some
23034 // platforms they have higher latency than the equivalent
23035 // series of shifts/or that would otherwise be generated.
23036 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23037 // have higher latencies and we are not optimizing for size.
23038 if (!OptForSize && Subtarget->isSHLDSlow())
23041 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23043 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23045 if (!N0.hasOneUse() || !N1.hasOneUse())
23048 SDValue ShAmt0 = N0.getOperand(1);
23049 if (ShAmt0.getValueType() != MVT::i8)
23051 SDValue ShAmt1 = N1.getOperand(1);
23052 if (ShAmt1.getValueType() != MVT::i8)
23054 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23055 ShAmt0 = ShAmt0.getOperand(0);
23056 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23057 ShAmt1 = ShAmt1.getOperand(0);
23060 unsigned Opc = X86ISD::SHLD;
23061 SDValue Op0 = N0.getOperand(0);
23062 SDValue Op1 = N1.getOperand(0);
23063 if (ShAmt0.getOpcode() == ISD::SUB) {
23064 Opc = X86ISD::SHRD;
23065 std::swap(Op0, Op1);
23066 std::swap(ShAmt0, ShAmt1);
23069 unsigned Bits = VT.getSizeInBits();
23070 if (ShAmt1.getOpcode() == ISD::SUB) {
23071 SDValue Sum = ShAmt1.getOperand(0);
23072 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23073 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23074 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23075 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23076 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23077 return DAG.getNode(Opc, DL, VT,
23079 DAG.getNode(ISD::TRUNCATE, DL,
23082 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23083 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23085 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23086 return DAG.getNode(Opc, DL, VT,
23087 N0.getOperand(0), N1.getOperand(0),
23088 DAG.getNode(ISD::TRUNCATE, DL,
23095 // Generate NEG and CMOV for integer abs.
23096 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23097 EVT VT = N->getValueType(0);
23099 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23100 // 8-bit integer abs to NEG and CMOV.
23101 if (VT.isInteger() && VT.getSizeInBits() == 8)
23104 SDValue N0 = N->getOperand(0);
23105 SDValue N1 = N->getOperand(1);
23108 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23109 // and change it to SUB and CMOV.
23110 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23111 N0.getOpcode() == ISD::ADD &&
23112 N0.getOperand(1) == N1 &&
23113 N1.getOpcode() == ISD::SRA &&
23114 N1.getOperand(0) == N0.getOperand(0))
23115 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23116 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23117 // Generate SUB & CMOV.
23118 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23119 DAG.getConstant(0, VT), N0.getOperand(0));
23121 SDValue Ops[] = { N0.getOperand(0), Neg,
23122 DAG.getConstant(X86::COND_GE, MVT::i8),
23123 SDValue(Neg.getNode(), 1) };
23124 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23129 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23130 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23131 TargetLowering::DAGCombinerInfo &DCI,
23132 const X86Subtarget *Subtarget) {
23133 if (DCI.isBeforeLegalizeOps())
23136 if (Subtarget->hasCMov()) {
23137 SDValue RV = performIntegerAbsCombine(N, DAG);
23145 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23146 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23147 TargetLowering::DAGCombinerInfo &DCI,
23148 const X86Subtarget *Subtarget) {
23149 LoadSDNode *Ld = cast<LoadSDNode>(N);
23150 EVT RegVT = Ld->getValueType(0);
23151 EVT MemVT = Ld->getMemoryVT();
23153 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23155 // On Sandybridge unaligned 256bit loads are inefficient.
23156 ISD::LoadExtType Ext = Ld->getExtensionType();
23157 unsigned Alignment = Ld->getAlignment();
23158 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23159 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23160 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23161 unsigned NumElems = RegVT.getVectorNumElements();
23165 SDValue Ptr = Ld->getBasePtr();
23166 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23168 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23170 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23171 Ld->getPointerInfo(), Ld->isVolatile(),
23172 Ld->isNonTemporal(), Ld->isInvariant(),
23174 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23175 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23176 Ld->getPointerInfo(), Ld->isVolatile(),
23177 Ld->isNonTemporal(), Ld->isInvariant(),
23178 std::min(16U, Alignment));
23179 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23181 Load2.getValue(1));
23183 SDValue NewVec = DAG.getUNDEF(RegVT);
23184 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23185 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23186 return DCI.CombineTo(N, NewVec, TF, true);
23192 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23193 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23194 const X86Subtarget *Subtarget) {
23195 StoreSDNode *St = cast<StoreSDNode>(N);
23196 EVT VT = St->getValue().getValueType();
23197 EVT StVT = St->getMemoryVT();
23199 SDValue StoredVal = St->getOperand(1);
23200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23202 // If we are saving a concatenation of two XMM registers, perform two stores.
23203 // On Sandy Bridge, 256-bit memory operations are executed by two
23204 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23205 // memory operation.
23206 unsigned Alignment = St->getAlignment();
23207 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23208 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23209 StVT == VT && !IsAligned) {
23210 unsigned NumElems = VT.getVectorNumElements();
23214 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23215 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23217 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23218 SDValue Ptr0 = St->getBasePtr();
23219 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23221 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23222 St->getPointerInfo(), St->isVolatile(),
23223 St->isNonTemporal(), Alignment);
23224 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23225 St->getPointerInfo(), St->isVolatile(),
23226 St->isNonTemporal(),
23227 std::min(16U, Alignment));
23228 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23231 // Optimize trunc store (of multiple scalars) to shuffle and store.
23232 // First, pack all of the elements in one place. Next, store to memory
23233 // in fewer chunks.
23234 if (St->isTruncatingStore() && VT.isVector()) {
23235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23236 unsigned NumElems = VT.getVectorNumElements();
23237 assert(StVT != VT && "Cannot truncate to the same type");
23238 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23239 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23241 // From, To sizes and ElemCount must be pow of two
23242 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23243 // We are going to use the original vector elt for storing.
23244 // Accumulated smaller vector elements must be a multiple of the store size.
23245 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23247 unsigned SizeRatio = FromSz / ToSz;
23249 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23251 // Create a type on which we perform the shuffle
23252 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23253 StVT.getScalarType(), NumElems*SizeRatio);
23255 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23257 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23258 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23259 for (unsigned i = 0; i != NumElems; ++i)
23260 ShuffleVec[i] = i * SizeRatio;
23262 // Can't shuffle using an illegal type.
23263 if (!TLI.isTypeLegal(WideVecVT))
23266 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23267 DAG.getUNDEF(WideVecVT),
23269 // At this point all of the data is stored at the bottom of the
23270 // register. We now need to save it to mem.
23272 // Find the largest store unit
23273 MVT StoreType = MVT::i8;
23274 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23275 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23276 MVT Tp = (MVT::SimpleValueType)tp;
23277 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23281 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23282 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23283 (64 <= NumElems * ToSz))
23284 StoreType = MVT::f64;
23286 // Bitcast the original vector into a vector of store-size units
23287 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23288 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23289 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23290 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23291 SmallVector<SDValue, 8> Chains;
23292 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23293 TLI.getPointerTy());
23294 SDValue Ptr = St->getBasePtr();
23296 // Perform one or more big stores into memory.
23297 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23298 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23299 StoreType, ShuffWide,
23300 DAG.getIntPtrConstant(i));
23301 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23302 St->getPointerInfo(), St->isVolatile(),
23303 St->isNonTemporal(), St->getAlignment());
23304 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23305 Chains.push_back(Ch);
23308 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23311 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23312 // the FP state in cases where an emms may be missing.
23313 // A preferable solution to the general problem is to figure out the right
23314 // places to insert EMMS. This qualifies as a quick hack.
23316 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23317 if (VT.getSizeInBits() != 64)
23320 const Function *F = DAG.getMachineFunction().getFunction();
23321 bool NoImplicitFloatOps = F->getAttributes().
23322 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23323 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23324 && Subtarget->hasSSE2();
23325 if ((VT.isVector() ||
23326 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23327 isa<LoadSDNode>(St->getValue()) &&
23328 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23329 St->getChain().hasOneUse() && !St->isVolatile()) {
23330 SDNode* LdVal = St->getValue().getNode();
23331 LoadSDNode *Ld = nullptr;
23332 int TokenFactorIndex = -1;
23333 SmallVector<SDValue, 8> Ops;
23334 SDNode* ChainVal = St->getChain().getNode();
23335 // Must be a store of a load. We currently handle two cases: the load
23336 // is a direct child, and it's under an intervening TokenFactor. It is
23337 // possible to dig deeper under nested TokenFactors.
23338 if (ChainVal == LdVal)
23339 Ld = cast<LoadSDNode>(St->getChain());
23340 else if (St->getValue().hasOneUse() &&
23341 ChainVal->getOpcode() == ISD::TokenFactor) {
23342 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23343 if (ChainVal->getOperand(i).getNode() == LdVal) {
23344 TokenFactorIndex = i;
23345 Ld = cast<LoadSDNode>(St->getValue());
23347 Ops.push_back(ChainVal->getOperand(i));
23351 if (!Ld || !ISD::isNormalLoad(Ld))
23354 // If this is not the MMX case, i.e. we are just turning i64 load/store
23355 // into f64 load/store, avoid the transformation if there are multiple
23356 // uses of the loaded value.
23357 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23362 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23363 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23365 if (Subtarget->is64Bit() || F64IsLegal) {
23366 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23367 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23368 Ld->getPointerInfo(), Ld->isVolatile(),
23369 Ld->isNonTemporal(), Ld->isInvariant(),
23370 Ld->getAlignment());
23371 SDValue NewChain = NewLd.getValue(1);
23372 if (TokenFactorIndex != -1) {
23373 Ops.push_back(NewChain);
23374 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23376 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23377 St->getPointerInfo(),
23378 St->isVolatile(), St->isNonTemporal(),
23379 St->getAlignment());
23382 // Otherwise, lower to two pairs of 32-bit loads / stores.
23383 SDValue LoAddr = Ld->getBasePtr();
23384 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23385 DAG.getConstant(4, MVT::i32));
23387 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23388 Ld->getPointerInfo(),
23389 Ld->isVolatile(), Ld->isNonTemporal(),
23390 Ld->isInvariant(), Ld->getAlignment());
23391 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23392 Ld->getPointerInfo().getWithOffset(4),
23393 Ld->isVolatile(), Ld->isNonTemporal(),
23395 MinAlign(Ld->getAlignment(), 4));
23397 SDValue NewChain = LoLd.getValue(1);
23398 if (TokenFactorIndex != -1) {
23399 Ops.push_back(LoLd);
23400 Ops.push_back(HiLd);
23401 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23404 LoAddr = St->getBasePtr();
23405 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23406 DAG.getConstant(4, MVT::i32));
23408 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23409 St->getPointerInfo(),
23410 St->isVolatile(), St->isNonTemporal(),
23411 St->getAlignment());
23412 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23413 St->getPointerInfo().getWithOffset(4),
23415 St->isNonTemporal(),
23416 MinAlign(St->getAlignment(), 4));
23417 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23422 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23423 /// and return the operands for the horizontal operation in LHS and RHS. A
23424 /// horizontal operation performs the binary operation on successive elements
23425 /// of its first operand, then on successive elements of its second operand,
23426 /// returning the resulting values in a vector. For example, if
23427 /// A = < float a0, float a1, float a2, float a3 >
23429 /// B = < float b0, float b1, float b2, float b3 >
23430 /// then the result of doing a horizontal operation on A and B is
23431 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23432 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23433 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23434 /// set to A, RHS to B, and the routine returns 'true'.
23435 /// Note that the binary operation should have the property that if one of the
23436 /// operands is UNDEF then the result is UNDEF.
23437 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23438 // Look for the following pattern: if
23439 // A = < float a0, float a1, float a2, float a3 >
23440 // B = < float b0, float b1, float b2, float b3 >
23442 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23443 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23444 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23445 // which is A horizontal-op B.
23447 // At least one of the operands should be a vector shuffle.
23448 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23449 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23452 MVT VT = LHS.getSimpleValueType();
23454 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23455 "Unsupported vector type for horizontal add/sub");
23457 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23458 // operate independently on 128-bit lanes.
23459 unsigned NumElts = VT.getVectorNumElements();
23460 unsigned NumLanes = VT.getSizeInBits()/128;
23461 unsigned NumLaneElts = NumElts / NumLanes;
23462 assert((NumLaneElts % 2 == 0) &&
23463 "Vector type should have an even number of elements in each lane");
23464 unsigned HalfLaneElts = NumLaneElts/2;
23466 // View LHS in the form
23467 // LHS = VECTOR_SHUFFLE A, B, LMask
23468 // If LHS is not a shuffle then pretend it is the shuffle
23469 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23470 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23473 SmallVector<int, 16> LMask(NumElts);
23474 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23475 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23476 A = LHS.getOperand(0);
23477 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23478 B = LHS.getOperand(1);
23479 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23480 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23482 if (LHS.getOpcode() != ISD::UNDEF)
23484 for (unsigned i = 0; i != NumElts; ++i)
23488 // Likewise, view RHS in the form
23489 // RHS = VECTOR_SHUFFLE C, D, RMask
23491 SmallVector<int, 16> RMask(NumElts);
23492 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23493 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23494 C = RHS.getOperand(0);
23495 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23496 D = RHS.getOperand(1);
23497 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23498 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23500 if (RHS.getOpcode() != ISD::UNDEF)
23502 for (unsigned i = 0; i != NumElts; ++i)
23506 // Check that the shuffles are both shuffling the same vectors.
23507 if (!(A == C && B == D) && !(A == D && B == C))
23510 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23511 if (!A.getNode() && !B.getNode())
23514 // If A and B occur in reverse order in RHS, then "swap" them (which means
23515 // rewriting the mask).
23517 CommuteVectorShuffleMask(RMask, NumElts);
23519 // At this point LHS and RHS are equivalent to
23520 // LHS = VECTOR_SHUFFLE A, B, LMask
23521 // RHS = VECTOR_SHUFFLE A, B, RMask
23522 // Check that the masks correspond to performing a horizontal operation.
23523 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23524 for (unsigned i = 0; i != NumLaneElts; ++i) {
23525 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23527 // Ignore any UNDEF components.
23528 if (LIdx < 0 || RIdx < 0 ||
23529 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23530 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23533 // Check that successive elements are being operated on. If not, this is
23534 // not a horizontal operation.
23535 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23536 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23537 if (!(LIdx == Index && RIdx == Index + 1) &&
23538 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23543 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23544 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23548 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23549 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23550 const X86Subtarget *Subtarget) {
23551 EVT VT = N->getValueType(0);
23552 SDValue LHS = N->getOperand(0);
23553 SDValue RHS = N->getOperand(1);
23555 // Try to synthesize horizontal adds from adds of shuffles.
23556 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23557 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23558 isHorizontalBinOp(LHS, RHS, true))
23559 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23563 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23564 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23565 const X86Subtarget *Subtarget) {
23566 EVT VT = N->getValueType(0);
23567 SDValue LHS = N->getOperand(0);
23568 SDValue RHS = N->getOperand(1);
23570 // Try to synthesize horizontal subs from subs of shuffles.
23571 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23572 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23573 isHorizontalBinOp(LHS, RHS, false))
23574 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23578 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23579 /// X86ISD::FXOR nodes.
23580 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23581 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23582 // F[X]OR(0.0, x) -> x
23583 // F[X]OR(x, 0.0) -> x
23584 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23585 if (C->getValueAPF().isPosZero())
23586 return N->getOperand(1);
23587 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23588 if (C->getValueAPF().isPosZero())
23589 return N->getOperand(0);
23593 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23594 /// X86ISD::FMAX nodes.
23595 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23596 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23598 // Only perform optimizations if UnsafeMath is used.
23599 if (!DAG.getTarget().Options.UnsafeFPMath)
23602 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23603 // into FMINC and FMAXC, which are Commutative operations.
23604 unsigned NewOp = 0;
23605 switch (N->getOpcode()) {
23606 default: llvm_unreachable("unknown opcode");
23607 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23608 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23611 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23612 N->getOperand(0), N->getOperand(1));
23615 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23616 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23617 // FAND(0.0, x) -> 0.0
23618 // FAND(x, 0.0) -> 0.0
23619 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23620 if (C->getValueAPF().isPosZero())
23621 return N->getOperand(0);
23622 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23623 if (C->getValueAPF().isPosZero())
23624 return N->getOperand(1);
23628 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23629 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23630 // FANDN(x, 0.0) -> 0.0
23631 // FANDN(0.0, x) -> x
23632 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23633 if (C->getValueAPF().isPosZero())
23634 return N->getOperand(1);
23635 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23636 if (C->getValueAPF().isPosZero())
23637 return N->getOperand(1);
23641 static SDValue PerformBTCombine(SDNode *N,
23643 TargetLowering::DAGCombinerInfo &DCI) {
23644 // BT ignores high bits in the bit index operand.
23645 SDValue Op1 = N->getOperand(1);
23646 if (Op1.hasOneUse()) {
23647 unsigned BitWidth = Op1.getValueSizeInBits();
23648 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23649 APInt KnownZero, KnownOne;
23650 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23651 !DCI.isBeforeLegalizeOps());
23652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23653 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23654 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23655 DCI.CommitTargetLoweringOpt(TLO);
23660 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23661 SDValue Op = N->getOperand(0);
23662 if (Op.getOpcode() == ISD::BITCAST)
23663 Op = Op.getOperand(0);
23664 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23665 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23666 VT.getVectorElementType().getSizeInBits() ==
23667 OpVT.getVectorElementType().getSizeInBits()) {
23668 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23673 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23674 const X86Subtarget *Subtarget) {
23675 EVT VT = N->getValueType(0);
23676 if (!VT.isVector())
23679 SDValue N0 = N->getOperand(0);
23680 SDValue N1 = N->getOperand(1);
23681 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23684 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23685 // both SSE and AVX2 since there is no sign-extended shift right
23686 // operation on a vector with 64-bit elements.
23687 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23688 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23689 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23690 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23691 SDValue N00 = N0.getOperand(0);
23693 // EXTLOAD has a better solution on AVX2,
23694 // it may be replaced with X86ISD::VSEXT node.
23695 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23696 if (!ISD::isNormalLoad(N00.getNode()))
23699 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23700 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23702 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23708 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23709 TargetLowering::DAGCombinerInfo &DCI,
23710 const X86Subtarget *Subtarget) {
23711 if (!DCI.isBeforeLegalizeOps())
23714 if (!Subtarget->hasFp256())
23717 EVT VT = N->getValueType(0);
23718 if (VT.isVector() && VT.getSizeInBits() == 256) {
23719 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23727 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23728 const X86Subtarget* Subtarget) {
23730 EVT VT = N->getValueType(0);
23732 // Let legalize expand this if it isn't a legal type yet.
23733 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23736 EVT ScalarVT = VT.getScalarType();
23737 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23738 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23741 SDValue A = N->getOperand(0);
23742 SDValue B = N->getOperand(1);
23743 SDValue C = N->getOperand(2);
23745 bool NegA = (A.getOpcode() == ISD::FNEG);
23746 bool NegB = (B.getOpcode() == ISD::FNEG);
23747 bool NegC = (C.getOpcode() == ISD::FNEG);
23749 // Negative multiplication when NegA xor NegB
23750 bool NegMul = (NegA != NegB);
23752 A = A.getOperand(0);
23754 B = B.getOperand(0);
23756 C = C.getOperand(0);
23760 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23762 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23764 return DAG.getNode(Opcode, dl, VT, A, B, C);
23767 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23768 TargetLowering::DAGCombinerInfo &DCI,
23769 const X86Subtarget *Subtarget) {
23770 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23771 // (and (i32 x86isd::setcc_carry), 1)
23772 // This eliminates the zext. This transformation is necessary because
23773 // ISD::SETCC is always legalized to i8.
23775 SDValue N0 = N->getOperand(0);
23776 EVT VT = N->getValueType(0);
23778 if (N0.getOpcode() == ISD::AND &&
23780 N0.getOperand(0).hasOneUse()) {
23781 SDValue N00 = N0.getOperand(0);
23782 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23783 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23784 if (!C || C->getZExtValue() != 1)
23786 return DAG.getNode(ISD::AND, dl, VT,
23787 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23788 N00.getOperand(0), N00.getOperand(1)),
23789 DAG.getConstant(1, VT));
23793 if (N0.getOpcode() == ISD::TRUNCATE &&
23795 N0.getOperand(0).hasOneUse()) {
23796 SDValue N00 = N0.getOperand(0);
23797 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23798 return DAG.getNode(ISD::AND, dl, VT,
23799 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23800 N00.getOperand(0), N00.getOperand(1)),
23801 DAG.getConstant(1, VT));
23804 if (VT.is256BitVector()) {
23805 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23813 // Optimize x == -y --> x+y == 0
23814 // x != -y --> x+y != 0
23815 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23816 const X86Subtarget* Subtarget) {
23817 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23818 SDValue LHS = N->getOperand(0);
23819 SDValue RHS = N->getOperand(1);
23820 EVT VT = N->getValueType(0);
23823 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23824 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23825 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23826 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23827 LHS.getValueType(), RHS, LHS.getOperand(1));
23828 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23829 addV, DAG.getConstant(0, addV.getValueType()), CC);
23831 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23833 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23834 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23835 RHS.getValueType(), LHS, RHS.getOperand(1));
23836 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23837 addV, DAG.getConstant(0, addV.getValueType()), CC);
23840 if (VT.getScalarType() == MVT::i1) {
23841 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23842 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23843 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23844 if (!IsSEXT0 && !IsVZero0)
23846 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23847 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23848 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23850 if (!IsSEXT1 && !IsVZero1)
23853 if (IsSEXT0 && IsVZero1) {
23854 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23855 if (CC == ISD::SETEQ)
23856 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23857 return LHS.getOperand(0);
23859 if (IsSEXT1 && IsVZero0) {
23860 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23861 if (CC == ISD::SETEQ)
23862 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23863 return RHS.getOperand(0);
23870 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23871 const X86Subtarget *Subtarget) {
23873 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23874 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23875 "X86insertps is only defined for v4x32");
23877 SDValue Ld = N->getOperand(1);
23878 if (MayFoldLoad(Ld)) {
23879 // Extract the countS bits from the immediate so we can get the proper
23880 // address when narrowing the vector load to a specific element.
23881 // When the second source op is a memory address, interps doesn't use
23882 // countS and just gets an f32 from that address.
23883 unsigned DestIndex =
23884 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23885 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23889 // Create this as a scalar to vector to match the instruction pattern.
23890 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23891 // countS bits are ignored when loading from memory on insertps, which
23892 // means we don't need to explicitly set them to 0.
23893 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23894 LoadScalarToVector, N->getOperand(2));
23897 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23898 // as "sbb reg,reg", since it can be extended without zext and produces
23899 // an all-ones bit which is more useful than 0/1 in some cases.
23900 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23903 return DAG.getNode(ISD::AND, DL, VT,
23904 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23905 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23906 DAG.getConstant(1, VT));
23907 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23908 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23909 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23910 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23913 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23914 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23915 TargetLowering::DAGCombinerInfo &DCI,
23916 const X86Subtarget *Subtarget) {
23918 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23919 SDValue EFLAGS = N->getOperand(1);
23921 if (CC == X86::COND_A) {
23922 // Try to convert COND_A into COND_B in an attempt to facilitate
23923 // materializing "setb reg".
23925 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23926 // cannot take an immediate as its first operand.
23928 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23929 EFLAGS.getValueType().isInteger() &&
23930 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23931 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23932 EFLAGS.getNode()->getVTList(),
23933 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23934 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23935 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23939 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23940 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23942 if (CC == X86::COND_B)
23943 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23947 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23948 if (Flags.getNode()) {
23949 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23950 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23956 // Optimize branch condition evaluation.
23958 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23959 TargetLowering::DAGCombinerInfo &DCI,
23960 const X86Subtarget *Subtarget) {
23962 SDValue Chain = N->getOperand(0);
23963 SDValue Dest = N->getOperand(1);
23964 SDValue EFLAGS = N->getOperand(3);
23965 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23969 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23970 if (Flags.getNode()) {
23971 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23972 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23979 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23980 SelectionDAG &DAG) {
23981 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23982 // optimize away operation when it's from a constant.
23984 // The general transformation is:
23985 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23986 // AND(VECTOR_CMP(x,y), constant2)
23987 // constant2 = UNARYOP(constant)
23989 // Early exit if this isn't a vector operation, the operand of the
23990 // unary operation isn't a bitwise AND, or if the sizes of the operations
23991 // aren't the same.
23992 EVT VT = N->getValueType(0);
23993 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23994 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23995 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23998 // Now check that the other operand of the AND is a constant. We could
23999 // make the transformation for non-constant splats as well, but it's unclear
24000 // that would be a benefit as it would not eliminate any operations, just
24001 // perform one more step in scalar code before moving to the vector unit.
24002 if (BuildVectorSDNode *BV =
24003 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24004 // Bail out if the vector isn't a constant.
24005 if (!BV->isConstant())
24008 // Everything checks out. Build up the new and improved node.
24010 EVT IntVT = BV->getValueType(0);
24011 // Create a new constant of the appropriate type for the transformed
24013 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24014 // The AND node needs bitcasts to/from an integer vector type around it.
24015 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24016 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24017 N->getOperand(0)->getOperand(0), MaskConst);
24018 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24025 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24026 const X86TargetLowering *XTLI) {
24027 // First try to optimize away the conversion entirely when it's
24028 // conditionally from a constant. Vectors only.
24029 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24030 if (Res != SDValue())
24033 // Now move on to more general possibilities.
24034 SDValue Op0 = N->getOperand(0);
24035 EVT InVT = Op0->getValueType(0);
24037 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24038 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24040 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24041 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24042 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24045 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24046 // a 32-bit target where SSE doesn't support i64->FP operations.
24047 if (Op0.getOpcode() == ISD::LOAD) {
24048 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24049 EVT VT = Ld->getValueType(0);
24050 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24051 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24052 !XTLI->getSubtarget()->is64Bit() &&
24054 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24055 Ld->getChain(), Op0, DAG);
24056 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24063 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24064 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24065 X86TargetLowering::DAGCombinerInfo &DCI) {
24066 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24067 // the result is either zero or one (depending on the input carry bit).
24068 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24069 if (X86::isZeroNode(N->getOperand(0)) &&
24070 X86::isZeroNode(N->getOperand(1)) &&
24071 // We don't have a good way to replace an EFLAGS use, so only do this when
24073 SDValue(N, 1).use_empty()) {
24075 EVT VT = N->getValueType(0);
24076 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24077 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24078 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24079 DAG.getConstant(X86::COND_B,MVT::i8),
24081 DAG.getConstant(1, VT));
24082 return DCI.CombineTo(N, Res1, CarryOut);
24088 // fold (add Y, (sete X, 0)) -> adc 0, Y
24089 // (add Y, (setne X, 0)) -> sbb -1, Y
24090 // (sub (sete X, 0), Y) -> sbb 0, Y
24091 // (sub (setne X, 0), Y) -> adc -1, Y
24092 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24095 // Look through ZExts.
24096 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24097 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24100 SDValue SetCC = Ext.getOperand(0);
24101 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24104 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24105 if (CC != X86::COND_E && CC != X86::COND_NE)
24108 SDValue Cmp = SetCC.getOperand(1);
24109 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24110 !X86::isZeroNode(Cmp.getOperand(1)) ||
24111 !Cmp.getOperand(0).getValueType().isInteger())
24114 SDValue CmpOp0 = Cmp.getOperand(0);
24115 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24116 DAG.getConstant(1, CmpOp0.getValueType()));
24118 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24119 if (CC == X86::COND_NE)
24120 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24121 DL, OtherVal.getValueType(), OtherVal,
24122 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24123 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24124 DL, OtherVal.getValueType(), OtherVal,
24125 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24128 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24129 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24130 const X86Subtarget *Subtarget) {
24131 EVT VT = N->getValueType(0);
24132 SDValue Op0 = N->getOperand(0);
24133 SDValue Op1 = N->getOperand(1);
24135 // Try to synthesize horizontal adds from adds of shuffles.
24136 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24137 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24138 isHorizontalBinOp(Op0, Op1, true))
24139 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24141 return OptimizeConditionalInDecrement(N, DAG);
24144 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24145 const X86Subtarget *Subtarget) {
24146 SDValue Op0 = N->getOperand(0);
24147 SDValue Op1 = N->getOperand(1);
24149 // X86 can't encode an immediate LHS of a sub. See if we can push the
24150 // negation into a preceding instruction.
24151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24152 // If the RHS of the sub is a XOR with one use and a constant, invert the
24153 // immediate. Then add one to the LHS of the sub so we can turn
24154 // X-Y -> X+~Y+1, saving one register.
24155 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24156 isa<ConstantSDNode>(Op1.getOperand(1))) {
24157 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24158 EVT VT = Op0.getValueType();
24159 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24161 DAG.getConstant(~XorC, VT));
24162 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24163 DAG.getConstant(C->getAPIntValue()+1, VT));
24167 // Try to synthesize horizontal adds from adds of shuffles.
24168 EVT VT = N->getValueType(0);
24169 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24170 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24171 isHorizontalBinOp(Op0, Op1, true))
24172 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24174 return OptimizeConditionalInDecrement(N, DAG);
24177 /// performVZEXTCombine - Performs build vector combines
24178 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24179 TargetLowering::DAGCombinerInfo &DCI,
24180 const X86Subtarget *Subtarget) {
24181 // (vzext (bitcast (vzext (x)) -> (vzext x)
24182 SDValue In = N->getOperand(0);
24183 while (In.getOpcode() == ISD::BITCAST)
24184 In = In.getOperand(0);
24186 if (In.getOpcode() != X86ISD::VZEXT)
24189 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24193 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24194 DAGCombinerInfo &DCI) const {
24195 SelectionDAG &DAG = DCI.DAG;
24196 switch (N->getOpcode()) {
24198 case ISD::EXTRACT_VECTOR_ELT:
24199 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24201 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24202 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24203 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24204 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24205 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24206 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24209 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24210 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24211 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24212 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24213 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24214 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24215 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24216 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24217 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24219 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24221 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24222 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24223 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24224 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24225 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24226 case ISD::ANY_EXTEND:
24227 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24228 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24229 case ISD::SIGN_EXTEND_INREG:
24230 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24231 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24232 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24233 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24234 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24235 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24236 case X86ISD::SHUFP: // Handle all target specific shuffles
24237 case X86ISD::PALIGNR:
24238 case X86ISD::UNPCKH:
24239 case X86ISD::UNPCKL:
24240 case X86ISD::MOVHLPS:
24241 case X86ISD::MOVLHPS:
24242 case X86ISD::PSHUFB:
24243 case X86ISD::PSHUFD:
24244 case X86ISD::PSHUFHW:
24245 case X86ISD::PSHUFLW:
24246 case X86ISD::MOVSS:
24247 case X86ISD::MOVSD:
24248 case X86ISD::VPERMILPI:
24249 case X86ISD::VPERM2X128:
24250 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24251 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24252 case ISD::INTRINSIC_WO_CHAIN:
24253 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24254 case X86ISD::INSERTPS:
24255 return PerformINSERTPSCombine(N, DAG, Subtarget);
24256 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24262 /// isTypeDesirableForOp - Return true if the target has native support for
24263 /// the specified value type and it is 'desirable' to use the type for the
24264 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24265 /// instruction encodings are longer and some i16 instructions are slow.
24266 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24267 if (!isTypeLegal(VT))
24269 if (VT != MVT::i16)
24276 case ISD::SIGN_EXTEND:
24277 case ISD::ZERO_EXTEND:
24278 case ISD::ANY_EXTEND:
24291 /// IsDesirableToPromoteOp - This method query the target whether it is
24292 /// beneficial for dag combiner to promote the specified node. If true, it
24293 /// should return the desired promotion type by reference.
24294 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24295 EVT VT = Op.getValueType();
24296 if (VT != MVT::i16)
24299 bool Promote = false;
24300 bool Commute = false;
24301 switch (Op.getOpcode()) {
24304 LoadSDNode *LD = cast<LoadSDNode>(Op);
24305 // If the non-extending load has a single use and it's not live out, then it
24306 // might be folded.
24307 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24308 Op.hasOneUse()*/) {
24309 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24310 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24311 // The only case where we'd want to promote LOAD (rather then it being
24312 // promoted as an operand is when it's only use is liveout.
24313 if (UI->getOpcode() != ISD::CopyToReg)
24320 case ISD::SIGN_EXTEND:
24321 case ISD::ZERO_EXTEND:
24322 case ISD::ANY_EXTEND:
24327 SDValue N0 = Op.getOperand(0);
24328 // Look out for (store (shl (load), x)).
24329 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24342 SDValue N0 = Op.getOperand(0);
24343 SDValue N1 = Op.getOperand(1);
24344 if (!Commute && MayFoldLoad(N1))
24346 // Avoid disabling potential load folding opportunities.
24347 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24349 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24359 //===----------------------------------------------------------------------===//
24360 // X86 Inline Assembly Support
24361 //===----------------------------------------------------------------------===//
24364 // Helper to match a string separated by whitespace.
24365 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24366 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24368 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24369 StringRef piece(*args[i]);
24370 if (!s.startswith(piece)) // Check if the piece matches.
24373 s = s.substr(piece.size());
24374 StringRef::size_type pos = s.find_first_not_of(" \t");
24375 if (pos == 0) // We matched a prefix.
24383 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24386 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24388 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24389 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24390 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24391 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24393 if (AsmPieces.size() == 3)
24395 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24402 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24403 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24405 std::string AsmStr = IA->getAsmString();
24407 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24408 if (!Ty || Ty->getBitWidth() % 16 != 0)
24411 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24412 SmallVector<StringRef, 4> AsmPieces;
24413 SplitString(AsmStr, AsmPieces, ";\n");
24415 switch (AsmPieces.size()) {
24416 default: return false;
24418 // FIXME: this should verify that we are targeting a 486 or better. If not,
24419 // we will turn this bswap into something that will be lowered to logical
24420 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24421 // lower so don't worry about this.
24423 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24424 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24425 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24426 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24427 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24428 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24429 // No need to check constraints, nothing other than the equivalent of
24430 // "=r,0" would be valid here.
24431 return IntrinsicLowering::LowerToByteSwap(CI);
24434 // rorw $$8, ${0:w} --> llvm.bswap.i16
24435 if (CI->getType()->isIntegerTy(16) &&
24436 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24437 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24438 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24440 const std::string &ConstraintsStr = IA->getConstraintString();
24441 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24442 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24443 if (clobbersFlagRegisters(AsmPieces))
24444 return IntrinsicLowering::LowerToByteSwap(CI);
24448 if (CI->getType()->isIntegerTy(32) &&
24449 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24450 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24451 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24452 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24454 const std::string &ConstraintsStr = IA->getConstraintString();
24455 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24456 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24457 if (clobbersFlagRegisters(AsmPieces))
24458 return IntrinsicLowering::LowerToByteSwap(CI);
24461 if (CI->getType()->isIntegerTy(64)) {
24462 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24463 if (Constraints.size() >= 2 &&
24464 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24465 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24466 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24467 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24468 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24469 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24470 return IntrinsicLowering::LowerToByteSwap(CI);
24478 /// getConstraintType - Given a constraint letter, return the type of
24479 /// constraint it is for this target.
24480 X86TargetLowering::ConstraintType
24481 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24482 if (Constraint.size() == 1) {
24483 switch (Constraint[0]) {
24494 return C_RegisterClass;
24518 return TargetLowering::getConstraintType(Constraint);
24521 /// Examine constraint type and operand type and determine a weight value.
24522 /// This object must already have been set up with the operand type
24523 /// and the current alternative constraint selected.
24524 TargetLowering::ConstraintWeight
24525 X86TargetLowering::getSingleConstraintMatchWeight(
24526 AsmOperandInfo &info, const char *constraint) const {
24527 ConstraintWeight weight = CW_Invalid;
24528 Value *CallOperandVal = info.CallOperandVal;
24529 // If we don't have a value, we can't do a match,
24530 // but allow it at the lowest weight.
24531 if (!CallOperandVal)
24533 Type *type = CallOperandVal->getType();
24534 // Look at the constraint type.
24535 switch (*constraint) {
24537 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24548 if (CallOperandVal->getType()->isIntegerTy())
24549 weight = CW_SpecificReg;
24554 if (type->isFloatingPointTy())
24555 weight = CW_SpecificReg;
24558 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24559 weight = CW_SpecificReg;
24563 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24564 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24565 weight = CW_Register;
24568 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24569 if (C->getZExtValue() <= 31)
24570 weight = CW_Constant;
24574 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24575 if (C->getZExtValue() <= 63)
24576 weight = CW_Constant;
24580 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24581 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24582 weight = CW_Constant;
24586 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24587 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24588 weight = CW_Constant;
24592 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24593 if (C->getZExtValue() <= 3)
24594 weight = CW_Constant;
24598 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24599 if (C->getZExtValue() <= 0xff)
24600 weight = CW_Constant;
24605 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24606 weight = CW_Constant;
24610 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24611 if ((C->getSExtValue() >= -0x80000000LL) &&
24612 (C->getSExtValue() <= 0x7fffffffLL))
24613 weight = CW_Constant;
24617 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24618 if (C->getZExtValue() <= 0xffffffff)
24619 weight = CW_Constant;
24626 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24627 /// with another that has more specific requirements based on the type of the
24628 /// corresponding operand.
24629 const char *X86TargetLowering::
24630 LowerXConstraint(EVT ConstraintVT) const {
24631 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24632 // 'f' like normal targets.
24633 if (ConstraintVT.isFloatingPoint()) {
24634 if (Subtarget->hasSSE2())
24636 if (Subtarget->hasSSE1())
24640 return TargetLowering::LowerXConstraint(ConstraintVT);
24643 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24644 /// vector. If it is invalid, don't add anything to Ops.
24645 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24646 std::string &Constraint,
24647 std::vector<SDValue>&Ops,
24648 SelectionDAG &DAG) const {
24651 // Only support length 1 constraints for now.
24652 if (Constraint.length() > 1) return;
24654 char ConstraintLetter = Constraint[0];
24655 switch (ConstraintLetter) {
24658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24659 if (C->getZExtValue() <= 31) {
24660 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24666 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24667 if (C->getZExtValue() <= 63) {
24668 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24674 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24675 if (isInt<8>(C->getSExtValue())) {
24676 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24682 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24683 if (C->getZExtValue() <= 255) {
24684 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24690 // 32-bit signed value
24691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24692 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24693 C->getSExtValue())) {
24694 // Widen to 64 bits here to get it sign extended.
24695 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24698 // FIXME gcc accepts some relocatable values here too, but only in certain
24699 // memory models; it's complicated.
24704 // 32-bit unsigned value
24705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24706 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24707 C->getZExtValue())) {
24708 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24712 // FIXME gcc accepts some relocatable values here too, but only in certain
24713 // memory models; it's complicated.
24717 // Literal immediates are always ok.
24718 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24719 // Widen to 64 bits here to get it sign extended.
24720 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24724 // In any sort of PIC mode addresses need to be computed at runtime by
24725 // adding in a register or some sort of table lookup. These can't
24726 // be used as immediates.
24727 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24730 // If we are in non-pic codegen mode, we allow the address of a global (with
24731 // an optional displacement) to be used with 'i'.
24732 GlobalAddressSDNode *GA = nullptr;
24733 int64_t Offset = 0;
24735 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24737 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24738 Offset += GA->getOffset();
24740 } else if (Op.getOpcode() == ISD::ADD) {
24741 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24742 Offset += C->getZExtValue();
24743 Op = Op.getOperand(0);
24746 } else if (Op.getOpcode() == ISD::SUB) {
24747 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24748 Offset += -C->getZExtValue();
24749 Op = Op.getOperand(0);
24754 // Otherwise, this isn't something we can handle, reject it.
24758 const GlobalValue *GV = GA->getGlobal();
24759 // If we require an extra load to get this address, as in PIC mode, we
24760 // can't accept it.
24761 if (isGlobalStubReference(
24762 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24765 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24766 GA->getValueType(0), Offset);
24771 if (Result.getNode()) {
24772 Ops.push_back(Result);
24775 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24778 std::pair<unsigned, const TargetRegisterClass*>
24779 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24781 // First, see if this is a constraint that directly corresponds to an LLVM
24783 if (Constraint.size() == 1) {
24784 // GCC Constraint Letters
24785 switch (Constraint[0]) {
24787 // TODO: Slight differences here in allocation order and leaving
24788 // RIP in the class. Do they matter any more here than they do
24789 // in the normal allocation?
24790 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24791 if (Subtarget->is64Bit()) {
24792 if (VT == MVT::i32 || VT == MVT::f32)
24793 return std::make_pair(0U, &X86::GR32RegClass);
24794 if (VT == MVT::i16)
24795 return std::make_pair(0U, &X86::GR16RegClass);
24796 if (VT == MVT::i8 || VT == MVT::i1)
24797 return std::make_pair(0U, &X86::GR8RegClass);
24798 if (VT == MVT::i64 || VT == MVT::f64)
24799 return std::make_pair(0U, &X86::GR64RegClass);
24802 // 32-bit fallthrough
24803 case 'Q': // Q_REGS
24804 if (VT == MVT::i32 || VT == MVT::f32)
24805 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24806 if (VT == MVT::i16)
24807 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24808 if (VT == MVT::i8 || VT == MVT::i1)
24809 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24810 if (VT == MVT::i64)
24811 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24813 case 'r': // GENERAL_REGS
24814 case 'l': // INDEX_REGS
24815 if (VT == MVT::i8 || VT == MVT::i1)
24816 return std::make_pair(0U, &X86::GR8RegClass);
24817 if (VT == MVT::i16)
24818 return std::make_pair(0U, &X86::GR16RegClass);
24819 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24820 return std::make_pair(0U, &X86::GR32RegClass);
24821 return std::make_pair(0U, &X86::GR64RegClass);
24822 case 'R': // LEGACY_REGS
24823 if (VT == MVT::i8 || VT == MVT::i1)
24824 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24825 if (VT == MVT::i16)
24826 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24827 if (VT == MVT::i32 || !Subtarget->is64Bit())
24828 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24829 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24830 case 'f': // FP Stack registers.
24831 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24832 // value to the correct fpstack register class.
24833 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24834 return std::make_pair(0U, &X86::RFP32RegClass);
24835 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24836 return std::make_pair(0U, &X86::RFP64RegClass);
24837 return std::make_pair(0U, &X86::RFP80RegClass);
24838 case 'y': // MMX_REGS if MMX allowed.
24839 if (!Subtarget->hasMMX()) break;
24840 return std::make_pair(0U, &X86::VR64RegClass);
24841 case 'Y': // SSE_REGS if SSE2 allowed
24842 if (!Subtarget->hasSSE2()) break;
24844 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24845 if (!Subtarget->hasSSE1()) break;
24847 switch (VT.SimpleTy) {
24849 // Scalar SSE types.
24852 return std::make_pair(0U, &X86::FR32RegClass);
24855 return std::make_pair(0U, &X86::FR64RegClass);
24863 return std::make_pair(0U, &X86::VR128RegClass);
24871 return std::make_pair(0U, &X86::VR256RegClass);
24876 return std::make_pair(0U, &X86::VR512RegClass);
24882 // Use the default implementation in TargetLowering to convert the register
24883 // constraint into a member of a register class.
24884 std::pair<unsigned, const TargetRegisterClass*> Res;
24885 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24887 // Not found as a standard register?
24889 // Map st(0) -> st(7) -> ST0
24890 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24891 tolower(Constraint[1]) == 's' &&
24892 tolower(Constraint[2]) == 't' &&
24893 Constraint[3] == '(' &&
24894 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24895 Constraint[5] == ')' &&
24896 Constraint[6] == '}') {
24898 Res.first = X86::FP0+Constraint[4]-'0';
24899 Res.second = &X86::RFP80RegClass;
24903 // GCC allows "st(0)" to be called just plain "st".
24904 if (StringRef("{st}").equals_lower(Constraint)) {
24905 Res.first = X86::FP0;
24906 Res.second = &X86::RFP80RegClass;
24911 if (StringRef("{flags}").equals_lower(Constraint)) {
24912 Res.first = X86::EFLAGS;
24913 Res.second = &X86::CCRRegClass;
24917 // 'A' means EAX + EDX.
24918 if (Constraint == "A") {
24919 Res.first = X86::EAX;
24920 Res.second = &X86::GR32_ADRegClass;
24926 // Otherwise, check to see if this is a register class of the wrong value
24927 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24928 // turn into {ax},{dx}.
24929 if (Res.second->hasType(VT))
24930 return Res; // Correct type already, nothing to do.
24932 // All of the single-register GCC register classes map their values onto
24933 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24934 // really want an 8-bit or 32-bit register, map to the appropriate register
24935 // class and return the appropriate register.
24936 if (Res.second == &X86::GR16RegClass) {
24937 if (VT == MVT::i8 || VT == MVT::i1) {
24938 unsigned DestReg = 0;
24939 switch (Res.first) {
24941 case X86::AX: DestReg = X86::AL; break;
24942 case X86::DX: DestReg = X86::DL; break;
24943 case X86::CX: DestReg = X86::CL; break;
24944 case X86::BX: DestReg = X86::BL; break;
24947 Res.first = DestReg;
24948 Res.second = &X86::GR8RegClass;
24950 } else if (VT == MVT::i32 || VT == MVT::f32) {
24951 unsigned DestReg = 0;
24952 switch (Res.first) {
24954 case X86::AX: DestReg = X86::EAX; break;
24955 case X86::DX: DestReg = X86::EDX; break;
24956 case X86::CX: DestReg = X86::ECX; break;
24957 case X86::BX: DestReg = X86::EBX; break;
24958 case X86::SI: DestReg = X86::ESI; break;
24959 case X86::DI: DestReg = X86::EDI; break;
24960 case X86::BP: DestReg = X86::EBP; break;
24961 case X86::SP: DestReg = X86::ESP; break;
24964 Res.first = DestReg;
24965 Res.second = &X86::GR32RegClass;
24967 } else if (VT == MVT::i64 || VT == MVT::f64) {
24968 unsigned DestReg = 0;
24969 switch (Res.first) {
24971 case X86::AX: DestReg = X86::RAX; break;
24972 case X86::DX: DestReg = X86::RDX; break;
24973 case X86::CX: DestReg = X86::RCX; break;
24974 case X86::BX: DestReg = X86::RBX; break;
24975 case X86::SI: DestReg = X86::RSI; break;
24976 case X86::DI: DestReg = X86::RDI; break;
24977 case X86::BP: DestReg = X86::RBP; break;
24978 case X86::SP: DestReg = X86::RSP; break;
24981 Res.first = DestReg;
24982 Res.second = &X86::GR64RegClass;
24985 } else if (Res.second == &X86::FR32RegClass ||
24986 Res.second == &X86::FR64RegClass ||
24987 Res.second == &X86::VR128RegClass ||
24988 Res.second == &X86::VR256RegClass ||
24989 Res.second == &X86::FR32XRegClass ||
24990 Res.second == &X86::FR64XRegClass ||
24991 Res.second == &X86::VR128XRegClass ||
24992 Res.second == &X86::VR256XRegClass ||
24993 Res.second == &X86::VR512RegClass) {
24994 // Handle references to XMM physical registers that got mapped into the
24995 // wrong class. This can happen with constraints like {xmm0} where the
24996 // target independent register mapper will just pick the first match it can
24997 // find, ignoring the required type.
24999 if (VT == MVT::f32 || VT == MVT::i32)
25000 Res.second = &X86::FR32RegClass;
25001 else if (VT == MVT::f64 || VT == MVT::i64)
25002 Res.second = &X86::FR64RegClass;
25003 else if (X86::VR128RegClass.hasType(VT))
25004 Res.second = &X86::VR128RegClass;
25005 else if (X86::VR256RegClass.hasType(VT))
25006 Res.second = &X86::VR256RegClass;
25007 else if (X86::VR512RegClass.hasType(VT))
25008 Res.second = &X86::VR512RegClass;
25014 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25016 // Scaling factors are not free at all.
25017 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25018 // will take 2 allocations in the out of order engine instead of 1
25019 // for plain addressing mode, i.e. inst (reg1).
25021 // vaddps (%rsi,%drx), %ymm0, %ymm1
25022 // Requires two allocations (one for the load, one for the computation)
25024 // vaddps (%rsi), %ymm0, %ymm1
25025 // Requires just 1 allocation, i.e., freeing allocations for other operations
25026 // and having less micro operations to execute.
25028 // For some X86 architectures, this is even worse because for instance for
25029 // stores, the complex addressing mode forces the instruction to use the
25030 // "load" ports instead of the dedicated "store" port.
25031 // E.g., on Haswell:
25032 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25033 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25034 if (isLegalAddressingMode(AM, Ty))
25035 // Scale represents reg2 * scale, thus account for 1
25036 // as soon as we use a second register.
25037 return AM.Scale != 0;
25041 bool X86TargetLowering::isTargetFTOL() const {
25042 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();