1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
35 // Set up the TargetLowering object.
37 // X86 is weird, it always uses i8 for shift amounts and setcc results.
38 setShiftAmountType(MVT::i8);
39 setSetCCResultType(MVT::i8);
40 setSetCCResultContents(ZeroOrOneSetCCResult);
41 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
43 // Set up the register classes.
44 addRegisterClass(MVT::i8, X86::R8RegisterClass);
45 addRegisterClass(MVT::i16, X86::R16RegisterClass);
46 addRegisterClass(MVT::i32, X86::R32RegisterClass);
48 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
50 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
53 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
55 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
57 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
58 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
61 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
63 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
66 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
69 // Handle FP_TO_UINT by promoting the destination to a larger signed
71 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
73 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
76 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
78 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
80 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
82 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
84 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
85 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
86 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
87 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
88 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
89 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
90 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
91 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
92 setOperationAction(ISD::FREM , MVT::f64 , Expand);
93 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
94 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
95 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
96 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
97 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
98 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
99 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
100 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
101 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
102 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
104 setOperationAction(ISD::READIO , MVT::i1 , Expand);
105 setOperationAction(ISD::READIO , MVT::i8 , Expand);
106 setOperationAction(ISD::READIO , MVT::i16 , Expand);
107 setOperationAction(ISD::READIO , MVT::i32 , Expand);
108 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
109 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
110 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
111 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
113 // These should be promoted to a larger select which is supported.
114 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
115 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
116 // X86 wants to expand cmov itself.
118 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
119 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
122 // We don't have line number support yet.
123 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
126 // Set up the FP register classes.
127 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
128 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
130 // SSE has no load+extend ops
131 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
132 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
134 // SSE has no i16 to fp conversion, only i32
135 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
136 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
138 // Expand FP_TO_UINT into a select.
139 // FIXME: We would like to use a Custom expander here eventually to do
140 // the optimal thing for SSE vs. the default expansion in the legalizer.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
143 // We don't support sin/cos/sqrt/fmod
144 setOperationAction(ISD::FSIN , MVT::f64, Expand);
145 setOperationAction(ISD::FCOS , MVT::f64, Expand);
146 setOperationAction(ISD::FABS , MVT::f64, Expand);
147 setOperationAction(ISD::FNEG , MVT::f64, Expand);
148 setOperationAction(ISD::FREM , MVT::f64, Expand);
149 setOperationAction(ISD::FSIN , MVT::f32, Expand);
150 setOperationAction(ISD::FCOS , MVT::f32, Expand);
151 setOperationAction(ISD::FABS , MVT::f32, Expand);
152 setOperationAction(ISD::FNEG , MVT::f32, Expand);
153 setOperationAction(ISD::FREM , MVT::f32, Expand);
155 addLegalFPImmediate(+0.0); // xorps / xorpd
157 // Set up the FP register classes.
158 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
161 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
162 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
165 addLegalFPImmediate(+0.0); // FLD0
166 addLegalFPImmediate(+1.0); // FLD1
167 addLegalFPImmediate(-0.0); // FLD0/FCHS
168 addLegalFPImmediate(-1.0); // FLD1/FCHS
170 computeRegisterProperties();
172 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
173 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
174 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
175 allowUnalignedMemoryAccesses = true; // x86 supports it!
178 std::vector<SDOperand>
179 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
180 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
181 return LowerFastCCArguments(F, DAG);
182 return LowerCCCArguments(F, DAG);
185 std::pair<SDOperand, SDOperand>
186 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
187 bool isVarArg, unsigned CallingConv,
189 SDOperand Callee, ArgListTy &Args,
191 assert((!isVarArg || CallingConv == CallingConv::C) &&
192 "Only C takes varargs!");
193 if (CallingConv == CallingConv::Fast && EnableFastCC)
194 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
195 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
198 //===----------------------------------------------------------------------===//
199 // C Calling Convention implementation
200 //===----------------------------------------------------------------------===//
202 std::vector<SDOperand>
203 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
204 std::vector<SDOperand> ArgValues;
206 MachineFunction &MF = DAG.getMachineFunction();
207 MachineFrameInfo *MFI = MF.getFrameInfo();
209 // Add DAG nodes to load the arguments... On entry to a function on the X86,
210 // the stack frame looks like this:
212 // [ESP] -- return address
213 // [ESP + 4] -- first argument (leftmost lexically)
214 // [ESP + 8] -- second argument, if first argument is four bytes in size
217 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
218 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
219 MVT::ValueType ObjectVT = getValueType(I->getType());
220 unsigned ArgIncrement = 4;
223 default: assert(0 && "Unhandled argument type!");
225 case MVT::i8: ObjSize = 1; break;
226 case MVT::i16: ObjSize = 2; break;
227 case MVT::i32: ObjSize = 4; break;
228 case MVT::i64: ObjSize = ArgIncrement = 8; break;
229 case MVT::f32: ObjSize = 4; break;
230 case MVT::f64: ObjSize = ArgIncrement = 8; break;
232 // Create the frame index object for this incoming parameter...
233 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
235 // Create the SelectionDAG nodes corresponding to a load from this parameter
236 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
238 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
242 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
243 DAG.getSrcValue(NULL));
245 if (MVT::isInteger(ObjectVT))
246 ArgValue = DAG.getConstant(0, ObjectVT);
248 ArgValue = DAG.getConstantFP(0, ObjectVT);
250 ArgValues.push_back(ArgValue);
252 ArgOffset += ArgIncrement; // Move on to the next argument...
255 // If the function takes variable number of arguments, make a frame index for
256 // the start of the first vararg value... for expansion of llvm.va_start.
258 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
259 ReturnAddrIndex = 0; // No return address slot generated yet.
260 BytesToPopOnReturn = 0; // Callee pops nothing.
261 BytesCallerReserves = ArgOffset;
263 // Finally, inform the code generator which regs we return values in.
264 switch (getValueType(F.getReturnType())) {
265 default: assert(0 && "Unknown type!");
266 case MVT::isVoid: break;
271 MF.addLiveOut(X86::EAX);
274 MF.addLiveOut(X86::EAX);
275 MF.addLiveOut(X86::EDX);
279 MF.addLiveOut(X86::ST0);
285 std::pair<SDOperand, SDOperand>
286 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
287 bool isVarArg, bool isTailCall,
288 SDOperand Callee, ArgListTy &Args,
290 // Count how many bytes are to be pushed on the stack.
291 unsigned NumBytes = 0;
295 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
296 DAG.getConstant(0, getPointerTy()));
298 for (unsigned i = 0, e = Args.size(); i != e; ++i)
299 switch (getValueType(Args[i].second)) {
300 default: assert(0 && "Unknown value type!");
314 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
315 DAG.getConstant(NumBytes, getPointerTy()));
317 // Arguments go on the stack in reverse order, as specified by the ABI.
318 unsigned ArgOffset = 0;
319 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
321 std::vector<SDOperand> Stores;
323 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
324 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
325 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
327 switch (getValueType(Args[i].second)) {
328 default: assert(0 && "Unexpected ValueType for argument!");
332 // Promote the integer to 32 bits. If the input type is signed use a
333 // sign extend, otherwise use a zero extend.
334 if (Args[i].second->isSigned())
335 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
337 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
342 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
343 Args[i].first, PtrOff,
344 DAG.getSrcValue(NULL)));
349 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
350 Args[i].first, PtrOff,
351 DAG.getSrcValue(NULL)));
356 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
359 std::vector<MVT::ValueType> RetVals;
360 MVT::ValueType RetTyVT = getValueType(RetTy);
361 RetVals.push_back(MVT::Other);
363 // The result values produced have to be legal. Promote the result.
365 case MVT::isVoid: break;
367 RetVals.push_back(RetTyVT);
372 RetVals.push_back(MVT::i32);
376 RetVals.push_back(MVT::f32);
378 RetVals.push_back(MVT::f64);
381 RetVals.push_back(MVT::i32);
382 RetVals.push_back(MVT::i32);
385 std::vector<SDOperand> Ops;
386 Ops.push_back(Chain);
387 Ops.push_back(Callee);
388 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
389 Ops.push_back(DAG.getConstant(0, getPointerTy()));
390 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
392 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
396 case MVT::isVoid: break;
398 ResultVal = TheCall.getValue(1);
403 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
406 // FIXME: we would really like to remember that this FP_ROUND operation is
407 // okay to eliminate if we allow excess FP precision.
408 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
411 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
412 TheCall.getValue(2));
416 return std::make_pair(ResultVal, Chain);
420 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
421 Value *VAListV, SelectionDAG &DAG) {
422 // vastart just stores the address of the VarArgsFrameIndex slot.
423 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
424 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
425 DAG.getSrcValue(VAListV));
429 std::pair<SDOperand,SDOperand>
430 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
431 Value *VAListV, const Type *ArgTy,
433 MVT::ValueType ArgVT = getValueType(ArgTy);
434 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
435 VAListP, DAG.getSrcValue(VAListV));
436 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
437 DAG.getSrcValue(NULL));
439 if (ArgVT == MVT::i32)
442 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
443 "Other types should have been promoted for varargs!");
446 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
447 DAG.getConstant(Amt, Val.getValueType()));
448 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
449 Val, VAListP, DAG.getSrcValue(VAListV));
450 return std::make_pair(Result, Chain);
453 //===----------------------------------------------------------------------===//
454 // Fast Calling Convention implementation
455 //===----------------------------------------------------------------------===//
457 // The X86 'fast' calling convention passes up to two integer arguments in
458 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
459 // and requires that the callee pop its arguments off the stack (allowing proper
460 // tail calls), and has the same return value conventions as C calling convs.
462 // This calling convention always arranges for the callee pop value to be 8n+4
463 // bytes, which is needed for tail recursion elimination and stack alignment
466 // Note that this can be enhanced in the future to pass fp vals in registers
467 // (when we have a global fp allocator) and do other tricks.
470 /// AddLiveIn - This helper function adds the specified physical register to the
471 /// MachineFunction as a live in value. It also creates a corresponding virtual
473 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
474 TargetRegisterClass *RC) {
475 assert(RC->contains(PReg) && "Not the correct regclass!");
476 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
477 MF.addLiveIn(PReg, VReg);
482 std::vector<SDOperand>
483 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
484 std::vector<SDOperand> ArgValues;
486 MachineFunction &MF = DAG.getMachineFunction();
487 MachineFrameInfo *MFI = MF.getFrameInfo();
489 // Add DAG nodes to load the arguments... On entry to a function the stack
490 // frame looks like this:
492 // [ESP] -- return address
493 // [ESP + 4] -- first nonreg argument (leftmost lexically)
494 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
496 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
498 // Keep track of the number of integer regs passed so far. This can be either
499 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
501 unsigned NumIntRegs = 0;
503 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
504 MVT::ValueType ObjectVT = getValueType(I->getType());
505 unsigned ArgIncrement = 4;
506 unsigned ObjSize = 0;
510 default: assert(0 && "Unhandled argument type!");
513 if (NumIntRegs < 2) {
514 if (!I->use_empty()) {
515 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
516 X86::R8RegisterClass);
517 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
518 DAG.setRoot(ArgValue.getValue(1));
527 if (NumIntRegs < 2) {
528 if (!I->use_empty()) {
529 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
530 X86::R16RegisterClass);
531 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
532 DAG.setRoot(ArgValue.getValue(1));
540 if (NumIntRegs < 2) {
541 if (!I->use_empty()) {
542 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
543 X86::R32RegisterClass);
544 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
545 DAG.setRoot(ArgValue.getValue(1));
553 if (NumIntRegs == 0) {
554 if (!I->use_empty()) {
555 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
556 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
558 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
559 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
560 DAG.setRoot(Hi.getValue(1));
562 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
566 } else if (NumIntRegs == 1) {
567 if (!I->use_empty()) {
568 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
569 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
570 DAG.setRoot(Low.getValue(1));
572 // Load the high part from memory.
573 // Create the frame index object for this incoming parameter...
574 int FI = MFI->CreateFixedObject(4, ArgOffset);
575 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
576 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
577 DAG.getSrcValue(NULL));
578 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
584 ObjSize = ArgIncrement = 8;
586 case MVT::f32: ObjSize = 4; break;
587 case MVT::f64: ObjSize = ArgIncrement = 8; break;
590 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
592 if (ObjSize && !I->use_empty()) {
593 // Create the frame index object for this incoming parameter...
594 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
596 // Create the SelectionDAG nodes corresponding to a load from this
598 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
600 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
601 DAG.getSrcValue(NULL));
602 } else if (ArgValue.Val == 0) {
603 if (MVT::isInteger(ObjectVT))
604 ArgValue = DAG.getConstant(0, ObjectVT);
606 ArgValue = DAG.getConstantFP(0, ObjectVT);
608 ArgValues.push_back(ArgValue);
611 ArgOffset += ArgIncrement; // Move on to the next argument.
614 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
615 // arguments and the arguments after the retaddr has been pushed are aligned.
616 if ((ArgOffset & 7) == 0)
619 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
620 ReturnAddrIndex = 0; // No return address slot generated yet.
621 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
622 BytesCallerReserves = 0;
624 // Finally, inform the code generator which regs we return values in.
625 switch (getValueType(F.getReturnType())) {
626 default: assert(0 && "Unknown type!");
627 case MVT::isVoid: break;
632 MF.addLiveOut(X86::EAX);
635 MF.addLiveOut(X86::EAX);
636 MF.addLiveOut(X86::EDX);
640 MF.addLiveOut(X86::ST0);
646 std::pair<SDOperand, SDOperand>
647 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
648 bool isTailCall, SDOperand Callee,
649 ArgListTy &Args, SelectionDAG &DAG) {
650 // Count how many bytes are to be pushed on the stack.
651 unsigned NumBytes = 0;
653 // Keep track of the number of integer regs passed so far. This can be either
654 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
656 unsigned NumIntRegs = 0;
658 for (unsigned i = 0, e = Args.size(); i != e; ++i)
659 switch (getValueType(Args[i].second)) {
660 default: assert(0 && "Unknown value type!");
665 if (NumIntRegs < 2) {
674 if (NumIntRegs == 0) {
677 } else if (NumIntRegs == 1) {
689 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
690 // arguments and the arguments after the retaddr has been pushed are aligned.
691 if ((NumBytes & 7) == 0)
694 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
695 DAG.getConstant(NumBytes, getPointerTy()));
697 // Arguments go on the stack in reverse order, as specified by the ABI.
698 unsigned ArgOffset = 0;
699 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
702 std::vector<SDOperand> Stores;
703 std::vector<SDOperand> RegValuesToPass;
704 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
705 switch (getValueType(Args[i].second)) {
706 default: assert(0 && "Unexpected ValueType for argument!");
711 if (NumIntRegs < 2) {
712 RegValuesToPass.push_back(Args[i].first);
718 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
719 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
720 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
721 Args[i].first, PtrOff,
722 DAG.getSrcValue(NULL)));
727 if (NumIntRegs < 2) { // Can pass part of it in regs?
728 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
729 Args[i].first, DAG.getConstant(1, MVT::i32));
730 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
731 Args[i].first, DAG.getConstant(0, MVT::i32));
732 RegValuesToPass.push_back(Lo);
734 if (NumIntRegs < 2) { // Pass both parts in regs?
735 RegValuesToPass.push_back(Hi);
738 // Pass the high part in memory.
739 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
740 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
741 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
742 Hi, PtrOff, DAG.getSrcValue(NULL)));
749 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
750 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
751 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
752 Args[i].first, PtrOff,
753 DAG.getSrcValue(NULL)));
759 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
761 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
762 // arguments and the arguments after the retaddr has been pushed are aligned.
763 if ((ArgOffset & 7) == 0)
766 std::vector<MVT::ValueType> RetVals;
767 MVT::ValueType RetTyVT = getValueType(RetTy);
769 RetVals.push_back(MVT::Other);
771 // The result values produced have to be legal. Promote the result.
773 case MVT::isVoid: break;
775 RetVals.push_back(RetTyVT);
780 RetVals.push_back(MVT::i32);
784 RetVals.push_back(MVT::f32);
786 RetVals.push_back(MVT::f64);
789 RetVals.push_back(MVT::i32);
790 RetVals.push_back(MVT::i32);
794 std::vector<SDOperand> Ops;
795 Ops.push_back(Chain);
796 Ops.push_back(Callee);
797 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
798 // Callee pops all arg values on the stack.
799 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
801 // Pass register arguments as needed.
802 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
804 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
806 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
810 case MVT::isVoid: break;
812 ResultVal = TheCall.getValue(1);
817 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
820 // FIXME: we would really like to remember that this FP_ROUND operation is
821 // okay to eliminate if we allow excess FP precision.
822 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
825 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
826 TheCall.getValue(2));
830 return std::make_pair(ResultVal, Chain);
833 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
834 if (ReturnAddrIndex == 0) {
835 // Set up a frame object for the return address.
836 MachineFunction &MF = DAG.getMachineFunction();
837 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
840 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
845 std::pair<SDOperand, SDOperand> X86TargetLowering::
846 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
849 if (Depth) // Depths > 0 not supported yet!
850 Result = DAG.getConstant(0, getPointerTy());
852 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
854 // Just load the return address
855 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
856 DAG.getSrcValue(NULL));
858 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
859 DAG.getConstant(4, MVT::i32));
861 return std::make_pair(Result, Chain);
864 //===----------------------------------------------------------------------===//
865 // X86 Custom Lowering Hooks
866 //===----------------------------------------------------------------------===//
868 /// LowerOperation - Provide custom lowering hooks for some operations.
870 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
871 switch (Op.getOpcode()) {
872 default: assert(0 && "Should not custom lower this!");
873 case ISD::SINT_TO_FP: {
874 assert(Op.getValueType() == MVT::f64 &&
875 Op.getOperand(0).getValueType() == MVT::i64 &&
876 "Unknown SINT_TO_FP to lower!");
877 // We lower sint64->FP into a store to a temporary stack slot, followed by a
879 MachineFunction &MF = DAG.getMachineFunction();
880 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
881 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
882 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
883 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
884 std::vector<MVT::ValueType> RTs;
885 RTs.push_back(MVT::f64);
886 RTs.push_back(MVT::Other);
887 std::vector<SDOperand> Ops;
888 Ops.push_back(Store);
889 Ops.push_back(StackSlot);
890 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
892 case ISD::FP_TO_SINT: {
893 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
894 Op.getOperand(0).getValueType() == MVT::f64 &&
895 "Unknown FP_TO_SINT to lower!");
896 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
898 MachineFunction &MF = DAG.getMachineFunction();
899 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
900 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
901 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
904 switch (Op.getValueType()) {
905 default: assert(0 && "Invalid FP_TO_SINT to lower!");
906 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
907 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
908 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
911 // Build the FP_TO_INT*_IN_MEM
912 std::vector<SDOperand> Ops;
913 Ops.push_back(DAG.getEntryNode());
914 Ops.push_back(Op.getOperand(0));
915 Ops.push_back(StackSlot);
916 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
919 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
920 DAG.getSrcValue(NULL));
922 case ISD::READCYCLECOUNTER: {
923 std::vector<MVT::ValueType> Tys;
924 Tys.push_back(MVT::Other);
925 Tys.push_back(MVT::Flag);
926 std::vector<SDOperand> Ops;
927 Ops.push_back(Op.getOperand(0));
928 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
930 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
931 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
932 MVT::i32, Ops[0].getValue(2)));
933 Ops.push_back(Ops[1].getValue(1));
934 Tys[0] = Tys[1] = MVT::i32;
935 Tys.push_back(MVT::Other);
936 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
940 SDOperand Cond = Op.getOperand(0);
941 SDOperand True = Op.getOperand(1);
942 SDOperand False = Op.getOperand(2);
944 if (Cond.getOpcode() == ISD::SETCC) {
945 CC = Cond.getOperand(2);
946 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
947 Cond.getOperand(0), Cond.getOperand(1));
949 CC = DAG.getCondCode(ISD::SETEQ);
950 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
952 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
953 Op.getOperand(1), Op.getOperand(2), CC, Cond);