1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/ADT/VectorExtras.h"
25 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/SelectionDAG.h"
30 #include "llvm/CodeGen/SSARegMap.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
38 cl::desc("Enable fastcc on X86"));
40 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
41 : TargetLowering(TM) {
42 Subtarget = &TM.getSubtarget<X86Subtarget>();
43 X86ScalarSSE = Subtarget->hasSSE2();
45 // Set up the TargetLowering object.
47 // X86 is weird, it always uses i8 for shift amounts and setcc results.
48 setShiftAmountType(MVT::i8);
49 setSetCCResultType(MVT::i8);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
51 setSchedulingPreference(SchedulingForRegPressure);
52 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
53 setStackPointerRegisterToSaveRestore(X86::ESP);
55 if (!Subtarget->isTargetDarwin())
56 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
57 setUseUnderscoreSetJmpLongJmp(true);
59 // Add legal addressing mode scale values.
60 addLegalAddressScale(8);
61 addLegalAddressScale(4);
62 addLegalAddressScale(2);
63 // Enter the ones which require both scale + index last. These are more
65 addLegalAddressScale(9);
66 addLegalAddressScale(5);
67 addLegalAddressScale(3);
69 // Set up the register classes.
70 addRegisterClass(MVT::i8, X86::R8RegisterClass);
71 addRegisterClass(MVT::i16, X86::R16RegisterClass);
72 addRegisterClass(MVT::i32, X86::R32RegisterClass);
74 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
76 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
77 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
78 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
81 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
82 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
86 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
88 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
89 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
90 // SSE has no i16 to fp conversion, only i32
92 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
94 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
95 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
98 // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
100 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
101 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
103 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
105 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
106 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
109 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
111 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
112 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
115 // Handle FP_TO_UINT by promoting the destination to a larger signed
117 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
118 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
119 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
121 if (X86ScalarSSE && !Subtarget->hasSSE3())
122 // Expand FP_TO_UINT into a select.
123 // FIXME: We would like to use a Custom expander here eventually to do
124 // the optimal thing for SSE vs. the default expansion in the legalizer.
125 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
127 // With SSE3 we can use fisttpll to convert to a signed i64.
128 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
130 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
131 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
133 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
134 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
135 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
136 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
140 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
141 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
142 setOperationAction(ISD::FREM , MVT::f64 , Expand);
143 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
144 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
145 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
146 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
147 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
148 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
149 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
150 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
151 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
152 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
153 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
155 // These should be promoted to a larger select which is supported.
156 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
157 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
159 // X86 wants to expand cmov itself.
160 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
161 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
162 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
163 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
164 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
165 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
166 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
167 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
168 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
169 // X86 ret instruction may pop stack.
170 setOperationAction(ISD::RET , MVT::Other, Custom);
172 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
173 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
174 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
175 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
176 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
177 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
178 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
179 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
180 // X86 wants to expand memset / memcpy itself.
181 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
182 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
184 // We don't have line number support yet.
185 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
186 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
187 // FIXME - use subtarget debug flags
188 if (!Subtarget->isTargetDarwin())
189 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // Use the default implementation.
195 setOperationAction(ISD::VAARG , MVT::Other, Expand);
196 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
197 setOperationAction(ISD::VAEND , MVT::Other, Expand);
198 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
199 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
200 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
202 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
203 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
206 // Set up the FP register classes.
207 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
208 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
210 // Use ANDPD to simulate FABS.
211 setOperationAction(ISD::FABS , MVT::f64, Custom);
212 setOperationAction(ISD::FABS , MVT::f32, Custom);
214 // Use XORP to simulate FNEG.
215 setOperationAction(ISD::FNEG , MVT::f64, Custom);
216 setOperationAction(ISD::FNEG , MVT::f32, Custom);
218 // We don't support sin/cos/fmod
219 setOperationAction(ISD::FSIN , MVT::f64, Expand);
220 setOperationAction(ISD::FCOS , MVT::f64, Expand);
221 setOperationAction(ISD::FREM , MVT::f64, Expand);
222 setOperationAction(ISD::FSIN , MVT::f32, Expand);
223 setOperationAction(ISD::FCOS , MVT::f32, Expand);
224 setOperationAction(ISD::FREM , MVT::f32, Expand);
226 // Expand FP immediates into loads from the stack, except for the special
228 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
229 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
230 addLegalFPImmediate(+0.0); // xorps / xorpd
232 // Set up the FP register classes.
233 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
235 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
238 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
239 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
242 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
243 addLegalFPImmediate(+0.0); // FLD0
244 addLegalFPImmediate(+1.0); // FLD1
245 addLegalFPImmediate(-0.0); // FLD0/FCHS
246 addLegalFPImmediate(-1.0); // FLD1/FCHS
249 // First set operation action for all vector types to expand. Then we
250 // will selectively turn on ones that can be effectively codegen'd.
251 for (unsigned VT = (unsigned)MVT::Vector + 1;
252 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
253 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
254 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
255 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
256 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
257 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
258 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
262 if (Subtarget->hasMMX()) {
263 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
264 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
265 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
267 // FIXME: add MMX packed arithmetics
268 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
269 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
270 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
273 if (Subtarget->hasSSE1()) {
274 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
276 setOperationAction(ISD::AND, MVT::v4f32, Legal);
277 setOperationAction(ISD::OR, MVT::v4f32, Legal);
278 setOperationAction(ISD::XOR, MVT::v4f32, Legal);
279 setOperationAction(ISD::ADD, MVT::v4f32, Legal);
280 setOperationAction(ISD::SUB, MVT::v4f32, Legal);
281 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
282 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
283 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
284 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
285 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
286 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
289 if (Subtarget->hasSSE2()) {
290 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
291 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
292 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
293 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
294 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
296 setOperationAction(ISD::ADD, MVT::v2f64, Legal);
297 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
298 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
299 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
300 setOperationAction(ISD::SUB, MVT::v2f64, Legal);
301 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
302 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
303 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
304 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
305 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
307 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
308 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
309 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
310 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
311 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
312 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
314 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
315 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
316 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
317 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
318 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
320 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
322 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
323 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
327 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
328 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
329 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
330 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
331 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
332 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
333 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
334 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
335 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
336 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
337 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
338 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
341 // Custom lower v2i64 and v2f64 selects.
342 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
343 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
344 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
345 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
348 // We want to custom lower some of our intrinsics.
349 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
351 computeRegisterProperties();
353 // FIXME: These should be based on subtarget info. Plus, the values should
354 // be smaller when we are in optimizing for size mode.
355 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
356 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
357 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
358 allowUnalignedMemoryAccesses = true; // x86 supports it!
361 std::vector<SDOperand>
362 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
363 std::vector<SDOperand> Args = TargetLowering::LowerArguments(F, DAG);
366 FormalArgLocs.clear();
368 // This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be set
369 // before the rest of the function can be lowered.
370 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
371 PreprocessFastCCArguments(Args, F, DAG);
373 PreprocessCCCArguments(Args, F, DAG);
377 std::pair<SDOperand, SDOperand>
378 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
379 bool isVarArg, unsigned CallingConv,
381 SDOperand Callee, ArgListTy &Args,
383 assert((!isVarArg || CallingConv == CallingConv::C) &&
384 "Only C takes varargs!");
386 // If the callee is a GlobalAddress node (quite common, every direct call is)
387 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
388 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
389 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
390 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
391 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
393 if (CallingConv == CallingConv::Fast && EnableFastCC)
394 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
395 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
398 //===----------------------------------------------------------------------===//
399 // C Calling Convention implementation
400 //===----------------------------------------------------------------------===//
402 /// AddLiveIn - This helper function adds the specified physical register to the
403 /// MachineFunction as a live in value. It also creates a corresponding virtual
405 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
406 TargetRegisterClass *RC) {
407 assert(RC->contains(PReg) && "Not the correct regclass!");
408 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
409 MF.addLiveIn(PReg, VReg);
413 /// HowToPassCCCArgument - Returns how an formal argument of the specified type
414 /// should be passed. If it is through stack, returns the size of the stack
415 /// frame; if it is through XMM register, returns the number of XMM registers
418 HowToPassCCCArgument(MVT::ValueType ObjectVT, unsigned NumXMMRegs,
419 unsigned &ObjSize, unsigned &ObjXMMRegs) {
421 default: assert(0 && "Unhandled argument type!");
423 case MVT::i8: ObjSize = 1; break;
424 case MVT::i16: ObjSize = 2; break;
425 case MVT::i32: ObjSize = 4; break;
426 case MVT::i64: ObjSize = 8; break;
427 case MVT::f32: ObjSize = 4; break;
428 case MVT::f64: ObjSize = 8; break;
443 /// getFormalArgObjects - Returns itself if Op is a FORMAL_ARGUMENTS, otherwise
444 /// returns the FORMAL_ARGUMENTS node(s) that made up parts of the node.
445 static std::vector<SDOperand> getFormalArgObjects(SDOperand Op) {
446 unsigned Opc = Op.getOpcode();
447 std::vector<SDOperand> Objs;
448 if (Opc == ISD::TRUNCATE) {
449 Op = Op.getOperand(0);
450 assert(Op.getOpcode() == ISD::AssertSext ||
451 Op.getOpcode() == ISD::AssertZext);
452 Objs.push_back(Op.getOperand(0));
453 } else if (Opc == ISD::FP_ROUND || Opc == ISD::VBIT_CONVERT) {
454 Objs.push_back(Op.getOperand(0));
455 } else if (Opc == ISD::BUILD_PAIR) {
456 Objs.push_back(Op.getOperand(0));
457 Objs.push_back(Op.getOperand(1));
464 void X86TargetLowering::PreprocessCCCArguments(std::vector<SDOperand>Args,
465 Function &F, SelectionDAG &DAG) {
466 unsigned NumArgs = Args.size();
467 MachineFunction &MF = DAG.getMachineFunction();
468 MachineFrameInfo *MFI = MF.getFrameInfo();
470 // Add DAG nodes to load the arguments... On entry to a function on the X86,
471 // the stack frame looks like this:
473 // [ESP] -- return address
474 // [ESP + 4] -- first argument (leftmost lexically)
475 // [ESP + 8] -- second argument, if first argument is four bytes in size
478 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
479 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
480 unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
481 for (unsigned i = 0; i < NumArgs; ++i) {
482 SDOperand Op = Args[i];
483 std::vector<SDOperand> Objs = getFormalArgObjects(Op);
484 for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
487 MVT::ValueType ObjectVT = Obj.getValueType();
488 unsigned ArgIncrement = 4;
489 unsigned ObjSize = 0;
490 unsigned ObjXMMRegs = 0;
491 HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs);
493 ArgIncrement = ObjSize;
496 // Passed in a XMM register.
497 unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
498 X86::VR128RegisterClass);
499 std::pair<FALocInfo, FALocInfo> Loc =
500 std::make_pair(FALocInfo(FALocInfo::LiveInRegLoc, Reg, ObjectVT),
502 FormalArgLocs.push_back(Loc);
503 NumXMMRegs += ObjXMMRegs;
505 // Create the frame index object for this incoming parameter...
506 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
507 std::pair<FALocInfo, FALocInfo> Loc =
508 std::make_pair(FALocInfo(FALocInfo::StackFrameLoc, FI), FALocInfo());
509 FormalArgLocs.push_back(Loc);
510 ArgOffset += ArgIncrement; // Move on to the next argument...
515 // If the function takes variable number of arguments, make a frame index for
516 // the start of the first vararg value... for expansion of llvm.va_start.
518 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
519 ReturnAddrIndex = 0; // No return address slot generated yet.
520 BytesToPopOnReturn = 0; // Callee pops nothing.
521 BytesCallerReserves = ArgOffset;
524 void X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
525 unsigned NumArgs = Op.Val->getNumValues();
526 MachineFunction &MF = DAG.getMachineFunction();
527 MachineFrameInfo *MFI = MF.getFrameInfo();
529 for (unsigned i = 0; i < NumArgs; ++i) {
530 std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
532 if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
533 // Create the SelectionDAG nodes corresponding to a load from this parameter
534 unsigned FI = FormalArgLocs[i].first.Loc;
535 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
536 ArgValue = DAG.getLoad(Op.Val->getValueType(i),
537 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
539 // Must be a CopyFromReg
540 ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
543 FormalArgs.push_back(ArgValue);
547 std::pair<SDOperand, SDOperand>
548 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
549 bool isVarArg, bool isTailCall,
550 SDOperand Callee, ArgListTy &Args,
552 // Count how many bytes are to be pushed on the stack.
553 unsigned NumBytes = 0;
555 // Keep track of the number of XMM regs passed so far.
556 unsigned NumXMMRegs = 0;
557 unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
559 std::vector<SDOperand> RegValuesToPass;
562 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy()));
564 for (unsigned i = 0, e = Args.size(); i != e; ++i)
565 switch (getValueType(Args[i].second)) {
566 default: assert(0 && "Unknown value type!");
586 Chain = DAG.getCALLSEQ_START(Chain,
587 DAG.getConstant(NumBytes, getPointerTy()));
589 // Arguments go on the stack in reverse order, as specified by the ABI.
590 unsigned ArgOffset = 0;
592 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
593 std::vector<SDOperand> Stores;
594 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
595 switch (getValueType(Args[i].second)) {
596 default: assert(0 && "Unexpected ValueType for argument!");
600 // Promote the integer to 32 bits. If the input type is signed use a
601 // sign extend, otherwise use a zero extend.
602 if (Args[i].second->isSigned())
603 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
605 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
610 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
611 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
612 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
613 Args[i].first, PtrOff,
614 DAG.getSrcValue(NULL)));
620 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
621 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
622 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
623 Args[i].first, PtrOff,
624 DAG.getSrcValue(NULL)));
629 if (NumXMMRegs < 3) {
630 RegValuesToPass.push_back(Args[i].first);
633 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
634 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
635 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
636 Args[i].first, PtrOff,
637 DAG.getSrcValue(NULL)));
643 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
646 std::vector<MVT::ValueType> RetVals;
647 MVT::ValueType RetTyVT = getValueType(RetTy);
648 RetVals.push_back(MVT::Other);
650 // The result values produced have to be legal. Promote the result.
652 case MVT::isVoid: break;
654 RetVals.push_back(RetTyVT);
659 RetVals.push_back(MVT::i32);
663 RetVals.push_back(MVT::f32);
665 RetVals.push_back(MVT::f64);
668 RetVals.push_back(MVT::i32);
669 RetVals.push_back(MVT::i32);
673 // Build a sequence of copy-to-reg nodes chained together with token chain
674 // and flag operands which copy the outgoing args into registers.
676 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
677 unsigned CCReg = XMMArgRegs[i];
678 SDOperand RegToPass = RegValuesToPass[i];
679 assert(RegToPass.getValueType() == MVT::Vector);
680 unsigned NumElems = cast<ConstantSDNode>(*(RegToPass.Val->op_end()-2))->getValue();
681 MVT::ValueType EVT = cast<VTSDNode>(*(RegToPass.Val->op_end()-1))->getVT();
682 MVT::ValueType PVT = getVectorType(EVT, NumElems);
683 SDOperand CCRegNode = DAG.getRegister(CCReg, PVT);
684 RegToPass = DAG.getNode(ISD::VBIT_CONVERT, PVT, RegToPass);
685 Chain = DAG.getCopyToReg(Chain, CCRegNode, RegToPass, InFlag);
686 InFlag = Chain.getValue(1);
689 std::vector<MVT::ValueType> NodeTys;
690 NodeTys.push_back(MVT::Other); // Returns a chain
691 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
692 std::vector<SDOperand> Ops;
693 Ops.push_back(Chain);
694 Ops.push_back(Callee);
696 Ops.push_back(InFlag);
698 // FIXME: Do not generate X86ISD::TAILCALL for now.
699 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
700 InFlag = Chain.getValue(1);
703 NodeTys.push_back(MVT::Other); // Returns a chain
704 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
706 Ops.push_back(Chain);
707 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
708 Ops.push_back(DAG.getConstant(0, getPointerTy()));
709 Ops.push_back(InFlag);
710 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
711 InFlag = Chain.getValue(1);
714 if (RetTyVT != MVT::isVoid) {
716 default: assert(0 && "Unknown value type to return!");
719 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
720 Chain = RetVal.getValue(1);
721 if (RetTyVT == MVT::i1)
722 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
725 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
726 Chain = RetVal.getValue(1);
729 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
730 Chain = RetVal.getValue(1);
733 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
734 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
736 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
737 Chain = Hi.getValue(1);
742 std::vector<MVT::ValueType> Tys;
743 Tys.push_back(MVT::f64);
744 Tys.push_back(MVT::Other);
745 Tys.push_back(MVT::Flag);
746 std::vector<SDOperand> Ops;
747 Ops.push_back(Chain);
748 Ops.push_back(InFlag);
749 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
750 Chain = RetVal.getValue(1);
751 InFlag = RetVal.getValue(2);
753 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
754 // shouldn't be necessary except that RFP cannot be live across
755 // multiple blocks. When stackifier is fixed, they can be uncoupled.
756 MachineFunction &MF = DAG.getMachineFunction();
757 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
758 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
760 Tys.push_back(MVT::Other);
762 Ops.push_back(Chain);
763 Ops.push_back(RetVal);
764 Ops.push_back(StackSlot);
765 Ops.push_back(DAG.getValueType(RetTyVT));
766 Ops.push_back(InFlag);
767 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
768 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
769 DAG.getSrcValue(NULL));
770 Chain = RetVal.getValue(1);
773 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
774 // FIXME: we would really like to remember that this FP_ROUND
775 // operation is okay to eliminate if we allow excess FP precision.
776 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
780 const PackedType *PTy = cast<PackedType>(RetTy);
783 unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
784 assert(NumRegs == 1 && "Unsupported type!");
785 RetVal = DAG.getCopyFromReg(Chain, X86::XMM0, EVT, InFlag);
786 Chain = RetVal.getValue(1);
792 return std::make_pair(RetVal, Chain);
795 //===----------------------------------------------------------------------===//
796 // Fast Calling Convention implementation
797 //===----------------------------------------------------------------------===//
799 // The X86 'fast' calling convention passes up to two integer arguments in
800 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
801 // and requires that the callee pop its arguments off the stack (allowing proper
802 // tail calls), and has the same return value conventions as C calling convs.
804 // This calling convention always arranges for the callee pop value to be 8n+4
805 // bytes, which is needed for tail recursion elimination and stack alignment
808 // Note that this can be enhanced in the future to pass fp vals in registers
809 // (when we have a global fp allocator) and do other tricks.
812 // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
813 // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
814 // EDX". Anything more is illegal.
816 // FIXME: The linscan register allocator currently has problem with
817 // coalescing. At the time of this writing, whenever it decides to coalesce
818 // a physreg with a virtreg, this increases the size of the physreg's live
819 // range, and the live range cannot ever be reduced. This causes problems if
820 // too many physregs are coaleced with virtregs, which can cause the register
821 // allocator to wedge itself.
823 // This code triggers this problem more often if we pass args in registers,
824 // so disable it until this is fixed.
826 // NOTE: this isn't marked const, so that GCC doesn't emit annoying warnings
827 // about code being dead.
829 static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0;
832 /// HowToPassFastCCArgument - Returns how an formal argument of the specified
833 /// type should be passed. If it is through stack, returns the size of the stack
834 /// frame; if it is through integer or XMM register, returns the number of
835 /// integer or XMM registers are needed.
837 HowToPassFastCCArgument(MVT::ValueType ObjectVT,
838 unsigned NumIntRegs, unsigned NumXMMRegs,
839 unsigned &ObjSize, unsigned &ObjIntRegs,
840 unsigned &ObjXMMRegs) {
845 default: assert(0 && "Unhandled argument type!");
848 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
854 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
860 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
866 if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
868 } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
894 X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand>Args,
895 Function &F, SelectionDAG &DAG) {
896 unsigned NumArgs = Args.size();
897 MachineFunction &MF = DAG.getMachineFunction();
898 MachineFrameInfo *MFI = MF.getFrameInfo();
900 // Add DAG nodes to load the arguments... On entry to a function the stack
901 // frame looks like this:
903 // [ESP] -- return address
904 // [ESP + 4] -- first nonreg argument (leftmost lexically)
905 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
907 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
909 // Keep track of the number of integer regs passed so far. This can be either
910 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
912 unsigned NumIntRegs = 0;
913 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
914 unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
916 for (unsigned i = 0; i < NumArgs; ++i) {
917 SDOperand Op = Args[i];
918 std::vector<SDOperand> Objs = getFormalArgObjects(Op);
919 for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
922 MVT::ValueType ObjectVT = Obj.getValueType();
923 unsigned ArgIncrement = 4;
924 unsigned ObjSize = 0;
925 unsigned ObjIntRegs = 0;
926 unsigned ObjXMMRegs = 0;
928 HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
929 ObjSize, ObjIntRegs, ObjXMMRegs);
931 ArgIncrement = ObjSize;
934 std::pair<FALocInfo,FALocInfo> Loc = std::make_pair(FALocInfo(),
938 default: assert(0 && "Unhandled argument type!");
941 Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
942 X86::R8RegisterClass);
943 Loc.first.Kind = FALocInfo::LiveInRegLoc;
945 Loc.first.Typ = MVT::i8;
948 Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
949 X86::R16RegisterClass);
950 Loc.first.Kind = FALocInfo::LiveInRegLoc;
952 Loc.first.Typ = MVT::i16;
955 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
956 X86::R32RegisterClass);
957 Loc.first.Kind = FALocInfo::LiveInRegLoc;
959 Loc.first.Typ = MVT::i32;
962 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
963 X86::R32RegisterClass);
964 Loc.first.Kind = FALocInfo::LiveInRegLoc;
966 Loc.first.Typ = MVT::i32;
967 if (ObjIntRegs == 2) {
968 Reg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
969 Loc.second.Kind = FALocInfo::LiveInRegLoc;
970 Loc.second.Loc = Reg;
971 Loc.second.Typ = MVT::i32;
980 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
981 Loc.first.Kind = FALocInfo::LiveInRegLoc;
983 Loc.first.Typ = ObjectVT;
986 NumIntRegs += ObjIntRegs;
987 NumXMMRegs += ObjXMMRegs;
990 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
991 if (ObjectVT == MVT::i64 && ObjIntRegs) {
992 Loc.second.Kind = FALocInfo::StackFrameLoc;
995 Loc.first.Kind = FALocInfo::StackFrameLoc;
998 ArgOffset += ArgIncrement; // Move on to the next argument.
1001 FormalArgLocs.push_back(Loc);
1005 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1006 // arguments and the arguments after the retaddr has been pushed are aligned.
1007 if ((ArgOffset & 7) == 0)
1010 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1011 ReturnAddrIndex = 0; // No return address slot generated yet.
1012 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
1013 BytesCallerReserves = 0;
1015 // Finally, inform the code generator which regs we return values in.
1016 switch (getValueType(F.getReturnType())) {
1017 default: assert(0 && "Unknown type!");
1018 case MVT::isVoid: break;
1023 MF.addLiveOut(X86::EAX);
1026 MF.addLiveOut(X86::EAX);
1027 MF.addLiveOut(X86::EDX);
1031 MF.addLiveOut(X86::ST0);
1034 const PackedType *PTy = cast<PackedType>(F.getReturnType());
1037 unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
1038 assert(NumRegs == 1 && "Unsupported type!");
1039 MF.addLiveOut(X86::XMM0);
1046 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
1047 unsigned NumArgs = Op.Val->getNumValues();
1048 MachineFunction &MF = DAG.getMachineFunction();
1049 MachineFrameInfo *MFI = MF.getFrameInfo();
1051 for (unsigned i = 0; i < NumArgs; ++i) {
1052 MVT::ValueType VT = Op.Val->getValueType(i);
1053 std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
1055 if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
1056 // Create the SelectionDAG nodes corresponding to a load from this parameter
1057 SDOperand FIN = DAG.getFrameIndex(Loc.first.Loc, MVT::i32);
1058 ArgValue = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
1059 DAG.getSrcValue(NULL));
1061 // Must be a CopyFromReg
1062 ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
1066 if (Loc.second.Kind != FALocInfo::None) {
1067 SDOperand ArgValue2;
1068 if (Loc.second.Kind == FALocInfo::StackFrameLoc) {
1069 // Create the SelectionDAG nodes corresponding to a load from this parameter
1070 SDOperand FIN = DAG.getFrameIndex(Loc.second.Loc, MVT::i32);
1071 ArgValue2 = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
1072 DAG.getSrcValue(NULL));
1074 // Must be a CopyFromReg
1075 ArgValue2 = DAG.getCopyFromReg(DAG.getEntryNode(),
1076 Loc.second.Loc, Loc.second.Typ);
1078 ArgValue = DAG.getNode(ISD::BUILD_PAIR, VT, ArgValue, ArgValue2);
1080 FormalArgs.push_back(ArgValue);
1084 std::pair<SDOperand, SDOperand>
1085 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
1086 bool isTailCall, SDOperand Callee,
1087 ArgListTy &Args, SelectionDAG &DAG) {
1088 // Count how many bytes are to be pushed on the stack.
1089 unsigned NumBytes = 0;
1091 // Keep track of the number of integer regs passed so far. This can be either
1092 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
1094 unsigned NumIntRegs = 0;
1096 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1097 switch (getValueType(Args[i].second)) {
1098 default: assert(0 && "Unknown value type!");
1103 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
1112 if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
1115 } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
1116 NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
1127 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1128 // arguments and the arguments after the retaddr has been pushed are aligned.
1129 if ((NumBytes & 7) == 0)
1132 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1134 // Arguments go on the stack in reverse order, as specified by the ABI.
1135 unsigned ArgOffset = 0;
1136 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
1138 std::vector<SDOperand> Stores;
1139 std::vector<SDOperand> RegValuesToPass;
1140 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1141 switch (getValueType(Args[i].second)) {
1142 default: assert(0 && "Unexpected ValueType for argument!");
1144 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
1149 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
1150 RegValuesToPass.push_back(Args[i].first);
1156 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1157 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1158 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1159 Args[i].first, PtrOff,
1160 DAG.getSrcValue(NULL)));
1165 // Can pass (at least) part of it in regs?
1166 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
1167 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1168 Args[i].first, DAG.getConstant(1, MVT::i32));
1169 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1170 Args[i].first, DAG.getConstant(0, MVT::i32));
1171 RegValuesToPass.push_back(Lo);
1174 // Pass both parts in regs?
1175 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
1176 RegValuesToPass.push_back(Hi);
1179 // Pass the high part in memory.
1180 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1181 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1182 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1183 Hi, PtrOff, DAG.getSrcValue(NULL)));
1190 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1191 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1192 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1193 Args[i].first, PtrOff,
1194 DAG.getSrcValue(NULL)));
1199 if (!Stores.empty())
1200 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
1202 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1203 // arguments and the arguments after the retaddr has been pushed are aligned.
1204 if ((ArgOffset & 7) == 0)
1207 std::vector<MVT::ValueType> RetVals;
1208 MVT::ValueType RetTyVT = getValueType(RetTy);
1210 RetVals.push_back(MVT::Other);
1212 // The result values produced have to be legal. Promote the result.
1214 case MVT::isVoid: break;
1216 RetVals.push_back(RetTyVT);
1221 RetVals.push_back(MVT::i32);
1225 RetVals.push_back(MVT::f32);
1227 RetVals.push_back(MVT::f64);
1230 RetVals.push_back(MVT::i32);
1231 RetVals.push_back(MVT::i32);
1235 // Build a sequence of copy-to-reg nodes chained together with token chain
1236 // and flag operands which copy the outgoing args into registers.
1238 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
1240 SDOperand RegToPass = RegValuesToPass[i];
1241 switch (RegToPass.getValueType()) {
1242 default: assert(0 && "Bad thing to pass in regs");
1244 CCReg = (i == 0) ? X86::AL : X86::DL;
1247 CCReg = (i == 0) ? X86::AX : X86::DX;
1250 CCReg = (i == 0) ? X86::EAX : X86::EDX;
1254 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
1255 InFlag = Chain.getValue(1);
1258 std::vector<MVT::ValueType> NodeTys;
1259 NodeTys.push_back(MVT::Other); // Returns a chain
1260 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1261 std::vector<SDOperand> Ops;
1262 Ops.push_back(Chain);
1263 Ops.push_back(Callee);
1265 Ops.push_back(InFlag);
1267 // FIXME: Do not generate X86ISD::TAILCALL for now.
1268 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, NodeTys, Ops);
1269 InFlag = Chain.getValue(1);
1272 NodeTys.push_back(MVT::Other); // Returns a chain
1273 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1275 Ops.push_back(Chain);
1276 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1277 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1278 Ops.push_back(InFlag);
1279 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
1280 InFlag = Chain.getValue(1);
1283 if (RetTyVT != MVT::isVoid) {
1285 default: assert(0 && "Unknown value type to return!");
1288 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1289 Chain = RetVal.getValue(1);
1290 if (RetTyVT == MVT::i1)
1291 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
1294 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1295 Chain = RetVal.getValue(1);
1298 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1299 Chain = RetVal.getValue(1);
1302 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1303 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1305 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1306 Chain = Hi.getValue(1);
1311 std::vector<MVT::ValueType> Tys;
1312 Tys.push_back(MVT::f64);
1313 Tys.push_back(MVT::Other);
1314 Tys.push_back(MVT::Flag);
1315 std::vector<SDOperand> Ops;
1316 Ops.push_back(Chain);
1317 Ops.push_back(InFlag);
1318 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1319 Chain = RetVal.getValue(1);
1320 InFlag = RetVal.getValue(2);
1322 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
1323 // shouldn't be necessary except that RFP cannot be live across
1324 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1325 MachineFunction &MF = DAG.getMachineFunction();
1326 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1327 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1329 Tys.push_back(MVT::Other);
1331 Ops.push_back(Chain);
1332 Ops.push_back(RetVal);
1333 Ops.push_back(StackSlot);
1334 Ops.push_back(DAG.getValueType(RetTyVT));
1335 Ops.push_back(InFlag);
1336 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1337 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1338 DAG.getSrcValue(NULL));
1339 Chain = RetVal.getValue(1);
1342 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1343 // FIXME: we would really like to remember that this FP_ROUND
1344 // operation is okay to eliminate if we allow excess FP precision.
1345 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1351 return std::make_pair(RetVal, Chain);
1354 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1355 if (ReturnAddrIndex == 0) {
1356 // Set up a frame object for the return address.
1357 MachineFunction &MF = DAG.getMachineFunction();
1358 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1361 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1366 std::pair<SDOperand, SDOperand> X86TargetLowering::
1367 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1368 SelectionDAG &DAG) {
1370 if (Depth) // Depths > 0 not supported yet!
1371 Result = DAG.getConstant(0, getPointerTy());
1373 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1374 if (!isFrameAddress)
1375 // Just load the return address
1376 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1377 DAG.getSrcValue(NULL));
1379 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1380 DAG.getConstant(4, MVT::i32));
1382 return std::make_pair(Result, Chain);
1385 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1386 /// which corresponds to the condition code.
1387 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1389 default: assert(0 && "Unknown X86 conditional code!");
1390 case X86ISD::COND_A: return X86::JA;
1391 case X86ISD::COND_AE: return X86::JAE;
1392 case X86ISD::COND_B: return X86::JB;
1393 case X86ISD::COND_BE: return X86::JBE;
1394 case X86ISD::COND_E: return X86::JE;
1395 case X86ISD::COND_G: return X86::JG;
1396 case X86ISD::COND_GE: return X86::JGE;
1397 case X86ISD::COND_L: return X86::JL;
1398 case X86ISD::COND_LE: return X86::JLE;
1399 case X86ISD::COND_NE: return X86::JNE;
1400 case X86ISD::COND_NO: return X86::JNO;
1401 case X86ISD::COND_NP: return X86::JNP;
1402 case X86ISD::COND_NS: return X86::JNS;
1403 case X86ISD::COND_O: return X86::JO;
1404 case X86ISD::COND_P: return X86::JP;
1405 case X86ISD::COND_S: return X86::JS;
1409 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1410 /// specific condition code. It returns a false if it cannot do a direct
1411 /// translation. X86CC is the translated CondCode. Flip is set to true if the
1412 /// the order of comparison operands should be flipped.
1413 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1414 unsigned &X86CC, bool &Flip) {
1416 X86CC = X86ISD::COND_INVALID;
1418 switch (SetCCOpcode) {
1420 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1421 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1422 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1423 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1424 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1425 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1426 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1427 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1428 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1429 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1432 // On a floating point condition, the flags are set as follows:
1434 // 0 | 0 | 0 | X > Y
1435 // 0 | 0 | 1 | X < Y
1436 // 1 | 0 | 0 | X == Y
1437 // 1 | 1 | 1 | unordered
1438 switch (SetCCOpcode) {
1441 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1442 case ISD::SETOLT: Flip = true; // Fallthrough
1444 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1445 case ISD::SETOLE: Flip = true; // Fallthrough
1447 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1448 case ISD::SETUGT: Flip = true; // Fallthrough
1450 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1451 case ISD::SETUGE: Flip = true; // Fallthrough
1453 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1455 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1456 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1457 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1461 return X86CC != X86ISD::COND_INVALID;
1464 static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
1466 return translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, Flip);
1469 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1470 /// code. Current x86 isa includes the following FP cmov instructions:
1471 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1472 static bool hasFPCMov(unsigned X86CC) {
1476 case X86ISD::COND_B:
1477 case X86ISD::COND_BE:
1478 case X86ISD::COND_E:
1479 case X86ISD::COND_P:
1480 case X86ISD::COND_A:
1481 case X86ISD::COND_AE:
1482 case X86ISD::COND_NE:
1483 case X86ISD::COND_NP:
1489 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1490 MachineBasicBlock *BB) {
1491 switch (MI->getOpcode()) {
1492 default: assert(false && "Unexpected instr type to insert");
1493 case X86::CMOV_FR32:
1494 case X86::CMOV_FR64:
1495 case X86::CMOV_V4F32:
1496 case X86::CMOV_V2F64:
1497 case X86::CMOV_V2I64: {
1498 // To "insert" a SELECT_CC instruction, we actually have to insert the
1499 // diamond control-flow pattern. The incoming instruction knows the
1500 // destination vreg to set, the condition code register to branch on, the
1501 // true/false values to select between, and a branch opcode to use.
1502 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1503 ilist<MachineBasicBlock>::iterator It = BB;
1509 // cmpTY ccX, r1, r2
1511 // fallthrough --> copy0MBB
1512 MachineBasicBlock *thisMBB = BB;
1513 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1514 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1515 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1516 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1517 MachineFunction *F = BB->getParent();
1518 F->getBasicBlockList().insert(It, copy0MBB);
1519 F->getBasicBlockList().insert(It, sinkMBB);
1520 // Update machine-CFG edges by first adding all successors of the current
1521 // block to the new block which will contain the Phi node for the select.
1522 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1523 e = BB->succ_end(); i != e; ++i)
1524 sinkMBB->addSuccessor(*i);
1525 // Next, remove all successors of the current block, and add the true
1526 // and fallthrough blocks as its successors.
1527 while(!BB->succ_empty())
1528 BB->removeSuccessor(BB->succ_begin());
1529 BB->addSuccessor(copy0MBB);
1530 BB->addSuccessor(sinkMBB);
1533 // %FalseValue = ...
1534 // # fallthrough to sinkMBB
1537 // Update machine-CFG edges
1538 BB->addSuccessor(sinkMBB);
1541 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1544 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1545 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1546 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1548 delete MI; // The pseudo instruction is gone now.
1552 case X86::FP_TO_INT16_IN_MEM:
1553 case X86::FP_TO_INT32_IN_MEM:
1554 case X86::FP_TO_INT64_IN_MEM: {
1555 // Change the floating point control register to use "round towards zero"
1556 // mode when truncating to an integer value.
1557 MachineFunction *F = BB->getParent();
1558 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1559 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1561 // Load the old value of the high byte of the control word...
1563 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1564 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1566 // Set the high part to be round to zero...
1567 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1569 // Reload the modified control word now...
1570 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1572 // Restore the memory image of control word to original value
1573 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1575 // Get the X86 opcode to use.
1577 switch (MI->getOpcode()) {
1578 default: assert(0 && "illegal opcode!");
1579 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1580 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1581 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1585 MachineOperand &Op = MI->getOperand(0);
1586 if (Op.isRegister()) {
1587 AM.BaseType = X86AddressMode::RegBase;
1588 AM.Base.Reg = Op.getReg();
1590 AM.BaseType = X86AddressMode::FrameIndexBase;
1591 AM.Base.FrameIndex = Op.getFrameIndex();
1593 Op = MI->getOperand(1);
1594 if (Op.isImmediate())
1595 AM.Scale = Op.getImmedValue();
1596 Op = MI->getOperand(2);
1597 if (Op.isImmediate())
1598 AM.IndexReg = Op.getImmedValue();
1599 Op = MI->getOperand(3);
1600 if (Op.isGlobalAddress()) {
1601 AM.GV = Op.getGlobal();
1603 AM.Disp = Op.getImmedValue();
1605 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1607 // Reload the original control word now.
1608 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1610 delete MI; // The pseudo instruction is gone now.
1617 //===----------------------------------------------------------------------===//
1618 // X86 Custom Lowering Hooks
1619 //===----------------------------------------------------------------------===//
1621 /// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra
1622 /// load. For Darwin, external and weak symbols are indirect, loading the value
1623 /// at address GV rather then the value of GV itself. This means that the
1624 /// GlobalAddress must be in the base or index register of the address, not the
1625 /// GV offset field.
1626 static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
1627 return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
1628 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
1631 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1632 /// true if Op is undef or if its value falls within the specified range (L, H].
1633 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1634 if (Op.getOpcode() == ISD::UNDEF)
1637 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1638 return (Val >= Low && Val < Hi);
1641 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1642 /// true if Op is undef or if its value equal to the specified value.
1643 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1644 if (Op.getOpcode() == ISD::UNDEF)
1646 return cast<ConstantSDNode>(Op)->getValue() == Val;
1649 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1650 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1651 bool X86::isPSHUFDMask(SDNode *N) {
1652 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1654 if (N->getNumOperands() != 4)
1657 // Check if the value doesn't reference the second vector.
1658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1659 SDOperand Arg = N->getOperand(i);
1660 if (Arg.getOpcode() == ISD::UNDEF) continue;
1661 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1662 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1669 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1670 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1671 bool X86::isPSHUFHWMask(SDNode *N) {
1672 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1674 if (N->getNumOperands() != 8)
1677 // Lower quadword copied in order.
1678 for (unsigned i = 0; i != 4; ++i) {
1679 SDOperand Arg = N->getOperand(i);
1680 if (Arg.getOpcode() == ISD::UNDEF) continue;
1681 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1682 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1686 // Upper quadword shuffled.
1687 for (unsigned i = 4; i != 8; ++i) {
1688 SDOperand Arg = N->getOperand(i);
1689 if (Arg.getOpcode() == ISD::UNDEF) continue;
1690 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1691 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1692 if (Val < 4 || Val > 7)
1699 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1700 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1701 bool X86::isPSHUFLWMask(SDNode *N) {
1702 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1704 if (N->getNumOperands() != 8)
1707 // Upper quadword copied in order.
1708 for (unsigned i = 4; i != 8; ++i)
1709 if (!isUndefOrEqual(N->getOperand(i), i))
1712 // Lower quadword shuffled.
1713 for (unsigned i = 0; i != 4; ++i)
1714 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1720 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1721 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1722 static bool isSHUFPMask(std::vector<SDOperand> &N) {
1723 unsigned NumElems = N.size();
1724 if (NumElems != 2 && NumElems != 4) return false;
1726 unsigned Half = NumElems / 2;
1727 for (unsigned i = 0; i < Half; ++i)
1728 if (!isUndefOrInRange(N[i], 0, NumElems))
1730 for (unsigned i = Half; i < NumElems; ++i)
1731 if (!isUndefOrInRange(N[i], NumElems, NumElems*2))
1737 bool X86::isSHUFPMask(SDNode *N) {
1738 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1739 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1740 return ::isSHUFPMask(Ops);
1743 /// isCommutedSHUFP - Returns true if the shuffle mask is except
1744 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1745 /// half elements to come from vector 1 (which would equal the dest.) and
1746 /// the upper half to come from vector 2.
1747 static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) {
1748 unsigned NumElems = Ops.size();
1749 if (NumElems != 2 && NumElems != 4) return false;
1751 unsigned Half = NumElems / 2;
1752 for (unsigned i = 0; i < Half; ++i)
1753 if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2))
1755 for (unsigned i = Half; i < NumElems; ++i)
1756 if (!isUndefOrInRange(Ops[i], 0, NumElems))
1761 static bool isCommutedSHUFP(SDNode *N) {
1762 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1763 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1764 return isCommutedSHUFP(Ops);
1767 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1768 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1769 bool X86::isMOVHLPSMask(SDNode *N) {
1770 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1772 if (N->getNumOperands() != 4)
1775 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1776 return isUndefOrEqual(N->getOperand(0), 6) &&
1777 isUndefOrEqual(N->getOperand(1), 7) &&
1778 isUndefOrEqual(N->getOperand(2), 2) &&
1779 isUndefOrEqual(N->getOperand(3), 3);
1782 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1783 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1784 bool X86::isMOVLPMask(SDNode *N) {
1785 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1787 unsigned NumElems = N->getNumOperands();
1788 if (NumElems != 2 && NumElems != 4)
1791 for (unsigned i = 0; i < NumElems/2; ++i)
1792 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1795 for (unsigned i = NumElems/2; i < NumElems; ++i)
1796 if (!isUndefOrEqual(N->getOperand(i), i))
1802 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1803 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1805 bool X86::isMOVHPMask(SDNode *N) {
1806 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1808 unsigned NumElems = N->getNumOperands();
1809 if (NumElems != 2 && NumElems != 4)
1812 for (unsigned i = 0; i < NumElems/2; ++i)
1813 if (!isUndefOrEqual(N->getOperand(i), i))
1816 for (unsigned i = 0; i < NumElems/2; ++i) {
1817 SDOperand Arg = N->getOperand(i + NumElems/2);
1818 if (!isUndefOrEqual(Arg, i + NumElems))
1825 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1826 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1827 bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
1828 unsigned NumElems = N.size();
1829 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1832 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1833 SDOperand BitI = N[i];
1834 SDOperand BitI1 = N[i+1];
1835 if (!isUndefOrEqual(BitI, j))
1838 if (isUndefOrEqual(BitI1, NumElems))
1841 if (!isUndefOrEqual(BitI1, j + NumElems))
1849 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1850 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1851 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1852 return ::isUNPCKLMask(Ops, V2IsSplat);
1855 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1856 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1857 bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
1858 unsigned NumElems = N.size();
1859 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1862 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1863 SDOperand BitI = N[i];
1864 SDOperand BitI1 = N[i+1];
1865 if (!isUndefOrEqual(BitI, j + NumElems/2))
1868 if (isUndefOrEqual(BitI1, NumElems))
1871 if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems))
1879 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1880 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1881 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1882 return ::isUNPCKHMask(Ops, V2IsSplat);
1885 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1886 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1888 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1889 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1891 unsigned NumElems = N->getNumOperands();
1892 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
1895 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1896 SDOperand BitI = N->getOperand(i);
1897 SDOperand BitI1 = N->getOperand(i+1);
1899 if (!isUndefOrEqual(BitI, j))
1901 if (!isUndefOrEqual(BitI1, j))
1908 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1909 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1910 /// MOVSD, and MOVD, i.e. setting the lowest element.
1911 static bool isMOVLMask(std::vector<SDOperand> &N) {
1912 unsigned NumElems = N.size();
1913 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1916 if (!isUndefOrEqual(N[0], NumElems))
1919 for (unsigned i = 1; i < NumElems; ++i) {
1920 SDOperand Arg = N[i];
1921 if (!isUndefOrEqual(Arg, i))
1928 bool X86::isMOVLMask(SDNode *N) {
1929 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1930 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1931 return ::isMOVLMask(Ops);
1934 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1935 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1936 /// element of vector 2 and the other elements to come from vector 1 in order.
1937 static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
1938 unsigned NumElems = Ops.size();
1939 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1942 if (!isUndefOrEqual(Ops[0], 0))
1945 for (unsigned i = 1; i < NumElems; ++i) {
1946 SDOperand Arg = Ops[i];
1948 if (!isUndefOrEqual(Arg, NumElems))
1951 if (!isUndefOrEqual(Arg, i+NumElems))
1959 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false) {
1960 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1961 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
1962 return isCommutedMOVL(Ops, V2IsSplat);
1965 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1966 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1967 bool X86::isMOVSHDUPMask(SDNode *N) {
1968 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1970 if (N->getNumOperands() != 4)
1973 // Expect 1, 1, 3, 3
1974 for (unsigned i = 0; i < 2; ++i) {
1975 SDOperand Arg = N->getOperand(i);
1976 if (Arg.getOpcode() == ISD::UNDEF) continue;
1977 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1978 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1979 if (Val != 1) return false;
1983 for (unsigned i = 2; i < 4; ++i) {
1984 SDOperand Arg = N->getOperand(i);
1985 if (Arg.getOpcode() == ISD::UNDEF) continue;
1986 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1987 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1988 if (Val != 3) return false;
1992 // Don't use movshdup if it can be done with a shufps.
1996 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1997 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1998 bool X86::isMOVSLDUPMask(SDNode *N) {
1999 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2001 if (N->getNumOperands() != 4)
2004 // Expect 0, 0, 2, 2
2005 for (unsigned i = 0; i < 2; ++i) {
2006 SDOperand Arg = N->getOperand(i);
2007 if (Arg.getOpcode() == ISD::UNDEF) continue;
2008 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2009 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2010 if (Val != 0) return false;
2014 for (unsigned i = 2; i < 4; ++i) {
2015 SDOperand Arg = N->getOperand(i);
2016 if (Arg.getOpcode() == ISD::UNDEF) continue;
2017 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2018 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2019 if (Val != 2) return false;
2023 // Don't use movshdup if it can be done with a shufps.
2027 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2028 /// a splat of a single element.
2029 static bool isSplatMask(SDNode *N) {
2030 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2032 // This is a splat operation if each element of the permute is the same, and
2033 // if the value doesn't reference the second vector.
2034 unsigned NumElems = N->getNumOperands();
2035 SDOperand ElementBase;
2037 for (; i != NumElems; ++i) {
2038 SDOperand Elt = N->getOperand(i);
2039 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) {
2045 if (!ElementBase.Val)
2048 for (; i != NumElems; ++i) {
2049 SDOperand Arg = N->getOperand(i);
2050 if (Arg.getOpcode() == ISD::UNDEF) continue;
2051 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2052 if (Arg != ElementBase) return false;
2055 // Make sure it is a splat of the first vector operand.
2056 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2059 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2060 /// a splat of a single element and it's a 2 or 4 element mask.
2061 bool X86::isSplatMask(SDNode *N) {
2062 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2064 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2065 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2067 return ::isSplatMask(N);
2070 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2071 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2073 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2074 unsigned NumOperands = N->getNumOperands();
2075 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2077 for (unsigned i = 0; i < NumOperands; ++i) {
2079 SDOperand Arg = N->getOperand(NumOperands-i-1);
2080 if (Arg.getOpcode() != ISD::UNDEF)
2081 Val = cast<ConstantSDNode>(Arg)->getValue();
2082 if (Val >= NumOperands) Val -= NumOperands;
2084 if (i != NumOperands - 1)
2091 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2092 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2094 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2096 // 8 nodes, but we only care about the last 4.
2097 for (unsigned i = 7; i >= 4; --i) {
2099 SDOperand Arg = N->getOperand(i);
2100 if (Arg.getOpcode() != ISD::UNDEF)
2101 Val = cast<ConstantSDNode>(Arg)->getValue();
2110 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2111 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2113 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2115 // 8 nodes, but we only care about the first 4.
2116 for (int i = 3; i >= 0; --i) {
2118 SDOperand Arg = N->getOperand(i);
2119 if (Arg.getOpcode() != ISD::UNDEF)
2120 Val = cast<ConstantSDNode>(Arg)->getValue();
2129 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2130 /// specifies a 8 element shuffle that can be broken into a pair of
2131 /// PSHUFHW and PSHUFLW.
2132 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2133 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2135 if (N->getNumOperands() != 8)
2138 // Lower quadword shuffled.
2139 for (unsigned i = 0; i != 4; ++i) {
2140 SDOperand Arg = N->getOperand(i);
2141 if (Arg.getOpcode() == ISD::UNDEF) continue;
2142 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2143 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2148 // Upper quadword shuffled.
2149 for (unsigned i = 4; i != 8; ++i) {
2150 SDOperand Arg = N->getOperand(i);
2151 if (Arg.getOpcode() == ISD::UNDEF) continue;
2152 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2153 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2154 if (Val < 4 || Val > 7)
2161 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2162 /// values in ther permute mask.
2163 static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) {
2164 SDOperand V1 = Op.getOperand(0);
2165 SDOperand V2 = Op.getOperand(1);
2166 SDOperand Mask = Op.getOperand(2);
2167 MVT::ValueType VT = Op.getValueType();
2168 MVT::ValueType MaskVT = Mask.getValueType();
2169 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2170 unsigned NumElems = Mask.getNumOperands();
2171 std::vector<SDOperand> MaskVec;
2173 for (unsigned i = 0; i != NumElems; ++i) {
2174 SDOperand Arg = Mask.getOperand(i);
2175 if (Arg.getOpcode() == ISD::UNDEF) {
2176 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2179 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2180 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2182 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2184 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2187 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2188 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
2191 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2192 /// match movhlps. The lower half elements should come from upper half of
2193 /// V1 (and in order), and the upper half elements should come from the upper
2194 /// half of V2 (and in order).
2195 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2196 unsigned NumElems = Mask->getNumOperands();
2199 for (unsigned i = 0, e = 2; i != e; ++i)
2200 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2202 for (unsigned i = 2; i != 4; ++i)
2203 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2208 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2209 /// is promoted to a vector.
2210 static inline bool isScalarLoadToVector(SDNode *N) {
2211 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2212 N = N->getOperand(0).Val;
2213 return (N->getOpcode() == ISD::LOAD);
2218 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2219 /// match movlp{s|d}. The lower half elements should come from lower half of
2220 /// V1 (and in order), and the upper half elements should come from the upper
2221 /// half of V2 (and in order). And since V1 will become the source of the
2222 /// MOVLP, it must be either a vector load or a scalar load to vector.
2223 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) {
2224 if (V1->getOpcode() != ISD::LOAD && !isScalarLoadToVector(V1))
2227 unsigned NumElems = Mask->getNumOperands();
2228 if (NumElems != 2 && NumElems != 4)
2230 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2231 if (!isUndefOrEqual(Mask->getOperand(i), i))
2233 for (unsigned i = NumElems/2; i != NumElems; ++i)
2234 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2239 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2241 static bool isSplatVector(SDNode *N) {
2242 if (N->getOpcode() != ISD::BUILD_VECTOR)
2245 SDOperand SplatValue = N->getOperand(0);
2246 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2247 if (N->getOperand(i) != SplatValue)
2252 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2253 /// that point to V2 points to its first element.
2254 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2255 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2257 bool Changed = false;
2258 std::vector<SDOperand> MaskVec;
2259 unsigned NumElems = Mask.getNumOperands();
2260 for (unsigned i = 0; i != NumElems; ++i) {
2261 SDOperand Arg = Mask.getOperand(i);
2262 if (Arg.getOpcode() != ISD::UNDEF) {
2263 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2264 if (Val > NumElems) {
2265 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2269 MaskVec.push_back(Arg);
2273 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
2277 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2278 /// operation of specified width.
2279 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2280 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2281 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2283 std::vector<SDOperand> MaskVec;
2284 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2285 for (unsigned i = 1; i != NumElems; ++i)
2286 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2287 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2290 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2291 /// of specified width.
2292 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2293 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2294 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2295 std::vector<SDOperand> MaskVec;
2296 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2297 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2298 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2300 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2303 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2304 /// of specified width.
2305 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2306 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2307 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2308 unsigned Half = NumElems/2;
2309 std::vector<SDOperand> MaskVec;
2310 for (unsigned i = 0; i != Half; ++i) {
2311 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2312 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2314 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2317 /// getZeroVector - Returns a vector of specified type with all zero elements.
2319 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2320 assert(MVT::isVector(VT) && "Expected a vector type");
2321 unsigned NumElems = getVectorNumElements(VT);
2322 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2323 bool isFP = MVT::isFloatingPoint(EVT);
2324 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2325 std::vector<SDOperand> ZeroVec(NumElems, Zero);
2326 return DAG.getNode(ISD::BUILD_VECTOR, VT, ZeroVec);
2329 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2331 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2332 SDOperand V1 = Op.getOperand(0);
2333 SDOperand Mask = Op.getOperand(2);
2334 MVT::ValueType VT = Op.getValueType();
2335 unsigned NumElems = Mask.getNumOperands();
2336 Mask = getUnpacklMask(NumElems, DAG);
2337 while (NumElems != 4) {
2338 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2341 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2343 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2344 Mask = getZeroVector(MaskVT, DAG);
2345 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2346 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2347 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2350 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2352 static inline bool isZeroNode(SDOperand Elt) {
2353 return ((isa<ConstantSDNode>(Elt) &&
2354 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2355 (isa<ConstantFPSDNode>(Elt) &&
2356 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2359 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2360 /// vector and zero or undef vector.
2361 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2362 unsigned NumElems, unsigned Idx,
2363 bool isZero, SelectionDAG &DAG) {
2364 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2365 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2366 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2367 SDOperand Zero = DAG.getConstant(0, EVT);
2368 std::vector<SDOperand> MaskVec(NumElems, Zero);
2369 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2370 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2371 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2374 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2376 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2377 unsigned NumNonZero, unsigned NumZero,
2378 SelectionDAG &DAG) {
2384 for (unsigned i = 0; i < 16; ++i) {
2385 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2386 if (ThisIsNonZero && First) {
2388 V = getZeroVector(MVT::v8i16, DAG);
2390 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2395 SDOperand ThisElt(0, 0), LastElt(0, 0);
2396 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2397 if (LastIsNonZero) {
2398 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2400 if (ThisIsNonZero) {
2401 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2402 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2403 ThisElt, DAG.getConstant(8, MVT::i8));
2405 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2410 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2411 DAG.getConstant(i/2, MVT::i32));
2415 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2418 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
2420 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2421 unsigned NumNonZero, unsigned NumZero,
2422 SelectionDAG &DAG) {
2428 for (unsigned i = 0; i < 8; ++i) {
2429 bool isNonZero = (NonZeros & (1 << i)) != 0;
2433 V = getZeroVector(MVT::v8i16, DAG);
2435 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2438 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2439 DAG.getConstant(i, MVT::i32));
2447 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2448 // All zero's are handled with pxor.
2449 if (ISD::isBuildVectorAllZeros(Op.Val))
2452 // All one's are handled with pcmpeqd.
2453 if (ISD::isBuildVectorAllOnes(Op.Val))
2456 MVT::ValueType VT = Op.getValueType();
2457 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2458 unsigned EVTBits = MVT::getSizeInBits(EVT);
2460 unsigned NumElems = Op.getNumOperands();
2461 unsigned NumZero = 0;
2462 unsigned NumNonZero = 0;
2463 unsigned NonZeros = 0;
2464 std::set<SDOperand> Values;
2465 for (unsigned i = 0; i < NumElems; ++i) {
2466 SDOperand Elt = Op.getOperand(i);
2467 if (Elt.getOpcode() != ISD::UNDEF) {
2469 if (isZeroNode(Elt))
2472 NonZeros |= (1 << i);
2478 if (NumNonZero == 0)
2479 // Must be a mix of zero and undef. Return a zero vector.
2480 return getZeroVector(VT, DAG);
2482 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2483 if (Values.size() == 1)
2486 // Special case for single non-zero element.
2487 if (NumNonZero == 1) {
2488 unsigned Idx = CountTrailingZeros_32(NonZeros);
2489 SDOperand Item = Op.getOperand(Idx);
2490 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2492 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2493 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2496 if (EVTBits == 32) {
2497 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2498 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2500 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2501 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2502 std::vector<SDOperand> MaskVec;
2503 for (unsigned i = 0; i < NumElems; i++)
2504 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2505 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2506 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2507 DAG.getNode(ISD::UNDEF, VT), Mask);
2511 // Let legalizer expand 2-widde build_vector's.
2515 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2517 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG);
2518 if (V.Val) return V;
2521 if (EVTBits == 16) {
2522 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG);
2523 if (V.Val) return V;
2526 // If element VT is == 32 bits, turn it into a number of shuffles.
2527 std::vector<SDOperand> V(NumElems);
2528 if (NumElems == 4 && NumZero > 0) {
2529 for (unsigned i = 0; i < 4; ++i) {
2530 bool isZero = !(NonZeros & (1 << i));
2532 V[i] = getZeroVector(VT, DAG);
2534 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2537 for (unsigned i = 0; i < 2; ++i) {
2538 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2541 V[i] = V[i*2]; // Must be a zero vector.
2544 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2545 getMOVLMask(NumElems, DAG));
2548 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2549 getMOVLMask(NumElems, DAG));
2552 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2553 getUnpacklMask(NumElems, DAG));
2558 // Take advantage of the fact R32 to VR128 scalar_to_vector (i.e. movd)
2559 // clears the upper bits.
2560 // FIXME: we can do the same for v4f32 case when we know both parts of
2561 // the lower half come from scalar_to_vector (loadf32). We should do
2562 // that in post legalizer dag combiner with target specific hooks.
2563 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2565 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2566 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2567 std::vector<SDOperand> MaskVec;
2568 bool Reverse = (NonZeros & 0x3) == 2;
2569 for (unsigned i = 0; i < 2; ++i)
2571 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2573 MaskVec.push_back(DAG.getConstant(i, EVT));
2574 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2575 for (unsigned i = 0; i < 2; ++i)
2577 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2579 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2580 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2581 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2584 if (Values.size() > 2) {
2585 // Expand into a number of unpckl*.
2587 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2588 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2589 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2590 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2591 for (unsigned i = 0; i < NumElems; ++i)
2592 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2594 while (NumElems != 0) {
2595 for (unsigned i = 0; i < NumElems; ++i)
2596 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2607 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2608 SDOperand V1 = Op.getOperand(0);
2609 SDOperand V2 = Op.getOperand(1);
2610 SDOperand PermMask = Op.getOperand(2);
2611 MVT::ValueType VT = Op.getValueType();
2612 unsigned NumElems = PermMask.getNumOperands();
2613 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2614 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2616 if (isSplatMask(PermMask.Val)) {
2617 if (NumElems <= 4) return Op;
2618 // Promote it to a v4i32 splat.
2619 return PromoteSplat(Op, DAG);
2622 if (X86::isMOVLMask(PermMask.Val))
2623 return (V1IsUndef) ? V2 : Op;
2625 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2626 X86::isMOVSLDUPMask(PermMask.Val) ||
2627 X86::isMOVHLPSMask(PermMask.Val) ||
2628 X86::isMOVHPMask(PermMask.Val) ||
2629 X86::isMOVLPMask(PermMask.Val))
2632 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2633 ShouldXformToMOVLP(V1.Val, PermMask.Val))
2634 return CommuteVectorShuffle(Op, DAG);
2636 bool V1IsSplat = isSplatVector(V1.Val) || V1.getOpcode() == ISD::UNDEF;
2637 bool V2IsSplat = isSplatVector(V2.Val) || V2.getOpcode() == ISD::UNDEF;
2638 if (V1IsSplat && !V2IsSplat) {
2639 Op = CommuteVectorShuffle(Op, DAG);
2640 V1 = Op.getOperand(0);
2641 V2 = Op.getOperand(1);
2642 PermMask = Op.getOperand(2);
2646 if (isCommutedMOVL(PermMask.Val, V2IsSplat)) {
2647 if (V2IsUndef) return V1;
2648 Op = CommuteVectorShuffle(Op, DAG);
2649 V1 = Op.getOperand(0);
2650 V2 = Op.getOperand(1);
2651 PermMask = Op.getOperand(2);
2653 // V2 is a splat, so the mask may be malformed. That is, it may point
2654 // to any V2 element. The instruction selectior won't like this. Get
2655 // a corrected mask and commute to form a proper MOVS{S|D}.
2656 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2657 if (NewMask.Val != PermMask.Val)
2658 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2663 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2664 X86::isUNPCKLMask(PermMask.Val) ||
2665 X86::isUNPCKHMask(PermMask.Val))
2669 // Normalize mask so all entries that point to V2 points to its first
2670 // element then try to match unpck{h|l} again. If match, return a
2671 // new vector_shuffle with the corrected mask.
2672 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2673 if (NewMask.Val != PermMask.Val) {
2674 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2675 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2676 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2677 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2678 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2679 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2684 // Normalize the node to match x86 shuffle ops if needed
2685 if (V2.getOpcode() != ISD::UNDEF)
2686 if (isCommutedSHUFP(PermMask.Val)) {
2687 Op = CommuteVectorShuffle(Op, DAG);
2688 V1 = Op.getOperand(0);
2689 V2 = Op.getOperand(1);
2690 PermMask = Op.getOperand(2);
2693 // If VT is integer, try PSHUF* first, then SHUFP*.
2694 if (MVT::isInteger(VT)) {
2695 if (X86::isPSHUFDMask(PermMask.Val) ||
2696 X86::isPSHUFHWMask(PermMask.Val) ||
2697 X86::isPSHUFLWMask(PermMask.Val)) {
2698 if (V2.getOpcode() != ISD::UNDEF)
2699 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2700 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2704 if (X86::isSHUFPMask(PermMask.Val))
2707 // Handle v8i16 shuffle high / low shuffle node pair.
2708 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2709 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2710 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2711 std::vector<SDOperand> MaskVec;
2712 for (unsigned i = 0; i != 4; ++i)
2713 MaskVec.push_back(PermMask.getOperand(i));
2714 for (unsigned i = 4; i != 8; ++i)
2715 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2716 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2717 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2719 for (unsigned i = 0; i != 4; ++i)
2720 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2721 for (unsigned i = 4; i != 8; ++i)
2722 MaskVec.push_back(PermMask.getOperand(i));
2723 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
2724 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2727 // Floating point cases in the other order.
2728 if (X86::isSHUFPMask(PermMask.Val))
2730 if (X86::isPSHUFDMask(PermMask.Val) ||
2731 X86::isPSHUFHWMask(PermMask.Val) ||
2732 X86::isPSHUFLWMask(PermMask.Val)) {
2733 if (V2.getOpcode() != ISD::UNDEF)
2734 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2735 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2740 if (NumElems == 4) {
2741 MVT::ValueType MaskVT = PermMask.getValueType();
2742 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2743 std::vector<std::pair<int, int> > Locs;
2744 Locs.reserve(NumElems);
2745 std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2746 std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2749 // If no more than two elements come from either vector. This can be
2750 // implemented with two shuffles. First shuffle gather the elements.
2751 // The second shuffle, which takes the first shuffle as both of its
2752 // vector operands, put the elements into the right order.
2753 for (unsigned i = 0; i != NumElems; ++i) {
2754 SDOperand Elt = PermMask.getOperand(i);
2755 if (Elt.getOpcode() == ISD::UNDEF) {
2756 Locs[i] = std::make_pair(-1, -1);
2758 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2759 if (Val < NumElems) {
2760 Locs[i] = std::make_pair(0, NumLo);
2764 Locs[i] = std::make_pair(1, NumHi);
2765 if (2+NumHi < NumElems)
2766 Mask1[2+NumHi] = Elt;
2771 if (NumLo <= 2 && NumHi <= 2) {
2772 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2773 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask1));
2774 for (unsigned i = 0; i != NumElems; ++i) {
2775 if (Locs[i].first == -1)
2778 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2779 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2780 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2784 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2785 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask2));
2788 // Break it into (shuffle shuffle_hi, shuffle_lo).
2790 std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2791 std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2792 std::vector<SDOperand> *MaskPtr = &LoMask;
2793 unsigned MaskIdx = 0;
2795 unsigned HiIdx = NumElems/2;
2796 for (unsigned i = 0; i != NumElems; ++i) {
2797 if (i == NumElems/2) {
2803 SDOperand Elt = PermMask.getOperand(i);
2804 if (Elt.getOpcode() == ISD::UNDEF) {
2805 Locs[i] = std::make_pair(-1, -1);
2806 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2807 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2808 (*MaskPtr)[LoIdx] = Elt;
2811 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2812 (*MaskPtr)[HiIdx] = Elt;
2817 SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2818 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask));
2819 SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2820 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask));
2821 std::vector<SDOperand> MaskOps;
2822 for (unsigned i = 0; i != NumElems; ++i) {
2823 if (Locs[i].first == -1) {
2824 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2826 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2827 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2830 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2831 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskOps));
2838 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2839 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2842 MVT::ValueType VT = Op.getValueType();
2843 // TODO: handle v16i8.
2844 if (MVT::getSizeInBits(VT) == 16) {
2845 // Transform it so it match pextrw which produces a 32-bit result.
2846 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2847 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2848 Op.getOperand(0), Op.getOperand(1));
2849 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2850 DAG.getValueType(VT));
2851 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2852 } else if (MVT::getSizeInBits(VT) == 32) {
2853 SDOperand Vec = Op.getOperand(0);
2854 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2858 // SHUFPS the element to the lowest double word, then movss.
2859 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2860 SDOperand IdxNode = DAG.getConstant((Idx < 2) ? Idx : Idx+4,
2861 MVT::getVectorBaseType(MaskVT));
2862 std::vector<SDOperand> IdxVec;
2863 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
2864 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2865 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2866 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2867 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
2868 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2871 DAG.getConstant(0, MVT::i32));
2872 } else if (MVT::getSizeInBits(VT) == 64) {
2873 SDOperand Vec = Op.getOperand(0);
2874 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2878 // UNPCKHPD the element to the lowest double word, then movsd.
2879 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2880 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2881 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2882 std::vector<SDOperand> IdxVec;
2883 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
2884 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2885 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
2886 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2887 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2888 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2889 DAG.getConstant(0, MVT::i32));
2896 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2897 // Transform it so it match pinsrw which expects a 16-bit value in a R32
2898 // as its second argument.
2899 MVT::ValueType VT = Op.getValueType();
2900 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
2901 SDOperand N0 = Op.getOperand(0);
2902 SDOperand N1 = Op.getOperand(1);
2903 SDOperand N2 = Op.getOperand(2);
2904 if (MVT::getSizeInBits(BaseVT) == 16) {
2905 if (N1.getValueType() != MVT::i32)
2906 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2907 if (N2.getValueType() != MVT::i32)
2908 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
2909 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2910 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2911 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2914 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2915 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2916 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2917 std::vector<SDOperand> MaskVec;
2918 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2919 for (unsigned i = 1; i <= 3; ++i)
2920 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2921 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2922 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec));
2924 // Use two pinsrw instructions to insert a 32 bit value.
2926 if (MVT::isFloatingPoint(N1.getValueType())) {
2927 if (N1.getOpcode() == ISD::LOAD) {
2928 // Just load directly from f32mem to R32.
2929 N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
2932 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2933 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2934 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2935 DAG.getConstant(0, MVT::i32));
2938 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2939 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2940 DAG.getConstant(Idx, MVT::i32));
2941 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2942 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2943 DAG.getConstant(Idx+1, MVT::i32));
2944 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2952 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2953 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
2954 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
2957 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2958 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
2959 // one of the above mentioned nodes. It has to be wrapped because otherwise
2960 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2961 // be used to form addressing mode. These wrapped nodes will be selected
2964 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
2965 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2966 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
2967 DAG.getTargetConstantPool(CP->get(), getPointerTy(),
2968 CP->getAlignment()));
2969 if (Subtarget->isTargetDarwin()) {
2970 // With PIC, the address is actually $g + Offset.
2971 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
2972 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2973 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
2980 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
2981 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2982 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
2983 DAG.getTargetGlobalAddress(GV, getPointerTy()));
2984 if (Subtarget->isTargetDarwin()) {
2985 // With PIC, the address is actually $g + Offset.
2986 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
2987 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2988 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
2990 // For Darwin, external and weak symbols are indirect, so we want to load
2991 // the value at address GV, not the value of GV itself. This means that
2992 // the GlobalAddress must be in the base or index register of the address,
2993 // not the GV offset field.
2994 if (getTargetMachine().getRelocationModel() != Reloc::Static &&
2995 DarwinGVRequiresExtraLoad(GV))
2996 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
2997 Result, DAG.getSrcValue(NULL));
3004 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3005 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3006 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
3007 DAG.getTargetExternalSymbol(Sym, getPointerTy()));
3008 if (Subtarget->isTargetDarwin()) {
3009 // With PIC, the address is actually $g + Offset.
3010 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
3011 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3012 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
3018 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3019 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3020 "Not an i64 shift!");
3021 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3022 SDOperand ShOpLo = Op.getOperand(0);
3023 SDOperand ShOpHi = Op.getOperand(1);
3024 SDOperand ShAmt = Op.getOperand(2);
3025 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
3026 DAG.getConstant(31, MVT::i8))
3027 : DAG.getConstant(0, MVT::i32);
3029 SDOperand Tmp2, Tmp3;
3030 if (Op.getOpcode() == ISD::SHL_PARTS) {
3031 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3032 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3034 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3035 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3038 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
3039 ShAmt, DAG.getConstant(32, MVT::i8));
3042 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
3044 std::vector<MVT::ValueType> Tys;
3045 Tys.push_back(MVT::i32);
3046 Tys.push_back(MVT::Flag);
3047 std::vector<SDOperand> Ops;
3048 if (Op.getOpcode() == ISD::SHL_PARTS) {
3049 Ops.push_back(Tmp2);
3050 Ops.push_back(Tmp3);
3052 Ops.push_back(InFlag);
3053 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
3054 InFlag = Hi.getValue(1);
3057 Ops.push_back(Tmp3);
3058 Ops.push_back(Tmp1);
3060 Ops.push_back(InFlag);
3061 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
3063 Ops.push_back(Tmp2);
3064 Ops.push_back(Tmp3);
3066 Ops.push_back(InFlag);
3067 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
3068 InFlag = Lo.getValue(1);
3071 Ops.push_back(Tmp3);
3072 Ops.push_back(Tmp1);
3074 Ops.push_back(InFlag);
3075 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
3079 Tys.push_back(MVT::i32);
3080 Tys.push_back(MVT::i32);
3084 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
3087 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3088 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3089 Op.getOperand(0).getValueType() >= MVT::i16 &&
3090 "Unknown SINT_TO_FP to lower!");
3093 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3094 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3095 MachineFunction &MF = DAG.getMachineFunction();
3096 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3097 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3098 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
3099 DAG.getEntryNode(), Op.getOperand(0),
3100 StackSlot, DAG.getSrcValue(NULL));
3103 std::vector<MVT::ValueType> Tys;
3104 Tys.push_back(MVT::f64);
3105 Tys.push_back(MVT::Other);
3106 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
3107 std::vector<SDOperand> Ops;
3108 Ops.push_back(Chain);
3109 Ops.push_back(StackSlot);
3110 Ops.push_back(DAG.getValueType(SrcVT));
3111 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3115 Chain = Result.getValue(1);
3116 SDOperand InFlag = Result.getValue(2);
3118 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3119 // shouldn't be necessary except that RFP cannot be live across
3120 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3121 MachineFunction &MF = DAG.getMachineFunction();
3122 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3123 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3124 std::vector<MVT::ValueType> Tys;
3125 Tys.push_back(MVT::Other);
3126 std::vector<SDOperand> Ops;
3127 Ops.push_back(Chain);
3128 Ops.push_back(Result);
3129 Ops.push_back(StackSlot);
3130 Ops.push_back(DAG.getValueType(Op.getValueType()));
3131 Ops.push_back(InFlag);
3132 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
3133 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
3134 DAG.getSrcValue(NULL));
3140 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3141 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3142 "Unknown FP_TO_SINT to lower!");
3143 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3145 MachineFunction &MF = DAG.getMachineFunction();
3146 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3147 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3148 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3151 switch (Op.getValueType()) {
3152 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3153 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3154 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3155 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3158 SDOperand Chain = DAG.getEntryNode();
3159 SDOperand Value = Op.getOperand(0);
3161 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3162 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot,
3163 DAG.getSrcValue(0));
3164 std::vector<MVT::ValueType> Tys;
3165 Tys.push_back(MVT::f64);
3166 Tys.push_back(MVT::Other);
3167 std::vector<SDOperand> Ops;
3168 Ops.push_back(Chain);
3169 Ops.push_back(StackSlot);
3170 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
3171 Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
3172 Chain = Value.getValue(1);
3173 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3174 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3177 // Build the FP_TO_INT*_IN_MEM
3178 std::vector<SDOperand> Ops;
3179 Ops.push_back(Chain);
3180 Ops.push_back(Value);
3181 Ops.push_back(StackSlot);
3182 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
3185 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
3186 DAG.getSrcValue(NULL));
3189 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3190 MVT::ValueType VT = Op.getValueType();
3191 const Type *OpNTy = MVT::getTypeForValueType(VT);
3192 std::vector<Constant*> CV;
3193 if (VT == MVT::f64) {
3194 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3195 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3197 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3198 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3199 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3200 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3202 Constant *CS = ConstantStruct::get(CV);
3203 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3205 = DAG.getNode(X86ISD::LOAD_PACK,
3206 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
3207 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3210 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3211 MVT::ValueType VT = Op.getValueType();
3212 const Type *OpNTy = MVT::getTypeForValueType(VT);
3213 std::vector<Constant*> CV;
3214 if (VT == MVT::f64) {
3215 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3216 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3218 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3219 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3220 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3221 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3223 Constant *CS = ConstantStruct::get(CV);
3224 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3225 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK,
3226 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
3227 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3230 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
3231 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3233 SDOperand CC = Op.getOperand(2);
3234 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3235 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3238 if (translateX86CC(CC, isFP, X86CC, Flip)) {
3240 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
3241 Op.getOperand(1), Op.getOperand(0));
3243 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
3244 Op.getOperand(0), Op.getOperand(1));
3245 return DAG.getNode(X86ISD::SETCC, MVT::i8,
3246 DAG.getConstant(X86CC, MVT::i8), Cond);
3248 assert(isFP && "Illegal integer SetCC!");
3250 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
3251 Op.getOperand(0), Op.getOperand(1));
3252 std::vector<MVT::ValueType> Tys;
3253 std::vector<SDOperand> Ops;
3254 switch (SetCCOpcode) {
3255 default: assert(false && "Illegal floating point SetCC!");
3256 case ISD::SETOEQ: { // !PF & ZF
3257 Tys.push_back(MVT::i8);
3258 Tys.push_back(MVT::Flag);
3259 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
3260 Ops.push_back(Cond);
3261 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
3262 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
3263 DAG.getConstant(X86ISD::COND_E, MVT::i8),
3265 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3267 case ISD::SETUNE: { // PF | !ZF
3268 Tys.push_back(MVT::i8);
3269 Tys.push_back(MVT::Flag);
3270 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
3271 Ops.push_back(Cond);
3272 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
3273 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
3274 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
3276 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3282 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3283 MVT::ValueType VT = Op.getValueType();
3284 bool isFPStack = MVT::isFloatingPoint(VT) && !X86ScalarSSE;
3285 bool addTest = false;
3286 SDOperand Op0 = Op.getOperand(0);
3288 if (Op0.getOpcode() == ISD::SETCC)
3289 Op0 = LowerOperation(Op0, DAG);
3291 if (Op0.getOpcode() == X86ISD::SETCC) {
3292 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3293 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
3294 // have another use it will be eliminated.
3295 // If the X86ISD::SETCC has more than one use, then it's probably better
3296 // to use a test instead of duplicating the X86ISD::CMP (for register
3297 // pressure reason).
3298 unsigned CmpOpc = Op0.getOperand(1).getOpcode();
3299 if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
3300 CmpOpc == X86ISD::UCOMI) {
3301 if (!Op0.hasOneUse()) {
3302 std::vector<MVT::ValueType> Tys;
3303 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
3304 Tys.push_back(Op0.Val->getValueType(i));
3305 std::vector<SDOperand> Ops;
3306 for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
3307 Ops.push_back(Op0.getOperand(i));
3308 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
3311 CC = Op0.getOperand(0);
3312 Cond = Op0.getOperand(1);
3313 // Make a copy as flag result cannot be used by more than one.
3314 Cond = DAG.getNode(CmpOpc, MVT::Flag,
3315 Cond.getOperand(0), Cond.getOperand(1));
3317 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3324 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
3325 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
3328 std::vector<MVT::ValueType> Tys;
3329 Tys.push_back(Op.getValueType());
3330 Tys.push_back(MVT::Flag);
3331 std::vector<SDOperand> Ops;
3332 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3333 // condition is true.
3334 Ops.push_back(Op.getOperand(2));
3335 Ops.push_back(Op.getOperand(1));
3337 Ops.push_back(Cond);
3338 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
3341 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3342 bool addTest = false;
3343 SDOperand Cond = Op.getOperand(1);
3344 SDOperand Dest = Op.getOperand(2);
3346 if (Cond.getOpcode() == ISD::SETCC)
3347 Cond = LowerOperation(Cond, DAG);
3349 if (Cond.getOpcode() == X86ISD::SETCC) {
3350 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3351 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
3352 // have another use it will be eliminated.
3353 // If the X86ISD::SETCC has more than one use, then it's probably better
3354 // to use a test instead of duplicating the X86ISD::CMP (for register
3355 // pressure reason).
3356 unsigned CmpOpc = Cond.getOperand(1).getOpcode();
3357 if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
3358 CmpOpc == X86ISD::UCOMI) {
3359 if (!Cond.hasOneUse()) {
3360 std::vector<MVT::ValueType> Tys;
3361 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
3362 Tys.push_back(Cond.Val->getValueType(i));
3363 std::vector<SDOperand> Ops;
3364 for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
3365 Ops.push_back(Cond.getOperand(i));
3366 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
3369 CC = Cond.getOperand(0);
3370 Cond = Cond.getOperand(1);
3371 // Make a copy as flag result cannot be used by more than one.
3372 Cond = DAG.getNode(CmpOpc, MVT::Flag,
3373 Cond.getOperand(0), Cond.getOperand(1));
3380 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
3381 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
3383 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3384 Op.getOperand(0), Op.getOperand(2), CC, Cond);
3387 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3388 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3389 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
3390 DAG.getTargetJumpTable(JT->getIndex(),
3392 if (Subtarget->isTargetDarwin()) {
3393 // With PIC, the address is actually $g + Offset.
3394 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
3395 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3396 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
3402 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
3405 switch(Op.getNumOperands()) {
3407 assert(0 && "Do not know how to return this many arguments!");
3409 case 1: // ret void.
3410 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
3411 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
3413 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
3415 if (MVT::isVector(ArgVT)) {
3416 // Integer or FP vector result -> XMM0.
3417 if (DAG.getMachineFunction().liveout_empty())
3418 DAG.getMachineFunction().addLiveOut(X86::XMM0);
3419 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
3421 } else if (MVT::isInteger(ArgVT)) {
3422 // Integer result -> EAX
3423 if (DAG.getMachineFunction().liveout_empty())
3424 DAG.getMachineFunction().addLiveOut(X86::EAX);
3426 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
3428 } else if (!X86ScalarSSE) {
3429 // FP return with fp-stack value.
3430 if (DAG.getMachineFunction().liveout_empty())
3431 DAG.getMachineFunction().addLiveOut(X86::ST0);
3433 std::vector<MVT::ValueType> Tys;
3434 Tys.push_back(MVT::Other);
3435 Tys.push_back(MVT::Flag);
3436 std::vector<SDOperand> Ops;
3437 Ops.push_back(Op.getOperand(0));
3438 Ops.push_back(Op.getOperand(1));
3439 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
3441 // FP return with ScalarSSE (return on fp-stack).
3442 if (DAG.getMachineFunction().liveout_empty())
3443 DAG.getMachineFunction().addLiveOut(X86::ST0);
3446 SDOperand Chain = Op.getOperand(0);
3447 SDOperand Value = Op.getOperand(1);
3449 if (Value.getOpcode() == ISD::LOAD &&
3450 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
3451 Chain = Value.getOperand(0);
3452 MemLoc = Value.getOperand(1);
3454 // Spill the value to memory and reload it into top of stack.
3455 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
3456 MachineFunction &MF = DAG.getMachineFunction();
3457 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3458 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
3459 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
3460 Value, MemLoc, DAG.getSrcValue(0));
3462 std::vector<MVT::ValueType> Tys;
3463 Tys.push_back(MVT::f64);
3464 Tys.push_back(MVT::Other);
3465 std::vector<SDOperand> Ops;
3466 Ops.push_back(Chain);
3467 Ops.push_back(MemLoc);
3468 Ops.push_back(DAG.getValueType(ArgVT));
3469 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
3471 Tys.push_back(MVT::Other);
3472 Tys.push_back(MVT::Flag);
3474 Ops.push_back(Copy.getValue(1));
3475 Ops.push_back(Copy);
3476 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
3481 if (DAG.getMachineFunction().liveout_empty()) {
3482 DAG.getMachineFunction().addLiveOut(X86::EAX);
3483 DAG.getMachineFunction().addLiveOut(X86::EDX);
3486 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
3488 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
3491 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
3492 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
3497 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3498 if (FormalArgs.size() == 0) {
3499 unsigned CC = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
3500 if (CC == CallingConv::Fast && EnableFastCC)
3501 LowerFastCCArguments(Op, DAG);
3503 LowerCCCArguments(Op, DAG);
3505 return FormalArgs[Op.ResNo];
3508 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3509 SDOperand InFlag(0, 0);
3510 SDOperand Chain = Op.getOperand(0);
3512 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3513 if (Align == 0) Align = 1;
3515 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3516 // If not DWORD aligned, call memset if size is less than the threshold.
3517 // It knows how to align to the right boundary first.
3518 if ((Align & 3) != 0 ||
3519 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3520 MVT::ValueType IntPtr = getPointerTy();
3521 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3522 std::vector<std::pair<SDOperand, const Type*> > Args;
3523 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
3524 // Extend the ubyte argument to be an int value for the call.
3525 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3526 Args.push_back(std::make_pair(Val, IntPtrTy));
3527 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
3528 std::pair<SDOperand,SDOperand> CallResult =
3529 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
3530 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3531 return CallResult.second;
3536 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3537 unsigned BytesLeft = 0;
3538 bool TwoRepStos = false;
3541 unsigned Val = ValC->getValue() & 255;
3543 // If the value is a constant, then we can potentially use larger sets.
3544 switch (Align & 3) {
3545 case 2: // WORD aligned
3547 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
3548 BytesLeft = I->getValue() % 2;
3549 Val = (Val << 8) | Val;
3552 case 0: // DWORD aligned
3555 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
3556 BytesLeft = I->getValue() % 4;
3558 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
3559 DAG.getConstant(2, MVT::i8));
3562 Val = (Val << 8) | Val;
3563 Val = (Val << 16) | Val;
3566 default: // Byte aligned
3568 Count = Op.getOperand(3);
3573 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3575 InFlag = Chain.getValue(1);
3578 Count = Op.getOperand(3);
3579 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3580 InFlag = Chain.getValue(1);
3583 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
3584 InFlag = Chain.getValue(1);
3585 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
3586 InFlag = Chain.getValue(1);
3588 std::vector<MVT::ValueType> Tys;
3589 Tys.push_back(MVT::Other);
3590 Tys.push_back(MVT::Flag);
3591 std::vector<SDOperand> Ops;
3592 Ops.push_back(Chain);
3593 Ops.push_back(DAG.getValueType(AVT));
3594 Ops.push_back(InFlag);
3595 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
3598 InFlag = Chain.getValue(1);
3599 Count = Op.getOperand(3);
3600 MVT::ValueType CVT = Count.getValueType();
3601 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3602 DAG.getConstant(3, CVT));
3603 Chain = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
3604 InFlag = Chain.getValue(1);
3606 Tys.push_back(MVT::Other);
3607 Tys.push_back(MVT::Flag);
3609 Ops.push_back(Chain);
3610 Ops.push_back(DAG.getValueType(MVT::i8));
3611 Ops.push_back(InFlag);
3612 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
3613 } else if (BytesLeft) {
3614 // Issue stores for the last 1 - 3 bytes.
3616 unsigned Val = ValC->getValue() & 255;
3617 unsigned Offset = I->getValue() - BytesLeft;
3618 SDOperand DstAddr = Op.getOperand(1);
3619 MVT::ValueType AddrVT = DstAddr.getValueType();
3620 if (BytesLeft >= 2) {
3621 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3622 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
3623 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3624 DAG.getConstant(Offset, AddrVT)),
3625 DAG.getSrcValue(NULL));
3630 if (BytesLeft == 1) {
3631 Value = DAG.getConstant(Val, MVT::i8);
3632 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
3633 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3634 DAG.getConstant(Offset, AddrVT)),
3635 DAG.getSrcValue(NULL));
3642 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3643 SDOperand Chain = Op.getOperand(0);
3645 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3646 if (Align == 0) Align = 1;
3648 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3649 // If not DWORD aligned, call memcpy if size is less than the threshold.
3650 // It knows how to align to the right boundary first.
3651 if ((Align & 3) != 0 ||
3652 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3653 MVT::ValueType IntPtr = getPointerTy();
3654 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3655 std::vector<std::pair<SDOperand, const Type*> > Args;
3656 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
3657 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
3658 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
3659 std::pair<SDOperand,SDOperand> CallResult =
3660 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
3661 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3662 return CallResult.second;
3667 unsigned BytesLeft = 0;
3668 bool TwoRepMovs = false;
3669 switch (Align & 3) {
3670 case 2: // WORD aligned
3672 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
3673 BytesLeft = I->getValue() % 2;
3675 case 0: // DWORD aligned
3678 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
3679 BytesLeft = I->getValue() % 4;
3681 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
3682 DAG.getConstant(2, MVT::i8));
3686 default: // Byte aligned
3688 Count = Op.getOperand(3);
3692 SDOperand InFlag(0, 0);
3693 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
3694 InFlag = Chain.getValue(1);
3695 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
3696 InFlag = Chain.getValue(1);
3697 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
3698 InFlag = Chain.getValue(1);
3700 std::vector<MVT::ValueType> Tys;
3701 Tys.push_back(MVT::Other);
3702 Tys.push_back(MVT::Flag);
3703 std::vector<SDOperand> Ops;
3704 Ops.push_back(Chain);
3705 Ops.push_back(DAG.getValueType(AVT));
3706 Ops.push_back(InFlag);
3707 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
3710 InFlag = Chain.getValue(1);
3711 Count = Op.getOperand(3);
3712 MVT::ValueType CVT = Count.getValueType();
3713 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3714 DAG.getConstant(3, CVT));
3715 Chain = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
3716 InFlag = Chain.getValue(1);
3718 Tys.push_back(MVT::Other);
3719 Tys.push_back(MVT::Flag);
3721 Ops.push_back(Chain);
3722 Ops.push_back(DAG.getValueType(MVT::i8));
3723 Ops.push_back(InFlag);
3724 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
3725 } else if (BytesLeft) {
3726 // Issue loads and stores for the last 1 - 3 bytes.
3727 unsigned Offset = I->getValue() - BytesLeft;
3728 SDOperand DstAddr = Op.getOperand(1);
3729 MVT::ValueType DstVT = DstAddr.getValueType();
3730 SDOperand SrcAddr = Op.getOperand(2);
3731 MVT::ValueType SrcVT = SrcAddr.getValueType();
3733 if (BytesLeft >= 2) {
3734 Value = DAG.getLoad(MVT::i16, Chain,
3735 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3736 DAG.getConstant(Offset, SrcVT)),
3737 DAG.getSrcValue(NULL));
3738 Chain = Value.getValue(1);
3739 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
3740 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3741 DAG.getConstant(Offset, DstVT)),
3742 DAG.getSrcValue(NULL));
3747 if (BytesLeft == 1) {
3748 Value = DAG.getLoad(MVT::i8, Chain,
3749 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3750 DAG.getConstant(Offset, SrcVT)),
3751 DAG.getSrcValue(NULL));
3752 Chain = Value.getValue(1);
3753 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
3754 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3755 DAG.getConstant(Offset, DstVT)),
3756 DAG.getSrcValue(NULL));
3764 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3765 std::vector<MVT::ValueType> Tys;
3766 Tys.push_back(MVT::Other);
3767 Tys.push_back(MVT::Flag);
3768 std::vector<SDOperand> Ops;
3769 Ops.push_back(Op.getOperand(0));
3770 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
3772 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
3773 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
3774 MVT::i32, Ops[0].getValue(2)));
3775 Ops.push_back(Ops[1].getValue(1));
3776 Tys[0] = Tys[1] = MVT::i32;
3777 Tys.push_back(MVT::Other);
3778 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
3781 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3782 // vastart just stores the address of the VarArgsFrameIndex slot into the
3783 // memory location argument.
3784 // FIXME: Replace MVT::i32 with PointerTy
3785 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
3786 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
3787 Op.getOperand(1), Op.getOperand(2));
3791 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
3792 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
3794 default: return SDOperand(); // Don't custom lower most intrinsics.
3795 // Comparison intrinsics.
3796 case Intrinsic::x86_sse_comieq_ss:
3797 case Intrinsic::x86_sse_comilt_ss:
3798 case Intrinsic::x86_sse_comile_ss:
3799 case Intrinsic::x86_sse_comigt_ss:
3800 case Intrinsic::x86_sse_comige_ss:
3801 case Intrinsic::x86_sse_comineq_ss:
3802 case Intrinsic::x86_sse_ucomieq_ss:
3803 case Intrinsic::x86_sse_ucomilt_ss:
3804 case Intrinsic::x86_sse_ucomile_ss:
3805 case Intrinsic::x86_sse_ucomigt_ss:
3806 case Intrinsic::x86_sse_ucomige_ss:
3807 case Intrinsic::x86_sse_ucomineq_ss:
3808 case Intrinsic::x86_sse2_comieq_sd:
3809 case Intrinsic::x86_sse2_comilt_sd:
3810 case Intrinsic::x86_sse2_comile_sd:
3811 case Intrinsic::x86_sse2_comigt_sd:
3812 case Intrinsic::x86_sse2_comige_sd:
3813 case Intrinsic::x86_sse2_comineq_sd:
3814 case Intrinsic::x86_sse2_ucomieq_sd:
3815 case Intrinsic::x86_sse2_ucomilt_sd:
3816 case Intrinsic::x86_sse2_ucomile_sd:
3817 case Intrinsic::x86_sse2_ucomigt_sd:
3818 case Intrinsic::x86_sse2_ucomige_sd:
3819 case Intrinsic::x86_sse2_ucomineq_sd: {
3821 ISD::CondCode CC = ISD::SETCC_INVALID;
3824 case Intrinsic::x86_sse_comieq_ss:
3825 case Intrinsic::x86_sse2_comieq_sd:
3829 case Intrinsic::x86_sse_comilt_ss:
3830 case Intrinsic::x86_sse2_comilt_sd:
3834 case Intrinsic::x86_sse_comile_ss:
3835 case Intrinsic::x86_sse2_comile_sd:
3839 case Intrinsic::x86_sse_comigt_ss:
3840 case Intrinsic::x86_sse2_comigt_sd:
3844 case Intrinsic::x86_sse_comige_ss:
3845 case Intrinsic::x86_sse2_comige_sd:
3849 case Intrinsic::x86_sse_comineq_ss:
3850 case Intrinsic::x86_sse2_comineq_sd:
3854 case Intrinsic::x86_sse_ucomieq_ss:
3855 case Intrinsic::x86_sse2_ucomieq_sd:
3856 Opc = X86ISD::UCOMI;
3859 case Intrinsic::x86_sse_ucomilt_ss:
3860 case Intrinsic::x86_sse2_ucomilt_sd:
3861 Opc = X86ISD::UCOMI;
3864 case Intrinsic::x86_sse_ucomile_ss:
3865 case Intrinsic::x86_sse2_ucomile_sd:
3866 Opc = X86ISD::UCOMI;
3869 case Intrinsic::x86_sse_ucomigt_ss:
3870 case Intrinsic::x86_sse2_ucomigt_sd:
3871 Opc = X86ISD::UCOMI;
3874 case Intrinsic::x86_sse_ucomige_ss:
3875 case Intrinsic::x86_sse2_ucomige_sd:
3876 Opc = X86ISD::UCOMI;
3879 case Intrinsic::x86_sse_ucomineq_ss:
3880 case Intrinsic::x86_sse2_ucomineq_sd:
3881 Opc = X86ISD::UCOMI;
3887 translateX86CC(CC, true, X86CC, Flip);
3888 SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1),
3889 Op.getOperand(Flip?1:2));
3890 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
3891 DAG.getConstant(X86CC, MVT::i8), Cond);
3892 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
3897 /// LowerOperation - Provide custom lowering hooks for some operations.
3899 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3900 switch (Op.getOpcode()) {
3901 default: assert(0 && "Should not custom lower this!");
3902 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3903 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3904 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3905 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
3906 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3907 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3908 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3909 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
3910 case ISD::SHL_PARTS:
3911 case ISD::SRA_PARTS:
3912 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
3913 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3914 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3915 case ISD::FABS: return LowerFABS(Op, DAG);
3916 case ISD::FNEG: return LowerFNEG(Op, DAG);
3917 case ISD::SETCC: return LowerSETCC(Op, DAG);
3918 case ISD::SELECT: return LowerSELECT(Op, DAG);
3919 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3920 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3921 case ISD::RET: return LowerRET(Op, DAG);
3922 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
3923 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
3924 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
3925 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
3926 case ISD::VASTART: return LowerVASTART(Op, DAG);
3927 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3931 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
3933 default: return NULL;
3934 case X86ISD::SHLD: return "X86ISD::SHLD";
3935 case X86ISD::SHRD: return "X86ISD::SHRD";
3936 case X86ISD::FAND: return "X86ISD::FAND";
3937 case X86ISD::FXOR: return "X86ISD::FXOR";
3938 case X86ISD::FILD: return "X86ISD::FILD";
3939 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
3940 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
3941 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
3942 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
3943 case X86ISD::FLD: return "X86ISD::FLD";
3944 case X86ISD::FST: return "X86ISD::FST";
3945 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
3946 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
3947 case X86ISD::CALL: return "X86ISD::CALL";
3948 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
3949 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
3950 case X86ISD::CMP: return "X86ISD::CMP";
3951 case X86ISD::TEST: return "X86ISD::TEST";
3952 case X86ISD::COMI: return "X86ISD::COMI";
3953 case X86ISD::UCOMI: return "X86ISD::UCOMI";
3954 case X86ISD::SETCC: return "X86ISD::SETCC";
3955 case X86ISD::CMOV: return "X86ISD::CMOV";
3956 case X86ISD::BRCOND: return "X86ISD::BRCOND";
3957 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
3958 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
3959 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
3960 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
3961 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
3962 case X86ISD::Wrapper: return "X86ISD::Wrapper";
3963 case X86ISD::S2VEC: return "X86ISD::S2VEC";
3964 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
3965 case X86ISD::PINSRW: return "X86ISD::PINSRW";
3969 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3971 uint64_t &KnownZero,
3973 unsigned Depth) const {
3974 unsigned Opc = Op.getOpcode();
3975 assert((Opc >= ISD::BUILTIN_OP_END ||
3976 Opc == ISD::INTRINSIC_WO_CHAIN ||
3977 Opc == ISD::INTRINSIC_W_CHAIN ||
3978 Opc == ISD::INTRINSIC_VOID) &&
3979 "Should use MaskedValueIsZero if you don't know whether Op"
3980 " is a target node!");
3982 KnownZero = KnownOne = 0; // Don't know anything.
3986 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
3991 std::vector<unsigned> X86TargetLowering::
3992 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3993 MVT::ValueType VT) const {
3994 if (Constraint.size() == 1) {
3995 // FIXME: not handling fp-stack yet!
3996 // FIXME: not handling MMX registers yet ('y' constraint).
3997 switch (Constraint[0]) { // GCC X86 Constraint Letters
3998 default: break; // Unknown constriant letter
3999 case 'r': // GENERAL_REGS
4000 case 'R': // LEGACY_REGS
4002 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
4003 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
4004 else if (VT == MVT::i16)
4005 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
4006 X86::SI, X86::DI, X86::BP, X86::SP, 0);
4007 else if (VT == MVT::i8)
4008 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4010 case 'l': // INDEX_REGS
4012 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
4013 X86::ESI, X86::EDI, X86::EBP, 0);
4014 else if (VT == MVT::i16)
4015 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
4016 X86::SI, X86::DI, X86::BP, 0);
4017 else if (VT == MVT::i8)
4018 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4020 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4023 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4024 else if (VT == MVT::i16)
4025 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4026 else if (VT == MVT::i8)
4027 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4029 case 'x': // SSE_REGS if SSE1 allowed
4030 if (Subtarget->hasSSE1())
4031 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4032 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
4034 return std::vector<unsigned>();
4035 case 'Y': // SSE_REGS if SSE2 allowed
4036 if (Subtarget->hasSSE2())
4037 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4038 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
4040 return std::vector<unsigned>();
4044 return std::vector<unsigned>();
4047 /// isLegalAddressImmediate - Return true if the integer value or
4048 /// GlobalValue can be used as the offset of the target addressing mode.
4049 bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
4050 // X86 allows a sign-extended 32-bit immediate field.
4051 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4054 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4055 if (Subtarget->isTargetDarwin()) {
4056 Reloc::Model RModel = getTargetMachine().getRelocationModel();
4057 if (RModel == Reloc::Static)
4059 else if (RModel == Reloc::DynamicNoPIC)
4060 return !DarwinGVRequiresExtraLoad(GV);
4067 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4068 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4069 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4070 /// are assumed to be legal.
4072 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4073 // Only do shuffles on 128-bit vector types for now.
4074 if (MVT::getSizeInBits(VT) == 64) return false;
4075 return (Mask.Val->getNumOperands() <= 4 ||
4076 isSplatMask(Mask.Val) ||
4077 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4078 X86::isUNPCKLMask(Mask.Val) ||
4079 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4080 X86::isUNPCKHMask(Mask.Val));
4083 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4085 SelectionDAG &DAG) const {
4086 unsigned NumElts = BVOps.size();
4087 // Only do shuffles on 128-bit vector types for now.
4088 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4089 if (NumElts == 2) return true;
4091 return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
4092 isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));