1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Only provide customized ctpop vector bit twiddling for vector types we
991 // know to perform better than using the popcnt instructions on each vector
992 // element. If popcnt isn't supported, always provide the custom version.
993 if (!Subtarget->hasPOPCNT()) {
994 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
995 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
998 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
999 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1000 MVT VT = (MVT::SimpleValueType)i;
1001 // Do not attempt to custom lower non-power-of-2 vectors
1002 if (!isPowerOf2_32(VT.getVectorNumElements()))
1004 // Do not attempt to custom lower non-128-bit vectors
1005 if (!VT.is128BitVector())
1007 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012 // We support custom legalizing of sext and anyext loads for specific
1013 // memory vector types which we can load as a scalar (or sequence of
1014 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1015 // loads these must work with a single scalar load.
1016 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1026 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1027 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1028 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1033 if (Subtarget->is64Bit()) {
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1038 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1039 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1040 MVT VT = (MVT::SimpleValueType)i;
1042 // Do not attempt to promote non-128-bit vectors
1043 if (!VT.is128BitVector())
1046 setOperationAction(ISD::AND, VT, Promote);
1047 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1048 setOperationAction(ISD::OR, VT, Promote);
1049 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1050 setOperationAction(ISD::XOR, VT, Promote);
1051 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1052 setOperationAction(ISD::LOAD, VT, Promote);
1053 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1054 setOperationAction(ISD::SELECT, VT, Promote);
1055 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1058 // Custom lower v2i64 and v2f64 selects.
1059 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1069 // As there is no 64-bit GPR available, we need build a special custom
1070 // sequence to convert from v2i32 to v2f32.
1071 if (!Subtarget->is64Bit())
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1074 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1075 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1077 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1079 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1080 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1081 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1084 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1085 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1090 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1107 // FIXME: Do we need to handle scalar-to-vector here?
1108 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1110 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1114 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1115 // There is no BLENDI for byte vectors. We don't need to custom lower
1116 // some vselects for now.
1117 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1119 // SSE41 brings specific instructions for doing vector sign extend even in
1120 // cases where we don't have SRA.
1121 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1122 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1123 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1125 // i8 and i16 vectors are custom because the source register and source
1126 // source memory operand types are not the same width. f32 vectors are
1127 // custom since the immediate controlling the insert encodes additional
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1139 // FIXME: these should be Legal, but that's only for the case where
1140 // the index is constant. For now custom expand to deal with that.
1141 if (Subtarget->is64Bit()) {
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1147 if (Subtarget->hasSSE2()) {
1148 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1154 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1157 // In the customized shift lowering, the legal cases in AVX2 will be
1159 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1163 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1165 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1168 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1169 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1172 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1173 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1176 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1180 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1191 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1193 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1204 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1206 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1207 // even though v8i16 is a legal type.
1208 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1209 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1210 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1212 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1213 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1214 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1216 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1217 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1219 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1221 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1235 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1242 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1254 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1255 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1257 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1258 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1260 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1261 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1262 setOperationAction(ISD::FMA, MVT::f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::f64, Legal);
1266 if (Subtarget->hasInt256()) {
1267 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1268 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1269 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1270 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1272 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1273 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1274 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1275 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1277 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1280 // Don't lower v32i8 because there is no 128-bit byte mul
1282 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1284 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1285 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1287 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1288 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1290 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1291 // when we have a 256bit-wide blend with immediate.
1292 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1294 // Only provide customized ctpop vector bit twiddling for vector types we
1295 // know to perform better than using the popcnt instructions on each
1296 // vector element. If popcnt isn't supported, always provide the custom
1298 if (!Subtarget->hasPOPCNT())
1299 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1301 // Custom CTPOP always performs better on natively supported v8i32
1302 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1305 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1306 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1307 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1309 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1312 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1314 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1317 // Don't lower v32i8 because there is no 128-bit byte mul
1320 // In the customized shift lowering, the legal cases in AVX2 will be
1322 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1323 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1325 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1330 // Custom lower several nodes for 256-bit types.
1331 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1332 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1333 MVT VT = (MVT::SimpleValueType)i;
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1434 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1435 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1439 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1445 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1446 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1506 // Custom lower several nodes.
1507 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1508 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1509 MVT VT = (MVT::SimpleValueType)i;
1511 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Extract subvector is special because the value type
1513 // (result) is 256/128-bit but the source is 512-bit wide.
1514 if (VT.is128BitVector() || VT.is256BitVector()) {
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1517 if (VT.getVectorElementType() == MVT::i1)
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1520 // Do not attempt to custom lower other non-512-bit vectors
1521 if (!VT.is512BitVector())
1524 if ( EltSize >= 32) {
1525 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1528 setOperationAction(ISD::VSELECT, VT, Legal);
1529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1532 setOperationAction(ISD::MLOAD, VT, Legal);
1533 setOperationAction(ISD::MSTORE, VT, Legal);
1536 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1537 MVT VT = (MVT::SimpleValueType)i;
1539 // Do not attempt to promote non-256-bit vectors.
1540 if (!VT.is512BitVector())
1543 setOperationAction(ISD::SELECT, VT, Promote);
1544 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1548 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1549 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1550 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1553 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1555 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1556 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1557 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1558 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1559 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1560 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1561 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1562 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1563 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1565 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1566 const MVT VT = (MVT::SimpleValueType)i;
1568 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1570 // Do not attempt to promote non-256-bit vectors.
1571 if (!VT.is512BitVector())
1575 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1576 setOperationAction(ISD::VSELECT, VT, Legal);
1581 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1582 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1583 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1585 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1586 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1589 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1590 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1591 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1592 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1597 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1598 // of this type with custom code.
1599 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1600 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1601 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 bool HaveXMMArgs = Is64Bit && !IsWin64;
2554 bool NoImplicitFloatOps = Fn->getAttributes().hasAttribute(
2555 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2556 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2557 "SSE register cannot be used when SSE is disabled!");
2558 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2559 !Subtarget->hasSSE1())
2560 HaveXMMArgs = false;
2562 // 64-bit calling conventions support varargs and register parameters, so we
2563 // have to do extra work to spill them in the prologue.
2564 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2565 // Find the first unallocated argument registers.
2566 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2567 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2568 unsigned NumIntRegs =
2569 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2570 unsigned NumXMMRegs =
2571 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2572 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2573 "SSE register cannot be used when SSE is disabled!");
2575 // Gather all the live in physical registers.
2576 SmallVector<SDValue, 6> LiveGPRs;
2577 SmallVector<SDValue, 8> LiveXMMRegs;
2579 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2580 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2582 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2584 if (!ArgXMMs.empty()) {
2585 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2586 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2587 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2588 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2589 LiveXMMRegs.push_back(
2590 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2595 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2596 // Get to the caller-allocated home save location. Add 8 to account
2597 // for the return address.
2598 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2599 FuncInfo->setRegSaveFrameIndex(
2600 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2601 // Fixup to set vararg frame on shadow area (4 x i64).
2603 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2605 // For X86-64, if there are vararg parameters that are passed via
2606 // registers, then we must store them to their spots on the stack so
2607 // they may be loaded by deferencing the result of va_next.
2608 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2609 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2610 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2611 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2614 // Store the integer parameter registers.
2615 SmallVector<SDValue, 8> MemOps;
2616 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2618 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2619 for (SDValue Val : LiveGPRs) {
2620 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2621 DAG.getIntPtrConstant(Offset));
2623 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2624 MachinePointerInfo::getFixedStack(
2625 FuncInfo->getRegSaveFrameIndex(), Offset),
2627 MemOps.push_back(Store);
2631 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2632 // Now store the XMM (fp + vector) parameter registers.
2633 SmallVector<SDValue, 12> SaveXMMOps;
2634 SaveXMMOps.push_back(Chain);
2635 SaveXMMOps.push_back(ALVal);
2636 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2637 FuncInfo->getRegSaveFrameIndex()));
2638 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2639 FuncInfo->getVarArgsFPOffset()));
2640 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2642 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2643 MVT::Other, SaveXMMOps));
2646 if (!MemOps.empty())
2647 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2650 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2651 // Find the largest legal vector type.
2652 MVT VecVT = MVT::Other;
2653 // FIXME: Only some x86_32 calling conventions support AVX512.
2654 if (Subtarget->hasAVX512() &&
2655 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2656 CallConv == CallingConv::Intel_OCL_BI)))
2657 VecVT = MVT::v16f32;
2658 else if (Subtarget->hasAVX())
2660 else if (Subtarget->hasSSE2())
2663 // We forward some GPRs and some vector types.
2664 SmallVector<MVT, 2> RegParmTypes;
2665 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2666 RegParmTypes.push_back(IntVT);
2667 if (VecVT != MVT::Other)
2668 RegParmTypes.push_back(VecVT);
2670 // Compute the set of forwarded registers. The rest are scratch.
2671 SmallVectorImpl<ForwardedRegister> &Forwards =
2672 FuncInfo->getForwardedMustTailRegParms();
2673 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2675 // Conservatively forward AL on x86_64, since it might be used for varargs.
2676 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2677 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2678 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2681 // Copy all forwards from physical to virtual registers.
2682 for (ForwardedRegister &F : Forwards) {
2683 // FIXME: Can we use a less constrained schedule?
2684 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2685 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2686 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2690 // Some CCs need callee pop.
2691 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2692 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2693 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2695 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2696 // If this is an sret function, the return should pop the hidden pointer.
2697 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2698 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2699 argsAreStructReturn(Ins) == StackStructReturn)
2700 FuncInfo->setBytesToPopOnReturn(4);
2704 // RegSaveFrameIndex is X86-64 only.
2705 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2706 if (CallConv == CallingConv::X86_FastCall ||
2707 CallConv == CallingConv::X86_ThisCall)
2708 // fastcc functions can't have varargs.
2709 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2712 FuncInfo->setArgumentStackSize(StackSize);
2718 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2719 SDValue StackPtr, SDValue Arg,
2720 SDLoc dl, SelectionDAG &DAG,
2721 const CCValAssign &VA,
2722 ISD::ArgFlagsTy Flags) const {
2723 unsigned LocMemOffset = VA.getLocMemOffset();
2724 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2725 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2726 if (Flags.isByVal())
2727 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2729 return DAG.getStore(Chain, dl, Arg, PtrOff,
2730 MachinePointerInfo::getStack(LocMemOffset),
2734 /// Emit a load of return address if tail call
2735 /// optimization is performed and it is required.
2737 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2738 SDValue &OutRetAddr, SDValue Chain,
2739 bool IsTailCall, bool Is64Bit,
2740 int FPDiff, SDLoc dl) const {
2741 // Adjust the Return address stack slot.
2742 EVT VT = getPointerTy();
2743 OutRetAddr = getReturnAddressFrameIndex(DAG);
2745 // Load the "old" Return address.
2746 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2747 false, false, false, 0);
2748 return SDValue(OutRetAddr.getNode(), 1);
2751 /// Emit a store of the return address if tail call
2752 /// optimization is performed and it is required (FPDiff!=0).
2753 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2754 SDValue Chain, SDValue RetAddrFrIdx,
2755 EVT PtrVT, unsigned SlotSize,
2756 int FPDiff, SDLoc dl) {
2757 // Store the return address to the appropriate stack slot.
2758 if (!FPDiff) return Chain;
2759 // Calculate the new stack slot for the return address.
2760 int NewReturnAddrFI =
2761 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2763 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2764 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2765 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2771 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2772 SmallVectorImpl<SDValue> &InVals) const {
2773 SelectionDAG &DAG = CLI.DAG;
2775 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2776 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2777 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2778 SDValue Chain = CLI.Chain;
2779 SDValue Callee = CLI.Callee;
2780 CallingConv::ID CallConv = CLI.CallConv;
2781 bool &isTailCall = CLI.IsTailCall;
2782 bool isVarArg = CLI.IsVarArg;
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 bool Is64Bit = Subtarget->is64Bit();
2786 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2787 StructReturnType SR = callIsStructReturn(Outs);
2788 bool IsSibcall = false;
2789 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2791 if (MF.getTarget().Options.DisableTailCalls)
2794 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2796 // Force this to be a tail call. The verifier rules are enough to ensure
2797 // that we can lower this successfully without moving the return address
2800 } else if (isTailCall) {
2801 // Check if it's really possible to do a tail call.
2802 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2803 isVarArg, SR != NotStructReturn,
2804 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2805 Outs, OutVals, Ins, DAG);
2807 // Sibcalls are automatically detected tailcalls which do not require
2809 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2816 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2817 "Var args not supported with calling convention fastcc, ghc or hipe");
2819 // Analyze operands of the call, assigning locations to each operand.
2820 SmallVector<CCValAssign, 16> ArgLocs;
2821 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2823 // Allocate shadow area for Win64
2825 CCInfo.AllocateStack(32, 8);
2827 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2829 // Get a count of how many bytes are to be pushed on the stack.
2830 unsigned NumBytes = CCInfo.getNextStackOffset();
2832 // This is a sibcall. The memory operands are available in caller's
2833 // own caller's stack.
2835 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2836 IsTailCallConvention(CallConv))
2837 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2840 if (isTailCall && !IsSibcall && !IsMustTail) {
2841 // Lower arguments at fp - stackoffset + fpdiff.
2842 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2844 FPDiff = NumBytesCallerPushed - NumBytes;
2846 // Set the delta of movement of the returnaddr stackslot.
2847 // But only set if delta is greater than previous delta.
2848 if (FPDiff < X86Info->getTCReturnAddrDelta())
2849 X86Info->setTCReturnAddrDelta(FPDiff);
2852 unsigned NumBytesToPush = NumBytes;
2853 unsigned NumBytesToPop = NumBytes;
2855 // If we have an inalloca argument, all stack space has already been allocated
2856 // for us and be right at the top of the stack. We don't support multiple
2857 // arguments passed in memory when using inalloca.
2858 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2860 if (!ArgLocs.back().isMemLoc())
2861 report_fatal_error("cannot use inalloca attribute on a register "
2863 if (ArgLocs.back().getLocMemOffset() != 0)
2864 report_fatal_error("any parameter with the inalloca attribute must be "
2865 "the only memory argument");
2869 Chain = DAG.getCALLSEQ_START(
2870 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2872 SDValue RetAddrFrIdx;
2873 // Load return address for tail calls.
2874 if (isTailCall && FPDiff)
2875 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2876 Is64Bit, FPDiff, dl);
2878 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2879 SmallVector<SDValue, 8> MemOpChains;
2882 // Walk the register/memloc assignments, inserting copies/loads. In the case
2883 // of tail call optimization arguments are handle later.
2884 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2885 DAG.getSubtarget().getRegisterInfo());
2886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2887 // Skip inalloca arguments, they have already been written.
2888 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2889 if (Flags.isInAlloca())
2892 CCValAssign &VA = ArgLocs[i];
2893 EVT RegVT = VA.getLocVT();
2894 SDValue Arg = OutVals[i];
2895 bool isByVal = Flags.isByVal();
2897 // Promote the value if needed.
2898 switch (VA.getLocInfo()) {
2899 default: llvm_unreachable("Unknown loc info!");
2900 case CCValAssign::Full: break;
2901 case CCValAssign::SExt:
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 case CCValAssign::ZExt:
2905 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2907 case CCValAssign::AExt:
2908 if (RegVT.is128BitVector()) {
2909 // Special case: passing MMX values in XMM registers.
2910 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2911 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2912 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2914 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2916 case CCValAssign::BCvt:
2917 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2919 case CCValAssign::Indirect: {
2920 // Store the argument.
2921 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2922 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2923 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2924 MachinePointerInfo::getFixedStack(FI),
2931 if (VA.isRegLoc()) {
2932 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2933 if (isVarArg && IsWin64) {
2934 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2935 // shadow reg if callee is a varargs function.
2936 unsigned ShadowReg = 0;
2937 switch (VA.getLocReg()) {
2938 case X86::XMM0: ShadowReg = X86::RCX; break;
2939 case X86::XMM1: ShadowReg = X86::RDX; break;
2940 case X86::XMM2: ShadowReg = X86::R8; break;
2941 case X86::XMM3: ShadowReg = X86::R9; break;
2944 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2946 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2947 assert(VA.isMemLoc());
2948 if (!StackPtr.getNode())
2949 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2951 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2952 dl, DAG, VA, Flags));
2956 if (!MemOpChains.empty())
2957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2959 if (Subtarget->isPICStyleGOT()) {
2960 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2964 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2966 // If we are tail calling and generating PIC/GOT style code load the
2967 // address of the callee into ECX. The value in ecx is used as target of
2968 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2969 // for tail calls on PIC/GOT architectures. Normally we would just put the
2970 // address of GOT into ebx and then call target@PLT. But for tail calls
2971 // ebx would be restored (since ebx is callee saved) before jumping to the
2974 // Note: The actual moving to ECX is done further down.
2975 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2976 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2977 !G->getGlobal()->hasProtectedVisibility())
2978 Callee = LowerGlobalAddress(Callee, DAG);
2979 else if (isa<ExternalSymbolSDNode>(Callee))
2980 Callee = LowerExternalSymbol(Callee, DAG);
2984 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2985 // From AMD64 ABI document:
2986 // For calls that may call functions that use varargs or stdargs
2987 // (prototype-less calls or calls to functions containing ellipsis (...) in
2988 // the declaration) %al is used as hidden argument to specify the number
2989 // of SSE registers used. The contents of %al do not need to match exactly
2990 // the number of registers, but must be an ubound on the number of SSE
2991 // registers used and is in the range 0 - 8 inclusive.
2993 // Count the number of XMM registers allocated.
2994 static const MCPhysReg XMMArgRegs[] = {
2995 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2996 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2998 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2999 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3000 && "SSE registers cannot be used when SSE is disabled");
3002 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3003 DAG.getConstant(NumXMMRegs, MVT::i8)));
3006 if (isVarArg && IsMustTail) {
3007 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3008 for (const auto &F : Forwards) {
3009 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3010 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3014 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3015 // don't need this because the eligibility check rejects calls that require
3016 // shuffling arguments passed in memory.
3017 if (!IsSibcall && isTailCall) {
3018 // Force all the incoming stack arguments to be loaded from the stack
3019 // before any new outgoing arguments are stored to the stack, because the
3020 // outgoing stack slots may alias the incoming argument stack slots, and
3021 // the alias isn't otherwise explicit. This is slightly more conservative
3022 // than necessary, because it means that each store effectively depends
3023 // on every argument instead of just those arguments it would clobber.
3024 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3026 SmallVector<SDValue, 8> MemOpChains2;
3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3030 CCValAssign &VA = ArgLocs[i];
3033 assert(VA.isMemLoc());
3034 SDValue Arg = OutVals[i];
3035 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3036 // Skip inalloca arguments. They don't require any work.
3037 if (Flags.isInAlloca())
3039 // Create frame index.
3040 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3041 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3042 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3043 FIN = DAG.getFrameIndex(FI, getPointerTy());
3045 if (Flags.isByVal()) {
3046 // Copy relative to framepointer.
3047 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3048 if (!StackPtr.getNode())
3049 StackPtr = DAG.getCopyFromReg(Chain, dl,
3050 RegInfo->getStackRegister(),
3052 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3054 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3058 // Store relative to framepointer.
3059 MemOpChains2.push_back(
3060 DAG.getStore(ArgChain, dl, Arg, FIN,
3061 MachinePointerInfo::getFixedStack(FI),
3066 if (!MemOpChains2.empty())
3067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3069 // Store the return address to the appropriate stack slot.
3070 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3071 getPointerTy(), RegInfo->getSlotSize(),
3075 // Build a sequence of copy-to-reg nodes chained together with token chain
3076 // and flag operands which copy the outgoing args into registers.
3078 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3079 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3080 RegsToPass[i].second, InFlag);
3081 InFlag = Chain.getValue(1);
3084 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3085 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3086 // In the 64-bit large code model, we have to make all calls
3087 // through a register, since the call instruction's 32-bit
3088 // pc-relative offset may not be large enough to hold the whole
3090 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3091 // If the callee is a GlobalAddress node (quite common, every direct call
3092 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3095 // We should use extra load for direct calls to dllimported functions in
3097 const GlobalValue *GV = G->getGlobal();
3098 if (!GV->hasDLLImportStorageClass()) {
3099 unsigned char OpFlags = 0;
3100 bool ExtraLoad = false;
3101 unsigned WrapperKind = ISD::DELETED_NODE;
3103 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3104 // external symbols most go through the PLT in PIC mode. If the symbol
3105 // has hidden or protected visibility, or if it is static or local, then
3106 // we don't need to use the PLT - we can directly call it.
3107 if (Subtarget->isTargetELF() &&
3108 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3109 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3110 OpFlags = X86II::MO_PLT;
3111 } else if (Subtarget->isPICStyleStubAny() &&
3112 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3119 } else if (Subtarget->isPICStyleRIPRel() &&
3120 isa<Function>(GV) &&
3121 cast<Function>(GV)->getAttributes().
3122 hasAttribute(AttributeSet::FunctionIndex,
3123 Attribute::NonLazyBind)) {
3124 // If the function is marked as non-lazy, generate an indirect call
3125 // which loads from the GOT directly. This avoids runtime overhead
3126 // at the cost of eager binding (and one extra byte of encoding).
3127 OpFlags = X86II::MO_GOTPCREL;
3128 WrapperKind = X86ISD::WrapperRIP;
3132 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3133 G->getOffset(), OpFlags);
3135 // Add a wrapper if needed.
3136 if (WrapperKind != ISD::DELETED_NODE)
3137 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3138 // Add extra indirection if needed.
3140 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3141 MachinePointerInfo::getGOT(),
3142 false, false, false, 0);
3144 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3145 unsigned char OpFlags = 0;
3147 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3148 // external symbols should go through the PLT.
3149 if (Subtarget->isTargetELF() &&
3150 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3151 OpFlags = X86II::MO_PLT;
3152 } else if (Subtarget->isPICStyleStubAny() &&
3153 (!Subtarget->getTargetTriple().isMacOSX() ||
3154 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3155 // PC-relative references to external symbols should go through $stub,
3156 // unless we're building with the leopard linker or later, which
3157 // automatically synthesizes these stubs.
3158 OpFlags = X86II::MO_DARWIN_STUB;
3161 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3163 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3164 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3165 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3168 // Returns a chain & a flag for retval copy to use.
3169 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3170 SmallVector<SDValue, 8> Ops;
3172 if (!IsSibcall && isTailCall) {
3173 Chain = DAG.getCALLSEQ_END(Chain,
3174 DAG.getIntPtrConstant(NumBytesToPop, true),
3175 DAG.getIntPtrConstant(0, true), InFlag, dl);
3176 InFlag = Chain.getValue(1);
3179 Ops.push_back(Chain);
3180 Ops.push_back(Callee);
3183 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3185 // Add argument registers to the end of the list so that they are known live
3187 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3188 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3189 RegsToPass[i].second.getValueType()));
3191 // Add a register mask operand representing the call-preserved registers.
3192 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3193 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3194 assert(Mask && "Missing call preserved mask for calling convention");
3195 Ops.push_back(DAG.getRegisterMask(Mask));
3197 if (InFlag.getNode())
3198 Ops.push_back(InFlag);
3202 //// If this is the first return lowered for this function, add the regs
3203 //// to the liveout set for the function.
3204 // This isn't right, although it's probably harmless on x86; liveouts
3205 // should be computed from returns not tail calls. Consider a void
3206 // function making a tail call to a function returning int.
3207 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3210 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3211 InFlag = Chain.getValue(1);
3213 // Create the CALLSEQ_END node.
3214 unsigned NumBytesForCalleeToPop;
3215 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3216 DAG.getTarget().Options.GuaranteedTailCallOpt))
3217 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3218 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3219 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3220 SR == StackStructReturn)
3221 // If this is a call to a struct-return function, the callee
3222 // pops the hidden struct pointer, so we have to push it back.
3223 // This is common for Darwin/X86, Linux & Mingw32 targets.
3224 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3225 NumBytesForCalleeToPop = 4;
3227 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3229 // Returns a flag for retval copy to use.
3231 Chain = DAG.getCALLSEQ_END(Chain,
3232 DAG.getIntPtrConstant(NumBytesToPop, true),
3233 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3236 InFlag = Chain.getValue(1);
3239 // Handle result values, copying them out of physregs into vregs that we
3241 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3242 Ins, dl, DAG, InVals);
3245 //===----------------------------------------------------------------------===//
3246 // Fast Calling Convention (tail call) implementation
3247 //===----------------------------------------------------------------------===//
3249 // Like std call, callee cleans arguments, convention except that ECX is
3250 // reserved for storing the tail called function address. Only 2 registers are
3251 // free for argument passing (inreg). Tail call optimization is performed
3253 // * tailcallopt is enabled
3254 // * caller/callee are fastcc
3255 // On X86_64 architecture with GOT-style position independent code only local
3256 // (within module) calls are supported at the moment.
3257 // To keep the stack aligned according to platform abi the function
3258 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3259 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3260 // If a tail called function callee has more arguments than the caller the
3261 // caller needs to make sure that there is room to move the RETADDR to. This is
3262 // achieved by reserving an area the size of the argument delta right after the
3263 // original RETADDR, but before the saved framepointer or the spilled registers
3264 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3276 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3277 /// for a 16 byte align requirement.
3279 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3280 SelectionDAG& DAG) const {
3281 MachineFunction &MF = DAG.getMachineFunction();
3282 const TargetMachine &TM = MF.getTarget();
3283 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3284 TM.getSubtargetImpl()->getRegisterInfo());
3285 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3286 unsigned StackAlignment = TFI.getStackAlignment();
3287 uint64_t AlignMask = StackAlignment - 1;
3288 int64_t Offset = StackSize;
3289 unsigned SlotSize = RegInfo->getSlotSize();
3290 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3291 // Number smaller than 12 so just add the difference.
3292 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3294 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3295 Offset = ((~AlignMask) & Offset) + StackAlignment +
3296 (StackAlignment-SlotSize);
3301 /// MatchingStackOffset - Return true if the given stack call argument is
3302 /// already available in the same position (relatively) of the caller's
3303 /// incoming argument stack.
3305 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3306 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3307 const X86InstrInfo *TII) {
3308 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3310 if (Arg.getOpcode() == ISD::CopyFromReg) {
3311 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3312 if (!TargetRegisterInfo::isVirtualRegister(VR))
3314 MachineInstr *Def = MRI->getVRegDef(VR);
3317 if (!Flags.isByVal()) {
3318 if (!TII->isLoadFromStackSlot(Def, FI))
3321 unsigned Opcode = Def->getOpcode();
3322 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3323 Def->getOperand(1).isFI()) {
3324 FI = Def->getOperand(1).getIndex();
3325 Bytes = Flags.getByValSize();
3329 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3330 if (Flags.isByVal())
3331 // ByVal argument is passed in as a pointer but it's now being
3332 // dereferenced. e.g.
3333 // define @foo(%struct.X* %A) {
3334 // tail call @bar(%struct.X* byval %A)
3337 SDValue Ptr = Ld->getBasePtr();
3338 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3341 FI = FINode->getIndex();
3342 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3343 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3344 FI = FINode->getIndex();
3345 Bytes = Flags.getByValSize();
3349 assert(FI != INT_MAX);
3350 if (!MFI->isFixedObjectIndex(FI))
3352 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3355 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3356 /// for tail call optimization. Targets which want to do tail call
3357 /// optimization should implement this function.
3359 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3360 CallingConv::ID CalleeCC,
3362 bool isCalleeStructRet,
3363 bool isCallerStructRet,
3365 const SmallVectorImpl<ISD::OutputArg> &Outs,
3366 const SmallVectorImpl<SDValue> &OutVals,
3367 const SmallVectorImpl<ISD::InputArg> &Ins,
3368 SelectionDAG &DAG) const {
3369 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3372 // If -tailcallopt is specified, make fastcc functions tail-callable.
3373 const MachineFunction &MF = DAG.getMachineFunction();
3374 const Function *CallerF = MF.getFunction();
3376 // If the function return type is x86_fp80 and the callee return type is not,
3377 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3378 // perform a tailcall optimization here.
3379 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3382 CallingConv::ID CallerCC = CallerF->getCallingConv();
3383 bool CCMatch = CallerCC == CalleeCC;
3384 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3385 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3387 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3388 if (IsTailCallConvention(CalleeCC) && CCMatch)
3393 // Look for obvious safe cases to perform tail call optimization that do not
3394 // require ABI changes. This is what gcc calls sibcall.
3396 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3397 // emit a special epilogue.
3398 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3399 DAG.getSubtarget().getRegisterInfo());
3400 if (RegInfo->needsStackRealignment(MF))
3403 // Also avoid sibcall optimization if either caller or callee uses struct
3404 // return semantics.
3405 if (isCalleeStructRet || isCallerStructRet)
3408 // An stdcall/thiscall caller is expected to clean up its arguments; the
3409 // callee isn't going to do that.
3410 // FIXME: this is more restrictive than needed. We could produce a tailcall
3411 // when the stack adjustment matches. For example, with a thiscall that takes
3412 // only one argument.
3413 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3414 CallerCC == CallingConv::X86_ThisCall))
3417 // Do not sibcall optimize vararg calls unless all arguments are passed via
3419 if (isVarArg && !Outs.empty()) {
3421 // Optimizing for varargs on Win64 is unlikely to be safe without
3422 // additional testing.
3423 if (IsCalleeWin64 || IsCallerWin64)
3426 SmallVector<CCValAssign, 16> ArgLocs;
3427 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3430 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3432 if (!ArgLocs[i].isRegLoc())
3436 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3437 // stack. Therefore, if it's not used by the call it is not safe to optimize
3438 // this into a sibcall.
3439 bool Unused = false;
3440 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3447 SmallVector<CCValAssign, 16> RVLocs;
3448 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3450 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3451 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3452 CCValAssign &VA = RVLocs[i];
3453 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3458 // If the calling conventions do not match, then we'd better make sure the
3459 // results are returned in the same way as what the caller expects.
3461 SmallVector<CCValAssign, 16> RVLocs1;
3462 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3464 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3466 SmallVector<CCValAssign, 16> RVLocs2;
3467 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3469 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3471 if (RVLocs1.size() != RVLocs2.size())
3473 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3474 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3476 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3478 if (RVLocs1[i].isRegLoc()) {
3479 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3482 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3488 // If the callee takes no arguments then go on to check the results of the
3490 if (!Outs.empty()) {
3491 // Check if stack adjustment is needed. For now, do not do this if any
3492 // argument is passed on the stack.
3493 SmallVector<CCValAssign, 16> ArgLocs;
3494 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3497 // Allocate shadow area for Win64
3499 CCInfo.AllocateStack(32, 8);
3501 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3502 if (CCInfo.getNextStackOffset()) {
3503 MachineFunction &MF = DAG.getMachineFunction();
3504 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3507 // Check if the arguments are already laid out in the right way as
3508 // the caller's fixed stack objects.
3509 MachineFrameInfo *MFI = MF.getFrameInfo();
3510 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3511 const X86InstrInfo *TII =
3512 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3513 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3514 CCValAssign &VA = ArgLocs[i];
3515 SDValue Arg = OutVals[i];
3516 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3517 if (VA.getLocInfo() == CCValAssign::Indirect)
3519 if (!VA.isRegLoc()) {
3520 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3527 // If the tailcall address may be in a register, then make sure it's
3528 // possible to register allocate for it. In 32-bit, the call address can
3529 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3530 // callee-saved registers are restored. These happen to be the same
3531 // registers used to pass 'inreg' arguments so watch out for those.
3532 if (!Subtarget->is64Bit() &&
3533 ((!isa<GlobalAddressSDNode>(Callee) &&
3534 !isa<ExternalSymbolSDNode>(Callee)) ||
3535 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3536 unsigned NumInRegs = 0;
3537 // In PIC we need an extra register to formulate the address computation
3539 unsigned MaxInRegs =
3540 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3542 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3543 CCValAssign &VA = ArgLocs[i];
3546 unsigned Reg = VA.getLocReg();
3549 case X86::EAX: case X86::EDX: case X86::ECX:
3550 if (++NumInRegs == MaxInRegs)
3562 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3563 const TargetLibraryInfo *libInfo) const {
3564 return X86::createFastISel(funcInfo, libInfo);
3567 //===----------------------------------------------------------------------===//
3568 // Other Lowering Hooks
3569 //===----------------------------------------------------------------------===//
3571 static bool MayFoldLoad(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3575 static bool MayFoldIntoStore(SDValue Op) {
3576 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3579 static bool isTargetShuffle(unsigned Opcode) {
3581 default: return false;
3582 case X86ISD::BLENDI:
3583 case X86ISD::PSHUFB:
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3588 case X86ISD::PALIGNR:
3589 case X86ISD::MOVLHPS:
3590 case X86ISD::MOVLHPD:
3591 case X86ISD::MOVHLPS:
3592 case X86ISD::MOVLPS:
3593 case X86ISD::MOVLPD:
3594 case X86ISD::MOVSHDUP:
3595 case X86ISD::MOVSLDUP:
3596 case X86ISD::MOVDDUP:
3599 case X86ISD::UNPCKL:
3600 case X86ISD::UNPCKH:
3601 case X86ISD::VPERMILPI:
3602 case X86ISD::VPERM2X128:
3603 case X86ISD::VPERMI:
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVSHDUP:
3613 case X86ISD::MOVSLDUP:
3614 case X86ISD::MOVDDUP:
3615 return DAG.getNode(Opc, dl, VT, V1);
3619 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3620 SDValue V1, unsigned TargetMask,
3621 SelectionDAG &DAG) {
3623 default: llvm_unreachable("Unknown x86 shuffle node");
3624 case X86ISD::PSHUFD:
3625 case X86ISD::PSHUFHW:
3626 case X86ISD::PSHUFLW:
3627 case X86ISD::VPERMILPI:
3628 case X86ISD::VPERMI:
3629 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3633 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3634 SDValue V1, SDValue V2, unsigned TargetMask,
3635 SelectionDAG &DAG) {
3637 default: llvm_unreachable("Unknown x86 shuffle node");
3638 case X86ISD::PALIGNR:
3639 case X86ISD::VALIGN:
3641 case X86ISD::VPERM2X128:
3642 return DAG.getNode(Opc, dl, VT, V1, V2,
3643 DAG.getConstant(TargetMask, MVT::i8));
3647 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3648 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3650 default: llvm_unreachable("Unknown x86 shuffle node");
3651 case X86ISD::MOVLHPS:
3652 case X86ISD::MOVLHPD:
3653 case X86ISD::MOVHLPS:
3654 case X86ISD::MOVLPS:
3655 case X86ISD::MOVLPD:
3658 case X86ISD::UNPCKL:
3659 case X86ISD::UNPCKH:
3660 return DAG.getNode(Opc, dl, VT, V1, V2);
3664 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3665 MachineFunction &MF = DAG.getMachineFunction();
3666 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3667 DAG.getSubtarget().getRegisterInfo());
3668 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3669 int ReturnAddrIndex = FuncInfo->getRAIndex();
3671 if (ReturnAddrIndex == 0) {
3672 // Set up a frame object for the return address.
3673 unsigned SlotSize = RegInfo->getSlotSize();
3674 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3677 FuncInfo->setRAIndex(ReturnAddrIndex);
3680 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3683 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3684 bool hasSymbolicDisplacement) {
3685 // Offset should fit into 32 bit immediate field.
3686 if (!isInt<32>(Offset))
3689 // If we don't have a symbolic displacement - we don't have any extra
3691 if (!hasSymbolicDisplacement)
3694 // FIXME: Some tweaks might be needed for medium code model.
3695 if (M != CodeModel::Small && M != CodeModel::Kernel)
3698 // For small code model we assume that latest object is 16MB before end of 31
3699 // bits boundary. We may also accept pretty large negative constants knowing
3700 // that all objects are in the positive half of address space.
3701 if (M == CodeModel::Small && Offset < 16*1024*1024)
3704 // For kernel code model we know that all object resist in the negative half
3705 // of 32bits address space. We may not accept negative offsets, since they may
3706 // be just off and we may accept pretty large positive ones.
3707 if (M == CodeModel::Kernel && Offset >= 0)
3713 /// isCalleePop - Determines whether the callee is required to pop its
3714 /// own arguments. Callee pop is necessary to support tail calls.
3715 bool X86::isCalleePop(CallingConv::ID CallingConv,
3716 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3717 switch (CallingConv) {
3720 case CallingConv::X86_StdCall:
3721 case CallingConv::X86_FastCall:
3722 case CallingConv::X86_ThisCall:
3724 case CallingConv::Fast:
3725 case CallingConv::GHC:
3726 case CallingConv::HiPE:
3733 /// \brief Return true if the condition is an unsigned comparison operation.
3734 static bool isX86CCUnsigned(unsigned X86CC) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case X86::COND_E: return true;
3738 case X86::COND_G: return false;
3739 case X86::COND_GE: return false;
3740 case X86::COND_L: return false;
3741 case X86::COND_LE: return false;
3742 case X86::COND_NE: return true;
3743 case X86::COND_B: return true;
3744 case X86::COND_A: return true;
3745 case X86::COND_BE: return true;
3746 case X86::COND_AE: return true;
3748 llvm_unreachable("covered switch fell through?!");
3751 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3752 /// specific condition code, returning the condition code and the LHS/RHS of the
3753 /// comparison to make.
3754 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3755 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3757 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3758 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3759 // X > -1 -> X == 0, jump !sign.
3760 RHS = DAG.getConstant(0, RHS.getValueType());
3761 return X86::COND_NS;
3763 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3764 // X < 0 -> X == 0, jump on sign.
3767 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3769 RHS = DAG.getConstant(0, RHS.getValueType());
3770 return X86::COND_LE;
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Invalid integer condition!");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETGT: return X86::COND_G;
3778 case ISD::SETGE: return X86::COND_GE;
3779 case ISD::SETLT: return X86::COND_L;
3780 case ISD::SETLE: return X86::COND_LE;
3781 case ISD::SETNE: return X86::COND_NE;
3782 case ISD::SETULT: return X86::COND_B;
3783 case ISD::SETUGT: return X86::COND_A;
3784 case ISD::SETULE: return X86::COND_BE;
3785 case ISD::SETUGE: return X86::COND_AE;
3789 // First determine if it is required or is profitable to flip the operands.
3791 // If LHS is a foldable load, but RHS is not, flip the condition.
3792 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3793 !ISD::isNON_EXTLoad(RHS.getNode())) {
3794 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3795 std::swap(LHS, RHS);
3798 switch (SetCCOpcode) {
3804 std::swap(LHS, RHS);
3808 // On a floating point condition, the flags are set as follows:
3810 // 0 | 0 | 0 | X > Y
3811 // 0 | 0 | 1 | X < Y
3812 // 1 | 0 | 0 | X == Y
3813 // 1 | 1 | 1 | unordered
3814 switch (SetCCOpcode) {
3815 default: llvm_unreachable("Condcode should be pre-legalized away");
3817 case ISD::SETEQ: return X86::COND_E;
3818 case ISD::SETOLT: // flipped
3820 case ISD::SETGT: return X86::COND_A;
3821 case ISD::SETOLE: // flipped
3823 case ISD::SETGE: return X86::COND_AE;
3824 case ISD::SETUGT: // flipped
3826 case ISD::SETLT: return X86::COND_B;
3827 case ISD::SETUGE: // flipped
3829 case ISD::SETLE: return X86::COND_BE;
3831 case ISD::SETNE: return X86::COND_NE;
3832 case ISD::SETUO: return X86::COND_P;
3833 case ISD::SETO: return X86::COND_NP;
3835 case ISD::SETUNE: return X86::COND_INVALID;
3839 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3840 /// code. Current x86 isa includes the following FP cmov instructions:
3841 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3842 static bool hasFPCMov(unsigned X86CC) {
3858 /// isFPImmLegal - Returns true if the target can instruction select the
3859 /// specified FP immediate natively. If false, the legalizer will
3860 /// materialize the FP immediate as a load from a constant pool.
3861 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3862 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3863 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3869 /// \brief Returns true if it is beneficial to convert a load of a constant
3870 /// to just the constant itself.
3871 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3873 assert(Ty->isIntegerTy());
3875 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3876 if (BitSize == 0 || BitSize > 64)
3881 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3882 unsigned Index) const {
3883 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3886 return (Index == 0 || Index == ResVT.getVectorNumElements());
3889 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3890 /// the specified range (L, H].
3891 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3892 return (Val < 0) || (Val >= Low && Val < Hi);
3895 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3896 /// specified value.
3897 static bool isUndefOrEqual(int Val, int CmpVal) {
3898 return (Val < 0 || Val == CmpVal);
3901 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3902 /// from position Pos and ending in Pos+Size, falls within the specified
3903 /// sequential range (L, L+Pos]. or is undef.
3904 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3905 unsigned Pos, unsigned Size, int Low) {
3906 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3907 if (!isUndefOrEqual(Mask[i], Low))
3912 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3913 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3914 /// operand - by default will match for first operand.
3915 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3916 bool TestSecondOperand = false) {
3917 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3918 VT != MVT::v2f64 && VT != MVT::v2i64)
3921 unsigned NumElems = VT.getVectorNumElements();
3922 unsigned Lo = TestSecondOperand ? NumElems : 0;
3923 unsigned Hi = Lo + NumElems;
3925 for (unsigned i = 0; i < NumElems; ++i)
3926 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3932 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3933 /// is suitable for input to PSHUFHW.
3934 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3935 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3938 // Lower quadword copied in order or undef.
3939 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3942 // Upper quadword shuffled.
3943 for (unsigned i = 4; i != 8; ++i)
3944 if (!isUndefOrInRange(Mask[i], 4, 8))
3947 if (VT == MVT::v16i16) {
3948 // Lower quadword copied in order or undef.
3949 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3952 // Upper quadword shuffled.
3953 for (unsigned i = 12; i != 16; ++i)
3954 if (!isUndefOrInRange(Mask[i], 12, 16))
3961 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3962 /// is suitable for input to PSHUFLW.
3963 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3964 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3967 // Upper quadword copied in order.
3968 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3971 // Lower quadword shuffled.
3972 for (unsigned i = 0; i != 4; ++i)
3973 if (!isUndefOrInRange(Mask[i], 0, 4))
3976 if (VT == MVT::v16i16) {
3977 // Upper quadword copied in order.
3978 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3981 // Lower quadword shuffled.
3982 for (unsigned i = 8; i != 12; ++i)
3983 if (!isUndefOrInRange(Mask[i], 8, 12))
3990 /// \brief Return true if the mask specifies a shuffle of elements that is
3991 /// suitable for input to intralane (palignr) or interlane (valign) vector
3993 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3994 unsigned NumElts = VT.getVectorNumElements();
3995 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3996 unsigned NumLaneElts = NumElts/NumLanes;
3998 // Do not handle 64-bit element shuffles with palignr.
3999 if (NumLaneElts == 2)
4002 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4004 for (i = 0; i != NumLaneElts; ++i) {
4009 // Lane is all undef, go to next lane
4010 if (i == NumLaneElts)
4013 int Start = Mask[i+l];
4015 // Make sure its in this lane in one of the sources
4016 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4017 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4020 // If not lane 0, then we must match lane 0
4021 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4024 // Correct second source to be contiguous with first source
4025 if (Start >= (int)NumElts)
4026 Start -= NumElts - NumLaneElts;
4028 // Make sure we're shifting in the right direction.
4029 if (Start <= (int)(i+l))
4034 // Check the rest of the elements to see if they are consecutive.
4035 for (++i; i != NumLaneElts; ++i) {
4036 int Idx = Mask[i+l];
4038 // Make sure its in this lane
4039 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4040 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4043 // If not lane 0, then we must match lane 0
4044 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4047 if (Idx >= (int)NumElts)
4048 Idx -= NumElts - NumLaneElts;
4050 if (!isUndefOrEqual(Idx, Start+i))
4059 /// \brief Return true if the node specifies a shuffle of elements that is
4060 /// suitable for input to PALIGNR.
4061 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4062 const X86Subtarget *Subtarget) {
4063 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4064 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4065 VT.is512BitVector())
4066 // FIXME: Add AVX512BW.
4069 return isAlignrMask(Mask, VT, false);
4072 /// \brief Return true if the node specifies a shuffle of elements that is
4073 /// suitable for input to VALIGN.
4074 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4075 const X86Subtarget *Subtarget) {
4076 // FIXME: Add AVX512VL.
4077 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4079 return isAlignrMask(Mask, VT, true);
4082 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4083 /// the two vector operands have swapped position.
4084 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4085 unsigned NumElems) {
4086 for (unsigned i = 0; i != NumElems; ++i) {
4090 else if (idx < (int)NumElems)
4091 Mask[i] = idx + NumElems;
4093 Mask[i] = idx - NumElems;
4097 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4098 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4099 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4100 /// reverse of what x86 shuffles want.
4101 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4103 unsigned NumElems = VT.getVectorNumElements();
4104 unsigned NumLanes = VT.getSizeInBits()/128;
4105 unsigned NumLaneElems = NumElems/NumLanes;
4107 if (NumLaneElems != 2 && NumLaneElems != 4)
4110 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4111 bool symetricMaskRequired =
4112 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4114 // VSHUFPSY divides the resulting vector into 4 chunks.
4115 // The sources are also splitted into 4 chunks, and each destination
4116 // chunk must come from a different source chunk.
4118 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4119 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4121 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4122 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4124 // VSHUFPDY divides the resulting vector into 4 chunks.
4125 // The sources are also splitted into 4 chunks, and each destination
4126 // chunk must come from a different source chunk.
4128 // SRC1 => X3 X2 X1 X0
4129 // SRC2 => Y3 Y2 Y1 Y0
4131 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4133 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4134 unsigned HalfLaneElems = NumLaneElems/2;
4135 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4136 for (unsigned i = 0; i != NumLaneElems; ++i) {
4137 int Idx = Mask[i+l];
4138 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4139 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4141 // For VSHUFPSY, the mask of the second half must be the same as the
4142 // first but with the appropriate offsets. This works in the same way as
4143 // VPERMILPS works with masks.
4144 if (!symetricMaskRequired || Idx < 0)
4146 if (MaskVal[i] < 0) {
4147 MaskVal[i] = Idx - l;
4150 if ((signed)(Idx - l) != MaskVal[i])
4158 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4160 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4169 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4170 return isUndefOrEqual(Mask[0], 6) &&
4171 isUndefOrEqual(Mask[1], 7) &&
4172 isUndefOrEqual(Mask[2], 2) &&
4173 isUndefOrEqual(Mask[3], 3);
4176 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4177 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4179 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4180 if (!VT.is128BitVector())
4183 unsigned NumElems = VT.getVectorNumElements();
4188 return isUndefOrEqual(Mask[0], 2) &&
4189 isUndefOrEqual(Mask[1], 3) &&
4190 isUndefOrEqual(Mask[2], 2) &&
4191 isUndefOrEqual(Mask[3], 3);
4194 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4195 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4196 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4197 if (!VT.is128BitVector())
4200 unsigned NumElems = VT.getVectorNumElements();
4202 if (NumElems != 2 && NumElems != 4)
4205 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4206 if (!isUndefOrEqual(Mask[i], i + NumElems))
4209 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4210 if (!isUndefOrEqual(Mask[i], i))
4216 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4217 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4218 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4219 if (!VT.is128BitVector())
4222 unsigned NumElems = VT.getVectorNumElements();
4224 if (NumElems != 2 && NumElems != 4)
4227 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4228 if (!isUndefOrEqual(Mask[i], i))
4231 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4232 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4238 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4239 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4240 /// i. e: If all but one element come from the same vector.
4241 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4242 // TODO: Deal with AVX's VINSERTPS
4243 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4246 unsigned CorrectPosV1 = 0;
4247 unsigned CorrectPosV2 = 0;
4248 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4249 if (Mask[i] == -1) {
4257 else if (Mask[i] == i + 4)
4261 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4262 // We have 3 elements (undefs count as elements from any vector) from one
4263 // vector, and one from another.
4270 // Some special combinations that can be optimized.
4273 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4274 SelectionDAG &DAG) {
4275 MVT VT = SVOp->getSimpleValueType(0);
4278 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4281 ArrayRef<int> Mask = SVOp->getMask();
4283 // These are the special masks that may be optimized.
4284 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4285 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4286 bool MatchEvenMask = true;
4287 bool MatchOddMask = true;
4288 for (int i=0; i<8; ++i) {
4289 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4290 MatchEvenMask = false;
4291 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4292 MatchOddMask = false;
4295 if (!MatchEvenMask && !MatchOddMask)
4298 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4300 SDValue Op0 = SVOp->getOperand(0);
4301 SDValue Op1 = SVOp->getOperand(1);
4303 if (MatchEvenMask) {
4304 // Shift the second operand right to 32 bits.
4305 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4306 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4308 // Shift the first operand left to 32 bits.
4309 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4310 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4312 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4313 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4316 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4317 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4318 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4319 bool HasInt256, bool V2IsSplat = false) {
4321 assert(VT.getSizeInBits() >= 128 &&
4322 "Unsupported vector type for unpckl");
4324 unsigned NumElts = VT.getVectorNumElements();
4325 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4326 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4329 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4330 "Unsupported vector type for unpckh");
4332 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4333 unsigned NumLanes = VT.getSizeInBits()/128;
4334 unsigned NumLaneElts = NumElts/NumLanes;
4336 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4337 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4338 int BitI = Mask[l+i];
4339 int BitI1 = Mask[l+i+1];
4340 if (!isUndefOrEqual(BitI, j))
4343 if (!isUndefOrEqual(BitI1, NumElts))
4346 if (!isUndefOrEqual(BitI1, j + NumElts))
4355 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4356 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4357 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4358 bool HasInt256, bool V2IsSplat = false) {
4359 assert(VT.getSizeInBits() >= 128 &&
4360 "Unsupported vector type for unpckh");
4362 unsigned NumElts = VT.getVectorNumElements();
4363 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4364 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4367 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4368 "Unsupported vector type for unpckh");
4370 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4371 unsigned NumLanes = VT.getSizeInBits()/128;
4372 unsigned NumLaneElts = NumElts/NumLanes;
4374 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4375 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4376 int BitI = Mask[l+i];
4377 int BitI1 = Mask[l+i+1];
4378 if (!isUndefOrEqual(BitI, j))
4381 if (isUndefOrEqual(BitI1, NumElts))
4384 if (!isUndefOrEqual(BitI1, j+NumElts))
4392 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4393 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4395 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4396 unsigned NumElts = VT.getVectorNumElements();
4397 bool Is256BitVec = VT.is256BitVector();
4399 if (VT.is512BitVector())
4401 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4402 "Unsupported vector type for unpckh");
4404 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4405 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4408 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4409 // FIXME: Need a better way to get rid of this, there's no latency difference
4410 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4411 // the former later. We should also remove the "_undef" special mask.
4412 if (NumElts == 4 && Is256BitVec)
4415 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4416 // independently on 128-bit lanes.
4417 unsigned NumLanes = VT.getSizeInBits()/128;
4418 unsigned NumLaneElts = NumElts/NumLanes;
4420 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4421 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4422 int BitI = Mask[l+i];
4423 int BitI1 = Mask[l+i+1];
4425 if (!isUndefOrEqual(BitI, j))
4427 if (!isUndefOrEqual(BitI1, j))
4435 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4436 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4438 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4439 unsigned NumElts = VT.getVectorNumElements();
4441 if (VT.is512BitVector())
4444 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4445 "Unsupported vector type for unpckh");
4447 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4448 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4451 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4452 // independently on 128-bit lanes.
4453 unsigned NumLanes = VT.getSizeInBits()/128;
4454 unsigned NumLaneElts = NumElts/NumLanes;
4456 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4457 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4458 int BitI = Mask[l+i];
4459 int BitI1 = Mask[l+i+1];
4460 if (!isUndefOrEqual(BitI, j))
4462 if (!isUndefOrEqual(BitI1, j))
4469 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4470 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4471 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4472 if (!VT.is512BitVector())
4475 unsigned NumElts = VT.getVectorNumElements();
4476 unsigned HalfSize = NumElts/2;
4477 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4478 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4483 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4484 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4492 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4493 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4494 /// MOVSD, and MOVD, i.e. setting the lowest element.
4495 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4496 if (VT.getVectorElementType().getSizeInBits() < 32)
4498 if (!VT.is128BitVector())
4501 unsigned NumElts = VT.getVectorNumElements();
4503 if (!isUndefOrEqual(Mask[0], NumElts))
4506 for (unsigned i = 1; i != NumElts; ++i)
4507 if (!isUndefOrEqual(Mask[i], i))
4513 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4514 /// as permutations between 128-bit chunks or halves. As an example: this
4516 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4517 /// The first half comes from the second half of V1 and the second half from the
4518 /// the second half of V2.
4519 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4520 if (!HasFp256 || !VT.is256BitVector())
4523 // The shuffle result is divided into half A and half B. In total the two
4524 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4525 // B must come from C, D, E or F.
4526 unsigned HalfSize = VT.getVectorNumElements()/2;
4527 bool MatchA = false, MatchB = false;
4529 // Check if A comes from one of C, D, E, F.
4530 for (unsigned Half = 0; Half != 4; ++Half) {
4531 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4537 // Check if B comes from one of C, D, E, F.
4538 for (unsigned Half = 0; Half != 4; ++Half) {
4539 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4545 return MatchA && MatchB;
4548 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4549 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4550 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4551 MVT VT = SVOp->getSimpleValueType(0);
4553 unsigned HalfSize = VT.getVectorNumElements()/2;
4555 unsigned FstHalf = 0, SndHalf = 0;
4556 for (unsigned i = 0; i < HalfSize; ++i) {
4557 if (SVOp->getMaskElt(i) > 0) {
4558 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4562 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4563 if (SVOp->getMaskElt(i) > 0) {
4564 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4569 return (FstHalf | (SndHalf << 4));
4572 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4573 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4574 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4578 unsigned NumElts = VT.getVectorNumElements();
4580 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4581 for (unsigned i = 0; i != NumElts; ++i) {
4584 Imm8 |= Mask[i] << (i*2);
4589 unsigned LaneSize = 4;
4590 SmallVector<int, 4> MaskVal(LaneSize, -1);
4592 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4593 for (unsigned i = 0; i != LaneSize; ++i) {
4594 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4598 if (MaskVal[i] < 0) {
4599 MaskVal[i] = Mask[i+l] - l;
4600 Imm8 |= MaskVal[i] << (i*2);
4603 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4610 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4611 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4612 /// Note that VPERMIL mask matching is different depending whether theunderlying
4613 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4614 /// to the same elements of the low, but to the higher half of the source.
4615 /// In VPERMILPD the two lanes could be shuffled independently of each other
4616 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4617 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4618 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4619 if (VT.getSizeInBits() < 256 || EltSize < 32)
4621 bool symetricMaskRequired = (EltSize == 32);
4622 unsigned NumElts = VT.getVectorNumElements();
4624 unsigned NumLanes = VT.getSizeInBits()/128;
4625 unsigned LaneSize = NumElts/NumLanes;
4626 // 2 or 4 elements in one lane
4628 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4629 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4630 for (unsigned i = 0; i != LaneSize; ++i) {
4631 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4633 if (symetricMaskRequired) {
4634 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4635 ExpectedMaskVal[i] = Mask[i+l] - l;
4638 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4646 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4647 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4648 /// element of vector 2 and the other elements to come from vector 1 in order.
4649 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4650 bool V2IsSplat = false, bool V2IsUndef = false) {
4651 if (!VT.is128BitVector())
4654 unsigned NumOps = VT.getVectorNumElements();
4655 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4658 if (!isUndefOrEqual(Mask[0], 0))
4661 for (unsigned i = 1; i != NumOps; ++i)
4662 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4663 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4664 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4670 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4671 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4672 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4673 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4674 const X86Subtarget *Subtarget) {
4675 if (!Subtarget->hasSSE3())
4678 unsigned NumElems = VT.getVectorNumElements();
4680 if ((VT.is128BitVector() && NumElems != 4) ||
4681 (VT.is256BitVector() && NumElems != 8) ||
4682 (VT.is512BitVector() && NumElems != 16))
4685 // "i+1" is the value the indexed mask element must have
4686 for (unsigned i = 0; i != NumElems; i += 2)
4687 if (!isUndefOrEqual(Mask[i], i+1) ||
4688 !isUndefOrEqual(Mask[i+1], i+1))
4694 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4695 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4696 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4697 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4698 const X86Subtarget *Subtarget) {
4699 if (!Subtarget->hasSSE3())
4702 unsigned NumElems = VT.getVectorNumElements();
4704 if ((VT.is128BitVector() && NumElems != 4) ||
4705 (VT.is256BitVector() && NumElems != 8) ||
4706 (VT.is512BitVector() && NumElems != 16))
4709 // "i" is the value the indexed mask element must have
4710 for (unsigned i = 0; i != NumElems; i += 2)
4711 if (!isUndefOrEqual(Mask[i], i) ||
4712 !isUndefOrEqual(Mask[i+1], i))
4718 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4719 /// specifies a shuffle of elements that is suitable for input to 256-bit
4720 /// version of MOVDDUP.
4721 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4722 if (!HasFp256 || !VT.is256BitVector())
4725 unsigned NumElts = VT.getVectorNumElements();
4729 for (unsigned i = 0; i != NumElts/2; ++i)
4730 if (!isUndefOrEqual(Mask[i], 0))
4732 for (unsigned i = NumElts/2; i != NumElts; ++i)
4733 if (!isUndefOrEqual(Mask[i], NumElts/2))
4738 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4739 /// specifies a shuffle of elements that is suitable for input to 128-bit
4740 /// version of MOVDDUP.
4741 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4742 if (!VT.is128BitVector())
4745 unsigned e = VT.getVectorNumElements() / 2;
4746 for (unsigned i = 0; i != e; ++i)
4747 if (!isUndefOrEqual(Mask[i], i))
4749 for (unsigned i = 0; i != e; ++i)
4750 if (!isUndefOrEqual(Mask[e+i], i))
4755 /// isVEXTRACTIndex - Return true if the specified
4756 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4757 /// suitable for instruction that extract 128 or 256 bit vectors
4758 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4759 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4760 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4763 // The index should be aligned on a vecWidth-bit boundary.
4765 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4767 MVT VT = N->getSimpleValueType(0);
4768 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4769 bool Result = (Index * ElSize) % vecWidth == 0;
4774 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4775 /// operand specifies a subvector insert that is suitable for input to
4776 /// insertion of 128 or 256-bit subvectors
4777 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4778 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4779 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4781 // The index should be aligned on a vecWidth-bit boundary.
4783 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4785 MVT VT = N->getSimpleValueType(0);
4786 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4787 bool Result = (Index * ElSize) % vecWidth == 0;
4792 bool X86::isVINSERT128Index(SDNode *N) {
4793 return isVINSERTIndex(N, 128);
4796 bool X86::isVINSERT256Index(SDNode *N) {
4797 return isVINSERTIndex(N, 256);
4800 bool X86::isVEXTRACT128Index(SDNode *N) {
4801 return isVEXTRACTIndex(N, 128);
4804 bool X86::isVEXTRACT256Index(SDNode *N) {
4805 return isVEXTRACTIndex(N, 256);
4808 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4809 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4810 /// Handles 128-bit and 256-bit.
4811 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4812 MVT VT = N->getSimpleValueType(0);
4814 assert((VT.getSizeInBits() >= 128) &&
4815 "Unsupported vector type for PSHUF/SHUFP");
4817 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4818 // independently on 128-bit lanes.
4819 unsigned NumElts = VT.getVectorNumElements();
4820 unsigned NumLanes = VT.getSizeInBits()/128;
4821 unsigned NumLaneElts = NumElts/NumLanes;
4823 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4824 "Only supports 2, 4 or 8 elements per lane");
4826 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4828 for (unsigned i = 0; i != NumElts; ++i) {
4829 int Elt = N->getMaskElt(i);
4830 if (Elt < 0) continue;
4831 Elt &= NumLaneElts - 1;
4832 unsigned ShAmt = (i << Shift) % 8;
4833 Mask |= Elt << ShAmt;
4839 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4840 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4841 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4842 MVT VT = N->getSimpleValueType(0);
4844 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4845 "Unsupported vector type for PSHUFHW");
4847 unsigned NumElts = VT.getVectorNumElements();
4850 for (unsigned l = 0; l != NumElts; l += 8) {
4851 // 8 nodes per lane, but we only care about the last 4.
4852 for (unsigned i = 0; i < 4; ++i) {
4853 int Elt = N->getMaskElt(l+i+4);
4854 if (Elt < 0) continue;
4855 Elt &= 0x3; // only 2-bits.
4856 Mask |= Elt << (i * 2);
4863 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4864 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4865 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4866 MVT VT = N->getSimpleValueType(0);
4868 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4869 "Unsupported vector type for PSHUFHW");
4871 unsigned NumElts = VT.getVectorNumElements();
4874 for (unsigned l = 0; l != NumElts; l += 8) {
4875 // 8 nodes per lane, but we only care about the first 4.
4876 for (unsigned i = 0; i < 4; ++i) {
4877 int Elt = N->getMaskElt(l+i);
4878 if (Elt < 0) continue;
4879 Elt &= 0x3; // only 2-bits
4880 Mask |= Elt << (i * 2);
4887 /// \brief Return the appropriate immediate to shuffle the specified
4888 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4889 /// VALIGN (if Interlane is true) instructions.
4890 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4892 MVT VT = SVOp->getSimpleValueType(0);
4893 unsigned EltSize = InterLane ? 1 :
4894 VT.getVectorElementType().getSizeInBits() >> 3;
4896 unsigned NumElts = VT.getVectorNumElements();
4897 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4898 unsigned NumLaneElts = NumElts/NumLanes;
4902 for (i = 0; i != NumElts; ++i) {
4903 Val = SVOp->getMaskElt(i);
4907 if (Val >= (int)NumElts)
4908 Val -= NumElts - NumLaneElts;
4910 assert(Val - i > 0 && "PALIGNR imm should be positive");
4911 return (Val - i) * EltSize;
4914 /// \brief Return the appropriate immediate to shuffle the specified
4915 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4916 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4917 return getShuffleAlignrImmediate(SVOp, false);
4920 /// \brief Return the appropriate immediate to shuffle the specified
4921 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4922 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4923 return getShuffleAlignrImmediate(SVOp, true);
4927 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4928 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4929 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4930 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4933 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4935 MVT VecVT = N->getOperand(0).getSimpleValueType();
4936 MVT ElVT = VecVT.getVectorElementType();
4938 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4939 return Index / NumElemsPerChunk;
4942 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4943 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4944 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4945 llvm_unreachable("Illegal insert subvector for VINSERT");
4948 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4950 MVT VecVT = N->getSimpleValueType(0);
4951 MVT ElVT = VecVT.getVectorElementType();
4953 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4954 return Index / NumElemsPerChunk;
4957 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4958 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4959 /// and VINSERTI128 instructions.
4960 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4961 return getExtractVEXTRACTImmediate(N, 128);
4964 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4965 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4966 /// and VINSERTI64x4 instructions.
4967 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4968 return getExtractVEXTRACTImmediate(N, 256);
4971 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4972 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4973 /// and VINSERTI128 instructions.
4974 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4975 return getInsertVINSERTImmediate(N, 128);
4978 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4979 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4980 /// and VINSERTI64x4 instructions.
4981 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4982 return getInsertVINSERTImmediate(N, 256);
4985 /// isZero - Returns true if Elt is a constant integer zero
4986 static bool isZero(SDValue V) {
4987 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4988 return C && C->isNullValue();
4991 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4993 bool X86::isZeroNode(SDValue Elt) {
4996 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4997 return CFP->getValueAPF().isPosZero();
5001 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5002 /// match movhlps. The lower half elements should come from upper half of
5003 /// V1 (and in order), and the upper half elements should come from the upper
5004 /// half of V2 (and in order).
5005 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5008 if (VT.getVectorNumElements() != 4)
5010 for (unsigned i = 0, e = 2; i != e; ++i)
5011 if (!isUndefOrEqual(Mask[i], i+2))
5013 for (unsigned i = 2; i != 4; ++i)
5014 if (!isUndefOrEqual(Mask[i], i+4))
5019 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5020 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5022 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5023 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5025 N = N->getOperand(0).getNode();
5026 if (!ISD::isNON_EXTLoad(N))
5029 *LD = cast<LoadSDNode>(N);
5033 // Test whether the given value is a vector value which will be legalized
5035 static bool WillBeConstantPoolLoad(SDNode *N) {
5036 if (N->getOpcode() != ISD::BUILD_VECTOR)
5039 // Check for any non-constant elements.
5040 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5041 switch (N->getOperand(i).getNode()->getOpcode()) {
5043 case ISD::ConstantFP:
5050 // Vectors of all-zeros and all-ones are materialized with special
5051 // instructions rather than being loaded.
5052 return !ISD::isBuildVectorAllZeros(N) &&
5053 !ISD::isBuildVectorAllOnes(N);
5056 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5057 /// match movlp{s|d}. The lower half elements should come from lower half of
5058 /// V1 (and in order), and the upper half elements should come from the upper
5059 /// half of V2 (and in order). And since V1 will become the source of the
5060 /// MOVLP, it must be either a vector load or a scalar load to vector.
5061 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5062 ArrayRef<int> Mask, MVT VT) {
5063 if (!VT.is128BitVector())
5066 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5068 // Is V2 is a vector load, don't do this transformation. We will try to use
5069 // load folding shufps op.
5070 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5073 unsigned NumElems = VT.getVectorNumElements();
5075 if (NumElems != 2 && NumElems != 4)
5077 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5078 if (!isUndefOrEqual(Mask[i], i))
5080 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5081 if (!isUndefOrEqual(Mask[i], i+NumElems))
5086 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5087 /// to an zero vector.
5088 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5089 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5090 SDValue V1 = N->getOperand(0);
5091 SDValue V2 = N->getOperand(1);
5092 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5093 for (unsigned i = 0; i != NumElems; ++i) {
5094 int Idx = N->getMaskElt(i);
5095 if (Idx >= (int)NumElems) {
5096 unsigned Opc = V2.getOpcode();
5097 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5099 if (Opc != ISD::BUILD_VECTOR ||
5100 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5102 } else if (Idx >= 0) {
5103 unsigned Opc = V1.getOpcode();
5104 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5106 if (Opc != ISD::BUILD_VECTOR ||
5107 !X86::isZeroNode(V1.getOperand(Idx)))
5114 /// getZeroVector - Returns a vector of specified type with all zero elements.
5116 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5117 SelectionDAG &DAG, SDLoc dl) {
5118 assert(VT.isVector() && "Expected a vector type");
5120 // Always build SSE zero vectors as <4 x i32> bitcasted
5121 // to their dest type. This ensures they get CSE'd.
5123 if (VT.is128BitVector()) { // SSE
5124 if (Subtarget->hasSSE2()) { // SSE2
5125 SDValue Cst = DAG.getConstant(0, MVT::i32);
5126 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5128 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5131 } else if (VT.is256BitVector()) { // AVX
5132 if (Subtarget->hasInt256()) { // AVX2
5133 SDValue Cst = DAG.getConstant(0, MVT::i32);
5134 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5137 // 256-bit logic and arithmetic instructions in AVX are all
5138 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5139 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5140 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5143 } else if (VT.is512BitVector()) { // AVX-512
5144 SDValue Cst = DAG.getConstant(0, MVT::i32);
5145 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5146 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5148 } else if (VT.getScalarType() == MVT::i1) {
5149 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5150 SDValue Cst = DAG.getConstant(0, MVT::i1);
5151 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5152 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5154 llvm_unreachable("Unexpected vector type");
5156 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5159 /// getOnesVector - Returns a vector of specified type with all bits set.
5160 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5161 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5162 /// Then bitcast to their original type, ensuring they get CSE'd.
5163 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5165 assert(VT.isVector() && "Expected a vector type");
5167 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5169 if (VT.is256BitVector()) {
5170 if (HasInt256) { // AVX2
5171 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5175 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5177 } else if (VT.is128BitVector()) {
5178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5180 llvm_unreachable("Unexpected vector type");
5182 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5185 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5186 /// that point to V2 points to its first element.
5187 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5188 for (unsigned i = 0; i != NumElems; ++i) {
5189 if (Mask[i] > (int)NumElems) {
5195 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5196 /// operation of specified width.
5197 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5199 unsigned NumElems = VT.getVectorNumElements();
5200 SmallVector<int, 8> Mask;
5201 Mask.push_back(NumElems);
5202 for (unsigned i = 1; i != NumElems; ++i)
5204 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5207 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5208 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5210 unsigned NumElems = VT.getVectorNumElements();
5211 SmallVector<int, 8> Mask;
5212 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5214 Mask.push_back(i + NumElems);
5216 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5219 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5220 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5222 unsigned NumElems = VT.getVectorNumElements();
5223 SmallVector<int, 8> Mask;
5224 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5225 Mask.push_back(i + Half);
5226 Mask.push_back(i + NumElems + Half);
5228 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5231 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5232 // a generic shuffle instruction because the target has no such instructions.
5233 // Generate shuffles which repeat i16 and i8 several times until they can be
5234 // represented by v4f32 and then be manipulated by target suported shuffles.
5235 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5236 MVT VT = V.getSimpleValueType();
5237 int NumElems = VT.getVectorNumElements();
5240 while (NumElems > 4) {
5241 if (EltNo < NumElems/2) {
5242 V = getUnpackl(DAG, dl, VT, V, V);
5244 V = getUnpackh(DAG, dl, VT, V, V);
5245 EltNo -= NumElems/2;
5252 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5253 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5254 MVT VT = V.getSimpleValueType();
5257 if (VT.is128BitVector()) {
5258 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5259 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5260 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5262 } else if (VT.is256BitVector()) {
5263 // To use VPERMILPS to splat scalars, the second half of indicies must
5264 // refer to the higher part, which is a duplication of the lower one,
5265 // because VPERMILPS can only handle in-lane permutations.
5266 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5267 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5269 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5270 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5273 llvm_unreachable("Vector size not supported");
5275 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5278 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5279 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5280 MVT SrcVT = SV->getSimpleValueType(0);
5281 SDValue V1 = SV->getOperand(0);
5284 int EltNo = SV->getSplatIndex();
5285 int NumElems = SrcVT.getVectorNumElements();
5286 bool Is256BitVec = SrcVT.is256BitVector();
5288 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5289 "Unknown how to promote splat for type");
5291 // Extract the 128-bit part containing the splat element and update
5292 // the splat element index when it refers to the higher register.
5294 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5295 if (EltNo >= NumElems/2)
5296 EltNo -= NumElems/2;
5299 // All i16 and i8 vector types can't be used directly by a generic shuffle
5300 // instruction because the target has no such instruction. Generate shuffles
5301 // which repeat i16 and i8 several times until they fit in i32, and then can
5302 // be manipulated by target suported shuffles.
5303 MVT EltVT = SrcVT.getVectorElementType();
5304 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5305 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5307 // Recreate the 256-bit vector and place the same 128-bit vector
5308 // into the low and high part. This is necessary because we want
5309 // to use VPERM* to shuffle the vectors
5311 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5314 return getLegalSplat(DAG, V1, EltNo);
5317 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5318 /// vector of zero or undef vector. This produces a shuffle where the low
5319 /// element of V2 is swizzled into the zero/undef vector, landing at element
5320 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5321 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5323 const X86Subtarget *Subtarget,
5324 SelectionDAG &DAG) {
5325 MVT VT = V2.getSimpleValueType();
5327 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5328 unsigned NumElems = VT.getVectorNumElements();
5329 SmallVector<int, 16> MaskVec;
5330 for (unsigned i = 0; i != NumElems; ++i)
5331 // If this is the insertion idx, put the low elt of V2 here.
5332 MaskVec.push_back(i == Idx ? NumElems : i);
5333 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5336 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5337 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5338 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5339 /// shuffles which use a single input multiple times, and in those cases it will
5340 /// adjust the mask to only have indices within that single input.
5341 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5342 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5343 unsigned NumElems = VT.getVectorNumElements();
5347 bool IsFakeUnary = false;
5348 switch(N->getOpcode()) {
5349 case X86ISD::BLENDI:
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5354 ImmN = N->getOperand(N->getNumOperands()-1);
5355 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5356 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5358 case X86ISD::UNPCKH:
5359 DecodeUNPCKHMask(VT, Mask);
5360 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5362 case X86ISD::UNPCKL:
5363 DecodeUNPCKLMask(VT, Mask);
5364 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5366 case X86ISD::MOVHLPS:
5367 DecodeMOVHLPSMask(NumElems, Mask);
5368 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5370 case X86ISD::MOVLHPS:
5371 DecodeMOVLHPSMask(NumElems, Mask);
5372 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5374 case X86ISD::PALIGNR:
5375 ImmN = N->getOperand(N->getNumOperands()-1);
5376 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5378 case X86ISD::PSHUFD:
5379 case X86ISD::VPERMILPI:
5380 ImmN = N->getOperand(N->getNumOperands()-1);
5381 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5384 case X86ISD::PSHUFHW:
5385 ImmN = N->getOperand(N->getNumOperands()-1);
5386 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5389 case X86ISD::PSHUFLW:
5390 ImmN = N->getOperand(N->getNumOperands()-1);
5391 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5394 case X86ISD::PSHUFB: {
5396 SDValue MaskNode = N->getOperand(1);
5397 while (MaskNode->getOpcode() == ISD::BITCAST)
5398 MaskNode = MaskNode->getOperand(0);
5400 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5401 // If we have a build-vector, then things are easy.
5402 EVT VT = MaskNode.getValueType();
5403 assert(VT.isVector() &&
5404 "Can't produce a non-vector with a build_vector!");
5405 if (!VT.isInteger())
5408 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5410 SmallVector<uint64_t, 32> RawMask;
5411 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5412 SDValue Op = MaskNode->getOperand(i);
5413 if (Op->getOpcode() == ISD::UNDEF) {
5414 RawMask.push_back((uint64_t)SM_SentinelUndef);
5417 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5420 APInt MaskElement = CN->getAPIntValue();
5422 // We now have to decode the element which could be any integer size and
5423 // extract each byte of it.
5424 for (int j = 0; j < NumBytesPerElement; ++j) {
5425 // Note that this is x86 and so always little endian: the low byte is
5426 // the first byte of the mask.
5427 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5428 MaskElement = MaskElement.lshr(8);
5431 DecodePSHUFBMask(RawMask, Mask);
5435 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5439 SDValue Ptr = MaskLoad->getBasePtr();
5440 if (Ptr->getOpcode() == X86ISD::Wrapper)
5441 Ptr = Ptr->getOperand(0);
5443 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5444 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5447 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5448 // FIXME: Support AVX-512 here.
5449 Type *Ty = C->getType();
5450 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5451 Ty->getVectorNumElements() != 32))
5454 DecodePSHUFBMask(C, Mask);
5460 case X86ISD::VPERMI:
5461 ImmN = N->getOperand(N->getNumOperands()-1);
5462 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5466 case X86ISD::MOVSD: {
5467 // The index 0 always comes from the first element of the second source,
5468 // this is why MOVSS and MOVSD are used in the first place. The other
5469 // elements come from the other positions of the first source vector
5470 Mask.push_back(NumElems);
5471 for (unsigned i = 1; i != NumElems; ++i) {
5476 case X86ISD::VPERM2X128:
5477 ImmN = N->getOperand(N->getNumOperands()-1);
5478 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5479 if (Mask.empty()) return false;
5481 case X86ISD::MOVSLDUP:
5482 DecodeMOVSLDUPMask(VT, Mask);
5484 case X86ISD::MOVSHDUP:
5485 DecodeMOVSHDUPMask(VT, Mask);
5487 case X86ISD::MOVDDUP:
5488 case X86ISD::MOVLHPD:
5489 case X86ISD::MOVLPD:
5490 case X86ISD::MOVLPS:
5491 // Not yet implemented
5493 default: llvm_unreachable("unknown target shuffle node");
5496 // If we have a fake unary shuffle, the shuffle mask is spread across two
5497 // inputs that are actually the same node. Re-map the mask to always point
5498 // into the first input.
5501 if (M >= (int)Mask.size())
5507 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5508 /// element of the result of the vector shuffle.
5509 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5512 return SDValue(); // Limit search depth.
5514 SDValue V = SDValue(N, 0);
5515 EVT VT = V.getValueType();
5516 unsigned Opcode = V.getOpcode();
5518 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5519 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5520 int Elt = SV->getMaskElt(Index);
5523 return DAG.getUNDEF(VT.getVectorElementType());
5525 unsigned NumElems = VT.getVectorNumElements();
5526 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5527 : SV->getOperand(1);
5528 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5531 // Recurse into target specific vector shuffles to find scalars.
5532 if (isTargetShuffle(Opcode)) {
5533 MVT ShufVT = V.getSimpleValueType();
5534 unsigned NumElems = ShufVT.getVectorNumElements();
5535 SmallVector<int, 16> ShuffleMask;
5538 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5541 int Elt = ShuffleMask[Index];
5543 return DAG.getUNDEF(ShufVT.getVectorElementType());
5545 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5547 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5551 // Actual nodes that may contain scalar elements
5552 if (Opcode == ISD::BITCAST) {
5553 V = V.getOperand(0);
5554 EVT SrcVT = V.getValueType();
5555 unsigned NumElems = VT.getVectorNumElements();
5557 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5561 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5562 return (Index == 0) ? V.getOperand(0)
5563 : DAG.getUNDEF(VT.getVectorElementType());
5565 if (V.getOpcode() == ISD::BUILD_VECTOR)
5566 return V.getOperand(Index);
5571 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5572 /// shuffle operation which come from a consecutively from a zero. The
5573 /// search can start in two different directions, from left or right.
5574 /// We count undefs as zeros until PreferredNum is reached.
5575 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5576 unsigned NumElems, bool ZerosFromLeft,
5578 unsigned PreferredNum = -1U) {
5579 unsigned NumZeros = 0;
5580 for (unsigned i = 0; i != NumElems; ++i) {
5581 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5582 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5586 if (X86::isZeroNode(Elt))
5588 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5589 NumZeros = std::min(NumZeros + 1, PreferredNum);
5597 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5598 /// correspond consecutively to elements from one of the vector operands,
5599 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5601 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5602 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5603 unsigned NumElems, unsigned &OpNum) {
5604 bool SeenV1 = false;
5605 bool SeenV2 = false;
5607 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5608 int Idx = SVOp->getMaskElt(i);
5609 // Ignore undef indicies
5613 if (Idx < (int)NumElems)
5618 // Only accept consecutive elements from the same vector
5619 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5623 OpNum = SeenV1 ? 0 : 1;
5627 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5628 /// logical left shift of a vector.
5629 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5632 SVOp->getSimpleValueType(0).getVectorNumElements();
5633 unsigned NumZeros = getNumOfConsecutiveZeros(
5634 SVOp, NumElems, false /* check zeros from right */, DAG,
5635 SVOp->getMaskElt(0));
5641 // Considering the elements in the mask that are not consecutive zeros,
5642 // check if they consecutively come from only one of the source vectors.
5644 // V1 = {X, A, B, C} 0
5646 // vector_shuffle V1, V2 <1, 2, 3, X>
5648 if (!isShuffleMaskConsecutive(SVOp,
5649 0, // Mask Start Index
5650 NumElems-NumZeros, // Mask End Index(exclusive)
5651 NumZeros, // Where to start looking in the src vector
5652 NumElems, // Number of elements in vector
5653 OpSrc)) // Which source operand ?
5658 ShVal = SVOp->getOperand(OpSrc);
5662 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5663 /// logical left shift of a vector.
5664 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5667 SVOp->getSimpleValueType(0).getVectorNumElements();
5668 unsigned NumZeros = getNumOfConsecutiveZeros(
5669 SVOp, NumElems, true /* check zeros from left */, DAG,
5670 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5676 // Considering the elements in the mask that are not consecutive zeros,
5677 // check if they consecutively come from only one of the source vectors.
5679 // 0 { A, B, X, X } = V2
5681 // vector_shuffle V1, V2 <X, X, 4, 5>
5683 if (!isShuffleMaskConsecutive(SVOp,
5684 NumZeros, // Mask Start Index
5685 NumElems, // Mask End Index(exclusive)
5686 0, // Where to start looking in the src vector
5687 NumElems, // Number of elements in vector
5688 OpSrc)) // Which source operand ?
5693 ShVal = SVOp->getOperand(OpSrc);
5697 /// isVectorShift - Returns true if the shuffle can be implemented as a
5698 /// logical left or right shift of a vector.
5699 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5700 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5701 // Although the logic below support any bitwidth size, there are no
5702 // shift instructions which handle more than 128-bit vectors.
5703 if (!SVOp->getSimpleValueType(0).is128BitVector())
5706 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5707 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5713 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5715 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5716 unsigned NumNonZero, unsigned NumZero,
5718 const X86Subtarget* Subtarget,
5719 const TargetLowering &TLI) {
5726 for (unsigned i = 0; i < 16; ++i) {
5727 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5728 if (ThisIsNonZero && First) {
5730 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5732 V = DAG.getUNDEF(MVT::v8i16);
5737 SDValue ThisElt, LastElt;
5738 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5739 if (LastIsNonZero) {
5740 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5741 MVT::i16, Op.getOperand(i-1));
5743 if (ThisIsNonZero) {
5744 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5745 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5746 ThisElt, DAG.getConstant(8, MVT::i8));
5748 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5752 if (ThisElt.getNode())
5753 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5754 DAG.getIntPtrConstant(i/2));
5758 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5761 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5763 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5764 unsigned NumNonZero, unsigned NumZero,
5766 const X86Subtarget* Subtarget,
5767 const TargetLowering &TLI) {
5774 for (unsigned i = 0; i < 8; ++i) {
5775 bool isNonZero = (NonZeros & (1 << i)) != 0;
5779 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5781 V = DAG.getUNDEF(MVT::v8i16);
5784 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5785 MVT::v8i16, V, Op.getOperand(i),
5786 DAG.getIntPtrConstant(i));
5793 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5794 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5795 const X86Subtarget *Subtarget,
5796 const TargetLowering &TLI) {
5797 // Find all zeroable elements.
5799 for (int i=0; i < 4; ++i) {
5800 SDValue Elt = Op->getOperand(i);
5801 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5803 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5804 [](bool M) { return !M; }) > 1 &&
5805 "We expect at least two non-zero elements!");
5807 // We only know how to deal with build_vector nodes where elements are either
5808 // zeroable or extract_vector_elt with constant index.
5809 SDValue FirstNonZero;
5810 unsigned FirstNonZeroIdx;
5811 for (unsigned i=0; i < 4; ++i) {
5814 SDValue Elt = Op->getOperand(i);
5815 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5816 !isa<ConstantSDNode>(Elt.getOperand(1)))
5818 // Make sure that this node is extracting from a 128-bit vector.
5819 MVT VT = Elt.getOperand(0).getSimpleValueType();
5820 if (!VT.is128BitVector())
5822 if (!FirstNonZero.getNode()) {
5824 FirstNonZeroIdx = i;
5828 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5829 SDValue V1 = FirstNonZero.getOperand(0);
5830 MVT VT = V1.getSimpleValueType();
5832 // See if this build_vector can be lowered as a blend with zero.
5834 unsigned EltMaskIdx, EltIdx;
5836 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5837 if (Zeroable[EltIdx]) {
5838 // The zero vector will be on the right hand side.
5839 Mask[EltIdx] = EltIdx+4;
5843 Elt = Op->getOperand(EltIdx);
5844 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5845 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5846 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5848 Mask[EltIdx] = EltIdx;
5852 // Let the shuffle legalizer deal with blend operations.
5853 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5854 if (V1.getSimpleValueType() != VT)
5855 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5856 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5859 // See if we can lower this build_vector to a INSERTPS.
5860 if (!Subtarget->hasSSE41())
5863 SDValue V2 = Elt.getOperand(0);
5864 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5867 bool CanFold = true;
5868 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5872 SDValue Current = Op->getOperand(i);
5873 SDValue SrcVector = Current->getOperand(0);
5876 CanFold = SrcVector == V1 &&
5877 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5883 assert(V1.getNode() && "Expected at least two non-zero elements!");
5884 if (V1.getSimpleValueType() != MVT::v4f32)
5885 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5886 if (V2.getSimpleValueType() != MVT::v4f32)
5887 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5889 // Ok, we can emit an INSERTPS instruction.
5891 for (int i = 0; i < 4; ++i)
5895 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5896 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5897 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5898 DAG.getIntPtrConstant(InsertPSMask));
5899 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5902 /// getVShift - Return a vector logical shift node.
5904 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5905 unsigned NumBits, SelectionDAG &DAG,
5906 const TargetLowering &TLI, SDLoc dl) {
5907 assert(VT.is128BitVector() && "Unknown type for VShift");
5908 EVT ShVT = MVT::v2i64;
5909 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5910 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5911 return DAG.getNode(ISD::BITCAST, dl, VT,
5912 DAG.getNode(Opc, dl, ShVT, SrcOp,
5913 DAG.getConstant(NumBits,
5914 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5918 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5920 // Check if the scalar load can be widened into a vector load. And if
5921 // the address is "base + cst" see if the cst can be "absorbed" into
5922 // the shuffle mask.
5923 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5924 SDValue Ptr = LD->getBasePtr();
5925 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5927 EVT PVT = LD->getValueType(0);
5928 if (PVT != MVT::i32 && PVT != MVT::f32)
5933 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5934 FI = FINode->getIndex();
5936 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5937 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5938 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5939 Offset = Ptr.getConstantOperandVal(1);
5940 Ptr = Ptr.getOperand(0);
5945 // FIXME: 256-bit vector instructions don't require a strict alignment,
5946 // improve this code to support it better.
5947 unsigned RequiredAlign = VT.getSizeInBits()/8;
5948 SDValue Chain = LD->getChain();
5949 // Make sure the stack object alignment is at least 16 or 32.
5950 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5951 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5952 if (MFI->isFixedObjectIndex(FI)) {
5953 // Can't change the alignment. FIXME: It's possible to compute
5954 // the exact stack offset and reference FI + adjust offset instead.
5955 // If someone *really* cares about this. That's the way to implement it.
5958 MFI->setObjectAlignment(FI, RequiredAlign);
5962 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5963 // Ptr + (Offset & ~15).
5966 if ((Offset % RequiredAlign) & 3)
5968 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5970 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5971 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5973 int EltNo = (Offset - StartOffset) >> 2;
5974 unsigned NumElems = VT.getVectorNumElements();
5976 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5977 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5978 LD->getPointerInfo().getWithOffset(StartOffset),
5979 false, false, false, 0);
5981 SmallVector<int, 8> Mask;
5982 for (unsigned i = 0; i != NumElems; ++i)
5983 Mask.push_back(EltNo);
5985 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5991 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5992 /// vector of type 'VT', see if the elements can be replaced by a single large
5993 /// load which has the same value as a build_vector whose operands are 'elts'.
5995 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5997 /// FIXME: we'd also like to handle the case where the last elements are zero
5998 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5999 /// There's even a handy isZeroNode for that purpose.
6000 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6001 SDLoc &DL, SelectionDAG &DAG,
6002 bool isAfterLegalize) {
6003 EVT EltVT = VT.getVectorElementType();
6004 unsigned NumElems = Elts.size();
6006 LoadSDNode *LDBase = nullptr;
6007 unsigned LastLoadedElt = -1U;
6009 // For each element in the initializer, see if we've found a load or an undef.
6010 // If we don't find an initial load element, or later load elements are
6011 // non-consecutive, bail out.
6012 for (unsigned i = 0; i < NumElems; ++i) {
6013 SDValue Elt = Elts[i];
6015 if (!Elt.getNode() ||
6016 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6019 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6021 LDBase = cast<LoadSDNode>(Elt.getNode());
6025 if (Elt.getOpcode() == ISD::UNDEF)
6028 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6029 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6034 // If we have found an entire vector of loads and undefs, then return a large
6035 // load of the entire vector width starting at the base pointer. If we found
6036 // consecutive loads for the low half, generate a vzext_load node.
6037 if (LastLoadedElt == NumElems - 1) {
6039 if (isAfterLegalize &&
6040 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6043 SDValue NewLd = SDValue();
6045 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6046 LDBase->getPointerInfo(), LDBase->isVolatile(),
6047 LDBase->isNonTemporal(), LDBase->isInvariant(),
6048 LDBase->getAlignment());
6050 if (LDBase->hasAnyUseOfValue(1)) {
6051 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6053 SDValue(NewLd.getNode(), 1));
6054 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6055 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6056 SDValue(NewLd.getNode(), 1));
6062 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6063 //of a v4i32 / v4f32. It's probably worth generalizing.
6064 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6065 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6066 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6067 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6069 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6070 LDBase->getPointerInfo(),
6071 LDBase->getAlignment(),
6072 false/*isVolatile*/, true/*ReadMem*/,
6075 // Make sure the newly-created LOAD is in the same position as LDBase in
6076 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6077 // update uses of LDBase's output chain to use the TokenFactor.
6078 if (LDBase->hasAnyUseOfValue(1)) {
6079 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6080 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6081 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6082 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6083 SDValue(ResNode.getNode(), 1));
6086 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6091 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6092 /// to generate a splat value for the following cases:
6093 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6094 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6095 /// a scalar load, or a constant.
6096 /// The VBROADCAST node is returned when a pattern is found,
6097 /// or SDValue() otherwise.
6098 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6099 SelectionDAG &DAG) {
6100 // VBROADCAST requires AVX.
6101 // TODO: Splats could be generated for non-AVX CPUs using SSE
6102 // instructions, but there's less potential gain for only 128-bit vectors.
6103 if (!Subtarget->hasAVX())
6106 MVT VT = Op.getSimpleValueType();
6109 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6110 "Unsupported vector type for broadcast.");
6115 switch (Op.getOpcode()) {
6117 // Unknown pattern found.
6120 case ISD::BUILD_VECTOR: {
6121 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6122 BitVector UndefElements;
6123 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6125 // We need a splat of a single value to use broadcast, and it doesn't
6126 // make any sense if the value is only in one element of the vector.
6127 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6131 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6132 Ld.getOpcode() == ISD::ConstantFP);
6134 // Make sure that all of the users of a non-constant load are from the
6135 // BUILD_VECTOR node.
6136 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6141 case ISD::VECTOR_SHUFFLE: {
6142 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6144 // Shuffles must have a splat mask where the first element is
6146 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6149 SDValue Sc = Op.getOperand(0);
6150 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6151 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6153 if (!Subtarget->hasInt256())
6156 // Use the register form of the broadcast instruction available on AVX2.
6157 if (VT.getSizeInBits() >= 256)
6158 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6159 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6162 Ld = Sc.getOperand(0);
6163 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6164 Ld.getOpcode() == ISD::ConstantFP);
6166 // The scalar_to_vector node and the suspected
6167 // load node must have exactly one user.
6168 // Constants may have multiple users.
6170 // AVX-512 has register version of the broadcast
6171 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6172 Ld.getValueType().getSizeInBits() >= 32;
6173 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6180 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6181 bool IsGE256 = (VT.getSizeInBits() >= 256);
6183 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6184 // instruction to save 8 or more bytes of constant pool data.
6185 // TODO: If multiple splats are generated to load the same constant,
6186 // it may be detrimental to overall size. There needs to be a way to detect
6187 // that condition to know if this is truly a size win.
6188 const Function *F = DAG.getMachineFunction().getFunction();
6189 bool OptForSize = F->getAttributes().
6190 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6192 // Handle broadcasting a single constant scalar from the constant pool
6194 // On Sandybridge (no AVX2), it is still better to load a constant vector
6195 // from the constant pool and not to broadcast it from a scalar.
6196 // But override that restriction when optimizing for size.
6197 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6198 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6199 EVT CVT = Ld.getValueType();
6200 assert(!CVT.isVector() && "Must not broadcast a vector type");
6202 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6203 // For size optimization, also splat v2f64 and v2i64, and for size opt
6204 // with AVX2, also splat i8 and i16.
6205 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6206 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6207 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6208 const Constant *C = nullptr;
6209 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6210 C = CI->getConstantIntValue();
6211 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6212 C = CF->getConstantFPValue();
6214 assert(C && "Invalid constant type");
6216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6217 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6218 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6219 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6220 MachinePointerInfo::getConstantPool(),
6221 false, false, false, Alignment);
6223 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6227 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6229 // Handle AVX2 in-register broadcasts.
6230 if (!IsLoad && Subtarget->hasInt256() &&
6231 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6232 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6234 // The scalar source must be a normal load.
6238 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6239 (Subtarget->hasVLX() && ScalarSize == 64))
6240 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6242 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6243 // double since there is no vbroadcastsd xmm
6244 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6245 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6246 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6249 // Unsupported broadcast.
6253 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6254 /// underlying vector and index.
6256 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6258 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6260 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6261 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6264 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6266 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6268 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6269 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6272 // In this case the vector is the extract_subvector expression and the index
6273 // is 2, as specified by the shuffle.
6274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6275 SDValue ShuffleVec = SVOp->getOperand(0);
6276 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6277 assert(ShuffleVecVT.getVectorElementType() ==
6278 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6280 int ShuffleIdx = SVOp->getMaskElt(Idx);
6281 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6282 ExtractedFromVec = ShuffleVec;
6288 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6289 MVT VT = Op.getSimpleValueType();
6291 // Skip if insert_vec_elt is not supported.
6292 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6293 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6297 unsigned NumElems = Op.getNumOperands();
6301 SmallVector<unsigned, 4> InsertIndices;
6302 SmallVector<int, 8> Mask(NumElems, -1);
6304 for (unsigned i = 0; i != NumElems; ++i) {
6305 unsigned Opc = Op.getOperand(i).getOpcode();
6307 if (Opc == ISD::UNDEF)
6310 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6311 // Quit if more than 1 elements need inserting.
6312 if (InsertIndices.size() > 1)
6315 InsertIndices.push_back(i);
6319 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6320 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6321 // Quit if non-constant index.
6322 if (!isa<ConstantSDNode>(ExtIdx))
6324 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6326 // Quit if extracted from vector of different type.
6327 if (ExtractedFromVec.getValueType() != VT)
6330 if (!VecIn1.getNode())
6331 VecIn1 = ExtractedFromVec;
6332 else if (VecIn1 != ExtractedFromVec) {
6333 if (!VecIn2.getNode())
6334 VecIn2 = ExtractedFromVec;
6335 else if (VecIn2 != ExtractedFromVec)
6336 // Quit if more than 2 vectors to shuffle
6340 if (ExtractedFromVec == VecIn1)
6342 else if (ExtractedFromVec == VecIn2)
6343 Mask[i] = Idx + NumElems;
6346 if (!VecIn1.getNode())
6349 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6350 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6351 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6352 unsigned Idx = InsertIndices[i];
6353 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6354 DAG.getIntPtrConstant(Idx));
6360 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6362 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6364 MVT VT = Op.getSimpleValueType();
6365 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6366 "Unexpected type in LowerBUILD_VECTORvXi1!");
6369 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6370 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6371 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6372 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6375 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6376 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6377 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6378 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6381 bool AllContants = true;
6382 uint64_t Immediate = 0;
6383 int NonConstIdx = -1;
6384 bool IsSplat = true;
6385 unsigned NumNonConsts = 0;
6386 unsigned NumConsts = 0;
6387 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6388 SDValue In = Op.getOperand(idx);
6389 if (In.getOpcode() == ISD::UNDEF)
6391 if (!isa<ConstantSDNode>(In)) {
6392 AllContants = false;
6397 if (cast<ConstantSDNode>(In)->getZExtValue())
6398 Immediate |= (1ULL << idx);
6400 if (In != Op.getOperand(0))
6405 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6406 DAG.getConstant(Immediate, MVT::i16));
6407 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6408 DAG.getIntPtrConstant(0));
6411 if (NumNonConsts == 1 && NonConstIdx != 0) {
6414 SDValue VecAsImm = DAG.getConstant(Immediate,
6415 MVT::getIntegerVT(VT.getSizeInBits()));
6416 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6419 DstVec = DAG.getUNDEF(VT);
6420 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6421 Op.getOperand(NonConstIdx),
6422 DAG.getIntPtrConstant(NonConstIdx));
6424 if (!IsSplat && (NonConstIdx != 0))
6425 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6426 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6429 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6430 DAG.getConstant(-1, SelectVT),
6431 DAG.getConstant(0, SelectVT));
6433 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6434 DAG.getConstant((Immediate | 1), SelectVT),
6435 DAG.getConstant(Immediate, SelectVT));
6436 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6439 /// \brief Return true if \p N implements a horizontal binop and return the
6440 /// operands for the horizontal binop into V0 and V1.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function checks that the build_vector \p N in input implements a
6444 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6445 /// operation to match.
6446 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6447 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6448 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6451 /// This function only analyzes elements of \p N whose indices are
6452 /// in range [BaseIdx, LastIdx).
6453 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6455 unsigned BaseIdx, unsigned LastIdx,
6456 SDValue &V0, SDValue &V1) {
6457 EVT VT = N->getValueType(0);
6459 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6460 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6461 "Invalid Vector in input!");
6463 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6464 bool CanFold = true;
6465 unsigned ExpectedVExtractIdx = BaseIdx;
6466 unsigned NumElts = LastIdx - BaseIdx;
6467 V0 = DAG.getUNDEF(VT);
6468 V1 = DAG.getUNDEF(VT);
6470 // Check if N implements a horizontal binop.
6471 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6472 SDValue Op = N->getOperand(i + BaseIdx);
6475 if (Op->getOpcode() == ISD::UNDEF) {
6476 // Update the expected vector extract index.
6477 if (i * 2 == NumElts)
6478 ExpectedVExtractIdx = BaseIdx;
6479 ExpectedVExtractIdx += 2;
6483 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6488 SDValue Op0 = Op.getOperand(0);
6489 SDValue Op1 = Op.getOperand(1);
6491 // Try to match the following pattern:
6492 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6493 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6494 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6495 Op0.getOperand(0) == Op1.getOperand(0) &&
6496 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6497 isa<ConstantSDNode>(Op1.getOperand(1)));
6501 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6502 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6504 if (i * 2 < NumElts) {
6505 if (V0.getOpcode() == ISD::UNDEF)
6506 V0 = Op0.getOperand(0);
6508 if (V1.getOpcode() == ISD::UNDEF)
6509 V1 = Op0.getOperand(0);
6510 if (i * 2 == NumElts)
6511 ExpectedVExtractIdx = BaseIdx;
6514 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6515 if (I0 == ExpectedVExtractIdx)
6516 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6517 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6518 // Try to match the following dag sequence:
6519 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6520 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6524 ExpectedVExtractIdx += 2;
6530 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6531 /// a concat_vector.
6533 /// This is a helper function of PerformBUILD_VECTORCombine.
6534 /// This function expects two 256-bit vectors called V0 and V1.
6535 /// At first, each vector is split into two separate 128-bit vectors.
6536 /// Then, the resulting 128-bit vectors are used to implement two
6537 /// horizontal binary operations.
6539 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6541 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6542 /// the two new horizontal binop.
6543 /// When Mode is set, the first horizontal binop dag node would take as input
6544 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6545 /// horizontal binop dag node would take as input the lower 128-bit of V1
6546 /// and the upper 128-bit of V1.
6548 /// HADD V0_LO, V0_HI
6549 /// HADD V1_LO, V1_HI
6551 /// Otherwise, the first horizontal binop dag node takes as input the lower
6552 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6553 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6555 /// HADD V0_LO, V1_LO
6556 /// HADD V0_HI, V1_HI
6558 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6559 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6560 /// the upper 128-bits of the result.
6561 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6562 SDLoc DL, SelectionDAG &DAG,
6563 unsigned X86Opcode, bool Mode,
6564 bool isUndefLO, bool isUndefHI) {
6565 EVT VT = V0.getValueType();
6566 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6567 "Invalid nodes in input!");
6569 unsigned NumElts = VT.getVectorNumElements();
6570 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6571 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6572 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6573 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6574 EVT NewVT = V0_LO.getValueType();
6576 SDValue LO = DAG.getUNDEF(NewVT);
6577 SDValue HI = DAG.getUNDEF(NewVT);
6580 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6581 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6582 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6583 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6584 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6586 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6587 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6588 V1_LO->getOpcode() != ISD::UNDEF))
6589 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6591 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6592 V1_HI->getOpcode() != ISD::UNDEF))
6593 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6596 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6599 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6600 /// sequence of 'vadd + vsub + blendi'.
6601 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = BV->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 SDValue InVec0 = DAG.getUNDEF(VT);
6607 SDValue InVec1 = DAG.getUNDEF(VT);
6609 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6610 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6612 // Odd-numbered elements in the input build vector are obtained from
6613 // adding two integer/float elements.
6614 // Even-numbered elements in the input build vector are obtained from
6615 // subtracting two integer/float elements.
6616 unsigned ExpectedOpcode = ISD::FSUB;
6617 unsigned NextExpectedOpcode = ISD::FADD;
6618 bool AddFound = false;
6619 bool SubFound = false;
6621 for (unsigned i = 0, e = NumElts; i != e; i++) {
6622 SDValue Op = BV->getOperand(i);
6624 // Skip 'undef' values.
6625 unsigned Opcode = Op.getOpcode();
6626 if (Opcode == ISD::UNDEF) {
6627 std::swap(ExpectedOpcode, NextExpectedOpcode);
6631 // Early exit if we found an unexpected opcode.
6632 if (Opcode != ExpectedOpcode)
6635 SDValue Op0 = Op.getOperand(0);
6636 SDValue Op1 = Op.getOperand(1);
6638 // Try to match the following pattern:
6639 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6640 // Early exit if we cannot match that sequence.
6641 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6642 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6643 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6644 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6645 Op0.getOperand(1) != Op1.getOperand(1))
6648 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6652 // We found a valid add/sub node. Update the information accordingly.
6658 // Update InVec0 and InVec1.
6659 if (InVec0.getOpcode() == ISD::UNDEF)
6660 InVec0 = Op0.getOperand(0);
6661 if (InVec1.getOpcode() == ISD::UNDEF)
6662 InVec1 = Op1.getOperand(0);
6664 // Make sure that operands in input to each add/sub node always
6665 // come from a same pair of vectors.
6666 if (InVec0 != Op0.getOperand(0)) {
6667 if (ExpectedOpcode == ISD::FSUB)
6670 // FADD is commutable. Try to commute the operands
6671 // and then test again.
6672 std::swap(Op0, Op1);
6673 if (InVec0 != Op0.getOperand(0))
6677 if (InVec1 != Op1.getOperand(0))
6680 // Update the pair of expected opcodes.
6681 std::swap(ExpectedOpcode, NextExpectedOpcode);
6684 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6685 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6686 InVec1.getOpcode() != ISD::UNDEF)
6687 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6692 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6693 const X86Subtarget *Subtarget) {
6695 EVT VT = N->getValueType(0);
6696 unsigned NumElts = VT.getVectorNumElements();
6697 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6698 SDValue InVec0, InVec1;
6700 // Try to match an ADDSUB.
6701 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6702 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6703 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6704 if (Value.getNode())
6708 // Try to match horizontal ADD/SUB.
6709 unsigned NumUndefsLO = 0;
6710 unsigned NumUndefsHI = 0;
6711 unsigned Half = NumElts/2;
6713 // Count the number of UNDEF operands in the build_vector in input.
6714 for (unsigned i = 0, e = Half; i != e; ++i)
6715 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6718 for (unsigned i = Half, e = NumElts; i != e; ++i)
6719 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6722 // Early exit if this is either a build_vector of all UNDEFs or all the
6723 // operands but one are UNDEF.
6724 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6727 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6728 // Try to match an SSE3 float HADD/HSUB.
6729 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6730 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6732 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6733 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6734 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6735 // Try to match an SSSE3 integer HADD/HSUB.
6736 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6737 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6739 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6740 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6743 if (!Subtarget->hasAVX())
6746 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6747 // Try to match an AVX horizontal add/sub of packed single/double
6748 // precision floating point values from 256-bit vectors.
6749 SDValue InVec2, InVec3;
6750 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6751 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6752 ((InVec0.getOpcode() == ISD::UNDEF ||
6753 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6754 ((InVec1.getOpcode() == ISD::UNDEF ||
6755 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6756 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6758 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6759 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6760 ((InVec0.getOpcode() == ISD::UNDEF ||
6761 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6762 ((InVec1.getOpcode() == ISD::UNDEF ||
6763 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6764 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6765 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6766 // Try to match an AVX2 horizontal add/sub of signed integers.
6767 SDValue InVec2, InVec3;
6769 bool CanFold = true;
6771 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6772 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6773 ((InVec0.getOpcode() == ISD::UNDEF ||
6774 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6775 ((InVec1.getOpcode() == ISD::UNDEF ||
6776 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6777 X86Opcode = X86ISD::HADD;
6778 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6779 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6780 ((InVec0.getOpcode() == ISD::UNDEF ||
6781 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6782 ((InVec1.getOpcode() == ISD::UNDEF ||
6783 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6784 X86Opcode = X86ISD::HSUB;
6789 // Fold this build_vector into a single horizontal add/sub.
6790 // Do this only if the target has AVX2.
6791 if (Subtarget->hasAVX2())
6792 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6794 // Do not try to expand this build_vector into a pair of horizontal
6795 // add/sub if we can emit a pair of scalar add/sub.
6796 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6799 // Convert this build_vector into a pair of horizontal binop followed by
6801 bool isUndefLO = NumUndefsLO == Half;
6802 bool isUndefHI = NumUndefsHI == Half;
6803 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6804 isUndefLO, isUndefHI);
6808 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6809 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6811 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6812 X86Opcode = X86ISD::HADD;
6813 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6814 X86Opcode = X86ISD::HSUB;
6815 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6816 X86Opcode = X86ISD::FHADD;
6817 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6818 X86Opcode = X86ISD::FHSUB;
6822 // Don't try to expand this build_vector into a pair of horizontal add/sub
6823 // if we can simply emit a pair of scalar add/sub.
6824 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6827 // Convert this build_vector into two horizontal add/sub followed by
6829 bool isUndefLO = NumUndefsLO == Half;
6830 bool isUndefHI = NumUndefsHI == Half;
6831 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6832 isUndefLO, isUndefHI);
6839 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6842 MVT VT = Op.getSimpleValueType();
6843 MVT ExtVT = VT.getVectorElementType();
6844 unsigned NumElems = Op.getNumOperands();
6846 // Generate vectors for predicate vectors.
6847 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6848 return LowerBUILD_VECTORvXi1(Op, DAG);
6850 // Vectors containing all zeros can be matched by pxor and xorps later
6851 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6852 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6853 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6854 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6857 return getZeroVector(VT, Subtarget, DAG, dl);
6860 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6861 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6862 // vpcmpeqd on 256-bit vectors.
6863 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6864 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6867 if (!VT.is512BitVector())
6868 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6871 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6872 if (Broadcast.getNode())
6875 unsigned EVTBits = ExtVT.getSizeInBits();
6877 unsigned NumZero = 0;
6878 unsigned NumNonZero = 0;
6879 unsigned NonZeros = 0;
6880 bool IsAllConstants = true;
6881 SmallSet<SDValue, 8> Values;
6882 for (unsigned i = 0; i < NumElems; ++i) {
6883 SDValue Elt = Op.getOperand(i);
6884 if (Elt.getOpcode() == ISD::UNDEF)
6887 if (Elt.getOpcode() != ISD::Constant &&
6888 Elt.getOpcode() != ISD::ConstantFP)
6889 IsAllConstants = false;
6890 if (X86::isZeroNode(Elt))
6893 NonZeros |= (1 << i);
6898 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6899 if (NumNonZero == 0)
6900 return DAG.getUNDEF(VT);
6902 // Special case for single non-zero, non-undef, element.
6903 if (NumNonZero == 1) {
6904 unsigned Idx = countTrailingZeros(NonZeros);
6905 SDValue Item = Op.getOperand(Idx);
6907 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6908 // the value are obviously zero, truncate the value to i32 and do the
6909 // insertion that way. Only do this if the value is non-constant or if the
6910 // value is a constant being inserted into element 0. It is cheaper to do
6911 // a constant pool load than it is to do a movd + shuffle.
6912 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6913 (!IsAllConstants || Idx == 0)) {
6914 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6916 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6917 EVT VecVT = MVT::v4i32;
6918 unsigned VecElts = 4;
6920 // Truncate the value (which may itself be a constant) to i32, and
6921 // convert it to a vector with movd (S2V+shuffle to zero extend).
6922 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6923 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6925 // If using the new shuffle lowering, just directly insert this.
6926 if (ExperimentalVectorShuffleLowering)
6928 ISD::BITCAST, dl, VT,
6929 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6931 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6933 // Now we have our 32-bit value zero extended in the low element of
6934 // a vector. If Idx != 0, swizzle it into place.
6936 SmallVector<int, 4> Mask;
6937 Mask.push_back(Idx);
6938 for (unsigned i = 1; i != VecElts; ++i)
6940 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6943 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6947 // If we have a constant or non-constant insertion into the low element of
6948 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6949 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6950 // depending on what the source datatype is.
6953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6955 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6956 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6957 if (VT.is256BitVector() || VT.is512BitVector()) {
6958 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6959 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6960 Item, DAG.getIntPtrConstant(0));
6962 assert(VT.is128BitVector() && "Expected an SSE value type!");
6963 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6964 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6965 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6968 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6969 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6970 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6971 if (VT.is256BitVector()) {
6972 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6973 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6975 assert(VT.is128BitVector() && "Expected an SSE value type!");
6976 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6978 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6982 // Is it a vector logical left shift?
6983 if (NumElems == 2 && Idx == 1 &&
6984 X86::isZeroNode(Op.getOperand(0)) &&
6985 !X86::isZeroNode(Op.getOperand(1))) {
6986 unsigned NumBits = VT.getSizeInBits();
6987 return getVShift(true, VT,
6988 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6989 VT, Op.getOperand(1)),
6990 NumBits/2, DAG, *this, dl);
6993 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6996 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6997 // is a non-constant being inserted into an element other than the low one,
6998 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6999 // movd/movss) to move this into the low element, then shuffle it into
7001 if (EVTBits == 32) {
7002 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7004 // If using the new shuffle lowering, just directly insert this.
7005 if (ExperimentalVectorShuffleLowering)
7006 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7008 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7009 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7010 SmallVector<int, 8> MaskVec;
7011 for (unsigned i = 0; i != NumElems; ++i)
7012 MaskVec.push_back(i == Idx ? 0 : 1);
7013 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7017 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7018 if (Values.size() == 1) {
7019 if (EVTBits == 32) {
7020 // Instead of a shuffle like this:
7021 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7022 // Check if it's possible to issue this instead.
7023 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7024 unsigned Idx = countTrailingZeros(NonZeros);
7025 SDValue Item = Op.getOperand(Idx);
7026 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7027 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7032 // A vector full of immediates; various special cases are already
7033 // handled, so this is best done with a single constant-pool load.
7037 // For AVX-length vectors, see if we can use a vector load to get all of the
7038 // elements, otherwise build the individual 128-bit pieces and use
7039 // shuffles to put them in place.
7040 if (VT.is256BitVector() || VT.is512BitVector()) {
7041 SmallVector<SDValue, 64> V;
7042 for (unsigned i = 0; i != NumElems; ++i)
7043 V.push_back(Op.getOperand(i));
7045 // Check for a build vector of consecutive loads.
7046 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7049 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7051 // Build both the lower and upper subvector.
7052 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7053 makeArrayRef(&V[0], NumElems/2));
7054 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7055 makeArrayRef(&V[NumElems / 2], NumElems/2));
7057 // Recreate the wider vector with the lower and upper part.
7058 if (VT.is256BitVector())
7059 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7060 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7063 // Let legalizer expand 2-wide build_vectors.
7064 if (EVTBits == 64) {
7065 if (NumNonZero == 1) {
7066 // One half is zero or undef.
7067 unsigned Idx = countTrailingZeros(NonZeros);
7068 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7069 Op.getOperand(Idx));
7070 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7075 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7076 if (EVTBits == 8 && NumElems == 16) {
7077 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7079 if (V.getNode()) return V;
7082 if (EVTBits == 16 && NumElems == 8) {
7083 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7085 if (V.getNode()) return V;
7088 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7089 if (EVTBits == 32 && NumElems == 4) {
7090 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7095 // If element VT is == 32 bits, turn it into a number of shuffles.
7096 SmallVector<SDValue, 8> V(NumElems);
7097 if (NumElems == 4 && NumZero > 0) {
7098 for (unsigned i = 0; i < 4; ++i) {
7099 bool isZero = !(NonZeros & (1 << i));
7101 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7103 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7106 for (unsigned i = 0; i < 2; ++i) {
7107 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7110 V[i] = V[i*2]; // Must be a zero vector.
7113 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7116 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7119 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7124 bool Reverse1 = (NonZeros & 0x3) == 2;
7125 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7129 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7130 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7132 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7135 if (Values.size() > 1 && VT.is128BitVector()) {
7136 // Check for a build vector of consecutive loads.
7137 for (unsigned i = 0; i < NumElems; ++i)
7138 V[i] = Op.getOperand(i);
7140 // Check for elements which are consecutive loads.
7141 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7145 // Check for a build vector from mostly shuffle plus few inserting.
7146 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7150 // For SSE 4.1, use insertps to put the high elements into the low element.
7151 if (getSubtarget()->hasSSE41()) {
7153 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7154 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7156 Result = DAG.getUNDEF(VT);
7158 for (unsigned i = 1; i < NumElems; ++i) {
7159 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7160 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7161 Op.getOperand(i), DAG.getIntPtrConstant(i));
7166 // Otherwise, expand into a number of unpckl*, start by extending each of
7167 // our (non-undef) elements to the full vector width with the element in the
7168 // bottom slot of the vector (which generates no code for SSE).
7169 for (unsigned i = 0; i < NumElems; ++i) {
7170 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7171 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7173 V[i] = DAG.getUNDEF(VT);
7176 // Next, we iteratively mix elements, e.g. for v4f32:
7177 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7178 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7179 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7180 unsigned EltStride = NumElems >> 1;
7181 while (EltStride != 0) {
7182 for (unsigned i = 0; i < EltStride; ++i) {
7183 // If V[i+EltStride] is undef and this is the first round of mixing,
7184 // then it is safe to just drop this shuffle: V[i] is already in the
7185 // right place, the one element (since it's the first round) being
7186 // inserted as undef can be dropped. This isn't safe for successive
7187 // rounds because they will permute elements within both vectors.
7188 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7189 EltStride == NumElems/2)
7192 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7201 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7202 // to create 256-bit vectors from two other 128-bit ones.
7203 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7205 MVT ResVT = Op.getSimpleValueType();
7207 assert((ResVT.is256BitVector() ||
7208 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7210 SDValue V1 = Op.getOperand(0);
7211 SDValue V2 = Op.getOperand(1);
7212 unsigned NumElems = ResVT.getVectorNumElements();
7213 if(ResVT.is256BitVector())
7214 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7216 if (Op.getNumOperands() == 4) {
7217 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7218 ResVT.getVectorNumElements()/2);
7219 SDValue V3 = Op.getOperand(2);
7220 SDValue V4 = Op.getOperand(3);
7221 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7222 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7224 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7227 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7228 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7229 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7230 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7231 Op.getNumOperands() == 4)));
7233 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7234 // from two other 128-bit ones.
7236 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7237 return LowerAVXCONCAT_VECTORS(Op, DAG);
7241 //===----------------------------------------------------------------------===//
7242 // Vector shuffle lowering
7244 // This is an experimental code path for lowering vector shuffles on x86. It is
7245 // designed to handle arbitrary vector shuffles and blends, gracefully
7246 // degrading performance as necessary. It works hard to recognize idiomatic
7247 // shuffles and lower them to optimal instruction patterns without leaving
7248 // a framework that allows reasonably efficient handling of all vector shuffle
7250 //===----------------------------------------------------------------------===//
7252 /// \brief Tiny helper function to identify a no-op mask.
7254 /// This is a somewhat boring predicate function. It checks whether the mask
7255 /// array input, which is assumed to be a single-input shuffle mask of the kind
7256 /// used by the X86 shuffle instructions (not a fully general
7257 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7258 /// in-place shuffle are 'no-op's.
7259 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7260 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7261 if (Mask[i] != -1 && Mask[i] != i)
7266 /// \brief Helper function to classify a mask as a single-input mask.
7268 /// This isn't a generic single-input test because in the vector shuffle
7269 /// lowering we canonicalize single inputs to be the first input operand. This
7270 /// means we can more quickly test for a single input by only checking whether
7271 /// an input from the second operand exists. We also assume that the size of
7272 /// mask corresponds to the size of the input vectors which isn't true in the
7273 /// fully general case.
7274 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7276 if (M >= (int)Mask.size())
7281 /// \brief Test whether there are elements crossing 128-bit lanes in this
7284 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7285 /// and we routinely test for these.
7286 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7287 int LaneSize = 128 / VT.getScalarSizeInBits();
7288 int Size = Mask.size();
7289 for (int i = 0; i < Size; ++i)
7290 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7295 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7297 /// This checks a shuffle mask to see if it is performing the same
7298 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7299 /// that it is also not lane-crossing. It may however involve a blend from the
7300 /// same lane of a second vector.
7302 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7303 /// non-trivial to compute in the face of undef lanes. The representation is
7304 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7305 /// entries from both V1 and V2 inputs to the wider mask.
7307 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7308 SmallVectorImpl<int> &RepeatedMask) {
7309 int LaneSize = 128 / VT.getScalarSizeInBits();
7310 RepeatedMask.resize(LaneSize, -1);
7311 int Size = Mask.size();
7312 for (int i = 0; i < Size; ++i) {
7315 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7316 // This entry crosses lanes, so there is no way to model this shuffle.
7319 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7320 if (RepeatedMask[i % LaneSize] == -1)
7321 // This is the first non-undef entry in this slot of a 128-bit lane.
7322 RepeatedMask[i % LaneSize] =
7323 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7324 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7325 // Found a mismatch with the repeated mask.
7331 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7332 // 2013 will allow us to use it as a non-type template parameter.
7335 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7337 /// See its documentation for details.
7338 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7339 if (Mask.size() != Args.size())
7341 for (int i = 0, e = Mask.size(); i < e; ++i) {
7342 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7343 if (Mask[i] != -1 && Mask[i] != *Args[i])
7351 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7354 /// This is a fast way to test a shuffle mask against a fixed pattern:
7356 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7358 /// It returns true if the mask is exactly as wide as the argument list, and
7359 /// each element of the mask is either -1 (signifying undef) or the value given
7360 /// in the argument.
7361 static const VariadicFunction1<
7362 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7364 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7366 /// This helper function produces an 8-bit shuffle immediate corresponding to
7367 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7368 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7371 /// NB: We rely heavily on "undef" masks preserving the input lane.
7372 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7373 SelectionDAG &DAG) {
7374 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7375 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7376 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7377 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7378 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7381 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7382 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7383 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7384 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7385 return DAG.getConstant(Imm, MVT::i8);
7388 /// \brief Try to emit a blend instruction for a shuffle.
7390 /// This doesn't do any checks for the availability of instructions for blending
7391 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7392 /// be matched in the backend with the type given. What it does check for is
7393 /// that the shuffle mask is in fact a blend.
7394 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7395 SDValue V2, ArrayRef<int> Mask,
7396 const X86Subtarget *Subtarget,
7397 SelectionDAG &DAG) {
7399 unsigned BlendMask = 0;
7400 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7401 if (Mask[i] >= Size) {
7402 if (Mask[i] != i + Size)
7403 return SDValue(); // Shuffled V2 input!
7404 BlendMask |= 1u << i;
7407 if (Mask[i] >= 0 && Mask[i] != i)
7408 return SDValue(); // Shuffled V1 input!
7410 switch (VT.SimpleTy) {
7415 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7416 DAG.getConstant(BlendMask, MVT::i8));
7420 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7424 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7425 // that instruction.
7426 if (Subtarget->hasAVX2()) {
7427 // Scale the blend by the number of 32-bit dwords per element.
7428 int Scale = VT.getScalarSizeInBits() / 32;
7430 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7431 if (Mask[i] >= Size)
7432 for (int j = 0; j < Scale; ++j)
7433 BlendMask |= 1u << (i * Scale + j);
7435 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7436 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7437 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7438 return DAG.getNode(ISD::BITCAST, DL, VT,
7439 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7440 DAG.getConstant(BlendMask, MVT::i8)));
7444 // For integer shuffles we need to expand the mask and cast the inputs to
7445 // v8i16s prior to blending.
7446 int Scale = 8 / VT.getVectorNumElements();
7448 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7449 if (Mask[i] >= Size)
7450 for (int j = 0; j < Scale; ++j)
7451 BlendMask |= 1u << (i * Scale + j);
7453 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7454 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7455 return DAG.getNode(ISD::BITCAST, DL, VT,
7456 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7457 DAG.getConstant(BlendMask, MVT::i8)));
7461 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7462 SmallVector<int, 8> RepeatedMask;
7463 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7464 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7465 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7467 for (int i = 0; i < 8; ++i)
7468 if (RepeatedMask[i] >= 16)
7469 BlendMask |= 1u << i;
7470 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7471 DAG.getConstant(BlendMask, MVT::i8));
7476 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7477 // Scale the blend by the number of bytes per element.
7478 int Scale = VT.getScalarSizeInBits() / 8;
7479 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7481 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7482 // mix of LLVM's code generator and the x86 backend. We tell the code
7483 // generator that boolean values in the elements of an x86 vector register
7484 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7485 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7486 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7487 // of the element (the remaining are ignored) and 0 in that high bit would
7488 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7489 // the LLVM model for boolean values in vector elements gets the relevant
7490 // bit set, it is set backwards and over constrained relative to x86's
7492 SDValue VSELECTMask[32];
7493 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7494 for (int j = 0; j < Scale; ++j)
7495 VSELECTMask[Scale * i + j] =
7496 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7497 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7499 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7500 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7502 ISD::BITCAST, DL, VT,
7503 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7504 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7509 llvm_unreachable("Not a supported integer vector type!");
7513 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7514 /// unblended shuffles followed by an unshuffled blend.
7516 /// This matches the extremely common pattern for handling combined
7517 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7519 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7523 SelectionDAG &DAG) {
7524 // Shuffle the input elements into the desired positions in V1 and V2 and
7525 // blend them together.
7526 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7527 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7528 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7529 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7530 if (Mask[i] >= 0 && Mask[i] < Size) {
7531 V1Mask[i] = Mask[i];
7533 } else if (Mask[i] >= Size) {
7534 V2Mask[i] = Mask[i] - Size;
7535 BlendMask[i] = i + Size;
7538 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7539 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7540 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7543 /// \brief Try to lower a vector shuffle as a byte rotation.
7545 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7546 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7547 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7548 /// try to generically lower a vector shuffle through such an pattern. It
7549 /// does not check for the profitability of lowering either as PALIGNR or
7550 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7551 /// This matches shuffle vectors that look like:
7553 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7555 /// Essentially it concatenates V1 and V2, shifts right by some number of
7556 /// elements, and takes the low elements as the result. Note that while this is
7557 /// specified as a *right shift* because x86 is little-endian, it is a *left
7558 /// rotate* of the vector lanes.
7560 /// Note that this only handles 128-bit vector widths currently.
7561 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7564 const X86Subtarget *Subtarget,
7565 SelectionDAG &DAG) {
7566 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7568 // We need to detect various ways of spelling a rotation:
7569 // [11, 12, 13, 14, 15, 0, 1, 2]
7570 // [-1, 12, 13, 14, -1, -1, 1, -1]
7571 // [-1, -1, -1, -1, -1, -1, 1, 2]
7572 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7573 // [-1, 4, 5, 6, -1, -1, 9, -1]
7574 // [-1, 4, 5, 6, -1, -1, -1, -1]
7577 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7580 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7582 // Based on the mod-Size value of this mask element determine where
7583 // a rotated vector would have started.
7584 int StartIdx = i - (Mask[i] % Size);
7586 // The identity rotation isn't interesting, stop.
7589 // If we found the tail of a vector the rotation must be the missing
7590 // front. If we found the head of a vector, it must be how much of the head.
7591 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7594 Rotation = CandidateRotation;
7595 else if (Rotation != CandidateRotation)
7596 // The rotations don't match, so we can't match this mask.
7599 // Compute which value this mask is pointing at.
7600 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7602 // Compute which of the two target values this index should be assigned to.
7603 // This reflects whether the high elements are remaining or the low elements
7605 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7607 // Either set up this value if we've not encountered it before, or check
7608 // that it remains consistent.
7611 else if (TargetV != MaskV)
7612 // This may be a rotation, but it pulls from the inputs in some
7613 // unsupported interleaving.
7617 // Check that we successfully analyzed the mask, and normalize the results.
7618 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7619 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7625 assert(VT.getSizeInBits() == 128 &&
7626 "Rotate-based lowering only supports 128-bit lowering!");
7627 assert(Mask.size() <= 16 &&
7628 "Can shuffle at most 16 bytes in a 128-bit vector!");
7630 // The actual rotate instruction rotates bytes, so we need to scale the
7631 // rotation based on how many bytes are in the vector.
7632 int Scale = 16 / Mask.size();
7634 // SSSE3 targets can use the palignr instruction
7635 if (Subtarget->hasSSSE3()) {
7636 // Cast the inputs to v16i8 to match PALIGNR.
7637 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7638 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7640 return DAG.getNode(ISD::BITCAST, DL, VT,
7641 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7642 DAG.getConstant(Rotation * Scale, MVT::i8)));
7645 // Default SSE2 implementation
7646 int LoByteShift = 16 - Rotation * Scale;
7647 int HiByteShift = Rotation * Scale;
7649 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7650 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7651 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7653 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7654 DAG.getConstant(8 * LoByteShift, MVT::i8));
7655 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7656 DAG.getConstant(8 * HiByteShift, MVT::i8));
7657 return DAG.getNode(ISD::BITCAST, DL, VT,
7658 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7661 /// \brief Compute whether each element of a shuffle is zeroable.
7663 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7664 /// Either it is an undef element in the shuffle mask, the element of the input
7665 /// referenced is undef, or the element of the input referenced is known to be
7666 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7667 /// as many lanes with this technique as possible to simplify the remaining
7669 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7670 SDValue V1, SDValue V2) {
7671 SmallBitVector Zeroable(Mask.size(), false);
7673 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7674 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7676 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7678 // Handle the easy cases.
7679 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7684 // If this is an index into a build_vector node, dig out the input value and
7686 SDValue V = M < Size ? V1 : V2;
7687 if (V.getOpcode() != ISD::BUILD_VECTOR)
7690 SDValue Input = V.getOperand(M % Size);
7691 // The UNDEF opcode check really should be dead code here, but not quite
7692 // worth asserting on (it isn't invalid, just unexpected).
7693 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7700 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7702 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7703 /// byte-shift instructions. The mask must consist of a shifted sequential
7704 /// shuffle from one of the input vectors and zeroable elements for the
7705 /// remaining 'shifted in' elements.
7707 /// Note that this only handles 128-bit vector widths currently.
7708 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7709 SDValue V2, ArrayRef<int> Mask,
7710 SelectionDAG &DAG) {
7711 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7713 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7715 int Size = Mask.size();
7716 int Scale = 16 / Size;
7718 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7719 ArrayRef<int> Mask) {
7720 for (int i = StartIndex; i < EndIndex; i++) {
7723 if (i + Base != Mask[i] - MaskOffset)
7729 for (int Shift = 1; Shift < Size; Shift++) {
7730 int ByteShift = Shift * Scale;
7732 // PSRLDQ : (little-endian) right byte shift
7733 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7734 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7735 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7736 bool ZeroableRight = true;
7737 for (int i = Size - Shift; i < Size; i++) {
7738 ZeroableRight &= Zeroable[i];
7741 if (ZeroableRight) {
7742 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7743 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7745 if (ValidShiftRight1 || ValidShiftRight2) {
7746 // Cast the inputs to v2i64 to match PSRLDQ.
7747 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7748 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7749 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7750 DAG.getConstant(ByteShift * 8, MVT::i8));
7751 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7755 // PSLLDQ : (little-endian) left byte shift
7756 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7757 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7758 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7759 bool ZeroableLeft = true;
7760 for (int i = 0; i < Shift; i++) {
7761 ZeroableLeft &= Zeroable[i];
7765 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7766 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7768 if (ValidShiftLeft1 || ValidShiftLeft2) {
7769 // Cast the inputs to v2i64 to match PSLLDQ.
7770 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7771 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7772 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7773 DAG.getConstant(ByteShift * 8, MVT::i8));
7774 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7782 /// \brief Lower a vector shuffle as a zero or any extension.
7784 /// Given a specific number of elements, element bit width, and extension
7785 /// stride, produce either a zero or any extension based on the available
7786 /// features of the subtarget.
7787 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7788 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7789 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7790 assert(Scale > 1 && "Need a scale to extend.");
7791 int EltBits = VT.getSizeInBits() / NumElements;
7792 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7793 "Only 8, 16, and 32 bit elements can be extended.");
7794 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7796 // Found a valid zext mask! Try various lowering strategies based on the
7797 // input type and available ISA extensions.
7798 if (Subtarget->hasSSE41()) {
7799 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7800 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7801 NumElements / Scale);
7802 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7803 return DAG.getNode(ISD::BITCAST, DL, VT,
7804 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7807 // For any extends we can cheat for larger element sizes and use shuffle
7808 // instructions that can fold with a load and/or copy.
7809 if (AnyExt && EltBits == 32) {
7810 int PSHUFDMask[4] = {0, -1, 1, -1};
7812 ISD::BITCAST, DL, VT,
7813 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7814 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7815 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7817 if (AnyExt && EltBits == 16 && Scale > 2) {
7818 int PSHUFDMask[4] = {0, -1, 0, -1};
7819 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7820 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7821 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7822 int PSHUFHWMask[4] = {1, -1, -1, -1};
7824 ISD::BITCAST, DL, VT,
7825 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7826 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7827 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7830 // If this would require more than 2 unpack instructions to expand, use
7831 // pshufb when available. We can only use more than 2 unpack instructions
7832 // when zero extending i8 elements which also makes it easier to use pshufb.
7833 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7834 assert(NumElements == 16 && "Unexpected byte vector width!");
7835 SDValue PSHUFBMask[16];
7836 for (int i = 0; i < 16; ++i)
7838 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7839 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7840 return DAG.getNode(ISD::BITCAST, DL, VT,
7841 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7842 DAG.getNode(ISD::BUILD_VECTOR, DL,
7843 MVT::v16i8, PSHUFBMask)));
7846 // Otherwise emit a sequence of unpacks.
7848 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7849 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7850 : getZeroVector(InputVT, Subtarget, DAG, DL);
7851 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7852 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7856 } while (Scale > 1);
7857 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7860 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7862 /// This routine will try to do everything in its power to cleverly lower
7863 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7864 /// check for the profitability of this lowering, it tries to aggressively
7865 /// match this pattern. It will use all of the micro-architectural details it
7866 /// can to emit an efficient lowering. It handles both blends with all-zero
7867 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7868 /// masking out later).
7870 /// The reason we have dedicated lowering for zext-style shuffles is that they
7871 /// are both incredibly common and often quite performance sensitive.
7872 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7873 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7874 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7875 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7877 int Bits = VT.getSizeInBits();
7878 int NumElements = Mask.size();
7880 // Define a helper function to check a particular ext-scale and lower to it if
7882 auto Lower = [&](int Scale) -> SDValue {
7885 for (int i = 0; i < NumElements; ++i) {
7887 continue; // Valid anywhere but doesn't tell us anything.
7888 if (i % Scale != 0) {
7889 // Each of the extend elements needs to be zeroable.
7893 // We no lorger are in the anyext case.
7898 // Each of the base elements needs to be consecutive indices into the
7899 // same input vector.
7900 SDValue V = Mask[i] < NumElements ? V1 : V2;
7903 else if (InputV != V)
7904 return SDValue(); // Flip-flopping inputs.
7906 if (Mask[i] % NumElements != i / Scale)
7907 return SDValue(); // Non-consecutive strided elemenst.
7910 // If we fail to find an input, we have a zero-shuffle which should always
7911 // have already been handled.
7912 // FIXME: Maybe handle this here in case during blending we end up with one?
7916 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7917 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7920 // The widest scale possible for extending is to a 64-bit integer.
7921 assert(Bits % 64 == 0 &&
7922 "The number of bits in a vector must be divisible by 64 on x86!");
7923 int NumExtElements = Bits / 64;
7925 // Each iteration, try extending the elements half as much, but into twice as
7927 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7928 assert(NumElements % NumExtElements == 0 &&
7929 "The input vector size must be divisble by the extended size.");
7930 if (SDValue V = Lower(NumElements / NumExtElements))
7934 // No viable ext lowering found.
7938 /// \brief Try to get a scalar value for a specific element of a vector.
7940 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7941 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7942 SelectionDAG &DAG) {
7943 MVT VT = V.getSimpleValueType();
7944 MVT EltVT = VT.getVectorElementType();
7945 while (V.getOpcode() == ISD::BITCAST)
7946 V = V.getOperand(0);
7947 // If the bitcasts shift the element size, we can't extract an equivalent
7949 MVT NewVT = V.getSimpleValueType();
7950 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7953 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7954 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7955 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7960 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7962 /// This is particularly important because the set of instructions varies
7963 /// significantly based on whether the operand is a load or not.
7964 static bool isShuffleFoldableLoad(SDValue V) {
7965 while (V.getOpcode() == ISD::BITCAST)
7966 V = V.getOperand(0);
7968 return ISD::isNON_EXTLoad(V.getNode());
7971 /// \brief Try to lower insertion of a single element into a zero vector.
7973 /// This is a common pattern that we have especially efficient patterns to lower
7974 /// across all subtarget feature sets.
7975 static SDValue lowerVectorShuffleAsElementInsertion(
7976 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7977 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7978 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7980 MVT EltVT = VT.getVectorElementType();
7982 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7983 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7985 bool IsV1Zeroable = true;
7986 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7987 if (i != V2Index && !Zeroable[i]) {
7988 IsV1Zeroable = false;
7992 // Check for a single input from a SCALAR_TO_VECTOR node.
7993 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7994 // all the smarts here sunk into that routine. However, the current
7995 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7996 // vector shuffle lowering is dead.
7997 if (SDValue V2S = getScalarValueForVectorElement(
7998 V2, Mask[V2Index] - Mask.size(), DAG)) {
7999 // We need to zext the scalar if it is smaller than an i32.
8000 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8001 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8002 // Using zext to expand a narrow element won't work for non-zero
8007 // Zero-extend directly to i32.
8009 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8011 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8012 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8013 EltVT == MVT::i16) {
8014 // Either not inserting from the low element of the input or the input
8015 // element size is too small to use VZEXT_MOVL to clear the high bits.
8019 if (!IsV1Zeroable) {
8020 // If V1 can't be treated as a zero vector we have fewer options to lower
8021 // this. We can't support integer vectors or non-zero targets cheaply, and
8022 // the V1 elements can't be permuted in any way.
8023 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8024 if (!VT.isFloatingPoint() || V2Index != 0)
8026 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8027 V1Mask[V2Index] = -1;
8028 if (!isNoopShuffleMask(V1Mask))
8030 // This is essentially a special case blend operation, but if we have
8031 // general purpose blend operations, they are always faster. Bail and let
8032 // the rest of the lowering handle these as blends.
8033 if (Subtarget->hasSSE41())
8036 // Otherwise, use MOVSD or MOVSS.
8037 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8038 "Only two types of floating point element types to handle!");
8039 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8043 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8045 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8048 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8049 // the desired position. Otherwise it is more efficient to do a vector
8050 // shift left. We know that we can do a vector shift left because all
8051 // the inputs are zero.
8052 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8053 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8054 V2Shuffle[V2Index] = 0;
8055 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8057 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8059 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8061 V2Index * EltVT.getSizeInBits(),
8062 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8063 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8069 /// \brief Try to lower broadcast of a single element.
8071 /// For convenience, this code also bundles all of the subtarget feature set
8072 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8073 /// a convenient way to factor it out.
8074 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8076 const X86Subtarget *Subtarget,
8077 SelectionDAG &DAG) {
8078 if (!Subtarget->hasAVX())
8080 if (VT.isInteger() && !Subtarget->hasAVX2())
8083 // Check that the mask is a broadcast.
8084 int BroadcastIdx = -1;
8086 if (M >= 0 && BroadcastIdx == -1)
8088 else if (M >= 0 && M != BroadcastIdx)
8091 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8092 "a sorted mask where the broadcast "
8095 // Go up the chain of (vector) values to try and find a scalar load that
8096 // we can combine with the broadcast.
8098 switch (V.getOpcode()) {
8099 case ISD::CONCAT_VECTORS: {
8100 int OperandSize = Mask.size() / V.getNumOperands();
8101 V = V.getOperand(BroadcastIdx / OperandSize);
8102 BroadcastIdx %= OperandSize;
8106 case ISD::INSERT_SUBVECTOR: {
8107 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8108 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8112 int BeginIdx = (int)ConstantIdx->getZExtValue();
8114 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8115 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8116 BroadcastIdx -= BeginIdx;
8127 // Check if this is a broadcast of a scalar. We special case lowering
8128 // for scalars so that we can more effectively fold with loads.
8129 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8130 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8131 V = V.getOperand(BroadcastIdx);
8133 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8135 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8137 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8138 // We can't broadcast from a vector register w/o AVX2, and we can only
8139 // broadcast from the zero-element of a vector register.
8143 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8146 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8148 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8149 /// support for floating point shuffles but not integer shuffles. These
8150 /// instructions will incur a domain crossing penalty on some chips though so
8151 /// it is better to avoid lowering through this for integer vectors where
8153 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8154 const X86Subtarget *Subtarget,
8155 SelectionDAG &DAG) {
8157 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8158 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8159 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8161 ArrayRef<int> Mask = SVOp->getMask();
8162 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8164 if (isSingleInputShuffleMask(Mask)) {
8165 // Straight shuffle of a single input vector. Simulate this by using the
8166 // single input as both of the "inputs" to this instruction..
8167 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8169 if (Subtarget->hasAVX()) {
8170 // If we have AVX, we can use VPERMILPS which will allow folding a load
8171 // into the shuffle.
8172 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8173 DAG.getConstant(SHUFPDMask, MVT::i8));
8176 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8177 DAG.getConstant(SHUFPDMask, MVT::i8));
8179 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8180 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8182 // Use dedicated unpack instructions for masks that match their pattern.
8183 if (isShuffleEquivalent(Mask, 0, 2))
8184 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8185 if (isShuffleEquivalent(Mask, 1, 3))
8186 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8188 // If we have a single input, insert that into V1 if we can do so cheaply.
8189 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8190 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8191 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8193 // Try inverting the insertion since for v2 masks it is easy to do and we
8194 // can't reliably sort the mask one way or the other.
8195 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8196 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8197 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8198 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8202 // Try to use one of the special instruction patterns to handle two common
8203 // blend patterns if a zero-blend above didn't work.
8204 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8205 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8206 // We can either use a special instruction to load over the low double or
8207 // to move just the low double.
8209 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8211 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8213 if (Subtarget->hasSSE41())
8214 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8218 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8219 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8220 DAG.getConstant(SHUFPDMask, MVT::i8));
8223 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8225 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8226 /// the integer unit to minimize domain crossing penalties. However, for blends
8227 /// it falls back to the floating point shuffle operation with appropriate bit
8229 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8230 const X86Subtarget *Subtarget,
8231 SelectionDAG &DAG) {
8233 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8234 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8235 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8237 ArrayRef<int> Mask = SVOp->getMask();
8238 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8240 if (isSingleInputShuffleMask(Mask)) {
8241 // Check for being able to broadcast a single element.
8242 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8243 Mask, Subtarget, DAG))
8246 // Straight shuffle of a single input vector. For everything from SSE2
8247 // onward this has a single fast instruction with no scary immediates.
8248 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8249 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8250 int WidenedMask[4] = {
8251 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8252 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8254 ISD::BITCAST, DL, MVT::v2i64,
8255 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8256 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8259 // Try to use byte shift instructions.
8260 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8261 DL, MVT::v2i64, V1, V2, Mask, DAG))
8264 // If we have a single input from V2 insert that into V1 if we can do so
8266 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8267 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8268 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8270 // Try inverting the insertion since for v2 masks it is easy to do and we
8271 // can't reliably sort the mask one way or the other.
8272 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8273 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8274 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8275 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8279 // Use dedicated unpack instructions for masks that match their pattern.
8280 if (isShuffleEquivalent(Mask, 0, 2))
8281 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8282 if (isShuffleEquivalent(Mask, 1, 3))
8283 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8285 if (Subtarget->hasSSE41())
8286 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8290 // Try to use byte rotation instructions.
8291 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8292 if (Subtarget->hasSSSE3())
8293 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8294 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8297 // We implement this with SHUFPD which is pretty lame because it will likely
8298 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8299 // However, all the alternatives are still more cycles and newer chips don't
8300 // have this problem. It would be really nice if x86 had better shuffles here.
8301 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8302 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8303 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8304 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8307 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8309 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8310 /// It makes no assumptions about whether this is the *best* lowering, it simply
8312 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8313 ArrayRef<int> Mask, SDValue V1,
8314 SDValue V2, SelectionDAG &DAG) {
8315 SDValue LowV = V1, HighV = V2;
8316 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8319 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8321 if (NumV2Elements == 1) {
8323 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8326 // Compute the index adjacent to V2Index and in the same half by toggling
8328 int V2AdjIndex = V2Index ^ 1;
8330 if (Mask[V2AdjIndex] == -1) {
8331 // Handles all the cases where we have a single V2 element and an undef.
8332 // This will only ever happen in the high lanes because we commute the
8333 // vector otherwise.
8335 std::swap(LowV, HighV);
8336 NewMask[V2Index] -= 4;
8338 // Handle the case where the V2 element ends up adjacent to a V1 element.
8339 // To make this work, blend them together as the first step.
8340 int V1Index = V2AdjIndex;
8341 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8342 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8343 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8345 // Now proceed to reconstruct the final blend as we have the necessary
8346 // high or low half formed.
8353 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8354 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8356 } else if (NumV2Elements == 2) {
8357 if (Mask[0] < 4 && Mask[1] < 4) {
8358 // Handle the easy case where we have V1 in the low lanes and V2 in the
8362 } else if (Mask[2] < 4 && Mask[3] < 4) {
8363 // We also handle the reversed case because this utility may get called
8364 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8365 // arrange things in the right direction.
8371 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8372 // trying to place elements directly, just blend them and set up the final
8373 // shuffle to place them.
8375 // The first two blend mask elements are for V1, the second two are for
8377 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8378 Mask[2] < 4 ? Mask[2] : Mask[3],
8379 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8380 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8381 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8382 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8384 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8387 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8388 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8389 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8390 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8393 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8394 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8397 /// \brief Lower 4-lane 32-bit floating point shuffles.
8399 /// Uses instructions exclusively from the floating point unit to minimize
8400 /// domain crossing penalties, as these are sufficient to implement all v4f32
8402 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8403 const X86Subtarget *Subtarget,
8404 SelectionDAG &DAG) {
8406 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8407 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8408 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8409 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8410 ArrayRef<int> Mask = SVOp->getMask();
8411 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8414 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8416 if (NumV2Elements == 0) {
8417 // Check for being able to broadcast a single element.
8418 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8419 Mask, Subtarget, DAG))
8422 if (Subtarget->hasAVX()) {
8423 // If we have AVX, we can use VPERMILPS which will allow folding a load
8424 // into the shuffle.
8425 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8426 getV4X86ShuffleImm8ForMask(Mask, DAG));
8429 // Otherwise, use a straight shuffle of a single input vector. We pass the
8430 // input vector to both operands to simulate this with a SHUFPS.
8431 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8432 getV4X86ShuffleImm8ForMask(Mask, DAG));
8435 // Use dedicated unpack instructions for masks that match their pattern.
8436 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8437 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8438 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8439 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8441 // There are special ways we can lower some single-element blends. However, we
8442 // have custom ways we can lower more complex single-element blends below that
8443 // we defer to if both this and BLENDPS fail to match, so restrict this to
8444 // when the V2 input is targeting element 0 of the mask -- that is the fast
8446 if (NumV2Elements == 1 && Mask[0] >= 4)
8447 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8448 Mask, Subtarget, DAG))
8451 if (Subtarget->hasSSE41())
8452 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8456 // Check for whether we can use INSERTPS to perform the blend. We only use
8457 // INSERTPS when the V1 elements are already in the correct locations
8458 // because otherwise we can just always use two SHUFPS instructions which
8459 // are much smaller to encode than a SHUFPS and an INSERTPS.
8460 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8462 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8465 // When using INSERTPS we can zero any lane of the destination. Collect
8466 // the zero inputs into a mask and drop them from the lanes of V1 which
8467 // actually need to be present as inputs to the INSERTPS.
8468 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8470 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8471 bool InsertNeedsShuffle = false;
8473 for (int i = 0; i < 4; ++i)
8477 } else if (Mask[i] != i) {
8478 InsertNeedsShuffle = true;
8483 // We don't want to use INSERTPS or other insertion techniques if it will
8484 // require shuffling anyways.
8485 if (!InsertNeedsShuffle) {
8486 // If all of V1 is zeroable, replace it with undef.
8487 if ((ZMask | 1 << V2Index) == 0xF)
8488 V1 = DAG.getUNDEF(MVT::v4f32);
8490 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8491 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8493 // Insert the V2 element into the desired position.
8494 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8495 DAG.getConstant(InsertPSMask, MVT::i8));
8499 // Otherwise fall back to a SHUFPS lowering strategy.
8500 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8503 /// \brief Lower 4-lane i32 vector shuffles.
8505 /// We try to handle these with integer-domain shuffles where we can, but for
8506 /// blends we use the floating point domain blend instructions.
8507 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8508 const X86Subtarget *Subtarget,
8509 SelectionDAG &DAG) {
8511 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8512 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8513 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8515 ArrayRef<int> Mask = SVOp->getMask();
8516 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8518 // Whenever we can lower this as a zext, that instruction is strictly faster
8519 // than any alternative. It also allows us to fold memory operands into the
8520 // shuffle in many cases.
8521 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8522 Mask, Subtarget, DAG))
8526 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8528 if (NumV2Elements == 0) {
8529 // Check for being able to broadcast a single element.
8530 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8531 Mask, Subtarget, DAG))
8534 // Straight shuffle of a single input vector. For everything from SSE2
8535 // onward this has a single fast instruction with no scary immediates.
8536 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8537 // but we aren't actually going to use the UNPCK instruction because doing
8538 // so prevents folding a load into this instruction or making a copy.
8539 const int UnpackLoMask[] = {0, 0, 1, 1};
8540 const int UnpackHiMask[] = {2, 2, 3, 3};
8541 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8542 Mask = UnpackLoMask;
8543 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8544 Mask = UnpackHiMask;
8546 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8547 getV4X86ShuffleImm8ForMask(Mask, DAG));
8550 // Try to use byte shift instructions.
8551 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8552 DL, MVT::v4i32, V1, V2, Mask, DAG))
8555 // There are special ways we can lower some single-element blends.
8556 if (NumV2Elements == 1)
8557 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8558 Mask, Subtarget, DAG))
8561 // Use dedicated unpack instructions for masks that match their pattern.
8562 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8563 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8564 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8565 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8567 if (Subtarget->hasSSE41())
8568 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8572 // Try to use byte rotation instructions.
8573 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8574 if (Subtarget->hasSSSE3())
8575 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8576 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8579 // We implement this with SHUFPS because it can blend from two vectors.
8580 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8581 // up the inputs, bypassing domain shift penalties that we would encur if we
8582 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8584 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8585 DAG.getVectorShuffle(
8587 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8588 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8591 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8592 /// shuffle lowering, and the most complex part.
8594 /// The lowering strategy is to try to form pairs of input lanes which are
8595 /// targeted at the same half of the final vector, and then use a dword shuffle
8596 /// to place them onto the right half, and finally unpack the paired lanes into
8597 /// their final position.
8599 /// The exact breakdown of how to form these dword pairs and align them on the
8600 /// correct sides is really tricky. See the comments within the function for
8601 /// more of the details.
8602 static SDValue lowerV8I16SingleInputVectorShuffle(
8603 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8604 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8605 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8606 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8607 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8609 SmallVector<int, 4> LoInputs;
8610 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8611 [](int M) { return M >= 0; });
8612 std::sort(LoInputs.begin(), LoInputs.end());
8613 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8614 SmallVector<int, 4> HiInputs;
8615 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8616 [](int M) { return M >= 0; });
8617 std::sort(HiInputs.begin(), HiInputs.end());
8618 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8620 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8621 int NumHToL = LoInputs.size() - NumLToL;
8623 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8624 int NumHToH = HiInputs.size() - NumLToH;
8625 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8626 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8627 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8628 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8630 // Check for being able to broadcast a single element.
8631 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8632 Mask, Subtarget, DAG))
8635 // Try to use byte shift instructions.
8636 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8637 DL, MVT::v8i16, V, V, Mask, DAG))
8640 // Use dedicated unpack instructions for masks that match their pattern.
8641 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8642 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8643 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8644 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8646 // Try to use byte rotation instructions.
8647 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8648 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8651 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8652 // such inputs we can swap two of the dwords across the half mark and end up
8653 // with <=2 inputs to each half in each half. Once there, we can fall through
8654 // to the generic code below. For example:
8656 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8657 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8659 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8660 // and an existing 2-into-2 on the other half. In this case we may have to
8661 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8662 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8663 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8664 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8665 // half than the one we target for fixing) will be fixed when we re-enter this
8666 // path. We will also combine away any sequence of PSHUFD instructions that
8667 // result into a single instruction. Here is an example of the tricky case:
8669 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8670 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8672 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8674 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8675 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8677 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8678 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8680 // The result is fine to be handled by the generic logic.
8681 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8682 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8683 int AOffset, int BOffset) {
8684 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8685 "Must call this with A having 3 or 1 inputs from the A half.");
8686 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8687 "Must call this with B having 1 or 3 inputs from the B half.");
8688 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8689 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8691 // Compute the index of dword with only one word among the three inputs in
8692 // a half by taking the sum of the half with three inputs and subtracting
8693 // the sum of the actual three inputs. The difference is the remaining
8696 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8697 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8698 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8699 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8700 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8701 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8702 int TripleNonInputIdx =
8703 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8704 TripleDWord = TripleNonInputIdx / 2;
8706 // We use xor with one to compute the adjacent DWord to whichever one the
8708 OneInputDWord = (OneInput / 2) ^ 1;
8710 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8711 // and BToA inputs. If there is also such a problem with the BToB and AToB
8712 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8713 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8714 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8715 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8716 // Compute how many inputs will be flipped by swapping these DWords. We
8718 // to balance this to ensure we don't form a 3-1 shuffle in the other
8720 int NumFlippedAToBInputs =
8721 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8722 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8723 int NumFlippedBToBInputs =
8724 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8725 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8726 if ((NumFlippedAToBInputs == 1 &&
8727 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8728 (NumFlippedBToBInputs == 1 &&
8729 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8730 // We choose whether to fix the A half or B half based on whether that
8731 // half has zero flipped inputs. At zero, we may not be able to fix it
8732 // with that half. We also bias towards fixing the B half because that
8733 // will more commonly be the high half, and we have to bias one way.
8734 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8735 ArrayRef<int> Inputs) {
8736 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8737 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8738 PinnedIdx ^ 1) != Inputs.end();
8739 // Determine whether the free index is in the flipped dword or the
8740 // unflipped dword based on where the pinned index is. We use this bit
8741 // in an xor to conditionally select the adjacent dword.
8742 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8743 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8744 FixFreeIdx) != Inputs.end();
8745 if (IsFixIdxInput == IsFixFreeIdxInput)
8747 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8748 FixFreeIdx) != Inputs.end();
8749 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8750 "We need to be changing the number of flipped inputs!");
8751 int PSHUFHalfMask[] = {0, 1, 2, 3};
8752 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8753 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8755 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8758 if (M != -1 && M == FixIdx)
8760 else if (M != -1 && M == FixFreeIdx)
8763 if (NumFlippedBToBInputs != 0) {
8765 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8766 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8768 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8770 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8771 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8776 int PSHUFDMask[] = {0, 1, 2, 3};
8777 PSHUFDMask[ADWord] = BDWord;
8778 PSHUFDMask[BDWord] = ADWord;
8779 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8780 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8781 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8782 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8784 // Adjust the mask to match the new locations of A and B.
8786 if (M != -1 && M/2 == ADWord)
8787 M = 2 * BDWord + M % 2;
8788 else if (M != -1 && M/2 == BDWord)
8789 M = 2 * ADWord + M % 2;
8791 // Recurse back into this routine to re-compute state now that this isn't
8792 // a 3 and 1 problem.
8793 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8796 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8797 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8798 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8799 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8801 // At this point there are at most two inputs to the low and high halves from
8802 // each half. That means the inputs can always be grouped into dwords and
8803 // those dwords can then be moved to the correct half with a dword shuffle.
8804 // We use at most one low and one high word shuffle to collect these paired
8805 // inputs into dwords, and finally a dword shuffle to place them.
8806 int PSHUFLMask[4] = {-1, -1, -1, -1};
8807 int PSHUFHMask[4] = {-1, -1, -1, -1};
8808 int PSHUFDMask[4] = {-1, -1, -1, -1};
8810 // First fix the masks for all the inputs that are staying in their
8811 // original halves. This will then dictate the targets of the cross-half
8813 auto fixInPlaceInputs =
8814 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8815 MutableArrayRef<int> SourceHalfMask,
8816 MutableArrayRef<int> HalfMask, int HalfOffset) {
8817 if (InPlaceInputs.empty())
8819 if (InPlaceInputs.size() == 1) {
8820 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8821 InPlaceInputs[0] - HalfOffset;
8822 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8825 if (IncomingInputs.empty()) {
8826 // Just fix all of the in place inputs.
8827 for (int Input : InPlaceInputs) {
8828 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8829 PSHUFDMask[Input / 2] = Input / 2;
8834 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8835 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8836 InPlaceInputs[0] - HalfOffset;
8837 // Put the second input next to the first so that they are packed into
8838 // a dword. We find the adjacent index by toggling the low bit.
8839 int AdjIndex = InPlaceInputs[0] ^ 1;
8840 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8841 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8842 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8844 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8845 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8847 // Now gather the cross-half inputs and place them into a free dword of
8848 // their target half.
8849 // FIXME: This operation could almost certainly be simplified dramatically to
8850 // look more like the 3-1 fixing operation.
8851 auto moveInputsToRightHalf = [&PSHUFDMask](
8852 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8853 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8854 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8856 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8857 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8859 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8861 int LowWord = Word & ~1;
8862 int HighWord = Word | 1;
8863 return isWordClobbered(SourceHalfMask, LowWord) ||
8864 isWordClobbered(SourceHalfMask, HighWord);
8867 if (IncomingInputs.empty())
8870 if (ExistingInputs.empty()) {
8871 // Map any dwords with inputs from them into the right half.
8872 for (int Input : IncomingInputs) {
8873 // If the source half mask maps over the inputs, turn those into
8874 // swaps and use the swapped lane.
8875 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8876 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8877 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8878 Input - SourceOffset;
8879 // We have to swap the uses in our half mask in one sweep.
8880 for (int &M : HalfMask)
8881 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8883 else if (M == Input)
8884 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8886 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8887 Input - SourceOffset &&
8888 "Previous placement doesn't match!");
8890 // Note that this correctly re-maps both when we do a swap and when
8891 // we observe the other side of the swap above. We rely on that to
8892 // avoid swapping the members of the input list directly.
8893 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8896 // Map the input's dword into the correct half.
8897 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8898 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8900 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8902 "Previous placement doesn't match!");
8905 // And just directly shift any other-half mask elements to be same-half
8906 // as we will have mirrored the dword containing the element into the
8907 // same position within that half.
8908 for (int &M : HalfMask)
8909 if (M >= SourceOffset && M < SourceOffset + 4) {
8910 M = M - SourceOffset + DestOffset;
8911 assert(M >= 0 && "This should never wrap below zero!");
8916 // Ensure we have the input in a viable dword of its current half. This
8917 // is particularly tricky because the original position may be clobbered
8918 // by inputs being moved and *staying* in that half.
8919 if (IncomingInputs.size() == 1) {
8920 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8921 int InputFixed = std::find(std::begin(SourceHalfMask),
8922 std::end(SourceHalfMask), -1) -
8923 std::begin(SourceHalfMask) + SourceOffset;
8924 SourceHalfMask[InputFixed - SourceOffset] =
8925 IncomingInputs[0] - SourceOffset;
8926 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8928 IncomingInputs[0] = InputFixed;
8930 } else if (IncomingInputs.size() == 2) {
8931 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8932 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8933 // We have two non-adjacent or clobbered inputs we need to extract from
8934 // the source half. To do this, we need to map them into some adjacent
8935 // dword slot in the source mask.
8936 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8937 IncomingInputs[1] - SourceOffset};
8939 // If there is a free slot in the source half mask adjacent to one of
8940 // the inputs, place the other input in it. We use (Index XOR 1) to
8941 // compute an adjacent index.
8942 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8943 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8944 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8945 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8946 InputsFixed[1] = InputsFixed[0] ^ 1;
8947 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8948 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8949 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8950 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8951 InputsFixed[0] = InputsFixed[1] ^ 1;
8952 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8953 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8954 // The two inputs are in the same DWord but it is clobbered and the
8955 // adjacent DWord isn't used at all. Move both inputs to the free
8957 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8958 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8959 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8960 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8962 // The only way we hit this point is if there is no clobbering
8963 // (because there are no off-half inputs to this half) and there is no
8964 // free slot adjacent to one of the inputs. In this case, we have to
8965 // swap an input with a non-input.
8966 for (int i = 0; i < 4; ++i)
8967 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8968 "We can't handle any clobbers here!");
8969 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8970 "Cannot have adjacent inputs here!");
8972 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8973 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8975 // We also have to update the final source mask in this case because
8976 // it may need to undo the above swap.
8977 for (int &M : FinalSourceHalfMask)
8978 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8979 M = InputsFixed[1] + SourceOffset;
8980 else if (M == InputsFixed[1] + SourceOffset)
8981 M = (InputsFixed[0] ^ 1) + SourceOffset;
8983 InputsFixed[1] = InputsFixed[0] ^ 1;
8986 // Point everything at the fixed inputs.
8987 for (int &M : HalfMask)
8988 if (M == IncomingInputs[0])
8989 M = InputsFixed[0] + SourceOffset;
8990 else if (M == IncomingInputs[1])
8991 M = InputsFixed[1] + SourceOffset;
8993 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8994 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8997 llvm_unreachable("Unhandled input size!");
9000 // Now hoist the DWord down to the right half.
9001 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9002 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9003 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9004 for (int &M : HalfMask)
9005 for (int Input : IncomingInputs)
9007 M = FreeDWord * 2 + Input % 2;
9009 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9010 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9011 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9012 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9014 // Now enact all the shuffles we've computed to move the inputs into their
9016 if (!isNoopShuffleMask(PSHUFLMask))
9017 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9018 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9019 if (!isNoopShuffleMask(PSHUFHMask))
9020 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9021 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9022 if (!isNoopShuffleMask(PSHUFDMask))
9023 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9024 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9025 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9026 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9028 // At this point, each half should contain all its inputs, and we can then
9029 // just shuffle them into their final position.
9030 assert(std::count_if(LoMask.begin(), LoMask.end(),
9031 [](int M) { return M >= 4; }) == 0 &&
9032 "Failed to lift all the high half inputs to the low mask!");
9033 assert(std::count_if(HiMask.begin(), HiMask.end(),
9034 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9035 "Failed to lift all the low half inputs to the high mask!");
9037 // Do a half shuffle for the low mask.
9038 if (!isNoopShuffleMask(LoMask))
9039 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9040 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9042 // Do a half shuffle with the high mask after shifting its values down.
9043 for (int &M : HiMask)
9046 if (!isNoopShuffleMask(HiMask))
9047 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9048 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9053 /// \brief Detect whether the mask pattern should be lowered through
9056 /// This essentially tests whether viewing the mask as an interleaving of two
9057 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9058 /// lowering it through interleaving is a significantly better strategy.
9059 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9060 int NumEvenInputs[2] = {0, 0};
9061 int NumOddInputs[2] = {0, 0};
9062 int NumLoInputs[2] = {0, 0};
9063 int NumHiInputs[2] = {0, 0};
9064 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9068 int InputIdx = Mask[i] >= Size;
9071 ++NumLoInputs[InputIdx];
9073 ++NumHiInputs[InputIdx];
9076 ++NumEvenInputs[InputIdx];
9078 ++NumOddInputs[InputIdx];
9081 // The minimum number of cross-input results for both the interleaved and
9082 // split cases. If interleaving results in fewer cross-input results, return
9084 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9085 NumEvenInputs[0] + NumOddInputs[1]);
9086 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9087 NumLoInputs[0] + NumHiInputs[1]);
9088 return InterleavedCrosses < SplitCrosses;
9091 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9093 /// This strategy only works when the inputs from each vector fit into a single
9094 /// half of that vector, and generally there are not so many inputs as to leave
9095 /// the in-place shuffles required highly constrained (and thus expensive). It
9096 /// shifts all the inputs into a single side of both input vectors and then
9097 /// uses an unpack to interleave these inputs in a single vector. At that
9098 /// point, we will fall back on the generic single input shuffle lowering.
9099 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9101 MutableArrayRef<int> Mask,
9102 const X86Subtarget *Subtarget,
9103 SelectionDAG &DAG) {
9104 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9105 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9106 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9107 for (int i = 0; i < 8; ++i)
9108 if (Mask[i] >= 0 && Mask[i] < 4)
9109 LoV1Inputs.push_back(i);
9110 else if (Mask[i] >= 4 && Mask[i] < 8)
9111 HiV1Inputs.push_back(i);
9112 else if (Mask[i] >= 8 && Mask[i] < 12)
9113 LoV2Inputs.push_back(i);
9114 else if (Mask[i] >= 12)
9115 HiV2Inputs.push_back(i);
9117 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9118 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9121 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9122 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9123 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9125 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9126 HiV1Inputs.size() + HiV2Inputs.size();
9128 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9129 ArrayRef<int> HiInputs, bool MoveToLo,
9131 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9132 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9133 if (BadInputs.empty())
9136 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9137 int MoveOffset = MoveToLo ? 0 : 4;
9139 if (GoodInputs.empty()) {
9140 for (int BadInput : BadInputs) {
9141 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9142 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9145 if (GoodInputs.size() == 2) {
9146 // If the low inputs are spread across two dwords, pack them into
9148 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9149 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9150 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9151 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9153 // Otherwise pin the good inputs.
9154 for (int GoodInput : GoodInputs)
9155 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9158 if (BadInputs.size() == 2) {
9159 // If we have two bad inputs then there may be either one or two good
9160 // inputs fixed in place. Find a fixed input, and then find the *other*
9161 // two adjacent indices by using modular arithmetic.
9163 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9164 [](int M) { return M >= 0; }) -
9165 std::begin(MoveMask);
9167 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9168 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9169 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9170 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9171 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9172 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9173 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9175 assert(BadInputs.size() == 1 && "All sizes handled");
9176 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9177 std::end(MoveMask), -1) -
9178 std::begin(MoveMask);
9179 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9180 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9184 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9187 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9189 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9192 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9193 // cross-half traffic in the final shuffle.
9195 // Munge the mask to be a single-input mask after the unpack merges the
9199 M = 2 * (M % 4) + (M / 8);
9201 return DAG.getVectorShuffle(
9202 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9203 DL, MVT::v8i16, V1, V2),
9204 DAG.getUNDEF(MVT::v8i16), Mask);
9207 /// \brief Generic lowering of 8-lane i16 shuffles.
9209 /// This handles both single-input shuffles and combined shuffle/blends with
9210 /// two inputs. The single input shuffles are immediately delegated to
9211 /// a dedicated lowering routine.
9213 /// The blends are lowered in one of three fundamental ways. If there are few
9214 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9215 /// of the input is significantly cheaper when lowered as an interleaving of
9216 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9217 /// halves of the inputs separately (making them have relatively few inputs)
9218 /// and then concatenate them.
9219 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9220 const X86Subtarget *Subtarget,
9221 SelectionDAG &DAG) {
9223 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9224 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9225 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9226 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9227 ArrayRef<int> OrigMask = SVOp->getMask();
9228 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9229 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9230 MutableArrayRef<int> Mask(MaskStorage);
9232 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9234 // Whenever we can lower this as a zext, that instruction is strictly faster
9235 // than any alternative.
9236 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9237 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9240 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9241 auto isV2 = [](int M) { return M >= 8; };
9243 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9244 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9246 if (NumV2Inputs == 0)
9247 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9249 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9250 "to be V1-input shuffles.");
9252 // Try to use byte shift instructions.
9253 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9254 DL, MVT::v8i16, V1, V2, Mask, DAG))
9257 // There are special ways we can lower some single-element blends.
9258 if (NumV2Inputs == 1)
9259 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9260 Mask, Subtarget, DAG))
9263 // Use dedicated unpack instructions for masks that match their pattern.
9264 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9265 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9266 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9267 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9269 if (Subtarget->hasSSE41())
9270 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9274 // Try to use byte rotation instructions.
9275 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9276 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9279 if (NumV1Inputs + NumV2Inputs <= 4)
9280 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9282 // Check whether an interleaving lowering is likely to be more efficient.
9283 // This isn't perfect but it is a strong heuristic that tends to work well on
9284 // the kinds of shuffles that show up in practice.
9286 // FIXME: Handle 1x, 2x, and 4x interleaving.
9287 if (shouldLowerAsInterleaving(Mask)) {
9288 // FIXME: Figure out whether we should pack these into the low or high
9291 int EMask[8], OMask[8];
9292 for (int i = 0; i < 4; ++i) {
9293 EMask[i] = Mask[2*i];
9294 OMask[i] = Mask[2*i + 1];
9299 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9300 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9302 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9305 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9306 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9308 for (int i = 0; i < 4; ++i) {
9309 LoBlendMask[i] = Mask[i];
9310 HiBlendMask[i] = Mask[i + 4];
9313 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9314 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9315 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9316 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9318 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9319 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9322 /// \brief Check whether a compaction lowering can be done by dropping even
9323 /// elements and compute how many times even elements must be dropped.
9325 /// This handles shuffles which take every Nth element where N is a power of
9326 /// two. Example shuffle masks:
9328 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9329 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9330 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9331 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9332 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9333 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9335 /// Any of these lanes can of course be undef.
9337 /// This routine only supports N <= 3.
9338 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9341 /// \returns N above, or the number of times even elements must be dropped if
9342 /// there is such a number. Otherwise returns zero.
9343 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9344 // Figure out whether we're looping over two inputs or just one.
9345 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9347 // The modulus for the shuffle vector entries is based on whether this is
9348 // a single input or not.
9349 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9350 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9351 "We should only be called with masks with a power-of-2 size!");
9353 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9355 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9356 // and 2^3 simultaneously. This is because we may have ambiguity with
9357 // partially undef inputs.
9358 bool ViableForN[3] = {true, true, true};
9360 for (int i = 0, e = Mask.size(); i < e; ++i) {
9361 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9366 bool IsAnyViable = false;
9367 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9368 if (ViableForN[j]) {
9371 // The shuffle mask must be equal to (i * 2^N) % M.
9372 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9375 ViableForN[j] = false;
9377 // Early exit if we exhaust the possible powers of two.
9382 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9386 // Return 0 as there is no viable power of two.
9390 /// \brief Generic lowering of v16i8 shuffles.
9392 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9393 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9394 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9395 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9397 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9398 const X86Subtarget *Subtarget,
9399 SelectionDAG &DAG) {
9401 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9402 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9403 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9405 ArrayRef<int> OrigMask = SVOp->getMask();
9406 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9408 // Try to use byte shift instructions.
9409 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9410 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9413 // Try to use byte rotation instructions.
9414 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9415 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9418 // Try to use a zext lowering.
9419 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9420 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9423 int MaskStorage[16] = {
9424 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9425 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9426 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9427 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9428 MutableArrayRef<int> Mask(MaskStorage);
9429 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9430 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9433 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9435 // For single-input shuffles, there are some nicer lowering tricks we can use.
9436 if (NumV2Elements == 0) {
9437 // Check for being able to broadcast a single element.
9438 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9439 Mask, Subtarget, DAG))
9442 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9443 // Notably, this handles splat and partial-splat shuffles more efficiently.
9444 // However, it only makes sense if the pre-duplication shuffle simplifies
9445 // things significantly. Currently, this means we need to be able to
9446 // express the pre-duplication shuffle as an i16 shuffle.
9448 // FIXME: We should check for other patterns which can be widened into an
9449 // i16 shuffle as well.
9450 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9451 for (int i = 0; i < 16; i += 2)
9452 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9457 auto tryToWidenViaDuplication = [&]() -> SDValue {
9458 if (!canWidenViaDuplication(Mask))
9460 SmallVector<int, 4> LoInputs;
9461 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9462 [](int M) { return M >= 0 && M < 8; });
9463 std::sort(LoInputs.begin(), LoInputs.end());
9464 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9466 SmallVector<int, 4> HiInputs;
9467 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9468 [](int M) { return M >= 8; });
9469 std::sort(HiInputs.begin(), HiInputs.end());
9470 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9473 bool TargetLo = LoInputs.size() >= HiInputs.size();
9474 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9475 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9477 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9478 SmallDenseMap<int, int, 8> LaneMap;
9479 for (int I : InPlaceInputs) {
9480 PreDupI16Shuffle[I/2] = I/2;
9483 int j = TargetLo ? 0 : 4, je = j + 4;
9484 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9485 // Check if j is already a shuffle of this input. This happens when
9486 // there are two adjacent bytes after we move the low one.
9487 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9488 // If we haven't yet mapped the input, search for a slot into which
9490 while (j < je && PreDupI16Shuffle[j] != -1)
9494 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9497 // Map this input with the i16 shuffle.
9498 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9501 // Update the lane map based on the mapping we ended up with.
9502 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9505 ISD::BITCAST, DL, MVT::v16i8,
9506 DAG.getVectorShuffle(MVT::v8i16, DL,
9507 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9508 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9510 // Unpack the bytes to form the i16s that will be shuffled into place.
9511 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9512 MVT::v16i8, V1, V1);
9514 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9515 for (int i = 0; i < 16; ++i)
9516 if (Mask[i] != -1) {
9517 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9518 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9519 if (PostDupI16Shuffle[i / 2] == -1)
9520 PostDupI16Shuffle[i / 2] = MappedMask;
9522 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9523 "Conflicting entrties in the original shuffle!");
9526 ISD::BITCAST, DL, MVT::v16i8,
9527 DAG.getVectorShuffle(MVT::v8i16, DL,
9528 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9529 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9531 if (SDValue V = tryToWidenViaDuplication())
9535 // Check whether an interleaving lowering is likely to be more efficient.
9536 // This isn't perfect but it is a strong heuristic that tends to work well on
9537 // the kinds of shuffles that show up in practice.
9539 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9540 if (shouldLowerAsInterleaving(Mask)) {
9541 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9542 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9544 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9545 return (M >= 8 && M < 16) || M >= 24;
9547 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9548 -1, -1, -1, -1, -1, -1, -1, -1};
9549 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9550 -1, -1, -1, -1, -1, -1, -1, -1};
9551 bool UnpackLo = NumLoHalf >= NumHiHalf;
9552 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9553 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9554 for (int i = 0; i < 8; ++i) {
9555 TargetEMask[i] = Mask[2 * i];
9556 TargetOMask[i] = Mask[2 * i + 1];
9559 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9560 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9562 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9563 MVT::v16i8, Evens, Odds);
9566 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9567 // with PSHUFB. It is important to do this before we attempt to generate any
9568 // blends but after all of the single-input lowerings. If the single input
9569 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9570 // want to preserve that and we can DAG combine any longer sequences into
9571 // a PSHUFB in the end. But once we start blending from multiple inputs,
9572 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9573 // and there are *very* few patterns that would actually be faster than the
9574 // PSHUFB approach because of its ability to zero lanes.
9576 // FIXME: The only exceptions to the above are blends which are exact
9577 // interleavings with direct instructions supporting them. We currently don't
9578 // handle those well here.
9579 if (Subtarget->hasSSSE3()) {
9582 for (int i = 0; i < 16; ++i)
9583 if (Mask[i] == -1) {
9584 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9586 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9588 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9590 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9591 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9592 if (isSingleInputShuffleMask(Mask))
9593 return V1; // Single inputs are easy.
9595 // Otherwise, blend the two.
9596 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9598 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9601 // There are special ways we can lower some single-element blends.
9602 if (NumV2Elements == 1)
9603 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9604 Mask, Subtarget, DAG))
9607 // Check whether a compaction lowering can be done. This handles shuffles
9608 // which take every Nth element for some even N. See the helper function for
9611 // We special case these as they can be particularly efficiently handled with
9612 // the PACKUSB instruction on x86 and they show up in common patterns of
9613 // rearranging bytes to truncate wide elements.
9614 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9615 // NumEvenDrops is the power of two stride of the elements. Another way of
9616 // thinking about it is that we need to drop the even elements this many
9617 // times to get the original input.
9618 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9620 // First we need to zero all the dropped bytes.
9621 assert(NumEvenDrops <= 3 &&
9622 "No support for dropping even elements more than 3 times.");
9623 // We use the mask type to pick which bytes are preserved based on how many
9624 // elements are dropped.
9625 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9626 SDValue ByteClearMask =
9627 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9628 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9629 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9631 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9633 // Now pack things back together.
9634 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9635 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9636 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9637 for (int i = 1; i < NumEvenDrops; ++i) {
9638 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9639 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9645 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9646 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9647 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9648 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9650 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9651 MutableArrayRef<int> V1HalfBlendMask,
9652 MutableArrayRef<int> V2HalfBlendMask) {
9653 for (int i = 0; i < 8; ++i)
9654 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9655 V1HalfBlendMask[i] = HalfMask[i];
9657 } else if (HalfMask[i] >= 16) {
9658 V2HalfBlendMask[i] = HalfMask[i] - 16;
9659 HalfMask[i] = i + 8;
9662 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9663 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9665 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9667 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9668 MutableArrayRef<int> HiBlendMask) {
9670 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9671 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9673 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9674 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9675 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9676 [](int M) { return M >= 0 && M % 2 == 1; })) {
9677 // Use a mask to drop the high bytes.
9678 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9679 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9680 DAG.getConstant(0x00FF, MVT::v8i16));
9682 // This will be a single vector shuffle instead of a blend so nuke V2.
9683 V2 = DAG.getUNDEF(MVT::v8i16);
9685 // Squash the masks to point directly into V1.
9686 for (int &M : LoBlendMask)
9689 for (int &M : HiBlendMask)
9693 // Otherwise just unpack the low half of V into V1 and the high half into
9694 // V2 so that we can blend them as i16s.
9695 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9696 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9697 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9698 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9701 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9702 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9703 return std::make_pair(BlendedLo, BlendedHi);
9705 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9706 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9707 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9709 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9710 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9712 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9715 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9717 /// This routine breaks down the specific type of 128-bit shuffle and
9718 /// dispatches to the lowering routines accordingly.
9719 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9720 MVT VT, const X86Subtarget *Subtarget,
9721 SelectionDAG &DAG) {
9722 switch (VT.SimpleTy) {
9724 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9726 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9728 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9730 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9732 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9734 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9737 llvm_unreachable("Unimplemented!");
9741 /// \brief Helper function to test whether a shuffle mask could be
9742 /// simplified by widening the elements being shuffled.
9744 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9745 /// leaves it in an unspecified state.
9747 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9748 /// shuffle masks. The latter have the special property of a '-2' representing
9749 /// a zero-ed lane of a vector.
9750 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9751 SmallVectorImpl<int> &WidenedMask) {
9752 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9753 // If both elements are undef, its trivial.
9754 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9755 WidenedMask.push_back(SM_SentinelUndef);
9759 // Check for an undef mask and a mask value properly aligned to fit with
9760 // a pair of values. If we find such a case, use the non-undef mask's value.
9761 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9762 WidenedMask.push_back(Mask[i + 1] / 2);
9765 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9766 WidenedMask.push_back(Mask[i] / 2);
9770 // When zeroing, we need to spread the zeroing across both lanes to widen.
9771 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9772 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9773 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9774 WidenedMask.push_back(SM_SentinelZero);
9780 // Finally check if the two mask values are adjacent and aligned with
9782 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9783 WidenedMask.push_back(Mask[i] / 2);
9787 // Otherwise we can't safely widen the elements used in this shuffle.
9790 assert(WidenedMask.size() == Mask.size() / 2 &&
9791 "Incorrect size of mask after widening the elements!");
9796 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9798 /// This routine just extracts two subvectors, shuffles them independently, and
9799 /// then concatenates them back together. This should work effectively with all
9800 /// AVX vector shuffle types.
9801 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9802 SDValue V2, ArrayRef<int> Mask,
9803 SelectionDAG &DAG) {
9804 assert(VT.getSizeInBits() >= 256 &&
9805 "Only for 256-bit or wider vector shuffles!");
9806 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9807 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9809 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9810 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9812 int NumElements = VT.getVectorNumElements();
9813 int SplitNumElements = NumElements / 2;
9814 MVT ScalarVT = VT.getScalarType();
9815 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9817 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9818 DAG.getIntPtrConstant(0));
9819 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9820 DAG.getIntPtrConstant(SplitNumElements));
9821 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9822 DAG.getIntPtrConstant(0));
9823 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9824 DAG.getIntPtrConstant(SplitNumElements));
9826 // Now create two 4-way blends of these half-width vectors.
9827 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9828 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9829 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9830 for (int i = 0; i < SplitNumElements; ++i) {
9831 int M = HalfMask[i];
9832 if (M >= NumElements) {
9833 if (M >= NumElements + SplitNumElements)
9837 V2BlendMask.push_back(M - NumElements);
9838 V1BlendMask.push_back(-1);
9839 BlendMask.push_back(SplitNumElements + i);
9840 } else if (M >= 0) {
9841 if (M >= SplitNumElements)
9845 V2BlendMask.push_back(-1);
9846 V1BlendMask.push_back(M);
9847 BlendMask.push_back(i);
9849 V2BlendMask.push_back(-1);
9850 V1BlendMask.push_back(-1);
9851 BlendMask.push_back(-1);
9855 // Because the lowering happens after all combining takes place, we need to
9856 // manually combine these blend masks as much as possible so that we create
9857 // a minimal number of high-level vector shuffle nodes.
9859 // First try just blending the halves of V1 or V2.
9860 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9861 return DAG.getUNDEF(SplitVT);
9862 if (!UseLoV2 && !UseHiV2)
9863 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9864 if (!UseLoV1 && !UseHiV1)
9865 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9867 SDValue V1Blend, V2Blend;
9868 if (UseLoV1 && UseHiV1) {
9870 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9872 // We only use half of V1 so map the usage down into the final blend mask.
9873 V1Blend = UseLoV1 ? LoV1 : HiV1;
9874 for (int i = 0; i < SplitNumElements; ++i)
9875 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9876 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9878 if (UseLoV2 && UseHiV2) {
9880 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9882 // We only use half of V2 so map the usage down into the final blend mask.
9883 V2Blend = UseLoV2 ? LoV2 : HiV2;
9884 for (int i = 0; i < SplitNumElements; ++i)
9885 if (BlendMask[i] >= SplitNumElements)
9886 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9888 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9890 SDValue Lo = HalfBlend(LoMask);
9891 SDValue Hi = HalfBlend(HiMask);
9892 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9895 /// \brief Either split a vector in halves or decompose the shuffles and the
9898 /// This is provided as a good fallback for many lowerings of non-single-input
9899 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9900 /// between splitting the shuffle into 128-bit components and stitching those
9901 /// back together vs. extracting the single-input shuffles and blending those
9903 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9904 SDValue V2, ArrayRef<int> Mask,
9905 SelectionDAG &DAG) {
9906 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9907 "lower single-input shuffles as it "
9908 "could then recurse on itself.");
9909 int Size = Mask.size();
9911 // If this can be modeled as a broadcast of two elements followed by a blend,
9912 // prefer that lowering. This is especially important because broadcasts can
9913 // often fold with memory operands.
9914 auto DoBothBroadcast = [&] {
9915 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9918 if (V2BroadcastIdx == -1)
9919 V2BroadcastIdx = M - Size;
9920 else if (M - Size != V2BroadcastIdx)
9922 } else if (M >= 0) {
9923 if (V1BroadcastIdx == -1)
9925 else if (M != V1BroadcastIdx)
9930 if (DoBothBroadcast())
9931 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9934 // If the inputs all stem from a single 128-bit lane of each input, then we
9935 // split them rather than blending because the split will decompose to
9936 // unusually few instructions.
9937 int LaneCount = VT.getSizeInBits() / 128;
9938 int LaneSize = Size / LaneCount;
9939 SmallBitVector LaneInputs[2];
9940 LaneInputs[0].resize(LaneCount, false);
9941 LaneInputs[1].resize(LaneCount, false);
9942 for (int i = 0; i < Size; ++i)
9944 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9945 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9946 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9948 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9949 // that the decomposed single-input shuffles don't end up here.
9950 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9953 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9954 /// a permutation and blend of those lanes.
9956 /// This essentially blends the out-of-lane inputs to each lane into the lane
9957 /// from a permuted copy of the vector. This lowering strategy results in four
9958 /// instructions in the worst case for a single-input cross lane shuffle which
9959 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9960 /// of. Special cases for each particular shuffle pattern should be handled
9961 /// prior to trying this lowering.
9962 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9963 SDValue V1, SDValue V2,
9965 SelectionDAG &DAG) {
9966 // FIXME: This should probably be generalized for 512-bit vectors as well.
9967 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9968 int LaneSize = Mask.size() / 2;
9970 // If there are only inputs from one 128-bit lane, splitting will in fact be
9971 // less expensive. The flags track wether the given lane contains an element
9972 // that crosses to another lane.
9973 bool LaneCrossing[2] = {false, false};
9974 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9975 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9976 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9977 if (!LaneCrossing[0] || !LaneCrossing[1])
9978 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9980 if (isSingleInputShuffleMask(Mask)) {
9981 SmallVector<int, 32> FlippedBlendMask;
9982 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9983 FlippedBlendMask.push_back(
9984 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9986 : Mask[i] % LaneSize +
9987 (i / LaneSize) * LaneSize + Size));
9989 // Flip the vector, and blend the results which should now be in-lane. The
9990 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9991 // 5 for the high source. The value 3 selects the high half of source 2 and
9992 // the value 2 selects the low half of source 2. We only use source 2 to
9993 // allow folding it into a memory operand.
9994 unsigned PERMMask = 3 | 2 << 4;
9995 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9996 V1, DAG.getConstant(PERMMask, MVT::i8));
9997 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10000 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10001 // will be handled by the above logic and a blend of the results, much like
10002 // other patterns in AVX.
10003 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10006 /// \brief Handle lowering 2-lane 128-bit shuffles.
10007 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10008 SDValue V2, ArrayRef<int> Mask,
10009 const X86Subtarget *Subtarget,
10010 SelectionDAG &DAG) {
10011 // Blends are faster and handle all the non-lane-crossing cases.
10012 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10016 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10017 VT.getVectorNumElements() / 2);
10018 // Check for patterns which can be matched with a single insert of a 128-bit
10020 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10021 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10022 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10023 DAG.getIntPtrConstant(0));
10024 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10025 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10026 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10028 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10029 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10030 DAG.getIntPtrConstant(0));
10031 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10032 DAG.getIntPtrConstant(2));
10033 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10036 // Otherwise form a 128-bit permutation.
10037 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10038 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10039 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10040 DAG.getConstant(PermMask, MVT::i8));
10043 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10044 /// shuffling each lane.
10046 /// This will only succeed when the result of fixing the 128-bit lanes results
10047 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10048 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10049 /// the lane crosses early and then use simpler shuffles within each lane.
10051 /// FIXME: It might be worthwhile at some point to support this without
10052 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10053 /// in x86 only floating point has interesting non-repeating shuffles, and even
10054 /// those are still *marginally* more expensive.
10055 static SDValue lowerVectorShuffleByMerging128BitLanes(
10056 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10057 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10058 assert(!isSingleInputShuffleMask(Mask) &&
10059 "This is only useful with multiple inputs.");
10061 int Size = Mask.size();
10062 int LaneSize = 128 / VT.getScalarSizeInBits();
10063 int NumLanes = Size / LaneSize;
10064 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10066 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10067 // check whether the in-128-bit lane shuffles share a repeating pattern.
10068 SmallVector<int, 4> Lanes;
10069 Lanes.resize(NumLanes, -1);
10070 SmallVector<int, 4> InLaneMask;
10071 InLaneMask.resize(LaneSize, -1);
10072 for (int i = 0; i < Size; ++i) {
10076 int j = i / LaneSize;
10078 if (Lanes[j] < 0) {
10079 // First entry we've seen for this lane.
10080 Lanes[j] = Mask[i] / LaneSize;
10081 } else if (Lanes[j] != Mask[i] / LaneSize) {
10082 // This doesn't match the lane selected previously!
10086 // Check that within each lane we have a consistent shuffle mask.
10087 int k = i % LaneSize;
10088 if (InLaneMask[k] < 0) {
10089 InLaneMask[k] = Mask[i] % LaneSize;
10090 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10091 // This doesn't fit a repeating in-lane mask.
10096 // First shuffle the lanes into place.
10097 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10098 VT.getSizeInBits() / 64);
10099 SmallVector<int, 8> LaneMask;
10100 LaneMask.resize(NumLanes * 2, -1);
10101 for (int i = 0; i < NumLanes; ++i)
10102 if (Lanes[i] >= 0) {
10103 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10104 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10107 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10108 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10109 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10111 // Cast it back to the type we actually want.
10112 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10114 // Now do a simple shuffle that isn't lane crossing.
10115 SmallVector<int, 8> NewMask;
10116 NewMask.resize(Size, -1);
10117 for (int i = 0; i < Size; ++i)
10119 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10120 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10121 "Must not introduce lane crosses at this point!");
10123 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10126 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10129 /// This returns true if the elements from a particular input are already in the
10130 /// slot required by the given mask and require no permutation.
10131 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10132 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10133 int Size = Mask.size();
10134 for (int i = 0; i < Size; ++i)
10135 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10141 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10143 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10144 /// isn't available.
10145 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10146 const X86Subtarget *Subtarget,
10147 SelectionDAG &DAG) {
10149 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10150 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10152 ArrayRef<int> Mask = SVOp->getMask();
10153 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10155 SmallVector<int, 4> WidenedMask;
10156 if (canWidenShuffleElements(Mask, WidenedMask))
10157 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10160 if (isSingleInputShuffleMask(Mask)) {
10161 // Check for being able to broadcast a single element.
10162 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10163 Mask, Subtarget, DAG))
10166 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10167 // Non-half-crossing single input shuffles can be lowerid with an
10168 // interleaved permutation.
10169 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10170 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10171 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10172 DAG.getConstant(VPERMILPMask, MVT::i8));
10175 // With AVX2 we have direct support for this permutation.
10176 if (Subtarget->hasAVX2())
10177 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10178 getV4X86ShuffleImm8ForMask(Mask, DAG));
10180 // Otherwise, fall back.
10181 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10185 // X86 has dedicated unpack instructions that can handle specific blend
10186 // operations: UNPCKH and UNPCKL.
10187 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10188 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10189 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10190 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10192 // If we have a single input to the zero element, insert that into V1 if we
10193 // can do so cheaply.
10194 int NumV2Elements =
10195 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10196 if (NumV2Elements == 1 && Mask[0] >= 4)
10197 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10198 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10201 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10205 // Check if the blend happens to exactly fit that of SHUFPD.
10206 if ((Mask[0] == -1 || Mask[0] < 2) &&
10207 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10208 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10209 (Mask[3] == -1 || Mask[3] >= 6)) {
10210 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10211 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10212 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10213 DAG.getConstant(SHUFPDMask, MVT::i8));
10215 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10216 (Mask[1] == -1 || Mask[1] < 2) &&
10217 (Mask[2] == -1 || Mask[2] >= 6) &&
10218 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10219 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10220 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10221 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10222 DAG.getConstant(SHUFPDMask, MVT::i8));
10225 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10226 // shuffle. However, if we have AVX2 and either inputs are already in place,
10227 // we will be able to shuffle even across lanes the other input in a single
10228 // instruction so skip this pattern.
10229 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10230 isShuffleMaskInputInPlace(1, Mask))))
10231 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10232 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10235 // If we have AVX2 then we always want to lower with a blend because an v4 we
10236 // can fully permute the elements.
10237 if (Subtarget->hasAVX2())
10238 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10241 // Otherwise fall back on generic lowering.
10242 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10245 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10247 /// This routine is only called when we have AVX2 and thus a reasonable
10248 /// instruction set for v4i64 shuffling..
10249 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10250 const X86Subtarget *Subtarget,
10251 SelectionDAG &DAG) {
10253 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10254 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10256 ArrayRef<int> Mask = SVOp->getMask();
10257 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10258 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10260 SmallVector<int, 4> WidenedMask;
10261 if (canWidenShuffleElements(Mask, WidenedMask))
10262 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10265 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10269 // Check for being able to broadcast a single element.
10270 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10271 Mask, Subtarget, DAG))
10274 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10275 // use lower latency instructions that will operate on both 128-bit lanes.
10276 SmallVector<int, 2> RepeatedMask;
10277 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10278 if (isSingleInputShuffleMask(Mask)) {
10279 int PSHUFDMask[] = {-1, -1, -1, -1};
10280 for (int i = 0; i < 2; ++i)
10281 if (RepeatedMask[i] >= 0) {
10282 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10283 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10285 return DAG.getNode(
10286 ISD::BITCAST, DL, MVT::v4i64,
10287 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10288 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10289 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10292 // Use dedicated unpack instructions for masks that match their pattern.
10293 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10294 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10295 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10296 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10299 // AVX2 provides a direct instruction for permuting a single input across
10301 if (isSingleInputShuffleMask(Mask))
10302 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10303 getV4X86ShuffleImm8ForMask(Mask, DAG));
10305 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10306 // shuffle. However, if we have AVX2 and either inputs are already in place,
10307 // we will be able to shuffle even across lanes the other input in a single
10308 // instruction so skip this pattern.
10309 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10310 isShuffleMaskInputInPlace(1, Mask))))
10311 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10312 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10315 // Otherwise fall back on generic blend lowering.
10316 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10320 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10322 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10323 /// isn't available.
10324 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10325 const X86Subtarget *Subtarget,
10326 SelectionDAG &DAG) {
10328 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10329 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10331 ArrayRef<int> Mask = SVOp->getMask();
10332 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10334 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10338 // Check for being able to broadcast a single element.
10339 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10340 Mask, Subtarget, DAG))
10343 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10344 // options to efficiently lower the shuffle.
10345 SmallVector<int, 4> RepeatedMask;
10346 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10347 assert(RepeatedMask.size() == 4 &&
10348 "Repeated masks must be half the mask width!");
10349 if (isSingleInputShuffleMask(Mask))
10350 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10351 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10353 // Use dedicated unpack instructions for masks that match their pattern.
10354 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10355 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10356 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10357 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10359 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10360 // have already handled any direct blends. We also need to squash the
10361 // repeated mask into a simulated v4f32 mask.
10362 for (int i = 0; i < 4; ++i)
10363 if (RepeatedMask[i] >= 8)
10364 RepeatedMask[i] -= 4;
10365 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10368 // If we have a single input shuffle with different shuffle patterns in the
10369 // two 128-bit lanes use the variable mask to VPERMILPS.
10370 if (isSingleInputShuffleMask(Mask)) {
10371 SDValue VPermMask[8];
10372 for (int i = 0; i < 8; ++i)
10373 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10374 : DAG.getConstant(Mask[i], MVT::i32);
10375 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10376 return DAG.getNode(
10377 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10378 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10380 if (Subtarget->hasAVX2())
10381 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10382 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10383 DAG.getNode(ISD::BUILD_VECTOR, DL,
10384 MVT::v8i32, VPermMask)),
10387 // Otherwise, fall back.
10388 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10392 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10394 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10395 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10398 // If we have AVX2 then we always want to lower with a blend because at v8 we
10399 // can fully permute the elements.
10400 if (Subtarget->hasAVX2())
10401 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10404 // Otherwise fall back on generic lowering.
10405 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10408 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10410 /// This routine is only called when we have AVX2 and thus a reasonable
10411 /// instruction set for v8i32 shuffling..
10412 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10413 const X86Subtarget *Subtarget,
10414 SelectionDAG &DAG) {
10416 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10417 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10418 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10419 ArrayRef<int> Mask = SVOp->getMask();
10420 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10421 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10423 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10427 // Check for being able to broadcast a single element.
10428 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10429 Mask, Subtarget, DAG))
10432 // If the shuffle mask is repeated in each 128-bit lane we can use more
10433 // efficient instructions that mirror the shuffles across the two 128-bit
10435 SmallVector<int, 4> RepeatedMask;
10436 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10437 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10438 if (isSingleInputShuffleMask(Mask))
10439 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10440 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10442 // Use dedicated unpack instructions for masks that match their pattern.
10443 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10444 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10445 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10446 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10449 // If the shuffle patterns aren't repeated but it is a single input, directly
10450 // generate a cross-lane VPERMD instruction.
10451 if (isSingleInputShuffleMask(Mask)) {
10452 SDValue VPermMask[8];
10453 for (int i = 0; i < 8; ++i)
10454 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10455 : DAG.getConstant(Mask[i], MVT::i32);
10456 return DAG.getNode(
10457 X86ISD::VPERMV, DL, MVT::v8i32,
10458 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10461 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10463 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10464 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10467 // Otherwise fall back on generic blend lowering.
10468 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10472 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10474 /// This routine is only called when we have AVX2 and thus a reasonable
10475 /// instruction set for v16i16 shuffling..
10476 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10477 const X86Subtarget *Subtarget,
10478 SelectionDAG &DAG) {
10480 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10481 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10483 ArrayRef<int> Mask = SVOp->getMask();
10484 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10485 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10487 // Check for being able to broadcast a single element.
10488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10489 Mask, Subtarget, DAG))
10492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10496 // Use dedicated unpack instructions for masks that match their pattern.
10497 if (isShuffleEquivalent(Mask,
10498 // First 128-bit lane:
10499 0, 16, 1, 17, 2, 18, 3, 19,
10500 // Second 128-bit lane:
10501 8, 24, 9, 25, 10, 26, 11, 27))
10502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10503 if (isShuffleEquivalent(Mask,
10504 // First 128-bit lane:
10505 4, 20, 5, 21, 6, 22, 7, 23,
10506 // Second 128-bit lane:
10507 12, 28, 13, 29, 14, 30, 15, 31))
10508 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10510 if (isSingleInputShuffleMask(Mask)) {
10511 // There are no generalized cross-lane shuffle operations available on i16
10513 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10514 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10517 SDValue PSHUFBMask[32];
10518 for (int i = 0; i < 16; ++i) {
10519 if (Mask[i] == -1) {
10520 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10524 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10525 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10526 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10527 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10529 return DAG.getNode(
10530 ISD::BITCAST, DL, MVT::v16i16,
10532 X86ISD::PSHUFB, DL, MVT::v32i8,
10533 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10534 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10537 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10539 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10540 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10543 // Otherwise fall back on generic lowering.
10544 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10547 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10549 /// This routine is only called when we have AVX2 and thus a reasonable
10550 /// instruction set for v32i8 shuffling..
10551 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10552 const X86Subtarget *Subtarget,
10553 SelectionDAG &DAG) {
10555 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10556 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10557 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10558 ArrayRef<int> Mask = SVOp->getMask();
10559 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10560 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10562 // Check for being able to broadcast a single element.
10563 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10564 Mask, Subtarget, DAG))
10567 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10571 // Use dedicated unpack instructions for masks that match their pattern.
10572 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10574 if (isShuffleEquivalent(
10576 // First 128-bit lane:
10577 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10578 // Second 128-bit lane:
10579 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10580 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10581 if (isShuffleEquivalent(
10583 // First 128-bit lane:
10584 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10585 // Second 128-bit lane:
10586 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10587 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10589 if (isSingleInputShuffleMask(Mask)) {
10590 // There are no generalized cross-lane shuffle operations available on i8
10592 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10593 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10596 SDValue PSHUFBMask[32];
10597 for (int i = 0; i < 32; ++i)
10600 ? DAG.getUNDEF(MVT::i8)
10601 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10603 return DAG.getNode(
10604 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10605 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10608 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10610 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10611 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10614 // Otherwise fall back on generic lowering.
10615 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10618 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10620 /// This routine either breaks down the specific type of a 256-bit x86 vector
10621 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10622 /// together based on the available instructions.
10623 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10624 MVT VT, const X86Subtarget *Subtarget,
10625 SelectionDAG &DAG) {
10627 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10628 ArrayRef<int> Mask = SVOp->getMask();
10630 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10631 // check for those subtargets here and avoid much of the subtarget querying in
10632 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10633 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10634 // floating point types there eventually, just immediately cast everything to
10635 // a float and operate entirely in that domain.
10636 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10637 int ElementBits = VT.getScalarSizeInBits();
10638 if (ElementBits < 32)
10639 // No floating point type available, decompose into 128-bit vectors.
10640 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10642 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10643 VT.getVectorNumElements());
10644 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10645 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10646 return DAG.getNode(ISD::BITCAST, DL, VT,
10647 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10650 switch (VT.SimpleTy) {
10652 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10654 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10656 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10658 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10660 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10662 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10665 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10669 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10670 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10671 const X86Subtarget *Subtarget,
10672 SelectionDAG &DAG) {
10674 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10675 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10677 ArrayRef<int> Mask = SVOp->getMask();
10678 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10680 // FIXME: Implement direct support for this type!
10681 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10684 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10685 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10686 const X86Subtarget *Subtarget,
10687 SelectionDAG &DAG) {
10689 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10690 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10692 ArrayRef<int> Mask = SVOp->getMask();
10693 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10695 // FIXME: Implement direct support for this type!
10696 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10699 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10700 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10701 const X86Subtarget *Subtarget,
10702 SelectionDAG &DAG) {
10704 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10705 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10707 ArrayRef<int> Mask = SVOp->getMask();
10708 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10710 // FIXME: Implement direct support for this type!
10711 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10714 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10715 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10716 const X86Subtarget *Subtarget,
10717 SelectionDAG &DAG) {
10719 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10720 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10722 ArrayRef<int> Mask = SVOp->getMask();
10723 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10725 // FIXME: Implement direct support for this type!
10726 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10729 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10730 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10731 const X86Subtarget *Subtarget,
10732 SelectionDAG &DAG) {
10734 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10735 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10737 ArrayRef<int> Mask = SVOp->getMask();
10738 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10739 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10741 // FIXME: Implement direct support for this type!
10742 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10745 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10746 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10747 const X86Subtarget *Subtarget,
10748 SelectionDAG &DAG) {
10750 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10751 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10752 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10753 ArrayRef<int> Mask = SVOp->getMask();
10754 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10755 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10757 // FIXME: Implement direct support for this type!
10758 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10761 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10763 /// This routine either breaks down the specific type of a 512-bit x86 vector
10764 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10765 /// together based on the available instructions.
10766 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10767 MVT VT, const X86Subtarget *Subtarget,
10768 SelectionDAG &DAG) {
10770 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10771 ArrayRef<int> Mask = SVOp->getMask();
10772 assert(Subtarget->hasAVX512() &&
10773 "Cannot lower 512-bit vectors w/ basic ISA!");
10775 // Check for being able to broadcast a single element.
10776 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10777 Mask, Subtarget, DAG))
10780 // Dispatch to each element type for lowering. If we don't have supprot for
10781 // specific element type shuffles at 512 bits, immediately split them and
10782 // lower them. Each lowering routine of a given type is allowed to assume that
10783 // the requisite ISA extensions for that element type are available.
10784 switch (VT.SimpleTy) {
10786 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10788 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10790 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10792 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10794 if (Subtarget->hasBWI())
10795 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10798 if (Subtarget->hasBWI())
10799 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10803 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10806 // Otherwise fall back on splitting.
10807 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10810 /// \brief Top-level lowering for x86 vector shuffles.
10812 /// This handles decomposition, canonicalization, and lowering of all x86
10813 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10814 /// above in helper routines. The canonicalization attempts to widen shuffles
10815 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10816 /// s.t. only one of the two inputs needs to be tested, etc.
10817 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10818 SelectionDAG &DAG) {
10819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10820 ArrayRef<int> Mask = SVOp->getMask();
10821 SDValue V1 = Op.getOperand(0);
10822 SDValue V2 = Op.getOperand(1);
10823 MVT VT = Op.getSimpleValueType();
10824 int NumElements = VT.getVectorNumElements();
10827 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10829 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10830 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10831 if (V1IsUndef && V2IsUndef)
10832 return DAG.getUNDEF(VT);
10834 // When we create a shuffle node we put the UNDEF node to second operand,
10835 // but in some cases the first operand may be transformed to UNDEF.
10836 // In this case we should just commute the node.
10838 return DAG.getCommutedVectorShuffle(*SVOp);
10840 // Check for non-undef masks pointing at an undef vector and make the masks
10841 // undef as well. This makes it easier to match the shuffle based solely on
10845 if (M >= NumElements) {
10846 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10847 for (int &M : NewMask)
10848 if (M >= NumElements)
10850 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10853 // Try to collapse shuffles into using a vector type with fewer elements but
10854 // wider element types. We cap this to not form integers or floating point
10855 // elements wider than 64 bits, but it might be interesting to form i128
10856 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10857 SmallVector<int, 16> WidenedMask;
10858 if (VT.getScalarSizeInBits() < 64 &&
10859 canWidenShuffleElements(Mask, WidenedMask)) {
10860 MVT NewEltVT = VT.isFloatingPoint()
10861 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10862 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10863 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10864 // Make sure that the new vector type is legal. For example, v2f64 isn't
10866 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10867 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10868 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10869 return DAG.getNode(ISD::BITCAST, dl, VT,
10870 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10874 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10875 for (int M : SVOp->getMask())
10877 ++NumUndefElements;
10878 else if (M < NumElements)
10883 // Commute the shuffle as needed such that more elements come from V1 than
10884 // V2. This allows us to match the shuffle pattern strictly on how many
10885 // elements come from V1 without handling the symmetric cases.
10886 if (NumV2Elements > NumV1Elements)
10887 return DAG.getCommutedVectorShuffle(*SVOp);
10889 // When the number of V1 and V2 elements are the same, try to minimize the
10890 // number of uses of V2 in the low half of the vector. When that is tied,
10891 // ensure that the sum of indices for V1 is equal to or lower than the sum
10892 // indices for V2. When those are equal, try to ensure that the number of odd
10893 // indices for V1 is lower than the number of odd indices for V2.
10894 if (NumV1Elements == NumV2Elements) {
10895 int LowV1Elements = 0, LowV2Elements = 0;
10896 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10897 if (M >= NumElements)
10901 if (LowV2Elements > LowV1Elements) {
10902 return DAG.getCommutedVectorShuffle(*SVOp);
10903 } else if (LowV2Elements == LowV1Elements) {
10904 int SumV1Indices = 0, SumV2Indices = 0;
10905 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10906 if (SVOp->getMask()[i] >= NumElements)
10908 else if (SVOp->getMask()[i] >= 0)
10910 if (SumV2Indices < SumV1Indices) {
10911 return DAG.getCommutedVectorShuffle(*SVOp);
10912 } else if (SumV2Indices == SumV1Indices) {
10913 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10914 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10915 if (SVOp->getMask()[i] >= NumElements)
10916 NumV2OddIndices += i % 2;
10917 else if (SVOp->getMask()[i] >= 0)
10918 NumV1OddIndices += i % 2;
10919 if (NumV2OddIndices < NumV1OddIndices)
10920 return DAG.getCommutedVectorShuffle(*SVOp);
10925 // For each vector width, delegate to a specialized lowering routine.
10926 if (VT.getSizeInBits() == 128)
10927 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10929 if (VT.getSizeInBits() == 256)
10930 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10932 // Force AVX-512 vectors to be scalarized for now.
10933 // FIXME: Implement AVX-512 support!
10934 if (VT.getSizeInBits() == 512)
10935 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10937 llvm_unreachable("Unimplemented!");
10941 //===----------------------------------------------------------------------===//
10942 // Legacy vector shuffle lowering
10944 // This code is the legacy code handling vector shuffles until the above
10945 // replaces its functionality and performance.
10946 //===----------------------------------------------------------------------===//
10948 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10949 bool hasInt256, unsigned *MaskOut = nullptr) {
10950 MVT EltVT = VT.getVectorElementType();
10952 // There is no blend with immediate in AVX-512.
10953 if (VT.is512BitVector())
10956 if (!hasSSE41 || EltVT == MVT::i8)
10958 if (!hasInt256 && VT == MVT::v16i16)
10961 unsigned MaskValue = 0;
10962 unsigned NumElems = VT.getVectorNumElements();
10963 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10964 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10965 unsigned NumElemsInLane = NumElems / NumLanes;
10967 // Blend for v16i16 should be symetric for the both lanes.
10968 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10970 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10971 int EltIdx = MaskVals[i];
10973 if ((EltIdx < 0 || EltIdx == (int)i) &&
10974 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10977 if (((unsigned)EltIdx == (i + NumElems)) &&
10978 (SndLaneEltIdx < 0 ||
10979 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10980 MaskValue |= (1 << i);
10986 *MaskOut = MaskValue;
10990 // Try to lower a shuffle node into a simple blend instruction.
10991 // This function assumes isBlendMask returns true for this
10992 // SuffleVectorSDNode
10993 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10994 unsigned MaskValue,
10995 const X86Subtarget *Subtarget,
10996 SelectionDAG &DAG) {
10997 MVT VT = SVOp->getSimpleValueType(0);
10998 MVT EltVT = VT.getVectorElementType();
10999 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11000 Subtarget->hasInt256() && "Trying to lower a "
11001 "VECTOR_SHUFFLE to a Blend but "
11002 "with the wrong mask"));
11003 SDValue V1 = SVOp->getOperand(0);
11004 SDValue V2 = SVOp->getOperand(1);
11006 unsigned NumElems = VT.getVectorNumElements();
11008 // Convert i32 vectors to floating point if it is not AVX2.
11009 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11011 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11012 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11014 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11015 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11018 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11019 DAG.getConstant(MaskValue, MVT::i32));
11020 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11023 /// In vector type \p VT, return true if the element at index \p InputIdx
11024 /// falls on a different 128-bit lane than \p OutputIdx.
11025 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11026 unsigned OutputIdx) {
11027 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11028 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11031 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11032 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11033 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11034 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11036 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11037 SelectionDAG &DAG) {
11038 MVT VT = V1.getSimpleValueType();
11039 assert(VT.is128BitVector() || VT.is256BitVector());
11041 MVT EltVT = VT.getVectorElementType();
11042 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11043 unsigned NumElts = VT.getVectorNumElements();
11045 SmallVector<SDValue, 32> PshufbMask;
11046 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11047 int InputIdx = MaskVals[OutputIdx];
11048 unsigned InputByteIdx;
11050 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11051 InputByteIdx = 0x80;
11053 // Cross lane is not allowed.
11054 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11056 InputByteIdx = InputIdx * EltSizeInBytes;
11057 // Index is an byte offset within the 128-bit lane.
11058 InputByteIdx &= 0xf;
11061 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11062 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11063 if (InputByteIdx != 0x80)
11068 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11070 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11071 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11072 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11075 // v8i16 shuffles - Prefer shuffles in the following order:
11076 // 1. [all] pshuflw, pshufhw, optional move
11077 // 2. [ssse3] 1 x pshufb
11078 // 3. [ssse3] 2 x pshufb + 1 x por
11079 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11081 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11082 SelectionDAG &DAG) {
11083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11084 SDValue V1 = SVOp->getOperand(0);
11085 SDValue V2 = SVOp->getOperand(1);
11087 SmallVector<int, 8> MaskVals;
11089 // Determine if more than 1 of the words in each of the low and high quadwords
11090 // of the result come from the same quadword of one of the two inputs. Undef
11091 // mask values count as coming from any quadword, for better codegen.
11093 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11094 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11095 unsigned LoQuad[] = { 0, 0, 0, 0 };
11096 unsigned HiQuad[] = { 0, 0, 0, 0 };
11097 // Indices of quads used.
11098 std::bitset<4> InputQuads;
11099 for (unsigned i = 0; i < 8; ++i) {
11100 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11101 int EltIdx = SVOp->getMaskElt(i);
11102 MaskVals.push_back(EltIdx);
11110 ++Quad[EltIdx / 4];
11111 InputQuads.set(EltIdx / 4);
11114 int BestLoQuad = -1;
11115 unsigned MaxQuad = 1;
11116 for (unsigned i = 0; i < 4; ++i) {
11117 if (LoQuad[i] > MaxQuad) {
11119 MaxQuad = LoQuad[i];
11123 int BestHiQuad = -1;
11125 for (unsigned i = 0; i < 4; ++i) {
11126 if (HiQuad[i] > MaxQuad) {
11128 MaxQuad = HiQuad[i];
11132 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11133 // of the two input vectors, shuffle them into one input vector so only a
11134 // single pshufb instruction is necessary. If there are more than 2 input
11135 // quads, disable the next transformation since it does not help SSSE3.
11136 bool V1Used = InputQuads[0] || InputQuads[1];
11137 bool V2Used = InputQuads[2] || InputQuads[3];
11138 if (Subtarget->hasSSSE3()) {
11139 if (InputQuads.count() == 2 && V1Used && V2Used) {
11140 BestLoQuad = InputQuads[0] ? 0 : 1;
11141 BestHiQuad = InputQuads[2] ? 2 : 3;
11143 if (InputQuads.count() > 2) {
11149 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11150 // the shuffle mask. If a quad is scored as -1, that means that it contains
11151 // words from all 4 input quadwords.
11153 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11155 BestLoQuad < 0 ? 0 : BestLoQuad,
11156 BestHiQuad < 0 ? 1 : BestHiQuad
11158 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11159 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11160 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11161 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11163 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11164 // source words for the shuffle, to aid later transformations.
11165 bool AllWordsInNewV = true;
11166 bool InOrder[2] = { true, true };
11167 for (unsigned i = 0; i != 8; ++i) {
11168 int idx = MaskVals[i];
11170 InOrder[i/4] = false;
11171 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11173 AllWordsInNewV = false;
11177 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11178 if (AllWordsInNewV) {
11179 for (int i = 0; i != 8; ++i) {
11180 int idx = MaskVals[i];
11183 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11184 if ((idx != i) && idx < 4)
11186 if ((idx != i) && idx > 3)
11195 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11196 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11197 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11198 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11199 unsigned TargetMask = 0;
11200 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11201 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11203 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11204 getShufflePSHUFLWImmediate(SVOp);
11205 V1 = NewV.getOperand(0);
11206 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11210 // Promote splats to a larger type which usually leads to more efficient code.
11211 // FIXME: Is this true if pshufb is available?
11212 if (SVOp->isSplat())
11213 return PromoteSplat(SVOp, DAG);
11215 // If we have SSSE3, and all words of the result are from 1 input vector,
11216 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11217 // is present, fall back to case 4.
11218 if (Subtarget->hasSSSE3()) {
11219 SmallVector<SDValue,16> pshufbMask;
11221 // If we have elements from both input vectors, set the high bit of the
11222 // shuffle mask element to zero out elements that come from V2 in the V1
11223 // mask, and elements that come from V1 in the V2 mask, so that the two
11224 // results can be OR'd together.
11225 bool TwoInputs = V1Used && V2Used;
11226 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11228 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11230 // Calculate the shuffle mask for the second input, shuffle it, and
11231 // OR it with the first shuffled input.
11232 CommuteVectorShuffleMask(MaskVals, 8);
11233 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11234 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11235 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11238 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11239 // and update MaskVals with new element order.
11240 std::bitset<8> InOrder;
11241 if (BestLoQuad >= 0) {
11242 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11243 for (int i = 0; i != 4; ++i) {
11244 int idx = MaskVals[i];
11247 } else if ((idx / 4) == BestLoQuad) {
11248 MaskV[i] = idx & 3;
11252 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11255 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11256 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11257 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11258 NewV.getOperand(0),
11259 getShufflePSHUFLWImmediate(SVOp), DAG);
11263 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11264 // and update MaskVals with the new element order.
11265 if (BestHiQuad >= 0) {
11266 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11267 for (unsigned i = 4; i != 8; ++i) {
11268 int idx = MaskVals[i];
11271 } else if ((idx / 4) == BestHiQuad) {
11272 MaskV[i] = (idx & 3) + 4;
11276 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11279 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11281 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11282 NewV.getOperand(0),
11283 getShufflePSHUFHWImmediate(SVOp), DAG);
11287 // In case BestHi & BestLo were both -1, which means each quadword has a word
11288 // from each of the four input quadwords, calculate the InOrder bitvector now
11289 // before falling through to the insert/extract cleanup.
11290 if (BestLoQuad == -1 && BestHiQuad == -1) {
11292 for (int i = 0; i != 8; ++i)
11293 if (MaskVals[i] < 0 || MaskVals[i] == i)
11297 // The other elements are put in the right place using pextrw and pinsrw.
11298 for (unsigned i = 0; i != 8; ++i) {
11301 int EltIdx = MaskVals[i];
11304 SDValue ExtOp = (EltIdx < 8) ?
11305 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11306 DAG.getIntPtrConstant(EltIdx)) :
11307 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11308 DAG.getIntPtrConstant(EltIdx - 8));
11309 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11310 DAG.getIntPtrConstant(i));
11315 /// \brief v16i16 shuffles
11317 /// FIXME: We only support generation of a single pshufb currently. We can
11318 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11319 /// well (e.g 2 x pshufb + 1 x por).
11321 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11323 SDValue V1 = SVOp->getOperand(0);
11324 SDValue V2 = SVOp->getOperand(1);
11327 if (V2.getOpcode() != ISD::UNDEF)
11330 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11331 return getPSHUFB(MaskVals, V1, dl, DAG);
11334 // v16i8 shuffles - Prefer shuffles in the following order:
11335 // 1. [ssse3] 1 x pshufb
11336 // 2. [ssse3] 2 x pshufb + 1 x por
11337 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11338 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11339 const X86Subtarget* Subtarget,
11340 SelectionDAG &DAG) {
11341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11342 SDValue V1 = SVOp->getOperand(0);
11343 SDValue V2 = SVOp->getOperand(1);
11345 ArrayRef<int> MaskVals = SVOp->getMask();
11347 // Promote splats to a larger type which usually leads to more efficient code.
11348 // FIXME: Is this true if pshufb is available?
11349 if (SVOp->isSplat())
11350 return PromoteSplat(SVOp, DAG);
11352 // If we have SSSE3, case 1 is generated when all result bytes come from
11353 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11354 // present, fall back to case 3.
11356 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11357 if (Subtarget->hasSSSE3()) {
11358 SmallVector<SDValue,16> pshufbMask;
11360 // If all result elements are from one input vector, then only translate
11361 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11363 // Otherwise, we have elements from both input vectors, and must zero out
11364 // elements that come from V2 in the first mask, and V1 in the second mask
11365 // so that we can OR them together.
11366 for (unsigned i = 0; i != 16; ++i) {
11367 int EltIdx = MaskVals[i];
11368 if (EltIdx < 0 || EltIdx >= 16)
11370 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11372 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11373 DAG.getNode(ISD::BUILD_VECTOR, dl,
11374 MVT::v16i8, pshufbMask));
11376 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11377 // the 2nd operand if it's undefined or zero.
11378 if (V2.getOpcode() == ISD::UNDEF ||
11379 ISD::isBuildVectorAllZeros(V2.getNode()))
11382 // Calculate the shuffle mask for the second input, shuffle it, and
11383 // OR it with the first shuffled input.
11384 pshufbMask.clear();
11385 for (unsigned i = 0; i != 16; ++i) {
11386 int EltIdx = MaskVals[i];
11387 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11388 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11390 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11391 DAG.getNode(ISD::BUILD_VECTOR, dl,
11392 MVT::v16i8, pshufbMask));
11393 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11396 // No SSSE3 - Calculate in place words and then fix all out of place words
11397 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11398 // the 16 different words that comprise the two doublequadword input vectors.
11399 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11400 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11402 for (int i = 0; i != 8; ++i) {
11403 int Elt0 = MaskVals[i*2];
11404 int Elt1 = MaskVals[i*2+1];
11406 // This word of the result is all undef, skip it.
11407 if (Elt0 < 0 && Elt1 < 0)
11410 // This word of the result is already in the correct place, skip it.
11411 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11414 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11415 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11418 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11419 // using a single extract together, load it and store it.
11420 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11421 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11422 DAG.getIntPtrConstant(Elt1 / 2));
11423 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11424 DAG.getIntPtrConstant(i));
11428 // If Elt1 is defined, extract it from the appropriate source. If the
11429 // source byte is not also odd, shift the extracted word left 8 bits
11430 // otherwise clear the bottom 8 bits if we need to do an or.
11432 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11433 DAG.getIntPtrConstant(Elt1 / 2));
11434 if ((Elt1 & 1) == 0)
11435 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11437 TLI.getShiftAmountTy(InsElt.getValueType())));
11438 else if (Elt0 >= 0)
11439 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11440 DAG.getConstant(0xFF00, MVT::i16));
11442 // If Elt0 is defined, extract it from the appropriate source. If the
11443 // source byte is not also even, shift the extracted word right 8 bits. If
11444 // Elt1 was also defined, OR the extracted values together before
11445 // inserting them in the result.
11447 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11448 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11449 if ((Elt0 & 1) != 0)
11450 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11452 TLI.getShiftAmountTy(InsElt0.getValueType())));
11453 else if (Elt1 >= 0)
11454 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11455 DAG.getConstant(0x00FF, MVT::i16));
11456 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11459 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11460 DAG.getIntPtrConstant(i));
11462 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11465 // v32i8 shuffles - Translate to VPSHUFB if possible.
11467 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11468 const X86Subtarget *Subtarget,
11469 SelectionDAG &DAG) {
11470 MVT VT = SVOp->getSimpleValueType(0);
11471 SDValue V1 = SVOp->getOperand(0);
11472 SDValue V2 = SVOp->getOperand(1);
11474 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11476 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11477 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11478 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11480 // VPSHUFB may be generated if
11481 // (1) one of input vector is undefined or zeroinitializer.
11482 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11483 // And (2) the mask indexes don't cross the 128-bit lane.
11484 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11485 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11488 if (V1IsAllZero && !V2IsAllZero) {
11489 CommuteVectorShuffleMask(MaskVals, 32);
11492 return getPSHUFB(MaskVals, V1, dl, DAG);
11495 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11496 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11497 /// done when every pair / quad of shuffle mask elements point to elements in
11498 /// the right sequence. e.g.
11499 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11501 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11502 SelectionDAG &DAG) {
11503 MVT VT = SVOp->getSimpleValueType(0);
11505 unsigned NumElems = VT.getVectorNumElements();
11508 switch (VT.SimpleTy) {
11509 default: llvm_unreachable("Unexpected!");
11512 return SDValue(SVOp, 0);
11513 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11514 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11515 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11516 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11517 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11518 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11521 SmallVector<int, 8> MaskVec;
11522 for (unsigned i = 0; i != NumElems; i += Scale) {
11524 for (unsigned j = 0; j != Scale; ++j) {
11525 int EltIdx = SVOp->getMaskElt(i+j);
11529 StartIdx = (EltIdx / Scale);
11530 if (EltIdx != (int)(StartIdx*Scale + j))
11533 MaskVec.push_back(StartIdx);
11536 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11537 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11538 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11541 /// getVZextMovL - Return a zero-extending vector move low node.
11543 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11544 SDValue SrcOp, SelectionDAG &DAG,
11545 const X86Subtarget *Subtarget, SDLoc dl) {
11546 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11547 LoadSDNode *LD = nullptr;
11548 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11549 LD = dyn_cast<LoadSDNode>(SrcOp);
11551 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11553 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11554 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11555 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11556 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11557 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11559 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11560 return DAG.getNode(ISD::BITCAST, dl, VT,
11561 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11562 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11564 SrcOp.getOperand(0)
11570 return DAG.getNode(ISD::BITCAST, dl, VT,
11571 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11572 DAG.getNode(ISD::BITCAST, dl,
11576 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11577 /// which could not be matched by any known target speficic shuffle
11579 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11581 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11582 if (NewOp.getNode())
11585 MVT VT = SVOp->getSimpleValueType(0);
11587 unsigned NumElems = VT.getVectorNumElements();
11588 unsigned NumLaneElems = NumElems / 2;
11591 MVT EltVT = VT.getVectorElementType();
11592 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11595 SmallVector<int, 16> Mask;
11596 for (unsigned l = 0; l < 2; ++l) {
11597 // Build a shuffle mask for the output, discovering on the fly which
11598 // input vectors to use as shuffle operands (recorded in InputUsed).
11599 // If building a suitable shuffle vector proves too hard, then bail
11600 // out with UseBuildVector set.
11601 bool UseBuildVector = false;
11602 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11603 unsigned LaneStart = l * NumLaneElems;
11604 for (unsigned i = 0; i != NumLaneElems; ++i) {
11605 // The mask element. This indexes into the input.
11606 int Idx = SVOp->getMaskElt(i+LaneStart);
11608 // the mask element does not index into any input vector.
11609 Mask.push_back(-1);
11613 // The input vector this mask element indexes into.
11614 int Input = Idx / NumLaneElems;
11616 // Turn the index into an offset from the start of the input vector.
11617 Idx -= Input * NumLaneElems;
11619 // Find or create a shuffle vector operand to hold this input.
11621 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11622 if (InputUsed[OpNo] == Input)
11623 // This input vector is already an operand.
11625 if (InputUsed[OpNo] < 0) {
11626 // Create a new operand for this input vector.
11627 InputUsed[OpNo] = Input;
11632 if (OpNo >= array_lengthof(InputUsed)) {
11633 // More than two input vectors used! Give up on trying to create a
11634 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11635 UseBuildVector = true;
11639 // Add the mask index for the new shuffle vector.
11640 Mask.push_back(Idx + OpNo * NumLaneElems);
11643 if (UseBuildVector) {
11644 SmallVector<SDValue, 16> SVOps;
11645 for (unsigned i = 0; i != NumLaneElems; ++i) {
11646 // The mask element. This indexes into the input.
11647 int Idx = SVOp->getMaskElt(i+LaneStart);
11649 SVOps.push_back(DAG.getUNDEF(EltVT));
11653 // The input vector this mask element indexes into.
11654 int Input = Idx / NumElems;
11656 // Turn the index into an offset from the start of the input vector.
11657 Idx -= Input * NumElems;
11659 // Extract the vector element by hand.
11660 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11661 SVOp->getOperand(Input),
11662 DAG.getIntPtrConstant(Idx)));
11665 // Construct the output using a BUILD_VECTOR.
11666 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11667 } else if (InputUsed[0] < 0) {
11668 // No input vectors were used! The result is undefined.
11669 Output[l] = DAG.getUNDEF(NVT);
11671 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11672 (InputUsed[0] % 2) * NumLaneElems,
11674 // If only one input was used, use an undefined vector for the other.
11675 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11676 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11677 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11678 // At least one input vector was used. Create a new shuffle vector.
11679 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11685 // Concatenate the result back
11686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11689 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11690 /// 4 elements, and match them with several different shuffle types.
11692 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11693 SDValue V1 = SVOp->getOperand(0);
11694 SDValue V2 = SVOp->getOperand(1);
11696 MVT VT = SVOp->getSimpleValueType(0);
11698 assert(VT.is128BitVector() && "Unsupported vector size");
11700 std::pair<int, int> Locs[4];
11701 int Mask1[] = { -1, -1, -1, -1 };
11702 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11704 unsigned NumHi = 0;
11705 unsigned NumLo = 0;
11706 for (unsigned i = 0; i != 4; ++i) {
11707 int Idx = PermMask[i];
11709 Locs[i] = std::make_pair(-1, -1);
11711 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11713 Locs[i] = std::make_pair(0, NumLo);
11714 Mask1[NumLo] = Idx;
11717 Locs[i] = std::make_pair(1, NumHi);
11719 Mask1[2+NumHi] = Idx;
11725 if (NumLo <= 2 && NumHi <= 2) {
11726 // If no more than two elements come from either vector. This can be
11727 // implemented with two shuffles. First shuffle gather the elements.
11728 // The second shuffle, which takes the first shuffle as both of its
11729 // vector operands, put the elements into the right order.
11730 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11732 int Mask2[] = { -1, -1, -1, -1 };
11734 for (unsigned i = 0; i != 4; ++i)
11735 if (Locs[i].first != -1) {
11736 unsigned Idx = (i < 2) ? 0 : 4;
11737 Idx += Locs[i].first * 2 + Locs[i].second;
11741 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11744 if (NumLo == 3 || NumHi == 3) {
11745 // Otherwise, we must have three elements from one vector, call it X, and
11746 // one element from the other, call it Y. First, use a shufps to build an
11747 // intermediate vector with the one element from Y and the element from X
11748 // that will be in the same half in the final destination (the indexes don't
11749 // matter). Then, use a shufps to build the final vector, taking the half
11750 // containing the element from Y from the intermediate, and the other half
11753 // Normalize it so the 3 elements come from V1.
11754 CommuteVectorShuffleMask(PermMask, 4);
11758 // Find the element from V2.
11760 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11761 int Val = PermMask[HiIndex];
11768 Mask1[0] = PermMask[HiIndex];
11770 Mask1[2] = PermMask[HiIndex^1];
11772 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11774 if (HiIndex >= 2) {
11775 Mask1[0] = PermMask[0];
11776 Mask1[1] = PermMask[1];
11777 Mask1[2] = HiIndex & 1 ? 6 : 4;
11778 Mask1[3] = HiIndex & 1 ? 4 : 6;
11779 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11782 Mask1[0] = HiIndex & 1 ? 2 : 0;
11783 Mask1[1] = HiIndex & 1 ? 0 : 2;
11784 Mask1[2] = PermMask[2];
11785 Mask1[3] = PermMask[3];
11790 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11793 // Break it into (shuffle shuffle_hi, shuffle_lo).
11794 int LoMask[] = { -1, -1, -1, -1 };
11795 int HiMask[] = { -1, -1, -1, -1 };
11797 int *MaskPtr = LoMask;
11798 unsigned MaskIdx = 0;
11799 unsigned LoIdx = 0;
11800 unsigned HiIdx = 2;
11801 for (unsigned i = 0; i != 4; ++i) {
11808 int Idx = PermMask[i];
11810 Locs[i] = std::make_pair(-1, -1);
11811 } else if (Idx < 4) {
11812 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11813 MaskPtr[LoIdx] = Idx;
11816 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11817 MaskPtr[HiIdx] = Idx;
11822 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11823 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11824 int MaskOps[] = { -1, -1, -1, -1 };
11825 for (unsigned i = 0; i != 4; ++i)
11826 if (Locs[i].first != -1)
11827 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11828 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11831 static bool MayFoldVectorLoad(SDValue V) {
11832 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11833 V = V.getOperand(0);
11835 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11836 V = V.getOperand(0);
11837 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11838 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11839 // BUILD_VECTOR (load), undef
11840 V = V.getOperand(0);
11842 return MayFoldLoad(V);
11846 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11847 MVT VT = Op.getSimpleValueType();
11849 // Canonizalize to v2f64.
11850 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11851 return DAG.getNode(ISD::BITCAST, dl, VT,
11852 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11857 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11859 SDValue V1 = Op.getOperand(0);
11860 SDValue V2 = Op.getOperand(1);
11861 MVT VT = Op.getSimpleValueType();
11863 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11865 if (HasSSE2 && VT == MVT::v2f64)
11866 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11868 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11869 return DAG.getNode(ISD::BITCAST, dl, VT,
11870 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11871 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11872 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11876 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11877 SDValue V1 = Op.getOperand(0);
11878 SDValue V2 = Op.getOperand(1);
11879 MVT VT = Op.getSimpleValueType();
11881 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11882 "unsupported shuffle type");
11884 if (V2.getOpcode() == ISD::UNDEF)
11888 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11892 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11893 SDValue V1 = Op.getOperand(0);
11894 SDValue V2 = Op.getOperand(1);
11895 MVT VT = Op.getSimpleValueType();
11896 unsigned NumElems = VT.getVectorNumElements();
11898 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11899 // operand of these instructions is only memory, so check if there's a
11900 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11902 bool CanFoldLoad = false;
11904 // Trivial case, when V2 comes from a load.
11905 if (MayFoldVectorLoad(V2))
11906 CanFoldLoad = true;
11908 // When V1 is a load, it can be folded later into a store in isel, example:
11909 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11911 // (MOVLPSmr addr:$src1, VR128:$src2)
11912 // So, recognize this potential and also use MOVLPS or MOVLPD
11913 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11914 CanFoldLoad = true;
11916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11918 if (HasSSE2 && NumElems == 2)
11919 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11922 // If we don't care about the second element, proceed to use movss.
11923 if (SVOp->getMaskElt(1) != -1)
11924 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11927 // movl and movlp will both match v2i64, but v2i64 is never matched by
11928 // movl earlier because we make it strict to avoid messing with the movlp load
11929 // folding logic (see the code above getMOVLP call). Match it here then,
11930 // this is horrible, but will stay like this until we move all shuffle
11931 // matching to x86 specific nodes. Note that for the 1st condition all
11932 // types are matched with movsd.
11934 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11935 // as to remove this logic from here, as much as possible
11936 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11937 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11938 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11941 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11943 // Invert the operand order and use SHUFPS to match it.
11944 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11945 getShuffleSHUFImmediate(SVOp), DAG);
11948 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11949 SelectionDAG &DAG) {
11951 MVT VT = Load->getSimpleValueType(0);
11952 MVT EVT = VT.getVectorElementType();
11953 SDValue Addr = Load->getOperand(1);
11954 SDValue NewAddr = DAG.getNode(
11955 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11956 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11959 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11960 DAG.getMachineFunction().getMachineMemOperand(
11961 Load->getMemOperand(), 0, EVT.getStoreSize()));
11965 // It is only safe to call this function if isINSERTPSMask is true for
11966 // this shufflevector mask.
11967 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11968 SelectionDAG &DAG) {
11969 // Generate an insertps instruction when inserting an f32 from memory onto a
11970 // v4f32 or when copying a member from one v4f32 to another.
11971 // We also use it for transferring i32 from one register to another,
11972 // since it simply copies the same bits.
11973 // If we're transferring an i32 from memory to a specific element in a
11974 // register, we output a generic DAG that will match the PINSRD
11976 MVT VT = SVOp->getSimpleValueType(0);
11977 MVT EVT = VT.getVectorElementType();
11978 SDValue V1 = SVOp->getOperand(0);
11979 SDValue V2 = SVOp->getOperand(1);
11980 auto Mask = SVOp->getMask();
11981 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11982 "unsupported vector type for insertps/pinsrd");
11984 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11985 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11986 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11990 unsigned DestIndex;
11994 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11997 // If we have 1 element from each vector, we have to check if we're
11998 // changing V1's element's place. If so, we're done. Otherwise, we
11999 // should assume we're changing V2's element's place and behave
12001 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12002 assert(DestIndex <= INT32_MAX && "truncated destination index");
12003 if (FromV1 == FromV2 &&
12004 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12008 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12011 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12012 "More than one element from V1 and from V2, or no elements from one "
12013 "of the vectors. This case should not have returned true from "
12018 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12021 // Get an index into the source vector in the range [0,4) (the mask is
12022 // in the range [0,8) because it can address V1 and V2)
12023 unsigned SrcIndex = Mask[DestIndex] % 4;
12024 if (MayFoldLoad(From)) {
12025 // Trivial case, when From comes from a load and is only used by the
12026 // shuffle. Make it use insertps from the vector that we need from that
12029 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12030 if (!NewLoad.getNode())
12033 if (EVT == MVT::f32) {
12034 // Create this as a scalar to vector to match the instruction pattern.
12035 SDValue LoadScalarToVector =
12036 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12037 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12038 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12040 } else { // EVT == MVT::i32
12041 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12042 // instruction, to match the PINSRD instruction, which loads an i32 to a
12043 // certain vector element.
12044 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12045 DAG.getConstant(DestIndex, MVT::i32));
12049 // Vector-element-to-vector
12050 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12051 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12054 // Reduce a vector shuffle to zext.
12055 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12056 SelectionDAG &DAG) {
12057 // PMOVZX is only available from SSE41.
12058 if (!Subtarget->hasSSE41())
12061 MVT VT = Op.getSimpleValueType();
12063 // Only AVX2 support 256-bit vector integer extending.
12064 if (!Subtarget->hasInt256() && VT.is256BitVector())
12067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12069 SDValue V1 = Op.getOperand(0);
12070 SDValue V2 = Op.getOperand(1);
12071 unsigned NumElems = VT.getVectorNumElements();
12073 // Extending is an unary operation and the element type of the source vector
12074 // won't be equal to or larger than i64.
12075 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12076 VT.getVectorElementType() == MVT::i64)
12079 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12080 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12081 while ((1U << Shift) < NumElems) {
12082 if (SVOp->getMaskElt(1U << Shift) == 1)
12085 // The maximal ratio is 8, i.e. from i8 to i64.
12090 // Check the shuffle mask.
12091 unsigned Mask = (1U << Shift) - 1;
12092 for (unsigned i = 0; i != NumElems; ++i) {
12093 int EltIdx = SVOp->getMaskElt(i);
12094 if ((i & Mask) != 0 && EltIdx != -1)
12096 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12100 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12101 MVT NeVT = MVT::getIntegerVT(NBits);
12102 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12104 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12107 return DAG.getNode(ISD::BITCAST, DL, VT,
12108 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12111 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12112 SelectionDAG &DAG) {
12113 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12114 MVT VT = Op.getSimpleValueType();
12116 SDValue V1 = Op.getOperand(0);
12117 SDValue V2 = Op.getOperand(1);
12119 if (isZeroShuffle(SVOp))
12120 return getZeroVector(VT, Subtarget, DAG, dl);
12122 // Handle splat operations
12123 if (SVOp->isSplat()) {
12124 // Use vbroadcast whenever the splat comes from a foldable load
12125 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12126 if (Broadcast.getNode())
12130 // Check integer expanding shuffles.
12131 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12132 if (NewOp.getNode())
12135 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12137 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12138 VT == MVT::v32i8) {
12139 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12140 if (NewOp.getNode())
12141 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12142 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12143 // FIXME: Figure out a cleaner way to do this.
12144 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12145 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12146 if (NewOp.getNode()) {
12147 MVT NewVT = NewOp.getSimpleValueType();
12148 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12149 NewVT, true, false))
12150 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12153 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12154 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12155 if (NewOp.getNode()) {
12156 MVT NewVT = NewOp.getSimpleValueType();
12157 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12158 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12167 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12169 SDValue V1 = Op.getOperand(0);
12170 SDValue V2 = Op.getOperand(1);
12171 MVT VT = Op.getSimpleValueType();
12173 unsigned NumElems = VT.getVectorNumElements();
12174 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12175 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12176 bool V1IsSplat = false;
12177 bool V2IsSplat = false;
12178 bool HasSSE2 = Subtarget->hasSSE2();
12179 bool HasFp256 = Subtarget->hasFp256();
12180 bool HasInt256 = Subtarget->hasInt256();
12181 MachineFunction &MF = DAG.getMachineFunction();
12182 bool OptForSize = MF.getFunction()->getAttributes().
12183 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12185 // Check if we should use the experimental vector shuffle lowering. If so,
12186 // delegate completely to that code path.
12187 if (ExperimentalVectorShuffleLowering)
12188 return lowerVectorShuffle(Op, Subtarget, DAG);
12190 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12192 if (V1IsUndef && V2IsUndef)
12193 return DAG.getUNDEF(VT);
12195 // When we create a shuffle node we put the UNDEF node to second operand,
12196 // but in some cases the first operand may be transformed to UNDEF.
12197 // In this case we should just commute the node.
12199 return DAG.getCommutedVectorShuffle(*SVOp);
12201 // Vector shuffle lowering takes 3 steps:
12203 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12204 // narrowing and commutation of operands should be handled.
12205 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12207 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12208 // so the shuffle can be broken into other shuffles and the legalizer can
12209 // try the lowering again.
12211 // The general idea is that no vector_shuffle operation should be left to
12212 // be matched during isel, all of them must be converted to a target specific
12215 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12216 // narrowing and commutation of operands should be handled. The actual code
12217 // doesn't include all of those, work in progress...
12218 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12219 if (NewOp.getNode())
12222 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12224 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12225 // unpckh_undef). Only use pshufd if speed is more important than size.
12226 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12227 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12228 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12229 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12231 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12232 V2IsUndef && MayFoldVectorLoad(V1))
12233 return getMOVDDup(Op, dl, V1, DAG);
12235 if (isMOVHLPS_v_undef_Mask(M, VT))
12236 return getMOVHighToLow(Op, dl, DAG);
12238 // Use to match splats
12239 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12240 (VT == MVT::v2f64 || VT == MVT::v2i64))
12241 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12243 if (isPSHUFDMask(M, VT)) {
12244 // The actual implementation will match the mask in the if above and then
12245 // during isel it can match several different instructions, not only pshufd
12246 // as its name says, sad but true, emulate the behavior for now...
12247 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12248 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12250 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12252 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12253 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12255 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12256 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12259 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12263 if (isPALIGNRMask(M, VT, Subtarget))
12264 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12265 getShufflePALIGNRImmediate(SVOp),
12268 if (isVALIGNMask(M, VT, Subtarget))
12269 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12270 getShuffleVALIGNImmediate(SVOp),
12273 // Check if this can be converted into a logical shift.
12274 bool isLeft = false;
12275 unsigned ShAmt = 0;
12277 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12278 if (isShift && ShVal.hasOneUse()) {
12279 // If the shifted value has multiple uses, it may be cheaper to use
12280 // v_set0 + movlhps or movhlps, etc.
12281 MVT EltVT = VT.getVectorElementType();
12282 ShAmt *= EltVT.getSizeInBits();
12283 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12286 if (isMOVLMask(M, VT)) {
12287 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12288 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12289 if (!isMOVLPMask(M, VT)) {
12290 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12291 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12293 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12294 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12298 // FIXME: fold these into legal mask.
12299 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12300 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12302 if (isMOVHLPSMask(M, VT))
12303 return getMOVHighToLow(Op, dl, DAG);
12305 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12306 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12308 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12309 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12311 if (isMOVLPMask(M, VT))
12312 return getMOVLP(Op, dl, DAG, HasSSE2);
12314 if (ShouldXformToMOVHLPS(M, VT) ||
12315 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12316 return DAG.getCommutedVectorShuffle(*SVOp);
12319 // No better options. Use a vshldq / vsrldq.
12320 MVT EltVT = VT.getVectorElementType();
12321 ShAmt *= EltVT.getSizeInBits();
12322 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12325 bool Commuted = false;
12326 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12327 // 1,1,1,1 -> v8i16 though.
12328 BitVector UndefElements;
12329 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12330 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12332 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12333 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12336 // Canonicalize the splat or undef, if present, to be on the RHS.
12337 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12338 CommuteVectorShuffleMask(M, NumElems);
12340 std::swap(V1IsSplat, V2IsSplat);
12344 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12345 // Shuffling low element of v1 into undef, just return v1.
12348 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12349 // the instruction selector will not match, so get a canonical MOVL with
12350 // swapped operands to undo the commute.
12351 return getMOVL(DAG, dl, VT, V2, V1);
12354 if (isUNPCKLMask(M, VT, HasInt256))
12355 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12357 if (isUNPCKHMask(M, VT, HasInt256))
12358 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12361 // Normalize mask so all entries that point to V2 points to its first
12362 // element then try to match unpck{h|l} again. If match, return a
12363 // new vector_shuffle with the corrected mask.p
12364 SmallVector<int, 8> NewMask(M.begin(), M.end());
12365 NormalizeMask(NewMask, NumElems);
12366 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12367 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12368 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12369 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12373 // Commute is back and try unpck* again.
12374 // FIXME: this seems wrong.
12375 CommuteVectorShuffleMask(M, NumElems);
12377 std::swap(V1IsSplat, V2IsSplat);
12379 if (isUNPCKLMask(M, VT, HasInt256))
12380 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12382 if (isUNPCKHMask(M, VT, HasInt256))
12383 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12386 // Normalize the node to match x86 shuffle ops if needed
12387 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12388 return DAG.getCommutedVectorShuffle(*SVOp);
12390 // The checks below are all present in isShuffleMaskLegal, but they are
12391 // inlined here right now to enable us to directly emit target specific
12392 // nodes, and remove one by one until they don't return Op anymore.
12394 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12395 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12396 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12397 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12400 if (isPSHUFHWMask(M, VT, HasInt256))
12401 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12402 getShufflePSHUFHWImmediate(SVOp),
12405 if (isPSHUFLWMask(M, VT, HasInt256))
12406 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12407 getShufflePSHUFLWImmediate(SVOp),
12410 unsigned MaskValue;
12411 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12413 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12415 if (isSHUFPMask(M, VT))
12416 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12417 getShuffleSHUFImmediate(SVOp), DAG);
12419 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12420 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12421 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12422 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12424 //===--------------------------------------------------------------------===//
12425 // Generate target specific nodes for 128 or 256-bit shuffles only
12426 // supported in the AVX instruction set.
12429 // Handle VMOVDDUPY permutations
12430 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12431 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12433 // Handle VPERMILPS/D* permutations
12434 if (isVPERMILPMask(M, VT)) {
12435 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12436 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12437 getShuffleSHUFImmediate(SVOp), DAG);
12438 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12439 getShuffleSHUFImmediate(SVOp), DAG);
12443 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12444 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12445 Idx*(NumElems/2), DAG, dl);
12447 // Handle VPERM2F128/VPERM2I128 permutations
12448 if (isVPERM2X128Mask(M, VT, HasFp256))
12449 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12450 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12452 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12453 return getINSERTPS(SVOp, dl, DAG);
12456 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12457 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12459 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12460 VT.is512BitVector()) {
12461 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12462 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12463 SmallVector<SDValue, 16> permclMask;
12464 for (unsigned i = 0; i != NumElems; ++i) {
12465 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12468 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12470 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12471 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12472 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12473 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12474 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12477 //===--------------------------------------------------------------------===//
12478 // Since no target specific shuffle was selected for this generic one,
12479 // lower it into other known shuffles. FIXME: this isn't true yet, but
12480 // this is the plan.
12483 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12484 if (VT == MVT::v8i16) {
12485 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12486 if (NewOp.getNode())
12490 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12491 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12492 if (NewOp.getNode())
12496 if (VT == MVT::v16i8) {
12497 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12498 if (NewOp.getNode())
12502 if (VT == MVT::v32i8) {
12503 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12504 if (NewOp.getNode())
12508 // Handle all 128-bit wide vectors with 4 elements, and match them with
12509 // several different shuffle types.
12510 if (NumElems == 4 && VT.is128BitVector())
12511 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12513 // Handle general 256-bit shuffles
12514 if (VT.is256BitVector())
12515 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12520 // This function assumes its argument is a BUILD_VECTOR of constants or
12521 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12523 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12524 unsigned &MaskValue) {
12526 unsigned NumElems = BuildVector->getNumOperands();
12527 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12528 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12529 unsigned NumElemsInLane = NumElems / NumLanes;
12531 // Blend for v16i16 should be symetric for the both lanes.
12532 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12533 SDValue EltCond = BuildVector->getOperand(i);
12534 SDValue SndLaneEltCond =
12535 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12537 int Lane1Cond = -1, Lane2Cond = -1;
12538 if (isa<ConstantSDNode>(EltCond))
12539 Lane1Cond = !isZero(EltCond);
12540 if (isa<ConstantSDNode>(SndLaneEltCond))
12541 Lane2Cond = !isZero(SndLaneEltCond);
12543 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12544 // Lane1Cond != 0, means we want the first argument.
12545 // Lane1Cond == 0, means we want the second argument.
12546 // The encoding of this argument is 0 for the first argument, 1
12547 // for the second. Therefore, invert the condition.
12548 MaskValue |= !Lane1Cond << i;
12549 else if (Lane1Cond < 0)
12550 MaskValue |= !Lane2Cond << i;
12557 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12559 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12560 SelectionDAG &DAG) {
12561 SDValue Cond = Op.getOperand(0);
12562 SDValue LHS = Op.getOperand(1);
12563 SDValue RHS = Op.getOperand(2);
12565 MVT VT = Op.getSimpleValueType();
12566 MVT EltVT = VT.getVectorElementType();
12567 unsigned NumElems = VT.getVectorNumElements();
12569 // There is no blend with immediate in AVX-512.
12570 if (VT.is512BitVector())
12573 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12575 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12578 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12581 // Check the mask for BLEND and build the value.
12582 unsigned MaskValue = 0;
12583 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12586 // Convert i32 vectors to floating point if it is not AVX2.
12587 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12589 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12590 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12592 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12593 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12596 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12597 DAG.getConstant(MaskValue, MVT::i32));
12598 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12601 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12602 // A vselect where all conditions and data are constants can be optimized into
12603 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12604 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12605 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12606 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12609 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12610 if (BlendOp.getNode())
12613 // Some types for vselect were previously set to Expand, not Legal or
12614 // Custom. Return an empty SDValue so we fall-through to Expand, after
12615 // the Custom lowering phase.
12616 MVT VT = Op.getSimpleValueType();
12617 switch (VT.SimpleTy) {
12622 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12627 // We couldn't create a "Blend with immediate" node.
12628 // This node should still be legal, but we'll have to emit a blendv*
12633 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12634 MVT VT = Op.getSimpleValueType();
12637 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12640 if (VT.getSizeInBits() == 8) {
12641 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12642 Op.getOperand(0), Op.getOperand(1));
12643 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12644 DAG.getValueType(VT));
12645 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12648 if (VT.getSizeInBits() == 16) {
12649 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12650 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12652 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12654 DAG.getNode(ISD::BITCAST, dl,
12657 Op.getOperand(1)));
12658 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12659 Op.getOperand(0), Op.getOperand(1));
12660 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12661 DAG.getValueType(VT));
12662 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12665 if (VT == MVT::f32) {
12666 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12667 // the result back to FR32 register. It's only worth matching if the
12668 // result has a single use which is a store or a bitcast to i32. And in
12669 // the case of a store, it's not worth it if the index is a constant 0,
12670 // because a MOVSSmr can be used instead, which is smaller and faster.
12671 if (!Op.hasOneUse())
12673 SDNode *User = *Op.getNode()->use_begin();
12674 if ((User->getOpcode() != ISD::STORE ||
12675 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12676 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12677 (User->getOpcode() != ISD::BITCAST ||
12678 User->getValueType(0) != MVT::i32))
12680 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12681 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12684 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12687 if (VT == MVT::i32 || VT == MVT::i64) {
12688 // ExtractPS/pextrq works with constant index.
12689 if (isa<ConstantSDNode>(Op.getOperand(1)))
12695 /// Extract one bit from mask vector, like v16i1 or v8i1.
12696 /// AVX-512 feature.
12698 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12699 SDValue Vec = Op.getOperand(0);
12701 MVT VecVT = Vec.getSimpleValueType();
12702 SDValue Idx = Op.getOperand(1);
12703 MVT EltVT = Op.getSimpleValueType();
12705 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12707 // variable index can't be handled in mask registers,
12708 // extend vector to VR512
12709 if (!isa<ConstantSDNode>(Idx)) {
12710 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12711 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12712 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12713 ExtVT.getVectorElementType(), Ext, Idx);
12714 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12717 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12718 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12719 unsigned MaxSift = rc->getSize()*8 - 1;
12720 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12721 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12722 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12723 DAG.getConstant(MaxSift, MVT::i8));
12724 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12725 DAG.getIntPtrConstant(0));
12729 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12730 SelectionDAG &DAG) const {
12732 SDValue Vec = Op.getOperand(0);
12733 MVT VecVT = Vec.getSimpleValueType();
12734 SDValue Idx = Op.getOperand(1);
12736 if (Op.getSimpleValueType() == MVT::i1)
12737 return ExtractBitFromMaskVector(Op, DAG);
12739 if (!isa<ConstantSDNode>(Idx)) {
12740 if (VecVT.is512BitVector() ||
12741 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12742 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12745 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12746 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12747 MaskEltVT.getSizeInBits());
12749 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12750 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12751 getZeroVector(MaskVT, Subtarget, DAG, dl),
12752 Idx, DAG.getConstant(0, getPointerTy()));
12753 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12754 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12755 Perm, DAG.getConstant(0, getPointerTy()));
12760 // If this is a 256-bit vector result, first extract the 128-bit vector and
12761 // then extract the element from the 128-bit vector.
12762 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12764 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12765 // Get the 128-bit vector.
12766 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12767 MVT EltVT = VecVT.getVectorElementType();
12769 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12771 //if (IdxVal >= NumElems/2)
12772 // IdxVal -= NumElems/2;
12773 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12774 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12775 DAG.getConstant(IdxVal, MVT::i32));
12778 assert(VecVT.is128BitVector() && "Unexpected vector length");
12780 if (Subtarget->hasSSE41()) {
12781 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12786 MVT VT = Op.getSimpleValueType();
12787 // TODO: handle v16i8.
12788 if (VT.getSizeInBits() == 16) {
12789 SDValue Vec = Op.getOperand(0);
12790 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12792 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12794 DAG.getNode(ISD::BITCAST, dl,
12796 Op.getOperand(1)));
12797 // Transform it so it match pextrw which produces a 32-bit result.
12798 MVT EltVT = MVT::i32;
12799 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12800 Op.getOperand(0), Op.getOperand(1));
12801 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12802 DAG.getValueType(VT));
12803 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12806 if (VT.getSizeInBits() == 32) {
12807 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12811 // SHUFPS the element to the lowest double word, then movss.
12812 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12813 MVT VVT = Op.getOperand(0).getSimpleValueType();
12814 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12815 DAG.getUNDEF(VVT), Mask);
12816 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12817 DAG.getIntPtrConstant(0));
12820 if (VT.getSizeInBits() == 64) {
12821 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12822 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12823 // to match extract_elt for f64.
12824 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12828 // UNPCKHPD the element to the lowest double word, then movsd.
12829 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12830 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12831 int Mask[2] = { 1, -1 };
12832 MVT VVT = Op.getOperand(0).getSimpleValueType();
12833 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12834 DAG.getUNDEF(VVT), Mask);
12835 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12836 DAG.getIntPtrConstant(0));
12842 /// Insert one bit to mask vector, like v16i1 or v8i1.
12843 /// AVX-512 feature.
12845 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12847 SDValue Vec = Op.getOperand(0);
12848 SDValue Elt = Op.getOperand(1);
12849 SDValue Idx = Op.getOperand(2);
12850 MVT VecVT = Vec.getSimpleValueType();
12852 if (!isa<ConstantSDNode>(Idx)) {
12853 // Non constant index. Extend source and destination,
12854 // insert element and then truncate the result.
12855 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12856 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12857 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12858 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12859 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12860 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12863 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12864 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12865 if (Vec.getOpcode() == ISD::UNDEF)
12866 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12867 DAG.getConstant(IdxVal, MVT::i8));
12868 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12869 unsigned MaxSift = rc->getSize()*8 - 1;
12870 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12871 DAG.getConstant(MaxSift, MVT::i8));
12872 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12873 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12874 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12877 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12878 SelectionDAG &DAG) const {
12879 MVT VT = Op.getSimpleValueType();
12880 MVT EltVT = VT.getVectorElementType();
12882 if (EltVT == MVT::i1)
12883 return InsertBitToMaskVector(Op, DAG);
12886 SDValue N0 = Op.getOperand(0);
12887 SDValue N1 = Op.getOperand(1);
12888 SDValue N2 = Op.getOperand(2);
12889 if (!isa<ConstantSDNode>(N2))
12891 auto *N2C = cast<ConstantSDNode>(N2);
12892 unsigned IdxVal = N2C->getZExtValue();
12894 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12895 // into that, and then insert the subvector back into the result.
12896 if (VT.is256BitVector() || VT.is512BitVector()) {
12897 // Get the desired 128-bit vector half.
12898 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12900 // Insert the element into the desired half.
12901 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12902 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12904 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12905 DAG.getConstant(IdxIn128, MVT::i32));
12907 // Insert the changed part back to the 256-bit vector
12908 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12910 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12912 if (Subtarget->hasSSE41()) {
12913 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12915 if (VT == MVT::v8i16) {
12916 Opc = X86ISD::PINSRW;
12918 assert(VT == MVT::v16i8);
12919 Opc = X86ISD::PINSRB;
12922 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12924 if (N1.getValueType() != MVT::i32)
12925 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12926 if (N2.getValueType() != MVT::i32)
12927 N2 = DAG.getIntPtrConstant(IdxVal);
12928 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12931 if (EltVT == MVT::f32) {
12932 // Bits [7:6] of the constant are the source select. This will always be
12933 // zero here. The DAG Combiner may combine an extract_elt index into
12935 // bits. For example (insert (extract, 3), 2) could be matched by
12937 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12938 // Bits [5:4] of the constant are the destination select. This is the
12939 // value of the incoming immediate.
12940 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12941 // combine either bitwise AND or insert of float 0.0 to set these bits.
12942 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12943 // Create this as a scalar to vector..
12944 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12945 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12948 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12949 // PINSR* works with constant index.
12954 if (EltVT == MVT::i8)
12957 if (EltVT.getSizeInBits() == 16) {
12958 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12959 // as its second argument.
12960 if (N1.getValueType() != MVT::i32)
12961 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12962 if (N2.getValueType() != MVT::i32)
12963 N2 = DAG.getIntPtrConstant(IdxVal);
12964 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12969 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12971 MVT OpVT = Op.getSimpleValueType();
12973 // If this is a 256-bit vector result, first insert into a 128-bit
12974 // vector and then insert into the 256-bit vector.
12975 if (!OpVT.is128BitVector()) {
12976 // Insert into a 128-bit vector.
12977 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12978 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12979 OpVT.getVectorNumElements() / SizeFactor);
12981 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12983 // Insert the 128-bit vector.
12984 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12987 if (OpVT == MVT::v1i64 &&
12988 Op.getOperand(0).getValueType() == MVT::i64)
12989 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12991 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12992 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12993 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12994 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12997 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12998 // a simple subregister reference or explicit instructions to grab
12999 // upper bits of a vector.
13000 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13001 SelectionDAG &DAG) {
13003 SDValue In = Op.getOperand(0);
13004 SDValue Idx = Op.getOperand(1);
13005 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13006 MVT ResVT = Op.getSimpleValueType();
13007 MVT InVT = In.getSimpleValueType();
13009 if (Subtarget->hasFp256()) {
13010 if (ResVT.is128BitVector() &&
13011 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13012 isa<ConstantSDNode>(Idx)) {
13013 return Extract128BitVector(In, IdxVal, DAG, dl);
13015 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13016 isa<ConstantSDNode>(Idx)) {
13017 return Extract256BitVector(In, IdxVal, DAG, dl);
13023 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13024 // simple superregister reference or explicit instructions to insert
13025 // the upper bits of a vector.
13026 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13027 SelectionDAG &DAG) {
13028 if (Subtarget->hasFp256()) {
13029 SDLoc dl(Op.getNode());
13030 SDValue Vec = Op.getNode()->getOperand(0);
13031 SDValue SubVec = Op.getNode()->getOperand(1);
13032 SDValue Idx = Op.getNode()->getOperand(2);
13034 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13035 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13036 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13037 isa<ConstantSDNode>(Idx)) {
13038 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13039 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13042 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13043 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13044 isa<ConstantSDNode>(Idx)) {
13045 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13046 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13052 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13053 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13054 // one of the above mentioned nodes. It has to be wrapped because otherwise
13055 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13056 // be used to form addressing mode. These wrapped nodes will be selected
13059 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13060 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13062 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13063 // global base reg.
13064 unsigned char OpFlag = 0;
13065 unsigned WrapperKind = X86ISD::Wrapper;
13066 CodeModel::Model M = DAG.getTarget().getCodeModel();
13068 if (Subtarget->isPICStyleRIPRel() &&
13069 (M == CodeModel::Small || M == CodeModel::Kernel))
13070 WrapperKind = X86ISD::WrapperRIP;
13071 else if (Subtarget->isPICStyleGOT())
13072 OpFlag = X86II::MO_GOTOFF;
13073 else if (Subtarget->isPICStyleStubPIC())
13074 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13076 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13077 CP->getAlignment(),
13078 CP->getOffset(), OpFlag);
13080 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13081 // With PIC, the address is actually $g + Offset.
13083 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13084 DAG.getNode(X86ISD::GlobalBaseReg,
13085 SDLoc(), getPointerTy()),
13092 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13093 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13095 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13096 // global base reg.
13097 unsigned char OpFlag = 0;
13098 unsigned WrapperKind = X86ISD::Wrapper;
13099 CodeModel::Model M = DAG.getTarget().getCodeModel();
13101 if (Subtarget->isPICStyleRIPRel() &&
13102 (M == CodeModel::Small || M == CodeModel::Kernel))
13103 WrapperKind = X86ISD::WrapperRIP;
13104 else if (Subtarget->isPICStyleGOT())
13105 OpFlag = X86II::MO_GOTOFF;
13106 else if (Subtarget->isPICStyleStubPIC())
13107 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13109 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13112 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13114 // With PIC, the address is actually $g + Offset.
13116 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13117 DAG.getNode(X86ISD::GlobalBaseReg,
13118 SDLoc(), getPointerTy()),
13125 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13126 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13128 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13129 // global base reg.
13130 unsigned char OpFlag = 0;
13131 unsigned WrapperKind = X86ISD::Wrapper;
13132 CodeModel::Model M = DAG.getTarget().getCodeModel();
13134 if (Subtarget->isPICStyleRIPRel() &&
13135 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13136 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13137 OpFlag = X86II::MO_GOTPCREL;
13138 WrapperKind = X86ISD::WrapperRIP;
13139 } else if (Subtarget->isPICStyleGOT()) {
13140 OpFlag = X86II::MO_GOT;
13141 } else if (Subtarget->isPICStyleStubPIC()) {
13142 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13143 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13144 OpFlag = X86II::MO_DARWIN_NONLAZY;
13147 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13150 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13152 // With PIC, the address is actually $g + Offset.
13153 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13154 !Subtarget->is64Bit()) {
13155 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13156 DAG.getNode(X86ISD::GlobalBaseReg,
13157 SDLoc(), getPointerTy()),
13161 // For symbols that require a load from a stub to get the address, emit the
13163 if (isGlobalStubReference(OpFlag))
13164 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13165 MachinePointerInfo::getGOT(), false, false, false, 0);
13171 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13172 // Create the TargetBlockAddressAddress node.
13173 unsigned char OpFlags =
13174 Subtarget->ClassifyBlockAddressReference();
13175 CodeModel::Model M = DAG.getTarget().getCodeModel();
13176 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13177 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13179 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13182 if (Subtarget->isPICStyleRIPRel() &&
13183 (M == CodeModel::Small || M == CodeModel::Kernel))
13184 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13186 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13188 // With PIC, the address is actually $g + Offset.
13189 if (isGlobalRelativeToPICBase(OpFlags)) {
13190 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13191 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13199 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13200 int64_t Offset, SelectionDAG &DAG) const {
13201 // Create the TargetGlobalAddress node, folding in the constant
13202 // offset if it is legal.
13203 unsigned char OpFlags =
13204 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13205 CodeModel::Model M = DAG.getTarget().getCodeModel();
13207 if (OpFlags == X86II::MO_NO_FLAG &&
13208 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13209 // A direct static reference to a global.
13210 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13213 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13216 if (Subtarget->isPICStyleRIPRel() &&
13217 (M == CodeModel::Small || M == CodeModel::Kernel))
13218 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13220 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13222 // With PIC, the address is actually $g + Offset.
13223 if (isGlobalRelativeToPICBase(OpFlags)) {
13224 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13225 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13229 // For globals that require a load from a stub to get the address, emit the
13231 if (isGlobalStubReference(OpFlags))
13232 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13233 MachinePointerInfo::getGOT(), false, false, false, 0);
13235 // If there was a non-zero offset that we didn't fold, create an explicit
13236 // addition for it.
13238 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13239 DAG.getConstant(Offset, getPointerTy()));
13245 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13246 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13247 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13248 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13252 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13253 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13254 unsigned char OperandFlags, bool LocalDynamic = false) {
13255 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13256 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13258 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13259 GA->getValueType(0),
13263 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13267 SDValue Ops[] = { Chain, TGA, *InFlag };
13268 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13270 SDValue Ops[] = { Chain, TGA };
13271 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13274 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13275 MFI->setAdjustsStack(true);
13276 MFI->setHasCalls(true);
13278 SDValue Flag = Chain.getValue(1);
13279 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13282 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13284 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13287 SDLoc dl(GA); // ? function entry point might be better
13288 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13289 DAG.getNode(X86ISD::GlobalBaseReg,
13290 SDLoc(), PtrVT), InFlag);
13291 InFlag = Chain.getValue(1);
13293 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13296 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13298 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13300 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13301 X86::RAX, X86II::MO_TLSGD);
13304 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13310 // Get the start address of the TLS block for this module.
13311 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13312 .getInfo<X86MachineFunctionInfo>();
13313 MFI->incNumLocalDynamicTLSAccesses();
13317 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13318 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13321 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13322 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13323 InFlag = Chain.getValue(1);
13324 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13325 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13328 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13332 unsigned char OperandFlags = X86II::MO_DTPOFF;
13333 unsigned WrapperKind = X86ISD::Wrapper;
13334 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13335 GA->getValueType(0),
13336 GA->getOffset(), OperandFlags);
13337 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13339 // Add x@dtpoff with the base.
13340 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13343 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13344 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13345 const EVT PtrVT, TLSModel::Model model,
13346 bool is64Bit, bool isPIC) {
13349 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13350 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13351 is64Bit ? 257 : 256));
13353 SDValue ThreadPointer =
13354 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13355 MachinePointerInfo(Ptr), false, false, false, 0);
13357 unsigned char OperandFlags = 0;
13358 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13360 unsigned WrapperKind = X86ISD::Wrapper;
13361 if (model == TLSModel::LocalExec) {
13362 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13363 } else if (model == TLSModel::InitialExec) {
13365 OperandFlags = X86II::MO_GOTTPOFF;
13366 WrapperKind = X86ISD::WrapperRIP;
13368 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13371 llvm_unreachable("Unexpected model");
13374 // emit "addl x@ntpoff,%eax" (local exec)
13375 // or "addl x@indntpoff,%eax" (initial exec)
13376 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13378 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13379 GA->getOffset(), OperandFlags);
13380 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13382 if (model == TLSModel::InitialExec) {
13383 if (isPIC && !is64Bit) {
13384 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13385 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13389 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13390 MachinePointerInfo::getGOT(), false, false, false, 0);
13393 // The address of the thread local variable is the add of the thread
13394 // pointer with the offset of the variable.
13395 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13399 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13401 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13402 const GlobalValue *GV = GA->getGlobal();
13404 if (Subtarget->isTargetELF()) {
13405 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13408 case TLSModel::GeneralDynamic:
13409 if (Subtarget->is64Bit())
13410 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13411 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13412 case TLSModel::LocalDynamic:
13413 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13414 Subtarget->is64Bit());
13415 case TLSModel::InitialExec:
13416 case TLSModel::LocalExec:
13417 return LowerToTLSExecModel(
13418 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13419 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13421 llvm_unreachable("Unknown TLS model.");
13424 if (Subtarget->isTargetDarwin()) {
13425 // Darwin only has one model of TLS. Lower to that.
13426 unsigned char OpFlag = 0;
13427 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13428 X86ISD::WrapperRIP : X86ISD::Wrapper;
13430 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13431 // global base reg.
13432 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13433 !Subtarget->is64Bit();
13435 OpFlag = X86II::MO_TLVP_PIC_BASE;
13437 OpFlag = X86II::MO_TLVP;
13439 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13440 GA->getValueType(0),
13441 GA->getOffset(), OpFlag);
13442 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13444 // With PIC32, the address is actually $g + Offset.
13446 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13447 DAG.getNode(X86ISD::GlobalBaseReg,
13448 SDLoc(), getPointerTy()),
13451 // Lowering the machine isd will make sure everything is in the right
13453 SDValue Chain = DAG.getEntryNode();
13454 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13455 SDValue Args[] = { Chain, Offset };
13456 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13458 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13459 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13460 MFI->setAdjustsStack(true);
13462 // And our return value (tls address) is in the standard call return value
13464 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13465 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13466 Chain.getValue(1));
13469 if (Subtarget->isTargetKnownWindowsMSVC() ||
13470 Subtarget->isTargetWindowsGNU()) {
13471 // Just use the implicit TLS architecture
13472 // Need to generate someting similar to:
13473 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13475 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13476 // mov rcx, qword [rdx+rcx*8]
13477 // mov eax, .tls$:tlsvar
13478 // [rax+rcx] contains the address
13479 // Windows 64bit: gs:0x58
13480 // Windows 32bit: fs:__tls_array
13483 SDValue Chain = DAG.getEntryNode();
13485 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13486 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13487 // use its literal value of 0x2C.
13488 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13489 ? Type::getInt8PtrTy(*DAG.getContext(),
13491 : Type::getInt32PtrTy(*DAG.getContext(),
13495 Subtarget->is64Bit()
13496 ? DAG.getIntPtrConstant(0x58)
13497 : (Subtarget->isTargetWindowsGNU()
13498 ? DAG.getIntPtrConstant(0x2C)
13499 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13501 SDValue ThreadPointer =
13502 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13503 MachinePointerInfo(Ptr), false, false, false, 0);
13505 // Load the _tls_index variable
13506 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13507 if (Subtarget->is64Bit())
13508 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13509 IDX, MachinePointerInfo(), MVT::i32,
13510 false, false, false, 0);
13512 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13513 false, false, false, 0);
13515 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13517 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13519 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13520 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13521 false, false, false, 0);
13523 // Get the offset of start of .tls section
13524 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13525 GA->getValueType(0),
13526 GA->getOffset(), X86II::MO_SECREL);
13527 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13529 // The address of the thread local variable is the add of the thread
13530 // pointer with the offset of the variable.
13531 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13534 llvm_unreachable("TLS not implemented for this target.");
13537 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13538 /// and take a 2 x i32 value to shift plus a shift amount.
13539 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13540 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13541 MVT VT = Op.getSimpleValueType();
13542 unsigned VTBits = VT.getSizeInBits();
13544 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13545 SDValue ShOpLo = Op.getOperand(0);
13546 SDValue ShOpHi = Op.getOperand(1);
13547 SDValue ShAmt = Op.getOperand(2);
13548 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13549 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13551 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13552 DAG.getConstant(VTBits - 1, MVT::i8));
13553 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13554 DAG.getConstant(VTBits - 1, MVT::i8))
13555 : DAG.getConstant(0, VT);
13557 SDValue Tmp2, Tmp3;
13558 if (Op.getOpcode() == ISD::SHL_PARTS) {
13559 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13560 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13562 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13563 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13566 // If the shift amount is larger or equal than the width of a part we can't
13567 // rely on the results of shld/shrd. Insert a test and select the appropriate
13568 // values for large shift amounts.
13569 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13570 DAG.getConstant(VTBits, MVT::i8));
13571 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13572 AndNode, DAG.getConstant(0, MVT::i8));
13575 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13576 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13577 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13579 if (Op.getOpcode() == ISD::SHL_PARTS) {
13580 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13581 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13583 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13584 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13587 SDValue Ops[2] = { Lo, Hi };
13588 return DAG.getMergeValues(Ops, dl);
13591 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13592 SelectionDAG &DAG) const {
13593 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13596 if (SrcVT.isVector()) {
13597 if (SrcVT.getVectorElementType() == MVT::i1) {
13598 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13599 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13600 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13601 Op.getOperand(0)));
13606 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13607 "Unknown SINT_TO_FP to lower!");
13609 // These are really Legal; return the operand so the caller accepts it as
13611 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13613 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13614 Subtarget->is64Bit()) {
13618 unsigned Size = SrcVT.getSizeInBits()/8;
13619 MachineFunction &MF = DAG.getMachineFunction();
13620 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13621 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13622 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13624 MachinePointerInfo::getFixedStack(SSFI),
13626 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13629 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13631 SelectionDAG &DAG) const {
13635 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13637 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13639 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13641 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13643 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13644 MachineMemOperand *MMO;
13646 int SSFI = FI->getIndex();
13648 DAG.getMachineFunction()
13649 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13650 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13652 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13653 StackSlot = StackSlot.getOperand(1);
13655 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13656 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13658 Tys, Ops, SrcVT, MMO);
13661 Chain = Result.getValue(1);
13662 SDValue InFlag = Result.getValue(2);
13664 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13665 // shouldn't be necessary except that RFP cannot be live across
13666 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13667 MachineFunction &MF = DAG.getMachineFunction();
13668 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13669 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13670 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13671 Tys = DAG.getVTList(MVT::Other);
13673 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13675 MachineMemOperand *MMO =
13676 DAG.getMachineFunction()
13677 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13678 MachineMemOperand::MOStore, SSFISize, SSFISize);
13680 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13681 Ops, Op.getValueType(), MMO);
13682 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13683 MachinePointerInfo::getFixedStack(SSFI),
13684 false, false, false, 0);
13690 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13691 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13692 SelectionDAG &DAG) const {
13693 // This algorithm is not obvious. Here it is what we're trying to output:
13696 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13697 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13699 haddpd %xmm0, %xmm0
13701 pshufd $0x4e, %xmm0, %xmm1
13707 LLVMContext *Context = DAG.getContext();
13709 // Build some magic constants.
13710 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13711 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13712 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13714 SmallVector<Constant*,2> CV1;
13716 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13717 APInt(64, 0x4330000000000000ULL))));
13719 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13720 APInt(64, 0x4530000000000000ULL))));
13721 Constant *C1 = ConstantVector::get(CV1);
13722 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13724 // Load the 64-bit value into an XMM register.
13725 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13727 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13728 MachinePointerInfo::getConstantPool(),
13729 false, false, false, 16);
13730 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13734 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13735 MachinePointerInfo::getConstantPool(),
13736 false, false, false, 16);
13737 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13738 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13741 if (Subtarget->hasSSE3()) {
13742 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13743 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13745 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13746 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13748 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13749 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13754 DAG.getIntPtrConstant(0));
13757 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13758 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13759 SelectionDAG &DAG) const {
13761 // FP constant to bias correct the final result.
13762 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13765 // Load the 32-bit value into an XMM register.
13766 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13769 // Zero out the upper parts of the register.
13770 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13772 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13773 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13774 DAG.getIntPtrConstant(0));
13776 // Or the load with the bias.
13777 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13778 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13779 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13780 MVT::v2f64, Load)),
13781 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13782 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13783 MVT::v2f64, Bias)));
13784 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13785 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13786 DAG.getIntPtrConstant(0));
13788 // Subtract the bias.
13789 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13791 // Handle final rounding.
13792 EVT DestVT = Op.getValueType();
13794 if (DestVT.bitsLT(MVT::f64))
13795 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13796 DAG.getIntPtrConstant(0));
13797 if (DestVT.bitsGT(MVT::f64))
13798 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13800 // Handle final rounding.
13804 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13805 const X86Subtarget &Subtarget) {
13806 // The algorithm is the following:
13807 // #ifdef __SSE4_1__
13808 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13809 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13810 // (uint4) 0x53000000, 0xaa);
13812 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13813 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13815 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13816 // return (float4) lo + fhi;
13819 SDValue V = Op->getOperand(0);
13820 EVT VecIntVT = V.getValueType();
13821 bool Is128 = VecIntVT == MVT::v4i32;
13822 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13823 // If we convert to something else than the supported type, e.g., to v4f64,
13825 if (VecFloatVT != Op->getValueType(0))
13828 unsigned NumElts = VecIntVT.getVectorNumElements();
13829 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13830 "Unsupported custom type");
13831 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13833 // In the #idef/#else code, we have in common:
13834 // - The vector of constants:
13840 // Create the splat vector for 0x4b000000.
13841 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13842 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13843 CstLow, CstLow, CstLow, CstLow};
13844 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13845 makeArrayRef(&CstLowArray[0], NumElts));
13846 // Create the splat vector for 0x53000000.
13847 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13848 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13849 CstHigh, CstHigh, CstHigh, CstHigh};
13850 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13851 makeArrayRef(&CstHighArray[0], NumElts));
13853 // Create the right shift.
13854 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13855 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13856 CstShift, CstShift, CstShift, CstShift};
13857 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13858 makeArrayRef(&CstShiftArray[0], NumElts));
13859 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13862 if (Subtarget.hasSSE41()) {
13863 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13864 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13865 SDValue VecCstLowBitcast =
13866 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13867 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13868 // Low will be bitcasted right away, so do not bother bitcasting back to its
13870 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13871 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13872 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13873 // (uint4) 0x53000000, 0xaa);
13874 SDValue VecCstHighBitcast =
13875 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13876 SDValue VecShiftBitcast =
13877 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13878 // High will be bitcasted right away, so do not bother bitcasting back to
13879 // its original type.
13880 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13881 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13883 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13884 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13885 CstMask, CstMask, CstMask);
13886 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13887 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13888 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13890 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13891 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13894 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13895 SDValue CstFAdd = DAG.getConstantFP(
13896 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13897 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13898 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13899 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13900 makeArrayRef(&CstFAddArray[0], NumElts));
13902 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13903 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13905 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13906 // return (float4) lo + fhi;
13907 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13908 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13911 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13912 SelectionDAG &DAG) const {
13913 SDValue N0 = Op.getOperand(0);
13914 MVT SVT = N0.getSimpleValueType();
13917 switch (SVT.SimpleTy) {
13919 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13924 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13925 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13926 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13930 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13932 llvm_unreachable(nullptr);
13935 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13936 SelectionDAG &DAG) const {
13937 SDValue N0 = Op.getOperand(0);
13940 if (Op.getValueType().isVector())
13941 return lowerUINT_TO_FP_vec(Op, DAG);
13943 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13944 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13945 // the optimization here.
13946 if (DAG.SignBitIsZero(N0))
13947 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13949 MVT SrcVT = N0.getSimpleValueType();
13950 MVT DstVT = Op.getSimpleValueType();
13951 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13952 return LowerUINT_TO_FP_i64(Op, DAG);
13953 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13954 return LowerUINT_TO_FP_i32(Op, DAG);
13955 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13958 // Make a 64-bit buffer, and use it to build an FILD.
13959 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13960 if (SrcVT == MVT::i32) {
13961 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13962 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13963 getPointerTy(), StackSlot, WordOff);
13964 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13965 StackSlot, MachinePointerInfo(),
13967 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13968 OffsetSlot, MachinePointerInfo(),
13970 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13974 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13975 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13976 StackSlot, MachinePointerInfo(),
13978 // For i64 source, we need to add the appropriate power of 2 if the input
13979 // was negative. This is the same as the optimization in
13980 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13981 // we must be careful to do the computation in x87 extended precision, not
13982 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13983 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13984 MachineMemOperand *MMO =
13985 DAG.getMachineFunction()
13986 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13987 MachineMemOperand::MOLoad, 8, 8);
13989 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13990 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13991 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13994 APInt FF(32, 0x5F800000ULL);
13996 // Check whether the sign bit is set.
13997 SDValue SignSet = DAG.getSetCC(dl,
13998 getSetCCResultType(*DAG.getContext(), MVT::i64),
13999 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14002 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14003 SDValue FudgePtr = DAG.getConstantPool(
14004 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14007 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14008 SDValue Zero = DAG.getIntPtrConstant(0);
14009 SDValue Four = DAG.getIntPtrConstant(4);
14010 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14012 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14014 // Load the value out, extending it from f32 to f80.
14015 // FIXME: Avoid the extend by constructing the right constant pool?
14016 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14017 FudgePtr, MachinePointerInfo::getConstantPool(),
14018 MVT::f32, false, false, false, 4);
14019 // Extend everything to 80 bits to force it to be done on x87.
14020 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14021 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14024 std::pair<SDValue,SDValue>
14025 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14026 bool IsSigned, bool IsReplace) const {
14029 EVT DstTy = Op.getValueType();
14031 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14032 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14036 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14037 DstTy.getSimpleVT() >= MVT::i16 &&
14038 "Unknown FP_TO_INT to lower!");
14040 // These are really Legal.
14041 if (DstTy == MVT::i32 &&
14042 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14043 return std::make_pair(SDValue(), SDValue());
14044 if (Subtarget->is64Bit() &&
14045 DstTy == MVT::i64 &&
14046 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14047 return std::make_pair(SDValue(), SDValue());
14049 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14050 // stack slot, or into the FTOL runtime function.
14051 MachineFunction &MF = DAG.getMachineFunction();
14052 unsigned MemSize = DstTy.getSizeInBits()/8;
14053 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14054 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14057 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14058 Opc = X86ISD::WIN_FTOL;
14060 switch (DstTy.getSimpleVT().SimpleTy) {
14061 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14062 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14063 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14064 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14067 SDValue Chain = DAG.getEntryNode();
14068 SDValue Value = Op.getOperand(0);
14069 EVT TheVT = Op.getOperand(0).getValueType();
14070 // FIXME This causes a redundant load/store if the SSE-class value is already
14071 // in memory, such as if it is on the callstack.
14072 if (isScalarFPTypeInSSEReg(TheVT)) {
14073 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14074 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14075 MachinePointerInfo::getFixedStack(SSFI),
14077 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14079 Chain, StackSlot, DAG.getValueType(TheVT)
14082 MachineMemOperand *MMO =
14083 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14084 MachineMemOperand::MOLoad, MemSize, MemSize);
14085 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14086 Chain = Value.getValue(1);
14087 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14088 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14091 MachineMemOperand *MMO =
14092 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14093 MachineMemOperand::MOStore, MemSize, MemSize);
14095 if (Opc != X86ISD::WIN_FTOL) {
14096 // Build the FP_TO_INT*_IN_MEM
14097 SDValue Ops[] = { Chain, Value, StackSlot };
14098 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14100 return std::make_pair(FIST, StackSlot);
14102 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14103 DAG.getVTList(MVT::Other, MVT::Glue),
14105 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14106 MVT::i32, ftol.getValue(1));
14107 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14108 MVT::i32, eax.getValue(2));
14109 SDValue Ops[] = { eax, edx };
14110 SDValue pair = IsReplace
14111 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14112 : DAG.getMergeValues(Ops, DL);
14113 return std::make_pair(pair, SDValue());
14117 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14118 const X86Subtarget *Subtarget) {
14119 MVT VT = Op->getSimpleValueType(0);
14120 SDValue In = Op->getOperand(0);
14121 MVT InVT = In.getSimpleValueType();
14124 // Optimize vectors in AVX mode:
14127 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14128 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14129 // Concat upper and lower parts.
14132 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14133 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14134 // Concat upper and lower parts.
14137 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14138 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14139 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14142 if (Subtarget->hasInt256())
14143 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14145 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14146 SDValue Undef = DAG.getUNDEF(InVT);
14147 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14148 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14149 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14151 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14152 VT.getVectorNumElements()/2);
14154 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14155 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14157 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14160 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14161 SelectionDAG &DAG) {
14162 MVT VT = Op->getSimpleValueType(0);
14163 SDValue In = Op->getOperand(0);
14164 MVT InVT = In.getSimpleValueType();
14166 unsigned int NumElts = VT.getVectorNumElements();
14167 if (NumElts != 8 && NumElts != 16)
14170 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14171 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14173 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14175 // Now we have only mask extension
14176 assert(InVT.getVectorElementType() == MVT::i1);
14177 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14178 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14179 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14180 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14181 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14182 MachinePointerInfo::getConstantPool(),
14183 false, false, false, Alignment);
14185 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14186 if (VT.is512BitVector())
14188 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14191 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14192 SelectionDAG &DAG) {
14193 if (Subtarget->hasFp256()) {
14194 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14202 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14203 SelectionDAG &DAG) {
14205 MVT VT = Op.getSimpleValueType();
14206 SDValue In = Op.getOperand(0);
14207 MVT SVT = In.getSimpleValueType();
14209 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14210 return LowerZERO_EXTEND_AVX512(Op, DAG);
14212 if (Subtarget->hasFp256()) {
14213 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14218 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14219 VT.getVectorNumElements() != SVT.getVectorNumElements());
14223 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14225 MVT VT = Op.getSimpleValueType();
14226 SDValue In = Op.getOperand(0);
14227 MVT InVT = In.getSimpleValueType();
14229 if (VT == MVT::i1) {
14230 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14231 "Invalid scalar TRUNCATE operation");
14232 if (InVT.getSizeInBits() >= 32)
14234 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14235 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14237 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14238 "Invalid TRUNCATE operation");
14240 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14241 if (VT.getVectorElementType().getSizeInBits() >=8)
14242 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14244 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14245 unsigned NumElts = InVT.getVectorNumElements();
14246 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14247 if (InVT.getSizeInBits() < 512) {
14248 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14249 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14253 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14254 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14255 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14256 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14257 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14258 MachinePointerInfo::getConstantPool(),
14259 false, false, false, Alignment);
14260 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14261 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14262 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14265 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14266 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14267 if (Subtarget->hasInt256()) {
14268 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14269 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14270 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14272 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14273 DAG.getIntPtrConstant(0));
14276 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14277 DAG.getIntPtrConstant(0));
14278 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14279 DAG.getIntPtrConstant(2));
14280 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14281 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14282 static const int ShufMask[] = {0, 2, 4, 6};
14283 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14286 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14287 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14288 if (Subtarget->hasInt256()) {
14289 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14291 SmallVector<SDValue,32> pshufbMask;
14292 for (unsigned i = 0; i < 2; ++i) {
14293 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14294 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14295 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14296 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14297 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14298 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14299 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14300 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14301 for (unsigned j = 0; j < 8; ++j)
14302 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14304 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14305 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14306 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14308 static const int ShufMask[] = {0, 2, -1, -1};
14309 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14311 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14312 DAG.getIntPtrConstant(0));
14313 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14316 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14317 DAG.getIntPtrConstant(0));
14319 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14320 DAG.getIntPtrConstant(4));
14322 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14323 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14325 // The PSHUFB mask:
14326 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14327 -1, -1, -1, -1, -1, -1, -1, -1};
14329 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14330 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14331 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14333 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14334 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14336 // The MOVLHPS Mask:
14337 static const int ShufMask2[] = {0, 1, 4, 5};
14338 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14339 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14342 // Handle truncation of V256 to V128 using shuffles.
14343 if (!VT.is128BitVector() || !InVT.is256BitVector())
14346 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14348 unsigned NumElems = VT.getVectorNumElements();
14349 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14351 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14352 // Prepare truncation shuffle mask
14353 for (unsigned i = 0; i != NumElems; ++i)
14354 MaskVec[i] = i * 2;
14355 SDValue V = DAG.getVectorShuffle(NVT, DL,
14356 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14357 DAG.getUNDEF(NVT), &MaskVec[0]);
14358 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14359 DAG.getIntPtrConstant(0));
14362 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14363 SelectionDAG &DAG) const {
14364 assert(!Op.getSimpleValueType().isVector());
14366 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14367 /*IsSigned=*/ true, /*IsReplace=*/ false);
14368 SDValue FIST = Vals.first, StackSlot = Vals.second;
14369 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14370 if (!FIST.getNode()) return Op;
14372 if (StackSlot.getNode())
14373 // Load the result.
14374 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14375 FIST, StackSlot, MachinePointerInfo(),
14376 false, false, false, 0);
14378 // The node is the result.
14382 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14383 SelectionDAG &DAG) const {
14384 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14385 /*IsSigned=*/ false, /*IsReplace=*/ false);
14386 SDValue FIST = Vals.first, StackSlot = Vals.second;
14387 assert(FIST.getNode() && "Unexpected failure");
14389 if (StackSlot.getNode())
14390 // Load the result.
14391 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14392 FIST, StackSlot, MachinePointerInfo(),
14393 false, false, false, 0);
14395 // The node is the result.
14399 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14401 MVT VT = Op.getSimpleValueType();
14402 SDValue In = Op.getOperand(0);
14403 MVT SVT = In.getSimpleValueType();
14405 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14407 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14408 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14409 In, DAG.getUNDEF(SVT)));
14412 /// The only differences between FABS and FNEG are the mask and the logic op.
14413 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14414 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14415 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14416 "Wrong opcode for lowering FABS or FNEG.");
14418 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14420 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14421 // into an FNABS. We'll lower the FABS after that if it is still in use.
14423 for (SDNode *User : Op->uses())
14424 if (User->getOpcode() == ISD::FNEG)
14427 SDValue Op0 = Op.getOperand(0);
14428 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14431 MVT VT = Op.getSimpleValueType();
14432 // Assume scalar op for initialization; update for vector if needed.
14433 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14434 // generate a 16-byte vector constant and logic op even for the scalar case.
14435 // Using a 16-byte mask allows folding the load of the mask with
14436 // the logic op, so it can save (~4 bytes) on code size.
14438 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14439 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14440 // decide if we should generate a 16-byte constant mask when we only need 4 or
14441 // 8 bytes for the scalar case.
14442 if (VT.isVector()) {
14443 EltVT = VT.getVectorElementType();
14444 NumElts = VT.getVectorNumElements();
14447 unsigned EltBits = EltVT.getSizeInBits();
14448 LLVMContext *Context = DAG.getContext();
14449 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14451 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14452 Constant *C = ConstantInt::get(*Context, MaskElt);
14453 C = ConstantVector::getSplat(NumElts, C);
14454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14455 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14456 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14457 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14458 MachinePointerInfo::getConstantPool(),
14459 false, false, false, Alignment);
14461 if (VT.isVector()) {
14462 // For a vector, cast operands to a vector type, perform the logic op,
14463 // and cast the result back to the original value type.
14464 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14465 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14466 SDValue Operand = IsFNABS ?
14467 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14468 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14469 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14470 return DAG.getNode(ISD::BITCAST, dl, VT,
14471 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14474 // If not vector, then scalar.
14475 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14476 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14477 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14480 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14482 LLVMContext *Context = DAG.getContext();
14483 SDValue Op0 = Op.getOperand(0);
14484 SDValue Op1 = Op.getOperand(1);
14486 MVT VT = Op.getSimpleValueType();
14487 MVT SrcVT = Op1.getSimpleValueType();
14489 // If second operand is smaller, extend it first.
14490 if (SrcVT.bitsLT(VT)) {
14491 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14494 // And if it is bigger, shrink it first.
14495 if (SrcVT.bitsGT(VT)) {
14496 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14500 // At this point the operands and the result should have the same
14501 // type, and that won't be f80 since that is not custom lowered.
14503 const fltSemantics &Sem =
14504 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14505 const unsigned SizeInBits = VT.getSizeInBits();
14507 SmallVector<Constant *, 4> CV(
14508 VT == MVT::f64 ? 2 : 4,
14509 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14511 // First, clear all bits but the sign bit from the second operand (sign).
14512 CV[0] = ConstantFP::get(*Context,
14513 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14514 Constant *C = ConstantVector::get(CV);
14515 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14516 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14517 MachinePointerInfo::getConstantPool(),
14518 false, false, false, 16);
14519 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14521 // Next, clear the sign bit from the first operand (magnitude).
14522 CV[0] = ConstantFP::get(
14523 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14524 C = ConstantVector::get(CV);
14525 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14526 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14527 MachinePointerInfo::getConstantPool(),
14528 false, false, false, 16);
14529 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14531 // OR the magnitude value with the sign bit.
14532 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14535 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14536 SDValue N0 = Op.getOperand(0);
14538 MVT VT = Op.getSimpleValueType();
14540 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14541 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14542 DAG.getConstant(1, VT));
14543 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14546 // Check whether an OR'd tree is PTEST-able.
14547 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14548 SelectionDAG &DAG) {
14549 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14551 if (!Subtarget->hasSSE41())
14554 if (!Op->hasOneUse())
14557 SDNode *N = Op.getNode();
14560 SmallVector<SDValue, 8> Opnds;
14561 DenseMap<SDValue, unsigned> VecInMap;
14562 SmallVector<SDValue, 8> VecIns;
14563 EVT VT = MVT::Other;
14565 // Recognize a special case where a vector is casted into wide integer to
14567 Opnds.push_back(N->getOperand(0));
14568 Opnds.push_back(N->getOperand(1));
14570 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14571 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14572 // BFS traverse all OR'd operands.
14573 if (I->getOpcode() == ISD::OR) {
14574 Opnds.push_back(I->getOperand(0));
14575 Opnds.push_back(I->getOperand(1));
14576 // Re-evaluate the number of nodes to be traversed.
14577 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14581 // Quit if a non-EXTRACT_VECTOR_ELT
14582 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14585 // Quit if without a constant index.
14586 SDValue Idx = I->getOperand(1);
14587 if (!isa<ConstantSDNode>(Idx))
14590 SDValue ExtractedFromVec = I->getOperand(0);
14591 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14592 if (M == VecInMap.end()) {
14593 VT = ExtractedFromVec.getValueType();
14594 // Quit if not 128/256-bit vector.
14595 if (!VT.is128BitVector() && !VT.is256BitVector())
14597 // Quit if not the same type.
14598 if (VecInMap.begin() != VecInMap.end() &&
14599 VT != VecInMap.begin()->first.getValueType())
14601 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14602 VecIns.push_back(ExtractedFromVec);
14604 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14607 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14608 "Not extracted from 128-/256-bit vector.");
14610 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14612 for (DenseMap<SDValue, unsigned>::const_iterator
14613 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14614 // Quit if not all elements are used.
14615 if (I->second != FullMask)
14619 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14621 // Cast all vectors into TestVT for PTEST.
14622 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14623 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14625 // If more than one full vectors are evaluated, OR them first before PTEST.
14626 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14627 // Each iteration will OR 2 nodes and append the result until there is only
14628 // 1 node left, i.e. the final OR'd value of all vectors.
14629 SDValue LHS = VecIns[Slot];
14630 SDValue RHS = VecIns[Slot + 1];
14631 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14634 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14635 VecIns.back(), VecIns.back());
14638 /// \brief return true if \c Op has a use that doesn't just read flags.
14639 static bool hasNonFlagsUse(SDValue Op) {
14640 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14642 SDNode *User = *UI;
14643 unsigned UOpNo = UI.getOperandNo();
14644 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14645 // Look pass truncate.
14646 UOpNo = User->use_begin().getOperandNo();
14647 User = *User->use_begin();
14650 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14651 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14657 /// Emit nodes that will be selected as "test Op0,Op0", or something
14659 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14660 SelectionDAG &DAG) const {
14661 if (Op.getValueType() == MVT::i1)
14662 // KORTEST instruction should be selected
14663 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14664 DAG.getConstant(0, Op.getValueType()));
14666 // CF and OF aren't always set the way we want. Determine which
14667 // of these we need.
14668 bool NeedCF = false;
14669 bool NeedOF = false;
14672 case X86::COND_A: case X86::COND_AE:
14673 case X86::COND_B: case X86::COND_BE:
14676 case X86::COND_G: case X86::COND_GE:
14677 case X86::COND_L: case X86::COND_LE:
14678 case X86::COND_O: case X86::COND_NO: {
14679 // Check if we really need to set the
14680 // Overflow flag. If NoSignedWrap is present
14681 // that is not actually needed.
14682 switch (Op->getOpcode()) {
14687 const BinaryWithFlagsSDNode *BinNode =
14688 cast<BinaryWithFlagsSDNode>(Op.getNode());
14689 if (BinNode->hasNoSignedWrap())
14699 // See if we can use the EFLAGS value from the operand instead of
14700 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14701 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14702 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14703 // Emit a CMP with 0, which is the TEST pattern.
14704 //if (Op.getValueType() == MVT::i1)
14705 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14706 // DAG.getConstant(0, MVT::i1));
14707 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14708 DAG.getConstant(0, Op.getValueType()));
14710 unsigned Opcode = 0;
14711 unsigned NumOperands = 0;
14713 // Truncate operations may prevent the merge of the SETCC instruction
14714 // and the arithmetic instruction before it. Attempt to truncate the operands
14715 // of the arithmetic instruction and use a reduced bit-width instruction.
14716 bool NeedTruncation = false;
14717 SDValue ArithOp = Op;
14718 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14719 SDValue Arith = Op->getOperand(0);
14720 // Both the trunc and the arithmetic op need to have one user each.
14721 if (Arith->hasOneUse())
14722 switch (Arith.getOpcode()) {
14729 NeedTruncation = true;
14735 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14736 // which may be the result of a CAST. We use the variable 'Op', which is the
14737 // non-casted variable when we check for possible users.
14738 switch (ArithOp.getOpcode()) {
14740 // Due to an isel shortcoming, be conservative if this add is likely to be
14741 // selected as part of a load-modify-store instruction. When the root node
14742 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14743 // uses of other nodes in the match, such as the ADD in this case. This
14744 // leads to the ADD being left around and reselected, with the result being
14745 // two adds in the output. Alas, even if none our users are stores, that
14746 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14747 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14748 // climbing the DAG back to the root, and it doesn't seem to be worth the
14750 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14751 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14752 if (UI->getOpcode() != ISD::CopyToReg &&
14753 UI->getOpcode() != ISD::SETCC &&
14754 UI->getOpcode() != ISD::STORE)
14757 if (ConstantSDNode *C =
14758 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14759 // An add of one will be selected as an INC.
14760 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14761 Opcode = X86ISD::INC;
14766 // An add of negative one (subtract of one) will be selected as a DEC.
14767 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14768 Opcode = X86ISD::DEC;
14774 // Otherwise use a regular EFLAGS-setting add.
14775 Opcode = X86ISD::ADD;
14780 // If we have a constant logical shift that's only used in a comparison
14781 // against zero turn it into an equivalent AND. This allows turning it into
14782 // a TEST instruction later.
14783 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14784 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14785 EVT VT = Op.getValueType();
14786 unsigned BitWidth = VT.getSizeInBits();
14787 unsigned ShAmt = Op->getConstantOperandVal(1);
14788 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14790 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14791 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14792 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14793 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14795 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14796 DAG.getConstant(Mask, VT));
14797 DAG.ReplaceAllUsesWith(Op, New);
14803 // If the primary and result isn't used, don't bother using X86ISD::AND,
14804 // because a TEST instruction will be better.
14805 if (!hasNonFlagsUse(Op))
14811 // Due to the ISEL shortcoming noted above, be conservative if this op is
14812 // likely to be selected as part of a load-modify-store instruction.
14813 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14814 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14815 if (UI->getOpcode() == ISD::STORE)
14818 // Otherwise use a regular EFLAGS-setting instruction.
14819 switch (ArithOp.getOpcode()) {
14820 default: llvm_unreachable("unexpected operator!");
14821 case ISD::SUB: Opcode = X86ISD::SUB; break;
14822 case ISD::XOR: Opcode = X86ISD::XOR; break;
14823 case ISD::AND: Opcode = X86ISD::AND; break;
14825 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14826 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14827 if (EFLAGS.getNode())
14830 Opcode = X86ISD::OR;
14844 return SDValue(Op.getNode(), 1);
14850 // If we found that truncation is beneficial, perform the truncation and
14852 if (NeedTruncation) {
14853 EVT VT = Op.getValueType();
14854 SDValue WideVal = Op->getOperand(0);
14855 EVT WideVT = WideVal.getValueType();
14856 unsigned ConvertedOp = 0;
14857 // Use a target machine opcode to prevent further DAGCombine
14858 // optimizations that may separate the arithmetic operations
14859 // from the setcc node.
14860 switch (WideVal.getOpcode()) {
14862 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14863 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14864 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14865 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14866 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14871 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14872 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14873 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14874 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14880 // Emit a CMP with 0, which is the TEST pattern.
14881 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14882 DAG.getConstant(0, Op.getValueType()));
14884 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14885 SmallVector<SDValue, 4> Ops;
14886 for (unsigned i = 0; i != NumOperands; ++i)
14887 Ops.push_back(Op.getOperand(i));
14889 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14890 DAG.ReplaceAllUsesWith(Op, New);
14891 return SDValue(New.getNode(), 1);
14894 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14896 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14897 SDLoc dl, SelectionDAG &DAG) const {
14898 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14899 if (C->getAPIntValue() == 0)
14900 return EmitTest(Op0, X86CC, dl, DAG);
14902 if (Op0.getValueType() == MVT::i1)
14903 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14906 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14907 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14908 // Do the comparison at i32 if it's smaller, besides the Atom case.
14909 // This avoids subregister aliasing issues. Keep the smaller reference
14910 // if we're optimizing for size, however, as that'll allow better folding
14911 // of memory operations.
14912 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14913 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14914 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14915 !Subtarget->isAtom()) {
14916 unsigned ExtendOp =
14917 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14918 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14919 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14921 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14922 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14923 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14925 return SDValue(Sub.getNode(), 1);
14927 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14930 /// Convert a comparison if required by the subtarget.
14931 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14932 SelectionDAG &DAG) const {
14933 // If the subtarget does not support the FUCOMI instruction, floating-point
14934 // comparisons have to be converted.
14935 if (Subtarget->hasCMov() ||
14936 Cmp.getOpcode() != X86ISD::CMP ||
14937 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14938 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14941 // The instruction selector will select an FUCOM instruction instead of
14942 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14943 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14944 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14946 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14947 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14948 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14949 DAG.getConstant(8, MVT::i8));
14950 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14951 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14954 /// The minimum architected relative accuracy is 2^-12. We need one
14955 /// Newton-Raphson step to have a good float result (24 bits of precision).
14956 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14957 DAGCombinerInfo &DCI,
14958 unsigned &RefinementSteps,
14959 bool &UseOneConstNR) const {
14960 // FIXME: We should use instruction latency models to calculate the cost of
14961 // each potential sequence, but this is very hard to do reliably because
14962 // at least Intel's Core* chips have variable timing based on the number of
14963 // significant digits in the divisor and/or sqrt operand.
14964 if (!Subtarget->useSqrtEst())
14967 EVT VT = Op.getValueType();
14969 // SSE1 has rsqrtss and rsqrtps.
14970 // TODO: Add support for AVX512 (v16f32).
14971 // It is likely not profitable to do this for f64 because a double-precision
14972 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14973 // instructions: convert to single, rsqrtss, convert back to double, refine
14974 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14975 // along with FMA, this could be a throughput win.
14976 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14977 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14978 RefinementSteps = 1;
14979 UseOneConstNR = false;
14980 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14985 /// The minimum architected relative accuracy is 2^-12. We need one
14986 /// Newton-Raphson step to have a good float result (24 bits of precision).
14987 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14988 DAGCombinerInfo &DCI,
14989 unsigned &RefinementSteps) const {
14990 // FIXME: We should use instruction latency models to calculate the cost of
14991 // each potential sequence, but this is very hard to do reliably because
14992 // at least Intel's Core* chips have variable timing based on the number of
14993 // significant digits in the divisor.
14994 if (!Subtarget->useReciprocalEst())
14997 EVT VT = Op.getValueType();
14999 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15000 // TODO: Add support for AVX512 (v16f32).
15001 // It is likely not profitable to do this for f64 because a double-precision
15002 // reciprocal estimate with refinement on x86 prior to FMA requires
15003 // 15 instructions: convert to single, rcpss, convert back to double, refine
15004 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15005 // along with FMA, this could be a throughput win.
15006 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15007 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15008 RefinementSteps = ReciprocalEstimateRefinementSteps;
15009 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15014 static bool isAllOnes(SDValue V) {
15015 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15016 return C && C->isAllOnesValue();
15019 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15020 /// if it's possible.
15021 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15022 SDLoc dl, SelectionDAG &DAG) const {
15023 SDValue Op0 = And.getOperand(0);
15024 SDValue Op1 = And.getOperand(1);
15025 if (Op0.getOpcode() == ISD::TRUNCATE)
15026 Op0 = Op0.getOperand(0);
15027 if (Op1.getOpcode() == ISD::TRUNCATE)
15028 Op1 = Op1.getOperand(0);
15031 if (Op1.getOpcode() == ISD::SHL)
15032 std::swap(Op0, Op1);
15033 if (Op0.getOpcode() == ISD::SHL) {
15034 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15035 if (And00C->getZExtValue() == 1) {
15036 // If we looked past a truncate, check that it's only truncating away
15038 unsigned BitWidth = Op0.getValueSizeInBits();
15039 unsigned AndBitWidth = And.getValueSizeInBits();
15040 if (BitWidth > AndBitWidth) {
15042 DAG.computeKnownBits(Op0, Zeros, Ones);
15043 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15047 RHS = Op0.getOperand(1);
15049 } else if (Op1.getOpcode() == ISD::Constant) {
15050 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15051 uint64_t AndRHSVal = AndRHS->getZExtValue();
15052 SDValue AndLHS = Op0;
15054 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15055 LHS = AndLHS.getOperand(0);
15056 RHS = AndLHS.getOperand(1);
15059 // Use BT if the immediate can't be encoded in a TEST instruction.
15060 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15062 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15066 if (LHS.getNode()) {
15067 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15068 // instruction. Since the shift amount is in-range-or-undefined, we know
15069 // that doing a bittest on the i32 value is ok. We extend to i32 because
15070 // the encoding for the i16 version is larger than the i32 version.
15071 // Also promote i16 to i32 for performance / code size reason.
15072 if (LHS.getValueType() == MVT::i8 ||
15073 LHS.getValueType() == MVT::i16)
15074 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15076 // If the operand types disagree, extend the shift amount to match. Since
15077 // BT ignores high bits (like shifts) we can use anyextend.
15078 if (LHS.getValueType() != RHS.getValueType())
15079 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15081 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15082 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15083 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15084 DAG.getConstant(Cond, MVT::i8), BT);
15090 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15092 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15097 // SSE Condition code mapping:
15106 switch (SetCCOpcode) {
15107 default: llvm_unreachable("Unexpected SETCC condition");
15109 case ISD::SETEQ: SSECC = 0; break;
15111 case ISD::SETGT: Swap = true; // Fallthrough
15113 case ISD::SETOLT: SSECC = 1; break;
15115 case ISD::SETGE: Swap = true; // Fallthrough
15117 case ISD::SETOLE: SSECC = 2; break;
15118 case ISD::SETUO: SSECC = 3; break;
15120 case ISD::SETNE: SSECC = 4; break;
15121 case ISD::SETULE: Swap = true; // Fallthrough
15122 case ISD::SETUGE: SSECC = 5; break;
15123 case ISD::SETULT: Swap = true; // Fallthrough
15124 case ISD::SETUGT: SSECC = 6; break;
15125 case ISD::SETO: SSECC = 7; break;
15127 case ISD::SETONE: SSECC = 8; break;
15130 std::swap(Op0, Op1);
15135 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15136 // ones, and then concatenate the result back.
15137 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15138 MVT VT = Op.getSimpleValueType();
15140 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15141 "Unsupported value type for operation");
15143 unsigned NumElems = VT.getVectorNumElements();
15145 SDValue CC = Op.getOperand(2);
15147 // Extract the LHS vectors
15148 SDValue LHS = Op.getOperand(0);
15149 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15150 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15152 // Extract the RHS vectors
15153 SDValue RHS = Op.getOperand(1);
15154 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15155 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15157 // Issue the operation on the smaller types and concatenate the result back
15158 MVT EltVT = VT.getVectorElementType();
15159 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15160 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15161 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15162 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15165 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15166 const X86Subtarget *Subtarget) {
15167 SDValue Op0 = Op.getOperand(0);
15168 SDValue Op1 = Op.getOperand(1);
15169 SDValue CC = Op.getOperand(2);
15170 MVT VT = Op.getSimpleValueType();
15173 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15174 Op.getValueType().getScalarType() == MVT::i1 &&
15175 "Cannot set masked compare for this operation");
15177 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15179 bool Unsigned = false;
15182 switch (SetCCOpcode) {
15183 default: llvm_unreachable("Unexpected SETCC condition");
15184 case ISD::SETNE: SSECC = 4; break;
15185 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15186 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15187 case ISD::SETLT: Swap = true; //fall-through
15188 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15189 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15190 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15191 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15192 case ISD::SETULE: Unsigned = true; //fall-through
15193 case ISD::SETLE: SSECC = 2; break;
15197 std::swap(Op0, Op1);
15199 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15200 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15201 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15202 DAG.getConstant(SSECC, MVT::i8));
15205 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15206 /// operand \p Op1. If non-trivial (for example because it's not constant)
15207 /// return an empty value.
15208 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15210 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15214 MVT VT = Op1.getSimpleValueType();
15215 MVT EVT = VT.getVectorElementType();
15216 unsigned n = VT.getVectorNumElements();
15217 SmallVector<SDValue, 8> ULTOp1;
15219 for (unsigned i = 0; i < n; ++i) {
15220 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15221 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15224 // Avoid underflow.
15225 APInt Val = Elt->getAPIntValue();
15229 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15232 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15235 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15236 SelectionDAG &DAG) {
15237 SDValue Op0 = Op.getOperand(0);
15238 SDValue Op1 = Op.getOperand(1);
15239 SDValue CC = Op.getOperand(2);
15240 MVT VT = Op.getSimpleValueType();
15241 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15242 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15247 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15248 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15251 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15252 unsigned Opc = X86ISD::CMPP;
15253 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15254 assert(VT.getVectorNumElements() <= 16);
15255 Opc = X86ISD::CMPM;
15257 // In the two special cases we can't handle, emit two comparisons.
15260 unsigned CombineOpc;
15261 if (SetCCOpcode == ISD::SETUEQ) {
15262 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15264 assert(SetCCOpcode == ISD::SETONE);
15265 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15268 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15269 DAG.getConstant(CC0, MVT::i8));
15270 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15271 DAG.getConstant(CC1, MVT::i8));
15272 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15274 // Handle all other FP comparisons here.
15275 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15276 DAG.getConstant(SSECC, MVT::i8));
15279 // Break 256-bit integer vector compare into smaller ones.
15280 if (VT.is256BitVector() && !Subtarget->hasInt256())
15281 return Lower256IntVSETCC(Op, DAG);
15283 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15284 EVT OpVT = Op1.getValueType();
15285 if (Subtarget->hasAVX512()) {
15286 if (Op1.getValueType().is512BitVector() ||
15287 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15288 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15289 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15291 // In AVX-512 architecture setcc returns mask with i1 elements,
15292 // But there is no compare instruction for i8 and i16 elements in KNL.
15293 // We are not talking about 512-bit operands in this case, these
15294 // types are illegal.
15296 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15297 OpVT.getVectorElementType().getSizeInBits() >= 8))
15298 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15299 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15302 // We are handling one of the integer comparisons here. Since SSE only has
15303 // GT and EQ comparisons for integer, swapping operands and multiple
15304 // operations may be required for some comparisons.
15306 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15307 bool Subus = false;
15309 switch (SetCCOpcode) {
15310 default: llvm_unreachable("Unexpected SETCC condition");
15311 case ISD::SETNE: Invert = true;
15312 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15313 case ISD::SETLT: Swap = true;
15314 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15315 case ISD::SETGE: Swap = true;
15316 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15317 Invert = true; break;
15318 case ISD::SETULT: Swap = true;
15319 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15320 FlipSigns = true; break;
15321 case ISD::SETUGE: Swap = true;
15322 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15323 FlipSigns = true; Invert = true; break;
15326 // Special case: Use min/max operations for SETULE/SETUGE
15327 MVT VET = VT.getVectorElementType();
15329 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15330 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15333 switch (SetCCOpcode) {
15335 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15336 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15339 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15342 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15343 if (!MinMax && hasSubus) {
15344 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15346 // t = psubus Op0, Op1
15347 // pcmpeq t, <0..0>
15348 switch (SetCCOpcode) {
15350 case ISD::SETULT: {
15351 // If the comparison is against a constant we can turn this into a
15352 // setule. With psubus, setule does not require a swap. This is
15353 // beneficial because the constant in the register is no longer
15354 // destructed as the destination so it can be hoisted out of a loop.
15355 // Only do this pre-AVX since vpcmp* is no longer destructive.
15356 if (Subtarget->hasAVX())
15358 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15359 if (ULEOp1.getNode()) {
15361 Subus = true; Invert = false; Swap = false;
15365 // Psubus is better than flip-sign because it requires no inversion.
15366 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15367 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15371 Opc = X86ISD::SUBUS;
15377 std::swap(Op0, Op1);
15379 // Check that the operation in question is available (most are plain SSE2,
15380 // but PCMPGTQ and PCMPEQQ have different requirements).
15381 if (VT == MVT::v2i64) {
15382 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15383 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15385 // First cast everything to the right type.
15386 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15387 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15389 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15390 // bits of the inputs before performing those operations. The lower
15391 // compare is always unsigned.
15394 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15396 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15397 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15398 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15399 Sign, Zero, Sign, Zero);
15401 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15402 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15404 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15405 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15406 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15408 // Create masks for only the low parts/high parts of the 64 bit integers.
15409 static const int MaskHi[] = { 1, 1, 3, 3 };
15410 static const int MaskLo[] = { 0, 0, 2, 2 };
15411 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15412 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15413 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15415 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15416 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15419 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15421 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15424 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15425 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15426 // pcmpeqd + pshufd + pand.
15427 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15429 // First cast everything to the right type.
15430 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15431 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15434 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15436 // Make sure the lower and upper halves are both all-ones.
15437 static const int Mask[] = { 1, 0, 3, 2 };
15438 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15439 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15442 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15444 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15448 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15449 // bits of the inputs before performing those operations.
15451 EVT EltVT = VT.getVectorElementType();
15452 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15453 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15454 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15457 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15459 // If the logical-not of the result is required, perform that now.
15461 Result = DAG.getNOT(dl, Result, VT);
15464 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15467 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15468 getZeroVector(VT, Subtarget, DAG, dl));
15473 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15475 MVT VT = Op.getSimpleValueType();
15477 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15479 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15480 && "SetCC type must be 8-bit or 1-bit integer");
15481 SDValue Op0 = Op.getOperand(0);
15482 SDValue Op1 = Op.getOperand(1);
15484 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15486 // Optimize to BT if possible.
15487 // Lower (X & (1 << N)) == 0 to BT(X, N).
15488 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15489 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15490 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15491 Op1.getOpcode() == ISD::Constant &&
15492 cast<ConstantSDNode>(Op1)->isNullValue() &&
15493 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15494 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15495 if (NewSetCC.getNode()) {
15497 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15502 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15504 if (Op1.getOpcode() == ISD::Constant &&
15505 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15506 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15507 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15509 // If the input is a setcc, then reuse the input setcc or use a new one with
15510 // the inverted condition.
15511 if (Op0.getOpcode() == X86ISD::SETCC) {
15512 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15513 bool Invert = (CC == ISD::SETNE) ^
15514 cast<ConstantSDNode>(Op1)->isNullValue();
15518 CCode = X86::GetOppositeBranchCondition(CCode);
15519 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15520 DAG.getConstant(CCode, MVT::i8),
15521 Op0.getOperand(1));
15523 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15527 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15528 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15529 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15531 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15532 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15535 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15536 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15537 if (X86CC == X86::COND_INVALID)
15540 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15541 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15542 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15543 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15545 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15549 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15550 static bool isX86LogicalCmp(SDValue Op) {
15551 unsigned Opc = Op.getNode()->getOpcode();
15552 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15553 Opc == X86ISD::SAHF)
15555 if (Op.getResNo() == 1 &&
15556 (Opc == X86ISD::ADD ||
15557 Opc == X86ISD::SUB ||
15558 Opc == X86ISD::ADC ||
15559 Opc == X86ISD::SBB ||
15560 Opc == X86ISD::SMUL ||
15561 Opc == X86ISD::UMUL ||
15562 Opc == X86ISD::INC ||
15563 Opc == X86ISD::DEC ||
15564 Opc == X86ISD::OR ||
15565 Opc == X86ISD::XOR ||
15566 Opc == X86ISD::AND))
15569 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15575 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15576 if (V.getOpcode() != ISD::TRUNCATE)
15579 SDValue VOp0 = V.getOperand(0);
15580 unsigned InBits = VOp0.getValueSizeInBits();
15581 unsigned Bits = V.getValueSizeInBits();
15582 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15585 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15586 bool addTest = true;
15587 SDValue Cond = Op.getOperand(0);
15588 SDValue Op1 = Op.getOperand(1);
15589 SDValue Op2 = Op.getOperand(2);
15591 EVT VT = Op1.getValueType();
15594 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15595 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15596 // sequence later on.
15597 if (Cond.getOpcode() == ISD::SETCC &&
15598 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15599 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15600 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15601 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15602 int SSECC = translateX86FSETCC(
15603 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15606 if (Subtarget->hasAVX512()) {
15607 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15608 DAG.getConstant(SSECC, MVT::i8));
15609 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15611 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15612 DAG.getConstant(SSECC, MVT::i8));
15613 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15614 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15615 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15619 if (Cond.getOpcode() == ISD::SETCC) {
15620 SDValue NewCond = LowerSETCC(Cond, DAG);
15621 if (NewCond.getNode())
15625 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15626 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15627 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15628 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15629 if (Cond.getOpcode() == X86ISD::SETCC &&
15630 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15631 isZero(Cond.getOperand(1).getOperand(1))) {
15632 SDValue Cmp = Cond.getOperand(1);
15634 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15636 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15637 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15638 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15640 SDValue CmpOp0 = Cmp.getOperand(0);
15641 // Apply further optimizations for special cases
15642 // (select (x != 0), -1, 0) -> neg & sbb
15643 // (select (x == 0), 0, -1) -> neg & sbb
15644 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15645 if (YC->isNullValue() &&
15646 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15647 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15648 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15649 DAG.getConstant(0, CmpOp0.getValueType()),
15651 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15652 DAG.getConstant(X86::COND_B, MVT::i8),
15653 SDValue(Neg.getNode(), 1));
15657 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15658 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15659 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15661 SDValue Res = // Res = 0 or -1.
15662 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15663 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15665 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15666 Res = DAG.getNOT(DL, Res, Res.getValueType());
15668 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15669 if (!N2C || !N2C->isNullValue())
15670 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15675 // Look past (and (setcc_carry (cmp ...)), 1).
15676 if (Cond.getOpcode() == ISD::AND &&
15677 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15678 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15679 if (C && C->getAPIntValue() == 1)
15680 Cond = Cond.getOperand(0);
15683 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15684 // setting operand in place of the X86ISD::SETCC.
15685 unsigned CondOpcode = Cond.getOpcode();
15686 if (CondOpcode == X86ISD::SETCC ||
15687 CondOpcode == X86ISD::SETCC_CARRY) {
15688 CC = Cond.getOperand(0);
15690 SDValue Cmp = Cond.getOperand(1);
15691 unsigned Opc = Cmp.getOpcode();
15692 MVT VT = Op.getSimpleValueType();
15694 bool IllegalFPCMov = false;
15695 if (VT.isFloatingPoint() && !VT.isVector() &&
15696 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15697 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15699 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15700 Opc == X86ISD::BT) { // FIXME
15704 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15705 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15706 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15707 Cond.getOperand(0).getValueType() != MVT::i8)) {
15708 SDValue LHS = Cond.getOperand(0);
15709 SDValue RHS = Cond.getOperand(1);
15710 unsigned X86Opcode;
15713 switch (CondOpcode) {
15714 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15715 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15716 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15717 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15718 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15719 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15720 default: llvm_unreachable("unexpected overflowing operator");
15722 if (CondOpcode == ISD::UMULO)
15723 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15726 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15728 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15730 if (CondOpcode == ISD::UMULO)
15731 Cond = X86Op.getValue(2);
15733 Cond = X86Op.getValue(1);
15735 CC = DAG.getConstant(X86Cond, MVT::i8);
15740 // Look pass the truncate if the high bits are known zero.
15741 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15742 Cond = Cond.getOperand(0);
15744 // We know the result of AND is compared against zero. Try to match
15746 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15747 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15748 if (NewSetCC.getNode()) {
15749 CC = NewSetCC.getOperand(0);
15750 Cond = NewSetCC.getOperand(1);
15757 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15758 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15761 // a < b ? -1 : 0 -> RES = ~setcc_carry
15762 // a < b ? 0 : -1 -> RES = setcc_carry
15763 // a >= b ? -1 : 0 -> RES = setcc_carry
15764 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15765 if (Cond.getOpcode() == X86ISD::SUB) {
15766 Cond = ConvertCmpIfNecessary(Cond, DAG);
15767 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15769 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15770 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15771 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15772 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15773 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15774 return DAG.getNOT(DL, Res, Res.getValueType());
15779 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15780 // widen the cmov and push the truncate through. This avoids introducing a new
15781 // branch during isel and doesn't add any extensions.
15782 if (Op.getValueType() == MVT::i8 &&
15783 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15784 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15785 if (T1.getValueType() == T2.getValueType() &&
15786 // Blacklist CopyFromReg to avoid partial register stalls.
15787 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15788 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15789 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15790 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15794 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15795 // condition is true.
15796 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15797 SDValue Ops[] = { Op2, Op1, CC, Cond };
15798 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15801 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15802 SelectionDAG &DAG) {
15803 MVT VT = Op->getSimpleValueType(0);
15804 SDValue In = Op->getOperand(0);
15805 MVT InVT = In.getSimpleValueType();
15806 MVT VTElt = VT.getVectorElementType();
15807 MVT InVTElt = InVT.getVectorElementType();
15811 if ((InVTElt == MVT::i1) &&
15812 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15813 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15815 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15816 VTElt.getSizeInBits() <= 16)) ||
15818 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15819 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15821 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15822 VTElt.getSizeInBits() >= 32))))
15823 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15825 unsigned int NumElts = VT.getVectorNumElements();
15827 if (NumElts != 8 && NumElts != 16)
15830 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15831 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15832 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15833 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15837 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15839 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15840 Constant *C = ConstantInt::get(*DAG.getContext(),
15841 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15843 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15844 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15845 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15846 MachinePointerInfo::getConstantPool(),
15847 false, false, false, Alignment);
15848 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15849 if (VT.is512BitVector())
15851 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15854 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15855 SelectionDAG &DAG) {
15856 MVT VT = Op->getSimpleValueType(0);
15857 SDValue In = Op->getOperand(0);
15858 MVT InVT = In.getSimpleValueType();
15861 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15862 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15864 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15865 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15866 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15869 if (Subtarget->hasInt256())
15870 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15872 // Optimize vectors in AVX mode
15873 // Sign extend v8i16 to v8i32 and
15876 // Divide input vector into two parts
15877 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15878 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15879 // concat the vectors to original VT
15881 unsigned NumElems = InVT.getVectorNumElements();
15882 SDValue Undef = DAG.getUNDEF(InVT);
15884 SmallVector<int,8> ShufMask1(NumElems, -1);
15885 for (unsigned i = 0; i != NumElems/2; ++i)
15888 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15890 SmallVector<int,8> ShufMask2(NumElems, -1);
15891 for (unsigned i = 0; i != NumElems/2; ++i)
15892 ShufMask2[i] = i + NumElems/2;
15894 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15896 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15897 VT.getVectorNumElements()/2);
15899 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15900 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15905 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15906 // may emit an illegal shuffle but the expansion is still better than scalar
15907 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15908 // we'll emit a shuffle and a arithmetic shift.
15909 // TODO: It is possible to support ZExt by zeroing the undef values during
15910 // the shuffle phase or after the shuffle.
15911 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15912 SelectionDAG &DAG) {
15913 MVT RegVT = Op.getSimpleValueType();
15914 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15915 assert(RegVT.isInteger() &&
15916 "We only custom lower integer vector sext loads.");
15918 // Nothing useful we can do without SSE2 shuffles.
15919 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15921 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15923 EVT MemVT = Ld->getMemoryVT();
15924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15925 unsigned RegSz = RegVT.getSizeInBits();
15927 ISD::LoadExtType Ext = Ld->getExtensionType();
15929 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15930 && "Only anyext and sext are currently implemented.");
15931 assert(MemVT != RegVT && "Cannot extend to the same type");
15932 assert(MemVT.isVector() && "Must load a vector from memory");
15934 unsigned NumElems = RegVT.getVectorNumElements();
15935 unsigned MemSz = MemVT.getSizeInBits();
15936 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15938 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15939 // The only way in which we have a legal 256-bit vector result but not the
15940 // integer 256-bit operations needed to directly lower a sextload is if we
15941 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15942 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15943 // correctly legalized. We do this late to allow the canonical form of
15944 // sextload to persist throughout the rest of the DAG combiner -- it wants
15945 // to fold together any extensions it can, and so will fuse a sign_extend
15946 // of an sextload into a sextload targeting a wider value.
15948 if (MemSz == 128) {
15949 // Just switch this to a normal load.
15950 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15951 "it must be a legal 128-bit vector "
15953 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15954 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15955 Ld->isInvariant(), Ld->getAlignment());
15957 assert(MemSz < 128 &&
15958 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15959 // Do an sext load to a 128-bit vector type. We want to use the same
15960 // number of elements, but elements half as wide. This will end up being
15961 // recursively lowered by this routine, but will succeed as we definitely
15962 // have all the necessary features if we're using AVX1.
15964 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15965 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15967 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15968 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15969 Ld->isNonTemporal(), Ld->isInvariant(),
15970 Ld->getAlignment());
15973 // Replace chain users with the new chain.
15974 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15975 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15977 // Finally, do a normal sign-extend to the desired register.
15978 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15981 // All sizes must be a power of two.
15982 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15983 "Non-power-of-two elements are not custom lowered!");
15985 // Attempt to load the original value using scalar loads.
15986 // Find the largest scalar type that divides the total loaded size.
15987 MVT SclrLoadTy = MVT::i8;
15988 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15989 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15990 MVT Tp = (MVT::SimpleValueType)tp;
15991 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15996 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15997 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15999 SclrLoadTy = MVT::f64;
16001 // Calculate the number of scalar loads that we need to perform
16002 // in order to load our vector from memory.
16003 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16005 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16006 "Can only lower sext loads with a single scalar load!");
16008 unsigned loadRegZize = RegSz;
16009 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16012 // Represent our vector as a sequence of elements which are the
16013 // largest scalar that we can load.
16014 EVT LoadUnitVecVT = EVT::getVectorVT(
16015 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16017 // Represent the data using the same element type that is stored in
16018 // memory. In practice, we ''widen'' MemVT.
16020 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16021 loadRegZize / MemVT.getScalarType().getSizeInBits());
16023 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16024 "Invalid vector type");
16026 // We can't shuffle using an illegal type.
16027 assert(TLI.isTypeLegal(WideVecVT) &&
16028 "We only lower types that form legal widened vector types");
16030 SmallVector<SDValue, 8> Chains;
16031 SDValue Ptr = Ld->getBasePtr();
16032 SDValue Increment =
16033 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16034 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16036 for (unsigned i = 0; i < NumLoads; ++i) {
16037 // Perform a single load.
16038 SDValue ScalarLoad =
16039 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16040 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16041 Ld->getAlignment());
16042 Chains.push_back(ScalarLoad.getValue(1));
16043 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16044 // another round of DAGCombining.
16046 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16048 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16049 ScalarLoad, DAG.getIntPtrConstant(i));
16051 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16054 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16056 // Bitcast the loaded value to a vector of the original element type, in
16057 // the size of the target vector type.
16058 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16059 unsigned SizeRatio = RegSz / MemSz;
16061 if (Ext == ISD::SEXTLOAD) {
16062 // If we have SSE4.1, we can directly emit a VSEXT node.
16063 if (Subtarget->hasSSE41()) {
16064 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16065 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16069 // Otherwise we'll shuffle the small elements in the high bits of the
16070 // larger type and perform an arithmetic shift. If the shift is not legal
16071 // it's better to scalarize.
16072 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16073 "We can't implement a sext load without an arithmetic right shift!");
16075 // Redistribute the loaded elements into the different locations.
16076 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16077 for (unsigned i = 0; i != NumElems; ++i)
16078 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16080 SDValue Shuff = DAG.getVectorShuffle(
16081 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16083 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16085 // Build the arithmetic shift.
16086 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16087 MemVT.getVectorElementType().getSizeInBits();
16089 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16091 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16095 // Redistribute the loaded elements into the different locations.
16096 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16097 for (unsigned i = 0; i != NumElems; ++i)
16098 ShuffleVec[i * SizeRatio] = i;
16100 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16101 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16103 // Bitcast to the requested type.
16104 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16105 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16109 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16110 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16111 // from the AND / OR.
16112 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16113 Opc = Op.getOpcode();
16114 if (Opc != ISD::OR && Opc != ISD::AND)
16116 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16117 Op.getOperand(0).hasOneUse() &&
16118 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16119 Op.getOperand(1).hasOneUse());
16122 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16123 // 1 and that the SETCC node has a single use.
16124 static bool isXor1OfSetCC(SDValue Op) {
16125 if (Op.getOpcode() != ISD::XOR)
16127 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16128 if (N1C && N1C->getAPIntValue() == 1) {
16129 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16130 Op.getOperand(0).hasOneUse();
16135 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16136 bool addTest = true;
16137 SDValue Chain = Op.getOperand(0);
16138 SDValue Cond = Op.getOperand(1);
16139 SDValue Dest = Op.getOperand(2);
16142 bool Inverted = false;
16144 if (Cond.getOpcode() == ISD::SETCC) {
16145 // Check for setcc([su]{add,sub,mul}o == 0).
16146 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16147 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16148 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16149 Cond.getOperand(0).getResNo() == 1 &&
16150 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16151 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16152 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16153 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16154 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16155 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16157 Cond = Cond.getOperand(0);
16159 SDValue NewCond = LowerSETCC(Cond, DAG);
16160 if (NewCond.getNode())
16165 // FIXME: LowerXALUO doesn't handle these!!
16166 else if (Cond.getOpcode() == X86ISD::ADD ||
16167 Cond.getOpcode() == X86ISD::SUB ||
16168 Cond.getOpcode() == X86ISD::SMUL ||
16169 Cond.getOpcode() == X86ISD::UMUL)
16170 Cond = LowerXALUO(Cond, DAG);
16173 // Look pass (and (setcc_carry (cmp ...)), 1).
16174 if (Cond.getOpcode() == ISD::AND &&
16175 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16176 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16177 if (C && C->getAPIntValue() == 1)
16178 Cond = Cond.getOperand(0);
16181 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16182 // setting operand in place of the X86ISD::SETCC.
16183 unsigned CondOpcode = Cond.getOpcode();
16184 if (CondOpcode == X86ISD::SETCC ||
16185 CondOpcode == X86ISD::SETCC_CARRY) {
16186 CC = Cond.getOperand(0);
16188 SDValue Cmp = Cond.getOperand(1);
16189 unsigned Opc = Cmp.getOpcode();
16190 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16191 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16195 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16199 // These can only come from an arithmetic instruction with overflow,
16200 // e.g. SADDO, UADDO.
16201 Cond = Cond.getNode()->getOperand(1);
16207 CondOpcode = Cond.getOpcode();
16208 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16209 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16210 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16211 Cond.getOperand(0).getValueType() != MVT::i8)) {
16212 SDValue LHS = Cond.getOperand(0);
16213 SDValue RHS = Cond.getOperand(1);
16214 unsigned X86Opcode;
16217 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16218 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16220 switch (CondOpcode) {
16221 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16225 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16228 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16229 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16233 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16236 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16237 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16238 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16239 default: llvm_unreachable("unexpected overflowing operator");
16242 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16243 if (CondOpcode == ISD::UMULO)
16244 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16247 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16249 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16251 if (CondOpcode == ISD::UMULO)
16252 Cond = X86Op.getValue(2);
16254 Cond = X86Op.getValue(1);
16256 CC = DAG.getConstant(X86Cond, MVT::i8);
16260 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16261 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16262 if (CondOpc == ISD::OR) {
16263 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16264 // two branches instead of an explicit OR instruction with a
16266 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16267 isX86LogicalCmp(Cmp)) {
16268 CC = Cond.getOperand(0).getOperand(0);
16269 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16270 Chain, Dest, CC, Cmp);
16271 CC = Cond.getOperand(1).getOperand(0);
16275 } else { // ISD::AND
16276 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16277 // two branches instead of an explicit AND instruction with a
16278 // separate test. However, we only do this if this block doesn't
16279 // have a fall-through edge, because this requires an explicit
16280 // jmp when the condition is false.
16281 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16282 isX86LogicalCmp(Cmp) &&
16283 Op.getNode()->hasOneUse()) {
16284 X86::CondCode CCode =
16285 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16286 CCode = X86::GetOppositeBranchCondition(CCode);
16287 CC = DAG.getConstant(CCode, MVT::i8);
16288 SDNode *User = *Op.getNode()->use_begin();
16289 // Look for an unconditional branch following this conditional branch.
16290 // We need this because we need to reverse the successors in order
16291 // to implement FCMP_OEQ.
16292 if (User->getOpcode() == ISD::BR) {
16293 SDValue FalseBB = User->getOperand(1);
16295 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16296 assert(NewBR == User);
16300 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16301 Chain, Dest, CC, Cmp);
16302 X86::CondCode CCode =
16303 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16304 CCode = X86::GetOppositeBranchCondition(CCode);
16305 CC = DAG.getConstant(CCode, MVT::i8);
16311 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16312 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16313 // It should be transformed during dag combiner except when the condition
16314 // is set by a arithmetics with overflow node.
16315 X86::CondCode CCode =
16316 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16317 CCode = X86::GetOppositeBranchCondition(CCode);
16318 CC = DAG.getConstant(CCode, MVT::i8);
16319 Cond = Cond.getOperand(0).getOperand(1);
16321 } else if (Cond.getOpcode() == ISD::SETCC &&
16322 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16323 // For FCMP_OEQ, we can emit
16324 // two branches instead of an explicit AND instruction with a
16325 // separate test. However, we only do this if this block doesn't
16326 // have a fall-through edge, because this requires an explicit
16327 // jmp when the condition is false.
16328 if (Op.getNode()->hasOneUse()) {
16329 SDNode *User = *Op.getNode()->use_begin();
16330 // Look for an unconditional branch following this conditional branch.
16331 // We need this because we need to reverse the successors in order
16332 // to implement FCMP_OEQ.
16333 if (User->getOpcode() == ISD::BR) {
16334 SDValue FalseBB = User->getOperand(1);
16336 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16337 assert(NewBR == User);
16341 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16342 Cond.getOperand(0), Cond.getOperand(1));
16343 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16344 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16345 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16346 Chain, Dest, CC, Cmp);
16347 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16352 } else if (Cond.getOpcode() == ISD::SETCC &&
16353 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16354 // For FCMP_UNE, we can emit
16355 // two branches instead of an explicit AND instruction with a
16356 // separate test. However, we only do this if this block doesn't
16357 // have a fall-through edge, because this requires an explicit
16358 // jmp when the condition is false.
16359 if (Op.getNode()->hasOneUse()) {
16360 SDNode *User = *Op.getNode()->use_begin();
16361 // Look for an unconditional branch following this conditional branch.
16362 // We need this because we need to reverse the successors in order
16363 // to implement FCMP_UNE.
16364 if (User->getOpcode() == ISD::BR) {
16365 SDValue FalseBB = User->getOperand(1);
16367 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16368 assert(NewBR == User);
16371 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16372 Cond.getOperand(0), Cond.getOperand(1));
16373 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16374 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16375 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16376 Chain, Dest, CC, Cmp);
16377 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16387 // Look pass the truncate if the high bits are known zero.
16388 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16389 Cond = Cond.getOperand(0);
16391 // We know the result of AND is compared against zero. Try to match
16393 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16394 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16395 if (NewSetCC.getNode()) {
16396 CC = NewSetCC.getOperand(0);
16397 Cond = NewSetCC.getOperand(1);
16404 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16405 CC = DAG.getConstant(X86Cond, MVT::i8);
16406 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16408 Cond = ConvertCmpIfNecessary(Cond, DAG);
16409 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16410 Chain, Dest, CC, Cond);
16413 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16414 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16415 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16416 // that the guard pages used by the OS virtual memory manager are allocated in
16417 // correct sequence.
16419 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16420 SelectionDAG &DAG) const {
16421 MachineFunction &MF = DAG.getMachineFunction();
16422 bool SplitStack = MF.shouldSplitStack();
16423 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16429 SDNode* Node = Op.getNode();
16431 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16432 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16433 " not tell us which reg is the stack pointer!");
16434 EVT VT = Node->getValueType(0);
16435 SDValue Tmp1 = SDValue(Node, 0);
16436 SDValue Tmp2 = SDValue(Node, 1);
16437 SDValue Tmp3 = Node->getOperand(2);
16438 SDValue Chain = Tmp1.getOperand(0);
16440 // Chain the dynamic stack allocation so that it doesn't modify the stack
16441 // pointer when other instructions are using the stack.
16442 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16445 SDValue Size = Tmp2.getOperand(1);
16446 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16447 Chain = SP.getValue(1);
16448 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16449 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16450 unsigned StackAlign = TFI.getStackAlignment();
16451 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16452 if (Align > StackAlign)
16453 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16454 DAG.getConstant(-(uint64_t)Align, VT));
16455 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16457 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16458 DAG.getIntPtrConstant(0, true), SDValue(),
16461 SDValue Ops[2] = { Tmp1, Tmp2 };
16462 return DAG.getMergeValues(Ops, dl);
16466 SDValue Chain = Op.getOperand(0);
16467 SDValue Size = Op.getOperand(1);
16468 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16469 EVT VT = Op.getNode()->getValueType(0);
16471 bool Is64Bit = Subtarget->is64Bit();
16472 EVT SPTy = getPointerTy();
16475 MachineRegisterInfo &MRI = MF.getRegInfo();
16478 // The 64 bit implementation of segmented stacks needs to clobber both r10
16479 // r11. This makes it impossible to use it along with nested parameters.
16480 const Function *F = MF.getFunction();
16482 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16484 if (I->hasNestAttr())
16485 report_fatal_error("Cannot use segmented stacks with functions that "
16486 "have nested arguments.");
16489 const TargetRegisterClass *AddrRegClass =
16490 getRegClassFor(getPointerTy());
16491 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16492 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16493 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16494 DAG.getRegister(Vreg, SPTy));
16495 SDValue Ops1[2] = { Value, Chain };
16496 return DAG.getMergeValues(Ops1, dl);
16499 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16501 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16502 Flag = Chain.getValue(1);
16503 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16505 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16507 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16508 DAG.getSubtarget().getRegisterInfo());
16509 unsigned SPReg = RegInfo->getStackRegister();
16510 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16511 Chain = SP.getValue(1);
16514 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16515 DAG.getConstant(-(uint64_t)Align, VT));
16516 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16519 SDValue Ops1[2] = { SP, Chain };
16520 return DAG.getMergeValues(Ops1, dl);
16524 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16525 MachineFunction &MF = DAG.getMachineFunction();
16526 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16528 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16531 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16532 // vastart just stores the address of the VarArgsFrameIndex slot into the
16533 // memory location argument.
16534 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16536 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16537 MachinePointerInfo(SV), false, false, 0);
16541 // gp_offset (0 - 6 * 8)
16542 // fp_offset (48 - 48 + 8 * 16)
16543 // overflow_arg_area (point to parameters coming in memory).
16545 SmallVector<SDValue, 8> MemOps;
16546 SDValue FIN = Op.getOperand(1);
16548 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16549 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16551 FIN, MachinePointerInfo(SV), false, false, 0);
16552 MemOps.push_back(Store);
16555 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16556 FIN, DAG.getIntPtrConstant(4));
16557 Store = DAG.getStore(Op.getOperand(0), DL,
16558 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16560 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16561 MemOps.push_back(Store);
16563 // Store ptr to overflow_arg_area
16564 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16565 FIN, DAG.getIntPtrConstant(4));
16566 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16568 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16569 MachinePointerInfo(SV, 8),
16571 MemOps.push_back(Store);
16573 // Store ptr to reg_save_area.
16574 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16575 FIN, DAG.getIntPtrConstant(8));
16576 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16578 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16579 MachinePointerInfo(SV, 16), false, false, 0);
16580 MemOps.push_back(Store);
16581 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16584 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16585 assert(Subtarget->is64Bit() &&
16586 "LowerVAARG only handles 64-bit va_arg!");
16587 assert((Subtarget->isTargetLinux() ||
16588 Subtarget->isTargetDarwin()) &&
16589 "Unhandled target in LowerVAARG");
16590 assert(Op.getNode()->getNumOperands() == 4);
16591 SDValue Chain = Op.getOperand(0);
16592 SDValue SrcPtr = Op.getOperand(1);
16593 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16594 unsigned Align = Op.getConstantOperandVal(3);
16597 EVT ArgVT = Op.getNode()->getValueType(0);
16598 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16599 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16602 // Decide which area this value should be read from.
16603 // TODO: Implement the AMD64 ABI in its entirety. This simple
16604 // selection mechanism works only for the basic types.
16605 if (ArgVT == MVT::f80) {
16606 llvm_unreachable("va_arg for f80 not yet implemented");
16607 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16608 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16609 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16610 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16612 llvm_unreachable("Unhandled argument type in LowerVAARG");
16615 if (ArgMode == 2) {
16616 // Sanity Check: Make sure using fp_offset makes sense.
16617 assert(!DAG.getTarget().Options.UseSoftFloat &&
16618 !(DAG.getMachineFunction()
16619 .getFunction()->getAttributes()
16620 .hasAttribute(AttributeSet::FunctionIndex,
16621 Attribute::NoImplicitFloat)) &&
16622 Subtarget->hasSSE1());
16625 // Insert VAARG_64 node into the DAG
16626 // VAARG_64 returns two values: Variable Argument Address, Chain
16627 SmallVector<SDValue, 11> InstOps;
16628 InstOps.push_back(Chain);
16629 InstOps.push_back(SrcPtr);
16630 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16631 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16632 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16633 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16634 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16635 VTs, InstOps, MVT::i64,
16636 MachinePointerInfo(SV),
16638 /*Volatile=*/false,
16640 /*WriteMem=*/true);
16641 Chain = VAARG.getValue(1);
16643 // Load the next argument and return it
16644 return DAG.getLoad(ArgVT, dl,
16647 MachinePointerInfo(),
16648 false, false, false, 0);
16651 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16652 SelectionDAG &DAG) {
16653 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16654 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16655 SDValue Chain = Op.getOperand(0);
16656 SDValue DstPtr = Op.getOperand(1);
16657 SDValue SrcPtr = Op.getOperand(2);
16658 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16659 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16662 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16663 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16665 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16668 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16669 // amount is a constant. Takes immediate version of shift as input.
16670 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16671 SDValue SrcOp, uint64_t ShiftAmt,
16672 SelectionDAG &DAG) {
16673 MVT ElementType = VT.getVectorElementType();
16675 // Fold this packed shift into its first operand if ShiftAmt is 0.
16679 // Check for ShiftAmt >= element width
16680 if (ShiftAmt >= ElementType.getSizeInBits()) {
16681 if (Opc == X86ISD::VSRAI)
16682 ShiftAmt = ElementType.getSizeInBits() - 1;
16684 return DAG.getConstant(0, VT);
16687 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16688 && "Unknown target vector shift-by-constant node");
16690 // Fold this packed vector shift into a build vector if SrcOp is a
16691 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16692 if (VT == SrcOp.getSimpleValueType() &&
16693 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16694 SmallVector<SDValue, 8> Elts;
16695 unsigned NumElts = SrcOp->getNumOperands();
16696 ConstantSDNode *ND;
16699 default: llvm_unreachable(nullptr);
16700 case X86ISD::VSHLI:
16701 for (unsigned i=0; i!=NumElts; ++i) {
16702 SDValue CurrentOp = SrcOp->getOperand(i);
16703 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16704 Elts.push_back(CurrentOp);
16707 ND = cast<ConstantSDNode>(CurrentOp);
16708 const APInt &C = ND->getAPIntValue();
16709 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16712 case X86ISD::VSRLI:
16713 for (unsigned i=0; i!=NumElts; ++i) {
16714 SDValue CurrentOp = SrcOp->getOperand(i);
16715 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16716 Elts.push_back(CurrentOp);
16719 ND = cast<ConstantSDNode>(CurrentOp);
16720 const APInt &C = ND->getAPIntValue();
16721 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16724 case X86ISD::VSRAI:
16725 for (unsigned i=0; i!=NumElts; ++i) {
16726 SDValue CurrentOp = SrcOp->getOperand(i);
16727 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16728 Elts.push_back(CurrentOp);
16731 ND = cast<ConstantSDNode>(CurrentOp);
16732 const APInt &C = ND->getAPIntValue();
16733 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16738 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16741 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16744 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16745 // may or may not be a constant. Takes immediate version of shift as input.
16746 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16747 SDValue SrcOp, SDValue ShAmt,
16748 SelectionDAG &DAG) {
16749 MVT SVT = ShAmt.getSimpleValueType();
16750 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16752 // Catch shift-by-constant.
16753 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16754 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16755 CShAmt->getZExtValue(), DAG);
16757 // Change opcode to non-immediate version
16759 default: llvm_unreachable("Unknown target vector shift node");
16760 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16761 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16762 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16765 const X86Subtarget &Subtarget =
16766 DAG.getTarget().getSubtarget<X86Subtarget>();
16767 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16768 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16769 // Let the shuffle legalizer expand this shift amount node.
16770 SDValue Op0 = ShAmt.getOperand(0);
16771 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16772 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16774 // Need to build a vector containing shift amount.
16775 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16776 SmallVector<SDValue, 4> ShOps;
16777 ShOps.push_back(ShAmt);
16778 if (SVT == MVT::i32) {
16779 ShOps.push_back(DAG.getConstant(0, SVT));
16780 ShOps.push_back(DAG.getUNDEF(SVT));
16782 ShOps.push_back(DAG.getUNDEF(SVT));
16784 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16785 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16788 // The return type has to be a 128-bit type with the same element
16789 // type as the input type.
16790 MVT EltVT = VT.getVectorElementType();
16791 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16793 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16794 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16797 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16798 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16799 /// necessary casting for \p Mask when lowering masking intrinsics.
16800 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16801 SDValue PreservedSrc,
16802 const X86Subtarget *Subtarget,
16803 SelectionDAG &DAG) {
16804 EVT VT = Op.getValueType();
16805 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16806 MVT::i1, VT.getVectorNumElements());
16807 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16808 Mask.getValueType().getSizeInBits());
16811 assert(MaskVT.isSimple() && "invalid mask type");
16813 if (isAllOnes(Mask))
16816 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16817 // are extracted by EXTRACT_SUBVECTOR.
16818 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16819 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16820 DAG.getIntPtrConstant(0));
16822 switch (Op.getOpcode()) {
16824 case X86ISD::PCMPEQM:
16825 case X86ISD::PCMPGTM:
16827 case X86ISD::CMPMU:
16828 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16830 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16831 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16832 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16835 /// \brief Creates an SDNode for a predicated scalar operation.
16836 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16837 /// The mask is comming as MVT::i8 and it should be truncated
16838 /// to MVT::i1 while lowering masking intrinsics.
16839 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16840 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16841 /// a scalar instruction.
16842 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16843 SDValue PreservedSrc,
16844 const X86Subtarget *Subtarget,
16845 SelectionDAG &DAG) {
16846 if (isAllOnes(Mask))
16849 EVT VT = Op.getValueType();
16851 // The mask should be of type MVT::i1
16852 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16854 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16855 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16856 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16859 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16861 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16862 case Intrinsic::x86_fma_vfmadd_ps:
16863 case Intrinsic::x86_fma_vfmadd_pd:
16864 case Intrinsic::x86_fma_vfmadd_ps_256:
16865 case Intrinsic::x86_fma_vfmadd_pd_256:
16866 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16867 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16868 return X86ISD::FMADD;
16869 case Intrinsic::x86_fma_vfmsub_ps:
16870 case Intrinsic::x86_fma_vfmsub_pd:
16871 case Intrinsic::x86_fma_vfmsub_ps_256:
16872 case Intrinsic::x86_fma_vfmsub_pd_256:
16873 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16874 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16875 return X86ISD::FMSUB;
16876 case Intrinsic::x86_fma_vfnmadd_ps:
16877 case Intrinsic::x86_fma_vfnmadd_pd:
16878 case Intrinsic::x86_fma_vfnmadd_ps_256:
16879 case Intrinsic::x86_fma_vfnmadd_pd_256:
16880 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16881 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16882 return X86ISD::FNMADD;
16883 case Intrinsic::x86_fma_vfnmsub_ps:
16884 case Intrinsic::x86_fma_vfnmsub_pd:
16885 case Intrinsic::x86_fma_vfnmsub_ps_256:
16886 case Intrinsic::x86_fma_vfnmsub_pd_256:
16887 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16888 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16889 return X86ISD::FNMSUB;
16890 case Intrinsic::x86_fma_vfmaddsub_ps:
16891 case Intrinsic::x86_fma_vfmaddsub_pd:
16892 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16893 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16894 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16895 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16896 return X86ISD::FMADDSUB;
16897 case Intrinsic::x86_fma_vfmsubadd_ps:
16898 case Intrinsic::x86_fma_vfmsubadd_pd:
16899 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16900 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16901 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16902 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16903 return X86ISD::FMSUBADD;
16907 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16908 SelectionDAG &DAG) {
16910 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16911 EVT VT = Op.getValueType();
16912 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16914 switch(IntrData->Type) {
16915 case INTR_TYPE_1OP:
16916 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16917 case INTR_TYPE_2OP:
16918 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16920 case INTR_TYPE_3OP:
16921 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16922 Op.getOperand(2), Op.getOperand(3));
16923 case INTR_TYPE_1OP_MASK_RM: {
16924 SDValue Src = Op.getOperand(1);
16925 SDValue Src0 = Op.getOperand(2);
16926 SDValue Mask = Op.getOperand(3);
16927 SDValue RoundingMode = Op.getOperand(4);
16928 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16930 Mask, Src0, Subtarget, DAG);
16932 case INTR_TYPE_SCALAR_MASK_RM: {
16933 SDValue Src1 = Op.getOperand(1);
16934 SDValue Src2 = Op.getOperand(2);
16935 SDValue Src0 = Op.getOperand(3);
16936 SDValue Mask = Op.getOperand(4);
16937 SDValue RoundingMode = Op.getOperand(5);
16938 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16940 Mask, Src0, Subtarget, DAG);
16942 case INTR_TYPE_2OP_MASK: {
16943 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16945 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16948 case CMP_MASK_CC: {
16949 // Comparison intrinsics with masks.
16950 // Example of transformation:
16951 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16952 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16954 // (v8i1 (insert_subvector undef,
16955 // (v2i1 (and (PCMPEQM %a, %b),
16956 // (extract_subvector
16957 // (v8i1 (bitcast %mask)), 0))), 0))))
16958 EVT VT = Op.getOperand(1).getValueType();
16959 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16960 VT.getVectorNumElements());
16961 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16962 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16963 Mask.getValueType().getSizeInBits());
16965 if (IntrData->Type == CMP_MASK_CC) {
16966 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16967 Op.getOperand(2), Op.getOperand(3));
16969 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16970 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16973 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16974 DAG.getTargetConstant(0, MaskVT),
16976 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16977 DAG.getUNDEF(BitcastVT), CmpMask,
16978 DAG.getIntPtrConstant(0));
16979 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16981 case COMI: { // Comparison intrinsics
16982 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16983 SDValue LHS = Op.getOperand(1);
16984 SDValue RHS = Op.getOperand(2);
16985 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16986 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16987 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16988 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16989 DAG.getConstant(X86CC, MVT::i8), Cond);
16990 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16993 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16994 Op.getOperand(1), Op.getOperand(2), DAG);
16996 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16997 Op.getSimpleValueType(),
16999 Op.getOperand(2), DAG),
17000 Op.getOperand(4), Op.getOperand(3), Subtarget,
17002 case COMPRESS_EXPAND_IN_REG: {
17003 SDValue Mask = Op.getOperand(3);
17004 SDValue DataToCompress = Op.getOperand(1);
17005 SDValue PassThru = Op.getOperand(2);
17006 if (isAllOnes(Mask)) // return data as is
17007 return Op.getOperand(1);
17008 EVT VT = Op.getValueType();
17009 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17010 VT.getVectorNumElements());
17011 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17012 Mask.getValueType().getSizeInBits());
17014 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17015 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17016 DAG.getIntPtrConstant(0));
17018 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17022 SDValue Mask = Op.getOperand(3);
17023 EVT VT = Op.getValueType();
17024 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17025 VT.getVectorNumElements());
17026 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17027 Mask.getValueType().getSizeInBits());
17029 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17030 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17031 DAG.getIntPtrConstant(0));
17032 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17041 default: return SDValue(); // Don't custom lower most intrinsics.
17043 case Intrinsic::x86_avx512_mask_valign_q_512:
17044 case Intrinsic::x86_avx512_mask_valign_d_512:
17045 // Vector source operands are swapped.
17046 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17047 Op.getValueType(), Op.getOperand(2),
17050 Op.getOperand(5), Op.getOperand(4),
17053 // ptest and testp intrinsics. The intrinsic these come from are designed to
17054 // return an integer value, not just an instruction so lower it to the ptest
17055 // or testp pattern and a setcc for the result.
17056 case Intrinsic::x86_sse41_ptestz:
17057 case Intrinsic::x86_sse41_ptestc:
17058 case Intrinsic::x86_sse41_ptestnzc:
17059 case Intrinsic::x86_avx_ptestz_256:
17060 case Intrinsic::x86_avx_ptestc_256:
17061 case Intrinsic::x86_avx_ptestnzc_256:
17062 case Intrinsic::x86_avx_vtestz_ps:
17063 case Intrinsic::x86_avx_vtestc_ps:
17064 case Intrinsic::x86_avx_vtestnzc_ps:
17065 case Intrinsic::x86_avx_vtestz_pd:
17066 case Intrinsic::x86_avx_vtestc_pd:
17067 case Intrinsic::x86_avx_vtestnzc_pd:
17068 case Intrinsic::x86_avx_vtestz_ps_256:
17069 case Intrinsic::x86_avx_vtestc_ps_256:
17070 case Intrinsic::x86_avx_vtestnzc_ps_256:
17071 case Intrinsic::x86_avx_vtestz_pd_256:
17072 case Intrinsic::x86_avx_vtestc_pd_256:
17073 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17074 bool IsTestPacked = false;
17077 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17078 case Intrinsic::x86_avx_vtestz_ps:
17079 case Intrinsic::x86_avx_vtestz_pd:
17080 case Intrinsic::x86_avx_vtestz_ps_256:
17081 case Intrinsic::x86_avx_vtestz_pd_256:
17082 IsTestPacked = true; // Fallthrough
17083 case Intrinsic::x86_sse41_ptestz:
17084 case Intrinsic::x86_avx_ptestz_256:
17086 X86CC = X86::COND_E;
17088 case Intrinsic::x86_avx_vtestc_ps:
17089 case Intrinsic::x86_avx_vtestc_pd:
17090 case Intrinsic::x86_avx_vtestc_ps_256:
17091 case Intrinsic::x86_avx_vtestc_pd_256:
17092 IsTestPacked = true; // Fallthrough
17093 case Intrinsic::x86_sse41_ptestc:
17094 case Intrinsic::x86_avx_ptestc_256:
17096 X86CC = X86::COND_B;
17098 case Intrinsic::x86_avx_vtestnzc_ps:
17099 case Intrinsic::x86_avx_vtestnzc_pd:
17100 case Intrinsic::x86_avx_vtestnzc_ps_256:
17101 case Intrinsic::x86_avx_vtestnzc_pd_256:
17102 IsTestPacked = true; // Fallthrough
17103 case Intrinsic::x86_sse41_ptestnzc:
17104 case Intrinsic::x86_avx_ptestnzc_256:
17106 X86CC = X86::COND_A;
17110 SDValue LHS = Op.getOperand(1);
17111 SDValue RHS = Op.getOperand(2);
17112 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17113 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17114 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17115 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17116 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17118 case Intrinsic::x86_avx512_kortestz_w:
17119 case Intrinsic::x86_avx512_kortestc_w: {
17120 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17121 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17122 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17123 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17124 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17125 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17126 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17129 case Intrinsic::x86_sse42_pcmpistria128:
17130 case Intrinsic::x86_sse42_pcmpestria128:
17131 case Intrinsic::x86_sse42_pcmpistric128:
17132 case Intrinsic::x86_sse42_pcmpestric128:
17133 case Intrinsic::x86_sse42_pcmpistrio128:
17134 case Intrinsic::x86_sse42_pcmpestrio128:
17135 case Intrinsic::x86_sse42_pcmpistris128:
17136 case Intrinsic::x86_sse42_pcmpestris128:
17137 case Intrinsic::x86_sse42_pcmpistriz128:
17138 case Intrinsic::x86_sse42_pcmpestriz128: {
17142 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17143 case Intrinsic::x86_sse42_pcmpistria128:
17144 Opcode = X86ISD::PCMPISTRI;
17145 X86CC = X86::COND_A;
17147 case Intrinsic::x86_sse42_pcmpestria128:
17148 Opcode = X86ISD::PCMPESTRI;
17149 X86CC = X86::COND_A;
17151 case Intrinsic::x86_sse42_pcmpistric128:
17152 Opcode = X86ISD::PCMPISTRI;
17153 X86CC = X86::COND_B;
17155 case Intrinsic::x86_sse42_pcmpestric128:
17156 Opcode = X86ISD::PCMPESTRI;
17157 X86CC = X86::COND_B;
17159 case Intrinsic::x86_sse42_pcmpistrio128:
17160 Opcode = X86ISD::PCMPISTRI;
17161 X86CC = X86::COND_O;
17163 case Intrinsic::x86_sse42_pcmpestrio128:
17164 Opcode = X86ISD::PCMPESTRI;
17165 X86CC = X86::COND_O;
17167 case Intrinsic::x86_sse42_pcmpistris128:
17168 Opcode = X86ISD::PCMPISTRI;
17169 X86CC = X86::COND_S;
17171 case Intrinsic::x86_sse42_pcmpestris128:
17172 Opcode = X86ISD::PCMPESTRI;
17173 X86CC = X86::COND_S;
17175 case Intrinsic::x86_sse42_pcmpistriz128:
17176 Opcode = X86ISD::PCMPISTRI;
17177 X86CC = X86::COND_E;
17179 case Intrinsic::x86_sse42_pcmpestriz128:
17180 Opcode = X86ISD::PCMPESTRI;
17181 X86CC = X86::COND_E;
17184 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17185 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17186 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17187 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17188 DAG.getConstant(X86CC, MVT::i8),
17189 SDValue(PCMP.getNode(), 1));
17190 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17193 case Intrinsic::x86_sse42_pcmpistri128:
17194 case Intrinsic::x86_sse42_pcmpestri128: {
17196 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17197 Opcode = X86ISD::PCMPISTRI;
17199 Opcode = X86ISD::PCMPESTRI;
17201 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17202 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17203 return DAG.getNode(Opcode, dl, VTs, NewOps);
17206 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17207 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17208 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17209 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17210 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17211 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17212 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17213 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17214 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17215 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17216 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17217 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17218 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17219 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17220 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17221 dl, Op.getValueType(),
17225 Op.getOperand(4), Op.getOperand(1),
17231 case Intrinsic::x86_fma_vfmadd_ps:
17232 case Intrinsic::x86_fma_vfmadd_pd:
17233 case Intrinsic::x86_fma_vfmsub_ps:
17234 case Intrinsic::x86_fma_vfmsub_pd:
17235 case Intrinsic::x86_fma_vfnmadd_ps:
17236 case Intrinsic::x86_fma_vfnmadd_pd:
17237 case Intrinsic::x86_fma_vfnmsub_ps:
17238 case Intrinsic::x86_fma_vfnmsub_pd:
17239 case Intrinsic::x86_fma_vfmaddsub_ps:
17240 case Intrinsic::x86_fma_vfmaddsub_pd:
17241 case Intrinsic::x86_fma_vfmsubadd_ps:
17242 case Intrinsic::x86_fma_vfmsubadd_pd:
17243 case Intrinsic::x86_fma_vfmadd_ps_256:
17244 case Intrinsic::x86_fma_vfmadd_pd_256:
17245 case Intrinsic::x86_fma_vfmsub_ps_256:
17246 case Intrinsic::x86_fma_vfmsub_pd_256:
17247 case Intrinsic::x86_fma_vfnmadd_ps_256:
17248 case Intrinsic::x86_fma_vfnmadd_pd_256:
17249 case Intrinsic::x86_fma_vfnmsub_ps_256:
17250 case Intrinsic::x86_fma_vfnmsub_pd_256:
17251 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17252 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17253 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17254 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17255 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17256 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17260 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17261 SDValue Src, SDValue Mask, SDValue Base,
17262 SDValue Index, SDValue ScaleOp, SDValue Chain,
17263 const X86Subtarget * Subtarget) {
17265 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17266 assert(C && "Invalid scale type");
17267 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17268 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17269 Index.getSimpleValueType().getVectorNumElements());
17271 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17273 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17275 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17276 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17277 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17278 SDValue Segment = DAG.getRegister(0, MVT::i32);
17279 if (Src.getOpcode() == ISD::UNDEF)
17280 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17281 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17282 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17283 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17284 return DAG.getMergeValues(RetOps, dl);
17287 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17288 SDValue Src, SDValue Mask, SDValue Base,
17289 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17291 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17292 assert(C && "Invalid scale type");
17293 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17294 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17295 SDValue Segment = DAG.getRegister(0, MVT::i32);
17296 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17297 Index.getSimpleValueType().getVectorNumElements());
17299 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17301 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17303 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17304 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17305 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17306 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17307 return SDValue(Res, 1);
17310 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17311 SDValue Mask, SDValue Base, SDValue Index,
17312 SDValue ScaleOp, SDValue Chain) {
17314 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17315 assert(C && "Invalid scale type");
17316 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17317 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17318 SDValue Segment = DAG.getRegister(0, MVT::i32);
17320 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17322 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17324 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17326 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17327 //SDVTList VTs = DAG.getVTList(MVT::Other);
17328 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17329 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17330 return SDValue(Res, 0);
17333 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17334 // read performance monitor counters (x86_rdpmc).
17335 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17336 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17337 SmallVectorImpl<SDValue> &Results) {
17338 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17339 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17342 // The ECX register is used to select the index of the performance counter
17344 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17346 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17348 // Reads the content of a 64-bit performance counter and returns it in the
17349 // registers EDX:EAX.
17350 if (Subtarget->is64Bit()) {
17351 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17352 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17355 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17356 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17359 Chain = HI.getValue(1);
17361 if (Subtarget->is64Bit()) {
17362 // The EAX register is loaded with the low-order 32 bits. The EDX register
17363 // is loaded with the supported high-order bits of the counter.
17364 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17365 DAG.getConstant(32, MVT::i8));
17366 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17367 Results.push_back(Chain);
17371 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17372 SDValue Ops[] = { LO, HI };
17373 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17374 Results.push_back(Pair);
17375 Results.push_back(Chain);
17378 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17379 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17380 // also used to custom lower READCYCLECOUNTER nodes.
17381 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17382 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17383 SmallVectorImpl<SDValue> &Results) {
17384 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17385 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17388 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17389 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17390 // and the EAX register is loaded with the low-order 32 bits.
17391 if (Subtarget->is64Bit()) {
17392 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17393 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17396 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17397 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17400 SDValue Chain = HI.getValue(1);
17402 if (Opcode == X86ISD::RDTSCP_DAG) {
17403 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17405 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17406 // the ECX register. Add 'ecx' explicitly to the chain.
17407 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17409 // Explicitly store the content of ECX at the location passed in input
17410 // to the 'rdtscp' intrinsic.
17411 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17412 MachinePointerInfo(), false, false, 0);
17415 if (Subtarget->is64Bit()) {
17416 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17417 // the EAX register is loaded with the low-order 32 bits.
17418 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17419 DAG.getConstant(32, MVT::i8));
17420 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17421 Results.push_back(Chain);
17425 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17426 SDValue Ops[] = { LO, HI };
17427 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17428 Results.push_back(Pair);
17429 Results.push_back(Chain);
17432 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17433 SelectionDAG &DAG) {
17434 SmallVector<SDValue, 2> Results;
17436 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17438 return DAG.getMergeValues(Results, DL);
17442 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17443 SelectionDAG &DAG) {
17444 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17446 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17451 switch(IntrData->Type) {
17453 llvm_unreachable("Unknown Intrinsic Type");
17457 // Emit the node with the right value type.
17458 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17459 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17461 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17462 // Otherwise return the value from Rand, which is always 0, casted to i32.
17463 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17464 DAG.getConstant(1, Op->getValueType(1)),
17465 DAG.getConstant(X86::COND_B, MVT::i32),
17466 SDValue(Result.getNode(), 1) };
17467 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17468 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17471 // Return { result, isValid, chain }.
17472 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17473 SDValue(Result.getNode(), 2));
17476 //gather(v1, mask, index, base, scale);
17477 SDValue Chain = Op.getOperand(0);
17478 SDValue Src = Op.getOperand(2);
17479 SDValue Base = Op.getOperand(3);
17480 SDValue Index = Op.getOperand(4);
17481 SDValue Mask = Op.getOperand(5);
17482 SDValue Scale = Op.getOperand(6);
17483 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17487 //scatter(base, mask, index, v1, scale);
17488 SDValue Chain = Op.getOperand(0);
17489 SDValue Base = Op.getOperand(2);
17490 SDValue Mask = Op.getOperand(3);
17491 SDValue Index = Op.getOperand(4);
17492 SDValue Src = Op.getOperand(5);
17493 SDValue Scale = Op.getOperand(6);
17494 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17497 SDValue Hint = Op.getOperand(6);
17499 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17500 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17501 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17502 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17503 SDValue Chain = Op.getOperand(0);
17504 SDValue Mask = Op.getOperand(2);
17505 SDValue Index = Op.getOperand(3);
17506 SDValue Base = Op.getOperand(4);
17507 SDValue Scale = Op.getOperand(5);
17508 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17510 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17512 SmallVector<SDValue, 2> Results;
17513 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17514 return DAG.getMergeValues(Results, dl);
17516 // Read Performance Monitoring Counters.
17518 SmallVector<SDValue, 2> Results;
17519 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17520 return DAG.getMergeValues(Results, dl);
17522 // XTEST intrinsics.
17524 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17525 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17526 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17527 DAG.getConstant(X86::COND_NE, MVT::i8),
17529 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17530 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17531 Ret, SDValue(InTrans.getNode(), 1));
17535 SmallVector<SDValue, 2> Results;
17536 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17537 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17538 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17539 DAG.getConstant(-1, MVT::i8));
17540 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17541 Op.getOperand(4), GenCF.getValue(1));
17542 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17543 Op.getOperand(5), MachinePointerInfo(),
17545 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17546 DAG.getConstant(X86::COND_B, MVT::i8),
17548 Results.push_back(SetCC);
17549 Results.push_back(Store);
17550 return DAG.getMergeValues(Results, dl);
17552 case COMPRESS_TO_MEM: {
17554 SDValue Mask = Op.getOperand(4);
17555 SDValue DataToCompress = Op.getOperand(3);
17556 SDValue Addr = Op.getOperand(2);
17557 SDValue Chain = Op.getOperand(0);
17559 if (isAllOnes(Mask)) // return just a store
17560 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17561 MachinePointerInfo(), false, false, 0);
17563 EVT VT = DataToCompress.getValueType();
17564 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17565 VT.getVectorNumElements());
17566 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17567 Mask.getValueType().getSizeInBits());
17568 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17569 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17570 DAG.getIntPtrConstant(0));
17572 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17573 DataToCompress, DAG.getUNDEF(VT));
17574 return DAG.getStore(Chain, dl, Compressed, Addr,
17575 MachinePointerInfo(), false, false, 0);
17577 case EXPAND_FROM_MEM: {
17579 SDValue Mask = Op.getOperand(4);
17580 SDValue PathThru = Op.getOperand(3);
17581 SDValue Addr = Op.getOperand(2);
17582 SDValue Chain = Op.getOperand(0);
17583 EVT VT = Op.getValueType();
17585 if (isAllOnes(Mask)) // return just a load
17586 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17588 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17589 VT.getVectorNumElements());
17590 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17591 Mask.getValueType().getSizeInBits());
17592 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17593 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17594 DAG.getIntPtrConstant(0));
17596 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17597 false, false, false, 0);
17599 SmallVector<SDValue, 2> Results;
17600 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17602 Results.push_back(Chain);
17603 return DAG.getMergeValues(Results, dl);
17608 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17609 SelectionDAG &DAG) const {
17610 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17611 MFI->setReturnAddressIsTaken(true);
17613 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17616 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17618 EVT PtrVT = getPointerTy();
17621 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17622 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17623 DAG.getSubtarget().getRegisterInfo());
17624 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17625 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17626 DAG.getNode(ISD::ADD, dl, PtrVT,
17627 FrameAddr, Offset),
17628 MachinePointerInfo(), false, false, false, 0);
17631 // Just load the return address.
17632 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17633 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17634 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17637 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17638 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17639 MFI->setFrameAddressIsTaken(true);
17641 EVT VT = Op.getValueType();
17642 SDLoc dl(Op); // FIXME probably not meaningful
17643 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17644 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17645 DAG.getSubtarget().getRegisterInfo());
17646 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17647 DAG.getMachineFunction());
17648 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17649 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17650 "Invalid Frame Register!");
17651 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17653 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17654 MachinePointerInfo(),
17655 false, false, false, 0);
17659 // FIXME? Maybe this could be a TableGen attribute on some registers and
17660 // this table could be generated automatically from RegInfo.
17661 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17663 unsigned Reg = StringSwitch<unsigned>(RegName)
17664 .Case("esp", X86::ESP)
17665 .Case("rsp", X86::RSP)
17669 report_fatal_error("Invalid register name global variable");
17672 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17673 SelectionDAG &DAG) const {
17674 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17675 DAG.getSubtarget().getRegisterInfo());
17676 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17679 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17680 SDValue Chain = Op.getOperand(0);
17681 SDValue Offset = Op.getOperand(1);
17682 SDValue Handler = Op.getOperand(2);
17685 EVT PtrVT = getPointerTy();
17686 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17687 DAG.getSubtarget().getRegisterInfo());
17688 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17689 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17690 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17691 "Invalid Frame Register!");
17692 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17693 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17695 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17696 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17697 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17698 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17700 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17702 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17703 DAG.getRegister(StoreAddrReg, PtrVT));
17706 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17707 SelectionDAG &DAG) const {
17709 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17710 DAG.getVTList(MVT::i32, MVT::Other),
17711 Op.getOperand(0), Op.getOperand(1));
17714 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17715 SelectionDAG &DAG) const {
17717 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17718 Op.getOperand(0), Op.getOperand(1));
17721 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17722 return Op.getOperand(0);
17725 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17726 SelectionDAG &DAG) const {
17727 SDValue Root = Op.getOperand(0);
17728 SDValue Trmp = Op.getOperand(1); // trampoline
17729 SDValue FPtr = Op.getOperand(2); // nested function
17730 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17733 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17734 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17736 if (Subtarget->is64Bit()) {
17737 SDValue OutChains[6];
17739 // Large code-model.
17740 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17741 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17743 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17744 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17746 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17748 // Load the pointer to the nested function into R11.
17749 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17750 SDValue Addr = Trmp;
17751 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17752 Addr, MachinePointerInfo(TrmpAddr),
17755 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17756 DAG.getConstant(2, MVT::i64));
17757 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17758 MachinePointerInfo(TrmpAddr, 2),
17761 // Load the 'nest' parameter value into R10.
17762 // R10 is specified in X86CallingConv.td
17763 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17765 DAG.getConstant(10, MVT::i64));
17766 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17767 Addr, MachinePointerInfo(TrmpAddr, 10),
17770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17771 DAG.getConstant(12, MVT::i64));
17772 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17773 MachinePointerInfo(TrmpAddr, 12),
17776 // Jump to the nested function.
17777 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17779 DAG.getConstant(20, MVT::i64));
17780 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17781 Addr, MachinePointerInfo(TrmpAddr, 20),
17784 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17785 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17786 DAG.getConstant(22, MVT::i64));
17787 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17788 MachinePointerInfo(TrmpAddr, 22),
17791 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17793 const Function *Func =
17794 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17795 CallingConv::ID CC = Func->getCallingConv();
17800 llvm_unreachable("Unsupported calling convention");
17801 case CallingConv::C:
17802 case CallingConv::X86_StdCall: {
17803 // Pass 'nest' parameter in ECX.
17804 // Must be kept in sync with X86CallingConv.td
17805 NestReg = X86::ECX;
17807 // Check that ECX wasn't needed by an 'inreg' parameter.
17808 FunctionType *FTy = Func->getFunctionType();
17809 const AttributeSet &Attrs = Func->getAttributes();
17811 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17812 unsigned InRegCount = 0;
17815 for (FunctionType::param_iterator I = FTy->param_begin(),
17816 E = FTy->param_end(); I != E; ++I, ++Idx)
17817 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17818 // FIXME: should only count parameters that are lowered to integers.
17819 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17821 if (InRegCount > 2) {
17822 report_fatal_error("Nest register in use - reduce number of inreg"
17828 case CallingConv::X86_FastCall:
17829 case CallingConv::X86_ThisCall:
17830 case CallingConv::Fast:
17831 // Pass 'nest' parameter in EAX.
17832 // Must be kept in sync with X86CallingConv.td
17833 NestReg = X86::EAX;
17837 SDValue OutChains[4];
17838 SDValue Addr, Disp;
17840 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17841 DAG.getConstant(10, MVT::i32));
17842 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17844 // This is storing the opcode for MOV32ri.
17845 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17846 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17847 OutChains[0] = DAG.getStore(Root, dl,
17848 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17849 Trmp, MachinePointerInfo(TrmpAddr),
17852 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17853 DAG.getConstant(1, MVT::i32));
17854 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17855 MachinePointerInfo(TrmpAddr, 1),
17858 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17859 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17860 DAG.getConstant(5, MVT::i32));
17861 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17862 MachinePointerInfo(TrmpAddr, 5),
17865 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17866 DAG.getConstant(6, MVT::i32));
17867 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17868 MachinePointerInfo(TrmpAddr, 6),
17871 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17875 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17876 SelectionDAG &DAG) const {
17878 The rounding mode is in bits 11:10 of FPSR, and has the following
17880 00 Round to nearest
17885 FLT_ROUNDS, on the other hand, expects the following:
17892 To perform the conversion, we do:
17893 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17896 MachineFunction &MF = DAG.getMachineFunction();
17897 const TargetMachine &TM = MF.getTarget();
17898 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17899 unsigned StackAlignment = TFI.getStackAlignment();
17900 MVT VT = Op.getSimpleValueType();
17903 // Save FP Control Word to stack slot
17904 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17905 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17907 MachineMemOperand *MMO =
17908 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17909 MachineMemOperand::MOStore, 2, 2);
17911 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17912 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17913 DAG.getVTList(MVT::Other),
17914 Ops, MVT::i16, MMO);
17916 // Load FP Control Word from stack slot
17917 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17918 MachinePointerInfo(), false, false, false, 0);
17920 // Transform as necessary
17922 DAG.getNode(ISD::SRL, DL, MVT::i16,
17923 DAG.getNode(ISD::AND, DL, MVT::i16,
17924 CWD, DAG.getConstant(0x800, MVT::i16)),
17925 DAG.getConstant(11, MVT::i8));
17927 DAG.getNode(ISD::SRL, DL, MVT::i16,
17928 DAG.getNode(ISD::AND, DL, MVT::i16,
17929 CWD, DAG.getConstant(0x400, MVT::i16)),
17930 DAG.getConstant(9, MVT::i8));
17933 DAG.getNode(ISD::AND, DL, MVT::i16,
17934 DAG.getNode(ISD::ADD, DL, MVT::i16,
17935 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17936 DAG.getConstant(1, MVT::i16)),
17937 DAG.getConstant(3, MVT::i16));
17939 return DAG.getNode((VT.getSizeInBits() < 16 ?
17940 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17943 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17944 MVT VT = Op.getSimpleValueType();
17946 unsigned NumBits = VT.getSizeInBits();
17949 Op = Op.getOperand(0);
17950 if (VT == MVT::i8) {
17951 // Zero extend to i32 since there is not an i8 bsr.
17953 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17956 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17957 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17958 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17960 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17963 DAG.getConstant(NumBits+NumBits-1, OpVT),
17964 DAG.getConstant(X86::COND_E, MVT::i8),
17967 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17969 // Finally xor with NumBits-1.
17970 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17973 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17977 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17978 MVT VT = Op.getSimpleValueType();
17980 unsigned NumBits = VT.getSizeInBits();
17983 Op = Op.getOperand(0);
17984 if (VT == MVT::i8) {
17985 // Zero extend to i32 since there is not an i8 bsr.
17987 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17990 // Issue a bsr (scan bits in reverse).
17991 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17992 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17994 // And xor with NumBits-1.
17995 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17998 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18002 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18003 MVT VT = Op.getSimpleValueType();
18004 unsigned NumBits = VT.getSizeInBits();
18006 Op = Op.getOperand(0);
18008 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18009 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18010 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18012 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18015 DAG.getConstant(NumBits, VT),
18016 DAG.getConstant(X86::COND_E, MVT::i8),
18019 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18022 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18023 // ones, and then concatenate the result back.
18024 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18025 MVT VT = Op.getSimpleValueType();
18027 assert(VT.is256BitVector() && VT.isInteger() &&
18028 "Unsupported value type for operation");
18030 unsigned NumElems = VT.getVectorNumElements();
18033 // Extract the LHS vectors
18034 SDValue LHS = Op.getOperand(0);
18035 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18036 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18038 // Extract the RHS vectors
18039 SDValue RHS = Op.getOperand(1);
18040 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18041 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18043 MVT EltVT = VT.getVectorElementType();
18044 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18046 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18047 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18048 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18051 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18052 assert(Op.getSimpleValueType().is256BitVector() &&
18053 Op.getSimpleValueType().isInteger() &&
18054 "Only handle AVX 256-bit vector integer operation");
18055 return Lower256IntArith(Op, DAG);
18058 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18059 assert(Op.getSimpleValueType().is256BitVector() &&
18060 Op.getSimpleValueType().isInteger() &&
18061 "Only handle AVX 256-bit vector integer operation");
18062 return Lower256IntArith(Op, DAG);
18065 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18066 SelectionDAG &DAG) {
18068 MVT VT = Op.getSimpleValueType();
18070 // Decompose 256-bit ops into smaller 128-bit ops.
18071 if (VT.is256BitVector() && !Subtarget->hasInt256())
18072 return Lower256IntArith(Op, DAG);
18074 SDValue A = Op.getOperand(0);
18075 SDValue B = Op.getOperand(1);
18077 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18078 if (VT == MVT::v4i32) {
18079 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18080 "Should not custom lower when pmuldq is available!");
18082 // Extract the odd parts.
18083 static const int UnpackMask[] = { 1, -1, 3, -1 };
18084 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18085 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18087 // Multiply the even parts.
18088 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18089 // Now multiply odd parts.
18090 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18092 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18093 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18095 // Merge the two vectors back together with a shuffle. This expands into 2
18097 static const int ShufMask[] = { 0, 4, 2, 6 };
18098 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18101 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18102 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18104 // Ahi = psrlqi(a, 32);
18105 // Bhi = psrlqi(b, 32);
18107 // AloBlo = pmuludq(a, b);
18108 // AloBhi = pmuludq(a, Bhi);
18109 // AhiBlo = pmuludq(Ahi, b);
18111 // AloBhi = psllqi(AloBhi, 32);
18112 // AhiBlo = psllqi(AhiBlo, 32);
18113 // return AloBlo + AloBhi + AhiBlo;
18115 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18116 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18118 // Bit cast to 32-bit vectors for MULUDQ
18119 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18120 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18121 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18122 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18123 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18124 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18126 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18127 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18128 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18130 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18131 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18133 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18134 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18137 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18138 assert(Subtarget->isTargetWin64() && "Unexpected target");
18139 EVT VT = Op.getValueType();
18140 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18141 "Unexpected return type for lowering");
18145 switch (Op->getOpcode()) {
18146 default: llvm_unreachable("Unexpected request for libcall!");
18147 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18148 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18149 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18150 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18151 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18152 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18156 SDValue InChain = DAG.getEntryNode();
18158 TargetLowering::ArgListTy Args;
18159 TargetLowering::ArgListEntry Entry;
18160 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18161 EVT ArgVT = Op->getOperand(i).getValueType();
18162 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18163 "Unexpected argument type for lowering");
18164 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18165 Entry.Node = StackPtr;
18166 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18168 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18169 Entry.Ty = PointerType::get(ArgTy,0);
18170 Entry.isSExt = false;
18171 Entry.isZExt = false;
18172 Args.push_back(Entry);
18175 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18178 TargetLowering::CallLoweringInfo CLI(DAG);
18179 CLI.setDebugLoc(dl).setChain(InChain)
18180 .setCallee(getLibcallCallingConv(LC),
18181 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18182 Callee, std::move(Args), 0)
18183 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18185 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18186 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18189 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18190 SelectionDAG &DAG) {
18191 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18192 EVT VT = Op0.getValueType();
18195 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18196 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18198 // PMULxD operations multiply each even value (starting at 0) of LHS with
18199 // the related value of RHS and produce a widen result.
18200 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18201 // => <2 x i64> <ae|cg>
18203 // In other word, to have all the results, we need to perform two PMULxD:
18204 // 1. one with the even values.
18205 // 2. one with the odd values.
18206 // To achieve #2, with need to place the odd values at an even position.
18208 // Place the odd value at an even position (basically, shift all values 1
18209 // step to the left):
18210 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18211 // <a|b|c|d> => <b|undef|d|undef>
18212 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18213 // <e|f|g|h> => <f|undef|h|undef>
18214 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18216 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18218 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18219 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18221 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18222 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18223 // => <2 x i64> <ae|cg>
18224 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18225 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18226 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18227 // => <2 x i64> <bf|dh>
18228 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18229 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18231 // Shuffle it back into the right order.
18232 SDValue Highs, Lows;
18233 if (VT == MVT::v8i32) {
18234 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18235 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18236 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18237 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18239 const int HighMask[] = {1, 5, 3, 7};
18240 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18241 const int LowMask[] = {0, 4, 2, 6};
18242 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18245 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18246 // unsigned multiply.
18247 if (IsSigned && !Subtarget->hasSSE41()) {
18249 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18250 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18251 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18252 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18253 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18255 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18256 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18259 // The first result of MUL_LOHI is actually the low value, followed by the
18261 SDValue Ops[] = {Lows, Highs};
18262 return DAG.getMergeValues(Ops, dl);
18265 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18266 const X86Subtarget *Subtarget) {
18267 MVT VT = Op.getSimpleValueType();
18269 SDValue R = Op.getOperand(0);
18270 SDValue Amt = Op.getOperand(1);
18272 // Optimize shl/srl/sra with constant shift amount.
18273 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18274 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18275 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18277 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18278 (Subtarget->hasInt256() &&
18279 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18280 (Subtarget->hasAVX512() &&
18281 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18282 if (Op.getOpcode() == ISD::SHL)
18283 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18285 if (Op.getOpcode() == ISD::SRL)
18286 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18288 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18289 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18293 if (VT == MVT::v16i8) {
18294 if (Op.getOpcode() == ISD::SHL) {
18295 // Make a large shift.
18296 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18297 MVT::v8i16, R, ShiftAmt,
18299 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18300 // Zero out the rightmost bits.
18301 SmallVector<SDValue, 16> V(16,
18302 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18304 return DAG.getNode(ISD::AND, dl, VT, SHL,
18305 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18307 if (Op.getOpcode() == ISD::SRL) {
18308 // Make a large shift.
18309 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18310 MVT::v8i16, R, ShiftAmt,
18312 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18313 // Zero out the leftmost bits.
18314 SmallVector<SDValue, 16> V(16,
18315 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18317 return DAG.getNode(ISD::AND, dl, VT, SRL,
18318 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18320 if (Op.getOpcode() == ISD::SRA) {
18321 if (ShiftAmt == 7) {
18322 // R s>> 7 === R s< 0
18323 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18324 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18327 // R s>> a === ((R u>> a) ^ m) - m
18328 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18329 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18331 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18332 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18333 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18336 llvm_unreachable("Unknown shift opcode.");
18339 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18340 if (Op.getOpcode() == ISD::SHL) {
18341 // Make a large shift.
18342 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18343 MVT::v16i16, R, ShiftAmt,
18345 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18346 // Zero out the rightmost bits.
18347 SmallVector<SDValue, 32> V(32,
18348 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18350 return DAG.getNode(ISD::AND, dl, VT, SHL,
18351 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18353 if (Op.getOpcode() == ISD::SRL) {
18354 // Make a large shift.
18355 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18356 MVT::v16i16, R, ShiftAmt,
18358 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18359 // Zero out the leftmost bits.
18360 SmallVector<SDValue, 32> V(32,
18361 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18363 return DAG.getNode(ISD::AND, dl, VT, SRL,
18364 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18366 if (Op.getOpcode() == ISD::SRA) {
18367 if (ShiftAmt == 7) {
18368 // R s>> 7 === R s< 0
18369 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18370 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18373 // R s>> a === ((R u>> a) ^ m) - m
18374 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18375 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18377 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18378 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18379 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18382 llvm_unreachable("Unknown shift opcode.");
18387 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18388 if (!Subtarget->is64Bit() &&
18389 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18390 Amt.getOpcode() == ISD::BITCAST &&
18391 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18392 Amt = Amt.getOperand(0);
18393 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18394 VT.getVectorNumElements();
18395 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18396 uint64_t ShiftAmt = 0;
18397 for (unsigned i = 0; i != Ratio; ++i) {
18398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18402 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18404 // Check remaining shift amounts.
18405 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18406 uint64_t ShAmt = 0;
18407 for (unsigned j = 0; j != Ratio; ++j) {
18408 ConstantSDNode *C =
18409 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18413 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18415 if (ShAmt != ShiftAmt)
18418 switch (Op.getOpcode()) {
18420 llvm_unreachable("Unknown shift opcode!");
18422 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18425 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18428 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18436 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18437 const X86Subtarget* Subtarget) {
18438 MVT VT = Op.getSimpleValueType();
18440 SDValue R = Op.getOperand(0);
18441 SDValue Amt = Op.getOperand(1);
18443 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18444 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18445 (Subtarget->hasInt256() &&
18446 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18447 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18448 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18450 EVT EltVT = VT.getVectorElementType();
18452 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18453 // Check if this build_vector node is doing a splat.
18454 // If so, then set BaseShAmt equal to the splat value.
18455 BaseShAmt = BV->getSplatValue();
18456 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18457 BaseShAmt = SDValue();
18459 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18460 Amt = Amt.getOperand(0);
18462 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18463 if (SVN && SVN->isSplat()) {
18464 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18465 SDValue InVec = Amt.getOperand(0);
18466 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18467 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18468 "Unexpected shuffle index found!");
18469 BaseShAmt = InVec.getOperand(SplatIdx);
18470 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18471 if (ConstantSDNode *C =
18472 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18473 if (C->getZExtValue() == SplatIdx)
18474 BaseShAmt = InVec.getOperand(1);
18479 // Avoid introducing an extract element from a shuffle.
18480 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18481 DAG.getIntPtrConstant(SplatIdx));
18485 if (BaseShAmt.getNode()) {
18486 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18487 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18488 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18489 else if (EltVT.bitsLT(MVT::i32))
18490 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18492 switch (Op.getOpcode()) {
18494 llvm_unreachable("Unknown shift opcode!");
18496 switch (VT.SimpleTy) {
18497 default: return SDValue();
18506 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18509 switch (VT.SimpleTy) {
18510 default: return SDValue();
18517 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18520 switch (VT.SimpleTy) {
18521 default: return SDValue();
18530 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18536 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18537 if (!Subtarget->is64Bit() &&
18538 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18539 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18540 Amt.getOpcode() == ISD::BITCAST &&
18541 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18542 Amt = Amt.getOperand(0);
18543 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18544 VT.getVectorNumElements();
18545 std::vector<SDValue> Vals(Ratio);
18546 for (unsigned i = 0; i != Ratio; ++i)
18547 Vals[i] = Amt.getOperand(i);
18548 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18549 for (unsigned j = 0; j != Ratio; ++j)
18550 if (Vals[j] != Amt.getOperand(i + j))
18553 switch (Op.getOpcode()) {
18555 llvm_unreachable("Unknown shift opcode!");
18557 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18559 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18561 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18568 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18569 SelectionDAG &DAG) {
18570 MVT VT = Op.getSimpleValueType();
18572 SDValue R = Op.getOperand(0);
18573 SDValue Amt = Op.getOperand(1);
18576 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18577 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18579 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18583 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18587 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18589 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18590 if (Subtarget->hasInt256()) {
18591 if (Op.getOpcode() == ISD::SRL &&
18592 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18593 VT == MVT::v4i64 || VT == MVT::v8i32))
18595 if (Op.getOpcode() == ISD::SHL &&
18596 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18597 VT == MVT::v4i64 || VT == MVT::v8i32))
18599 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18603 // If possible, lower this packed shift into a vector multiply instead of
18604 // expanding it into a sequence of scalar shifts.
18605 // Do this only if the vector shift count is a constant build_vector.
18606 if (Op.getOpcode() == ISD::SHL &&
18607 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18608 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18609 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18610 SmallVector<SDValue, 8> Elts;
18611 EVT SVT = VT.getScalarType();
18612 unsigned SVTBits = SVT.getSizeInBits();
18613 const APInt &One = APInt(SVTBits, 1);
18614 unsigned NumElems = VT.getVectorNumElements();
18616 for (unsigned i=0; i !=NumElems; ++i) {
18617 SDValue Op = Amt->getOperand(i);
18618 if (Op->getOpcode() == ISD::UNDEF) {
18619 Elts.push_back(Op);
18623 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18624 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18625 uint64_t ShAmt = C.getZExtValue();
18626 if (ShAmt >= SVTBits) {
18627 Elts.push_back(DAG.getUNDEF(SVT));
18630 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18632 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18633 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18636 // Lower SHL with variable shift amount.
18637 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18638 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18640 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18641 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18642 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18643 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18646 // If possible, lower this shift as a sequence of two shifts by
18647 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18649 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18651 // Could be rewritten as:
18652 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18654 // The advantage is that the two shifts from the example would be
18655 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18656 // the vector shift into four scalar shifts plus four pairs of vector
18658 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18659 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18660 unsigned TargetOpcode = X86ISD::MOVSS;
18661 bool CanBeSimplified;
18662 // The splat value for the first packed shift (the 'X' from the example).
18663 SDValue Amt1 = Amt->getOperand(0);
18664 // The splat value for the second packed shift (the 'Y' from the example).
18665 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18666 Amt->getOperand(2);
18668 // See if it is possible to replace this node with a sequence of
18669 // two shifts followed by a MOVSS/MOVSD
18670 if (VT == MVT::v4i32) {
18671 // Check if it is legal to use a MOVSS.
18672 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18673 Amt2 == Amt->getOperand(3);
18674 if (!CanBeSimplified) {
18675 // Otherwise, check if we can still simplify this node using a MOVSD.
18676 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18677 Amt->getOperand(2) == Amt->getOperand(3);
18678 TargetOpcode = X86ISD::MOVSD;
18679 Amt2 = Amt->getOperand(2);
18682 // Do similar checks for the case where the machine value type
18684 CanBeSimplified = Amt1 == Amt->getOperand(1);
18685 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18686 CanBeSimplified = Amt2 == Amt->getOperand(i);
18688 if (!CanBeSimplified) {
18689 TargetOpcode = X86ISD::MOVSD;
18690 CanBeSimplified = true;
18691 Amt2 = Amt->getOperand(4);
18692 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18693 CanBeSimplified = Amt1 == Amt->getOperand(i);
18694 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18695 CanBeSimplified = Amt2 == Amt->getOperand(j);
18699 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18700 isa<ConstantSDNode>(Amt2)) {
18701 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18702 EVT CastVT = MVT::v4i32;
18704 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18705 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18707 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18708 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18709 if (TargetOpcode == X86ISD::MOVSD)
18710 CastVT = MVT::v2i64;
18711 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18712 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18713 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18715 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18719 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18720 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18723 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18724 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18726 // Turn 'a' into a mask suitable for VSELECT
18727 SDValue VSelM = DAG.getConstant(0x80, VT);
18728 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18729 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18731 SDValue CM1 = DAG.getConstant(0x0f, VT);
18732 SDValue CM2 = DAG.getConstant(0x3f, VT);
18734 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18735 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18736 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18737 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18738 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18741 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18742 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18743 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18745 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18746 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18747 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18748 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18749 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18752 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18753 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18754 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18756 // return VSELECT(r, r+r, a);
18757 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18758 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18762 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18763 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18764 // solution better.
18765 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18766 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18768 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18769 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18770 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18771 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18772 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18775 // Decompose 256-bit shifts into smaller 128-bit shifts.
18776 if (VT.is256BitVector()) {
18777 unsigned NumElems = VT.getVectorNumElements();
18778 MVT EltVT = VT.getVectorElementType();
18779 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18781 // Extract the two vectors
18782 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18783 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18785 // Recreate the shift amount vectors
18786 SDValue Amt1, Amt2;
18787 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18788 // Constant shift amount
18789 SmallVector<SDValue, 4> Amt1Csts;
18790 SmallVector<SDValue, 4> Amt2Csts;
18791 for (unsigned i = 0; i != NumElems/2; ++i)
18792 Amt1Csts.push_back(Amt->getOperand(i));
18793 for (unsigned i = NumElems/2; i != NumElems; ++i)
18794 Amt2Csts.push_back(Amt->getOperand(i));
18796 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18797 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18799 // Variable shift amount
18800 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18801 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18804 // Issue new vector shifts for the smaller types
18805 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18806 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18808 // Concatenate the result back
18809 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18815 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18816 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18817 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18818 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18819 // has only one use.
18820 SDNode *N = Op.getNode();
18821 SDValue LHS = N->getOperand(0);
18822 SDValue RHS = N->getOperand(1);
18823 unsigned BaseOp = 0;
18826 switch (Op.getOpcode()) {
18827 default: llvm_unreachable("Unknown ovf instruction!");
18829 // A subtract of one will be selected as a INC. Note that INC doesn't
18830 // set CF, so we can't do this for UADDO.
18831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18833 BaseOp = X86ISD::INC;
18834 Cond = X86::COND_O;
18837 BaseOp = X86ISD::ADD;
18838 Cond = X86::COND_O;
18841 BaseOp = X86ISD::ADD;
18842 Cond = X86::COND_B;
18845 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18846 // set CF, so we can't do this for USUBO.
18847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18849 BaseOp = X86ISD::DEC;
18850 Cond = X86::COND_O;
18853 BaseOp = X86ISD::SUB;
18854 Cond = X86::COND_O;
18857 BaseOp = X86ISD::SUB;
18858 Cond = X86::COND_B;
18861 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18862 Cond = X86::COND_O;
18864 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18865 if (N->getValueType(0) == MVT::i8) {
18866 BaseOp = X86ISD::UMUL8;
18867 Cond = X86::COND_O;
18870 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18872 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18875 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18876 DAG.getConstant(X86::COND_O, MVT::i32),
18877 SDValue(Sum.getNode(), 2));
18879 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18883 // Also sets EFLAGS.
18884 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18885 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18888 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18889 DAG.getConstant(Cond, MVT::i32),
18890 SDValue(Sum.getNode(), 1));
18892 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18895 // Sign extension of the low part of vector elements. This may be used either
18896 // when sign extend instructions are not available or if the vector element
18897 // sizes already match the sign-extended size. If the vector elements are in
18898 // their pre-extended size and sign extend instructions are available, that will
18899 // be handled by LowerSIGN_EXTEND.
18900 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18901 SelectionDAG &DAG) const {
18903 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18904 MVT VT = Op.getSimpleValueType();
18906 if (!Subtarget->hasSSE2() || !VT.isVector())
18909 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18910 ExtraVT.getScalarType().getSizeInBits();
18912 switch (VT.SimpleTy) {
18913 default: return SDValue();
18916 if (!Subtarget->hasFp256())
18918 if (!Subtarget->hasInt256()) {
18919 // needs to be split
18920 unsigned NumElems = VT.getVectorNumElements();
18922 // Extract the LHS vectors
18923 SDValue LHS = Op.getOperand(0);
18924 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18925 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18927 MVT EltVT = VT.getVectorElementType();
18928 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18930 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18931 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18932 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18934 SDValue Extra = DAG.getValueType(ExtraVT);
18936 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18937 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18939 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18944 SDValue Op0 = Op.getOperand(0);
18946 // This is a sign extension of some low part of vector elements without
18947 // changing the size of the vector elements themselves:
18948 // Shift-Left + Shift-Right-Algebraic.
18949 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18951 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18957 /// Returns true if the operand type is exactly twice the native width, and
18958 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18959 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18960 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18961 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18962 const X86Subtarget &Subtarget =
18963 getTargetMachine().getSubtarget<X86Subtarget>();
18964 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18967 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18968 else if (OpWidth == 128)
18969 return Subtarget.hasCmpxchg16b();
18974 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18975 return needsCmpXchgNb(SI->getValueOperand()->getType());
18978 // Note: this turns large loads into lock cmpxchg8b/16b.
18979 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18980 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18981 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18982 return needsCmpXchgNb(PTy->getElementType());
18985 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18986 const X86Subtarget &Subtarget =
18987 getTargetMachine().getSubtarget<X86Subtarget>();
18988 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18989 const Type *MemType = AI->getType();
18991 // If the operand is too big, we must see if cmpxchg8/16b is available
18992 // and default to library calls otherwise.
18993 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18994 return needsCmpXchgNb(MemType);
18996 AtomicRMWInst::BinOp Op = AI->getOperation();
18999 llvm_unreachable("Unknown atomic operation");
19000 case AtomicRMWInst::Xchg:
19001 case AtomicRMWInst::Add:
19002 case AtomicRMWInst::Sub:
19003 // It's better to use xadd, xsub or xchg for these in all cases.
19005 case AtomicRMWInst::Or:
19006 case AtomicRMWInst::And:
19007 case AtomicRMWInst::Xor:
19008 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19009 // prefix to a normal instruction for these operations.
19010 return !AI->use_empty();
19011 case AtomicRMWInst::Nand:
19012 case AtomicRMWInst::Max:
19013 case AtomicRMWInst::Min:
19014 case AtomicRMWInst::UMax:
19015 case AtomicRMWInst::UMin:
19016 // These always require a non-trivial set of data operations on x86. We must
19017 // use a cmpxchg loop.
19022 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19023 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19024 // no-sse2). There isn't any reason to disable it if the target processor
19026 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19030 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19031 const X86Subtarget &Subtarget =
19032 getTargetMachine().getSubtarget<X86Subtarget>();
19033 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19034 const Type *MemType = AI->getType();
19035 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19036 // there is no benefit in turning such RMWs into loads, and it is actually
19037 // harmful as it introduces a mfence.
19038 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19041 auto Builder = IRBuilder<>(AI);
19042 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19043 auto SynchScope = AI->getSynchScope();
19044 // We must restrict the ordering to avoid generating loads with Release or
19045 // ReleaseAcquire orderings.
19046 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19047 auto Ptr = AI->getPointerOperand();
19049 // Before the load we need a fence. Here is an example lifted from
19050 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19053 // x.store(1, relaxed);
19054 // r1 = y.fetch_add(0, release);
19056 // y.fetch_add(42, acquire);
19057 // r2 = x.load(relaxed);
19058 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19059 // lowered to just a load without a fence. A mfence flushes the store buffer,
19060 // making the optimization clearly correct.
19061 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19062 // otherwise, we might be able to be more agressive on relaxed idempotent
19063 // rmw. In practice, they do not look useful, so we don't try to be
19064 // especially clever.
19065 if (SynchScope == SingleThread) {
19066 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19067 // the IR level, so we must wrap it in an intrinsic.
19069 } else if (hasMFENCE(Subtarget)) {
19070 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19071 Intrinsic::x86_sse2_mfence);
19072 Builder.CreateCall(MFence);
19074 // FIXME: it might make sense to use a locked operation here but on a
19075 // different cache-line to prevent cache-line bouncing. In practice it
19076 // is probably a small win, and x86 processors without mfence are rare
19077 // enough that we do not bother.
19081 // Finally we can emit the atomic load.
19082 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19083 AI->getType()->getPrimitiveSizeInBits());
19084 Loaded->setAtomic(Order, SynchScope);
19085 AI->replaceAllUsesWith(Loaded);
19086 AI->eraseFromParent();
19090 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19091 SelectionDAG &DAG) {
19093 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19094 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19095 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19096 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19098 // The only fence that needs an instruction is a sequentially-consistent
19099 // cross-thread fence.
19100 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19101 if (hasMFENCE(*Subtarget))
19102 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19104 SDValue Chain = Op.getOperand(0);
19105 SDValue Zero = DAG.getConstant(0, MVT::i32);
19107 DAG.getRegister(X86::ESP, MVT::i32), // Base
19108 DAG.getTargetConstant(1, MVT::i8), // Scale
19109 DAG.getRegister(0, MVT::i32), // Index
19110 DAG.getTargetConstant(0, MVT::i32), // Disp
19111 DAG.getRegister(0, MVT::i32), // Segment.
19115 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19116 return SDValue(Res, 0);
19119 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19120 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19123 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19124 SelectionDAG &DAG) {
19125 MVT T = Op.getSimpleValueType();
19129 switch(T.SimpleTy) {
19130 default: llvm_unreachable("Invalid value type!");
19131 case MVT::i8: Reg = X86::AL; size = 1; break;
19132 case MVT::i16: Reg = X86::AX; size = 2; break;
19133 case MVT::i32: Reg = X86::EAX; size = 4; break;
19135 assert(Subtarget->is64Bit() && "Node not type legal!");
19136 Reg = X86::RAX; size = 8;
19139 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19140 Op.getOperand(2), SDValue());
19141 SDValue Ops[] = { cpIn.getValue(0),
19144 DAG.getTargetConstant(size, MVT::i8),
19145 cpIn.getValue(1) };
19146 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19147 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19148 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19152 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19153 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19154 MVT::i32, cpOut.getValue(2));
19155 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19156 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19158 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19159 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19160 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19164 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19165 SelectionDAG &DAG) {
19166 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19167 MVT DstVT = Op.getSimpleValueType();
19169 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19170 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19171 if (DstVT != MVT::f64)
19172 // This conversion needs to be expanded.
19175 SDValue InVec = Op->getOperand(0);
19177 unsigned NumElts = SrcVT.getVectorNumElements();
19178 EVT SVT = SrcVT.getVectorElementType();
19180 // Widen the vector in input in the case of MVT::v2i32.
19181 // Example: from MVT::v2i32 to MVT::v4i32.
19182 SmallVector<SDValue, 16> Elts;
19183 for (unsigned i = 0, e = NumElts; i != e; ++i)
19184 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19185 DAG.getIntPtrConstant(i)));
19187 // Explicitly mark the extra elements as Undef.
19188 SDValue Undef = DAG.getUNDEF(SVT);
19189 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19190 Elts.push_back(Undef);
19192 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19193 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19194 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19195 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19196 DAG.getIntPtrConstant(0));
19199 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19200 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19201 assert((DstVT == MVT::i64 ||
19202 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19203 "Unexpected custom BITCAST");
19204 // i64 <=> MMX conversions are Legal.
19205 if (SrcVT==MVT::i64 && DstVT.isVector())
19207 if (DstVT==MVT::i64 && SrcVT.isVector())
19209 // MMX <=> MMX conversions are Legal.
19210 if (SrcVT.isVector() && DstVT.isVector())
19212 // All other conversions need to be expanded.
19216 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19217 SelectionDAG &DAG) {
19218 SDNode *Node = Op.getNode();
19221 Op = Op.getOperand(0);
19222 EVT VT = Op.getValueType();
19223 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19224 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19226 unsigned NumElts = VT.getVectorNumElements();
19227 EVT EltVT = VT.getVectorElementType();
19228 unsigned Len = EltVT.getSizeInBits();
19230 // This is the vectorized version of the "best" algorithm from
19231 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19232 // with a minor tweak to use a series of adds + shifts instead of vector
19233 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19235 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19236 // v8i32 => Always profitable
19238 // FIXME: There a couple of possible improvements:
19240 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19241 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19243 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19244 "CTPOP not implemented for this vector element type.");
19246 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19247 // extra legalization.
19248 bool NeedsBitcast = EltVT == MVT::i32;
19249 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19251 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19252 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19253 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19255 // v = v - ((v >> 1) & 0x55555555...)
19256 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19257 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19258 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19260 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19262 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19263 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19265 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19267 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19268 if (VT != And.getValueType())
19269 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19270 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19272 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19273 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19274 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19275 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19276 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19278 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19279 if (NeedsBitcast) {
19280 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19281 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19282 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19285 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19286 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19287 if (VT != AndRHS.getValueType()) {
19288 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19289 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19291 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19293 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19294 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19295 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19296 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19297 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19299 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19300 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19301 if (NeedsBitcast) {
19302 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19303 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19305 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19306 if (VT != And.getValueType())
19307 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19309 // The algorithm mentioned above uses:
19310 // v = (v * 0x01010101...) >> (Len - 8)
19312 // Change it to use vector adds + vector shifts which yield faster results on
19313 // Haswell than using vector integer multiplication.
19315 // For i32 elements:
19316 // v = v + (v >> 8)
19317 // v = v + (v >> 16)
19319 // For i64 elements:
19320 // v = v + (v >> 8)
19321 // v = v + (v >> 16)
19322 // v = v + (v >> 32)
19325 SmallVector<SDValue, 8> Csts;
19326 for (unsigned i = 8; i <= Len/2; i *= 2) {
19327 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19328 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19329 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19330 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19334 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19335 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19336 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19337 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19338 if (NeedsBitcast) {
19339 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19340 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19342 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19343 if (VT != And.getValueType())
19344 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19349 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19350 SDNode *Node = Op.getNode();
19352 EVT T = Node->getValueType(0);
19353 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19354 DAG.getConstant(0, T), Node->getOperand(2));
19355 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19356 cast<AtomicSDNode>(Node)->getMemoryVT(),
19357 Node->getOperand(0),
19358 Node->getOperand(1), negOp,
19359 cast<AtomicSDNode>(Node)->getMemOperand(),
19360 cast<AtomicSDNode>(Node)->getOrdering(),
19361 cast<AtomicSDNode>(Node)->getSynchScope());
19364 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19365 SDNode *Node = Op.getNode();
19367 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19369 // Convert seq_cst store -> xchg
19370 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19371 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19372 // (The only way to get a 16-byte store is cmpxchg16b)
19373 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19374 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19375 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19376 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19377 cast<AtomicSDNode>(Node)->getMemoryVT(),
19378 Node->getOperand(0),
19379 Node->getOperand(1), Node->getOperand(2),
19380 cast<AtomicSDNode>(Node)->getMemOperand(),
19381 cast<AtomicSDNode>(Node)->getOrdering(),
19382 cast<AtomicSDNode>(Node)->getSynchScope());
19383 return Swap.getValue(1);
19385 // Other atomic stores have a simple pattern.
19389 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19390 EVT VT = Op.getNode()->getSimpleValueType(0);
19392 // Let legalize expand this if it isn't a legal type yet.
19393 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19396 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19399 bool ExtraOp = false;
19400 switch (Op.getOpcode()) {
19401 default: llvm_unreachable("Invalid code");
19402 case ISD::ADDC: Opc = X86ISD::ADD; break;
19403 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19404 case ISD::SUBC: Opc = X86ISD::SUB; break;
19405 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19409 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19411 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19412 Op.getOperand(1), Op.getOperand(2));
19415 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19416 SelectionDAG &DAG) {
19417 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19419 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19420 // which returns the values as { float, float } (in XMM0) or
19421 // { double, double } (which is returned in XMM0, XMM1).
19423 SDValue Arg = Op.getOperand(0);
19424 EVT ArgVT = Arg.getValueType();
19425 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19427 TargetLowering::ArgListTy Args;
19428 TargetLowering::ArgListEntry Entry;
19432 Entry.isSExt = false;
19433 Entry.isZExt = false;
19434 Args.push_back(Entry);
19436 bool isF64 = ArgVT == MVT::f64;
19437 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19438 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19439 // the results are returned via SRet in memory.
19440 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19441 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19442 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19444 Type *RetTy = isF64
19445 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19446 : (Type*)VectorType::get(ArgTy, 4);
19448 TargetLowering::CallLoweringInfo CLI(DAG);
19449 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19450 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19452 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19455 // Returned in xmm0 and xmm1.
19456 return CallResult.first;
19458 // Returned in bits 0:31 and 32:64 xmm0.
19459 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19460 CallResult.first, DAG.getIntPtrConstant(0));
19461 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19462 CallResult.first, DAG.getIntPtrConstant(1));
19463 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19464 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19467 /// LowerOperation - Provide custom lowering hooks for some operations.
19469 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19470 switch (Op.getOpcode()) {
19471 default: llvm_unreachable("Should not custom lower this!");
19472 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19473 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19474 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19475 return LowerCMP_SWAP(Op, Subtarget, DAG);
19476 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19477 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19478 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19479 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19480 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19481 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19482 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19483 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19484 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19485 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19486 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19487 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19488 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19489 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19490 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19491 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19492 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19493 case ISD::SHL_PARTS:
19494 case ISD::SRA_PARTS:
19495 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19496 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19497 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19498 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19499 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19500 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19501 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19502 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19503 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19504 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19505 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19507 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19508 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19509 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19510 case ISD::SETCC: return LowerSETCC(Op, DAG);
19511 case ISD::SELECT: return LowerSELECT(Op, DAG);
19512 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19513 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19514 case ISD::VASTART: return LowerVASTART(Op, DAG);
19515 case ISD::VAARG: return LowerVAARG(Op, DAG);
19516 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19517 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19518 case ISD::INTRINSIC_VOID:
19519 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19520 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19521 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19522 case ISD::FRAME_TO_ARGS_OFFSET:
19523 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19524 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19525 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19526 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19527 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19528 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19529 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19530 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19531 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19532 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19533 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19534 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19535 case ISD::UMUL_LOHI:
19536 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19539 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19545 case ISD::UMULO: return LowerXALUO(Op, DAG);
19546 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19547 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19551 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19552 case ISD::ADD: return LowerADD(Op, DAG);
19553 case ISD::SUB: return LowerSUB(Op, DAG);
19554 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19558 /// ReplaceNodeResults - Replace a node with an illegal result type
19559 /// with a new node built out of custom code.
19560 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19561 SmallVectorImpl<SDValue>&Results,
19562 SelectionDAG &DAG) const {
19564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19565 switch (N->getOpcode()) {
19567 llvm_unreachable("Do not know how to custom type legalize this operation!");
19568 case ISD::SIGN_EXTEND_INREG:
19573 // We don't want to expand or promote these.
19580 case ISD::UDIVREM: {
19581 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19582 Results.push_back(V);
19585 case ISD::FP_TO_SINT:
19586 case ISD::FP_TO_UINT: {
19587 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19589 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19592 std::pair<SDValue,SDValue> Vals =
19593 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19594 SDValue FIST = Vals.first, StackSlot = Vals.second;
19595 if (FIST.getNode()) {
19596 EVT VT = N->getValueType(0);
19597 // Return a load from the stack slot.
19598 if (StackSlot.getNode())
19599 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19600 MachinePointerInfo(),
19601 false, false, false, 0));
19603 Results.push_back(FIST);
19607 case ISD::UINT_TO_FP: {
19608 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19609 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19610 N->getValueType(0) != MVT::v2f32)
19612 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19614 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19616 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19617 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19618 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19619 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19620 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19621 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19624 case ISD::FP_ROUND: {
19625 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19627 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19628 Results.push_back(V);
19631 case ISD::INTRINSIC_W_CHAIN: {
19632 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19634 default : llvm_unreachable("Do not know how to custom type "
19635 "legalize this intrinsic operation!");
19636 case Intrinsic::x86_rdtsc:
19637 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19639 case Intrinsic::x86_rdtscp:
19640 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19642 case Intrinsic::x86_rdpmc:
19643 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19646 case ISD::READCYCLECOUNTER: {
19647 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19650 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19651 EVT T = N->getValueType(0);
19652 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19653 bool Regs64bit = T == MVT::i128;
19654 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19655 SDValue cpInL, cpInH;
19656 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19657 DAG.getConstant(0, HalfT));
19658 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19659 DAG.getConstant(1, HalfT));
19660 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19661 Regs64bit ? X86::RAX : X86::EAX,
19663 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19664 Regs64bit ? X86::RDX : X86::EDX,
19665 cpInH, cpInL.getValue(1));
19666 SDValue swapInL, swapInH;
19667 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19668 DAG.getConstant(0, HalfT));
19669 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19670 DAG.getConstant(1, HalfT));
19671 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19672 Regs64bit ? X86::RBX : X86::EBX,
19673 swapInL, cpInH.getValue(1));
19674 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19675 Regs64bit ? X86::RCX : X86::ECX,
19676 swapInH, swapInL.getValue(1));
19677 SDValue Ops[] = { swapInH.getValue(0),
19679 swapInH.getValue(1) };
19680 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19681 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19682 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19683 X86ISD::LCMPXCHG8_DAG;
19684 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19685 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19686 Regs64bit ? X86::RAX : X86::EAX,
19687 HalfT, Result.getValue(1));
19688 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19689 Regs64bit ? X86::RDX : X86::EDX,
19690 HalfT, cpOutL.getValue(2));
19691 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19693 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19694 MVT::i32, cpOutH.getValue(2));
19696 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19697 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19698 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19700 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19701 Results.push_back(Success);
19702 Results.push_back(EFLAGS.getValue(1));
19705 case ISD::ATOMIC_SWAP:
19706 case ISD::ATOMIC_LOAD_ADD:
19707 case ISD::ATOMIC_LOAD_SUB:
19708 case ISD::ATOMIC_LOAD_AND:
19709 case ISD::ATOMIC_LOAD_OR:
19710 case ISD::ATOMIC_LOAD_XOR:
19711 case ISD::ATOMIC_LOAD_NAND:
19712 case ISD::ATOMIC_LOAD_MIN:
19713 case ISD::ATOMIC_LOAD_MAX:
19714 case ISD::ATOMIC_LOAD_UMIN:
19715 case ISD::ATOMIC_LOAD_UMAX:
19716 case ISD::ATOMIC_LOAD: {
19717 // Delegate to generic TypeLegalization. Situations we can really handle
19718 // should have already been dealt with by AtomicExpandPass.cpp.
19721 case ISD::BITCAST: {
19722 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19723 EVT DstVT = N->getValueType(0);
19724 EVT SrcVT = N->getOperand(0)->getValueType(0);
19726 if (SrcVT != MVT::f64 ||
19727 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19730 unsigned NumElts = DstVT.getVectorNumElements();
19731 EVT SVT = DstVT.getVectorElementType();
19732 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19733 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19734 MVT::v2f64, N->getOperand(0));
19735 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19737 if (ExperimentalVectorWideningLegalization) {
19738 // If we are legalizing vectors by widening, we already have the desired
19739 // legal vector type, just return it.
19740 Results.push_back(ToVecInt);
19744 SmallVector<SDValue, 8> Elts;
19745 for (unsigned i = 0, e = NumElts; i != e; ++i)
19746 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19747 ToVecInt, DAG.getIntPtrConstant(i)));
19749 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19754 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19756 default: return nullptr;
19757 case X86ISD::BSF: return "X86ISD::BSF";
19758 case X86ISD::BSR: return "X86ISD::BSR";
19759 case X86ISD::SHLD: return "X86ISD::SHLD";
19760 case X86ISD::SHRD: return "X86ISD::SHRD";
19761 case X86ISD::FAND: return "X86ISD::FAND";
19762 case X86ISD::FANDN: return "X86ISD::FANDN";
19763 case X86ISD::FOR: return "X86ISD::FOR";
19764 case X86ISD::FXOR: return "X86ISD::FXOR";
19765 case X86ISD::FSRL: return "X86ISD::FSRL";
19766 case X86ISD::FILD: return "X86ISD::FILD";
19767 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19768 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19769 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19770 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19771 case X86ISD::FLD: return "X86ISD::FLD";
19772 case X86ISD::FST: return "X86ISD::FST";
19773 case X86ISD::CALL: return "X86ISD::CALL";
19774 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19775 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19776 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19777 case X86ISD::BT: return "X86ISD::BT";
19778 case X86ISD::CMP: return "X86ISD::CMP";
19779 case X86ISD::COMI: return "X86ISD::COMI";
19780 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19781 case X86ISD::CMPM: return "X86ISD::CMPM";
19782 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19783 case X86ISD::SETCC: return "X86ISD::SETCC";
19784 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19785 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19786 case X86ISD::CMOV: return "X86ISD::CMOV";
19787 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19788 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19789 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19790 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19791 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19792 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19793 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19794 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19795 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19796 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19797 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19798 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19799 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19800 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19801 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19802 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19803 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19804 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19805 case X86ISD::HADD: return "X86ISD::HADD";
19806 case X86ISD::HSUB: return "X86ISD::HSUB";
19807 case X86ISD::FHADD: return "X86ISD::FHADD";
19808 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19809 case X86ISD::UMAX: return "X86ISD::UMAX";
19810 case X86ISD::UMIN: return "X86ISD::UMIN";
19811 case X86ISD::SMAX: return "X86ISD::SMAX";
19812 case X86ISD::SMIN: return "X86ISD::SMIN";
19813 case X86ISD::FMAX: return "X86ISD::FMAX";
19814 case X86ISD::FMIN: return "X86ISD::FMIN";
19815 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19816 case X86ISD::FMINC: return "X86ISD::FMINC";
19817 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19818 case X86ISD::FRCP: return "X86ISD::FRCP";
19819 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19820 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19821 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19822 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19823 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19824 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19825 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19826 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19827 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19828 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19829 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19830 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19831 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19832 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19833 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19834 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19835 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19836 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19837 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19838 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19839 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19840 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19841 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19842 case X86ISD::VSHL: return "X86ISD::VSHL";
19843 case X86ISD::VSRL: return "X86ISD::VSRL";
19844 case X86ISD::VSRA: return "X86ISD::VSRA";
19845 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19846 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19847 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19848 case X86ISD::CMPP: return "X86ISD::CMPP";
19849 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19850 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19851 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19852 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19853 case X86ISD::ADD: return "X86ISD::ADD";
19854 case X86ISD::SUB: return "X86ISD::SUB";
19855 case X86ISD::ADC: return "X86ISD::ADC";
19856 case X86ISD::SBB: return "X86ISD::SBB";
19857 case X86ISD::SMUL: return "X86ISD::SMUL";
19858 case X86ISD::UMUL: return "X86ISD::UMUL";
19859 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19860 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19861 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19862 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19863 case X86ISD::INC: return "X86ISD::INC";
19864 case X86ISD::DEC: return "X86ISD::DEC";
19865 case X86ISD::OR: return "X86ISD::OR";
19866 case X86ISD::XOR: return "X86ISD::XOR";
19867 case X86ISD::AND: return "X86ISD::AND";
19868 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19869 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19870 case X86ISD::PTEST: return "X86ISD::PTEST";
19871 case X86ISD::TESTP: return "X86ISD::TESTP";
19872 case X86ISD::TESTM: return "X86ISD::TESTM";
19873 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19874 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19875 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19876 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19877 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19878 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19879 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19880 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19881 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19882 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19883 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19884 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19885 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19886 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19887 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19888 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19889 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19890 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19891 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19892 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19893 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19894 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19895 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19896 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19897 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19898 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19899 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19900 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19901 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19902 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19903 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19904 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19905 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19906 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19907 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19908 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19909 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19910 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19911 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19912 case X86ISD::SAHF: return "X86ISD::SAHF";
19913 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19914 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19915 case X86ISD::FMADD: return "X86ISD::FMADD";
19916 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19917 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19918 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19919 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19920 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19921 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19922 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19923 case X86ISD::XTEST: return "X86ISD::XTEST";
19924 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19925 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19929 // isLegalAddressingMode - Return true if the addressing mode represented
19930 // by AM is legal for this target, for a load/store of the specified type.
19931 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19933 // X86 supports extremely general addressing modes.
19934 CodeModel::Model M = getTargetMachine().getCodeModel();
19935 Reloc::Model R = getTargetMachine().getRelocationModel();
19937 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19938 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19943 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19945 // If a reference to this global requires an extra load, we can't fold it.
19946 if (isGlobalStubReference(GVFlags))
19949 // If BaseGV requires a register for the PIC base, we cannot also have a
19950 // BaseReg specified.
19951 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19954 // If lower 4G is not available, then we must use rip-relative addressing.
19955 if ((M != CodeModel::Small || R != Reloc::Static) &&
19956 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19960 switch (AM.Scale) {
19966 // These scales always work.
19971 // These scales are formed with basereg+scalereg. Only accept if there is
19976 default: // Other stuff never works.
19983 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19984 unsigned Bits = Ty->getScalarSizeInBits();
19986 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19987 // particularly cheaper than those without.
19991 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19992 // variable shifts just as cheap as scalar ones.
19993 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19996 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19997 // fully general vector.
20001 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20002 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20004 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20005 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20006 return NumBits1 > NumBits2;
20009 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20010 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20013 if (!isTypeLegal(EVT::getEVT(Ty1)))
20016 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20018 // Assuming the caller doesn't have a zeroext or signext return parameter,
20019 // truncation all the way down to i1 is valid.
20023 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20024 return isInt<32>(Imm);
20027 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20028 // Can also use sub to handle negated immediates.
20029 return isInt<32>(Imm);
20032 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20033 if (!VT1.isInteger() || !VT2.isInteger())
20035 unsigned NumBits1 = VT1.getSizeInBits();
20036 unsigned NumBits2 = VT2.getSizeInBits();
20037 return NumBits1 > NumBits2;
20040 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20041 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20042 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20045 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20046 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20047 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20050 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20051 EVT VT1 = Val.getValueType();
20052 if (isZExtFree(VT1, VT2))
20055 if (Val.getOpcode() != ISD::LOAD)
20058 if (!VT1.isSimple() || !VT1.isInteger() ||
20059 !VT2.isSimple() || !VT2.isInteger())
20062 switch (VT1.getSimpleVT().SimpleTy) {
20067 // X86 has 8, 16, and 32-bit zero-extending loads.
20075 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20076 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20079 VT = VT.getScalarType();
20081 if (!VT.isSimple())
20084 switch (VT.getSimpleVT().SimpleTy) {
20095 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20096 // i16 instructions are longer (0x66 prefix) and potentially slower.
20097 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20100 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20101 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20102 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20103 /// are assumed to be legal.
20105 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20107 if (!VT.isSimple())
20110 MVT SVT = VT.getSimpleVT();
20112 // Very little shuffling can be done for 64-bit vectors right now.
20113 if (VT.getSizeInBits() == 64)
20116 // If this is a single-input shuffle with no 128 bit lane crossings we can
20117 // lower it into pshufb.
20118 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20119 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20120 bool isLegal = true;
20121 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20122 if (M[I] >= (int)SVT.getVectorNumElements() ||
20123 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20132 // FIXME: blends, shifts.
20133 return (SVT.getVectorNumElements() == 2 ||
20134 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20135 isMOVLMask(M, SVT) ||
20136 isCommutedMOVLMask(M, SVT) ||
20137 isMOVHLPSMask(M, SVT) ||
20138 isSHUFPMask(M, SVT) ||
20139 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20140 isPSHUFDMask(M, SVT) ||
20141 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20142 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20143 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20144 isPALIGNRMask(M, SVT, Subtarget) ||
20145 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20146 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20147 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20148 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20149 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20150 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20154 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20156 if (!VT.isSimple())
20159 MVT SVT = VT.getSimpleVT();
20160 unsigned NumElts = SVT.getVectorNumElements();
20161 // FIXME: This collection of masks seems suspect.
20164 if (NumElts == 4 && SVT.is128BitVector()) {
20165 return (isMOVLMask(Mask, SVT) ||
20166 isCommutedMOVLMask(Mask, SVT, true) ||
20167 isSHUFPMask(Mask, SVT) ||
20168 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20169 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20170 Subtarget->hasInt256()));
20175 //===----------------------------------------------------------------------===//
20176 // X86 Scheduler Hooks
20177 //===----------------------------------------------------------------------===//
20179 /// Utility function to emit xbegin specifying the start of an RTM region.
20180 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20181 const TargetInstrInfo *TII) {
20182 DebugLoc DL = MI->getDebugLoc();
20184 const BasicBlock *BB = MBB->getBasicBlock();
20185 MachineFunction::iterator I = MBB;
20188 // For the v = xbegin(), we generate
20199 MachineBasicBlock *thisMBB = MBB;
20200 MachineFunction *MF = MBB->getParent();
20201 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20202 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20203 MF->insert(I, mainMBB);
20204 MF->insert(I, sinkMBB);
20206 // Transfer the remainder of BB and its successor edges to sinkMBB.
20207 sinkMBB->splice(sinkMBB->begin(), MBB,
20208 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20209 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20213 // # fallthrough to mainMBB
20214 // # abortion to sinkMBB
20215 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20216 thisMBB->addSuccessor(mainMBB);
20217 thisMBB->addSuccessor(sinkMBB);
20221 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20222 mainMBB->addSuccessor(sinkMBB);
20225 // EAX is live into the sinkMBB
20226 sinkMBB->addLiveIn(X86::EAX);
20227 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20228 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20231 MI->eraseFromParent();
20235 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20236 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20237 // in the .td file.
20238 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20239 const TargetInstrInfo *TII) {
20241 switch (MI->getOpcode()) {
20242 default: llvm_unreachable("illegal opcode!");
20243 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20244 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20245 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20246 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20247 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20248 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20249 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20250 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20253 DebugLoc dl = MI->getDebugLoc();
20254 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20256 unsigned NumArgs = MI->getNumOperands();
20257 for (unsigned i = 1; i < NumArgs; ++i) {
20258 MachineOperand &Op = MI->getOperand(i);
20259 if (!(Op.isReg() && Op.isImplicit()))
20260 MIB.addOperand(Op);
20262 if (MI->hasOneMemOperand())
20263 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20265 BuildMI(*BB, MI, dl,
20266 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20267 .addReg(X86::XMM0);
20269 MI->eraseFromParent();
20273 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20274 // defs in an instruction pattern
20275 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20276 const TargetInstrInfo *TII) {
20278 switch (MI->getOpcode()) {
20279 default: llvm_unreachable("illegal opcode!");
20280 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20281 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20282 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20283 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20284 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20285 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20286 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20287 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20290 DebugLoc dl = MI->getDebugLoc();
20291 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20293 unsigned NumArgs = MI->getNumOperands(); // remove the results
20294 for (unsigned i = 1; i < NumArgs; ++i) {
20295 MachineOperand &Op = MI->getOperand(i);
20296 if (!(Op.isReg() && Op.isImplicit()))
20297 MIB.addOperand(Op);
20299 if (MI->hasOneMemOperand())
20300 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20302 BuildMI(*BB, MI, dl,
20303 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20306 MI->eraseFromParent();
20310 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20311 const TargetInstrInfo *TII,
20312 const X86Subtarget* Subtarget) {
20313 DebugLoc dl = MI->getDebugLoc();
20315 // Address into RAX/EAX, other two args into ECX, EDX.
20316 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20317 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20318 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20319 for (int i = 0; i < X86::AddrNumOperands; ++i)
20320 MIB.addOperand(MI->getOperand(i));
20322 unsigned ValOps = X86::AddrNumOperands;
20323 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20324 .addReg(MI->getOperand(ValOps).getReg());
20325 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20326 .addReg(MI->getOperand(ValOps+1).getReg());
20328 // The instruction doesn't actually take any operands though.
20329 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20331 MI->eraseFromParent(); // The pseudo is gone now.
20335 MachineBasicBlock *
20336 X86TargetLowering::EmitVAARG64WithCustomInserter(
20338 MachineBasicBlock *MBB) const {
20339 // Emit va_arg instruction on X86-64.
20341 // Operands to this pseudo-instruction:
20342 // 0 ) Output : destination address (reg)
20343 // 1-5) Input : va_list address (addr, i64mem)
20344 // 6 ) ArgSize : Size (in bytes) of vararg type
20345 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20346 // 8 ) Align : Alignment of type
20347 // 9 ) EFLAGS (implicit-def)
20349 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20350 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20352 unsigned DestReg = MI->getOperand(0).getReg();
20353 MachineOperand &Base = MI->getOperand(1);
20354 MachineOperand &Scale = MI->getOperand(2);
20355 MachineOperand &Index = MI->getOperand(3);
20356 MachineOperand &Disp = MI->getOperand(4);
20357 MachineOperand &Segment = MI->getOperand(5);
20358 unsigned ArgSize = MI->getOperand(6).getImm();
20359 unsigned ArgMode = MI->getOperand(7).getImm();
20360 unsigned Align = MI->getOperand(8).getImm();
20362 // Memory Reference
20363 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20364 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20365 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20367 // Machine Information
20368 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20369 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20370 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20371 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20372 DebugLoc DL = MI->getDebugLoc();
20374 // struct va_list {
20377 // i64 overflow_area (address)
20378 // i64 reg_save_area (address)
20380 // sizeof(va_list) = 24
20381 // alignment(va_list) = 8
20383 unsigned TotalNumIntRegs = 6;
20384 unsigned TotalNumXMMRegs = 8;
20385 bool UseGPOffset = (ArgMode == 1);
20386 bool UseFPOffset = (ArgMode == 2);
20387 unsigned MaxOffset = TotalNumIntRegs * 8 +
20388 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20390 /* Align ArgSize to a multiple of 8 */
20391 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20392 bool NeedsAlign = (Align > 8);
20394 MachineBasicBlock *thisMBB = MBB;
20395 MachineBasicBlock *overflowMBB;
20396 MachineBasicBlock *offsetMBB;
20397 MachineBasicBlock *endMBB;
20399 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20400 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20401 unsigned OffsetReg = 0;
20403 if (!UseGPOffset && !UseFPOffset) {
20404 // If we only pull from the overflow region, we don't create a branch.
20405 // We don't need to alter control flow.
20406 OffsetDestReg = 0; // unused
20407 OverflowDestReg = DestReg;
20409 offsetMBB = nullptr;
20410 overflowMBB = thisMBB;
20413 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20414 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20415 // If not, pull from overflow_area. (branch to overflowMBB)
20420 // offsetMBB overflowMBB
20425 // Registers for the PHI in endMBB
20426 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20427 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20429 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20430 MachineFunction *MF = MBB->getParent();
20431 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20432 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20433 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20435 MachineFunction::iterator MBBIter = MBB;
20438 // Insert the new basic blocks
20439 MF->insert(MBBIter, offsetMBB);
20440 MF->insert(MBBIter, overflowMBB);
20441 MF->insert(MBBIter, endMBB);
20443 // Transfer the remainder of MBB and its successor edges to endMBB.
20444 endMBB->splice(endMBB->begin(), thisMBB,
20445 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20446 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20448 // Make offsetMBB and overflowMBB successors of thisMBB
20449 thisMBB->addSuccessor(offsetMBB);
20450 thisMBB->addSuccessor(overflowMBB);
20452 // endMBB is a successor of both offsetMBB and overflowMBB
20453 offsetMBB->addSuccessor(endMBB);
20454 overflowMBB->addSuccessor(endMBB);
20456 // Load the offset value into a register
20457 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20458 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20462 .addDisp(Disp, UseFPOffset ? 4 : 0)
20463 .addOperand(Segment)
20464 .setMemRefs(MMOBegin, MMOEnd);
20466 // Check if there is enough room left to pull this argument.
20467 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20469 .addImm(MaxOffset + 8 - ArgSizeA8);
20471 // Branch to "overflowMBB" if offset >= max
20472 // Fall through to "offsetMBB" otherwise
20473 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20474 .addMBB(overflowMBB);
20477 // In offsetMBB, emit code to use the reg_save_area.
20479 assert(OffsetReg != 0);
20481 // Read the reg_save_area address.
20482 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20483 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20488 .addOperand(Segment)
20489 .setMemRefs(MMOBegin, MMOEnd);
20491 // Zero-extend the offset
20492 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20493 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20496 .addImm(X86::sub_32bit);
20498 // Add the offset to the reg_save_area to get the final address.
20499 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20500 .addReg(OffsetReg64)
20501 .addReg(RegSaveReg);
20503 // Compute the offset for the next argument
20504 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20505 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20507 .addImm(UseFPOffset ? 16 : 8);
20509 // Store it back into the va_list.
20510 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20514 .addDisp(Disp, UseFPOffset ? 4 : 0)
20515 .addOperand(Segment)
20516 .addReg(NextOffsetReg)
20517 .setMemRefs(MMOBegin, MMOEnd);
20520 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20525 // Emit code to use overflow area
20528 // Load the overflow_area address into a register.
20529 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20530 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20535 .addOperand(Segment)
20536 .setMemRefs(MMOBegin, MMOEnd);
20538 // If we need to align it, do so. Otherwise, just copy the address
20539 // to OverflowDestReg.
20541 // Align the overflow address
20542 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20543 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20545 // aligned_addr = (addr + (align-1)) & ~(align-1)
20546 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20547 .addReg(OverflowAddrReg)
20550 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20552 .addImm(~(uint64_t)(Align-1));
20554 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20555 .addReg(OverflowAddrReg);
20558 // Compute the next overflow address after this argument.
20559 // (the overflow address should be kept 8-byte aligned)
20560 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20561 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20562 .addReg(OverflowDestReg)
20563 .addImm(ArgSizeA8);
20565 // Store the new overflow address.
20566 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20571 .addOperand(Segment)
20572 .addReg(NextAddrReg)
20573 .setMemRefs(MMOBegin, MMOEnd);
20575 // If we branched, emit the PHI to the front of endMBB.
20577 BuildMI(*endMBB, endMBB->begin(), DL,
20578 TII->get(X86::PHI), DestReg)
20579 .addReg(OffsetDestReg).addMBB(offsetMBB)
20580 .addReg(OverflowDestReg).addMBB(overflowMBB);
20583 // Erase the pseudo instruction
20584 MI->eraseFromParent();
20589 MachineBasicBlock *
20590 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20592 MachineBasicBlock *MBB) const {
20593 // Emit code to save XMM registers to the stack. The ABI says that the
20594 // number of registers to save is given in %al, so it's theoretically
20595 // possible to do an indirect jump trick to avoid saving all of them,
20596 // however this code takes a simpler approach and just executes all
20597 // of the stores if %al is non-zero. It's less code, and it's probably
20598 // easier on the hardware branch predictor, and stores aren't all that
20599 // expensive anyway.
20601 // Create the new basic blocks. One block contains all the XMM stores,
20602 // and one block is the final destination regardless of whether any
20603 // stores were performed.
20604 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20605 MachineFunction *F = MBB->getParent();
20606 MachineFunction::iterator MBBIter = MBB;
20608 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20609 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20610 F->insert(MBBIter, XMMSaveMBB);
20611 F->insert(MBBIter, EndMBB);
20613 // Transfer the remainder of MBB and its successor edges to EndMBB.
20614 EndMBB->splice(EndMBB->begin(), MBB,
20615 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20616 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20618 // The original block will now fall through to the XMM save block.
20619 MBB->addSuccessor(XMMSaveMBB);
20620 // The XMMSaveMBB will fall through to the end block.
20621 XMMSaveMBB->addSuccessor(EndMBB);
20623 // Now add the instructions.
20624 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20625 DebugLoc DL = MI->getDebugLoc();
20627 unsigned CountReg = MI->getOperand(0).getReg();
20628 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20629 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20631 if (!Subtarget->isTargetWin64()) {
20632 // If %al is 0, branch around the XMM save block.
20633 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20634 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20635 MBB->addSuccessor(EndMBB);
20638 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20639 // that was just emitted, but clearly shouldn't be "saved".
20640 assert((MI->getNumOperands() <= 3 ||
20641 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20642 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20643 && "Expected last argument to be EFLAGS");
20644 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20645 // In the XMM save block, save all the XMM argument registers.
20646 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20647 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20648 MachineMemOperand *MMO =
20649 F->getMachineMemOperand(
20650 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20651 MachineMemOperand::MOStore,
20652 /*Size=*/16, /*Align=*/16);
20653 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20654 .addFrameIndex(RegSaveFrameIndex)
20655 .addImm(/*Scale=*/1)
20656 .addReg(/*IndexReg=*/0)
20657 .addImm(/*Disp=*/Offset)
20658 .addReg(/*Segment=*/0)
20659 .addReg(MI->getOperand(i).getReg())
20660 .addMemOperand(MMO);
20663 MI->eraseFromParent(); // The pseudo instruction is gone now.
20668 // The EFLAGS operand of SelectItr might be missing a kill marker
20669 // because there were multiple uses of EFLAGS, and ISel didn't know
20670 // which to mark. Figure out whether SelectItr should have had a
20671 // kill marker, and set it if it should. Returns the correct kill
20673 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20674 MachineBasicBlock* BB,
20675 const TargetRegisterInfo* TRI) {
20676 // Scan forward through BB for a use/def of EFLAGS.
20677 MachineBasicBlock::iterator miI(std::next(SelectItr));
20678 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20679 const MachineInstr& mi = *miI;
20680 if (mi.readsRegister(X86::EFLAGS))
20682 if (mi.definesRegister(X86::EFLAGS))
20683 break; // Should have kill-flag - update below.
20686 // If we hit the end of the block, check whether EFLAGS is live into a
20688 if (miI == BB->end()) {
20689 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20690 sEnd = BB->succ_end();
20691 sItr != sEnd; ++sItr) {
20692 MachineBasicBlock* succ = *sItr;
20693 if (succ->isLiveIn(X86::EFLAGS))
20698 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20699 // out. SelectMI should have a kill flag on EFLAGS.
20700 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20704 MachineBasicBlock *
20705 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20706 MachineBasicBlock *BB) const {
20707 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20708 DebugLoc DL = MI->getDebugLoc();
20710 // To "insert" a SELECT_CC instruction, we actually have to insert the
20711 // diamond control-flow pattern. The incoming instruction knows the
20712 // destination vreg to set, the condition code register to branch on, the
20713 // true/false values to select between, and a branch opcode to use.
20714 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20715 MachineFunction::iterator It = BB;
20721 // cmpTY ccX, r1, r2
20723 // fallthrough --> copy0MBB
20724 MachineBasicBlock *thisMBB = BB;
20725 MachineFunction *F = BB->getParent();
20726 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20727 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20728 F->insert(It, copy0MBB);
20729 F->insert(It, sinkMBB);
20731 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20732 // live into the sink and copy blocks.
20733 const TargetRegisterInfo *TRI =
20734 BB->getParent()->getSubtarget().getRegisterInfo();
20735 if (!MI->killsRegister(X86::EFLAGS) &&
20736 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20737 copy0MBB->addLiveIn(X86::EFLAGS);
20738 sinkMBB->addLiveIn(X86::EFLAGS);
20741 // Transfer the remainder of BB and its successor edges to sinkMBB.
20742 sinkMBB->splice(sinkMBB->begin(), BB,
20743 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20744 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20746 // Add the true and fallthrough blocks as its successors.
20747 BB->addSuccessor(copy0MBB);
20748 BB->addSuccessor(sinkMBB);
20750 // Create the conditional branch instruction.
20752 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20753 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20756 // %FalseValue = ...
20757 // # fallthrough to sinkMBB
20758 copy0MBB->addSuccessor(sinkMBB);
20761 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20763 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20764 TII->get(X86::PHI), MI->getOperand(0).getReg())
20765 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20766 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20768 MI->eraseFromParent(); // The pseudo instruction is gone now.
20772 MachineBasicBlock *
20773 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20774 MachineBasicBlock *BB) const {
20775 MachineFunction *MF = BB->getParent();
20776 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20777 DebugLoc DL = MI->getDebugLoc();
20778 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20780 assert(MF->shouldSplitStack());
20782 const bool Is64Bit = Subtarget->is64Bit();
20783 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20785 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20786 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20789 // ... [Till the alloca]
20790 // If stacklet is not large enough, jump to mallocMBB
20793 // Allocate by subtracting from RSP
20794 // Jump to continueMBB
20797 // Allocate by call to runtime
20801 // [rest of original BB]
20804 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20805 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20806 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20808 MachineRegisterInfo &MRI = MF->getRegInfo();
20809 const TargetRegisterClass *AddrRegClass =
20810 getRegClassFor(getPointerTy());
20812 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20813 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20814 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20815 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20816 sizeVReg = MI->getOperand(1).getReg(),
20817 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20819 MachineFunction::iterator MBBIter = BB;
20822 MF->insert(MBBIter, bumpMBB);
20823 MF->insert(MBBIter, mallocMBB);
20824 MF->insert(MBBIter, continueMBB);
20826 continueMBB->splice(continueMBB->begin(), BB,
20827 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20828 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20830 // Add code to the main basic block to check if the stack limit has been hit,
20831 // and if so, jump to mallocMBB otherwise to bumpMBB.
20832 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20833 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20834 .addReg(tmpSPVReg).addReg(sizeVReg);
20835 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20836 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20837 .addReg(SPLimitVReg);
20838 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20840 // bumpMBB simply decreases the stack pointer, since we know the current
20841 // stacklet has enough space.
20842 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20843 .addReg(SPLimitVReg);
20844 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20845 .addReg(SPLimitVReg);
20846 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20848 // Calls into a routine in libgcc to allocate more space from the heap.
20849 const uint32_t *RegMask = MF->getTarget()
20850 .getSubtargetImpl()
20851 ->getRegisterInfo()
20852 ->getCallPreservedMask(CallingConv::C);
20854 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20856 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20857 .addExternalSymbol("__morestack_allocate_stack_space")
20858 .addRegMask(RegMask)
20859 .addReg(X86::RDI, RegState::Implicit)
20860 .addReg(X86::RAX, RegState::ImplicitDefine);
20861 } else if (Is64Bit) {
20862 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20864 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20865 .addExternalSymbol("__morestack_allocate_stack_space")
20866 .addRegMask(RegMask)
20867 .addReg(X86::EDI, RegState::Implicit)
20868 .addReg(X86::EAX, RegState::ImplicitDefine);
20870 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20872 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20873 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20874 .addExternalSymbol("__morestack_allocate_stack_space")
20875 .addRegMask(RegMask)
20876 .addReg(X86::EAX, RegState::ImplicitDefine);
20880 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20883 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20884 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20885 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20887 // Set up the CFG correctly.
20888 BB->addSuccessor(bumpMBB);
20889 BB->addSuccessor(mallocMBB);
20890 mallocMBB->addSuccessor(continueMBB);
20891 bumpMBB->addSuccessor(continueMBB);
20893 // Take care of the PHI nodes.
20894 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20895 MI->getOperand(0).getReg())
20896 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20897 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20899 // Delete the original pseudo instruction.
20900 MI->eraseFromParent();
20903 return continueMBB;
20906 MachineBasicBlock *
20907 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20908 MachineBasicBlock *BB) const {
20909 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20910 DebugLoc DL = MI->getDebugLoc();
20912 assert(!Subtarget->isTargetMachO());
20914 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20915 // non-trivial part is impdef of ESP.
20917 if (Subtarget->isTargetWin64()) {
20918 if (Subtarget->isTargetCygMing()) {
20919 // ___chkstk(Mingw64):
20920 // Clobbers R10, R11, RAX and EFLAGS.
20922 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20923 .addExternalSymbol("___chkstk")
20924 .addReg(X86::RAX, RegState::Implicit)
20925 .addReg(X86::RSP, RegState::Implicit)
20926 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20927 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20928 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20930 // __chkstk(MSVCRT): does not update stack pointer.
20931 // Clobbers R10, R11 and EFLAGS.
20932 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20933 .addExternalSymbol("__chkstk")
20934 .addReg(X86::RAX, RegState::Implicit)
20935 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20936 // RAX has the offset to be subtracted from RSP.
20937 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20942 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20943 Subtarget->isTargetWindowsItanium())
20947 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20948 .addExternalSymbol(StackProbeSymbol)
20949 .addReg(X86::EAX, RegState::Implicit)
20950 .addReg(X86::ESP, RegState::Implicit)
20951 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20952 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20953 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20956 MI->eraseFromParent(); // The pseudo instruction is gone now.
20960 MachineBasicBlock *
20961 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20962 MachineBasicBlock *BB) const {
20963 // This is pretty easy. We're taking the value that we received from
20964 // our load from the relocation, sticking it in either RDI (x86-64)
20965 // or EAX and doing an indirect call. The return value will then
20966 // be in the normal return register.
20967 MachineFunction *F = BB->getParent();
20968 const X86InstrInfo *TII =
20969 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20970 DebugLoc DL = MI->getDebugLoc();
20972 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20973 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20975 // Get a register mask for the lowered call.
20976 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20977 // proper register mask.
20978 const uint32_t *RegMask = F->getTarget()
20979 .getSubtargetImpl()
20980 ->getRegisterInfo()
20981 ->getCallPreservedMask(CallingConv::C);
20982 if (Subtarget->is64Bit()) {
20983 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20984 TII->get(X86::MOV64rm), X86::RDI)
20986 .addImm(0).addReg(0)
20987 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20988 MI->getOperand(3).getTargetFlags())
20990 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20991 addDirectMem(MIB, X86::RDI);
20992 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20993 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20994 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20995 TII->get(X86::MOV32rm), X86::EAX)
20997 .addImm(0).addReg(0)
20998 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20999 MI->getOperand(3).getTargetFlags())
21001 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21002 addDirectMem(MIB, X86::EAX);
21003 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21005 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21006 TII->get(X86::MOV32rm), X86::EAX)
21007 .addReg(TII->getGlobalBaseReg(F))
21008 .addImm(0).addReg(0)
21009 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21010 MI->getOperand(3).getTargetFlags())
21012 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21013 addDirectMem(MIB, X86::EAX);
21014 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21017 MI->eraseFromParent(); // The pseudo instruction is gone now.
21021 MachineBasicBlock *
21022 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21023 MachineBasicBlock *MBB) const {
21024 DebugLoc DL = MI->getDebugLoc();
21025 MachineFunction *MF = MBB->getParent();
21026 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21027 MachineRegisterInfo &MRI = MF->getRegInfo();
21029 const BasicBlock *BB = MBB->getBasicBlock();
21030 MachineFunction::iterator I = MBB;
21033 // Memory Reference
21034 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21035 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21038 unsigned MemOpndSlot = 0;
21040 unsigned CurOp = 0;
21042 DstReg = MI->getOperand(CurOp++).getReg();
21043 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21044 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21045 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21046 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21048 MemOpndSlot = CurOp;
21050 MVT PVT = getPointerTy();
21051 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21052 "Invalid Pointer Size!");
21054 // For v = setjmp(buf), we generate
21057 // buf[LabelOffset] = restoreMBB
21058 // SjLjSetup restoreMBB
21064 // v = phi(main, restore)
21067 // if base pointer being used, load it from frame
21070 MachineBasicBlock *thisMBB = MBB;
21071 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21072 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21073 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21074 MF->insert(I, mainMBB);
21075 MF->insert(I, sinkMBB);
21076 MF->push_back(restoreMBB);
21078 MachineInstrBuilder MIB;
21080 // Transfer the remainder of BB and its successor edges to sinkMBB.
21081 sinkMBB->splice(sinkMBB->begin(), MBB,
21082 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21083 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21086 unsigned PtrStoreOpc = 0;
21087 unsigned LabelReg = 0;
21088 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21089 Reloc::Model RM = MF->getTarget().getRelocationModel();
21090 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21091 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21093 // Prepare IP either in reg or imm.
21094 if (!UseImmLabel) {
21095 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21096 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21097 LabelReg = MRI.createVirtualRegister(PtrRC);
21098 if (Subtarget->is64Bit()) {
21099 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21103 .addMBB(restoreMBB)
21106 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21107 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21108 .addReg(XII->getGlobalBaseReg(MF))
21111 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21115 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21117 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21118 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21119 if (i == X86::AddrDisp)
21120 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21122 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21125 MIB.addReg(LabelReg);
21127 MIB.addMBB(restoreMBB);
21128 MIB.setMemRefs(MMOBegin, MMOEnd);
21130 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21131 .addMBB(restoreMBB);
21133 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21134 MF->getSubtarget().getRegisterInfo());
21135 MIB.addRegMask(RegInfo->getNoPreservedMask());
21136 thisMBB->addSuccessor(mainMBB);
21137 thisMBB->addSuccessor(restoreMBB);
21141 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21142 mainMBB->addSuccessor(sinkMBB);
21145 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21146 TII->get(X86::PHI), DstReg)
21147 .addReg(mainDstReg).addMBB(mainMBB)
21148 .addReg(restoreDstReg).addMBB(restoreMBB);
21151 if (RegInfo->hasBasePointer(*MF)) {
21152 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21153 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21154 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21155 X86FI->setRestoreBasePointer(MF);
21156 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21157 unsigned BasePtr = RegInfo->getBaseRegister();
21158 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21159 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21160 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21161 .setMIFlag(MachineInstr::FrameSetup);
21163 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21164 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21165 restoreMBB->addSuccessor(sinkMBB);
21167 MI->eraseFromParent();
21171 MachineBasicBlock *
21172 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21173 MachineBasicBlock *MBB) const {
21174 DebugLoc DL = MI->getDebugLoc();
21175 MachineFunction *MF = MBB->getParent();
21176 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21177 MachineRegisterInfo &MRI = MF->getRegInfo();
21179 // Memory Reference
21180 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21181 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21183 MVT PVT = getPointerTy();
21184 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21185 "Invalid Pointer Size!");
21187 const TargetRegisterClass *RC =
21188 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21189 unsigned Tmp = MRI.createVirtualRegister(RC);
21190 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21191 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21192 MF->getSubtarget().getRegisterInfo());
21193 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21194 unsigned SP = RegInfo->getStackRegister();
21196 MachineInstrBuilder MIB;
21198 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21199 const int64_t SPOffset = 2 * PVT.getStoreSize();
21201 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21202 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21205 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21206 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21207 MIB.addOperand(MI->getOperand(i));
21208 MIB.setMemRefs(MMOBegin, MMOEnd);
21210 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21211 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21212 if (i == X86::AddrDisp)
21213 MIB.addDisp(MI->getOperand(i), LabelOffset);
21215 MIB.addOperand(MI->getOperand(i));
21217 MIB.setMemRefs(MMOBegin, MMOEnd);
21219 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21220 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21221 if (i == X86::AddrDisp)
21222 MIB.addDisp(MI->getOperand(i), SPOffset);
21224 MIB.addOperand(MI->getOperand(i));
21226 MIB.setMemRefs(MMOBegin, MMOEnd);
21228 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21230 MI->eraseFromParent();
21234 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21235 // accumulator loops. Writing back to the accumulator allows the coalescer
21236 // to remove extra copies in the loop.
21237 MachineBasicBlock *
21238 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21239 MachineBasicBlock *MBB) const {
21240 MachineOperand &AddendOp = MI->getOperand(3);
21242 // Bail out early if the addend isn't a register - we can't switch these.
21243 if (!AddendOp.isReg())
21246 MachineFunction &MF = *MBB->getParent();
21247 MachineRegisterInfo &MRI = MF.getRegInfo();
21249 // Check whether the addend is defined by a PHI:
21250 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21251 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21252 if (!AddendDef.isPHI())
21255 // Look for the following pattern:
21257 // %addend = phi [%entry, 0], [%loop, %result]
21259 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21263 // %addend = phi [%entry, 0], [%loop, %result]
21265 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21267 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21268 assert(AddendDef.getOperand(i).isReg());
21269 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21270 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21271 if (&PHISrcInst == MI) {
21272 // Found a matching instruction.
21273 unsigned NewFMAOpc = 0;
21274 switch (MI->getOpcode()) {
21275 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21276 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21277 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21278 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21279 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21280 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21281 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21282 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21283 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21284 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21285 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21286 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21287 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21288 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21289 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21290 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21291 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21292 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21293 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21294 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21296 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21297 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21298 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21299 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21300 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21301 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21302 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21303 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21304 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21305 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21306 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21307 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21308 default: llvm_unreachable("Unrecognized FMA variant.");
21311 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21312 MachineInstrBuilder MIB =
21313 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21314 .addOperand(MI->getOperand(0))
21315 .addOperand(MI->getOperand(3))
21316 .addOperand(MI->getOperand(2))
21317 .addOperand(MI->getOperand(1));
21318 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21319 MI->eraseFromParent();
21326 MachineBasicBlock *
21327 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21328 MachineBasicBlock *BB) const {
21329 switch (MI->getOpcode()) {
21330 default: llvm_unreachable("Unexpected instr type to insert");
21331 case X86::TAILJMPd64:
21332 case X86::TAILJMPr64:
21333 case X86::TAILJMPm64:
21334 llvm_unreachable("TAILJMP64 would not be touched here.");
21335 case X86::TCRETURNdi64:
21336 case X86::TCRETURNri64:
21337 case X86::TCRETURNmi64:
21339 case X86::WIN_ALLOCA:
21340 return EmitLoweredWinAlloca(MI, BB);
21341 case X86::SEG_ALLOCA_32:
21342 case X86::SEG_ALLOCA_64:
21343 return EmitLoweredSegAlloca(MI, BB);
21344 case X86::TLSCall_32:
21345 case X86::TLSCall_64:
21346 return EmitLoweredTLSCall(MI, BB);
21347 case X86::CMOV_GR8:
21348 case X86::CMOV_FR32:
21349 case X86::CMOV_FR64:
21350 case X86::CMOV_V4F32:
21351 case X86::CMOV_V2F64:
21352 case X86::CMOV_V2I64:
21353 case X86::CMOV_V8F32:
21354 case X86::CMOV_V4F64:
21355 case X86::CMOV_V4I64:
21356 case X86::CMOV_V16F32:
21357 case X86::CMOV_V8F64:
21358 case X86::CMOV_V8I64:
21359 case X86::CMOV_GR16:
21360 case X86::CMOV_GR32:
21361 case X86::CMOV_RFP32:
21362 case X86::CMOV_RFP64:
21363 case X86::CMOV_RFP80:
21364 return EmitLoweredSelect(MI, BB);
21366 case X86::FP32_TO_INT16_IN_MEM:
21367 case X86::FP32_TO_INT32_IN_MEM:
21368 case X86::FP32_TO_INT64_IN_MEM:
21369 case X86::FP64_TO_INT16_IN_MEM:
21370 case X86::FP64_TO_INT32_IN_MEM:
21371 case X86::FP64_TO_INT64_IN_MEM:
21372 case X86::FP80_TO_INT16_IN_MEM:
21373 case X86::FP80_TO_INT32_IN_MEM:
21374 case X86::FP80_TO_INT64_IN_MEM: {
21375 MachineFunction *F = BB->getParent();
21376 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21377 DebugLoc DL = MI->getDebugLoc();
21379 // Change the floating point control register to use "round towards zero"
21380 // mode when truncating to an integer value.
21381 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21382 addFrameReference(BuildMI(*BB, MI, DL,
21383 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21385 // Load the old value of the high byte of the control word...
21387 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21388 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21391 // Set the high part to be round to zero...
21392 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21395 // Reload the modified control word now...
21396 addFrameReference(BuildMI(*BB, MI, DL,
21397 TII->get(X86::FLDCW16m)), CWFrameIdx);
21399 // Restore the memory image of control word to original value
21400 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21403 // Get the X86 opcode to use.
21405 switch (MI->getOpcode()) {
21406 default: llvm_unreachable("illegal opcode!");
21407 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21408 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21409 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21410 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21411 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21412 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21413 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21414 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21415 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21419 MachineOperand &Op = MI->getOperand(0);
21421 AM.BaseType = X86AddressMode::RegBase;
21422 AM.Base.Reg = Op.getReg();
21424 AM.BaseType = X86AddressMode::FrameIndexBase;
21425 AM.Base.FrameIndex = Op.getIndex();
21427 Op = MI->getOperand(1);
21429 AM.Scale = Op.getImm();
21430 Op = MI->getOperand(2);
21432 AM.IndexReg = Op.getImm();
21433 Op = MI->getOperand(3);
21434 if (Op.isGlobal()) {
21435 AM.GV = Op.getGlobal();
21437 AM.Disp = Op.getImm();
21439 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21440 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21442 // Reload the original control word now.
21443 addFrameReference(BuildMI(*BB, MI, DL,
21444 TII->get(X86::FLDCW16m)), CWFrameIdx);
21446 MI->eraseFromParent(); // The pseudo instruction is gone now.
21449 // String/text processing lowering.
21450 case X86::PCMPISTRM128REG:
21451 case X86::VPCMPISTRM128REG:
21452 case X86::PCMPISTRM128MEM:
21453 case X86::VPCMPISTRM128MEM:
21454 case X86::PCMPESTRM128REG:
21455 case X86::VPCMPESTRM128REG:
21456 case X86::PCMPESTRM128MEM:
21457 case X86::VPCMPESTRM128MEM:
21458 assert(Subtarget->hasSSE42() &&
21459 "Target must have SSE4.2 or AVX features enabled");
21460 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21462 // String/text processing lowering.
21463 case X86::PCMPISTRIREG:
21464 case X86::VPCMPISTRIREG:
21465 case X86::PCMPISTRIMEM:
21466 case X86::VPCMPISTRIMEM:
21467 case X86::PCMPESTRIREG:
21468 case X86::VPCMPESTRIREG:
21469 case X86::PCMPESTRIMEM:
21470 case X86::VPCMPESTRIMEM:
21471 assert(Subtarget->hasSSE42() &&
21472 "Target must have SSE4.2 or AVX features enabled");
21473 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21475 // Thread synchronization.
21477 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21482 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21484 case X86::VASTART_SAVE_XMM_REGS:
21485 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21487 case X86::VAARG_64:
21488 return EmitVAARG64WithCustomInserter(MI, BB);
21490 case X86::EH_SjLj_SetJmp32:
21491 case X86::EH_SjLj_SetJmp64:
21492 return emitEHSjLjSetJmp(MI, BB);
21494 case X86::EH_SjLj_LongJmp32:
21495 case X86::EH_SjLj_LongJmp64:
21496 return emitEHSjLjLongJmp(MI, BB);
21498 case TargetOpcode::STATEPOINT:
21499 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21500 // this point in the process. We diverge later.
21501 return emitPatchPoint(MI, BB);
21503 case TargetOpcode::STACKMAP:
21504 case TargetOpcode::PATCHPOINT:
21505 return emitPatchPoint(MI, BB);
21507 case X86::VFMADDPDr213r:
21508 case X86::VFMADDPSr213r:
21509 case X86::VFMADDSDr213r:
21510 case X86::VFMADDSSr213r:
21511 case X86::VFMSUBPDr213r:
21512 case X86::VFMSUBPSr213r:
21513 case X86::VFMSUBSDr213r:
21514 case X86::VFMSUBSSr213r:
21515 case X86::VFNMADDPDr213r:
21516 case X86::VFNMADDPSr213r:
21517 case X86::VFNMADDSDr213r:
21518 case X86::VFNMADDSSr213r:
21519 case X86::VFNMSUBPDr213r:
21520 case X86::VFNMSUBPSr213r:
21521 case X86::VFNMSUBSDr213r:
21522 case X86::VFNMSUBSSr213r:
21523 case X86::VFMADDSUBPDr213r:
21524 case X86::VFMADDSUBPSr213r:
21525 case X86::VFMSUBADDPDr213r:
21526 case X86::VFMSUBADDPSr213r:
21527 case X86::VFMADDPDr213rY:
21528 case X86::VFMADDPSr213rY:
21529 case X86::VFMSUBPDr213rY:
21530 case X86::VFMSUBPSr213rY:
21531 case X86::VFNMADDPDr213rY:
21532 case X86::VFNMADDPSr213rY:
21533 case X86::VFNMSUBPDr213rY:
21534 case X86::VFNMSUBPSr213rY:
21535 case X86::VFMADDSUBPDr213rY:
21536 case X86::VFMADDSUBPSr213rY:
21537 case X86::VFMSUBADDPDr213rY:
21538 case X86::VFMSUBADDPSr213rY:
21539 return emitFMA3Instr(MI, BB);
21543 //===----------------------------------------------------------------------===//
21544 // X86 Optimization Hooks
21545 //===----------------------------------------------------------------------===//
21547 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21550 const SelectionDAG &DAG,
21551 unsigned Depth) const {
21552 unsigned BitWidth = KnownZero.getBitWidth();
21553 unsigned Opc = Op.getOpcode();
21554 assert((Opc >= ISD::BUILTIN_OP_END ||
21555 Opc == ISD::INTRINSIC_WO_CHAIN ||
21556 Opc == ISD::INTRINSIC_W_CHAIN ||
21557 Opc == ISD::INTRINSIC_VOID) &&
21558 "Should use MaskedValueIsZero if you don't know whether Op"
21559 " is a target node!");
21561 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21575 // These nodes' second result is a boolean.
21576 if (Op.getResNo() == 0)
21579 case X86ISD::SETCC:
21580 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21582 case ISD::INTRINSIC_WO_CHAIN: {
21583 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21584 unsigned NumLoBits = 0;
21587 case Intrinsic::x86_sse_movmsk_ps:
21588 case Intrinsic::x86_avx_movmsk_ps_256:
21589 case Intrinsic::x86_sse2_movmsk_pd:
21590 case Intrinsic::x86_avx_movmsk_pd_256:
21591 case Intrinsic::x86_mmx_pmovmskb:
21592 case Intrinsic::x86_sse2_pmovmskb_128:
21593 case Intrinsic::x86_avx2_pmovmskb: {
21594 // High bits of movmskp{s|d}, pmovmskb are known zero.
21596 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21597 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21598 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21599 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21600 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21601 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21602 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21603 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21605 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21614 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21616 const SelectionDAG &,
21617 unsigned Depth) const {
21618 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21619 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21620 return Op.getValueType().getScalarType().getSizeInBits();
21626 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21627 /// node is a GlobalAddress + offset.
21628 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21629 const GlobalValue* &GA,
21630 int64_t &Offset) const {
21631 if (N->getOpcode() == X86ISD::Wrapper) {
21632 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21633 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21634 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21638 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21641 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21642 /// same as extracting the high 128-bit part of 256-bit vector and then
21643 /// inserting the result into the low part of a new 256-bit vector
21644 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21645 EVT VT = SVOp->getValueType(0);
21646 unsigned NumElems = VT.getVectorNumElements();
21648 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21649 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21650 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21651 SVOp->getMaskElt(j) >= 0)
21657 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21658 /// same as extracting the low 128-bit part of 256-bit vector and then
21659 /// inserting the result into the high part of a new 256-bit vector
21660 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21661 EVT VT = SVOp->getValueType(0);
21662 unsigned NumElems = VT.getVectorNumElements();
21664 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21665 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21666 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21667 SVOp->getMaskElt(j) >= 0)
21673 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21674 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21675 TargetLowering::DAGCombinerInfo &DCI,
21676 const X86Subtarget* Subtarget) {
21678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21679 SDValue V1 = SVOp->getOperand(0);
21680 SDValue V2 = SVOp->getOperand(1);
21681 EVT VT = SVOp->getValueType(0);
21682 unsigned NumElems = VT.getVectorNumElements();
21684 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21685 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21689 // V UNDEF BUILD_VECTOR UNDEF
21691 // CONCAT_VECTOR CONCAT_VECTOR
21694 // RESULT: V + zero extended
21696 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21697 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21698 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21701 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21704 // To match the shuffle mask, the first half of the mask should
21705 // be exactly the first vector, and all the rest a splat with the
21706 // first element of the second one.
21707 for (unsigned i = 0; i != NumElems/2; ++i)
21708 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21709 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21712 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21713 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21714 if (Ld->hasNUsesOfValue(1, 0)) {
21715 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21716 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21718 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21720 Ld->getPointerInfo(),
21721 Ld->getAlignment(),
21722 false/*isVolatile*/, true/*ReadMem*/,
21723 false/*WriteMem*/);
21725 // Make sure the newly-created LOAD is in the same position as Ld in
21726 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21727 // and update uses of Ld's output chain to use the TokenFactor.
21728 if (Ld->hasAnyUseOfValue(1)) {
21729 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21730 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21731 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21732 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21733 SDValue(ResNode.getNode(), 1));
21736 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21740 // Emit a zeroed vector and insert the desired subvector on its
21742 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21743 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21744 return DCI.CombineTo(N, InsV);
21747 //===--------------------------------------------------------------------===//
21748 // Combine some shuffles into subvector extracts and inserts:
21751 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21752 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21753 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21754 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21755 return DCI.CombineTo(N, InsV);
21758 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21759 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21760 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21761 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21762 return DCI.CombineTo(N, InsV);
21768 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21771 /// This is the leaf of the recursive combinine below. When we have found some
21772 /// chain of single-use x86 shuffle instructions and accumulated the combined
21773 /// shuffle mask represented by them, this will try to pattern match that mask
21774 /// into either a single instruction if there is a special purpose instruction
21775 /// for this operation, or into a PSHUFB instruction which is a fully general
21776 /// instruction but should only be used to replace chains over a certain depth.
21777 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21778 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21779 TargetLowering::DAGCombinerInfo &DCI,
21780 const X86Subtarget *Subtarget) {
21781 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21783 // Find the operand that enters the chain. Note that multiple uses are OK
21784 // here, we're not going to remove the operand we find.
21785 SDValue Input = Op.getOperand(0);
21786 while (Input.getOpcode() == ISD::BITCAST)
21787 Input = Input.getOperand(0);
21789 MVT VT = Input.getSimpleValueType();
21790 MVT RootVT = Root.getSimpleValueType();
21793 // Just remove no-op shuffle masks.
21794 if (Mask.size() == 1) {
21795 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21800 // Use the float domain if the operand type is a floating point type.
21801 bool FloatDomain = VT.isFloatingPoint();
21803 // For floating point shuffles, we don't have free copies in the shuffle
21804 // instructions or the ability to load as part of the instruction, so
21805 // canonicalize their shuffles to UNPCK or MOV variants.
21807 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21808 // vectors because it can have a load folded into it that UNPCK cannot. This
21809 // doesn't preclude something switching to the shorter encoding post-RA.
21811 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21812 bool Lo = Mask.equals(0, 0);
21815 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21816 // is no slower than UNPCKLPD but has the option to fold the input operand
21817 // into even an unaligned memory load.
21818 if (Lo && Subtarget->hasSSE3()) {
21819 Shuffle = X86ISD::MOVDDUP;
21820 ShuffleVT = MVT::v2f64;
21822 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21823 // than the UNPCK variants.
21824 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21825 ShuffleVT = MVT::v4f32;
21827 if (Depth == 1 && Root->getOpcode() == Shuffle)
21828 return false; // Nothing to do!
21829 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21830 DCI.AddToWorklist(Op.getNode());
21831 if (Shuffle == X86ISD::MOVDDUP)
21832 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21834 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21835 DCI.AddToWorklist(Op.getNode());
21836 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21840 if (Subtarget->hasSSE3() &&
21841 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21842 bool Lo = Mask.equals(0, 0, 2, 2);
21843 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21844 MVT ShuffleVT = MVT::v4f32;
21845 if (Depth == 1 && Root->getOpcode() == Shuffle)
21846 return false; // Nothing to do!
21847 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21848 DCI.AddToWorklist(Op.getNode());
21849 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21850 DCI.AddToWorklist(Op.getNode());
21851 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21855 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21856 bool Lo = Mask.equals(0, 0, 1, 1);
21857 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21858 MVT ShuffleVT = MVT::v4f32;
21859 if (Depth == 1 && Root->getOpcode() == Shuffle)
21860 return false; // Nothing to do!
21861 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21862 DCI.AddToWorklist(Op.getNode());
21863 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21864 DCI.AddToWorklist(Op.getNode());
21865 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21871 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21872 // variants as none of these have single-instruction variants that are
21873 // superior to the UNPCK formulation.
21874 if (!FloatDomain &&
21875 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21876 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21877 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21878 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21880 bool Lo = Mask[0] == 0;
21881 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21882 if (Depth == 1 && Root->getOpcode() == Shuffle)
21883 return false; // Nothing to do!
21885 switch (Mask.size()) {
21887 ShuffleVT = MVT::v8i16;
21890 ShuffleVT = MVT::v16i8;
21893 llvm_unreachable("Impossible mask size!");
21895 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21896 DCI.AddToWorklist(Op.getNode());
21897 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21898 DCI.AddToWorklist(Op.getNode());
21899 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21904 // Don't try to re-form single instruction chains under any circumstances now
21905 // that we've done encoding canonicalization for them.
21909 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21910 // can replace them with a single PSHUFB instruction profitably. Intel's
21911 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21912 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21913 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21914 SmallVector<SDValue, 16> PSHUFBMask;
21915 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21916 int Ratio = 16 / Mask.size();
21917 for (unsigned i = 0; i < 16; ++i) {
21918 if (Mask[i / Ratio] == SM_SentinelUndef) {
21919 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21922 int M = Mask[i / Ratio] != SM_SentinelZero
21923 ? Ratio * Mask[i / Ratio] + i % Ratio
21925 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21927 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21928 DCI.AddToWorklist(Op.getNode());
21929 SDValue PSHUFBMaskOp =
21930 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21931 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21932 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21933 DCI.AddToWorklist(Op.getNode());
21934 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21939 // Failed to find any combines.
21943 /// \brief Fully generic combining of x86 shuffle instructions.
21945 /// This should be the last combine run over the x86 shuffle instructions. Once
21946 /// they have been fully optimized, this will recursively consider all chains
21947 /// of single-use shuffle instructions, build a generic model of the cumulative
21948 /// shuffle operation, and check for simpler instructions which implement this
21949 /// operation. We use this primarily for two purposes:
21951 /// 1) Collapse generic shuffles to specialized single instructions when
21952 /// equivalent. In most cases, this is just an encoding size win, but
21953 /// sometimes we will collapse multiple generic shuffles into a single
21954 /// special-purpose shuffle.
21955 /// 2) Look for sequences of shuffle instructions with 3 or more total
21956 /// instructions, and replace them with the slightly more expensive SSSE3
21957 /// PSHUFB instruction if available. We do this as the last combining step
21958 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21959 /// a suitable short sequence of other instructions. The PHUFB will either
21960 /// use a register or have to read from memory and so is slightly (but only
21961 /// slightly) more expensive than the other shuffle instructions.
21963 /// Because this is inherently a quadratic operation (for each shuffle in
21964 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21965 /// This should never be an issue in practice as the shuffle lowering doesn't
21966 /// produce sequences of more than 8 instructions.
21968 /// FIXME: We will currently miss some cases where the redundant shuffling
21969 /// would simplify under the threshold for PSHUFB formation because of
21970 /// combine-ordering. To fix this, we should do the redundant instruction
21971 /// combining in this recursive walk.
21972 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21973 ArrayRef<int> RootMask,
21974 int Depth, bool HasPSHUFB,
21976 TargetLowering::DAGCombinerInfo &DCI,
21977 const X86Subtarget *Subtarget) {
21978 // Bound the depth of our recursive combine because this is ultimately
21979 // quadratic in nature.
21983 // Directly rip through bitcasts to find the underlying operand.
21984 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21985 Op = Op.getOperand(0);
21987 MVT VT = Op.getSimpleValueType();
21988 if (!VT.isVector())
21989 return false; // Bail if we hit a non-vector.
21990 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21991 // version should be added.
21992 if (VT.getSizeInBits() != 128)
21995 assert(Root.getSimpleValueType().isVector() &&
21996 "Shuffles operate on vector types!");
21997 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21998 "Can only combine shuffles of the same vector register size.");
22000 if (!isTargetShuffle(Op.getOpcode()))
22002 SmallVector<int, 16> OpMask;
22004 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22005 // We only can combine unary shuffles which we can decode the mask for.
22006 if (!HaveMask || !IsUnary)
22009 assert(VT.getVectorNumElements() == OpMask.size() &&
22010 "Different mask size from vector size!");
22011 assert(((RootMask.size() > OpMask.size() &&
22012 RootMask.size() % OpMask.size() == 0) ||
22013 (OpMask.size() > RootMask.size() &&
22014 OpMask.size() % RootMask.size() == 0) ||
22015 OpMask.size() == RootMask.size()) &&
22016 "The smaller number of elements must divide the larger.");
22017 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22018 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22019 assert(((RootRatio == 1 && OpRatio == 1) ||
22020 (RootRatio == 1) != (OpRatio == 1)) &&
22021 "Must not have a ratio for both incoming and op masks!");
22023 SmallVector<int, 16> Mask;
22024 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22026 // Merge this shuffle operation's mask into our accumulated mask. Note that
22027 // this shuffle's mask will be the first applied to the input, followed by the
22028 // root mask to get us all the way to the root value arrangement. The reason
22029 // for this order is that we are recursing up the operation chain.
22030 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22031 int RootIdx = i / RootRatio;
22032 if (RootMask[RootIdx] < 0) {
22033 // This is a zero or undef lane, we're done.
22034 Mask.push_back(RootMask[RootIdx]);
22038 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22039 int OpIdx = RootMaskedIdx / OpRatio;
22040 if (OpMask[OpIdx] < 0) {
22041 // The incoming lanes are zero or undef, it doesn't matter which ones we
22043 Mask.push_back(OpMask[OpIdx]);
22047 // Ok, we have non-zero lanes, map them through.
22048 Mask.push_back(OpMask[OpIdx] * OpRatio +
22049 RootMaskedIdx % OpRatio);
22052 // See if we can recurse into the operand to combine more things.
22053 switch (Op.getOpcode()) {
22054 case X86ISD::PSHUFB:
22056 case X86ISD::PSHUFD:
22057 case X86ISD::PSHUFHW:
22058 case X86ISD::PSHUFLW:
22059 if (Op.getOperand(0).hasOneUse() &&
22060 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22061 HasPSHUFB, DAG, DCI, Subtarget))
22065 case X86ISD::UNPCKL:
22066 case X86ISD::UNPCKH:
22067 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22068 // We can't check for single use, we have to check that this shuffle is the only user.
22069 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22070 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22071 HasPSHUFB, DAG, DCI, Subtarget))
22076 // Minor canonicalization of the accumulated shuffle mask to make it easier
22077 // to match below. All this does is detect masks with squential pairs of
22078 // elements, and shrink them to the half-width mask. It does this in a loop
22079 // so it will reduce the size of the mask to the minimal width mask which
22080 // performs an equivalent shuffle.
22081 SmallVector<int, 16> WidenedMask;
22082 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22083 Mask = std::move(WidenedMask);
22084 WidenedMask.clear();
22087 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22091 /// \brief Get the PSHUF-style mask from PSHUF node.
22093 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22094 /// PSHUF-style masks that can be reused with such instructions.
22095 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22096 SmallVector<int, 4> Mask;
22098 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22102 switch (N.getOpcode()) {
22103 case X86ISD::PSHUFD:
22105 case X86ISD::PSHUFLW:
22108 case X86ISD::PSHUFHW:
22109 Mask.erase(Mask.begin(), Mask.begin() + 4);
22110 for (int &M : Mask)
22114 llvm_unreachable("No valid shuffle instruction found!");
22118 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22120 /// We walk up the chain and look for a combinable shuffle, skipping over
22121 /// shuffles that we could hoist this shuffle's transformation past without
22122 /// altering anything.
22124 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22126 TargetLowering::DAGCombinerInfo &DCI) {
22127 assert(N.getOpcode() == X86ISD::PSHUFD &&
22128 "Called with something other than an x86 128-bit half shuffle!");
22131 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22132 // of the shuffles in the chain so that we can form a fresh chain to replace
22134 SmallVector<SDValue, 8> Chain;
22135 SDValue V = N.getOperand(0);
22136 for (; V.hasOneUse(); V = V.getOperand(0)) {
22137 switch (V.getOpcode()) {
22139 return SDValue(); // Nothing combined!
22142 // Skip bitcasts as we always know the type for the target specific
22146 case X86ISD::PSHUFD:
22147 // Found another dword shuffle.
22150 case X86ISD::PSHUFLW:
22151 // Check that the low words (being shuffled) are the identity in the
22152 // dword shuffle, and the high words are self-contained.
22153 if (Mask[0] != 0 || Mask[1] != 1 ||
22154 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22157 Chain.push_back(V);
22160 case X86ISD::PSHUFHW:
22161 // Check that the high words (being shuffled) are the identity in the
22162 // dword shuffle, and the low words are self-contained.
22163 if (Mask[2] != 2 || Mask[3] != 3 ||
22164 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22167 Chain.push_back(V);
22170 case X86ISD::UNPCKL:
22171 case X86ISD::UNPCKH:
22172 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22173 // shuffle into a preceding word shuffle.
22174 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22177 // Search for a half-shuffle which we can combine with.
22178 unsigned CombineOp =
22179 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22180 if (V.getOperand(0) != V.getOperand(1) ||
22181 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22183 Chain.push_back(V);
22184 V = V.getOperand(0);
22186 switch (V.getOpcode()) {
22188 return SDValue(); // Nothing to combine.
22190 case X86ISD::PSHUFLW:
22191 case X86ISD::PSHUFHW:
22192 if (V.getOpcode() == CombineOp)
22195 Chain.push_back(V);
22199 V = V.getOperand(0);
22203 } while (V.hasOneUse());
22206 // Break out of the loop if we break out of the switch.
22210 if (!V.hasOneUse())
22211 // We fell out of the loop without finding a viable combining instruction.
22214 // Merge this node's mask and our incoming mask.
22215 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22216 for (int &M : Mask)
22218 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22219 getV4X86ShuffleImm8ForMask(Mask, DAG));
22221 // Rebuild the chain around this new shuffle.
22222 while (!Chain.empty()) {
22223 SDValue W = Chain.pop_back_val();
22225 if (V.getValueType() != W.getOperand(0).getValueType())
22226 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22228 switch (W.getOpcode()) {
22230 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22232 case X86ISD::UNPCKL:
22233 case X86ISD::UNPCKH:
22234 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22237 case X86ISD::PSHUFD:
22238 case X86ISD::PSHUFLW:
22239 case X86ISD::PSHUFHW:
22240 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22244 if (V.getValueType() != N.getValueType())
22245 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22247 // Return the new chain to replace N.
22251 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22253 /// We walk up the chain, skipping shuffles of the other half and looking
22254 /// through shuffles which switch halves trying to find a shuffle of the same
22255 /// pair of dwords.
22256 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22258 TargetLowering::DAGCombinerInfo &DCI) {
22260 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22261 "Called with something other than an x86 128-bit half shuffle!");
22263 unsigned CombineOpcode = N.getOpcode();
22265 // Walk up a single-use chain looking for a combinable shuffle.
22266 SDValue V = N.getOperand(0);
22267 for (; V.hasOneUse(); V = V.getOperand(0)) {
22268 switch (V.getOpcode()) {
22270 return false; // Nothing combined!
22273 // Skip bitcasts as we always know the type for the target specific
22277 case X86ISD::PSHUFLW:
22278 case X86ISD::PSHUFHW:
22279 if (V.getOpcode() == CombineOpcode)
22282 // Other-half shuffles are no-ops.
22285 // Break out of the loop if we break out of the switch.
22289 if (!V.hasOneUse())
22290 // We fell out of the loop without finding a viable combining instruction.
22293 // Combine away the bottom node as its shuffle will be accumulated into
22294 // a preceding shuffle.
22295 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22297 // Record the old value.
22300 // Merge this node's mask and our incoming mask (adjusted to account for all
22301 // the pshufd instructions encountered).
22302 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22303 for (int &M : Mask)
22305 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22306 getV4X86ShuffleImm8ForMask(Mask, DAG));
22308 // Check that the shuffles didn't cancel each other out. If not, we need to
22309 // combine to the new one.
22311 // Replace the combinable shuffle with the combined one, updating all users
22312 // so that we re-evaluate the chain here.
22313 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22318 /// \brief Try to combine x86 target specific shuffles.
22319 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22320 TargetLowering::DAGCombinerInfo &DCI,
22321 const X86Subtarget *Subtarget) {
22323 MVT VT = N.getSimpleValueType();
22324 SmallVector<int, 4> Mask;
22326 switch (N.getOpcode()) {
22327 case X86ISD::PSHUFD:
22328 case X86ISD::PSHUFLW:
22329 case X86ISD::PSHUFHW:
22330 Mask = getPSHUFShuffleMask(N);
22331 assert(Mask.size() == 4);
22337 // Nuke no-op shuffles that show up after combining.
22338 if (isNoopShuffleMask(Mask))
22339 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22341 // Look for simplifications involving one or two shuffle instructions.
22342 SDValue V = N.getOperand(0);
22343 switch (N.getOpcode()) {
22346 case X86ISD::PSHUFLW:
22347 case X86ISD::PSHUFHW:
22348 assert(VT == MVT::v8i16);
22351 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22352 return SDValue(); // We combined away this shuffle, so we're done.
22354 // See if this reduces to a PSHUFD which is no more expensive and can
22355 // combine with more operations. Note that it has to at least flip the
22356 // dwords as otherwise it would have been removed as a no-op.
22357 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22358 int DMask[] = {0, 1, 2, 3};
22359 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22360 DMask[DOffset + 0] = DOffset + 1;
22361 DMask[DOffset + 1] = DOffset + 0;
22362 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22363 DCI.AddToWorklist(V.getNode());
22364 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22365 getV4X86ShuffleImm8ForMask(DMask, DAG));
22366 DCI.AddToWorklist(V.getNode());
22367 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22370 // Look for shuffle patterns which can be implemented as a single unpack.
22371 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22372 // only works when we have a PSHUFD followed by two half-shuffles.
22373 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22374 (V.getOpcode() == X86ISD::PSHUFLW ||
22375 V.getOpcode() == X86ISD::PSHUFHW) &&
22376 V.getOpcode() != N.getOpcode() &&
22378 SDValue D = V.getOperand(0);
22379 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22380 D = D.getOperand(0);
22381 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22382 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22383 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22384 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22385 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22387 for (int i = 0; i < 4; ++i) {
22388 WordMask[i + NOffset] = Mask[i] + NOffset;
22389 WordMask[i + VOffset] = VMask[i] + VOffset;
22391 // Map the word mask through the DWord mask.
22393 for (int i = 0; i < 8; ++i)
22394 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22395 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22396 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22397 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22398 std::begin(UnpackLoMask)) ||
22399 std::equal(std::begin(MappedMask), std::end(MappedMask),
22400 std::begin(UnpackHiMask))) {
22401 // We can replace all three shuffles with an unpack.
22402 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22403 DCI.AddToWorklist(V.getNode());
22404 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22406 DL, MVT::v8i16, V, V);
22413 case X86ISD::PSHUFD:
22414 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22423 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22425 /// We combine this directly on the abstract vector shuffle nodes so it is
22426 /// easier to generically match. We also insert dummy vector shuffle nodes for
22427 /// the operands which explicitly discard the lanes which are unused by this
22428 /// operation to try to flow through the rest of the combiner the fact that
22429 /// they're unused.
22430 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22432 EVT VT = N->getValueType(0);
22434 // We only handle target-independent shuffles.
22435 // FIXME: It would be easy and harmless to use the target shuffle mask
22436 // extraction tool to support more.
22437 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22440 auto *SVN = cast<ShuffleVectorSDNode>(N);
22441 ArrayRef<int> Mask = SVN->getMask();
22442 SDValue V1 = N->getOperand(0);
22443 SDValue V2 = N->getOperand(1);
22445 // We require the first shuffle operand to be the SUB node, and the second to
22446 // be the ADD node.
22447 // FIXME: We should support the commuted patterns.
22448 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22451 // If there are other uses of these operations we can't fold them.
22452 if (!V1->hasOneUse() || !V2->hasOneUse())
22455 // Ensure that both operations have the same operands. Note that we can
22456 // commute the FADD operands.
22457 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22458 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22459 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22462 // We're looking for blends between FADD and FSUB nodes. We insist on these
22463 // nodes being lined up in a specific expected pattern.
22464 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22465 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22466 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22469 // Only specific types are legal at this point, assert so we notice if and
22470 // when these change.
22471 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22472 VT == MVT::v4f64) &&
22473 "Unknown vector type encountered!");
22475 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22478 /// PerformShuffleCombine - Performs several different shuffle combines.
22479 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22480 TargetLowering::DAGCombinerInfo &DCI,
22481 const X86Subtarget *Subtarget) {
22483 SDValue N0 = N->getOperand(0);
22484 SDValue N1 = N->getOperand(1);
22485 EVT VT = N->getValueType(0);
22487 // Don't create instructions with illegal types after legalize types has run.
22488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22489 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22492 // If we have legalized the vector types, look for blends of FADD and FSUB
22493 // nodes that we can fuse into an ADDSUB node.
22494 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22495 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22498 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22499 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22500 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22501 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22503 // During Type Legalization, when promoting illegal vector types,
22504 // the backend might introduce new shuffle dag nodes and bitcasts.
22506 // This code performs the following transformation:
22507 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22508 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22510 // We do this only if both the bitcast and the BINOP dag nodes have
22511 // one use. Also, perform this transformation only if the new binary
22512 // operation is legal. This is to avoid introducing dag nodes that
22513 // potentially need to be further expanded (or custom lowered) into a
22514 // less optimal sequence of dag nodes.
22515 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22516 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22517 N0.getOpcode() == ISD::BITCAST) {
22518 SDValue BC0 = N0.getOperand(0);
22519 EVT SVT = BC0.getValueType();
22520 unsigned Opcode = BC0.getOpcode();
22521 unsigned NumElts = VT.getVectorNumElements();
22523 if (BC0.hasOneUse() && SVT.isVector() &&
22524 SVT.getVectorNumElements() * 2 == NumElts &&
22525 TLI.isOperationLegal(Opcode, VT)) {
22526 bool CanFold = false;
22538 unsigned SVTNumElts = SVT.getVectorNumElements();
22539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22540 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22541 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22542 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22543 CanFold = SVOp->getMaskElt(i) < 0;
22546 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22547 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22548 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22549 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22554 // Only handle 128 wide vector from here on.
22555 if (!VT.is128BitVector())
22558 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22559 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22560 // consecutive, non-overlapping, and in the right order.
22561 SmallVector<SDValue, 16> Elts;
22562 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22563 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22565 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22569 if (isTargetShuffle(N->getOpcode())) {
22571 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22572 if (Shuffle.getNode())
22575 // Try recursively combining arbitrary sequences of x86 shuffle
22576 // instructions into higher-order shuffles. We do this after combining
22577 // specific PSHUF instruction sequences into their minimal form so that we
22578 // can evaluate how many specialized shuffle instructions are involved in
22579 // a particular chain.
22580 SmallVector<int, 1> NonceMask; // Just a placeholder.
22581 NonceMask.push_back(0);
22582 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22583 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22585 return SDValue(); // This routine will use CombineTo to replace N.
22591 /// PerformTruncateCombine - Converts truncate operation to
22592 /// a sequence of vector shuffle operations.
22593 /// It is possible when we truncate 256-bit vector to 128-bit vector
22594 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22595 TargetLowering::DAGCombinerInfo &DCI,
22596 const X86Subtarget *Subtarget) {
22600 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22601 /// specific shuffle of a load can be folded into a single element load.
22602 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22603 /// shuffles have been custom lowered so we need to handle those here.
22604 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22605 TargetLowering::DAGCombinerInfo &DCI) {
22606 if (DCI.isBeforeLegalizeOps())
22609 SDValue InVec = N->getOperand(0);
22610 SDValue EltNo = N->getOperand(1);
22612 if (!isa<ConstantSDNode>(EltNo))
22615 EVT OriginalVT = InVec.getValueType();
22617 if (InVec.getOpcode() == ISD::BITCAST) {
22618 // Don't duplicate a load with other uses.
22619 if (!InVec.hasOneUse())
22621 EVT BCVT = InVec.getOperand(0).getValueType();
22622 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22624 InVec = InVec.getOperand(0);
22627 EVT CurrentVT = InVec.getValueType();
22629 if (!isTargetShuffle(InVec.getOpcode()))
22632 // Don't duplicate a load with other uses.
22633 if (!InVec.hasOneUse())
22636 SmallVector<int, 16> ShuffleMask;
22638 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22639 ShuffleMask, UnaryShuffle))
22642 // Select the input vector, guarding against out of range extract vector.
22643 unsigned NumElems = CurrentVT.getVectorNumElements();
22644 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22645 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22646 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22647 : InVec.getOperand(1);
22649 // If inputs to shuffle are the same for both ops, then allow 2 uses
22650 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22652 if (LdNode.getOpcode() == ISD::BITCAST) {
22653 // Don't duplicate a load with other uses.
22654 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22657 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22658 LdNode = LdNode.getOperand(0);
22661 if (!ISD::isNormalLoad(LdNode.getNode()))
22664 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22666 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22669 EVT EltVT = N->getValueType(0);
22670 // If there's a bitcast before the shuffle, check if the load type and
22671 // alignment is valid.
22672 unsigned Align = LN0->getAlignment();
22673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22674 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22675 EltVT.getTypeForEVT(*DAG.getContext()));
22677 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22680 // All checks match so transform back to vector_shuffle so that DAG combiner
22681 // can finish the job
22684 // Create shuffle node taking into account the case that its a unary shuffle
22685 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22686 : InVec.getOperand(1);
22687 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22688 InVec.getOperand(0), Shuffle,
22690 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22691 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22695 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22696 /// generation and convert it from being a bunch of shuffles and extracts
22697 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22698 /// storing the value and loading scalars back, while for x64 we should
22699 /// use 64-bit extracts and shifts.
22700 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22701 TargetLowering::DAGCombinerInfo &DCI) {
22702 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22703 if (NewOp.getNode())
22706 SDValue InputVector = N->getOperand(0);
22708 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22709 // from mmx to v2i32 has a single usage.
22710 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22711 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22712 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22713 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22714 N->getValueType(0),
22715 InputVector.getNode()->getOperand(0));
22717 // Only operate on vectors of 4 elements, where the alternative shuffling
22718 // gets to be more expensive.
22719 if (InputVector.getValueType() != MVT::v4i32)
22722 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22723 // single use which is a sign-extend or zero-extend, and all elements are
22725 SmallVector<SDNode *, 4> Uses;
22726 unsigned ExtractedElements = 0;
22727 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22728 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22729 if (UI.getUse().getResNo() != InputVector.getResNo())
22732 SDNode *Extract = *UI;
22733 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22736 if (Extract->getValueType(0) != MVT::i32)
22738 if (!Extract->hasOneUse())
22740 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22741 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22743 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22746 // Record which element was extracted.
22747 ExtractedElements |=
22748 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22750 Uses.push_back(Extract);
22753 // If not all the elements were used, this may not be worthwhile.
22754 if (ExtractedElements != 15)
22757 // Ok, we've now decided to do the transformation.
22758 // If 64-bit shifts are legal, use the extract-shift sequence,
22759 // otherwise bounce the vector off the cache.
22760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22762 SDLoc dl(InputVector);
22764 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22765 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22766 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22767 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22768 DAG.getConstant(0, VecIdxTy));
22769 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22770 DAG.getConstant(1, VecIdxTy));
22772 SDValue ShAmt = DAG.getConstant(32,
22773 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22774 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22775 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22776 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22777 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22778 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22779 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22781 // Store the value to a temporary stack slot.
22782 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22783 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22784 MachinePointerInfo(), false, false, 0);
22786 EVT ElementType = InputVector.getValueType().getVectorElementType();
22787 unsigned EltSize = ElementType.getSizeInBits() / 8;
22789 // Replace each use (extract) with a load of the appropriate element.
22790 for (unsigned i = 0; i < 4; ++i) {
22791 uint64_t Offset = EltSize * i;
22792 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22794 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22795 StackPtr, OffsetVal);
22797 // Load the scalar.
22798 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22799 ScalarAddr, MachinePointerInfo(),
22800 false, false, false, 0);
22805 // Replace the extracts
22806 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22807 UE = Uses.end(); UI != UE; ++UI) {
22808 SDNode *Extract = *UI;
22810 SDValue Idx = Extract->getOperand(1);
22811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22812 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22815 // The replacement was made in place; don't return anything.
22819 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22820 static std::pair<unsigned, bool>
22821 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22822 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22823 if (!VT.isVector())
22824 return std::make_pair(0, false);
22826 bool NeedSplit = false;
22827 switch (VT.getSimpleVT().SimpleTy) {
22828 default: return std::make_pair(0, false);
22831 if (!Subtarget->hasVLX())
22832 return std::make_pair(0, false);
22836 if (!Subtarget->hasBWI())
22837 return std::make_pair(0, false);
22841 if (!Subtarget->hasAVX512())
22842 return std::make_pair(0, false);
22847 if (!Subtarget->hasAVX2())
22849 if (!Subtarget->hasAVX())
22850 return std::make_pair(0, false);
22855 if (!Subtarget->hasSSE2())
22856 return std::make_pair(0, false);
22859 // SSE2 has only a small subset of the operations.
22860 bool hasUnsigned = Subtarget->hasSSE41() ||
22861 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22862 bool hasSigned = Subtarget->hasSSE41() ||
22863 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22865 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22868 // Check for x CC y ? x : y.
22869 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22870 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22875 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22878 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22881 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22884 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22886 // Check for x CC y ? y : x -- a min/max with reversed arms.
22887 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22888 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22893 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22896 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22899 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22902 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22906 return std::make_pair(Opc, NeedSplit);
22910 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22911 const X86Subtarget *Subtarget) {
22913 SDValue Cond = N->getOperand(0);
22914 SDValue LHS = N->getOperand(1);
22915 SDValue RHS = N->getOperand(2);
22917 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22918 SDValue CondSrc = Cond->getOperand(0);
22919 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22920 Cond = CondSrc->getOperand(0);
22923 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22926 // A vselect where all conditions and data are constants can be optimized into
22927 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22928 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22929 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22932 unsigned MaskValue = 0;
22933 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22936 MVT VT = N->getSimpleValueType(0);
22937 unsigned NumElems = VT.getVectorNumElements();
22938 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22939 for (unsigned i = 0; i < NumElems; ++i) {
22940 // Be sure we emit undef where we can.
22941 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22942 ShuffleMask[i] = -1;
22944 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22948 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22950 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22953 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22955 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22956 TargetLowering::DAGCombinerInfo &DCI,
22957 const X86Subtarget *Subtarget) {
22959 SDValue Cond = N->getOperand(0);
22960 // Get the LHS/RHS of the select.
22961 SDValue LHS = N->getOperand(1);
22962 SDValue RHS = N->getOperand(2);
22963 EVT VT = LHS.getValueType();
22964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22966 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22967 // instructions match the semantics of the common C idiom x<y?x:y but not
22968 // x<=y?x:y, because of how they handle negative zero (which can be
22969 // ignored in unsafe-math mode).
22970 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22971 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22972 (Subtarget->hasSSE2() ||
22973 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22974 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22976 unsigned Opcode = 0;
22977 // Check for x CC y ? x : y.
22978 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22979 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22983 // Converting this to a min would handle NaNs incorrectly, and swapping
22984 // the operands would cause it to handle comparisons between positive
22985 // and negative zero incorrectly.
22986 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22987 if (!DAG.getTarget().Options.UnsafeFPMath &&
22988 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22990 std::swap(LHS, RHS);
22992 Opcode = X86ISD::FMIN;
22995 // Converting this to a min would handle comparisons between positive
22996 // and negative zero incorrectly.
22997 if (!DAG.getTarget().Options.UnsafeFPMath &&
22998 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23000 Opcode = X86ISD::FMIN;
23003 // Converting this to a min would handle both negative zeros and NaNs
23004 // incorrectly, but we can swap the operands to fix both.
23005 std::swap(LHS, RHS);
23009 Opcode = X86ISD::FMIN;
23013 // Converting this to a max would handle comparisons between positive
23014 // and negative zero incorrectly.
23015 if (!DAG.getTarget().Options.UnsafeFPMath &&
23016 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23018 Opcode = X86ISD::FMAX;
23021 // Converting this to a max would handle NaNs incorrectly, and swapping
23022 // the operands would cause it to handle comparisons between positive
23023 // and negative zero incorrectly.
23024 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23025 if (!DAG.getTarget().Options.UnsafeFPMath &&
23026 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23028 std::swap(LHS, RHS);
23030 Opcode = X86ISD::FMAX;
23033 // Converting this to a max would handle both negative zeros and NaNs
23034 // incorrectly, but we can swap the operands to fix both.
23035 std::swap(LHS, RHS);
23039 Opcode = X86ISD::FMAX;
23042 // Check for x CC y ? y : x -- a min/max with reversed arms.
23043 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23044 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23048 // Converting this to a min would handle comparisons between positive
23049 // and negative zero incorrectly, and swapping the operands would
23050 // cause it to handle NaNs incorrectly.
23051 if (!DAG.getTarget().Options.UnsafeFPMath &&
23052 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23053 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23055 std::swap(LHS, RHS);
23057 Opcode = X86ISD::FMIN;
23060 // Converting this to a min would handle NaNs incorrectly.
23061 if (!DAG.getTarget().Options.UnsafeFPMath &&
23062 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23064 Opcode = X86ISD::FMIN;
23067 // Converting this to a min would handle both negative zeros and NaNs
23068 // incorrectly, but we can swap the operands to fix both.
23069 std::swap(LHS, RHS);
23073 Opcode = X86ISD::FMIN;
23077 // Converting this to a max would handle NaNs incorrectly.
23078 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23080 Opcode = X86ISD::FMAX;
23083 // Converting this to a max would handle comparisons between positive
23084 // and negative zero incorrectly, and swapping the operands would
23085 // cause it to handle NaNs incorrectly.
23086 if (!DAG.getTarget().Options.UnsafeFPMath &&
23087 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23088 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23090 std::swap(LHS, RHS);
23092 Opcode = X86ISD::FMAX;
23095 // Converting this to a max would handle both negative zeros and NaNs
23096 // incorrectly, but we can swap the operands to fix both.
23097 std::swap(LHS, RHS);
23101 Opcode = X86ISD::FMAX;
23107 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23110 EVT CondVT = Cond.getValueType();
23111 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23112 CondVT.getVectorElementType() == MVT::i1) {
23113 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23114 // lowering on KNL. In this case we convert it to
23115 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23116 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23117 // Since SKX these selects have a proper lowering.
23118 EVT OpVT = LHS.getValueType();
23119 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23120 (OpVT.getVectorElementType() == MVT::i8 ||
23121 OpVT.getVectorElementType() == MVT::i16) &&
23122 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23123 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23124 DCI.AddToWorklist(Cond.getNode());
23125 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23128 // If this is a select between two integer constants, try to do some
23130 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23131 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23132 // Don't do this for crazy integer types.
23133 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23134 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23135 // so that TrueC (the true value) is larger than FalseC.
23136 bool NeedsCondInvert = false;
23138 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23139 // Efficiently invertible.
23140 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23141 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23142 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23143 NeedsCondInvert = true;
23144 std::swap(TrueC, FalseC);
23147 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23148 if (FalseC->getAPIntValue() == 0 &&
23149 TrueC->getAPIntValue().isPowerOf2()) {
23150 if (NeedsCondInvert) // Invert the condition if needed.
23151 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23152 DAG.getConstant(1, Cond.getValueType()));
23154 // Zero extend the condition if needed.
23155 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23157 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23158 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23159 DAG.getConstant(ShAmt, MVT::i8));
23162 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23163 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23164 if (NeedsCondInvert) // Invert the condition if needed.
23165 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23166 DAG.getConstant(1, Cond.getValueType()));
23168 // Zero extend the condition if needed.
23169 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23170 FalseC->getValueType(0), Cond);
23171 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23172 SDValue(FalseC, 0));
23175 // Optimize cases that will turn into an LEA instruction. This requires
23176 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23177 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23178 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23179 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23181 bool isFastMultiplier = false;
23183 switch ((unsigned char)Diff) {
23185 case 1: // result = add base, cond
23186 case 2: // result = lea base( , cond*2)
23187 case 3: // result = lea base(cond, cond*2)
23188 case 4: // result = lea base( , cond*4)
23189 case 5: // result = lea base(cond, cond*4)
23190 case 8: // result = lea base( , cond*8)
23191 case 9: // result = lea base(cond, cond*8)
23192 isFastMultiplier = true;
23197 if (isFastMultiplier) {
23198 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23199 if (NeedsCondInvert) // Invert the condition if needed.
23200 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23201 DAG.getConstant(1, Cond.getValueType()));
23203 // Zero extend the condition if needed.
23204 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23206 // Scale the condition by the difference.
23208 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23209 DAG.getConstant(Diff, Cond.getValueType()));
23211 // Add the base if non-zero.
23212 if (FalseC->getAPIntValue() != 0)
23213 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23214 SDValue(FalseC, 0));
23221 // Canonicalize max and min:
23222 // (x > y) ? x : y -> (x >= y) ? x : y
23223 // (x < y) ? x : y -> (x <= y) ? x : y
23224 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23225 // the need for an extra compare
23226 // against zero. e.g.
23227 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23229 // testl %edi, %edi
23231 // cmovgl %edi, %eax
23235 // cmovsl %eax, %edi
23236 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23237 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23238 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23239 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23244 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23245 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23246 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23247 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23252 // Early exit check
23253 if (!TLI.isTypeLegal(VT))
23256 // Match VSELECTs into subs with unsigned saturation.
23257 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23258 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23259 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23260 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23261 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23263 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23264 // left side invert the predicate to simplify logic below.
23266 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23268 CC = ISD::getSetCCInverse(CC, true);
23269 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23273 if (Other.getNode() && Other->getNumOperands() == 2 &&
23274 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23275 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23276 SDValue CondRHS = Cond->getOperand(1);
23278 // Look for a general sub with unsigned saturation first.
23279 // x >= y ? x-y : 0 --> subus x, y
23280 // x > y ? x-y : 0 --> subus x, y
23281 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23282 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23283 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23285 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23286 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23287 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23288 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23289 // If the RHS is a constant we have to reverse the const
23290 // canonicalization.
23291 // x > C-1 ? x+-C : 0 --> subus x, C
23292 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23293 CondRHSConst->getAPIntValue() ==
23294 (-OpRHSConst->getAPIntValue() - 1))
23295 return DAG.getNode(
23296 X86ISD::SUBUS, DL, VT, OpLHS,
23297 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23299 // Another special case: If C was a sign bit, the sub has been
23300 // canonicalized into a xor.
23301 // FIXME: Would it be better to use computeKnownBits to determine
23302 // whether it's safe to decanonicalize the xor?
23303 // x s< 0 ? x^C : 0 --> subus x, C
23304 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23305 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23306 OpRHSConst->getAPIntValue().isSignBit())
23307 // Note that we have to rebuild the RHS constant here to ensure we
23308 // don't rely on particular values of undef lanes.
23309 return DAG.getNode(
23310 X86ISD::SUBUS, DL, VT, OpLHS,
23311 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23316 // Try to match a min/max vector operation.
23317 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23318 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23319 unsigned Opc = ret.first;
23320 bool NeedSplit = ret.second;
23322 if (Opc && NeedSplit) {
23323 unsigned NumElems = VT.getVectorNumElements();
23324 // Extract the LHS vectors
23325 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23326 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23328 // Extract the RHS vectors
23329 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23330 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23332 // Create min/max for each subvector
23333 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23334 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23336 // Merge the result
23337 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23339 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23342 // Simplify vector selection if condition value type matches vselect
23344 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23345 assert(Cond.getValueType().isVector() &&
23346 "vector select expects a vector selector!");
23348 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23349 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23351 // Try invert the condition if true value is not all 1s and false value
23353 if (!TValIsAllOnes && !FValIsAllZeros &&
23354 // Check if the selector will be produced by CMPP*/PCMP*
23355 Cond.getOpcode() == ISD::SETCC &&
23356 // Check if SETCC has already been promoted
23357 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23358 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23359 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23361 if (TValIsAllZeros || FValIsAllOnes) {
23362 SDValue CC = Cond.getOperand(2);
23363 ISD::CondCode NewCC =
23364 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23365 Cond.getOperand(0).getValueType().isInteger());
23366 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23367 std::swap(LHS, RHS);
23368 TValIsAllOnes = FValIsAllOnes;
23369 FValIsAllZeros = TValIsAllZeros;
23373 if (TValIsAllOnes || FValIsAllZeros) {
23376 if (TValIsAllOnes && FValIsAllZeros)
23378 else if (TValIsAllOnes)
23379 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23380 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23381 else if (FValIsAllZeros)
23382 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23383 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23385 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23389 // If we know that this node is legal then we know that it is going to be
23390 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23391 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23392 // to simplify previous instructions.
23393 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23394 !DCI.isBeforeLegalize() &&
23395 // We explicitly check against v8i16 and v16i16 because, although
23396 // they're marked as Custom, they might only be legal when Cond is a
23397 // build_vector of constants. This will be taken care in a later
23399 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23400 VT != MVT::v8i16) &&
23401 // Don't optimize vector of constants. Those are handled by
23402 // the generic code and all the bits must be properly set for
23403 // the generic optimizer.
23404 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23405 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23407 // Don't optimize vector selects that map to mask-registers.
23411 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23412 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23414 APInt KnownZero, KnownOne;
23415 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23416 DCI.isBeforeLegalizeOps());
23417 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23418 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23420 // If we changed the computation somewhere in the DAG, this change
23421 // will affect all users of Cond.
23422 // Make sure it is fine and update all the nodes so that we do not
23423 // use the generic VSELECT anymore. Otherwise, we may perform
23424 // wrong optimizations as we messed up with the actual expectation
23425 // for the vector boolean values.
23426 if (Cond != TLO.Old) {
23427 // Check all uses of that condition operand to check whether it will be
23428 // consumed by non-BLEND instructions, which may depend on all bits are
23430 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23432 if (I->getOpcode() != ISD::VSELECT)
23433 // TODO: Add other opcodes eventually lowered into BLEND.
23436 // Update all the users of the condition, before committing the change,
23437 // so that the VSELECT optimizations that expect the correct vector
23438 // boolean value will not be triggered.
23439 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23441 DAG.ReplaceAllUsesOfValueWith(
23443 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23444 Cond, I->getOperand(1), I->getOperand(2)));
23445 DCI.CommitTargetLoweringOpt(TLO);
23448 // At this point, only Cond is changed. Change the condition
23449 // just for N to keep the opportunity to optimize all other
23450 // users their own way.
23451 DAG.ReplaceAllUsesOfValueWith(
23453 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23454 TLO.New, N->getOperand(1), N->getOperand(2)));
23459 // We should generate an X86ISD::BLENDI from a vselect if its argument
23460 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23461 // constants. This specific pattern gets generated when we split a
23462 // selector for a 512 bit vector in a machine without AVX512 (but with
23463 // 256-bit vectors), during legalization:
23465 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23467 // Iff we find this pattern and the build_vectors are built from
23468 // constants, we translate the vselect into a shuffle_vector that we
23469 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23470 if ((N->getOpcode() == ISD::VSELECT ||
23471 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23472 !DCI.isBeforeLegalize()) {
23473 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23474 if (Shuffle.getNode())
23481 // Check whether a boolean test is testing a boolean value generated by
23482 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23485 // Simplify the following patterns:
23486 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23487 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23488 // to (Op EFLAGS Cond)
23490 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23491 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23492 // to (Op EFLAGS !Cond)
23494 // where Op could be BRCOND or CMOV.
23496 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23497 // Quit if not CMP and SUB with its value result used.
23498 if (Cmp.getOpcode() != X86ISD::CMP &&
23499 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23502 // Quit if not used as a boolean value.
23503 if (CC != X86::COND_E && CC != X86::COND_NE)
23506 // Check CMP operands. One of them should be 0 or 1 and the other should be
23507 // an SetCC or extended from it.
23508 SDValue Op1 = Cmp.getOperand(0);
23509 SDValue Op2 = Cmp.getOperand(1);
23512 const ConstantSDNode* C = nullptr;
23513 bool needOppositeCond = (CC == X86::COND_E);
23514 bool checkAgainstTrue = false; // Is it a comparison against 1?
23516 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23518 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23520 else // Quit if all operands are not constants.
23523 if (C->getZExtValue() == 1) {
23524 needOppositeCond = !needOppositeCond;
23525 checkAgainstTrue = true;
23526 } else if (C->getZExtValue() != 0)
23527 // Quit if the constant is neither 0 or 1.
23530 bool truncatedToBoolWithAnd = false;
23531 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23532 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23533 SetCC.getOpcode() == ISD::TRUNCATE ||
23534 SetCC.getOpcode() == ISD::AND) {
23535 if (SetCC.getOpcode() == ISD::AND) {
23537 ConstantSDNode *CS;
23538 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23539 CS->getZExtValue() == 1)
23541 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23542 CS->getZExtValue() == 1)
23546 SetCC = SetCC.getOperand(OpIdx);
23547 truncatedToBoolWithAnd = true;
23549 SetCC = SetCC.getOperand(0);
23552 switch (SetCC.getOpcode()) {
23553 case X86ISD::SETCC_CARRY:
23554 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23555 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23556 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23557 // truncated to i1 using 'and'.
23558 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23560 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23561 "Invalid use of SETCC_CARRY!");
23563 case X86ISD::SETCC:
23564 // Set the condition code or opposite one if necessary.
23565 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23566 if (needOppositeCond)
23567 CC = X86::GetOppositeBranchCondition(CC);
23568 return SetCC.getOperand(1);
23569 case X86ISD::CMOV: {
23570 // Check whether false/true value has canonical one, i.e. 0 or 1.
23571 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23572 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23573 // Quit if true value is not a constant.
23576 // Quit if false value is not a constant.
23578 SDValue Op = SetCC.getOperand(0);
23579 // Skip 'zext' or 'trunc' node.
23580 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23581 Op.getOpcode() == ISD::TRUNCATE)
23582 Op = Op.getOperand(0);
23583 // A special case for rdrand/rdseed, where 0 is set if false cond is
23585 if ((Op.getOpcode() != X86ISD::RDRAND &&
23586 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23589 // Quit if false value is not the constant 0 or 1.
23590 bool FValIsFalse = true;
23591 if (FVal && FVal->getZExtValue() != 0) {
23592 if (FVal->getZExtValue() != 1)
23594 // If FVal is 1, opposite cond is needed.
23595 needOppositeCond = !needOppositeCond;
23596 FValIsFalse = false;
23598 // Quit if TVal is not the constant opposite of FVal.
23599 if (FValIsFalse && TVal->getZExtValue() != 1)
23601 if (!FValIsFalse && TVal->getZExtValue() != 0)
23603 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23604 if (needOppositeCond)
23605 CC = X86::GetOppositeBranchCondition(CC);
23606 return SetCC.getOperand(3);
23613 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23614 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23615 TargetLowering::DAGCombinerInfo &DCI,
23616 const X86Subtarget *Subtarget) {
23619 // If the flag operand isn't dead, don't touch this CMOV.
23620 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23623 SDValue FalseOp = N->getOperand(0);
23624 SDValue TrueOp = N->getOperand(1);
23625 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23626 SDValue Cond = N->getOperand(3);
23628 if (CC == X86::COND_E || CC == X86::COND_NE) {
23629 switch (Cond.getOpcode()) {
23633 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23634 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23635 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23641 Flags = checkBoolTestSetCCCombine(Cond, CC);
23642 if (Flags.getNode() &&
23643 // Extra check as FCMOV only supports a subset of X86 cond.
23644 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23645 SDValue Ops[] = { FalseOp, TrueOp,
23646 DAG.getConstant(CC, MVT::i8), Flags };
23647 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23650 // If this is a select between two integer constants, try to do some
23651 // optimizations. Note that the operands are ordered the opposite of SELECT
23653 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23654 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23655 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23656 // larger than FalseC (the false value).
23657 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23658 CC = X86::GetOppositeBranchCondition(CC);
23659 std::swap(TrueC, FalseC);
23660 std::swap(TrueOp, FalseOp);
23663 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23664 // This is efficient for any integer data type (including i8/i16) and
23666 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23667 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23668 DAG.getConstant(CC, MVT::i8), Cond);
23670 // Zero extend the condition if needed.
23671 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23673 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23674 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23675 DAG.getConstant(ShAmt, MVT::i8));
23676 if (N->getNumValues() == 2) // Dead flag value?
23677 return DCI.CombineTo(N, Cond, SDValue());
23681 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23682 // for any integer data type, including i8/i16.
23683 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23684 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23685 DAG.getConstant(CC, MVT::i8), Cond);
23687 // Zero extend the condition if needed.
23688 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23689 FalseC->getValueType(0), Cond);
23690 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23691 SDValue(FalseC, 0));
23693 if (N->getNumValues() == 2) // Dead flag value?
23694 return DCI.CombineTo(N, Cond, SDValue());
23698 // Optimize cases that will turn into an LEA instruction. This requires
23699 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23700 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23701 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23702 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23704 bool isFastMultiplier = false;
23706 switch ((unsigned char)Diff) {
23708 case 1: // result = add base, cond
23709 case 2: // result = lea base( , cond*2)
23710 case 3: // result = lea base(cond, cond*2)
23711 case 4: // result = lea base( , cond*4)
23712 case 5: // result = lea base(cond, cond*4)
23713 case 8: // result = lea base( , cond*8)
23714 case 9: // result = lea base(cond, cond*8)
23715 isFastMultiplier = true;
23720 if (isFastMultiplier) {
23721 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23722 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23723 DAG.getConstant(CC, MVT::i8), Cond);
23724 // Zero extend the condition if needed.
23725 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23727 // Scale the condition by the difference.
23729 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23730 DAG.getConstant(Diff, Cond.getValueType()));
23732 // Add the base if non-zero.
23733 if (FalseC->getAPIntValue() != 0)
23734 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23735 SDValue(FalseC, 0));
23736 if (N->getNumValues() == 2) // Dead flag value?
23737 return DCI.CombineTo(N, Cond, SDValue());
23744 // Handle these cases:
23745 // (select (x != c), e, c) -> select (x != c), e, x),
23746 // (select (x == c), c, e) -> select (x == c), x, e)
23747 // where the c is an integer constant, and the "select" is the combination
23748 // of CMOV and CMP.
23750 // The rationale for this change is that the conditional-move from a constant
23751 // needs two instructions, however, conditional-move from a register needs
23752 // only one instruction.
23754 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23755 // some instruction-combining opportunities. This opt needs to be
23756 // postponed as late as possible.
23758 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23759 // the DCI.xxxx conditions are provided to postpone the optimization as
23760 // late as possible.
23762 ConstantSDNode *CmpAgainst = nullptr;
23763 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23764 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23765 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23767 if (CC == X86::COND_NE &&
23768 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23769 CC = X86::GetOppositeBranchCondition(CC);
23770 std::swap(TrueOp, FalseOp);
23773 if (CC == X86::COND_E &&
23774 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23775 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23776 DAG.getConstant(CC, MVT::i8), Cond };
23777 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23785 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23786 const X86Subtarget *Subtarget) {
23787 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23789 default: return SDValue();
23790 // SSE/AVX/AVX2 blend intrinsics.
23791 case Intrinsic::x86_avx2_pblendvb:
23792 case Intrinsic::x86_avx2_pblendw:
23793 case Intrinsic::x86_avx2_pblendd_128:
23794 case Intrinsic::x86_avx2_pblendd_256:
23795 // Don't try to simplify this intrinsic if we don't have AVX2.
23796 if (!Subtarget->hasAVX2())
23799 case Intrinsic::x86_avx_blend_pd_256:
23800 case Intrinsic::x86_avx_blend_ps_256:
23801 case Intrinsic::x86_avx_blendv_pd_256:
23802 case Intrinsic::x86_avx_blendv_ps_256:
23803 // Don't try to simplify this intrinsic if we don't have AVX.
23804 if (!Subtarget->hasAVX())
23807 case Intrinsic::x86_sse41_pblendw:
23808 case Intrinsic::x86_sse41_blendpd:
23809 case Intrinsic::x86_sse41_blendps:
23810 case Intrinsic::x86_sse41_blendvps:
23811 case Intrinsic::x86_sse41_blendvpd:
23812 case Intrinsic::x86_sse41_pblendvb: {
23813 SDValue Op0 = N->getOperand(1);
23814 SDValue Op1 = N->getOperand(2);
23815 SDValue Mask = N->getOperand(3);
23817 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23818 if (!Subtarget->hasSSE41())
23821 // fold (blend A, A, Mask) -> A
23824 // fold (blend A, B, allZeros) -> A
23825 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23827 // fold (blend A, B, allOnes) -> B
23828 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23831 // Simplify the case where the mask is a constant i32 value.
23832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23833 if (C->isNullValue())
23835 if (C->isAllOnesValue())
23842 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23843 case Intrinsic::x86_sse2_psrai_w:
23844 case Intrinsic::x86_sse2_psrai_d:
23845 case Intrinsic::x86_avx2_psrai_w:
23846 case Intrinsic::x86_avx2_psrai_d:
23847 case Intrinsic::x86_sse2_psra_w:
23848 case Intrinsic::x86_sse2_psra_d:
23849 case Intrinsic::x86_avx2_psra_w:
23850 case Intrinsic::x86_avx2_psra_d: {
23851 SDValue Op0 = N->getOperand(1);
23852 SDValue Op1 = N->getOperand(2);
23853 EVT VT = Op0.getValueType();
23854 assert(VT.isVector() && "Expected a vector type!");
23856 if (isa<BuildVectorSDNode>(Op1))
23857 Op1 = Op1.getOperand(0);
23859 if (!isa<ConstantSDNode>(Op1))
23862 EVT SVT = VT.getVectorElementType();
23863 unsigned SVTBits = SVT.getSizeInBits();
23865 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23866 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23867 uint64_t ShAmt = C.getZExtValue();
23869 // Don't try to convert this shift into a ISD::SRA if the shift
23870 // count is bigger than or equal to the element size.
23871 if (ShAmt >= SVTBits)
23874 // Trivial case: if the shift count is zero, then fold this
23875 // into the first operand.
23879 // Replace this packed shift intrinsic with a target independent
23881 SDValue Splat = DAG.getConstant(C, VT);
23882 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23887 /// PerformMulCombine - Optimize a single multiply with constant into two
23888 /// in order to implement it with two cheaper instructions, e.g.
23889 /// LEA + SHL, LEA + LEA.
23890 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23891 TargetLowering::DAGCombinerInfo &DCI) {
23892 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23895 EVT VT = N->getValueType(0);
23896 if (VT != MVT::i64)
23899 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23902 uint64_t MulAmt = C->getZExtValue();
23903 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23906 uint64_t MulAmt1 = 0;
23907 uint64_t MulAmt2 = 0;
23908 if ((MulAmt % 9) == 0) {
23910 MulAmt2 = MulAmt / 9;
23911 } else if ((MulAmt % 5) == 0) {
23913 MulAmt2 = MulAmt / 5;
23914 } else if ((MulAmt % 3) == 0) {
23916 MulAmt2 = MulAmt / 3;
23919 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23922 if (isPowerOf2_64(MulAmt2) &&
23923 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23924 // If second multiplifer is pow2, issue it first. We want the multiply by
23925 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23927 std::swap(MulAmt1, MulAmt2);
23930 if (isPowerOf2_64(MulAmt1))
23931 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23932 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23934 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23935 DAG.getConstant(MulAmt1, VT));
23937 if (isPowerOf2_64(MulAmt2))
23938 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23939 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23941 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23942 DAG.getConstant(MulAmt2, VT));
23944 // Do not add new nodes to DAG combiner worklist.
23945 DCI.CombineTo(N, NewMul, false);
23950 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23951 SDValue N0 = N->getOperand(0);
23952 SDValue N1 = N->getOperand(1);
23953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23954 EVT VT = N0.getValueType();
23956 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23957 // since the result of setcc_c is all zero's or all ones.
23958 if (VT.isInteger() && !VT.isVector() &&
23959 N1C && N0.getOpcode() == ISD::AND &&
23960 N0.getOperand(1).getOpcode() == ISD::Constant) {
23961 SDValue N00 = N0.getOperand(0);
23962 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23963 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23964 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23965 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23966 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23967 APInt ShAmt = N1C->getAPIntValue();
23968 Mask = Mask.shl(ShAmt);
23970 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23971 N00, DAG.getConstant(Mask, VT));
23975 // Hardware support for vector shifts is sparse which makes us scalarize the
23976 // vector operations in many cases. Also, on sandybridge ADD is faster than
23978 // (shl V, 1) -> add V,V
23979 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23980 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23981 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23982 // We shift all of the values by one. In many cases we do not have
23983 // hardware support for this operation. This is better expressed as an ADD
23985 if (N1SplatC->getZExtValue() == 1)
23986 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23992 /// \brief Returns a vector of 0s if the node in input is a vector logical
23993 /// shift by a constant amount which is known to be bigger than or equal
23994 /// to the vector element size in bits.
23995 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23996 const X86Subtarget *Subtarget) {
23997 EVT VT = N->getValueType(0);
23999 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24000 (!Subtarget->hasInt256() ||
24001 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24004 SDValue Amt = N->getOperand(1);
24006 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24007 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24008 APInt ShiftAmt = AmtSplat->getAPIntValue();
24009 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24011 // SSE2/AVX2 logical shifts always return a vector of 0s
24012 // if the shift amount is bigger than or equal to
24013 // the element size. The constant shift amount will be
24014 // encoded as a 8-bit immediate.
24015 if (ShiftAmt.trunc(8).uge(MaxAmount))
24016 return getZeroVector(VT, Subtarget, DAG, DL);
24022 /// PerformShiftCombine - Combine shifts.
24023 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24024 TargetLowering::DAGCombinerInfo &DCI,
24025 const X86Subtarget *Subtarget) {
24026 if (N->getOpcode() == ISD::SHL) {
24027 SDValue V = PerformSHLCombine(N, DAG);
24028 if (V.getNode()) return V;
24031 if (N->getOpcode() != ISD::SRA) {
24032 // Try to fold this logical shift into a zero vector.
24033 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24034 if (V.getNode()) return V;
24040 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24041 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24042 // and friends. Likewise for OR -> CMPNEQSS.
24043 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24044 TargetLowering::DAGCombinerInfo &DCI,
24045 const X86Subtarget *Subtarget) {
24048 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24049 // we're requiring SSE2 for both.
24050 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24051 SDValue N0 = N->getOperand(0);
24052 SDValue N1 = N->getOperand(1);
24053 SDValue CMP0 = N0->getOperand(1);
24054 SDValue CMP1 = N1->getOperand(1);
24057 // The SETCCs should both refer to the same CMP.
24058 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24061 SDValue CMP00 = CMP0->getOperand(0);
24062 SDValue CMP01 = CMP0->getOperand(1);
24063 EVT VT = CMP00.getValueType();
24065 if (VT == MVT::f32 || VT == MVT::f64) {
24066 bool ExpectingFlags = false;
24067 // Check for any users that want flags:
24068 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24069 !ExpectingFlags && UI != UE; ++UI)
24070 switch (UI->getOpcode()) {
24075 ExpectingFlags = true;
24077 case ISD::CopyToReg:
24078 case ISD::SIGN_EXTEND:
24079 case ISD::ZERO_EXTEND:
24080 case ISD::ANY_EXTEND:
24084 if (!ExpectingFlags) {
24085 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24086 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24088 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24089 X86::CondCode tmp = cc0;
24094 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24095 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24096 // FIXME: need symbolic constants for these magic numbers.
24097 // See X86ATTInstPrinter.cpp:printSSECC().
24098 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24099 if (Subtarget->hasAVX512()) {
24100 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24101 CMP01, DAG.getConstant(x86cc, MVT::i8));
24102 if (N->getValueType(0) != MVT::i1)
24103 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24107 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24108 CMP00.getValueType(), CMP00, CMP01,
24109 DAG.getConstant(x86cc, MVT::i8));
24111 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24112 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24114 if (is64BitFP && !Subtarget->is64Bit()) {
24115 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24116 // 64-bit integer, since that's not a legal type. Since
24117 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24118 // bits, but can do this little dance to extract the lowest 32 bits
24119 // and work with those going forward.
24120 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24122 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24124 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24125 Vector32, DAG.getIntPtrConstant(0));
24129 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24130 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24131 DAG.getConstant(1, IntVT));
24132 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24133 return OneBitOfTruth;
24141 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24142 /// so it can be folded inside ANDNP.
24143 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24144 EVT VT = N->getValueType(0);
24146 // Match direct AllOnes for 128 and 256-bit vectors
24147 if (ISD::isBuildVectorAllOnes(N))
24150 // Look through a bit convert.
24151 if (N->getOpcode() == ISD::BITCAST)
24152 N = N->getOperand(0).getNode();
24154 // Sometimes the operand may come from a insert_subvector building a 256-bit
24156 if (VT.is256BitVector() &&
24157 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24158 SDValue V1 = N->getOperand(0);
24159 SDValue V2 = N->getOperand(1);
24161 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24162 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24163 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24164 ISD::isBuildVectorAllOnes(V2.getNode()))
24171 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24172 // register. In most cases we actually compare or select YMM-sized registers
24173 // and mixing the two types creates horrible code. This method optimizes
24174 // some of the transition sequences.
24175 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24176 TargetLowering::DAGCombinerInfo &DCI,
24177 const X86Subtarget *Subtarget) {
24178 EVT VT = N->getValueType(0);
24179 if (!VT.is256BitVector())
24182 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24183 N->getOpcode() == ISD::ZERO_EXTEND ||
24184 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24186 SDValue Narrow = N->getOperand(0);
24187 EVT NarrowVT = Narrow->getValueType(0);
24188 if (!NarrowVT.is128BitVector())
24191 if (Narrow->getOpcode() != ISD::XOR &&
24192 Narrow->getOpcode() != ISD::AND &&
24193 Narrow->getOpcode() != ISD::OR)
24196 SDValue N0 = Narrow->getOperand(0);
24197 SDValue N1 = Narrow->getOperand(1);
24200 // The Left side has to be a trunc.
24201 if (N0.getOpcode() != ISD::TRUNCATE)
24204 // The type of the truncated inputs.
24205 EVT WideVT = N0->getOperand(0)->getValueType(0);
24209 // The right side has to be a 'trunc' or a constant vector.
24210 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24211 ConstantSDNode *RHSConstSplat = nullptr;
24212 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24213 RHSConstSplat = RHSBV->getConstantSplatNode();
24214 if (!RHSTrunc && !RHSConstSplat)
24217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24219 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24222 // Set N0 and N1 to hold the inputs to the new wide operation.
24223 N0 = N0->getOperand(0);
24224 if (RHSConstSplat) {
24225 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24226 SDValue(RHSConstSplat, 0));
24227 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24228 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24229 } else if (RHSTrunc) {
24230 N1 = N1->getOperand(0);
24233 // Generate the wide operation.
24234 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24235 unsigned Opcode = N->getOpcode();
24237 case ISD::ANY_EXTEND:
24239 case ISD::ZERO_EXTEND: {
24240 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24241 APInt Mask = APInt::getAllOnesValue(InBits);
24242 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24243 return DAG.getNode(ISD::AND, DL, VT,
24244 Op, DAG.getConstant(Mask, VT));
24246 case ISD::SIGN_EXTEND:
24247 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24248 Op, DAG.getValueType(NarrowVT));
24250 llvm_unreachable("Unexpected opcode");
24254 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24255 TargetLowering::DAGCombinerInfo &DCI,
24256 const X86Subtarget *Subtarget) {
24257 EVT VT = N->getValueType(0);
24258 if (DCI.isBeforeLegalizeOps())
24261 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24265 // Create BEXTR instructions
24266 // BEXTR is ((X >> imm) & (2**size-1))
24267 if (VT == MVT::i32 || VT == MVT::i64) {
24268 SDValue N0 = N->getOperand(0);
24269 SDValue N1 = N->getOperand(1);
24272 // Check for BEXTR.
24273 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24274 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24275 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24276 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24277 if (MaskNode && ShiftNode) {
24278 uint64_t Mask = MaskNode->getZExtValue();
24279 uint64_t Shift = ShiftNode->getZExtValue();
24280 if (isMask_64(Mask)) {
24281 uint64_t MaskSize = CountPopulation_64(Mask);
24282 if (Shift + MaskSize <= VT.getSizeInBits())
24283 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24284 DAG.getConstant(Shift | (MaskSize << 8), VT));
24292 // Want to form ANDNP nodes:
24293 // 1) In the hopes of then easily combining them with OR and AND nodes
24294 // to form PBLEND/PSIGN.
24295 // 2) To match ANDN packed intrinsics
24296 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24299 SDValue N0 = N->getOperand(0);
24300 SDValue N1 = N->getOperand(1);
24303 // Check LHS for vnot
24304 if (N0.getOpcode() == ISD::XOR &&
24305 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24306 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24307 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24309 // Check RHS for vnot
24310 if (N1.getOpcode() == ISD::XOR &&
24311 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24312 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24313 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24318 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24319 TargetLowering::DAGCombinerInfo &DCI,
24320 const X86Subtarget *Subtarget) {
24321 if (DCI.isBeforeLegalizeOps())
24324 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24328 SDValue N0 = N->getOperand(0);
24329 SDValue N1 = N->getOperand(1);
24330 EVT VT = N->getValueType(0);
24332 // look for psign/blend
24333 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24334 if (!Subtarget->hasSSSE3() ||
24335 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24338 // Canonicalize pandn to RHS
24339 if (N0.getOpcode() == X86ISD::ANDNP)
24341 // or (and (m, y), (pandn m, x))
24342 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24343 SDValue Mask = N1.getOperand(0);
24344 SDValue X = N1.getOperand(1);
24346 if (N0.getOperand(0) == Mask)
24347 Y = N0.getOperand(1);
24348 if (N0.getOperand(1) == Mask)
24349 Y = N0.getOperand(0);
24351 // Check to see if the mask appeared in both the AND and ANDNP and
24355 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24356 // Look through mask bitcast.
24357 if (Mask.getOpcode() == ISD::BITCAST)
24358 Mask = Mask.getOperand(0);
24359 if (X.getOpcode() == ISD::BITCAST)
24360 X = X.getOperand(0);
24361 if (Y.getOpcode() == ISD::BITCAST)
24362 Y = Y.getOperand(0);
24364 EVT MaskVT = Mask.getValueType();
24366 // Validate that the Mask operand is a vector sra node.
24367 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24368 // there is no psrai.b
24369 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24370 unsigned SraAmt = ~0;
24371 if (Mask.getOpcode() == ISD::SRA) {
24372 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24373 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24374 SraAmt = AmtConst->getZExtValue();
24375 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24376 SDValue SraC = Mask.getOperand(1);
24377 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24379 if ((SraAmt + 1) != EltBits)
24384 // Now we know we at least have a plendvb with the mask val. See if
24385 // we can form a psignb/w/d.
24386 // psign = x.type == y.type == mask.type && y = sub(0, x);
24387 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24388 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24389 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24390 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24391 "Unsupported VT for PSIGN");
24392 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24393 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24395 // PBLENDVB only available on SSE 4.1
24396 if (!Subtarget->hasSSE41())
24399 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24401 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24402 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24403 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24404 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24405 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24409 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24412 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24413 MachineFunction &MF = DAG.getMachineFunction();
24414 bool OptForSize = MF.getFunction()->getAttributes().
24415 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24417 // SHLD/SHRD instructions have lower register pressure, but on some
24418 // platforms they have higher latency than the equivalent
24419 // series of shifts/or that would otherwise be generated.
24420 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24421 // have higher latencies and we are not optimizing for size.
24422 if (!OptForSize && Subtarget->isSHLDSlow())
24425 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24427 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24429 if (!N0.hasOneUse() || !N1.hasOneUse())
24432 SDValue ShAmt0 = N0.getOperand(1);
24433 if (ShAmt0.getValueType() != MVT::i8)
24435 SDValue ShAmt1 = N1.getOperand(1);
24436 if (ShAmt1.getValueType() != MVT::i8)
24438 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24439 ShAmt0 = ShAmt0.getOperand(0);
24440 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24441 ShAmt1 = ShAmt1.getOperand(0);
24444 unsigned Opc = X86ISD::SHLD;
24445 SDValue Op0 = N0.getOperand(0);
24446 SDValue Op1 = N1.getOperand(0);
24447 if (ShAmt0.getOpcode() == ISD::SUB) {
24448 Opc = X86ISD::SHRD;
24449 std::swap(Op0, Op1);
24450 std::swap(ShAmt0, ShAmt1);
24453 unsigned Bits = VT.getSizeInBits();
24454 if (ShAmt1.getOpcode() == ISD::SUB) {
24455 SDValue Sum = ShAmt1.getOperand(0);
24456 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24457 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24458 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24459 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24460 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24461 return DAG.getNode(Opc, DL, VT,
24463 DAG.getNode(ISD::TRUNCATE, DL,
24466 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24467 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24469 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24470 return DAG.getNode(Opc, DL, VT,
24471 N0.getOperand(0), N1.getOperand(0),
24472 DAG.getNode(ISD::TRUNCATE, DL,
24479 // Generate NEG and CMOV for integer abs.
24480 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24481 EVT VT = N->getValueType(0);
24483 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24484 // 8-bit integer abs to NEG and CMOV.
24485 if (VT.isInteger() && VT.getSizeInBits() == 8)
24488 SDValue N0 = N->getOperand(0);
24489 SDValue N1 = N->getOperand(1);
24492 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24493 // and change it to SUB and CMOV.
24494 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24495 N0.getOpcode() == ISD::ADD &&
24496 N0.getOperand(1) == N1 &&
24497 N1.getOpcode() == ISD::SRA &&
24498 N1.getOperand(0) == N0.getOperand(0))
24499 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24500 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24501 // Generate SUB & CMOV.
24502 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24503 DAG.getConstant(0, VT), N0.getOperand(0));
24505 SDValue Ops[] = { N0.getOperand(0), Neg,
24506 DAG.getConstant(X86::COND_GE, MVT::i8),
24507 SDValue(Neg.getNode(), 1) };
24508 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24513 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24514 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24515 TargetLowering::DAGCombinerInfo &DCI,
24516 const X86Subtarget *Subtarget) {
24517 if (DCI.isBeforeLegalizeOps())
24520 if (Subtarget->hasCMov()) {
24521 SDValue RV = performIntegerAbsCombine(N, DAG);
24529 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24530 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24531 TargetLowering::DAGCombinerInfo &DCI,
24532 const X86Subtarget *Subtarget) {
24533 LoadSDNode *Ld = cast<LoadSDNode>(N);
24534 EVT RegVT = Ld->getValueType(0);
24535 EVT MemVT = Ld->getMemoryVT();
24537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24539 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24540 // into two 16-byte operations.
24541 ISD::LoadExtType Ext = Ld->getExtensionType();
24542 unsigned Alignment = Ld->getAlignment();
24543 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24544 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24545 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24546 unsigned NumElems = RegVT.getVectorNumElements();
24550 SDValue Ptr = Ld->getBasePtr();
24551 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24553 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24555 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24556 Ld->getPointerInfo(), Ld->isVolatile(),
24557 Ld->isNonTemporal(), Ld->isInvariant(),
24559 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24560 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24561 Ld->getPointerInfo(), Ld->isVolatile(),
24562 Ld->isNonTemporal(), Ld->isInvariant(),
24563 std::min(16U, Alignment));
24564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24566 Load2.getValue(1));
24568 SDValue NewVec = DAG.getUNDEF(RegVT);
24569 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24570 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24571 return DCI.CombineTo(N, NewVec, TF, true);
24577 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24578 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24579 const X86Subtarget *Subtarget) {
24580 StoreSDNode *St = cast<StoreSDNode>(N);
24581 EVT VT = St->getValue().getValueType();
24582 EVT StVT = St->getMemoryVT();
24584 SDValue StoredVal = St->getOperand(1);
24585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24587 // If we are saving a concatenation of two XMM registers and 32-byte stores
24588 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24589 unsigned Alignment = St->getAlignment();
24590 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24591 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24592 StVT == VT && !IsAligned) {
24593 unsigned NumElems = VT.getVectorNumElements();
24597 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24598 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24600 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24601 SDValue Ptr0 = St->getBasePtr();
24602 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24604 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24605 St->getPointerInfo(), St->isVolatile(),
24606 St->isNonTemporal(), Alignment);
24607 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24608 St->getPointerInfo(), St->isVolatile(),
24609 St->isNonTemporal(),
24610 std::min(16U, Alignment));
24611 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24614 // Optimize trunc store (of multiple scalars) to shuffle and store.
24615 // First, pack all of the elements in one place. Next, store to memory
24616 // in fewer chunks.
24617 if (St->isTruncatingStore() && VT.isVector()) {
24618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24619 unsigned NumElems = VT.getVectorNumElements();
24620 assert(StVT != VT && "Cannot truncate to the same type");
24621 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24622 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24624 // From, To sizes and ElemCount must be pow of two
24625 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24626 // We are going to use the original vector elt for storing.
24627 // Accumulated smaller vector elements must be a multiple of the store size.
24628 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24630 unsigned SizeRatio = FromSz / ToSz;
24632 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24634 // Create a type on which we perform the shuffle
24635 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24636 StVT.getScalarType(), NumElems*SizeRatio);
24638 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24640 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24641 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24642 for (unsigned i = 0; i != NumElems; ++i)
24643 ShuffleVec[i] = i * SizeRatio;
24645 // Can't shuffle using an illegal type.
24646 if (!TLI.isTypeLegal(WideVecVT))
24649 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24650 DAG.getUNDEF(WideVecVT),
24652 // At this point all of the data is stored at the bottom of the
24653 // register. We now need to save it to mem.
24655 // Find the largest store unit
24656 MVT StoreType = MVT::i8;
24657 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24658 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24659 MVT Tp = (MVT::SimpleValueType)tp;
24660 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24664 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24665 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24666 (64 <= NumElems * ToSz))
24667 StoreType = MVT::f64;
24669 // Bitcast the original vector into a vector of store-size units
24670 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24671 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24672 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24673 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24674 SmallVector<SDValue, 8> Chains;
24675 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24676 TLI.getPointerTy());
24677 SDValue Ptr = St->getBasePtr();
24679 // Perform one or more big stores into memory.
24680 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24681 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24682 StoreType, ShuffWide,
24683 DAG.getIntPtrConstant(i));
24684 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24685 St->getPointerInfo(), St->isVolatile(),
24686 St->isNonTemporal(), St->getAlignment());
24687 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24688 Chains.push_back(Ch);
24691 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24694 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24695 // the FP state in cases where an emms may be missing.
24696 // A preferable solution to the general problem is to figure out the right
24697 // places to insert EMMS. This qualifies as a quick hack.
24699 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24700 if (VT.getSizeInBits() != 64)
24703 const Function *F = DAG.getMachineFunction().getFunction();
24704 bool NoImplicitFloatOps = F->getAttributes().
24705 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24706 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24707 && Subtarget->hasSSE2();
24708 if ((VT.isVector() ||
24709 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24710 isa<LoadSDNode>(St->getValue()) &&
24711 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24712 St->getChain().hasOneUse() && !St->isVolatile()) {
24713 SDNode* LdVal = St->getValue().getNode();
24714 LoadSDNode *Ld = nullptr;
24715 int TokenFactorIndex = -1;
24716 SmallVector<SDValue, 8> Ops;
24717 SDNode* ChainVal = St->getChain().getNode();
24718 // Must be a store of a load. We currently handle two cases: the load
24719 // is a direct child, and it's under an intervening TokenFactor. It is
24720 // possible to dig deeper under nested TokenFactors.
24721 if (ChainVal == LdVal)
24722 Ld = cast<LoadSDNode>(St->getChain());
24723 else if (St->getValue().hasOneUse() &&
24724 ChainVal->getOpcode() == ISD::TokenFactor) {
24725 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24726 if (ChainVal->getOperand(i).getNode() == LdVal) {
24727 TokenFactorIndex = i;
24728 Ld = cast<LoadSDNode>(St->getValue());
24730 Ops.push_back(ChainVal->getOperand(i));
24734 if (!Ld || !ISD::isNormalLoad(Ld))
24737 // If this is not the MMX case, i.e. we are just turning i64 load/store
24738 // into f64 load/store, avoid the transformation if there are multiple
24739 // uses of the loaded value.
24740 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24745 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24746 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24748 if (Subtarget->is64Bit() || F64IsLegal) {
24749 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24750 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24751 Ld->getPointerInfo(), Ld->isVolatile(),
24752 Ld->isNonTemporal(), Ld->isInvariant(),
24753 Ld->getAlignment());
24754 SDValue NewChain = NewLd.getValue(1);
24755 if (TokenFactorIndex != -1) {
24756 Ops.push_back(NewChain);
24757 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24759 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24760 St->getPointerInfo(),
24761 St->isVolatile(), St->isNonTemporal(),
24762 St->getAlignment());
24765 // Otherwise, lower to two pairs of 32-bit loads / stores.
24766 SDValue LoAddr = Ld->getBasePtr();
24767 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24768 DAG.getConstant(4, MVT::i32));
24770 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24771 Ld->getPointerInfo(),
24772 Ld->isVolatile(), Ld->isNonTemporal(),
24773 Ld->isInvariant(), Ld->getAlignment());
24774 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24775 Ld->getPointerInfo().getWithOffset(4),
24776 Ld->isVolatile(), Ld->isNonTemporal(),
24778 MinAlign(Ld->getAlignment(), 4));
24780 SDValue NewChain = LoLd.getValue(1);
24781 if (TokenFactorIndex != -1) {
24782 Ops.push_back(LoLd);
24783 Ops.push_back(HiLd);
24784 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24787 LoAddr = St->getBasePtr();
24788 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24789 DAG.getConstant(4, MVT::i32));
24791 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24792 St->getPointerInfo(),
24793 St->isVolatile(), St->isNonTemporal(),
24794 St->getAlignment());
24795 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24796 St->getPointerInfo().getWithOffset(4),
24798 St->isNonTemporal(),
24799 MinAlign(St->getAlignment(), 4));
24800 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24805 /// Return 'true' if this vector operation is "horizontal"
24806 /// and return the operands for the horizontal operation in LHS and RHS. A
24807 /// horizontal operation performs the binary operation on successive elements
24808 /// of its first operand, then on successive elements of its second operand,
24809 /// returning the resulting values in a vector. For example, if
24810 /// A = < float a0, float a1, float a2, float a3 >
24812 /// B = < float b0, float b1, float b2, float b3 >
24813 /// then the result of doing a horizontal operation on A and B is
24814 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24815 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24816 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24817 /// set to A, RHS to B, and the routine returns 'true'.
24818 /// Note that the binary operation should have the property that if one of the
24819 /// operands is UNDEF then the result is UNDEF.
24820 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24821 // Look for the following pattern: if
24822 // A = < float a0, float a1, float a2, float a3 >
24823 // B = < float b0, float b1, float b2, float b3 >
24825 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24826 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24827 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24828 // which is A horizontal-op B.
24830 // At least one of the operands should be a vector shuffle.
24831 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24832 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24835 MVT VT = LHS.getSimpleValueType();
24837 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24838 "Unsupported vector type for horizontal add/sub");
24840 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24841 // operate independently on 128-bit lanes.
24842 unsigned NumElts = VT.getVectorNumElements();
24843 unsigned NumLanes = VT.getSizeInBits()/128;
24844 unsigned NumLaneElts = NumElts / NumLanes;
24845 assert((NumLaneElts % 2 == 0) &&
24846 "Vector type should have an even number of elements in each lane");
24847 unsigned HalfLaneElts = NumLaneElts/2;
24849 // View LHS in the form
24850 // LHS = VECTOR_SHUFFLE A, B, LMask
24851 // If LHS is not a shuffle then pretend it is the shuffle
24852 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24853 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24856 SmallVector<int, 16> LMask(NumElts);
24857 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24858 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24859 A = LHS.getOperand(0);
24860 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24861 B = LHS.getOperand(1);
24862 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24863 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24865 if (LHS.getOpcode() != ISD::UNDEF)
24867 for (unsigned i = 0; i != NumElts; ++i)
24871 // Likewise, view RHS in the form
24872 // RHS = VECTOR_SHUFFLE C, D, RMask
24874 SmallVector<int, 16> RMask(NumElts);
24875 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24876 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24877 C = RHS.getOperand(0);
24878 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24879 D = RHS.getOperand(1);
24880 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24881 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24883 if (RHS.getOpcode() != ISD::UNDEF)
24885 for (unsigned i = 0; i != NumElts; ++i)
24889 // Check that the shuffles are both shuffling the same vectors.
24890 if (!(A == C && B == D) && !(A == D && B == C))
24893 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24894 if (!A.getNode() && !B.getNode())
24897 // If A and B occur in reverse order in RHS, then "swap" them (which means
24898 // rewriting the mask).
24900 CommuteVectorShuffleMask(RMask, NumElts);
24902 // At this point LHS and RHS are equivalent to
24903 // LHS = VECTOR_SHUFFLE A, B, LMask
24904 // RHS = VECTOR_SHUFFLE A, B, RMask
24905 // Check that the masks correspond to performing a horizontal operation.
24906 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24907 for (unsigned i = 0; i != NumLaneElts; ++i) {
24908 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24910 // Ignore any UNDEF components.
24911 if (LIdx < 0 || RIdx < 0 ||
24912 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24913 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24916 // Check that successive elements are being operated on. If not, this is
24917 // not a horizontal operation.
24918 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24919 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24920 if (!(LIdx == Index && RIdx == Index + 1) &&
24921 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24926 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24927 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24931 /// Do target-specific dag combines on floating point adds.
24932 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24933 const X86Subtarget *Subtarget) {
24934 EVT VT = N->getValueType(0);
24935 SDValue LHS = N->getOperand(0);
24936 SDValue RHS = N->getOperand(1);
24938 // Try to synthesize horizontal adds from adds of shuffles.
24939 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24940 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24941 isHorizontalBinOp(LHS, RHS, true))
24942 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24946 /// Do target-specific dag combines on floating point subs.
24947 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24948 const X86Subtarget *Subtarget) {
24949 EVT VT = N->getValueType(0);
24950 SDValue LHS = N->getOperand(0);
24951 SDValue RHS = N->getOperand(1);
24953 // Try to synthesize horizontal subs from subs of shuffles.
24954 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24955 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24956 isHorizontalBinOp(LHS, RHS, false))
24957 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24961 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24962 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24963 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24964 // F[X]OR(0.0, x) -> x
24965 // F[X]OR(x, 0.0) -> x
24966 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24967 if (C->getValueAPF().isPosZero())
24968 return N->getOperand(1);
24969 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24970 if (C->getValueAPF().isPosZero())
24971 return N->getOperand(0);
24975 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24976 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24977 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24979 // Only perform optimizations if UnsafeMath is used.
24980 if (!DAG.getTarget().Options.UnsafeFPMath)
24983 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24984 // into FMINC and FMAXC, which are Commutative operations.
24985 unsigned NewOp = 0;
24986 switch (N->getOpcode()) {
24987 default: llvm_unreachable("unknown opcode");
24988 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24989 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24992 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24993 N->getOperand(0), N->getOperand(1));
24996 /// Do target-specific dag combines on X86ISD::FAND nodes.
24997 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24998 // FAND(0.0, x) -> 0.0
24999 // FAND(x, 0.0) -> 0.0
25000 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25001 if (C->getValueAPF().isPosZero())
25002 return N->getOperand(0);
25003 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25004 if (C->getValueAPF().isPosZero())
25005 return N->getOperand(1);
25009 /// Do target-specific dag combines on X86ISD::FANDN nodes
25010 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25011 // FANDN(x, 0.0) -> 0.0
25012 // FANDN(0.0, x) -> x
25013 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25014 if (C->getValueAPF().isPosZero())
25015 return N->getOperand(1);
25016 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25017 if (C->getValueAPF().isPosZero())
25018 return N->getOperand(1);
25022 static SDValue PerformBTCombine(SDNode *N,
25024 TargetLowering::DAGCombinerInfo &DCI) {
25025 // BT ignores high bits in the bit index operand.
25026 SDValue Op1 = N->getOperand(1);
25027 if (Op1.hasOneUse()) {
25028 unsigned BitWidth = Op1.getValueSizeInBits();
25029 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25030 APInt KnownZero, KnownOne;
25031 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25032 !DCI.isBeforeLegalizeOps());
25033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25034 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25035 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25036 DCI.CommitTargetLoweringOpt(TLO);
25041 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25042 SDValue Op = N->getOperand(0);
25043 if (Op.getOpcode() == ISD::BITCAST)
25044 Op = Op.getOperand(0);
25045 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25046 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25047 VT.getVectorElementType().getSizeInBits() ==
25048 OpVT.getVectorElementType().getSizeInBits()) {
25049 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25054 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25055 const X86Subtarget *Subtarget) {
25056 EVT VT = N->getValueType(0);
25057 if (!VT.isVector())
25060 SDValue N0 = N->getOperand(0);
25061 SDValue N1 = N->getOperand(1);
25062 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25065 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25066 // both SSE and AVX2 since there is no sign-extended shift right
25067 // operation on a vector with 64-bit elements.
25068 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25069 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25070 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25071 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25072 SDValue N00 = N0.getOperand(0);
25074 // EXTLOAD has a better solution on AVX2,
25075 // it may be replaced with X86ISD::VSEXT node.
25076 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25077 if (!ISD::isNormalLoad(N00.getNode()))
25080 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25081 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25083 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25089 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25090 TargetLowering::DAGCombinerInfo &DCI,
25091 const X86Subtarget *Subtarget) {
25092 SDValue N0 = N->getOperand(0);
25093 EVT VT = N->getValueType(0);
25095 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25096 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25097 // This exposes the sext to the sdivrem lowering, so that it directly extends
25098 // from AH (which we otherwise need to do contortions to access).
25099 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25100 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25102 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25103 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25104 N0.getOperand(0), N0.getOperand(1));
25105 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25106 return R.getValue(1);
25109 if (!DCI.isBeforeLegalizeOps())
25112 if (!Subtarget->hasFp256())
25115 if (VT.isVector() && VT.getSizeInBits() == 256) {
25116 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25124 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25125 const X86Subtarget* Subtarget) {
25127 EVT VT = N->getValueType(0);
25129 // Let legalize expand this if it isn't a legal type yet.
25130 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25133 EVT ScalarVT = VT.getScalarType();
25134 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25135 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25138 SDValue A = N->getOperand(0);
25139 SDValue B = N->getOperand(1);
25140 SDValue C = N->getOperand(2);
25142 bool NegA = (A.getOpcode() == ISD::FNEG);
25143 bool NegB = (B.getOpcode() == ISD::FNEG);
25144 bool NegC = (C.getOpcode() == ISD::FNEG);
25146 // Negative multiplication when NegA xor NegB
25147 bool NegMul = (NegA != NegB);
25149 A = A.getOperand(0);
25151 B = B.getOperand(0);
25153 C = C.getOperand(0);
25157 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25159 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25161 return DAG.getNode(Opcode, dl, VT, A, B, C);
25164 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25165 TargetLowering::DAGCombinerInfo &DCI,
25166 const X86Subtarget *Subtarget) {
25167 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25168 // (and (i32 x86isd::setcc_carry), 1)
25169 // This eliminates the zext. This transformation is necessary because
25170 // ISD::SETCC is always legalized to i8.
25172 SDValue N0 = N->getOperand(0);
25173 EVT VT = N->getValueType(0);
25175 if (N0.getOpcode() == ISD::AND &&
25177 N0.getOperand(0).hasOneUse()) {
25178 SDValue N00 = N0.getOperand(0);
25179 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25180 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25181 if (!C || C->getZExtValue() != 1)
25183 return DAG.getNode(ISD::AND, dl, VT,
25184 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25185 N00.getOperand(0), N00.getOperand(1)),
25186 DAG.getConstant(1, VT));
25190 if (N0.getOpcode() == ISD::TRUNCATE &&
25192 N0.getOperand(0).hasOneUse()) {
25193 SDValue N00 = N0.getOperand(0);
25194 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25195 return DAG.getNode(ISD::AND, dl, VT,
25196 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25197 N00.getOperand(0), N00.getOperand(1)),
25198 DAG.getConstant(1, VT));
25201 if (VT.is256BitVector()) {
25202 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25207 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25208 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25209 // This exposes the zext to the udivrem lowering, so that it directly extends
25210 // from AH (which we otherwise need to do contortions to access).
25211 if (N0.getOpcode() == ISD::UDIVREM &&
25212 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25213 (VT == MVT::i32 || VT == MVT::i64)) {
25214 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25215 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25216 N0.getOperand(0), N0.getOperand(1));
25217 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25218 return R.getValue(1);
25224 // Optimize x == -y --> x+y == 0
25225 // x != -y --> x+y != 0
25226 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25227 const X86Subtarget* Subtarget) {
25228 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25229 SDValue LHS = N->getOperand(0);
25230 SDValue RHS = N->getOperand(1);
25231 EVT VT = N->getValueType(0);
25234 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25236 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25237 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25238 LHS.getValueType(), RHS, LHS.getOperand(1));
25239 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25240 addV, DAG.getConstant(0, addV.getValueType()), CC);
25242 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25243 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25244 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25245 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25246 RHS.getValueType(), LHS, RHS.getOperand(1));
25247 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25248 addV, DAG.getConstant(0, addV.getValueType()), CC);
25251 if (VT.getScalarType() == MVT::i1) {
25252 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25253 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25254 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25255 if (!IsSEXT0 && !IsVZero0)
25257 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25258 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25259 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25261 if (!IsSEXT1 && !IsVZero1)
25264 if (IsSEXT0 && IsVZero1) {
25265 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25266 if (CC == ISD::SETEQ)
25267 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25268 return LHS.getOperand(0);
25270 if (IsSEXT1 && IsVZero0) {
25271 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25272 if (CC == ISD::SETEQ)
25273 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25274 return RHS.getOperand(0);
25281 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25282 const X86Subtarget *Subtarget) {
25284 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25285 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25286 "X86insertps is only defined for v4x32");
25288 SDValue Ld = N->getOperand(1);
25289 if (MayFoldLoad(Ld)) {
25290 // Extract the countS bits from the immediate so we can get the proper
25291 // address when narrowing the vector load to a specific element.
25292 // When the second source op is a memory address, interps doesn't use
25293 // countS and just gets an f32 from that address.
25294 unsigned DestIndex =
25295 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25296 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25300 // Create this as a scalar to vector to match the instruction pattern.
25301 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25302 // countS bits are ignored when loading from memory on insertps, which
25303 // means we don't need to explicitly set them to 0.
25304 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25305 LoadScalarToVector, N->getOperand(2));
25308 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25309 // as "sbb reg,reg", since it can be extended without zext and produces
25310 // an all-ones bit which is more useful than 0/1 in some cases.
25311 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25314 return DAG.getNode(ISD::AND, DL, VT,
25315 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25316 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25317 DAG.getConstant(1, VT));
25318 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25319 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25320 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25321 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25324 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25325 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25326 TargetLowering::DAGCombinerInfo &DCI,
25327 const X86Subtarget *Subtarget) {
25329 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25330 SDValue EFLAGS = N->getOperand(1);
25332 if (CC == X86::COND_A) {
25333 // Try to convert COND_A into COND_B in an attempt to facilitate
25334 // materializing "setb reg".
25336 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25337 // cannot take an immediate as its first operand.
25339 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25340 EFLAGS.getValueType().isInteger() &&
25341 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25342 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25343 EFLAGS.getNode()->getVTList(),
25344 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25345 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25346 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25350 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25351 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25353 if (CC == X86::COND_B)
25354 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25358 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25359 if (Flags.getNode()) {
25360 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25361 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25367 // Optimize branch condition evaluation.
25369 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25370 TargetLowering::DAGCombinerInfo &DCI,
25371 const X86Subtarget *Subtarget) {
25373 SDValue Chain = N->getOperand(0);
25374 SDValue Dest = N->getOperand(1);
25375 SDValue EFLAGS = N->getOperand(3);
25376 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25380 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25381 if (Flags.getNode()) {
25382 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25383 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25390 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25391 SelectionDAG &DAG) {
25392 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25393 // optimize away operation when it's from a constant.
25395 // The general transformation is:
25396 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25397 // AND(VECTOR_CMP(x,y), constant2)
25398 // constant2 = UNARYOP(constant)
25400 // Early exit if this isn't a vector operation, the operand of the
25401 // unary operation isn't a bitwise AND, or if the sizes of the operations
25402 // aren't the same.
25403 EVT VT = N->getValueType(0);
25404 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25405 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25406 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25409 // Now check that the other operand of the AND is a constant. We could
25410 // make the transformation for non-constant splats as well, but it's unclear
25411 // that would be a benefit as it would not eliminate any operations, just
25412 // perform one more step in scalar code before moving to the vector unit.
25413 if (BuildVectorSDNode *BV =
25414 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25415 // Bail out if the vector isn't a constant.
25416 if (!BV->isConstant())
25419 // Everything checks out. Build up the new and improved node.
25421 EVT IntVT = BV->getValueType(0);
25422 // Create a new constant of the appropriate type for the transformed
25424 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25425 // The AND node needs bitcasts to/from an integer vector type around it.
25426 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25427 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25428 N->getOperand(0)->getOperand(0), MaskConst);
25429 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25436 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25437 const X86TargetLowering *XTLI) {
25438 // First try to optimize away the conversion entirely when it's
25439 // conditionally from a constant. Vectors only.
25440 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25441 if (Res != SDValue())
25444 // Now move on to more general possibilities.
25445 SDValue Op0 = N->getOperand(0);
25446 EVT InVT = Op0->getValueType(0);
25448 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25449 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25451 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25452 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25453 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25456 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25457 // a 32-bit target where SSE doesn't support i64->FP operations.
25458 if (Op0.getOpcode() == ISD::LOAD) {
25459 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25460 EVT VT = Ld->getValueType(0);
25461 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25462 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25463 !XTLI->getSubtarget()->is64Bit() &&
25465 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25466 Ld->getChain(), Op0, DAG);
25467 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25474 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25475 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25476 X86TargetLowering::DAGCombinerInfo &DCI) {
25477 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25478 // the result is either zero or one (depending on the input carry bit).
25479 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25480 if (X86::isZeroNode(N->getOperand(0)) &&
25481 X86::isZeroNode(N->getOperand(1)) &&
25482 // We don't have a good way to replace an EFLAGS use, so only do this when
25484 SDValue(N, 1).use_empty()) {
25486 EVT VT = N->getValueType(0);
25487 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25488 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25489 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25490 DAG.getConstant(X86::COND_B,MVT::i8),
25492 DAG.getConstant(1, VT));
25493 return DCI.CombineTo(N, Res1, CarryOut);
25499 // fold (add Y, (sete X, 0)) -> adc 0, Y
25500 // (add Y, (setne X, 0)) -> sbb -1, Y
25501 // (sub (sete X, 0), Y) -> sbb 0, Y
25502 // (sub (setne X, 0), Y) -> adc -1, Y
25503 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25506 // Look through ZExts.
25507 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25508 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25511 SDValue SetCC = Ext.getOperand(0);
25512 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25515 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25516 if (CC != X86::COND_E && CC != X86::COND_NE)
25519 SDValue Cmp = SetCC.getOperand(1);
25520 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25521 !X86::isZeroNode(Cmp.getOperand(1)) ||
25522 !Cmp.getOperand(0).getValueType().isInteger())
25525 SDValue CmpOp0 = Cmp.getOperand(0);
25526 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25527 DAG.getConstant(1, CmpOp0.getValueType()));
25529 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25530 if (CC == X86::COND_NE)
25531 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25532 DL, OtherVal.getValueType(), OtherVal,
25533 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25534 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25535 DL, OtherVal.getValueType(), OtherVal,
25536 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25539 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25540 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25541 const X86Subtarget *Subtarget) {
25542 EVT VT = N->getValueType(0);
25543 SDValue Op0 = N->getOperand(0);
25544 SDValue Op1 = N->getOperand(1);
25546 // Try to synthesize horizontal adds from adds of shuffles.
25547 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25548 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25549 isHorizontalBinOp(Op0, Op1, true))
25550 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25552 return OptimizeConditionalInDecrement(N, DAG);
25555 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25556 const X86Subtarget *Subtarget) {
25557 SDValue Op0 = N->getOperand(0);
25558 SDValue Op1 = N->getOperand(1);
25560 // X86 can't encode an immediate LHS of a sub. See if we can push the
25561 // negation into a preceding instruction.
25562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25563 // If the RHS of the sub is a XOR with one use and a constant, invert the
25564 // immediate. Then add one to the LHS of the sub so we can turn
25565 // X-Y -> X+~Y+1, saving one register.
25566 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25567 isa<ConstantSDNode>(Op1.getOperand(1))) {
25568 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25569 EVT VT = Op0.getValueType();
25570 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25572 DAG.getConstant(~XorC, VT));
25573 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25574 DAG.getConstant(C->getAPIntValue()+1, VT));
25578 // Try to synthesize horizontal adds from adds of shuffles.
25579 EVT VT = N->getValueType(0);
25580 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25581 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25582 isHorizontalBinOp(Op0, Op1, true))
25583 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25585 return OptimizeConditionalInDecrement(N, DAG);
25588 /// performVZEXTCombine - Performs build vector combines
25589 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25590 TargetLowering::DAGCombinerInfo &DCI,
25591 const X86Subtarget *Subtarget) {
25593 MVT VT = N->getSimpleValueType(0);
25594 SDValue Op = N->getOperand(0);
25595 MVT OpVT = Op.getSimpleValueType();
25596 MVT OpEltVT = OpVT.getVectorElementType();
25597 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25599 // (vzext (bitcast (vzext (x)) -> (vzext x)
25601 while (V.getOpcode() == ISD::BITCAST)
25602 V = V.getOperand(0);
25604 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25605 MVT InnerVT = V.getSimpleValueType();
25606 MVT InnerEltVT = InnerVT.getVectorElementType();
25608 // If the element sizes match exactly, we can just do one larger vzext. This
25609 // is always an exact type match as vzext operates on integer types.
25610 if (OpEltVT == InnerEltVT) {
25611 assert(OpVT == InnerVT && "Types must match for vzext!");
25612 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25615 // The only other way we can combine them is if only a single element of the
25616 // inner vzext is used in the input to the outer vzext.
25617 if (InnerEltVT.getSizeInBits() < InputBits)
25620 // In this case, the inner vzext is completely dead because we're going to
25621 // only look at bits inside of the low element. Just do the outer vzext on
25622 // a bitcast of the input to the inner.
25623 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25624 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25627 // Check if we can bypass extracting and re-inserting an element of an input
25628 // vector. Essentialy:
25629 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25630 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25631 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25632 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25633 SDValue ExtractedV = V.getOperand(0);
25634 SDValue OrigV = ExtractedV.getOperand(0);
25635 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25636 if (ExtractIdx->getZExtValue() == 0) {
25637 MVT OrigVT = OrigV.getSimpleValueType();
25638 // Extract a subvector if necessary...
25639 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25640 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25641 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25642 OrigVT.getVectorNumElements() / Ratio);
25643 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25644 DAG.getIntPtrConstant(0));
25646 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25647 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25654 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25655 DAGCombinerInfo &DCI) const {
25656 SelectionDAG &DAG = DCI.DAG;
25657 switch (N->getOpcode()) {
25659 case ISD::EXTRACT_VECTOR_ELT:
25660 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25663 case X86ISD::SHRUNKBLEND:
25664 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25665 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25666 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25667 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25668 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25669 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25672 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25673 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25674 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25675 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25676 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25677 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25678 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25679 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25680 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25682 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25684 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25685 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25686 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25687 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25688 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25689 case ISD::ANY_EXTEND:
25690 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25691 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25692 case ISD::SIGN_EXTEND_INREG:
25693 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25694 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25695 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25696 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25697 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25698 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25699 case X86ISD::SHUFP: // Handle all target specific shuffles
25700 case X86ISD::PALIGNR:
25701 case X86ISD::UNPCKH:
25702 case X86ISD::UNPCKL:
25703 case X86ISD::MOVHLPS:
25704 case X86ISD::MOVLHPS:
25705 case X86ISD::PSHUFB:
25706 case X86ISD::PSHUFD:
25707 case X86ISD::PSHUFHW:
25708 case X86ISD::PSHUFLW:
25709 case X86ISD::MOVSS:
25710 case X86ISD::MOVSD:
25711 case X86ISD::VPERMILPI:
25712 case X86ISD::VPERM2X128:
25713 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25714 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25715 case ISD::INTRINSIC_WO_CHAIN:
25716 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25717 case X86ISD::INSERTPS:
25718 return PerformINSERTPSCombine(N, DAG, Subtarget);
25719 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25725 /// isTypeDesirableForOp - Return true if the target has native support for
25726 /// the specified value type and it is 'desirable' to use the type for the
25727 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25728 /// instruction encodings are longer and some i16 instructions are slow.
25729 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25730 if (!isTypeLegal(VT))
25732 if (VT != MVT::i16)
25739 case ISD::SIGN_EXTEND:
25740 case ISD::ZERO_EXTEND:
25741 case ISD::ANY_EXTEND:
25754 /// IsDesirableToPromoteOp - This method query the target whether it is
25755 /// beneficial for dag combiner to promote the specified node. If true, it
25756 /// should return the desired promotion type by reference.
25757 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25758 EVT VT = Op.getValueType();
25759 if (VT != MVT::i16)
25762 bool Promote = false;
25763 bool Commute = false;
25764 switch (Op.getOpcode()) {
25767 LoadSDNode *LD = cast<LoadSDNode>(Op);
25768 // If the non-extending load has a single use and it's not live out, then it
25769 // might be folded.
25770 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25771 Op.hasOneUse()*/) {
25772 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25773 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25774 // The only case where we'd want to promote LOAD (rather then it being
25775 // promoted as an operand is when it's only use is liveout.
25776 if (UI->getOpcode() != ISD::CopyToReg)
25783 case ISD::SIGN_EXTEND:
25784 case ISD::ZERO_EXTEND:
25785 case ISD::ANY_EXTEND:
25790 SDValue N0 = Op.getOperand(0);
25791 // Look out for (store (shl (load), x)).
25792 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25805 SDValue N0 = Op.getOperand(0);
25806 SDValue N1 = Op.getOperand(1);
25807 if (!Commute && MayFoldLoad(N1))
25809 // Avoid disabling potential load folding opportunities.
25810 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25812 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25822 //===----------------------------------------------------------------------===//
25823 // X86 Inline Assembly Support
25824 //===----------------------------------------------------------------------===//
25827 // Helper to match a string separated by whitespace.
25828 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25829 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25831 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25832 StringRef piece(*args[i]);
25833 if (!s.startswith(piece)) // Check if the piece matches.
25836 s = s.substr(piece.size());
25837 StringRef::size_type pos = s.find_first_not_of(" \t");
25838 if (pos == 0) // We matched a prefix.
25846 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25849 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25851 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25852 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25853 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25854 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25856 if (AsmPieces.size() == 3)
25858 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25865 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25866 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25868 std::string AsmStr = IA->getAsmString();
25870 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25871 if (!Ty || Ty->getBitWidth() % 16 != 0)
25874 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25875 SmallVector<StringRef, 4> AsmPieces;
25876 SplitString(AsmStr, AsmPieces, ";\n");
25878 switch (AsmPieces.size()) {
25879 default: return false;
25881 // FIXME: this should verify that we are targeting a 486 or better. If not,
25882 // we will turn this bswap into something that will be lowered to logical
25883 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25884 // lower so don't worry about this.
25886 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25887 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25888 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25889 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25890 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25891 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25892 // No need to check constraints, nothing other than the equivalent of
25893 // "=r,0" would be valid here.
25894 return IntrinsicLowering::LowerToByteSwap(CI);
25897 // rorw $$8, ${0:w} --> llvm.bswap.i16
25898 if (CI->getType()->isIntegerTy(16) &&
25899 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25900 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25901 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25903 const std::string &ConstraintsStr = IA->getConstraintString();
25904 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25905 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25906 if (clobbersFlagRegisters(AsmPieces))
25907 return IntrinsicLowering::LowerToByteSwap(CI);
25911 if (CI->getType()->isIntegerTy(32) &&
25912 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25913 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25914 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25915 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25917 const std::string &ConstraintsStr = IA->getConstraintString();
25918 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25919 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25920 if (clobbersFlagRegisters(AsmPieces))
25921 return IntrinsicLowering::LowerToByteSwap(CI);
25924 if (CI->getType()->isIntegerTy(64)) {
25925 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25926 if (Constraints.size() >= 2 &&
25927 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25928 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25929 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25930 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25931 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25932 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25933 return IntrinsicLowering::LowerToByteSwap(CI);
25941 /// getConstraintType - Given a constraint letter, return the type of
25942 /// constraint it is for this target.
25943 X86TargetLowering::ConstraintType
25944 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25945 if (Constraint.size() == 1) {
25946 switch (Constraint[0]) {
25957 return C_RegisterClass;
25981 return TargetLowering::getConstraintType(Constraint);
25984 /// Examine constraint type and operand type and determine a weight value.
25985 /// This object must already have been set up with the operand type
25986 /// and the current alternative constraint selected.
25987 TargetLowering::ConstraintWeight
25988 X86TargetLowering::getSingleConstraintMatchWeight(
25989 AsmOperandInfo &info, const char *constraint) const {
25990 ConstraintWeight weight = CW_Invalid;
25991 Value *CallOperandVal = info.CallOperandVal;
25992 // If we don't have a value, we can't do a match,
25993 // but allow it at the lowest weight.
25994 if (!CallOperandVal)
25996 Type *type = CallOperandVal->getType();
25997 // Look at the constraint type.
25998 switch (*constraint) {
26000 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26011 if (CallOperandVal->getType()->isIntegerTy())
26012 weight = CW_SpecificReg;
26017 if (type->isFloatingPointTy())
26018 weight = CW_SpecificReg;
26021 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26022 weight = CW_SpecificReg;
26026 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26027 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26028 weight = CW_Register;
26031 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26032 if (C->getZExtValue() <= 31)
26033 weight = CW_Constant;
26037 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26038 if (C->getZExtValue() <= 63)
26039 weight = CW_Constant;
26043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26044 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26045 weight = CW_Constant;
26049 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26050 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26051 weight = CW_Constant;
26055 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26056 if (C->getZExtValue() <= 3)
26057 weight = CW_Constant;
26061 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26062 if (C->getZExtValue() <= 0xff)
26063 weight = CW_Constant;
26068 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26069 weight = CW_Constant;
26073 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26074 if ((C->getSExtValue() >= -0x80000000LL) &&
26075 (C->getSExtValue() <= 0x7fffffffLL))
26076 weight = CW_Constant;
26080 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26081 if (C->getZExtValue() <= 0xffffffff)
26082 weight = CW_Constant;
26089 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26090 /// with another that has more specific requirements based on the type of the
26091 /// corresponding operand.
26092 const char *X86TargetLowering::
26093 LowerXConstraint(EVT ConstraintVT) const {
26094 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26095 // 'f' like normal targets.
26096 if (ConstraintVT.isFloatingPoint()) {
26097 if (Subtarget->hasSSE2())
26099 if (Subtarget->hasSSE1())
26103 return TargetLowering::LowerXConstraint(ConstraintVT);
26106 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26107 /// vector. If it is invalid, don't add anything to Ops.
26108 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26109 std::string &Constraint,
26110 std::vector<SDValue>&Ops,
26111 SelectionDAG &DAG) const {
26114 // Only support length 1 constraints for now.
26115 if (Constraint.length() > 1) return;
26117 char ConstraintLetter = Constraint[0];
26118 switch (ConstraintLetter) {
26121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26122 if (C->getZExtValue() <= 31) {
26123 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26129 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26130 if (C->getZExtValue() <= 63) {
26131 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26138 if (isInt<8>(C->getSExtValue())) {
26139 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26146 if (C->getZExtValue() <= 255) {
26147 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26153 // 32-bit signed value
26154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26155 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26156 C->getSExtValue())) {
26157 // Widen to 64 bits here to get it sign extended.
26158 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26161 // FIXME gcc accepts some relocatable values here too, but only in certain
26162 // memory models; it's complicated.
26167 // 32-bit unsigned value
26168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26169 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26170 C->getZExtValue())) {
26171 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26175 // FIXME gcc accepts some relocatable values here too, but only in certain
26176 // memory models; it's complicated.
26180 // Literal immediates are always ok.
26181 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26182 // Widen to 64 bits here to get it sign extended.
26183 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26187 // In any sort of PIC mode addresses need to be computed at runtime by
26188 // adding in a register or some sort of table lookup. These can't
26189 // be used as immediates.
26190 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26193 // If we are in non-pic codegen mode, we allow the address of a global (with
26194 // an optional displacement) to be used with 'i'.
26195 GlobalAddressSDNode *GA = nullptr;
26196 int64_t Offset = 0;
26198 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26200 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26201 Offset += GA->getOffset();
26203 } else if (Op.getOpcode() == ISD::ADD) {
26204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26205 Offset += C->getZExtValue();
26206 Op = Op.getOperand(0);
26209 } else if (Op.getOpcode() == ISD::SUB) {
26210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26211 Offset += -C->getZExtValue();
26212 Op = Op.getOperand(0);
26217 // Otherwise, this isn't something we can handle, reject it.
26221 const GlobalValue *GV = GA->getGlobal();
26222 // If we require an extra load to get this address, as in PIC mode, we
26223 // can't accept it.
26224 if (isGlobalStubReference(
26225 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26228 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26229 GA->getValueType(0), Offset);
26234 if (Result.getNode()) {
26235 Ops.push_back(Result);
26238 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26241 std::pair<unsigned, const TargetRegisterClass*>
26242 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26244 // First, see if this is a constraint that directly corresponds to an LLVM
26246 if (Constraint.size() == 1) {
26247 // GCC Constraint Letters
26248 switch (Constraint[0]) {
26250 // TODO: Slight differences here in allocation order and leaving
26251 // RIP in the class. Do they matter any more here than they do
26252 // in the normal allocation?
26253 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26254 if (Subtarget->is64Bit()) {
26255 if (VT == MVT::i32 || VT == MVT::f32)
26256 return std::make_pair(0U, &X86::GR32RegClass);
26257 if (VT == MVT::i16)
26258 return std::make_pair(0U, &X86::GR16RegClass);
26259 if (VT == MVT::i8 || VT == MVT::i1)
26260 return std::make_pair(0U, &X86::GR8RegClass);
26261 if (VT == MVT::i64 || VT == MVT::f64)
26262 return std::make_pair(0U, &X86::GR64RegClass);
26265 // 32-bit fallthrough
26266 case 'Q': // Q_REGS
26267 if (VT == MVT::i32 || VT == MVT::f32)
26268 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26269 if (VT == MVT::i16)
26270 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26271 if (VT == MVT::i8 || VT == MVT::i1)
26272 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26273 if (VT == MVT::i64)
26274 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26276 case 'r': // GENERAL_REGS
26277 case 'l': // INDEX_REGS
26278 if (VT == MVT::i8 || VT == MVT::i1)
26279 return std::make_pair(0U, &X86::GR8RegClass);
26280 if (VT == MVT::i16)
26281 return std::make_pair(0U, &X86::GR16RegClass);
26282 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26283 return std::make_pair(0U, &X86::GR32RegClass);
26284 return std::make_pair(0U, &X86::GR64RegClass);
26285 case 'R': // LEGACY_REGS
26286 if (VT == MVT::i8 || VT == MVT::i1)
26287 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26288 if (VT == MVT::i16)
26289 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26290 if (VT == MVT::i32 || !Subtarget->is64Bit())
26291 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26292 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26293 case 'f': // FP Stack registers.
26294 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26295 // value to the correct fpstack register class.
26296 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26297 return std::make_pair(0U, &X86::RFP32RegClass);
26298 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26299 return std::make_pair(0U, &X86::RFP64RegClass);
26300 return std::make_pair(0U, &X86::RFP80RegClass);
26301 case 'y': // MMX_REGS if MMX allowed.
26302 if (!Subtarget->hasMMX()) break;
26303 return std::make_pair(0U, &X86::VR64RegClass);
26304 case 'Y': // SSE_REGS if SSE2 allowed
26305 if (!Subtarget->hasSSE2()) break;
26307 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26308 if (!Subtarget->hasSSE1()) break;
26310 switch (VT.SimpleTy) {
26312 // Scalar SSE types.
26315 return std::make_pair(0U, &X86::FR32RegClass);
26318 return std::make_pair(0U, &X86::FR64RegClass);
26326 return std::make_pair(0U, &X86::VR128RegClass);
26334 return std::make_pair(0U, &X86::VR256RegClass);
26339 return std::make_pair(0U, &X86::VR512RegClass);
26345 // Use the default implementation in TargetLowering to convert the register
26346 // constraint into a member of a register class.
26347 std::pair<unsigned, const TargetRegisterClass*> Res;
26348 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26350 // Not found as a standard register?
26352 // Map st(0) -> st(7) -> ST0
26353 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26354 tolower(Constraint[1]) == 's' &&
26355 tolower(Constraint[2]) == 't' &&
26356 Constraint[3] == '(' &&
26357 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26358 Constraint[5] == ')' &&
26359 Constraint[6] == '}') {
26361 Res.first = X86::FP0+Constraint[4]-'0';
26362 Res.second = &X86::RFP80RegClass;
26366 // GCC allows "st(0)" to be called just plain "st".
26367 if (StringRef("{st}").equals_lower(Constraint)) {
26368 Res.first = X86::FP0;
26369 Res.second = &X86::RFP80RegClass;
26374 if (StringRef("{flags}").equals_lower(Constraint)) {
26375 Res.first = X86::EFLAGS;
26376 Res.second = &X86::CCRRegClass;
26380 // 'A' means EAX + EDX.
26381 if (Constraint == "A") {
26382 Res.first = X86::EAX;
26383 Res.second = &X86::GR32_ADRegClass;
26389 // Otherwise, check to see if this is a register class of the wrong value
26390 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26391 // turn into {ax},{dx}.
26392 if (Res.second->hasType(VT))
26393 return Res; // Correct type already, nothing to do.
26395 // All of the single-register GCC register classes map their values onto
26396 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26397 // really want an 8-bit or 32-bit register, map to the appropriate register
26398 // class and return the appropriate register.
26399 if (Res.second == &X86::GR16RegClass) {
26400 if (VT == MVT::i8 || VT == MVT::i1) {
26401 unsigned DestReg = 0;
26402 switch (Res.first) {
26404 case X86::AX: DestReg = X86::AL; break;
26405 case X86::DX: DestReg = X86::DL; break;
26406 case X86::CX: DestReg = X86::CL; break;
26407 case X86::BX: DestReg = X86::BL; break;
26410 Res.first = DestReg;
26411 Res.second = &X86::GR8RegClass;
26413 } else if (VT == MVT::i32 || VT == MVT::f32) {
26414 unsigned DestReg = 0;
26415 switch (Res.first) {
26417 case X86::AX: DestReg = X86::EAX; break;
26418 case X86::DX: DestReg = X86::EDX; break;
26419 case X86::CX: DestReg = X86::ECX; break;
26420 case X86::BX: DestReg = X86::EBX; break;
26421 case X86::SI: DestReg = X86::ESI; break;
26422 case X86::DI: DestReg = X86::EDI; break;
26423 case X86::BP: DestReg = X86::EBP; break;
26424 case X86::SP: DestReg = X86::ESP; break;
26427 Res.first = DestReg;
26428 Res.second = &X86::GR32RegClass;
26430 } else if (VT == MVT::i64 || VT == MVT::f64) {
26431 unsigned DestReg = 0;
26432 switch (Res.first) {
26434 case X86::AX: DestReg = X86::RAX; break;
26435 case X86::DX: DestReg = X86::RDX; break;
26436 case X86::CX: DestReg = X86::RCX; break;
26437 case X86::BX: DestReg = X86::RBX; break;
26438 case X86::SI: DestReg = X86::RSI; break;
26439 case X86::DI: DestReg = X86::RDI; break;
26440 case X86::BP: DestReg = X86::RBP; break;
26441 case X86::SP: DestReg = X86::RSP; break;
26444 Res.first = DestReg;
26445 Res.second = &X86::GR64RegClass;
26448 } else if (Res.second == &X86::FR32RegClass ||
26449 Res.second == &X86::FR64RegClass ||
26450 Res.second == &X86::VR128RegClass ||
26451 Res.second == &X86::VR256RegClass ||
26452 Res.second == &X86::FR32XRegClass ||
26453 Res.second == &X86::FR64XRegClass ||
26454 Res.second == &X86::VR128XRegClass ||
26455 Res.second == &X86::VR256XRegClass ||
26456 Res.second == &X86::VR512RegClass) {
26457 // Handle references to XMM physical registers that got mapped into the
26458 // wrong class. This can happen with constraints like {xmm0} where the
26459 // target independent register mapper will just pick the first match it can
26460 // find, ignoring the required type.
26462 if (VT == MVT::f32 || VT == MVT::i32)
26463 Res.second = &X86::FR32RegClass;
26464 else if (VT == MVT::f64 || VT == MVT::i64)
26465 Res.second = &X86::FR64RegClass;
26466 else if (X86::VR128RegClass.hasType(VT))
26467 Res.second = &X86::VR128RegClass;
26468 else if (X86::VR256RegClass.hasType(VT))
26469 Res.second = &X86::VR256RegClass;
26470 else if (X86::VR512RegClass.hasType(VT))
26471 Res.second = &X86::VR512RegClass;
26477 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26479 // Scaling factors are not free at all.
26480 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26481 // will take 2 allocations in the out of order engine instead of 1
26482 // for plain addressing mode, i.e. inst (reg1).
26484 // vaddps (%rsi,%drx), %ymm0, %ymm1
26485 // Requires two allocations (one for the load, one for the computation)
26487 // vaddps (%rsi), %ymm0, %ymm1
26488 // Requires just 1 allocation, i.e., freeing allocations for other operations
26489 // and having less micro operations to execute.
26491 // For some X86 architectures, this is even worse because for instance for
26492 // stores, the complex addressing mode forces the instruction to use the
26493 // "load" ports instead of the dedicated "store" port.
26494 // E.g., on Haswell:
26495 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26496 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26497 if (isLegalAddressingMode(AM, Ty))
26498 // Scale represents reg2 * scale, thus account for 1
26499 // as soon as we use a second register.
26500 return AM.Scale != 0;
26504 bool X86TargetLowering::isTargetFTOL() const {
26505 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();