1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Only provide customized ctpop vector bit twiddling for vector types we
991 // know to perform better than using the popcnt instructions on each vector
992 // element. If popcnt isn't supported, always provide the custom version.
993 if (!Subtarget->hasPOPCNT()) {
994 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
995 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
998 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
999 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1000 MVT VT = (MVT::SimpleValueType)i;
1001 // Do not attempt to custom lower non-power-of-2 vectors
1002 if (!isPowerOf2_32(VT.getVectorNumElements()))
1004 // Do not attempt to custom lower non-128-bit vectors
1005 if (!VT.is128BitVector())
1007 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012 // We support custom legalizing of sext and anyext loads for specific
1013 // memory vector types which we can load as a scalar (or sequence of
1014 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1015 // loads these must work with a single scalar load.
1016 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1026 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1027 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1028 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1033 if (Subtarget->is64Bit()) {
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1038 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1039 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1040 MVT VT = (MVT::SimpleValueType)i;
1042 // Do not attempt to promote non-128-bit vectors
1043 if (!VT.is128BitVector())
1046 setOperationAction(ISD::AND, VT, Promote);
1047 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1048 setOperationAction(ISD::OR, VT, Promote);
1049 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1050 setOperationAction(ISD::XOR, VT, Promote);
1051 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1052 setOperationAction(ISD::LOAD, VT, Promote);
1053 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1054 setOperationAction(ISD::SELECT, VT, Promote);
1055 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1058 // Custom lower v2i64 and v2f64 selects.
1059 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1069 // As there is no 64-bit GPR available, we need build a special custom
1070 // sequence to convert from v2i32 to v2f32.
1071 if (!Subtarget->is64Bit())
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1074 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1075 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1077 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1079 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1080 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1081 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1084 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1085 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1090 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1107 // FIXME: Do we need to handle scalar-to-vector here?
1108 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1110 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1114 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1115 // There is no BLENDI for byte vectors. We don't need to custom lower
1116 // some vselects for now.
1117 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1119 // SSE41 brings specific instructions for doing vector sign extend even in
1120 // cases where we don't have SRA.
1121 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1122 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1123 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1125 // i8 and i16 vectors are custom because the source register and source
1126 // source memory operand types are not the same width. f32 vectors are
1127 // custom since the immediate controlling the insert encodes additional
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1139 // FIXME: these should be Legal, but that's only for the case where
1140 // the index is constant. For now custom expand to deal with that.
1141 if (Subtarget->is64Bit()) {
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1147 if (Subtarget->hasSSE2()) {
1148 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1154 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1157 // In the customized shift lowering, the legal cases in AVX2 will be
1159 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1163 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1165 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1168 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1169 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1172 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1173 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1176 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1180 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1191 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1193 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1204 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1206 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1207 // even though v8i16 is a legal type.
1208 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1209 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1210 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1212 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1213 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1214 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1216 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1217 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1219 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1221 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1235 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1242 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1254 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1255 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1257 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1258 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1260 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1261 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1262 setOperationAction(ISD::FMA, MVT::f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::f64, Legal);
1266 if (Subtarget->hasInt256()) {
1267 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1268 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1269 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1270 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1272 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1273 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1274 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1275 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1277 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1280 // Don't lower v32i8 because there is no 128-bit byte mul
1282 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1284 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1285 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1287 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1288 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1290 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1291 // when we have a 256bit-wide blend with immediate.
1292 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1294 // Only provide customized ctpop vector bit twiddling for vector types we
1295 // know to perform better than using the popcnt instructions on each
1296 // vector element. If popcnt isn't supported, always provide the custom
1298 if (!Subtarget->hasPOPCNT())
1299 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1301 // Custom CTPOP always performs better on natively supported v8i32
1302 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1305 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1306 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1307 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1309 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1312 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1314 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1317 // Don't lower v32i8 because there is no 128-bit byte mul
1320 // In the customized shift lowering, the legal cases in AVX2 will be
1322 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1323 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1325 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1330 // Custom lower several nodes for 256-bit types.
1331 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1332 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1333 MVT VT = (MVT::SimpleValueType)i;
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1434 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1435 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1439 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1445 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1446 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1506 // Custom lower several nodes.
1507 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1508 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1509 MVT VT = (MVT::SimpleValueType)i;
1511 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Extract subvector is special because the value type
1513 // (result) is 256/128-bit but the source is 512-bit wide.
1514 if (VT.is128BitVector() || VT.is256BitVector()) {
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1517 if (VT.getVectorElementType() == MVT::i1)
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1520 // Do not attempt to custom lower other non-512-bit vectors
1521 if (!VT.is512BitVector())
1524 if ( EltSize >= 32) {
1525 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1528 setOperationAction(ISD::VSELECT, VT, Legal);
1529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1532 setOperationAction(ISD::MLOAD, VT, Legal);
1533 setOperationAction(ISD::MSTORE, VT, Legal);
1536 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1537 MVT VT = (MVT::SimpleValueType)i;
1539 // Do not attempt to promote non-256-bit vectors.
1540 if (!VT.is512BitVector())
1543 setOperationAction(ISD::SELECT, VT, Promote);
1544 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1548 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1549 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1550 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1553 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1555 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1556 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1557 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1558 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1559 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1560 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1561 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1562 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1563 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1565 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1566 const MVT VT = (MVT::SimpleValueType)i;
1568 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1570 // Do not attempt to promote non-256-bit vectors.
1571 if (!VT.is512BitVector())
1575 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1576 setOperationAction(ISD::VSELECT, VT, Legal);
1581 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1582 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1583 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1585 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1586 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1589 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1590 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1591 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1592 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1597 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1598 // of this type with custom code.
1599 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1600 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1601 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 bool NoImplicitFloatOps = Fn->getAttributes().hasAttribute(
2554 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2555 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2556 "SSE register cannot be used when SSE is disabled!");
2558 // 64-bit calling conventions support varargs and register parameters, so we
2559 // have to do extra work to spill them in the prologue.
2560 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2561 // Find the first unallocated argument registers.
2562 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2563 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2564 unsigned NumIntRegs =
2565 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2566 unsigned NumXMMRegs =
2567 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2568 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // Gather all the live in physical registers.
2572 SmallVector<SDValue, 6> LiveGPRs;
2573 SmallVector<SDValue, 8> LiveXMMRegs;
2575 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2576 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2578 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2580 if (!ArgXMMs.empty()) {
2581 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2582 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2583 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2584 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2585 LiveXMMRegs.push_back(
2586 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2591 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(
2596 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2597 // Fixup to set vararg frame on shadow area (4 x i64).
2599 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2601 // For X86-64, if there are vararg parameters that are passed via
2602 // registers, then we must store them to their spots on the stack so
2603 // they may be loaded by deferencing the result of va_next.
2604 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2605 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2606 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2607 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2610 // Store the integer parameter registers.
2611 SmallVector<SDValue, 8> MemOps;
2612 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2614 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2615 for (SDValue Val : LiveGPRs) {
2616 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2617 DAG.getIntPtrConstant(Offset));
2619 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo::getFixedStack(
2621 FuncInfo->getRegSaveFrameIndex(), Offset),
2623 MemOps.push_back(Store);
2627 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2628 // Now store the XMM (fp + vector) parameter registers.
2629 SmallVector<SDValue, 12> SaveXMMOps;
2630 SaveXMMOps.push_back(Chain);
2631 SaveXMMOps.push_back(ALVal);
2632 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2633 FuncInfo->getRegSaveFrameIndex()));
2634 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2635 FuncInfo->getVarArgsFPOffset()));
2636 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2638 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2639 MVT::Other, SaveXMMOps));
2642 if (!MemOps.empty())
2643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2646 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2647 // Find the largest legal vector type.
2648 MVT VecVT = MVT::Other;
2649 // FIXME: Only some x86_32 calling conventions support AVX512.
2650 if (Subtarget->hasAVX512() &&
2651 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2652 CallConv == CallingConv::Intel_OCL_BI)))
2653 VecVT = MVT::v16f32;
2654 else if (Subtarget->hasAVX())
2656 else if (Subtarget->hasSSE2())
2659 // We forward some GPRs and some vector types.
2660 SmallVector<MVT, 2> RegParmTypes;
2661 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2662 RegParmTypes.push_back(IntVT);
2663 if (VecVT != MVT::Other)
2664 RegParmTypes.push_back(VecVT);
2666 // Compute the set of forwarded registers. The rest are scratch.
2667 SmallVectorImpl<ForwardedRegister> &Forwards =
2668 FuncInfo->getForwardedMustTailRegParms();
2669 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2671 // Conservatively forward AL on x86_64, since it might be used for varargs.
2672 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2673 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2674 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2677 // Copy all forwards from physical to virtual registers.
2678 for (ForwardedRegister &F : Forwards) {
2679 // FIXME: Can we use a less constrained schedule?
2680 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2681 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2682 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2686 // Some CCs need callee pop.
2687 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2688 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2689 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2691 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2692 // If this is an sret function, the return should pop the hidden pointer.
2693 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2694 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2695 argsAreStructReturn(Ins) == StackStructReturn)
2696 FuncInfo->setBytesToPopOnReturn(4);
2700 // RegSaveFrameIndex is X86-64 only.
2701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2702 if (CallConv == CallingConv::X86_FastCall ||
2703 CallConv == CallingConv::X86_ThisCall)
2704 // fastcc functions can't have varargs.
2705 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2708 FuncInfo->setArgumentStackSize(StackSize);
2714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2715 SDValue StackPtr, SDValue Arg,
2716 SDLoc dl, SelectionDAG &DAG,
2717 const CCValAssign &VA,
2718 ISD::ArgFlagsTy Flags) const {
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2721 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2722 if (Flags.isByVal())
2723 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2725 return DAG.getStore(Chain, dl, Arg, PtrOff,
2726 MachinePointerInfo::getStack(LocMemOffset),
2730 /// Emit a load of return address if tail call
2731 /// optimization is performed and it is required.
2733 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2734 SDValue &OutRetAddr, SDValue Chain,
2735 bool IsTailCall, bool Is64Bit,
2736 int FPDiff, SDLoc dl) const {
2737 // Adjust the Return address stack slot.
2738 EVT VT = getPointerTy();
2739 OutRetAddr = getReturnAddressFrameIndex(DAG);
2741 // Load the "old" Return address.
2742 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2743 false, false, false, 0);
2744 return SDValue(OutRetAddr.getNode(), 1);
2747 /// Emit a store of the return address if tail call
2748 /// optimization is performed and it is required (FPDiff!=0).
2749 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2750 SDValue Chain, SDValue RetAddrFrIdx,
2751 EVT PtrVT, unsigned SlotSize,
2752 int FPDiff, SDLoc dl) {
2753 // Store the return address to the appropriate stack slot.
2754 if (!FPDiff) return Chain;
2755 // Calculate the new stack slot for the return address.
2756 int NewReturnAddrFI =
2757 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2759 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2760 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2761 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2767 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2768 SmallVectorImpl<SDValue> &InVals) const {
2769 SelectionDAG &DAG = CLI.DAG;
2771 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2772 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2773 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2774 SDValue Chain = CLI.Chain;
2775 SDValue Callee = CLI.Callee;
2776 CallingConv::ID CallConv = CLI.CallConv;
2777 bool &isTailCall = CLI.IsTailCall;
2778 bool isVarArg = CLI.IsVarArg;
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 bool Is64Bit = Subtarget->is64Bit();
2782 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2783 StructReturnType SR = callIsStructReturn(Outs);
2784 bool IsSibcall = false;
2785 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2787 if (MF.getTarget().Options.DisableTailCalls)
2790 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2792 // Force this to be a tail call. The verifier rules are enough to ensure
2793 // that we can lower this successfully without moving the return address
2796 } else if (isTailCall) {
2797 // Check if it's really possible to do a tail call.
2798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2799 isVarArg, SR != NotStructReturn,
2800 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2801 Outs, OutVals, Ins, DAG);
2803 // Sibcalls are automatically detected tailcalls which do not require
2805 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2813 "Var args not supported with calling convention fastcc, ghc or hipe");
2815 // Analyze operands of the call, assigning locations to each operand.
2816 SmallVector<CCValAssign, 16> ArgLocs;
2817 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2821 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 // Get a count of how many bytes are to be pushed on the stack.
2826 unsigned NumBytes = CCInfo.getNextStackOffset();
2828 // This is a sibcall. The memory operands are available in caller's
2829 // own caller's stack.
2831 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2832 IsTailCallConvention(CallConv))
2833 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2836 if (isTailCall && !IsSibcall && !IsMustTail) {
2837 // Lower arguments at fp - stackoffset + fpdiff.
2838 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2840 FPDiff = NumBytesCallerPushed - NumBytes;
2842 // Set the delta of movement of the returnaddr stackslot.
2843 // But only set if delta is greater than previous delta.
2844 if (FPDiff < X86Info->getTCReturnAddrDelta())
2845 X86Info->setTCReturnAddrDelta(FPDiff);
2848 unsigned NumBytesToPush = NumBytes;
2849 unsigned NumBytesToPop = NumBytes;
2851 // If we have an inalloca argument, all stack space has already been allocated
2852 // for us and be right at the top of the stack. We don't support multiple
2853 // arguments passed in memory when using inalloca.
2854 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2856 if (!ArgLocs.back().isMemLoc())
2857 report_fatal_error("cannot use inalloca attribute on a register "
2859 if (ArgLocs.back().getLocMemOffset() != 0)
2860 report_fatal_error("any parameter with the inalloca attribute must be "
2861 "the only memory argument");
2865 Chain = DAG.getCALLSEQ_START(
2866 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2868 SDValue RetAddrFrIdx;
2869 // Load return address for tail calls.
2870 if (isTailCall && FPDiff)
2871 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2872 Is64Bit, FPDiff, dl);
2874 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2875 SmallVector<SDValue, 8> MemOpChains;
2878 // Walk the register/memloc assignments, inserting copies/loads. In the case
2879 // of tail call optimization arguments are handle later.
2880 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2881 DAG.getSubtarget().getRegisterInfo());
2882 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2883 // Skip inalloca arguments, they have already been written.
2884 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2885 if (Flags.isInAlloca())
2888 CCValAssign &VA = ArgLocs[i];
2889 EVT RegVT = VA.getLocVT();
2890 SDValue Arg = OutVals[i];
2891 bool isByVal = Flags.isByVal();
2893 // Promote the value if needed.
2894 switch (VA.getLocInfo()) {
2895 default: llvm_unreachable("Unknown loc info!");
2896 case CCValAssign::Full: break;
2897 case CCValAssign::SExt:
2898 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::ZExt:
2901 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2903 case CCValAssign::AExt:
2904 if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2973 !G->getGlobal()->hasProtectedVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, MVT::i8)));
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 // We should use extra load for direct calls to dllimported functions in
3093 const GlobalValue *GV = G->getGlobal();
3094 if (!GV->hasDLLImportStorageClass()) {
3095 unsigned char OpFlags = 0;
3096 bool ExtraLoad = false;
3097 unsigned WrapperKind = ISD::DELETED_NODE;
3099 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3100 // external symbols most go through the PLT in PIC mode. If the symbol
3101 // has hidden or protected visibility, or if it is static or local, then
3102 // we don't need to use the PLT - we can directly call it.
3103 if (Subtarget->isTargetELF() &&
3104 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3105 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3109 (!Subtarget->getTargetTriple().isMacOSX() ||
3110 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3111 // PC-relative references to external symbols should go through $stub,
3112 // unless we're building with the leopard linker or later, which
3113 // automatically synthesizes these stubs.
3114 OpFlags = X86II::MO_DARWIN_STUB;
3115 } else if (Subtarget->isPICStyleRIPRel() &&
3116 isa<Function>(GV) &&
3117 cast<Function>(GV)->getAttributes().
3118 hasAttribute(AttributeSet::FunctionIndex,
3119 Attribute::NonLazyBind)) {
3120 // If the function is marked as non-lazy, generate an indirect call
3121 // which loads from the GOT directly. This avoids runtime overhead
3122 // at the cost of eager binding (and one extra byte of encoding).
3123 OpFlags = X86II::MO_GOTPCREL;
3124 WrapperKind = X86ISD::WrapperRIP;
3128 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3129 G->getOffset(), OpFlags);
3131 // Add a wrapper if needed.
3132 if (WrapperKind != ISD::DELETED_NODE)
3133 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3134 // Add extra indirection if needed.
3136 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3137 MachinePointerInfo::getGOT(),
3138 false, false, false, 0);
3140 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3141 unsigned char OpFlags = 0;
3143 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3144 // external symbols should go through the PLT.
3145 if (Subtarget->isTargetELF() &&
3146 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3147 OpFlags = X86II::MO_PLT;
3148 } else if (Subtarget->isPICStyleStubAny() &&
3149 (!Subtarget->getTargetTriple().isMacOSX() ||
3150 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3151 // PC-relative references to external symbols should go through $stub,
3152 // unless we're building with the leopard linker or later, which
3153 // automatically synthesizes these stubs.
3154 OpFlags = X86II::MO_DARWIN_STUB;
3157 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3159 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, true),
3171 DAG.getIntPtrConstant(0, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 MachineFunction &MF = DAG.getMachineFunction();
3278 const TargetMachine &TM = MF.getTarget();
3279 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3280 TM.getSubtargetImpl()->getRegisterInfo());
3281 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3319 Def->getOperand(1).isFI()) {
3320 FI = Def->getOperand(1).getIndex();
3321 Bytes = Flags.getByValSize();
3325 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3326 if (Flags.isByVal())
3327 // ByVal argument is passed in as a pointer but it's now being
3328 // dereferenced. e.g.
3329 // define @foo(%struct.X* %A) {
3330 // tail call @bar(%struct.X* byval %A)
3333 SDValue Ptr = Ld->getBasePtr();
3334 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3337 FI = FINode->getIndex();
3338 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3339 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3340 FI = FINode->getIndex();
3341 Bytes = Flags.getByValSize();
3345 assert(FI != INT_MAX);
3346 if (!MFI->isFixedObjectIndex(FI))
3348 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3351 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3352 /// for tail call optimization. Targets which want to do tail call
3353 /// optimization should implement this function.
3355 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3356 CallingConv::ID CalleeCC,
3358 bool isCalleeStructRet,
3359 bool isCallerStructRet,
3361 const SmallVectorImpl<ISD::OutputArg> &Outs,
3362 const SmallVectorImpl<SDValue> &OutVals,
3363 const SmallVectorImpl<ISD::InputArg> &Ins,
3364 SelectionDAG &DAG) const {
3365 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3368 // If -tailcallopt is specified, make fastcc functions tail-callable.
3369 const MachineFunction &MF = DAG.getMachineFunction();
3370 const Function *CallerF = MF.getFunction();
3372 // If the function return type is x86_fp80 and the callee return type is not,
3373 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3374 // perform a tailcall optimization here.
3375 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3378 CallingConv::ID CallerCC = CallerF->getCallingConv();
3379 bool CCMatch = CallerCC == CalleeCC;
3380 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3381 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3383 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3384 if (IsTailCallConvention(CalleeCC) && CCMatch)
3389 // Look for obvious safe cases to perform tail call optimization that do not
3390 // require ABI changes. This is what gcc calls sibcall.
3392 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3393 // emit a special epilogue.
3394 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3395 DAG.getSubtarget().getRegisterInfo());
3396 if (RegInfo->needsStackRealignment(MF))
3399 // Also avoid sibcall optimization if either caller or callee uses struct
3400 // return semantics.
3401 if (isCalleeStructRet || isCallerStructRet)
3404 // An stdcall/thiscall caller is expected to clean up its arguments; the
3405 // callee isn't going to do that.
3406 // FIXME: this is more restrictive than needed. We could produce a tailcall
3407 // when the stack adjustment matches. For example, with a thiscall that takes
3408 // only one argument.
3409 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3410 CallerCC == CallingConv::X86_ThisCall))
3413 // Do not sibcall optimize vararg calls unless all arguments are passed via
3415 if (isVarArg && !Outs.empty()) {
3417 // Optimizing for varargs on Win64 is unlikely to be safe without
3418 // additional testing.
3419 if (IsCalleeWin64 || IsCallerWin64)
3422 SmallVector<CCValAssign, 16> ArgLocs;
3423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3426 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3428 if (!ArgLocs[i].isRegLoc())
3432 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3433 // stack. Therefore, if it's not used by the call it is not safe to optimize
3434 // this into a sibcall.
3435 bool Unused = false;
3436 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3443 SmallVector<CCValAssign, 16> RVLocs;
3444 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3446 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3447 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = RVLocs[i];
3449 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3454 // If the calling conventions do not match, then we'd better make sure the
3455 // results are returned in the same way as what the caller expects.
3457 SmallVector<CCValAssign, 16> RVLocs1;
3458 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3460 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3462 SmallVector<CCValAssign, 16> RVLocs2;
3463 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3465 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3467 if (RVLocs1.size() != RVLocs2.size())
3469 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3470 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3472 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3474 if (RVLocs1[i].isRegLoc()) {
3475 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3478 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3484 // If the callee takes no arguments then go on to check the results of the
3486 if (!Outs.empty()) {
3487 // Check if stack adjustment is needed. For now, do not do this if any
3488 // argument is passed on the stack.
3489 SmallVector<CCValAssign, 16> ArgLocs;
3490 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3493 // Allocate shadow area for Win64
3495 CCInfo.AllocateStack(32, 8);
3497 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3498 if (CCInfo.getNextStackOffset()) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3503 // Check if the arguments are already laid out in the right way as
3504 // the caller's fixed stack objects.
3505 MachineFrameInfo *MFI = MF.getFrameInfo();
3506 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3507 const X86InstrInfo *TII =
3508 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = ArgLocs[i];
3511 SDValue Arg = OutVals[i];
3512 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3513 if (VA.getLocInfo() == CCValAssign::Indirect)
3515 if (!VA.isRegLoc()) {
3516 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3523 // If the tailcall address may be in a register, then make sure it's
3524 // possible to register allocate for it. In 32-bit, the call address can
3525 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3526 // callee-saved registers are restored. These happen to be the same
3527 // registers used to pass 'inreg' arguments so watch out for those.
3528 if (!Subtarget->is64Bit() &&
3529 ((!isa<GlobalAddressSDNode>(Callee) &&
3530 !isa<ExternalSymbolSDNode>(Callee)) ||
3531 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3532 unsigned NumInRegs = 0;
3533 // In PIC we need an extra register to formulate the address computation
3535 unsigned MaxInRegs =
3536 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3538 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3539 CCValAssign &VA = ArgLocs[i];
3542 unsigned Reg = VA.getLocReg();
3545 case X86::EAX: case X86::EDX: case X86::ECX:
3546 if (++NumInRegs == MaxInRegs)
3558 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3559 const TargetLibraryInfo *libInfo) const {
3560 return X86::createFastISel(funcInfo, libInfo);
3563 //===----------------------------------------------------------------------===//
3564 // Other Lowering Hooks
3565 //===----------------------------------------------------------------------===//
3567 static bool MayFoldLoad(SDValue Op) {
3568 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3571 static bool MayFoldIntoStore(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3575 static bool isTargetShuffle(unsigned Opcode) {
3577 default: return false;
3578 case X86ISD::BLENDI:
3579 case X86ISD::PSHUFB:
3580 case X86ISD::PSHUFD:
3581 case X86ISD::PSHUFHW:
3582 case X86ISD::PSHUFLW:
3584 case X86ISD::PALIGNR:
3585 case X86ISD::MOVLHPS:
3586 case X86ISD::MOVLHPD:
3587 case X86ISD::MOVHLPS:
3588 case X86ISD::MOVLPS:
3589 case X86ISD::MOVLPD:
3590 case X86ISD::MOVSHDUP:
3591 case X86ISD::MOVSLDUP:
3592 case X86ISD::MOVDDUP:
3595 case X86ISD::UNPCKL:
3596 case X86ISD::UNPCKH:
3597 case X86ISD::VPERMILPI:
3598 case X86ISD::VPERM2X128:
3599 case X86ISD::VPERMI:
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVSHDUP:
3609 case X86ISD::MOVSLDUP:
3610 case X86ISD::MOVDDUP:
3611 return DAG.getNode(Opc, dl, VT, V1);
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, unsigned TargetMask,
3617 SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::PSHUFD:
3621 case X86ISD::PSHUFHW:
3622 case X86ISD::PSHUFLW:
3623 case X86ISD::VPERMILPI:
3624 case X86ISD::VPERMI:
3625 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3629 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3630 SDValue V1, SDValue V2, unsigned TargetMask,
3631 SelectionDAG &DAG) {
3633 default: llvm_unreachable("Unknown x86 shuffle node");
3634 case X86ISD::PALIGNR:
3635 case X86ISD::VALIGN:
3637 case X86ISD::VPERM2X128:
3638 return DAG.getNode(Opc, dl, VT, V1, V2,
3639 DAG.getConstant(TargetMask, MVT::i8));
3643 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3644 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3646 default: llvm_unreachable("Unknown x86 shuffle node");
3647 case X86ISD::MOVLHPS:
3648 case X86ISD::MOVLHPD:
3649 case X86ISD::MOVHLPS:
3650 case X86ISD::MOVLPS:
3651 case X86ISD::MOVLPD:
3654 case X86ISD::UNPCKL:
3655 case X86ISD::UNPCKH:
3656 return DAG.getNode(Opc, dl, VT, V1, V2);
3660 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3661 MachineFunction &MF = DAG.getMachineFunction();
3662 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3663 DAG.getSubtarget().getRegisterInfo());
3664 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3665 int ReturnAddrIndex = FuncInfo->getRAIndex();
3667 if (ReturnAddrIndex == 0) {
3668 // Set up a frame object for the return address.
3669 unsigned SlotSize = RegInfo->getSlotSize();
3670 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3673 FuncInfo->setRAIndex(ReturnAddrIndex);
3676 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3679 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3680 bool hasSymbolicDisplacement) {
3681 // Offset should fit into 32 bit immediate field.
3682 if (!isInt<32>(Offset))
3685 // If we don't have a symbolic displacement - we don't have any extra
3687 if (!hasSymbolicDisplacement)
3690 // FIXME: Some tweaks might be needed for medium code model.
3691 if (M != CodeModel::Small && M != CodeModel::Kernel)
3694 // For small code model we assume that latest object is 16MB before end of 31
3695 // bits boundary. We may also accept pretty large negative constants knowing
3696 // that all objects are in the positive half of address space.
3697 if (M == CodeModel::Small && Offset < 16*1024*1024)
3700 // For kernel code model we know that all object resist in the negative half
3701 // of 32bits address space. We may not accept negative offsets, since they may
3702 // be just off and we may accept pretty large positive ones.
3703 if (M == CodeModel::Kernel && Offset >= 0)
3709 /// isCalleePop - Determines whether the callee is required to pop its
3710 /// own arguments. Callee pop is necessary to support tail calls.
3711 bool X86::isCalleePop(CallingConv::ID CallingConv,
3712 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3713 switch (CallingConv) {
3716 case CallingConv::X86_StdCall:
3717 case CallingConv::X86_FastCall:
3718 case CallingConv::X86_ThisCall:
3720 case CallingConv::Fast:
3721 case CallingConv::GHC:
3722 case CallingConv::HiPE:
3729 /// \brief Return true if the condition is an unsigned comparison operation.
3730 static bool isX86CCUnsigned(unsigned X86CC) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case X86::COND_E: return true;
3734 case X86::COND_G: return false;
3735 case X86::COND_GE: return false;
3736 case X86::COND_L: return false;
3737 case X86::COND_LE: return false;
3738 case X86::COND_NE: return true;
3739 case X86::COND_B: return true;
3740 case X86::COND_A: return true;
3741 case X86::COND_BE: return true;
3742 case X86::COND_AE: return true;
3744 llvm_unreachable("covered switch fell through?!");
3747 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3748 /// specific condition code, returning the condition code and the LHS/RHS of the
3749 /// comparison to make.
3750 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3751 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3753 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3754 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3755 // X > -1 -> X == 0, jump !sign.
3756 RHS = DAG.getConstant(0, RHS.getValueType());
3757 return X86::COND_NS;
3759 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3760 // X < 0 -> X == 0, jump on sign.
3763 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_LE;
3770 switch (SetCCOpcode) {
3771 default: llvm_unreachable("Invalid integer condition!");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETGT: return X86::COND_G;
3774 case ISD::SETGE: return X86::COND_GE;
3775 case ISD::SETLT: return X86::COND_L;
3776 case ISD::SETLE: return X86::COND_LE;
3777 case ISD::SETNE: return X86::COND_NE;
3778 case ISD::SETULT: return X86::COND_B;
3779 case ISD::SETUGT: return X86::COND_A;
3780 case ISD::SETULE: return X86::COND_BE;
3781 case ISD::SETUGE: return X86::COND_AE;
3785 // First determine if it is required or is profitable to flip the operands.
3787 // If LHS is a foldable load, but RHS is not, flip the condition.
3788 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3789 !ISD::isNON_EXTLoad(RHS.getNode())) {
3790 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3791 std::swap(LHS, RHS);
3794 switch (SetCCOpcode) {
3800 std::swap(LHS, RHS);
3804 // On a floating point condition, the flags are set as follows:
3806 // 0 | 0 | 0 | X > Y
3807 // 0 | 0 | 1 | X < Y
3808 // 1 | 0 | 0 | X == Y
3809 // 1 | 1 | 1 | unordered
3810 switch (SetCCOpcode) {
3811 default: llvm_unreachable("Condcode should be pre-legalized away");
3813 case ISD::SETEQ: return X86::COND_E;
3814 case ISD::SETOLT: // flipped
3816 case ISD::SETGT: return X86::COND_A;
3817 case ISD::SETOLE: // flipped
3819 case ISD::SETGE: return X86::COND_AE;
3820 case ISD::SETUGT: // flipped
3822 case ISD::SETLT: return X86::COND_B;
3823 case ISD::SETUGE: // flipped
3825 case ISD::SETLE: return X86::COND_BE;
3827 case ISD::SETNE: return X86::COND_NE;
3828 case ISD::SETUO: return X86::COND_P;
3829 case ISD::SETO: return X86::COND_NP;
3831 case ISD::SETUNE: return X86::COND_INVALID;
3835 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3836 /// code. Current x86 isa includes the following FP cmov instructions:
3837 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3838 static bool hasFPCMov(unsigned X86CC) {
3854 /// isFPImmLegal - Returns true if the target can instruction select the
3855 /// specified FP immediate natively. If false, the legalizer will
3856 /// materialize the FP immediate as a load from a constant pool.
3857 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3858 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3859 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3865 /// \brief Returns true if it is beneficial to convert a load of a constant
3866 /// to just the constant itself.
3867 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3869 assert(Ty->isIntegerTy());
3871 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3872 if (BitSize == 0 || BitSize > 64)
3877 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3878 unsigned Index) const {
3879 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3882 return (Index == 0 || Index == ResVT.getVectorNumElements());
3885 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3886 /// the specified range (L, H].
3887 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3888 return (Val < 0) || (Val >= Low && Val < Hi);
3891 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3892 /// specified value.
3893 static bool isUndefOrEqual(int Val, int CmpVal) {
3894 return (Val < 0 || Val == CmpVal);
3897 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3898 /// from position Pos and ending in Pos+Size, falls within the specified
3899 /// sequential range (L, L+Pos]. or is undef.
3900 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3901 unsigned Pos, unsigned Size, int Low) {
3902 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3903 if (!isUndefOrEqual(Mask[i], Low))
3908 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3909 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3910 /// operand - by default will match for first operand.
3911 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3912 bool TestSecondOperand = false) {
3913 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3914 VT != MVT::v2f64 && VT != MVT::v2i64)
3917 unsigned NumElems = VT.getVectorNumElements();
3918 unsigned Lo = TestSecondOperand ? NumElems : 0;
3919 unsigned Hi = Lo + NumElems;
3921 for (unsigned i = 0; i < NumElems; ++i)
3922 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3928 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3929 /// is suitable for input to PSHUFHW.
3930 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3931 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3934 // Lower quadword copied in order or undef.
3935 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3938 // Upper quadword shuffled.
3939 for (unsigned i = 4; i != 8; ++i)
3940 if (!isUndefOrInRange(Mask[i], 4, 8))
3943 if (VT == MVT::v16i16) {
3944 // Lower quadword copied in order or undef.
3945 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3948 // Upper quadword shuffled.
3949 for (unsigned i = 12; i != 16; ++i)
3950 if (!isUndefOrInRange(Mask[i], 12, 16))
3957 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3958 /// is suitable for input to PSHUFLW.
3959 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3960 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3963 // Upper quadword copied in order.
3964 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3967 // Lower quadword shuffled.
3968 for (unsigned i = 0; i != 4; ++i)
3969 if (!isUndefOrInRange(Mask[i], 0, 4))
3972 if (VT == MVT::v16i16) {
3973 // Upper quadword copied in order.
3974 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3977 // Lower quadword shuffled.
3978 for (unsigned i = 8; i != 12; ++i)
3979 if (!isUndefOrInRange(Mask[i], 8, 12))
3986 /// \brief Return true if the mask specifies a shuffle of elements that is
3987 /// suitable for input to intralane (palignr) or interlane (valign) vector
3989 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3990 unsigned NumElts = VT.getVectorNumElements();
3991 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3992 unsigned NumLaneElts = NumElts/NumLanes;
3994 // Do not handle 64-bit element shuffles with palignr.
3995 if (NumLaneElts == 2)
3998 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4000 for (i = 0; i != NumLaneElts; ++i) {
4005 // Lane is all undef, go to next lane
4006 if (i == NumLaneElts)
4009 int Start = Mask[i+l];
4011 // Make sure its in this lane in one of the sources
4012 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4013 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4016 // If not lane 0, then we must match lane 0
4017 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4020 // Correct second source to be contiguous with first source
4021 if (Start >= (int)NumElts)
4022 Start -= NumElts - NumLaneElts;
4024 // Make sure we're shifting in the right direction.
4025 if (Start <= (int)(i+l))
4030 // Check the rest of the elements to see if they are consecutive.
4031 for (++i; i != NumLaneElts; ++i) {
4032 int Idx = Mask[i+l];
4034 // Make sure its in this lane
4035 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4036 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4039 // If not lane 0, then we must match lane 0
4040 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4043 if (Idx >= (int)NumElts)
4044 Idx -= NumElts - NumLaneElts;
4046 if (!isUndefOrEqual(Idx, Start+i))
4055 /// \brief Return true if the node specifies a shuffle of elements that is
4056 /// suitable for input to PALIGNR.
4057 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4058 const X86Subtarget *Subtarget) {
4059 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4060 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4061 VT.is512BitVector())
4062 // FIXME: Add AVX512BW.
4065 return isAlignrMask(Mask, VT, false);
4068 /// \brief Return true if the node specifies a shuffle of elements that is
4069 /// suitable for input to VALIGN.
4070 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4071 const X86Subtarget *Subtarget) {
4072 // FIXME: Add AVX512VL.
4073 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4075 return isAlignrMask(Mask, VT, true);
4078 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4079 /// the two vector operands have swapped position.
4080 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4081 unsigned NumElems) {
4082 for (unsigned i = 0; i != NumElems; ++i) {
4086 else if (idx < (int)NumElems)
4087 Mask[i] = idx + NumElems;
4089 Mask[i] = idx - NumElems;
4093 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4094 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4095 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4096 /// reverse of what x86 shuffles want.
4097 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4099 unsigned NumElems = VT.getVectorNumElements();
4100 unsigned NumLanes = VT.getSizeInBits()/128;
4101 unsigned NumLaneElems = NumElems/NumLanes;
4103 if (NumLaneElems != 2 && NumLaneElems != 4)
4106 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4107 bool symetricMaskRequired =
4108 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4110 // VSHUFPSY divides the resulting vector into 4 chunks.
4111 // The sources are also splitted into 4 chunks, and each destination
4112 // chunk must come from a different source chunk.
4114 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4115 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4117 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4118 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4120 // VSHUFPDY divides the resulting vector into 4 chunks.
4121 // The sources are also splitted into 4 chunks, and each destination
4122 // chunk must come from a different source chunk.
4124 // SRC1 => X3 X2 X1 X0
4125 // SRC2 => Y3 Y2 Y1 Y0
4127 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4129 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4130 unsigned HalfLaneElems = NumLaneElems/2;
4131 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4132 for (unsigned i = 0; i != NumLaneElems; ++i) {
4133 int Idx = Mask[i+l];
4134 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4135 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4137 // For VSHUFPSY, the mask of the second half must be the same as the
4138 // first but with the appropriate offsets. This works in the same way as
4139 // VPERMILPS works with masks.
4140 if (!symetricMaskRequired || Idx < 0)
4142 if (MaskVal[i] < 0) {
4143 MaskVal[i] = Idx - l;
4146 if ((signed)(Idx - l) != MaskVal[i])
4154 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4155 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4156 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4157 if (!VT.is128BitVector())
4160 unsigned NumElems = VT.getVectorNumElements();
4165 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4166 return isUndefOrEqual(Mask[0], 6) &&
4167 isUndefOrEqual(Mask[1], 7) &&
4168 isUndefOrEqual(Mask[2], 2) &&
4169 isUndefOrEqual(Mask[3], 3);
4172 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4173 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4175 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4176 if (!VT.is128BitVector())
4179 unsigned NumElems = VT.getVectorNumElements();
4184 return isUndefOrEqual(Mask[0], 2) &&
4185 isUndefOrEqual(Mask[1], 3) &&
4186 isUndefOrEqual(Mask[2], 2) &&
4187 isUndefOrEqual(Mask[3], 3);
4190 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4191 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4192 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4193 if (!VT.is128BitVector())
4196 unsigned NumElems = VT.getVectorNumElements();
4198 if (NumElems != 2 && NumElems != 4)
4201 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4202 if (!isUndefOrEqual(Mask[i], i + NumElems))
4205 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4206 if (!isUndefOrEqual(Mask[i], i))
4212 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4213 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4214 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4215 if (!VT.is128BitVector())
4218 unsigned NumElems = VT.getVectorNumElements();
4220 if (NumElems != 2 && NumElems != 4)
4223 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4224 if (!isUndefOrEqual(Mask[i], i))
4227 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4228 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4234 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4235 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4236 /// i. e: If all but one element come from the same vector.
4237 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4238 // TODO: Deal with AVX's VINSERTPS
4239 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4242 unsigned CorrectPosV1 = 0;
4243 unsigned CorrectPosV2 = 0;
4244 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4245 if (Mask[i] == -1) {
4253 else if (Mask[i] == i + 4)
4257 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4258 // We have 3 elements (undefs count as elements from any vector) from one
4259 // vector, and one from another.
4266 // Some special combinations that can be optimized.
4269 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4270 SelectionDAG &DAG) {
4271 MVT VT = SVOp->getSimpleValueType(0);
4274 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4277 ArrayRef<int> Mask = SVOp->getMask();
4279 // These are the special masks that may be optimized.
4280 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4281 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4282 bool MatchEvenMask = true;
4283 bool MatchOddMask = true;
4284 for (int i=0; i<8; ++i) {
4285 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4286 MatchEvenMask = false;
4287 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4288 MatchOddMask = false;
4291 if (!MatchEvenMask && !MatchOddMask)
4294 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4296 SDValue Op0 = SVOp->getOperand(0);
4297 SDValue Op1 = SVOp->getOperand(1);
4299 if (MatchEvenMask) {
4300 // Shift the second operand right to 32 bits.
4301 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4302 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4304 // Shift the first operand left to 32 bits.
4305 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4306 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4308 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4309 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4312 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4313 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4314 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4315 bool HasInt256, bool V2IsSplat = false) {
4317 assert(VT.getSizeInBits() >= 128 &&
4318 "Unsupported vector type for unpckl");
4320 unsigned NumElts = VT.getVectorNumElements();
4321 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4322 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4325 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4326 "Unsupported vector type for unpckh");
4328 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4329 unsigned NumLanes = VT.getSizeInBits()/128;
4330 unsigned NumLaneElts = NumElts/NumLanes;
4332 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4333 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4334 int BitI = Mask[l+i];
4335 int BitI1 = Mask[l+i+1];
4336 if (!isUndefOrEqual(BitI, j))
4339 if (!isUndefOrEqual(BitI1, NumElts))
4342 if (!isUndefOrEqual(BitI1, j + NumElts))
4351 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4352 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4353 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4354 bool HasInt256, bool V2IsSplat = false) {
4355 assert(VT.getSizeInBits() >= 128 &&
4356 "Unsupported vector type for unpckh");
4358 unsigned NumElts = VT.getVectorNumElements();
4359 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4360 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4363 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4364 "Unsupported vector type for unpckh");
4366 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4367 unsigned NumLanes = VT.getSizeInBits()/128;
4368 unsigned NumLaneElts = NumElts/NumLanes;
4370 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4371 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4372 int BitI = Mask[l+i];
4373 int BitI1 = Mask[l+i+1];
4374 if (!isUndefOrEqual(BitI, j))
4377 if (isUndefOrEqual(BitI1, NumElts))
4380 if (!isUndefOrEqual(BitI1, j+NumElts))
4388 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4389 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4391 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4392 unsigned NumElts = VT.getVectorNumElements();
4393 bool Is256BitVec = VT.is256BitVector();
4395 if (VT.is512BitVector())
4397 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4398 "Unsupported vector type for unpckh");
4400 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4401 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4404 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4405 // FIXME: Need a better way to get rid of this, there's no latency difference
4406 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4407 // the former later. We should also remove the "_undef" special mask.
4408 if (NumElts == 4 && Is256BitVec)
4411 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4412 // independently on 128-bit lanes.
4413 unsigned NumLanes = VT.getSizeInBits()/128;
4414 unsigned NumLaneElts = NumElts/NumLanes;
4416 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4417 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4418 int BitI = Mask[l+i];
4419 int BitI1 = Mask[l+i+1];
4421 if (!isUndefOrEqual(BitI, j))
4423 if (!isUndefOrEqual(BitI1, j))
4431 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4432 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4434 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4435 unsigned NumElts = VT.getVectorNumElements();
4437 if (VT.is512BitVector())
4440 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4441 "Unsupported vector type for unpckh");
4443 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4444 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4447 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4448 // independently on 128-bit lanes.
4449 unsigned NumLanes = VT.getSizeInBits()/128;
4450 unsigned NumLaneElts = NumElts/NumLanes;
4452 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4453 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4454 int BitI = Mask[l+i];
4455 int BitI1 = Mask[l+i+1];
4456 if (!isUndefOrEqual(BitI, j))
4458 if (!isUndefOrEqual(BitI1, j))
4465 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4466 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4467 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4468 if (!VT.is512BitVector())
4471 unsigned NumElts = VT.getVectorNumElements();
4472 unsigned HalfSize = NumElts/2;
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4474 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4479 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4480 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4488 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4489 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4490 /// MOVSD, and MOVD, i.e. setting the lowest element.
4491 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4492 if (VT.getVectorElementType().getSizeInBits() < 32)
4494 if (!VT.is128BitVector())
4497 unsigned NumElts = VT.getVectorNumElements();
4499 if (!isUndefOrEqual(Mask[0], NumElts))
4502 for (unsigned i = 1; i != NumElts; ++i)
4503 if (!isUndefOrEqual(Mask[i], i))
4509 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4510 /// as permutations between 128-bit chunks or halves. As an example: this
4512 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4513 /// The first half comes from the second half of V1 and the second half from the
4514 /// the second half of V2.
4515 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4516 if (!HasFp256 || !VT.is256BitVector())
4519 // The shuffle result is divided into half A and half B. In total the two
4520 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4521 // B must come from C, D, E or F.
4522 unsigned HalfSize = VT.getVectorNumElements()/2;
4523 bool MatchA = false, MatchB = false;
4525 // Check if A comes from one of C, D, E, F.
4526 for (unsigned Half = 0; Half != 4; ++Half) {
4527 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4533 // Check if B comes from one of C, D, E, F.
4534 for (unsigned Half = 0; Half != 4; ++Half) {
4535 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4541 return MatchA && MatchB;
4544 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4545 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4546 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4547 MVT VT = SVOp->getSimpleValueType(0);
4549 unsigned HalfSize = VT.getVectorNumElements()/2;
4551 unsigned FstHalf = 0, SndHalf = 0;
4552 for (unsigned i = 0; i < HalfSize; ++i) {
4553 if (SVOp->getMaskElt(i) > 0) {
4554 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4558 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4559 if (SVOp->getMaskElt(i) > 0) {
4560 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4565 return (FstHalf | (SndHalf << 4));
4568 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4569 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4570 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4574 unsigned NumElts = VT.getVectorNumElements();
4576 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4577 for (unsigned i = 0; i != NumElts; ++i) {
4580 Imm8 |= Mask[i] << (i*2);
4585 unsigned LaneSize = 4;
4586 SmallVector<int, 4> MaskVal(LaneSize, -1);
4588 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4589 for (unsigned i = 0; i != LaneSize; ++i) {
4590 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4594 if (MaskVal[i] < 0) {
4595 MaskVal[i] = Mask[i+l] - l;
4596 Imm8 |= MaskVal[i] << (i*2);
4599 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4606 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4607 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4608 /// Note that VPERMIL mask matching is different depending whether theunderlying
4609 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4610 /// to the same elements of the low, but to the higher half of the source.
4611 /// In VPERMILPD the two lanes could be shuffled independently of each other
4612 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4613 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4614 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4615 if (VT.getSizeInBits() < 256 || EltSize < 32)
4617 bool symetricMaskRequired = (EltSize == 32);
4618 unsigned NumElts = VT.getVectorNumElements();
4620 unsigned NumLanes = VT.getSizeInBits()/128;
4621 unsigned LaneSize = NumElts/NumLanes;
4622 // 2 or 4 elements in one lane
4624 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4625 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4626 for (unsigned i = 0; i != LaneSize; ++i) {
4627 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4629 if (symetricMaskRequired) {
4630 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4631 ExpectedMaskVal[i] = Mask[i+l] - l;
4634 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4642 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4643 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4644 /// element of vector 2 and the other elements to come from vector 1 in order.
4645 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4646 bool V2IsSplat = false, bool V2IsUndef = false) {
4647 if (!VT.is128BitVector())
4650 unsigned NumOps = VT.getVectorNumElements();
4651 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4654 if (!isUndefOrEqual(Mask[0], 0))
4657 for (unsigned i = 1; i != NumOps; ++i)
4658 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4659 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4660 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4666 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4667 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4668 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4669 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4670 const X86Subtarget *Subtarget) {
4671 if (!Subtarget->hasSSE3())
4674 unsigned NumElems = VT.getVectorNumElements();
4676 if ((VT.is128BitVector() && NumElems != 4) ||
4677 (VT.is256BitVector() && NumElems != 8) ||
4678 (VT.is512BitVector() && NumElems != 16))
4681 // "i+1" is the value the indexed mask element must have
4682 for (unsigned i = 0; i != NumElems; i += 2)
4683 if (!isUndefOrEqual(Mask[i], i+1) ||
4684 !isUndefOrEqual(Mask[i+1], i+1))
4690 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4691 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4692 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4693 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4694 const X86Subtarget *Subtarget) {
4695 if (!Subtarget->hasSSE3())
4698 unsigned NumElems = VT.getVectorNumElements();
4700 if ((VT.is128BitVector() && NumElems != 4) ||
4701 (VT.is256BitVector() && NumElems != 8) ||
4702 (VT.is512BitVector() && NumElems != 16))
4705 // "i" is the value the indexed mask element must have
4706 for (unsigned i = 0; i != NumElems; i += 2)
4707 if (!isUndefOrEqual(Mask[i], i) ||
4708 !isUndefOrEqual(Mask[i+1], i))
4714 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4715 /// specifies a shuffle of elements that is suitable for input to 256-bit
4716 /// version of MOVDDUP.
4717 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4718 if (!HasFp256 || !VT.is256BitVector())
4721 unsigned NumElts = VT.getVectorNumElements();
4725 for (unsigned i = 0; i != NumElts/2; ++i)
4726 if (!isUndefOrEqual(Mask[i], 0))
4728 for (unsigned i = NumElts/2; i != NumElts; ++i)
4729 if (!isUndefOrEqual(Mask[i], NumElts/2))
4734 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4735 /// specifies a shuffle of elements that is suitable for input to 128-bit
4736 /// version of MOVDDUP.
4737 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4738 if (!VT.is128BitVector())
4741 unsigned e = VT.getVectorNumElements() / 2;
4742 for (unsigned i = 0; i != e; ++i)
4743 if (!isUndefOrEqual(Mask[i], i))
4745 for (unsigned i = 0; i != e; ++i)
4746 if (!isUndefOrEqual(Mask[e+i], i))
4751 /// isVEXTRACTIndex - Return true if the specified
4752 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4753 /// suitable for instruction that extract 128 or 256 bit vectors
4754 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4755 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4756 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4759 // The index should be aligned on a vecWidth-bit boundary.
4761 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4763 MVT VT = N->getSimpleValueType(0);
4764 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4765 bool Result = (Index * ElSize) % vecWidth == 0;
4770 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4771 /// operand specifies a subvector insert that is suitable for input to
4772 /// insertion of 128 or 256-bit subvectors
4773 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4774 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4775 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4777 // The index should be aligned on a vecWidth-bit boundary.
4779 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4781 MVT VT = N->getSimpleValueType(0);
4782 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4783 bool Result = (Index * ElSize) % vecWidth == 0;
4788 bool X86::isVINSERT128Index(SDNode *N) {
4789 return isVINSERTIndex(N, 128);
4792 bool X86::isVINSERT256Index(SDNode *N) {
4793 return isVINSERTIndex(N, 256);
4796 bool X86::isVEXTRACT128Index(SDNode *N) {
4797 return isVEXTRACTIndex(N, 128);
4800 bool X86::isVEXTRACT256Index(SDNode *N) {
4801 return isVEXTRACTIndex(N, 256);
4804 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4805 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4806 /// Handles 128-bit and 256-bit.
4807 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT.getSizeInBits() >= 128) &&
4811 "Unsupported vector type for PSHUF/SHUFP");
4813 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4814 // independently on 128-bit lanes.
4815 unsigned NumElts = VT.getVectorNumElements();
4816 unsigned NumLanes = VT.getSizeInBits()/128;
4817 unsigned NumLaneElts = NumElts/NumLanes;
4819 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4820 "Only supports 2, 4 or 8 elements per lane");
4822 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4824 for (unsigned i = 0; i != NumElts; ++i) {
4825 int Elt = N->getMaskElt(i);
4826 if (Elt < 0) continue;
4827 Elt &= NumLaneElts - 1;
4828 unsigned ShAmt = (i << Shift) % 8;
4829 Mask |= Elt << ShAmt;
4835 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4836 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4837 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4838 MVT VT = N->getSimpleValueType(0);
4840 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4841 "Unsupported vector type for PSHUFHW");
4843 unsigned NumElts = VT.getVectorNumElements();
4846 for (unsigned l = 0; l != NumElts; l += 8) {
4847 // 8 nodes per lane, but we only care about the last 4.
4848 for (unsigned i = 0; i < 4; ++i) {
4849 int Elt = N->getMaskElt(l+i+4);
4850 if (Elt < 0) continue;
4851 Elt &= 0x3; // only 2-bits.
4852 Mask |= Elt << (i * 2);
4859 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4860 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4861 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4862 MVT VT = N->getSimpleValueType(0);
4864 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4865 "Unsupported vector type for PSHUFHW");
4867 unsigned NumElts = VT.getVectorNumElements();
4870 for (unsigned l = 0; l != NumElts; l += 8) {
4871 // 8 nodes per lane, but we only care about the first 4.
4872 for (unsigned i = 0; i < 4; ++i) {
4873 int Elt = N->getMaskElt(l+i);
4874 if (Elt < 0) continue;
4875 Elt &= 0x3; // only 2-bits
4876 Mask |= Elt << (i * 2);
4883 /// \brief Return the appropriate immediate to shuffle the specified
4884 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4885 /// VALIGN (if Interlane is true) instructions.
4886 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4888 MVT VT = SVOp->getSimpleValueType(0);
4889 unsigned EltSize = InterLane ? 1 :
4890 VT.getVectorElementType().getSizeInBits() >> 3;
4892 unsigned NumElts = VT.getVectorNumElements();
4893 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4894 unsigned NumLaneElts = NumElts/NumLanes;
4898 for (i = 0; i != NumElts; ++i) {
4899 Val = SVOp->getMaskElt(i);
4903 if (Val >= (int)NumElts)
4904 Val -= NumElts - NumLaneElts;
4906 assert(Val - i > 0 && "PALIGNR imm should be positive");
4907 return (Val - i) * EltSize;
4910 /// \brief Return the appropriate immediate to shuffle the specified
4911 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4912 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4913 return getShuffleAlignrImmediate(SVOp, false);
4916 /// \brief Return the appropriate immediate to shuffle the specified
4917 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4918 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4919 return getShuffleAlignrImmediate(SVOp, true);
4923 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4924 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4925 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4926 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4929 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4931 MVT VecVT = N->getOperand(0).getSimpleValueType();
4932 MVT ElVT = VecVT.getVectorElementType();
4934 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4935 return Index / NumElemsPerChunk;
4938 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4939 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4940 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4941 llvm_unreachable("Illegal insert subvector for VINSERT");
4944 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4946 MVT VecVT = N->getSimpleValueType(0);
4947 MVT ElVT = VecVT.getVectorElementType();
4949 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4950 return Index / NumElemsPerChunk;
4953 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4954 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4955 /// and VINSERTI128 instructions.
4956 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4957 return getExtractVEXTRACTImmediate(N, 128);
4960 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4961 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4962 /// and VINSERTI64x4 instructions.
4963 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4964 return getExtractVEXTRACTImmediate(N, 256);
4967 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4968 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4969 /// and VINSERTI128 instructions.
4970 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4971 return getInsertVINSERTImmediate(N, 128);
4974 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4975 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4976 /// and VINSERTI64x4 instructions.
4977 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4978 return getInsertVINSERTImmediate(N, 256);
4981 /// isZero - Returns true if Elt is a constant integer zero
4982 static bool isZero(SDValue V) {
4983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4984 return C && C->isNullValue();
4987 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4989 bool X86::isZeroNode(SDValue Elt) {
4992 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4993 return CFP->getValueAPF().isPosZero();
4997 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4998 /// match movhlps. The lower half elements should come from upper half of
4999 /// V1 (and in order), and the upper half elements should come from the upper
5000 /// half of V2 (and in order).
5001 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5002 if (!VT.is128BitVector())
5004 if (VT.getVectorNumElements() != 4)
5006 for (unsigned i = 0, e = 2; i != e; ++i)
5007 if (!isUndefOrEqual(Mask[i], i+2))
5009 for (unsigned i = 2; i != 4; ++i)
5010 if (!isUndefOrEqual(Mask[i], i+4))
5015 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5016 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5018 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5019 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5021 N = N->getOperand(0).getNode();
5022 if (!ISD::isNON_EXTLoad(N))
5025 *LD = cast<LoadSDNode>(N);
5029 // Test whether the given value is a vector value which will be legalized
5031 static bool WillBeConstantPoolLoad(SDNode *N) {
5032 if (N->getOpcode() != ISD::BUILD_VECTOR)
5035 // Check for any non-constant elements.
5036 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5037 switch (N->getOperand(i).getNode()->getOpcode()) {
5039 case ISD::ConstantFP:
5046 // Vectors of all-zeros and all-ones are materialized with special
5047 // instructions rather than being loaded.
5048 return !ISD::isBuildVectorAllZeros(N) &&
5049 !ISD::isBuildVectorAllOnes(N);
5052 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5053 /// match movlp{s|d}. The lower half elements should come from lower half of
5054 /// V1 (and in order), and the upper half elements should come from the upper
5055 /// half of V2 (and in order). And since V1 will become the source of the
5056 /// MOVLP, it must be either a vector load or a scalar load to vector.
5057 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5058 ArrayRef<int> Mask, MVT VT) {
5059 if (!VT.is128BitVector())
5062 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5064 // Is V2 is a vector load, don't do this transformation. We will try to use
5065 // load folding shufps op.
5066 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5069 unsigned NumElems = VT.getVectorNumElements();
5071 if (NumElems != 2 && NumElems != 4)
5073 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5074 if (!isUndefOrEqual(Mask[i], i))
5076 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5077 if (!isUndefOrEqual(Mask[i], i+NumElems))
5082 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5083 /// to an zero vector.
5084 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5085 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5086 SDValue V1 = N->getOperand(0);
5087 SDValue V2 = N->getOperand(1);
5088 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5089 for (unsigned i = 0; i != NumElems; ++i) {
5090 int Idx = N->getMaskElt(i);
5091 if (Idx >= (int)NumElems) {
5092 unsigned Opc = V2.getOpcode();
5093 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5095 if (Opc != ISD::BUILD_VECTOR ||
5096 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5098 } else if (Idx >= 0) {
5099 unsigned Opc = V1.getOpcode();
5100 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5102 if (Opc != ISD::BUILD_VECTOR ||
5103 !X86::isZeroNode(V1.getOperand(Idx)))
5110 /// getZeroVector - Returns a vector of specified type with all zero elements.
5112 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5113 SelectionDAG &DAG, SDLoc dl) {
5114 assert(VT.isVector() && "Expected a vector type");
5116 // Always build SSE zero vectors as <4 x i32> bitcasted
5117 // to their dest type. This ensures they get CSE'd.
5119 if (VT.is128BitVector()) { // SSE
5120 if (Subtarget->hasSSE2()) { // SSE2
5121 SDValue Cst = DAG.getConstant(0, MVT::i32);
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5125 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5127 } else if (VT.is256BitVector()) { // AVX
5128 if (Subtarget->hasInt256()) { // AVX2
5129 SDValue Cst = DAG.getConstant(0, MVT::i32);
5130 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5133 // 256-bit logic and arithmetic instructions in AVX are all
5134 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5135 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5136 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5137 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5139 } else if (VT.is512BitVector()) { // AVX-512
5140 SDValue Cst = DAG.getConstant(0, MVT::i32);
5141 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5142 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5143 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5144 } else if (VT.getScalarType() == MVT::i1) {
5145 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5146 SDValue Cst = DAG.getConstant(0, MVT::i1);
5147 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5148 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5150 llvm_unreachable("Unexpected vector type");
5152 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5155 /// getOnesVector - Returns a vector of specified type with all bits set.
5156 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5157 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5158 /// Then bitcast to their original type, ensuring they get CSE'd.
5159 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5161 assert(VT.isVector() && "Expected a vector type");
5163 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5165 if (VT.is256BitVector()) {
5166 if (HasInt256) { // AVX2
5167 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5168 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5170 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5171 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5173 } else if (VT.is128BitVector()) {
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5176 llvm_unreachable("Unexpected vector type");
5178 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5181 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5182 /// that point to V2 points to its first element.
5183 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5184 for (unsigned i = 0; i != NumElems; ++i) {
5185 if (Mask[i] > (int)NumElems) {
5191 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5192 /// operation of specified width.
5193 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5195 unsigned NumElems = VT.getVectorNumElements();
5196 SmallVector<int, 8> Mask;
5197 Mask.push_back(NumElems);
5198 for (unsigned i = 1; i != NumElems; ++i)
5200 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5203 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5204 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5206 unsigned NumElems = VT.getVectorNumElements();
5207 SmallVector<int, 8> Mask;
5208 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5210 Mask.push_back(i + NumElems);
5212 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5215 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5216 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5218 unsigned NumElems = VT.getVectorNumElements();
5219 SmallVector<int, 8> Mask;
5220 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5221 Mask.push_back(i + Half);
5222 Mask.push_back(i + NumElems + Half);
5224 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5227 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5228 // a generic shuffle instruction because the target has no such instructions.
5229 // Generate shuffles which repeat i16 and i8 several times until they can be
5230 // represented by v4f32 and then be manipulated by target suported shuffles.
5231 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5232 MVT VT = V.getSimpleValueType();
5233 int NumElems = VT.getVectorNumElements();
5236 while (NumElems > 4) {
5237 if (EltNo < NumElems/2) {
5238 V = getUnpackl(DAG, dl, VT, V, V);
5240 V = getUnpackh(DAG, dl, VT, V, V);
5241 EltNo -= NumElems/2;
5248 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5249 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5250 MVT VT = V.getSimpleValueType();
5253 if (VT.is128BitVector()) {
5254 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5255 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5256 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5258 } else if (VT.is256BitVector()) {
5259 // To use VPERMILPS to splat scalars, the second half of indicies must
5260 // refer to the higher part, which is a duplication of the lower one,
5261 // because VPERMILPS can only handle in-lane permutations.
5262 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5263 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5265 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5266 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5269 llvm_unreachable("Vector size not supported");
5271 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5274 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5275 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5276 MVT SrcVT = SV->getSimpleValueType(0);
5277 SDValue V1 = SV->getOperand(0);
5280 int EltNo = SV->getSplatIndex();
5281 int NumElems = SrcVT.getVectorNumElements();
5282 bool Is256BitVec = SrcVT.is256BitVector();
5284 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5285 "Unknown how to promote splat for type");
5287 // Extract the 128-bit part containing the splat element and update
5288 // the splat element index when it refers to the higher register.
5290 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5291 if (EltNo >= NumElems/2)
5292 EltNo -= NumElems/2;
5295 // All i16 and i8 vector types can't be used directly by a generic shuffle
5296 // instruction because the target has no such instruction. Generate shuffles
5297 // which repeat i16 and i8 several times until they fit in i32, and then can
5298 // be manipulated by target suported shuffles.
5299 MVT EltVT = SrcVT.getVectorElementType();
5300 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5301 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5303 // Recreate the 256-bit vector and place the same 128-bit vector
5304 // into the low and high part. This is necessary because we want
5305 // to use VPERM* to shuffle the vectors
5307 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5310 return getLegalSplat(DAG, V1, EltNo);
5313 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5314 /// vector of zero or undef vector. This produces a shuffle where the low
5315 /// element of V2 is swizzled into the zero/undef vector, landing at element
5316 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5317 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5319 const X86Subtarget *Subtarget,
5320 SelectionDAG &DAG) {
5321 MVT VT = V2.getSimpleValueType();
5323 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5324 unsigned NumElems = VT.getVectorNumElements();
5325 SmallVector<int, 16> MaskVec;
5326 for (unsigned i = 0; i != NumElems; ++i)
5327 // If this is the insertion idx, put the low elt of V2 here.
5328 MaskVec.push_back(i == Idx ? NumElems : i);
5329 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5332 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5333 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5334 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5335 /// shuffles which use a single input multiple times, and in those cases it will
5336 /// adjust the mask to only have indices within that single input.
5337 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5338 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5339 unsigned NumElems = VT.getVectorNumElements();
5343 bool IsFakeUnary = false;
5344 switch(N->getOpcode()) {
5345 case X86ISD::BLENDI:
5346 ImmN = N->getOperand(N->getNumOperands()-1);
5347 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5352 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5354 case X86ISD::UNPCKH:
5355 DecodeUNPCKHMask(VT, Mask);
5356 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5358 case X86ISD::UNPCKL:
5359 DecodeUNPCKLMask(VT, Mask);
5360 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5362 case X86ISD::MOVHLPS:
5363 DecodeMOVHLPSMask(NumElems, Mask);
5364 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5366 case X86ISD::MOVLHPS:
5367 DecodeMOVLHPSMask(NumElems, Mask);
5368 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5370 case X86ISD::PALIGNR:
5371 ImmN = N->getOperand(N->getNumOperands()-1);
5372 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5374 case X86ISD::PSHUFD:
5375 case X86ISD::VPERMILPI:
5376 ImmN = N->getOperand(N->getNumOperands()-1);
5377 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5380 case X86ISD::PSHUFHW:
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5385 case X86ISD::PSHUFLW:
5386 ImmN = N->getOperand(N->getNumOperands()-1);
5387 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5390 case X86ISD::PSHUFB: {
5392 SDValue MaskNode = N->getOperand(1);
5393 while (MaskNode->getOpcode() == ISD::BITCAST)
5394 MaskNode = MaskNode->getOperand(0);
5396 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5397 // If we have a build-vector, then things are easy.
5398 EVT VT = MaskNode.getValueType();
5399 assert(VT.isVector() &&
5400 "Can't produce a non-vector with a build_vector!");
5401 if (!VT.isInteger())
5404 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5406 SmallVector<uint64_t, 32> RawMask;
5407 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5408 SDValue Op = MaskNode->getOperand(i);
5409 if (Op->getOpcode() == ISD::UNDEF) {
5410 RawMask.push_back((uint64_t)SM_SentinelUndef);
5413 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5416 APInt MaskElement = CN->getAPIntValue();
5418 // We now have to decode the element which could be any integer size and
5419 // extract each byte of it.
5420 for (int j = 0; j < NumBytesPerElement; ++j) {
5421 // Note that this is x86 and so always little endian: the low byte is
5422 // the first byte of the mask.
5423 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5424 MaskElement = MaskElement.lshr(8);
5427 DecodePSHUFBMask(RawMask, Mask);
5431 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5435 SDValue Ptr = MaskLoad->getBasePtr();
5436 if (Ptr->getOpcode() == X86ISD::Wrapper)
5437 Ptr = Ptr->getOperand(0);
5439 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5440 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5443 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5444 // FIXME: Support AVX-512 here.
5445 Type *Ty = C->getType();
5446 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5447 Ty->getVectorNumElements() != 32))
5450 DecodePSHUFBMask(C, Mask);
5456 case X86ISD::VPERMI:
5457 ImmN = N->getOperand(N->getNumOperands()-1);
5458 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5462 case X86ISD::MOVSD: {
5463 // The index 0 always comes from the first element of the second source,
5464 // this is why MOVSS and MOVSD are used in the first place. The other
5465 // elements come from the other positions of the first source vector
5466 Mask.push_back(NumElems);
5467 for (unsigned i = 1; i != NumElems; ++i) {
5472 case X86ISD::VPERM2X128:
5473 ImmN = N->getOperand(N->getNumOperands()-1);
5474 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5475 if (Mask.empty()) return false;
5477 case X86ISD::MOVSLDUP:
5478 DecodeMOVSLDUPMask(VT, Mask);
5480 case X86ISD::MOVSHDUP:
5481 DecodeMOVSHDUPMask(VT, Mask);
5483 case X86ISD::MOVDDUP:
5484 case X86ISD::MOVLHPD:
5485 case X86ISD::MOVLPD:
5486 case X86ISD::MOVLPS:
5487 // Not yet implemented
5489 default: llvm_unreachable("unknown target shuffle node");
5492 // If we have a fake unary shuffle, the shuffle mask is spread across two
5493 // inputs that are actually the same node. Re-map the mask to always point
5494 // into the first input.
5497 if (M >= (int)Mask.size())
5503 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5504 /// element of the result of the vector shuffle.
5505 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5508 return SDValue(); // Limit search depth.
5510 SDValue V = SDValue(N, 0);
5511 EVT VT = V.getValueType();
5512 unsigned Opcode = V.getOpcode();
5514 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5515 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5516 int Elt = SV->getMaskElt(Index);
5519 return DAG.getUNDEF(VT.getVectorElementType());
5521 unsigned NumElems = VT.getVectorNumElements();
5522 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5523 : SV->getOperand(1);
5524 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5527 // Recurse into target specific vector shuffles to find scalars.
5528 if (isTargetShuffle(Opcode)) {
5529 MVT ShufVT = V.getSimpleValueType();
5530 unsigned NumElems = ShufVT.getVectorNumElements();
5531 SmallVector<int, 16> ShuffleMask;
5534 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5537 int Elt = ShuffleMask[Index];
5539 return DAG.getUNDEF(ShufVT.getVectorElementType());
5541 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5543 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5547 // Actual nodes that may contain scalar elements
5548 if (Opcode == ISD::BITCAST) {
5549 V = V.getOperand(0);
5550 EVT SrcVT = V.getValueType();
5551 unsigned NumElems = VT.getVectorNumElements();
5553 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5557 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5558 return (Index == 0) ? V.getOperand(0)
5559 : DAG.getUNDEF(VT.getVectorElementType());
5561 if (V.getOpcode() == ISD::BUILD_VECTOR)
5562 return V.getOperand(Index);
5567 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5568 /// shuffle operation which come from a consecutively from a zero. The
5569 /// search can start in two different directions, from left or right.
5570 /// We count undefs as zeros until PreferredNum is reached.
5571 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5572 unsigned NumElems, bool ZerosFromLeft,
5574 unsigned PreferredNum = -1U) {
5575 unsigned NumZeros = 0;
5576 for (unsigned i = 0; i != NumElems; ++i) {
5577 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5578 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5582 if (X86::isZeroNode(Elt))
5584 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5585 NumZeros = std::min(NumZeros + 1, PreferredNum);
5593 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5594 /// correspond consecutively to elements from one of the vector operands,
5595 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5597 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5598 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5599 unsigned NumElems, unsigned &OpNum) {
5600 bool SeenV1 = false;
5601 bool SeenV2 = false;
5603 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5604 int Idx = SVOp->getMaskElt(i);
5605 // Ignore undef indicies
5609 if (Idx < (int)NumElems)
5614 // Only accept consecutive elements from the same vector
5615 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5619 OpNum = SeenV1 ? 0 : 1;
5623 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5624 /// logical left shift of a vector.
5625 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5626 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5628 SVOp->getSimpleValueType(0).getVectorNumElements();
5629 unsigned NumZeros = getNumOfConsecutiveZeros(
5630 SVOp, NumElems, false /* check zeros from right */, DAG,
5631 SVOp->getMaskElt(0));
5637 // Considering the elements in the mask that are not consecutive zeros,
5638 // check if they consecutively come from only one of the source vectors.
5640 // V1 = {X, A, B, C} 0
5642 // vector_shuffle V1, V2 <1, 2, 3, X>
5644 if (!isShuffleMaskConsecutive(SVOp,
5645 0, // Mask Start Index
5646 NumElems-NumZeros, // Mask End Index(exclusive)
5647 NumZeros, // Where to start looking in the src vector
5648 NumElems, // Number of elements in vector
5649 OpSrc)) // Which source operand ?
5654 ShVal = SVOp->getOperand(OpSrc);
5658 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5659 /// logical left shift of a vector.
5660 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5661 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5663 SVOp->getSimpleValueType(0).getVectorNumElements();
5664 unsigned NumZeros = getNumOfConsecutiveZeros(
5665 SVOp, NumElems, true /* check zeros from left */, DAG,
5666 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5672 // Considering the elements in the mask that are not consecutive zeros,
5673 // check if they consecutively come from only one of the source vectors.
5675 // 0 { A, B, X, X } = V2
5677 // vector_shuffle V1, V2 <X, X, 4, 5>
5679 if (!isShuffleMaskConsecutive(SVOp,
5680 NumZeros, // Mask Start Index
5681 NumElems, // Mask End Index(exclusive)
5682 0, // Where to start looking in the src vector
5683 NumElems, // Number of elements in vector
5684 OpSrc)) // Which source operand ?
5689 ShVal = SVOp->getOperand(OpSrc);
5693 /// isVectorShift - Returns true if the shuffle can be implemented as a
5694 /// logical left or right shift of a vector.
5695 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5696 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5697 // Although the logic below support any bitwidth size, there are no
5698 // shift instructions which handle more than 128-bit vectors.
5699 if (!SVOp->getSimpleValueType(0).is128BitVector())
5702 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5703 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5709 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5711 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5712 unsigned NumNonZero, unsigned NumZero,
5714 const X86Subtarget* Subtarget,
5715 const TargetLowering &TLI) {
5722 for (unsigned i = 0; i < 16; ++i) {
5723 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5724 if (ThisIsNonZero && First) {
5726 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5728 V = DAG.getUNDEF(MVT::v8i16);
5733 SDValue ThisElt, LastElt;
5734 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5735 if (LastIsNonZero) {
5736 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5737 MVT::i16, Op.getOperand(i-1));
5739 if (ThisIsNonZero) {
5740 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5741 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5742 ThisElt, DAG.getConstant(8, MVT::i8));
5744 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5748 if (ThisElt.getNode())
5749 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5750 DAG.getIntPtrConstant(i/2));
5754 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5757 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5759 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5760 unsigned NumNonZero, unsigned NumZero,
5762 const X86Subtarget* Subtarget,
5763 const TargetLowering &TLI) {
5770 for (unsigned i = 0; i < 8; ++i) {
5771 bool isNonZero = (NonZeros & (1 << i)) != 0;
5775 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5777 V = DAG.getUNDEF(MVT::v8i16);
5780 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5781 MVT::v8i16, V, Op.getOperand(i),
5782 DAG.getIntPtrConstant(i));
5789 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5790 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5791 const X86Subtarget *Subtarget,
5792 const TargetLowering &TLI) {
5793 // Find all zeroable elements.
5795 for (int i=0; i < 4; ++i) {
5796 SDValue Elt = Op->getOperand(i);
5797 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5799 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5800 [](bool M) { return !M; }) > 1 &&
5801 "We expect at least two non-zero elements!");
5803 // We only know how to deal with build_vector nodes where elements are either
5804 // zeroable or extract_vector_elt with constant index.
5805 SDValue FirstNonZero;
5806 unsigned FirstNonZeroIdx;
5807 for (unsigned i=0; i < 4; ++i) {
5810 SDValue Elt = Op->getOperand(i);
5811 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5812 !isa<ConstantSDNode>(Elt.getOperand(1)))
5814 // Make sure that this node is extracting from a 128-bit vector.
5815 MVT VT = Elt.getOperand(0).getSimpleValueType();
5816 if (!VT.is128BitVector())
5818 if (!FirstNonZero.getNode()) {
5820 FirstNonZeroIdx = i;
5824 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5825 SDValue V1 = FirstNonZero.getOperand(0);
5826 MVT VT = V1.getSimpleValueType();
5828 // See if this build_vector can be lowered as a blend with zero.
5830 unsigned EltMaskIdx, EltIdx;
5832 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5833 if (Zeroable[EltIdx]) {
5834 // The zero vector will be on the right hand side.
5835 Mask[EltIdx] = EltIdx+4;
5839 Elt = Op->getOperand(EltIdx);
5840 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5841 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5842 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5844 Mask[EltIdx] = EltIdx;
5848 // Let the shuffle legalizer deal with blend operations.
5849 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5850 if (V1.getSimpleValueType() != VT)
5851 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5852 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5855 // See if we can lower this build_vector to a INSERTPS.
5856 if (!Subtarget->hasSSE41())
5859 SDValue V2 = Elt.getOperand(0);
5860 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5863 bool CanFold = true;
5864 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5868 SDValue Current = Op->getOperand(i);
5869 SDValue SrcVector = Current->getOperand(0);
5872 CanFold = SrcVector == V1 &&
5873 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5879 assert(V1.getNode() && "Expected at least two non-zero elements!");
5880 if (V1.getSimpleValueType() != MVT::v4f32)
5881 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5882 if (V2.getSimpleValueType() != MVT::v4f32)
5883 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5885 // Ok, we can emit an INSERTPS instruction.
5887 for (int i = 0; i < 4; ++i)
5891 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5892 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5893 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5894 DAG.getIntPtrConstant(InsertPSMask));
5895 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5898 /// getVShift - Return a vector logical shift node.
5900 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5901 unsigned NumBits, SelectionDAG &DAG,
5902 const TargetLowering &TLI, SDLoc dl) {
5903 assert(VT.is128BitVector() && "Unknown type for VShift");
5904 EVT ShVT = MVT::v2i64;
5905 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5906 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5907 return DAG.getNode(ISD::BITCAST, dl, VT,
5908 DAG.getNode(Opc, dl, ShVT, SrcOp,
5909 DAG.getConstant(NumBits,
5910 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5914 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5916 // Check if the scalar load can be widened into a vector load. And if
5917 // the address is "base + cst" see if the cst can be "absorbed" into
5918 // the shuffle mask.
5919 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5920 SDValue Ptr = LD->getBasePtr();
5921 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5923 EVT PVT = LD->getValueType(0);
5924 if (PVT != MVT::i32 && PVT != MVT::f32)
5929 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5930 FI = FINode->getIndex();
5932 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5933 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5934 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5935 Offset = Ptr.getConstantOperandVal(1);
5936 Ptr = Ptr.getOperand(0);
5941 // FIXME: 256-bit vector instructions don't require a strict alignment,
5942 // improve this code to support it better.
5943 unsigned RequiredAlign = VT.getSizeInBits()/8;
5944 SDValue Chain = LD->getChain();
5945 // Make sure the stack object alignment is at least 16 or 32.
5946 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5947 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5948 if (MFI->isFixedObjectIndex(FI)) {
5949 // Can't change the alignment. FIXME: It's possible to compute
5950 // the exact stack offset and reference FI + adjust offset instead.
5951 // If someone *really* cares about this. That's the way to implement it.
5954 MFI->setObjectAlignment(FI, RequiredAlign);
5958 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5959 // Ptr + (Offset & ~15).
5962 if ((Offset % RequiredAlign) & 3)
5964 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5966 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5967 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5969 int EltNo = (Offset - StartOffset) >> 2;
5970 unsigned NumElems = VT.getVectorNumElements();
5972 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5973 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5974 LD->getPointerInfo().getWithOffset(StartOffset),
5975 false, false, false, 0);
5977 SmallVector<int, 8> Mask;
5978 for (unsigned i = 0; i != NumElems; ++i)
5979 Mask.push_back(EltNo);
5981 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5987 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5988 /// vector of type 'VT', see if the elements can be replaced by a single large
5989 /// load which has the same value as a build_vector whose operands are 'elts'.
5991 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5993 /// FIXME: we'd also like to handle the case where the last elements are zero
5994 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5995 /// There's even a handy isZeroNode for that purpose.
5996 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5997 SDLoc &DL, SelectionDAG &DAG,
5998 bool isAfterLegalize) {
5999 EVT EltVT = VT.getVectorElementType();
6000 unsigned NumElems = Elts.size();
6002 LoadSDNode *LDBase = nullptr;
6003 unsigned LastLoadedElt = -1U;
6005 // For each element in the initializer, see if we've found a load or an undef.
6006 // If we don't find an initial load element, or later load elements are
6007 // non-consecutive, bail out.
6008 for (unsigned i = 0; i < NumElems; ++i) {
6009 SDValue Elt = Elts[i];
6011 if (!Elt.getNode() ||
6012 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6015 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6017 LDBase = cast<LoadSDNode>(Elt.getNode());
6021 if (Elt.getOpcode() == ISD::UNDEF)
6024 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6025 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6030 // If we have found an entire vector of loads and undefs, then return a large
6031 // load of the entire vector width starting at the base pointer. If we found
6032 // consecutive loads for the low half, generate a vzext_load node.
6033 if (LastLoadedElt == NumElems - 1) {
6035 if (isAfterLegalize &&
6036 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6039 SDValue NewLd = SDValue();
6041 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6042 LDBase->getPointerInfo(), LDBase->isVolatile(),
6043 LDBase->isNonTemporal(), LDBase->isInvariant(),
6044 LDBase->getAlignment());
6046 if (LDBase->hasAnyUseOfValue(1)) {
6047 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6049 SDValue(NewLd.getNode(), 1));
6050 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6051 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6052 SDValue(NewLd.getNode(), 1));
6058 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6059 //of a v4i32 / v4f32. It's probably worth generalizing.
6060 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6061 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6062 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6063 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6065 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6066 LDBase->getPointerInfo(),
6067 LDBase->getAlignment(),
6068 false/*isVolatile*/, true/*ReadMem*/,
6071 // Make sure the newly-created LOAD is in the same position as LDBase in
6072 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6073 // update uses of LDBase's output chain to use the TokenFactor.
6074 if (LDBase->hasAnyUseOfValue(1)) {
6075 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6076 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6077 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6078 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6079 SDValue(ResNode.getNode(), 1));
6082 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6087 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6088 /// to generate a splat value for the following cases:
6089 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6090 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6091 /// a scalar load, or a constant.
6092 /// The VBROADCAST node is returned when a pattern is found,
6093 /// or SDValue() otherwise.
6094 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6095 SelectionDAG &DAG) {
6096 // VBROADCAST requires AVX.
6097 // TODO: Splats could be generated for non-AVX CPUs using SSE
6098 // instructions, but there's less potential gain for only 128-bit vectors.
6099 if (!Subtarget->hasAVX())
6102 MVT VT = Op.getSimpleValueType();
6105 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6106 "Unsupported vector type for broadcast.");
6111 switch (Op.getOpcode()) {
6113 // Unknown pattern found.
6116 case ISD::BUILD_VECTOR: {
6117 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6118 BitVector UndefElements;
6119 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6121 // We need a splat of a single value to use broadcast, and it doesn't
6122 // make any sense if the value is only in one element of the vector.
6123 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6127 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6128 Ld.getOpcode() == ISD::ConstantFP);
6130 // Make sure that all of the users of a non-constant load are from the
6131 // BUILD_VECTOR node.
6132 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6137 case ISD::VECTOR_SHUFFLE: {
6138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6140 // Shuffles must have a splat mask where the first element is
6142 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6145 SDValue Sc = Op.getOperand(0);
6146 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6147 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6149 if (!Subtarget->hasInt256())
6152 // Use the register form of the broadcast instruction available on AVX2.
6153 if (VT.getSizeInBits() >= 256)
6154 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6158 Ld = Sc.getOperand(0);
6159 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6160 Ld.getOpcode() == ISD::ConstantFP);
6162 // The scalar_to_vector node and the suspected
6163 // load node must have exactly one user.
6164 // Constants may have multiple users.
6166 // AVX-512 has register version of the broadcast
6167 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6168 Ld.getValueType().getSizeInBits() >= 32;
6169 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6176 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6177 bool IsGE256 = (VT.getSizeInBits() >= 256);
6179 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6180 // instruction to save 8 or more bytes of constant pool data.
6181 // TODO: If multiple splats are generated to load the same constant,
6182 // it may be detrimental to overall size. There needs to be a way to detect
6183 // that condition to know if this is truly a size win.
6184 const Function *F = DAG.getMachineFunction().getFunction();
6185 bool OptForSize = F->getAttributes().
6186 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6188 // Handle broadcasting a single constant scalar from the constant pool
6190 // On Sandybridge (no AVX2), it is still better to load a constant vector
6191 // from the constant pool and not to broadcast it from a scalar.
6192 // But override that restriction when optimizing for size.
6193 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6194 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6195 EVT CVT = Ld.getValueType();
6196 assert(!CVT.isVector() && "Must not broadcast a vector type");
6198 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6199 // For size optimization, also splat v2f64 and v2i64, and for size opt
6200 // with AVX2, also splat i8 and i16.
6201 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6202 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6203 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6204 const Constant *C = nullptr;
6205 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6206 C = CI->getConstantIntValue();
6207 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6208 C = CF->getConstantFPValue();
6210 assert(C && "Invalid constant type");
6212 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6213 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6214 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6215 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6216 MachinePointerInfo::getConstantPool(),
6217 false, false, false, Alignment);
6219 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6223 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6225 // Handle AVX2 in-register broadcasts.
6226 if (!IsLoad && Subtarget->hasInt256() &&
6227 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6228 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6230 // The scalar source must be a normal load.
6234 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6235 (Subtarget->hasVLX() && ScalarSize == 64))
6236 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6238 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6239 // double since there is no vbroadcastsd xmm
6240 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6241 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6242 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6245 // Unsupported broadcast.
6249 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6250 /// underlying vector and index.
6252 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6254 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6256 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6257 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6260 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6262 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6264 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6265 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6268 // In this case the vector is the extract_subvector expression and the index
6269 // is 2, as specified by the shuffle.
6270 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6271 SDValue ShuffleVec = SVOp->getOperand(0);
6272 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6273 assert(ShuffleVecVT.getVectorElementType() ==
6274 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6276 int ShuffleIdx = SVOp->getMaskElt(Idx);
6277 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6278 ExtractedFromVec = ShuffleVec;
6284 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6285 MVT VT = Op.getSimpleValueType();
6287 // Skip if insert_vec_elt is not supported.
6288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6289 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6293 unsigned NumElems = Op.getNumOperands();
6297 SmallVector<unsigned, 4> InsertIndices;
6298 SmallVector<int, 8> Mask(NumElems, -1);
6300 for (unsigned i = 0; i != NumElems; ++i) {
6301 unsigned Opc = Op.getOperand(i).getOpcode();
6303 if (Opc == ISD::UNDEF)
6306 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6307 // Quit if more than 1 elements need inserting.
6308 if (InsertIndices.size() > 1)
6311 InsertIndices.push_back(i);
6315 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6316 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6317 // Quit if non-constant index.
6318 if (!isa<ConstantSDNode>(ExtIdx))
6320 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6322 // Quit if extracted from vector of different type.
6323 if (ExtractedFromVec.getValueType() != VT)
6326 if (!VecIn1.getNode())
6327 VecIn1 = ExtractedFromVec;
6328 else if (VecIn1 != ExtractedFromVec) {
6329 if (!VecIn2.getNode())
6330 VecIn2 = ExtractedFromVec;
6331 else if (VecIn2 != ExtractedFromVec)
6332 // Quit if more than 2 vectors to shuffle
6336 if (ExtractedFromVec == VecIn1)
6338 else if (ExtractedFromVec == VecIn2)
6339 Mask[i] = Idx + NumElems;
6342 if (!VecIn1.getNode())
6345 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6346 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6347 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6348 unsigned Idx = InsertIndices[i];
6349 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6350 DAG.getIntPtrConstant(Idx));
6356 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6358 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6360 MVT VT = Op.getSimpleValueType();
6361 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6362 "Unexpected type in LowerBUILD_VECTORvXi1!");
6365 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6366 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6367 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6368 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6371 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6372 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6373 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6374 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6377 bool AllContants = true;
6378 uint64_t Immediate = 0;
6379 int NonConstIdx = -1;
6380 bool IsSplat = true;
6381 unsigned NumNonConsts = 0;
6382 unsigned NumConsts = 0;
6383 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6384 SDValue In = Op.getOperand(idx);
6385 if (In.getOpcode() == ISD::UNDEF)
6387 if (!isa<ConstantSDNode>(In)) {
6388 AllContants = false;
6393 if (cast<ConstantSDNode>(In)->getZExtValue())
6394 Immediate |= (1ULL << idx);
6396 if (In != Op.getOperand(0))
6401 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6402 DAG.getConstant(Immediate, MVT::i16));
6403 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6404 DAG.getIntPtrConstant(0));
6407 if (NumNonConsts == 1 && NonConstIdx != 0) {
6410 SDValue VecAsImm = DAG.getConstant(Immediate,
6411 MVT::getIntegerVT(VT.getSizeInBits()));
6412 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6415 DstVec = DAG.getUNDEF(VT);
6416 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6417 Op.getOperand(NonConstIdx),
6418 DAG.getIntPtrConstant(NonConstIdx));
6420 if (!IsSplat && (NonConstIdx != 0))
6421 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6422 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6425 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6426 DAG.getConstant(-1, SelectVT),
6427 DAG.getConstant(0, SelectVT));
6429 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6430 DAG.getConstant((Immediate | 1), SelectVT),
6431 DAG.getConstant(Immediate, SelectVT));
6432 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6435 /// \brief Return true if \p N implements a horizontal binop and return the
6436 /// operands for the horizontal binop into V0 and V1.
6438 /// This is a helper function of PerformBUILD_VECTORCombine.
6439 /// This function checks that the build_vector \p N in input implements a
6440 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6441 /// operation to match.
6442 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6443 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6444 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6447 /// This function only analyzes elements of \p N whose indices are
6448 /// in range [BaseIdx, LastIdx).
6449 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6451 unsigned BaseIdx, unsigned LastIdx,
6452 SDValue &V0, SDValue &V1) {
6453 EVT VT = N->getValueType(0);
6455 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6456 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6457 "Invalid Vector in input!");
6459 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6460 bool CanFold = true;
6461 unsigned ExpectedVExtractIdx = BaseIdx;
6462 unsigned NumElts = LastIdx - BaseIdx;
6463 V0 = DAG.getUNDEF(VT);
6464 V1 = DAG.getUNDEF(VT);
6466 // Check if N implements a horizontal binop.
6467 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6468 SDValue Op = N->getOperand(i + BaseIdx);
6471 if (Op->getOpcode() == ISD::UNDEF) {
6472 // Update the expected vector extract index.
6473 if (i * 2 == NumElts)
6474 ExpectedVExtractIdx = BaseIdx;
6475 ExpectedVExtractIdx += 2;
6479 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6484 SDValue Op0 = Op.getOperand(0);
6485 SDValue Op1 = Op.getOperand(1);
6487 // Try to match the following pattern:
6488 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6489 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6490 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6491 Op0.getOperand(0) == Op1.getOperand(0) &&
6492 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6493 isa<ConstantSDNode>(Op1.getOperand(1)));
6497 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6498 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6500 if (i * 2 < NumElts) {
6501 if (V0.getOpcode() == ISD::UNDEF)
6502 V0 = Op0.getOperand(0);
6504 if (V1.getOpcode() == ISD::UNDEF)
6505 V1 = Op0.getOperand(0);
6506 if (i * 2 == NumElts)
6507 ExpectedVExtractIdx = BaseIdx;
6510 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6511 if (I0 == ExpectedVExtractIdx)
6512 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6513 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6514 // Try to match the following dag sequence:
6515 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6516 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6520 ExpectedVExtractIdx += 2;
6526 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6527 /// a concat_vector.
6529 /// This is a helper function of PerformBUILD_VECTORCombine.
6530 /// This function expects two 256-bit vectors called V0 and V1.
6531 /// At first, each vector is split into two separate 128-bit vectors.
6532 /// Then, the resulting 128-bit vectors are used to implement two
6533 /// horizontal binary operations.
6535 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6537 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6538 /// the two new horizontal binop.
6539 /// When Mode is set, the first horizontal binop dag node would take as input
6540 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6541 /// horizontal binop dag node would take as input the lower 128-bit of V1
6542 /// and the upper 128-bit of V1.
6544 /// HADD V0_LO, V0_HI
6545 /// HADD V1_LO, V1_HI
6547 /// Otherwise, the first horizontal binop dag node takes as input the lower
6548 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6549 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6551 /// HADD V0_LO, V1_LO
6552 /// HADD V0_HI, V1_HI
6554 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6555 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6556 /// the upper 128-bits of the result.
6557 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6558 SDLoc DL, SelectionDAG &DAG,
6559 unsigned X86Opcode, bool Mode,
6560 bool isUndefLO, bool isUndefHI) {
6561 EVT VT = V0.getValueType();
6562 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6563 "Invalid nodes in input!");
6565 unsigned NumElts = VT.getVectorNumElements();
6566 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6567 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6568 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6569 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6570 EVT NewVT = V0_LO.getValueType();
6572 SDValue LO = DAG.getUNDEF(NewVT);
6573 SDValue HI = DAG.getUNDEF(NewVT);
6576 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6577 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6578 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6579 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6580 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6582 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6583 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6584 V1_LO->getOpcode() != ISD::UNDEF))
6585 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6587 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6588 V1_HI->getOpcode() != ISD::UNDEF))
6589 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6592 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6595 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6596 /// sequence of 'vadd + vsub + blendi'.
6597 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6598 const X86Subtarget *Subtarget) {
6600 EVT VT = BV->getValueType(0);
6601 unsigned NumElts = VT.getVectorNumElements();
6602 SDValue InVec0 = DAG.getUNDEF(VT);
6603 SDValue InVec1 = DAG.getUNDEF(VT);
6605 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6606 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6608 // Odd-numbered elements in the input build vector are obtained from
6609 // adding two integer/float elements.
6610 // Even-numbered elements in the input build vector are obtained from
6611 // subtracting two integer/float elements.
6612 unsigned ExpectedOpcode = ISD::FSUB;
6613 unsigned NextExpectedOpcode = ISD::FADD;
6614 bool AddFound = false;
6615 bool SubFound = false;
6617 for (unsigned i = 0, e = NumElts; i != e; i++) {
6618 SDValue Op = BV->getOperand(i);
6620 // Skip 'undef' values.
6621 unsigned Opcode = Op.getOpcode();
6622 if (Opcode == ISD::UNDEF) {
6623 std::swap(ExpectedOpcode, NextExpectedOpcode);
6627 // Early exit if we found an unexpected opcode.
6628 if (Opcode != ExpectedOpcode)
6631 SDValue Op0 = Op.getOperand(0);
6632 SDValue Op1 = Op.getOperand(1);
6634 // Try to match the following pattern:
6635 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6636 // Early exit if we cannot match that sequence.
6637 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6638 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6639 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6640 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6641 Op0.getOperand(1) != Op1.getOperand(1))
6644 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6648 // We found a valid add/sub node. Update the information accordingly.
6654 // Update InVec0 and InVec1.
6655 if (InVec0.getOpcode() == ISD::UNDEF)
6656 InVec0 = Op0.getOperand(0);
6657 if (InVec1.getOpcode() == ISD::UNDEF)
6658 InVec1 = Op1.getOperand(0);
6660 // Make sure that operands in input to each add/sub node always
6661 // come from a same pair of vectors.
6662 if (InVec0 != Op0.getOperand(0)) {
6663 if (ExpectedOpcode == ISD::FSUB)
6666 // FADD is commutable. Try to commute the operands
6667 // and then test again.
6668 std::swap(Op0, Op1);
6669 if (InVec0 != Op0.getOperand(0))
6673 if (InVec1 != Op1.getOperand(0))
6676 // Update the pair of expected opcodes.
6677 std::swap(ExpectedOpcode, NextExpectedOpcode);
6680 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6681 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6682 InVec1.getOpcode() != ISD::UNDEF)
6683 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6688 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6689 const X86Subtarget *Subtarget) {
6691 EVT VT = N->getValueType(0);
6692 unsigned NumElts = VT.getVectorNumElements();
6693 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6694 SDValue InVec0, InVec1;
6696 // Try to match an ADDSUB.
6697 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6698 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6699 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6700 if (Value.getNode())
6704 // Try to match horizontal ADD/SUB.
6705 unsigned NumUndefsLO = 0;
6706 unsigned NumUndefsHI = 0;
6707 unsigned Half = NumElts/2;
6709 // Count the number of UNDEF operands in the build_vector in input.
6710 for (unsigned i = 0, e = Half; i != e; ++i)
6711 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6714 for (unsigned i = Half, e = NumElts; i != e; ++i)
6715 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6718 // Early exit if this is either a build_vector of all UNDEFs or all the
6719 // operands but one are UNDEF.
6720 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6723 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6724 // Try to match an SSE3 float HADD/HSUB.
6725 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6728 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6729 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6730 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6731 // Try to match an SSSE3 integer HADD/HSUB.
6732 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6733 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6735 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6736 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6739 if (!Subtarget->hasAVX())
6742 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6743 // Try to match an AVX horizontal add/sub of packed single/double
6744 // precision floating point values from 256-bit vectors.
6745 SDValue InVec2, InVec3;
6746 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6747 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6748 ((InVec0.getOpcode() == ISD::UNDEF ||
6749 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6750 ((InVec1.getOpcode() == ISD::UNDEF ||
6751 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6752 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6754 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6755 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6756 ((InVec0.getOpcode() == ISD::UNDEF ||
6757 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6758 ((InVec1.getOpcode() == ISD::UNDEF ||
6759 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6760 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6761 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6762 // Try to match an AVX2 horizontal add/sub of signed integers.
6763 SDValue InVec2, InVec3;
6765 bool CanFold = true;
6767 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6768 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6769 ((InVec0.getOpcode() == ISD::UNDEF ||
6770 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6771 ((InVec1.getOpcode() == ISD::UNDEF ||
6772 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6773 X86Opcode = X86ISD::HADD;
6774 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6775 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6776 ((InVec0.getOpcode() == ISD::UNDEF ||
6777 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6778 ((InVec1.getOpcode() == ISD::UNDEF ||
6779 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6780 X86Opcode = X86ISD::HSUB;
6785 // Fold this build_vector into a single horizontal add/sub.
6786 // Do this only if the target has AVX2.
6787 if (Subtarget->hasAVX2())
6788 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6790 // Do not try to expand this build_vector into a pair of horizontal
6791 // add/sub if we can emit a pair of scalar add/sub.
6792 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6795 // Convert this build_vector into a pair of horizontal binop followed by
6797 bool isUndefLO = NumUndefsLO == Half;
6798 bool isUndefHI = NumUndefsHI == Half;
6799 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6800 isUndefLO, isUndefHI);
6804 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6805 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6807 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6808 X86Opcode = X86ISD::HADD;
6809 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6810 X86Opcode = X86ISD::HSUB;
6811 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6812 X86Opcode = X86ISD::FHADD;
6813 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6814 X86Opcode = X86ISD::FHSUB;
6818 // Don't try to expand this build_vector into a pair of horizontal add/sub
6819 // if we can simply emit a pair of scalar add/sub.
6820 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6823 // Convert this build_vector into two horizontal add/sub followed by
6825 bool isUndefLO = NumUndefsLO == Half;
6826 bool isUndefHI = NumUndefsHI == Half;
6827 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6828 isUndefLO, isUndefHI);
6835 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6838 MVT VT = Op.getSimpleValueType();
6839 MVT ExtVT = VT.getVectorElementType();
6840 unsigned NumElems = Op.getNumOperands();
6842 // Generate vectors for predicate vectors.
6843 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6844 return LowerBUILD_VECTORvXi1(Op, DAG);
6846 // Vectors containing all zeros can be matched by pxor and xorps later
6847 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6848 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6849 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6850 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6853 return getZeroVector(VT, Subtarget, DAG, dl);
6856 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6857 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6858 // vpcmpeqd on 256-bit vectors.
6859 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6860 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6863 if (!VT.is512BitVector())
6864 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6867 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6868 if (Broadcast.getNode())
6871 unsigned EVTBits = ExtVT.getSizeInBits();
6873 unsigned NumZero = 0;
6874 unsigned NumNonZero = 0;
6875 unsigned NonZeros = 0;
6876 bool IsAllConstants = true;
6877 SmallSet<SDValue, 8> Values;
6878 for (unsigned i = 0; i < NumElems; ++i) {
6879 SDValue Elt = Op.getOperand(i);
6880 if (Elt.getOpcode() == ISD::UNDEF)
6883 if (Elt.getOpcode() != ISD::Constant &&
6884 Elt.getOpcode() != ISD::ConstantFP)
6885 IsAllConstants = false;
6886 if (X86::isZeroNode(Elt))
6889 NonZeros |= (1 << i);
6894 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6895 if (NumNonZero == 0)
6896 return DAG.getUNDEF(VT);
6898 // Special case for single non-zero, non-undef, element.
6899 if (NumNonZero == 1) {
6900 unsigned Idx = countTrailingZeros(NonZeros);
6901 SDValue Item = Op.getOperand(Idx);
6903 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6904 // the value are obviously zero, truncate the value to i32 and do the
6905 // insertion that way. Only do this if the value is non-constant or if the
6906 // value is a constant being inserted into element 0. It is cheaper to do
6907 // a constant pool load than it is to do a movd + shuffle.
6908 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6909 (!IsAllConstants || Idx == 0)) {
6910 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6912 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6913 EVT VecVT = MVT::v4i32;
6914 unsigned VecElts = 4;
6916 // Truncate the value (which may itself be a constant) to i32, and
6917 // convert it to a vector with movd (S2V+shuffle to zero extend).
6918 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6921 // If using the new shuffle lowering, just directly insert this.
6922 if (ExperimentalVectorShuffleLowering)
6924 ISD::BITCAST, dl, VT,
6925 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6927 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6929 // Now we have our 32-bit value zero extended in the low element of
6930 // a vector. If Idx != 0, swizzle it into place.
6932 SmallVector<int, 4> Mask;
6933 Mask.push_back(Idx);
6934 for (unsigned i = 1; i != VecElts; ++i)
6936 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6939 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6943 // If we have a constant or non-constant insertion into the low element of
6944 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6945 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6946 // depending on what the source datatype is.
6949 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6951 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6952 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6953 if (VT.is256BitVector() || VT.is512BitVector()) {
6954 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6955 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6956 Item, DAG.getIntPtrConstant(0));
6958 assert(VT.is128BitVector() && "Expected an SSE value type!");
6959 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6960 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6961 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6964 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6965 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6966 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6967 if (VT.is256BitVector()) {
6968 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6969 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6971 assert(VT.is128BitVector() && "Expected an SSE value type!");
6972 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6974 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6978 // Is it a vector logical left shift?
6979 if (NumElems == 2 && Idx == 1 &&
6980 X86::isZeroNode(Op.getOperand(0)) &&
6981 !X86::isZeroNode(Op.getOperand(1))) {
6982 unsigned NumBits = VT.getSizeInBits();
6983 return getVShift(true, VT,
6984 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6985 VT, Op.getOperand(1)),
6986 NumBits/2, DAG, *this, dl);
6989 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6992 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6993 // is a non-constant being inserted into an element other than the low one,
6994 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6995 // movd/movss) to move this into the low element, then shuffle it into
6997 if (EVTBits == 32) {
6998 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7000 // If using the new shuffle lowering, just directly insert this.
7001 if (ExperimentalVectorShuffleLowering)
7002 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7004 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7005 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7006 SmallVector<int, 8> MaskVec;
7007 for (unsigned i = 0; i != NumElems; ++i)
7008 MaskVec.push_back(i == Idx ? 0 : 1);
7009 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7013 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7014 if (Values.size() == 1) {
7015 if (EVTBits == 32) {
7016 // Instead of a shuffle like this:
7017 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7018 // Check if it's possible to issue this instead.
7019 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7020 unsigned Idx = countTrailingZeros(NonZeros);
7021 SDValue Item = Op.getOperand(Idx);
7022 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7023 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7028 // A vector full of immediates; various special cases are already
7029 // handled, so this is best done with a single constant-pool load.
7033 // For AVX-length vectors, see if we can use a vector load to get all of the
7034 // elements, otherwise build the individual 128-bit pieces and use
7035 // shuffles to put them in place.
7036 if (VT.is256BitVector() || VT.is512BitVector()) {
7037 SmallVector<SDValue, 64> V;
7038 for (unsigned i = 0; i != NumElems; ++i)
7039 V.push_back(Op.getOperand(i));
7041 // Check for a build vector of consecutive loads.
7042 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7045 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7047 // Build both the lower and upper subvector.
7048 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7049 makeArrayRef(&V[0], NumElems/2));
7050 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7051 makeArrayRef(&V[NumElems / 2], NumElems/2));
7053 // Recreate the wider vector with the lower and upper part.
7054 if (VT.is256BitVector())
7055 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7056 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7059 // Let legalizer expand 2-wide build_vectors.
7060 if (EVTBits == 64) {
7061 if (NumNonZero == 1) {
7062 // One half is zero or undef.
7063 unsigned Idx = countTrailingZeros(NonZeros);
7064 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7065 Op.getOperand(Idx));
7066 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7071 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7072 if (EVTBits == 8 && NumElems == 16) {
7073 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7075 if (V.getNode()) return V;
7078 if (EVTBits == 16 && NumElems == 8) {
7079 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7081 if (V.getNode()) return V;
7084 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7085 if (EVTBits == 32 && NumElems == 4) {
7086 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7091 // If element VT is == 32 bits, turn it into a number of shuffles.
7092 SmallVector<SDValue, 8> V(NumElems);
7093 if (NumElems == 4 && NumZero > 0) {
7094 for (unsigned i = 0; i < 4; ++i) {
7095 bool isZero = !(NonZeros & (1 << i));
7097 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7099 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7102 for (unsigned i = 0; i < 2; ++i) {
7103 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7106 V[i] = V[i*2]; // Must be a zero vector.
7109 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7112 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7115 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7120 bool Reverse1 = (NonZeros & 0x3) == 2;
7121 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7125 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7126 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7128 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7131 if (Values.size() > 1 && VT.is128BitVector()) {
7132 // Check for a build vector of consecutive loads.
7133 for (unsigned i = 0; i < NumElems; ++i)
7134 V[i] = Op.getOperand(i);
7136 // Check for elements which are consecutive loads.
7137 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7141 // Check for a build vector from mostly shuffle plus few inserting.
7142 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7146 // For SSE 4.1, use insertps to put the high elements into the low element.
7147 if (getSubtarget()->hasSSE41()) {
7149 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7150 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7152 Result = DAG.getUNDEF(VT);
7154 for (unsigned i = 1; i < NumElems; ++i) {
7155 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7156 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7157 Op.getOperand(i), DAG.getIntPtrConstant(i));
7162 // Otherwise, expand into a number of unpckl*, start by extending each of
7163 // our (non-undef) elements to the full vector width with the element in the
7164 // bottom slot of the vector (which generates no code for SSE).
7165 for (unsigned i = 0; i < NumElems; ++i) {
7166 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7167 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7169 V[i] = DAG.getUNDEF(VT);
7172 // Next, we iteratively mix elements, e.g. for v4f32:
7173 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7174 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7175 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7176 unsigned EltStride = NumElems >> 1;
7177 while (EltStride != 0) {
7178 for (unsigned i = 0; i < EltStride; ++i) {
7179 // If V[i+EltStride] is undef and this is the first round of mixing,
7180 // then it is safe to just drop this shuffle: V[i] is already in the
7181 // right place, the one element (since it's the first round) being
7182 // inserted as undef can be dropped. This isn't safe for successive
7183 // rounds because they will permute elements within both vectors.
7184 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7185 EltStride == NumElems/2)
7188 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7197 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7198 // to create 256-bit vectors from two other 128-bit ones.
7199 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7201 MVT ResVT = Op.getSimpleValueType();
7203 assert((ResVT.is256BitVector() ||
7204 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7206 SDValue V1 = Op.getOperand(0);
7207 SDValue V2 = Op.getOperand(1);
7208 unsigned NumElems = ResVT.getVectorNumElements();
7209 if(ResVT.is256BitVector())
7210 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7212 if (Op.getNumOperands() == 4) {
7213 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7214 ResVT.getVectorNumElements()/2);
7215 SDValue V3 = Op.getOperand(2);
7216 SDValue V4 = Op.getOperand(3);
7217 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7218 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7220 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7223 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7224 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7225 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7226 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7227 Op.getNumOperands() == 4)));
7229 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7230 // from two other 128-bit ones.
7232 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7233 return LowerAVXCONCAT_VECTORS(Op, DAG);
7237 //===----------------------------------------------------------------------===//
7238 // Vector shuffle lowering
7240 // This is an experimental code path for lowering vector shuffles on x86. It is
7241 // designed to handle arbitrary vector shuffles and blends, gracefully
7242 // degrading performance as necessary. It works hard to recognize idiomatic
7243 // shuffles and lower them to optimal instruction patterns without leaving
7244 // a framework that allows reasonably efficient handling of all vector shuffle
7246 //===----------------------------------------------------------------------===//
7248 /// \brief Tiny helper function to identify a no-op mask.
7250 /// This is a somewhat boring predicate function. It checks whether the mask
7251 /// array input, which is assumed to be a single-input shuffle mask of the kind
7252 /// used by the X86 shuffle instructions (not a fully general
7253 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7254 /// in-place shuffle are 'no-op's.
7255 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7256 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7257 if (Mask[i] != -1 && Mask[i] != i)
7262 /// \brief Helper function to classify a mask as a single-input mask.
7264 /// This isn't a generic single-input test because in the vector shuffle
7265 /// lowering we canonicalize single inputs to be the first input operand. This
7266 /// means we can more quickly test for a single input by only checking whether
7267 /// an input from the second operand exists. We also assume that the size of
7268 /// mask corresponds to the size of the input vectors which isn't true in the
7269 /// fully general case.
7270 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7272 if (M >= (int)Mask.size())
7277 /// \brief Test whether there are elements crossing 128-bit lanes in this
7280 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7281 /// and we routinely test for these.
7282 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7283 int LaneSize = 128 / VT.getScalarSizeInBits();
7284 int Size = Mask.size();
7285 for (int i = 0; i < Size; ++i)
7286 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7291 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7293 /// This checks a shuffle mask to see if it is performing the same
7294 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7295 /// that it is also not lane-crossing. It may however involve a blend from the
7296 /// same lane of a second vector.
7298 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7299 /// non-trivial to compute in the face of undef lanes. The representation is
7300 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7301 /// entries from both V1 and V2 inputs to the wider mask.
7303 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7304 SmallVectorImpl<int> &RepeatedMask) {
7305 int LaneSize = 128 / VT.getScalarSizeInBits();
7306 RepeatedMask.resize(LaneSize, -1);
7307 int Size = Mask.size();
7308 for (int i = 0; i < Size; ++i) {
7311 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7312 // This entry crosses lanes, so there is no way to model this shuffle.
7315 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7316 if (RepeatedMask[i % LaneSize] == -1)
7317 // This is the first non-undef entry in this slot of a 128-bit lane.
7318 RepeatedMask[i % LaneSize] =
7319 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7320 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7321 // Found a mismatch with the repeated mask.
7327 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7328 // 2013 will allow us to use it as a non-type template parameter.
7331 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7333 /// See its documentation for details.
7334 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7335 if (Mask.size() != Args.size())
7337 for (int i = 0, e = Mask.size(); i < e; ++i) {
7338 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7339 if (Mask[i] != -1 && Mask[i] != *Args[i])
7347 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7350 /// This is a fast way to test a shuffle mask against a fixed pattern:
7352 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7354 /// It returns true if the mask is exactly as wide as the argument list, and
7355 /// each element of the mask is either -1 (signifying undef) or the value given
7356 /// in the argument.
7357 static const VariadicFunction1<
7358 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7360 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7362 /// This helper function produces an 8-bit shuffle immediate corresponding to
7363 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7364 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7367 /// NB: We rely heavily on "undef" masks preserving the input lane.
7368 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7369 SelectionDAG &DAG) {
7370 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7371 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7372 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7373 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7374 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7377 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7378 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7379 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7380 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7381 return DAG.getConstant(Imm, MVT::i8);
7384 /// \brief Try to emit a blend instruction for a shuffle.
7386 /// This doesn't do any checks for the availability of instructions for blending
7387 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7388 /// be matched in the backend with the type given. What it does check for is
7389 /// that the shuffle mask is in fact a blend.
7390 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7391 SDValue V2, ArrayRef<int> Mask,
7392 const X86Subtarget *Subtarget,
7393 SelectionDAG &DAG) {
7395 unsigned BlendMask = 0;
7396 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7397 if (Mask[i] >= Size) {
7398 if (Mask[i] != i + Size)
7399 return SDValue(); // Shuffled V2 input!
7400 BlendMask |= 1u << i;
7403 if (Mask[i] >= 0 && Mask[i] != i)
7404 return SDValue(); // Shuffled V1 input!
7406 switch (VT.SimpleTy) {
7411 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7412 DAG.getConstant(BlendMask, MVT::i8));
7416 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7420 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7421 // that instruction.
7422 if (Subtarget->hasAVX2()) {
7423 // Scale the blend by the number of 32-bit dwords per element.
7424 int Scale = VT.getScalarSizeInBits() / 32;
7426 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7427 if (Mask[i] >= Size)
7428 for (int j = 0; j < Scale; ++j)
7429 BlendMask |= 1u << (i * Scale + j);
7431 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7432 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7433 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7434 return DAG.getNode(ISD::BITCAST, DL, VT,
7435 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7436 DAG.getConstant(BlendMask, MVT::i8)));
7440 // For integer shuffles we need to expand the mask and cast the inputs to
7441 // v8i16s prior to blending.
7442 int Scale = 8 / VT.getVectorNumElements();
7444 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7445 if (Mask[i] >= Size)
7446 for (int j = 0; j < Scale; ++j)
7447 BlendMask |= 1u << (i * Scale + j);
7449 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7450 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7451 return DAG.getNode(ISD::BITCAST, DL, VT,
7452 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7453 DAG.getConstant(BlendMask, MVT::i8)));
7457 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7458 SmallVector<int, 8> RepeatedMask;
7459 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7460 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7461 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7463 for (int i = 0; i < 8; ++i)
7464 if (RepeatedMask[i] >= 16)
7465 BlendMask |= 1u << i;
7466 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7467 DAG.getConstant(BlendMask, MVT::i8));
7472 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7473 // Scale the blend by the number of bytes per element.
7474 int Scale = VT.getScalarSizeInBits() / 8;
7475 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7477 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7478 // mix of LLVM's code generator and the x86 backend. We tell the code
7479 // generator that boolean values in the elements of an x86 vector register
7480 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7481 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7482 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7483 // of the element (the remaining are ignored) and 0 in that high bit would
7484 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7485 // the LLVM model for boolean values in vector elements gets the relevant
7486 // bit set, it is set backwards and over constrained relative to x86's
7488 SDValue VSELECTMask[32];
7489 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7490 for (int j = 0; j < Scale; ++j)
7491 VSELECTMask[Scale * i + j] =
7492 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7493 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7495 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7496 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7498 ISD::BITCAST, DL, VT,
7499 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7500 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7505 llvm_unreachable("Not a supported integer vector type!");
7509 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7510 /// unblended shuffles followed by an unshuffled blend.
7512 /// This matches the extremely common pattern for handling combined
7513 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7515 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7519 SelectionDAG &DAG) {
7520 // Shuffle the input elements into the desired positions in V1 and V2 and
7521 // blend them together.
7522 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7523 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7524 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7525 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7526 if (Mask[i] >= 0 && Mask[i] < Size) {
7527 V1Mask[i] = Mask[i];
7529 } else if (Mask[i] >= Size) {
7530 V2Mask[i] = Mask[i] - Size;
7531 BlendMask[i] = i + Size;
7534 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7535 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7536 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7539 /// \brief Try to lower a vector shuffle as a byte rotation.
7541 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7542 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7543 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7544 /// try to generically lower a vector shuffle through such an pattern. It
7545 /// does not check for the profitability of lowering either as PALIGNR or
7546 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7547 /// This matches shuffle vectors that look like:
7549 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7551 /// Essentially it concatenates V1 and V2, shifts right by some number of
7552 /// elements, and takes the low elements as the result. Note that while this is
7553 /// specified as a *right shift* because x86 is little-endian, it is a *left
7554 /// rotate* of the vector lanes.
7556 /// Note that this only handles 128-bit vector widths currently.
7557 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7560 const X86Subtarget *Subtarget,
7561 SelectionDAG &DAG) {
7562 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7564 // We need to detect various ways of spelling a rotation:
7565 // [11, 12, 13, 14, 15, 0, 1, 2]
7566 // [-1, 12, 13, 14, -1, -1, 1, -1]
7567 // [-1, -1, -1, -1, -1, -1, 1, 2]
7568 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7569 // [-1, 4, 5, 6, -1, -1, 9, -1]
7570 // [-1, 4, 5, 6, -1, -1, -1, -1]
7573 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7576 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7578 // Based on the mod-Size value of this mask element determine where
7579 // a rotated vector would have started.
7580 int StartIdx = i - (Mask[i] % Size);
7582 // The identity rotation isn't interesting, stop.
7585 // If we found the tail of a vector the rotation must be the missing
7586 // front. If we found the head of a vector, it must be how much of the head.
7587 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7590 Rotation = CandidateRotation;
7591 else if (Rotation != CandidateRotation)
7592 // The rotations don't match, so we can't match this mask.
7595 // Compute which value this mask is pointing at.
7596 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7598 // Compute which of the two target values this index should be assigned to.
7599 // This reflects whether the high elements are remaining or the low elements
7601 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7603 // Either set up this value if we've not encountered it before, or check
7604 // that it remains consistent.
7607 else if (TargetV != MaskV)
7608 // This may be a rotation, but it pulls from the inputs in some
7609 // unsupported interleaving.
7613 // Check that we successfully analyzed the mask, and normalize the results.
7614 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7615 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7621 assert(VT.getSizeInBits() == 128 &&
7622 "Rotate-based lowering only supports 128-bit lowering!");
7623 assert(Mask.size() <= 16 &&
7624 "Can shuffle at most 16 bytes in a 128-bit vector!");
7626 // The actual rotate instruction rotates bytes, so we need to scale the
7627 // rotation based on how many bytes are in the vector.
7628 int Scale = 16 / Mask.size();
7630 // SSSE3 targets can use the palignr instruction
7631 if (Subtarget->hasSSSE3()) {
7632 // Cast the inputs to v16i8 to match PALIGNR.
7633 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7634 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7636 return DAG.getNode(ISD::BITCAST, DL, VT,
7637 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7638 DAG.getConstant(Rotation * Scale, MVT::i8)));
7641 // Default SSE2 implementation
7642 int LoByteShift = 16 - Rotation * Scale;
7643 int HiByteShift = Rotation * Scale;
7645 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7646 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7647 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7649 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7650 DAG.getConstant(8 * LoByteShift, MVT::i8));
7651 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7652 DAG.getConstant(8 * HiByteShift, MVT::i8));
7653 return DAG.getNode(ISD::BITCAST, DL, VT,
7654 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7657 /// \brief Compute whether each element of a shuffle is zeroable.
7659 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7660 /// Either it is an undef element in the shuffle mask, the element of the input
7661 /// referenced is undef, or the element of the input referenced is known to be
7662 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7663 /// as many lanes with this technique as possible to simplify the remaining
7665 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7666 SDValue V1, SDValue V2) {
7667 SmallBitVector Zeroable(Mask.size(), false);
7669 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7670 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7672 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7674 // Handle the easy cases.
7675 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7680 // If this is an index into a build_vector node, dig out the input value and
7682 SDValue V = M < Size ? V1 : V2;
7683 if (V.getOpcode() != ISD::BUILD_VECTOR)
7686 SDValue Input = V.getOperand(M % Size);
7687 // The UNDEF opcode check really should be dead code here, but not quite
7688 // worth asserting on (it isn't invalid, just unexpected).
7689 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7696 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7698 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7699 /// byte-shift instructions. The mask must consist of a shifted sequential
7700 /// shuffle from one of the input vectors and zeroable elements for the
7701 /// remaining 'shifted in' elements.
7703 /// Note that this only handles 128-bit vector widths currently.
7704 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7705 SDValue V2, ArrayRef<int> Mask,
7706 SelectionDAG &DAG) {
7707 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7709 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7711 int Size = Mask.size();
7712 int Scale = 16 / Size;
7714 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7715 ArrayRef<int> Mask) {
7716 for (int i = StartIndex; i < EndIndex; i++) {
7719 if (i + Base != Mask[i] - MaskOffset)
7725 for (int Shift = 1; Shift < Size; Shift++) {
7726 int ByteShift = Shift * Scale;
7728 // PSRLDQ : (little-endian) right byte shift
7729 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7730 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7731 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7732 bool ZeroableRight = true;
7733 for (int i = Size - Shift; i < Size; i++) {
7734 ZeroableRight &= Zeroable[i];
7737 if (ZeroableRight) {
7738 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7739 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7741 if (ValidShiftRight1 || ValidShiftRight2) {
7742 // Cast the inputs to v2i64 to match PSRLDQ.
7743 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7744 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7745 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7746 DAG.getConstant(ByteShift * 8, MVT::i8));
7747 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7751 // PSLLDQ : (little-endian) left byte shift
7752 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7753 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7754 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7755 bool ZeroableLeft = true;
7756 for (int i = 0; i < Shift; i++) {
7757 ZeroableLeft &= Zeroable[i];
7761 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7762 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7764 if (ValidShiftLeft1 || ValidShiftLeft2) {
7765 // Cast the inputs to v2i64 to match PSLLDQ.
7766 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7767 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7768 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7769 DAG.getConstant(ByteShift * 8, MVT::i8));
7770 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7778 /// \brief Lower a vector shuffle as a zero or any extension.
7780 /// Given a specific number of elements, element bit width, and extension
7781 /// stride, produce either a zero or any extension based on the available
7782 /// features of the subtarget.
7783 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7784 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7785 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7786 assert(Scale > 1 && "Need a scale to extend.");
7787 int EltBits = VT.getSizeInBits() / NumElements;
7788 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7789 "Only 8, 16, and 32 bit elements can be extended.");
7790 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7792 // Found a valid zext mask! Try various lowering strategies based on the
7793 // input type and available ISA extensions.
7794 if (Subtarget->hasSSE41()) {
7795 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7796 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7797 NumElements / Scale);
7798 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7799 return DAG.getNode(ISD::BITCAST, DL, VT,
7800 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7803 // For any extends we can cheat for larger element sizes and use shuffle
7804 // instructions that can fold with a load and/or copy.
7805 if (AnyExt && EltBits == 32) {
7806 int PSHUFDMask[4] = {0, -1, 1, -1};
7808 ISD::BITCAST, DL, VT,
7809 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7810 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7811 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7813 if (AnyExt && EltBits == 16 && Scale > 2) {
7814 int PSHUFDMask[4] = {0, -1, 0, -1};
7815 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7816 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7817 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7818 int PSHUFHWMask[4] = {1, -1, -1, -1};
7820 ISD::BITCAST, DL, VT,
7821 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7822 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7823 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7826 // If this would require more than 2 unpack instructions to expand, use
7827 // pshufb when available. We can only use more than 2 unpack instructions
7828 // when zero extending i8 elements which also makes it easier to use pshufb.
7829 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7830 assert(NumElements == 16 && "Unexpected byte vector width!");
7831 SDValue PSHUFBMask[16];
7832 for (int i = 0; i < 16; ++i)
7834 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7835 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7836 return DAG.getNode(ISD::BITCAST, DL, VT,
7837 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7838 DAG.getNode(ISD::BUILD_VECTOR, DL,
7839 MVT::v16i8, PSHUFBMask)));
7842 // Otherwise emit a sequence of unpacks.
7844 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7845 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7846 : getZeroVector(InputVT, Subtarget, DAG, DL);
7847 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7848 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7852 } while (Scale > 1);
7853 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7856 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7858 /// This routine will try to do everything in its power to cleverly lower
7859 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7860 /// check for the profitability of this lowering, it tries to aggressively
7861 /// match this pattern. It will use all of the micro-architectural details it
7862 /// can to emit an efficient lowering. It handles both blends with all-zero
7863 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7864 /// masking out later).
7866 /// The reason we have dedicated lowering for zext-style shuffles is that they
7867 /// are both incredibly common and often quite performance sensitive.
7868 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7869 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7870 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7871 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7873 int Bits = VT.getSizeInBits();
7874 int NumElements = Mask.size();
7876 // Define a helper function to check a particular ext-scale and lower to it if
7878 auto Lower = [&](int Scale) -> SDValue {
7881 for (int i = 0; i < NumElements; ++i) {
7883 continue; // Valid anywhere but doesn't tell us anything.
7884 if (i % Scale != 0) {
7885 // Each of the extend elements needs to be zeroable.
7889 // We no lorger are in the anyext case.
7894 // Each of the base elements needs to be consecutive indices into the
7895 // same input vector.
7896 SDValue V = Mask[i] < NumElements ? V1 : V2;
7899 else if (InputV != V)
7900 return SDValue(); // Flip-flopping inputs.
7902 if (Mask[i] % NumElements != i / Scale)
7903 return SDValue(); // Non-consecutive strided elemenst.
7906 // If we fail to find an input, we have a zero-shuffle which should always
7907 // have already been handled.
7908 // FIXME: Maybe handle this here in case during blending we end up with one?
7912 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7913 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7916 // The widest scale possible for extending is to a 64-bit integer.
7917 assert(Bits % 64 == 0 &&
7918 "The number of bits in a vector must be divisible by 64 on x86!");
7919 int NumExtElements = Bits / 64;
7921 // Each iteration, try extending the elements half as much, but into twice as
7923 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7924 assert(NumElements % NumExtElements == 0 &&
7925 "The input vector size must be divisble by the extended size.");
7926 if (SDValue V = Lower(NumElements / NumExtElements))
7930 // No viable ext lowering found.
7934 /// \brief Try to get a scalar value for a specific element of a vector.
7936 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7937 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7938 SelectionDAG &DAG) {
7939 MVT VT = V.getSimpleValueType();
7940 MVT EltVT = VT.getVectorElementType();
7941 while (V.getOpcode() == ISD::BITCAST)
7942 V = V.getOperand(0);
7943 // If the bitcasts shift the element size, we can't extract an equivalent
7945 MVT NewVT = V.getSimpleValueType();
7946 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7949 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7950 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7951 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7956 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7958 /// This is particularly important because the set of instructions varies
7959 /// significantly based on whether the operand is a load or not.
7960 static bool isShuffleFoldableLoad(SDValue V) {
7961 while (V.getOpcode() == ISD::BITCAST)
7962 V = V.getOperand(0);
7964 return ISD::isNON_EXTLoad(V.getNode());
7967 /// \brief Try to lower insertion of a single element into a zero vector.
7969 /// This is a common pattern that we have especially efficient patterns to lower
7970 /// across all subtarget feature sets.
7971 static SDValue lowerVectorShuffleAsElementInsertion(
7972 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7973 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7974 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7976 MVT EltVT = VT.getVectorElementType();
7978 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7979 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7981 bool IsV1Zeroable = true;
7982 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7983 if (i != V2Index && !Zeroable[i]) {
7984 IsV1Zeroable = false;
7988 // Check for a single input from a SCALAR_TO_VECTOR node.
7989 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7990 // all the smarts here sunk into that routine. However, the current
7991 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7992 // vector shuffle lowering is dead.
7993 if (SDValue V2S = getScalarValueForVectorElement(
7994 V2, Mask[V2Index] - Mask.size(), DAG)) {
7995 // We need to zext the scalar if it is smaller than an i32.
7996 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7997 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7998 // Using zext to expand a narrow element won't work for non-zero
8003 // Zero-extend directly to i32.
8005 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8007 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8008 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8009 EltVT == MVT::i16) {
8010 // Either not inserting from the low element of the input or the input
8011 // element size is too small to use VZEXT_MOVL to clear the high bits.
8015 if (!IsV1Zeroable) {
8016 // If V1 can't be treated as a zero vector we have fewer options to lower
8017 // this. We can't support integer vectors or non-zero targets cheaply, and
8018 // the V1 elements can't be permuted in any way.
8019 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8020 if (!VT.isFloatingPoint() || V2Index != 0)
8022 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8023 V1Mask[V2Index] = -1;
8024 if (!isNoopShuffleMask(V1Mask))
8026 // This is essentially a special case blend operation, but if we have
8027 // general purpose blend operations, they are always faster. Bail and let
8028 // the rest of the lowering handle these as blends.
8029 if (Subtarget->hasSSE41())
8032 // Otherwise, use MOVSD or MOVSS.
8033 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8034 "Only two types of floating point element types to handle!");
8035 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8039 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8041 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8044 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8045 // the desired position. Otherwise it is more efficient to do a vector
8046 // shift left. We know that we can do a vector shift left because all
8047 // the inputs are zero.
8048 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8049 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8050 V2Shuffle[V2Index] = 0;
8051 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8053 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8055 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8057 V2Index * EltVT.getSizeInBits(),
8058 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8059 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8065 /// \brief Try to lower broadcast of a single element.
8067 /// For convenience, this code also bundles all of the subtarget feature set
8068 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8069 /// a convenient way to factor it out.
8070 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8072 const X86Subtarget *Subtarget,
8073 SelectionDAG &DAG) {
8074 if (!Subtarget->hasAVX())
8076 if (VT.isInteger() && !Subtarget->hasAVX2())
8079 // Check that the mask is a broadcast.
8080 int BroadcastIdx = -1;
8082 if (M >= 0 && BroadcastIdx == -1)
8084 else if (M >= 0 && M != BroadcastIdx)
8087 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8088 "a sorted mask where the broadcast "
8091 // Go up the chain of (vector) values to try and find a scalar load that
8092 // we can combine with the broadcast.
8094 switch (V.getOpcode()) {
8095 case ISD::CONCAT_VECTORS: {
8096 int OperandSize = Mask.size() / V.getNumOperands();
8097 V = V.getOperand(BroadcastIdx / OperandSize);
8098 BroadcastIdx %= OperandSize;
8102 case ISD::INSERT_SUBVECTOR: {
8103 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8104 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8108 int BeginIdx = (int)ConstantIdx->getZExtValue();
8110 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8111 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8112 BroadcastIdx -= BeginIdx;
8123 // Check if this is a broadcast of a scalar. We special case lowering
8124 // for scalars so that we can more effectively fold with loads.
8125 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8126 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8127 V = V.getOperand(BroadcastIdx);
8129 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8131 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8133 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8134 // We can't broadcast from a vector register w/o AVX2, and we can only
8135 // broadcast from the zero-element of a vector register.
8139 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8142 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8144 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8145 /// support for floating point shuffles but not integer shuffles. These
8146 /// instructions will incur a domain crossing penalty on some chips though so
8147 /// it is better to avoid lowering through this for integer vectors where
8149 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8150 const X86Subtarget *Subtarget,
8151 SelectionDAG &DAG) {
8153 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8154 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8155 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8157 ArrayRef<int> Mask = SVOp->getMask();
8158 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8160 if (isSingleInputShuffleMask(Mask)) {
8161 // Straight shuffle of a single input vector. Simulate this by using the
8162 // single input as both of the "inputs" to this instruction..
8163 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8165 if (Subtarget->hasAVX()) {
8166 // If we have AVX, we can use VPERMILPS which will allow folding a load
8167 // into the shuffle.
8168 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8169 DAG.getConstant(SHUFPDMask, MVT::i8));
8172 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8173 DAG.getConstant(SHUFPDMask, MVT::i8));
8175 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8176 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8178 // Use dedicated unpack instructions for masks that match their pattern.
8179 if (isShuffleEquivalent(Mask, 0, 2))
8180 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8181 if (isShuffleEquivalent(Mask, 1, 3))
8182 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8184 // If we have a single input, insert that into V1 if we can do so cheaply.
8185 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8186 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8187 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8189 // Try inverting the insertion since for v2 masks it is easy to do and we
8190 // can't reliably sort the mask one way or the other.
8191 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8192 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8193 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8194 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8198 // Try to use one of the special instruction patterns to handle two common
8199 // blend patterns if a zero-blend above didn't work.
8200 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8201 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8202 // We can either use a special instruction to load over the low double or
8203 // to move just the low double.
8205 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8207 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8209 if (Subtarget->hasSSE41())
8210 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8214 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8215 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8216 DAG.getConstant(SHUFPDMask, MVT::i8));
8219 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8221 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8222 /// the integer unit to minimize domain crossing penalties. However, for blends
8223 /// it falls back to the floating point shuffle operation with appropriate bit
8225 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8226 const X86Subtarget *Subtarget,
8227 SelectionDAG &DAG) {
8229 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8230 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8231 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8233 ArrayRef<int> Mask = SVOp->getMask();
8234 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8236 if (isSingleInputShuffleMask(Mask)) {
8237 // Check for being able to broadcast a single element.
8238 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8239 Mask, Subtarget, DAG))
8242 // Straight shuffle of a single input vector. For everything from SSE2
8243 // onward this has a single fast instruction with no scary immediates.
8244 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8245 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8246 int WidenedMask[4] = {
8247 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8248 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8250 ISD::BITCAST, DL, MVT::v2i64,
8251 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8252 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8255 // Try to use byte shift instructions.
8256 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8257 DL, MVT::v2i64, V1, V2, Mask, DAG))
8260 // If we have a single input from V2 insert that into V1 if we can do so
8262 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8263 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8264 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8266 // Try inverting the insertion since for v2 masks it is easy to do and we
8267 // can't reliably sort the mask one way or the other.
8268 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8269 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8270 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8271 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8275 // Use dedicated unpack instructions for masks that match their pattern.
8276 if (isShuffleEquivalent(Mask, 0, 2))
8277 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8278 if (isShuffleEquivalent(Mask, 1, 3))
8279 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8281 if (Subtarget->hasSSE41())
8282 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8286 // Try to use byte rotation instructions.
8287 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8288 if (Subtarget->hasSSSE3())
8289 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8290 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8293 // We implement this with SHUFPD which is pretty lame because it will likely
8294 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8295 // However, all the alternatives are still more cycles and newer chips don't
8296 // have this problem. It would be really nice if x86 had better shuffles here.
8297 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8298 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8299 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8300 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8303 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8305 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8306 /// It makes no assumptions about whether this is the *best* lowering, it simply
8308 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8309 ArrayRef<int> Mask, SDValue V1,
8310 SDValue V2, SelectionDAG &DAG) {
8311 SDValue LowV = V1, HighV = V2;
8312 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8315 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8317 if (NumV2Elements == 1) {
8319 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8322 // Compute the index adjacent to V2Index and in the same half by toggling
8324 int V2AdjIndex = V2Index ^ 1;
8326 if (Mask[V2AdjIndex] == -1) {
8327 // Handles all the cases where we have a single V2 element and an undef.
8328 // This will only ever happen in the high lanes because we commute the
8329 // vector otherwise.
8331 std::swap(LowV, HighV);
8332 NewMask[V2Index] -= 4;
8334 // Handle the case where the V2 element ends up adjacent to a V1 element.
8335 // To make this work, blend them together as the first step.
8336 int V1Index = V2AdjIndex;
8337 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8338 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8339 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8341 // Now proceed to reconstruct the final blend as we have the necessary
8342 // high or low half formed.
8349 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8350 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8352 } else if (NumV2Elements == 2) {
8353 if (Mask[0] < 4 && Mask[1] < 4) {
8354 // Handle the easy case where we have V1 in the low lanes and V2 in the
8358 } else if (Mask[2] < 4 && Mask[3] < 4) {
8359 // We also handle the reversed case because this utility may get called
8360 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8361 // arrange things in the right direction.
8367 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8368 // trying to place elements directly, just blend them and set up the final
8369 // shuffle to place them.
8371 // The first two blend mask elements are for V1, the second two are for
8373 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8374 Mask[2] < 4 ? Mask[2] : Mask[3],
8375 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8376 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8377 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8378 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8380 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8383 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8384 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8385 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8386 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8389 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8390 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8393 /// \brief Lower 4-lane 32-bit floating point shuffles.
8395 /// Uses instructions exclusively from the floating point unit to minimize
8396 /// domain crossing penalties, as these are sufficient to implement all v4f32
8398 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8399 const X86Subtarget *Subtarget,
8400 SelectionDAG &DAG) {
8402 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8403 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8404 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8406 ArrayRef<int> Mask = SVOp->getMask();
8407 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8410 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8412 if (NumV2Elements == 0) {
8413 // Check for being able to broadcast a single element.
8414 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8415 Mask, Subtarget, DAG))
8418 if (Subtarget->hasAVX()) {
8419 // If we have AVX, we can use VPERMILPS which will allow folding a load
8420 // into the shuffle.
8421 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8422 getV4X86ShuffleImm8ForMask(Mask, DAG));
8425 // Otherwise, use a straight shuffle of a single input vector. We pass the
8426 // input vector to both operands to simulate this with a SHUFPS.
8427 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8428 getV4X86ShuffleImm8ForMask(Mask, DAG));
8431 // Use dedicated unpack instructions for masks that match their pattern.
8432 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8433 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8434 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8435 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8437 // There are special ways we can lower some single-element blends. However, we
8438 // have custom ways we can lower more complex single-element blends below that
8439 // we defer to if both this and BLENDPS fail to match, so restrict this to
8440 // when the V2 input is targeting element 0 of the mask -- that is the fast
8442 if (NumV2Elements == 1 && Mask[0] >= 4)
8443 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8444 Mask, Subtarget, DAG))
8447 if (Subtarget->hasSSE41())
8448 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8452 // Check for whether we can use INSERTPS to perform the blend. We only use
8453 // INSERTPS when the V1 elements are already in the correct locations
8454 // because otherwise we can just always use two SHUFPS instructions which
8455 // are much smaller to encode than a SHUFPS and an INSERTPS.
8456 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8458 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8461 // When using INSERTPS we can zero any lane of the destination. Collect
8462 // the zero inputs into a mask and drop them from the lanes of V1 which
8463 // actually need to be present as inputs to the INSERTPS.
8464 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8466 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8467 bool InsertNeedsShuffle = false;
8469 for (int i = 0; i < 4; ++i)
8473 } else if (Mask[i] != i) {
8474 InsertNeedsShuffle = true;
8479 // We don't want to use INSERTPS or other insertion techniques if it will
8480 // require shuffling anyways.
8481 if (!InsertNeedsShuffle) {
8482 // If all of V1 is zeroable, replace it with undef.
8483 if ((ZMask | 1 << V2Index) == 0xF)
8484 V1 = DAG.getUNDEF(MVT::v4f32);
8486 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8487 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8489 // Insert the V2 element into the desired position.
8490 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8491 DAG.getConstant(InsertPSMask, MVT::i8));
8495 // Otherwise fall back to a SHUFPS lowering strategy.
8496 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8499 /// \brief Lower 4-lane i32 vector shuffles.
8501 /// We try to handle these with integer-domain shuffles where we can, but for
8502 /// blends we use the floating point domain blend instructions.
8503 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8504 const X86Subtarget *Subtarget,
8505 SelectionDAG &DAG) {
8507 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8508 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8509 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8510 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8511 ArrayRef<int> Mask = SVOp->getMask();
8512 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8514 // Whenever we can lower this as a zext, that instruction is strictly faster
8515 // than any alternative. It also allows us to fold memory operands into the
8516 // shuffle in many cases.
8517 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8518 Mask, Subtarget, DAG))
8522 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8524 if (NumV2Elements == 0) {
8525 // Check for being able to broadcast a single element.
8526 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8527 Mask, Subtarget, DAG))
8530 // Straight shuffle of a single input vector. For everything from SSE2
8531 // onward this has a single fast instruction with no scary immediates.
8532 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8533 // but we aren't actually going to use the UNPCK instruction because doing
8534 // so prevents folding a load into this instruction or making a copy.
8535 const int UnpackLoMask[] = {0, 0, 1, 1};
8536 const int UnpackHiMask[] = {2, 2, 3, 3};
8537 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8538 Mask = UnpackLoMask;
8539 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8540 Mask = UnpackHiMask;
8542 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8543 getV4X86ShuffleImm8ForMask(Mask, DAG));
8546 // Try to use byte shift instructions.
8547 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8548 DL, MVT::v4i32, V1, V2, Mask, DAG))
8551 // There are special ways we can lower some single-element blends.
8552 if (NumV2Elements == 1)
8553 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8554 Mask, Subtarget, DAG))
8557 // Use dedicated unpack instructions for masks that match their pattern.
8558 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8559 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8560 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8561 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8563 if (Subtarget->hasSSE41())
8564 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8568 // Try to use byte rotation instructions.
8569 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8570 if (Subtarget->hasSSSE3())
8571 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8572 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8575 // We implement this with SHUFPS because it can blend from two vectors.
8576 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8577 // up the inputs, bypassing domain shift penalties that we would encur if we
8578 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8580 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8581 DAG.getVectorShuffle(
8583 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8584 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8587 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8588 /// shuffle lowering, and the most complex part.
8590 /// The lowering strategy is to try to form pairs of input lanes which are
8591 /// targeted at the same half of the final vector, and then use a dword shuffle
8592 /// to place them onto the right half, and finally unpack the paired lanes into
8593 /// their final position.
8595 /// The exact breakdown of how to form these dword pairs and align them on the
8596 /// correct sides is really tricky. See the comments within the function for
8597 /// more of the details.
8598 static SDValue lowerV8I16SingleInputVectorShuffle(
8599 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8600 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8601 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8602 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8603 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8605 SmallVector<int, 4> LoInputs;
8606 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8607 [](int M) { return M >= 0; });
8608 std::sort(LoInputs.begin(), LoInputs.end());
8609 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8610 SmallVector<int, 4> HiInputs;
8611 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8612 [](int M) { return M >= 0; });
8613 std::sort(HiInputs.begin(), HiInputs.end());
8614 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8616 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8617 int NumHToL = LoInputs.size() - NumLToL;
8619 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8620 int NumHToH = HiInputs.size() - NumLToH;
8621 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8622 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8623 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8624 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8626 // Check for being able to broadcast a single element.
8627 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8628 Mask, Subtarget, DAG))
8631 // Try to use byte shift instructions.
8632 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8633 DL, MVT::v8i16, V, V, Mask, DAG))
8636 // Use dedicated unpack instructions for masks that match their pattern.
8637 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8638 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8639 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8640 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8642 // Try to use byte rotation instructions.
8643 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8644 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8647 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8648 // such inputs we can swap two of the dwords across the half mark and end up
8649 // with <=2 inputs to each half in each half. Once there, we can fall through
8650 // to the generic code below. For example:
8652 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8653 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8655 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8656 // and an existing 2-into-2 on the other half. In this case we may have to
8657 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8658 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8659 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8660 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8661 // half than the one we target for fixing) will be fixed when we re-enter this
8662 // path. We will also combine away any sequence of PSHUFD instructions that
8663 // result into a single instruction. Here is an example of the tricky case:
8665 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8666 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8668 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8670 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8671 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8673 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8674 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8676 // The result is fine to be handled by the generic logic.
8677 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8678 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8679 int AOffset, int BOffset) {
8680 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8681 "Must call this with A having 3 or 1 inputs from the A half.");
8682 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8683 "Must call this with B having 1 or 3 inputs from the B half.");
8684 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8685 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8687 // Compute the index of dword with only one word among the three inputs in
8688 // a half by taking the sum of the half with three inputs and subtracting
8689 // the sum of the actual three inputs. The difference is the remaining
8692 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8693 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8694 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8695 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8696 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8697 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8698 int TripleNonInputIdx =
8699 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8700 TripleDWord = TripleNonInputIdx / 2;
8702 // We use xor with one to compute the adjacent DWord to whichever one the
8704 OneInputDWord = (OneInput / 2) ^ 1;
8706 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8707 // and BToA inputs. If there is also such a problem with the BToB and AToB
8708 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8709 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8710 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8711 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8712 // Compute how many inputs will be flipped by swapping these DWords. We
8714 // to balance this to ensure we don't form a 3-1 shuffle in the other
8716 int NumFlippedAToBInputs =
8717 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8718 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8719 int NumFlippedBToBInputs =
8720 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8721 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8722 if ((NumFlippedAToBInputs == 1 &&
8723 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8724 (NumFlippedBToBInputs == 1 &&
8725 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8726 // We choose whether to fix the A half or B half based on whether that
8727 // half has zero flipped inputs. At zero, we may not be able to fix it
8728 // with that half. We also bias towards fixing the B half because that
8729 // will more commonly be the high half, and we have to bias one way.
8730 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8731 ArrayRef<int> Inputs) {
8732 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8733 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8734 PinnedIdx ^ 1) != Inputs.end();
8735 // Determine whether the free index is in the flipped dword or the
8736 // unflipped dword based on where the pinned index is. We use this bit
8737 // in an xor to conditionally select the adjacent dword.
8738 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8739 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8740 FixFreeIdx) != Inputs.end();
8741 if (IsFixIdxInput == IsFixFreeIdxInput)
8743 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8744 FixFreeIdx) != Inputs.end();
8745 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8746 "We need to be changing the number of flipped inputs!");
8747 int PSHUFHalfMask[] = {0, 1, 2, 3};
8748 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8749 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8751 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8754 if (M != -1 && M == FixIdx)
8756 else if (M != -1 && M == FixFreeIdx)
8759 if (NumFlippedBToBInputs != 0) {
8761 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8762 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8764 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8766 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8767 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8772 int PSHUFDMask[] = {0, 1, 2, 3};
8773 PSHUFDMask[ADWord] = BDWord;
8774 PSHUFDMask[BDWord] = ADWord;
8775 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8776 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8777 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8778 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8780 // Adjust the mask to match the new locations of A and B.
8782 if (M != -1 && M/2 == ADWord)
8783 M = 2 * BDWord + M % 2;
8784 else if (M != -1 && M/2 == BDWord)
8785 M = 2 * ADWord + M % 2;
8787 // Recurse back into this routine to re-compute state now that this isn't
8788 // a 3 and 1 problem.
8789 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8792 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8793 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8794 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8795 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8797 // At this point there are at most two inputs to the low and high halves from
8798 // each half. That means the inputs can always be grouped into dwords and
8799 // those dwords can then be moved to the correct half with a dword shuffle.
8800 // We use at most one low and one high word shuffle to collect these paired
8801 // inputs into dwords, and finally a dword shuffle to place them.
8802 int PSHUFLMask[4] = {-1, -1, -1, -1};
8803 int PSHUFHMask[4] = {-1, -1, -1, -1};
8804 int PSHUFDMask[4] = {-1, -1, -1, -1};
8806 // First fix the masks for all the inputs that are staying in their
8807 // original halves. This will then dictate the targets of the cross-half
8809 auto fixInPlaceInputs =
8810 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8811 MutableArrayRef<int> SourceHalfMask,
8812 MutableArrayRef<int> HalfMask, int HalfOffset) {
8813 if (InPlaceInputs.empty())
8815 if (InPlaceInputs.size() == 1) {
8816 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8817 InPlaceInputs[0] - HalfOffset;
8818 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8821 if (IncomingInputs.empty()) {
8822 // Just fix all of the in place inputs.
8823 for (int Input : InPlaceInputs) {
8824 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8825 PSHUFDMask[Input / 2] = Input / 2;
8830 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8831 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8832 InPlaceInputs[0] - HalfOffset;
8833 // Put the second input next to the first so that they are packed into
8834 // a dword. We find the adjacent index by toggling the low bit.
8835 int AdjIndex = InPlaceInputs[0] ^ 1;
8836 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8837 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8838 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8840 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8841 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8843 // Now gather the cross-half inputs and place them into a free dword of
8844 // their target half.
8845 // FIXME: This operation could almost certainly be simplified dramatically to
8846 // look more like the 3-1 fixing operation.
8847 auto moveInputsToRightHalf = [&PSHUFDMask](
8848 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8849 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8850 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8852 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8853 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8855 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8857 int LowWord = Word & ~1;
8858 int HighWord = Word | 1;
8859 return isWordClobbered(SourceHalfMask, LowWord) ||
8860 isWordClobbered(SourceHalfMask, HighWord);
8863 if (IncomingInputs.empty())
8866 if (ExistingInputs.empty()) {
8867 // Map any dwords with inputs from them into the right half.
8868 for (int Input : IncomingInputs) {
8869 // If the source half mask maps over the inputs, turn those into
8870 // swaps and use the swapped lane.
8871 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8872 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8873 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8874 Input - SourceOffset;
8875 // We have to swap the uses in our half mask in one sweep.
8876 for (int &M : HalfMask)
8877 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8879 else if (M == Input)
8880 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8882 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8883 Input - SourceOffset &&
8884 "Previous placement doesn't match!");
8886 // Note that this correctly re-maps both when we do a swap and when
8887 // we observe the other side of the swap above. We rely on that to
8888 // avoid swapping the members of the input list directly.
8889 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8892 // Map the input's dword into the correct half.
8893 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8894 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8896 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8898 "Previous placement doesn't match!");
8901 // And just directly shift any other-half mask elements to be same-half
8902 // as we will have mirrored the dword containing the element into the
8903 // same position within that half.
8904 for (int &M : HalfMask)
8905 if (M >= SourceOffset && M < SourceOffset + 4) {
8906 M = M - SourceOffset + DestOffset;
8907 assert(M >= 0 && "This should never wrap below zero!");
8912 // Ensure we have the input in a viable dword of its current half. This
8913 // is particularly tricky because the original position may be clobbered
8914 // by inputs being moved and *staying* in that half.
8915 if (IncomingInputs.size() == 1) {
8916 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8917 int InputFixed = std::find(std::begin(SourceHalfMask),
8918 std::end(SourceHalfMask), -1) -
8919 std::begin(SourceHalfMask) + SourceOffset;
8920 SourceHalfMask[InputFixed - SourceOffset] =
8921 IncomingInputs[0] - SourceOffset;
8922 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8924 IncomingInputs[0] = InputFixed;
8926 } else if (IncomingInputs.size() == 2) {
8927 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8928 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8929 // We have two non-adjacent or clobbered inputs we need to extract from
8930 // the source half. To do this, we need to map them into some adjacent
8931 // dword slot in the source mask.
8932 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8933 IncomingInputs[1] - SourceOffset};
8935 // If there is a free slot in the source half mask adjacent to one of
8936 // the inputs, place the other input in it. We use (Index XOR 1) to
8937 // compute an adjacent index.
8938 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8939 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8940 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8941 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8942 InputsFixed[1] = InputsFixed[0] ^ 1;
8943 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8944 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8945 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8946 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8947 InputsFixed[0] = InputsFixed[1] ^ 1;
8948 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8949 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8950 // The two inputs are in the same DWord but it is clobbered and the
8951 // adjacent DWord isn't used at all. Move both inputs to the free
8953 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8954 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8955 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8956 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8958 // The only way we hit this point is if there is no clobbering
8959 // (because there are no off-half inputs to this half) and there is no
8960 // free slot adjacent to one of the inputs. In this case, we have to
8961 // swap an input with a non-input.
8962 for (int i = 0; i < 4; ++i)
8963 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8964 "We can't handle any clobbers here!");
8965 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8966 "Cannot have adjacent inputs here!");
8968 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8969 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8971 // We also have to update the final source mask in this case because
8972 // it may need to undo the above swap.
8973 for (int &M : FinalSourceHalfMask)
8974 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8975 M = InputsFixed[1] + SourceOffset;
8976 else if (M == InputsFixed[1] + SourceOffset)
8977 M = (InputsFixed[0] ^ 1) + SourceOffset;
8979 InputsFixed[1] = InputsFixed[0] ^ 1;
8982 // Point everything at the fixed inputs.
8983 for (int &M : HalfMask)
8984 if (M == IncomingInputs[0])
8985 M = InputsFixed[0] + SourceOffset;
8986 else if (M == IncomingInputs[1])
8987 M = InputsFixed[1] + SourceOffset;
8989 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8990 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8993 llvm_unreachable("Unhandled input size!");
8996 // Now hoist the DWord down to the right half.
8997 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8998 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8999 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9000 for (int &M : HalfMask)
9001 for (int Input : IncomingInputs)
9003 M = FreeDWord * 2 + Input % 2;
9005 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9006 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9007 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9008 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9010 // Now enact all the shuffles we've computed to move the inputs into their
9012 if (!isNoopShuffleMask(PSHUFLMask))
9013 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9014 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9015 if (!isNoopShuffleMask(PSHUFHMask))
9016 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9017 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9018 if (!isNoopShuffleMask(PSHUFDMask))
9019 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9020 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9021 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9022 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9024 // At this point, each half should contain all its inputs, and we can then
9025 // just shuffle them into their final position.
9026 assert(std::count_if(LoMask.begin(), LoMask.end(),
9027 [](int M) { return M >= 4; }) == 0 &&
9028 "Failed to lift all the high half inputs to the low mask!");
9029 assert(std::count_if(HiMask.begin(), HiMask.end(),
9030 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9031 "Failed to lift all the low half inputs to the high mask!");
9033 // Do a half shuffle for the low mask.
9034 if (!isNoopShuffleMask(LoMask))
9035 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9036 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9038 // Do a half shuffle with the high mask after shifting its values down.
9039 for (int &M : HiMask)
9042 if (!isNoopShuffleMask(HiMask))
9043 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9044 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9049 /// \brief Detect whether the mask pattern should be lowered through
9052 /// This essentially tests whether viewing the mask as an interleaving of two
9053 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9054 /// lowering it through interleaving is a significantly better strategy.
9055 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9056 int NumEvenInputs[2] = {0, 0};
9057 int NumOddInputs[2] = {0, 0};
9058 int NumLoInputs[2] = {0, 0};
9059 int NumHiInputs[2] = {0, 0};
9060 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9064 int InputIdx = Mask[i] >= Size;
9067 ++NumLoInputs[InputIdx];
9069 ++NumHiInputs[InputIdx];
9072 ++NumEvenInputs[InputIdx];
9074 ++NumOddInputs[InputIdx];
9077 // The minimum number of cross-input results for both the interleaved and
9078 // split cases. If interleaving results in fewer cross-input results, return
9080 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9081 NumEvenInputs[0] + NumOddInputs[1]);
9082 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9083 NumLoInputs[0] + NumHiInputs[1]);
9084 return InterleavedCrosses < SplitCrosses;
9087 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9089 /// This strategy only works when the inputs from each vector fit into a single
9090 /// half of that vector, and generally there are not so many inputs as to leave
9091 /// the in-place shuffles required highly constrained (and thus expensive). It
9092 /// shifts all the inputs into a single side of both input vectors and then
9093 /// uses an unpack to interleave these inputs in a single vector. At that
9094 /// point, we will fall back on the generic single input shuffle lowering.
9095 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9097 MutableArrayRef<int> Mask,
9098 const X86Subtarget *Subtarget,
9099 SelectionDAG &DAG) {
9100 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9101 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9102 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9103 for (int i = 0; i < 8; ++i)
9104 if (Mask[i] >= 0 && Mask[i] < 4)
9105 LoV1Inputs.push_back(i);
9106 else if (Mask[i] >= 4 && Mask[i] < 8)
9107 HiV1Inputs.push_back(i);
9108 else if (Mask[i] >= 8 && Mask[i] < 12)
9109 LoV2Inputs.push_back(i);
9110 else if (Mask[i] >= 12)
9111 HiV2Inputs.push_back(i);
9113 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9114 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9117 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9118 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9119 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9121 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9122 HiV1Inputs.size() + HiV2Inputs.size();
9124 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9125 ArrayRef<int> HiInputs, bool MoveToLo,
9127 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9128 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9129 if (BadInputs.empty())
9132 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9133 int MoveOffset = MoveToLo ? 0 : 4;
9135 if (GoodInputs.empty()) {
9136 for (int BadInput : BadInputs) {
9137 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9138 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9141 if (GoodInputs.size() == 2) {
9142 // If the low inputs are spread across two dwords, pack them into
9144 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9145 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9146 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9147 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9149 // Otherwise pin the good inputs.
9150 for (int GoodInput : GoodInputs)
9151 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9154 if (BadInputs.size() == 2) {
9155 // If we have two bad inputs then there may be either one or two good
9156 // inputs fixed in place. Find a fixed input, and then find the *other*
9157 // two adjacent indices by using modular arithmetic.
9159 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9160 [](int M) { return M >= 0; }) -
9161 std::begin(MoveMask);
9163 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9164 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9165 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9166 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9167 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9168 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9169 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9171 assert(BadInputs.size() == 1 && "All sizes handled");
9172 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9173 std::end(MoveMask), -1) -
9174 std::begin(MoveMask);
9175 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9176 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9180 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9183 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9185 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9188 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9189 // cross-half traffic in the final shuffle.
9191 // Munge the mask to be a single-input mask after the unpack merges the
9195 M = 2 * (M % 4) + (M / 8);
9197 return DAG.getVectorShuffle(
9198 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9199 DL, MVT::v8i16, V1, V2),
9200 DAG.getUNDEF(MVT::v8i16), Mask);
9203 /// \brief Generic lowering of 8-lane i16 shuffles.
9205 /// This handles both single-input shuffles and combined shuffle/blends with
9206 /// two inputs. The single input shuffles are immediately delegated to
9207 /// a dedicated lowering routine.
9209 /// The blends are lowered in one of three fundamental ways. If there are few
9210 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9211 /// of the input is significantly cheaper when lowered as an interleaving of
9212 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9213 /// halves of the inputs separately (making them have relatively few inputs)
9214 /// and then concatenate them.
9215 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9216 const X86Subtarget *Subtarget,
9217 SelectionDAG &DAG) {
9219 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9220 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9221 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9223 ArrayRef<int> OrigMask = SVOp->getMask();
9224 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9225 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9226 MutableArrayRef<int> Mask(MaskStorage);
9228 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9230 // Whenever we can lower this as a zext, that instruction is strictly faster
9231 // than any alternative.
9232 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9233 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9236 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9237 auto isV2 = [](int M) { return M >= 8; };
9239 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9240 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9242 if (NumV2Inputs == 0)
9243 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9245 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9246 "to be V1-input shuffles.");
9248 // Try to use byte shift instructions.
9249 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9250 DL, MVT::v8i16, V1, V2, Mask, DAG))
9253 // There are special ways we can lower some single-element blends.
9254 if (NumV2Inputs == 1)
9255 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9256 Mask, Subtarget, DAG))
9259 // Use dedicated unpack instructions for masks that match their pattern.
9260 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9261 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9262 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9263 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9265 if (Subtarget->hasSSE41())
9266 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9270 // Try to use byte rotation instructions.
9271 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9272 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9275 if (NumV1Inputs + NumV2Inputs <= 4)
9276 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9278 // Check whether an interleaving lowering is likely to be more efficient.
9279 // This isn't perfect but it is a strong heuristic that tends to work well on
9280 // the kinds of shuffles that show up in practice.
9282 // FIXME: Handle 1x, 2x, and 4x interleaving.
9283 if (shouldLowerAsInterleaving(Mask)) {
9284 // FIXME: Figure out whether we should pack these into the low or high
9287 int EMask[8], OMask[8];
9288 for (int i = 0; i < 4; ++i) {
9289 EMask[i] = Mask[2*i];
9290 OMask[i] = Mask[2*i + 1];
9295 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9296 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9298 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9301 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9302 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9304 for (int i = 0; i < 4; ++i) {
9305 LoBlendMask[i] = Mask[i];
9306 HiBlendMask[i] = Mask[i + 4];
9309 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9310 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9311 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9312 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9314 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9315 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9318 /// \brief Check whether a compaction lowering can be done by dropping even
9319 /// elements and compute how many times even elements must be dropped.
9321 /// This handles shuffles which take every Nth element where N is a power of
9322 /// two. Example shuffle masks:
9324 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9325 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9326 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9327 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9328 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9329 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9331 /// Any of these lanes can of course be undef.
9333 /// This routine only supports N <= 3.
9334 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9337 /// \returns N above, or the number of times even elements must be dropped if
9338 /// there is such a number. Otherwise returns zero.
9339 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9340 // Figure out whether we're looping over two inputs or just one.
9341 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9343 // The modulus for the shuffle vector entries is based on whether this is
9344 // a single input or not.
9345 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9346 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9347 "We should only be called with masks with a power-of-2 size!");
9349 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9351 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9352 // and 2^3 simultaneously. This is because we may have ambiguity with
9353 // partially undef inputs.
9354 bool ViableForN[3] = {true, true, true};
9356 for (int i = 0, e = Mask.size(); i < e; ++i) {
9357 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9362 bool IsAnyViable = false;
9363 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9364 if (ViableForN[j]) {
9367 // The shuffle mask must be equal to (i * 2^N) % M.
9368 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9371 ViableForN[j] = false;
9373 // Early exit if we exhaust the possible powers of two.
9378 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9382 // Return 0 as there is no viable power of two.
9386 /// \brief Generic lowering of v16i8 shuffles.
9388 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9389 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9390 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9391 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9393 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9394 const X86Subtarget *Subtarget,
9395 SelectionDAG &DAG) {
9397 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9398 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9399 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9401 ArrayRef<int> OrigMask = SVOp->getMask();
9402 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9404 // Try to use byte shift instructions.
9405 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9406 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9409 // Try to use byte rotation instructions.
9410 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9411 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9414 // Try to use a zext lowering.
9415 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9416 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9419 int MaskStorage[16] = {
9420 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9421 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9422 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9423 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9424 MutableArrayRef<int> Mask(MaskStorage);
9425 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9426 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9429 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9431 // For single-input shuffles, there are some nicer lowering tricks we can use.
9432 if (NumV2Elements == 0) {
9433 // Check for being able to broadcast a single element.
9434 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9435 Mask, Subtarget, DAG))
9438 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9439 // Notably, this handles splat and partial-splat shuffles more efficiently.
9440 // However, it only makes sense if the pre-duplication shuffle simplifies
9441 // things significantly. Currently, this means we need to be able to
9442 // express the pre-duplication shuffle as an i16 shuffle.
9444 // FIXME: We should check for other patterns which can be widened into an
9445 // i16 shuffle as well.
9446 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9447 for (int i = 0; i < 16; i += 2)
9448 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9453 auto tryToWidenViaDuplication = [&]() -> SDValue {
9454 if (!canWidenViaDuplication(Mask))
9456 SmallVector<int, 4> LoInputs;
9457 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9458 [](int M) { return M >= 0 && M < 8; });
9459 std::sort(LoInputs.begin(), LoInputs.end());
9460 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9462 SmallVector<int, 4> HiInputs;
9463 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9464 [](int M) { return M >= 8; });
9465 std::sort(HiInputs.begin(), HiInputs.end());
9466 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9469 bool TargetLo = LoInputs.size() >= HiInputs.size();
9470 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9471 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9473 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9474 SmallDenseMap<int, int, 8> LaneMap;
9475 for (int I : InPlaceInputs) {
9476 PreDupI16Shuffle[I/2] = I/2;
9479 int j = TargetLo ? 0 : 4, je = j + 4;
9480 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9481 // Check if j is already a shuffle of this input. This happens when
9482 // there are two adjacent bytes after we move the low one.
9483 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9484 // If we haven't yet mapped the input, search for a slot into which
9486 while (j < je && PreDupI16Shuffle[j] != -1)
9490 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9493 // Map this input with the i16 shuffle.
9494 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9497 // Update the lane map based on the mapping we ended up with.
9498 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9501 ISD::BITCAST, DL, MVT::v16i8,
9502 DAG.getVectorShuffle(MVT::v8i16, DL,
9503 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9504 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9506 // Unpack the bytes to form the i16s that will be shuffled into place.
9507 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9508 MVT::v16i8, V1, V1);
9510 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9511 for (int i = 0; i < 16; ++i)
9512 if (Mask[i] != -1) {
9513 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9514 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9515 if (PostDupI16Shuffle[i / 2] == -1)
9516 PostDupI16Shuffle[i / 2] = MappedMask;
9518 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9519 "Conflicting entrties in the original shuffle!");
9522 ISD::BITCAST, DL, MVT::v16i8,
9523 DAG.getVectorShuffle(MVT::v8i16, DL,
9524 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9525 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9527 if (SDValue V = tryToWidenViaDuplication())
9531 // Check whether an interleaving lowering is likely to be more efficient.
9532 // This isn't perfect but it is a strong heuristic that tends to work well on
9533 // the kinds of shuffles that show up in practice.
9535 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9536 if (shouldLowerAsInterleaving(Mask)) {
9537 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9538 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9540 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9541 return (M >= 8 && M < 16) || M >= 24;
9543 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9544 -1, -1, -1, -1, -1, -1, -1, -1};
9545 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9546 -1, -1, -1, -1, -1, -1, -1, -1};
9547 bool UnpackLo = NumLoHalf >= NumHiHalf;
9548 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9549 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9550 for (int i = 0; i < 8; ++i) {
9551 TargetEMask[i] = Mask[2 * i];
9552 TargetOMask[i] = Mask[2 * i + 1];
9555 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9556 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9558 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9559 MVT::v16i8, Evens, Odds);
9562 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9563 // with PSHUFB. It is important to do this before we attempt to generate any
9564 // blends but after all of the single-input lowerings. If the single input
9565 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9566 // want to preserve that and we can DAG combine any longer sequences into
9567 // a PSHUFB in the end. But once we start blending from multiple inputs,
9568 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9569 // and there are *very* few patterns that would actually be faster than the
9570 // PSHUFB approach because of its ability to zero lanes.
9572 // FIXME: The only exceptions to the above are blends which are exact
9573 // interleavings with direct instructions supporting them. We currently don't
9574 // handle those well here.
9575 if (Subtarget->hasSSSE3()) {
9578 for (int i = 0; i < 16; ++i)
9579 if (Mask[i] == -1) {
9580 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9582 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9584 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9586 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9587 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9588 if (isSingleInputShuffleMask(Mask))
9589 return V1; // Single inputs are easy.
9591 // Otherwise, blend the two.
9592 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9593 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9594 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9597 // There are special ways we can lower some single-element blends.
9598 if (NumV2Elements == 1)
9599 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9600 Mask, Subtarget, DAG))
9603 // Check whether a compaction lowering can be done. This handles shuffles
9604 // which take every Nth element for some even N. See the helper function for
9607 // We special case these as they can be particularly efficiently handled with
9608 // the PACKUSB instruction on x86 and they show up in common patterns of
9609 // rearranging bytes to truncate wide elements.
9610 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9611 // NumEvenDrops is the power of two stride of the elements. Another way of
9612 // thinking about it is that we need to drop the even elements this many
9613 // times to get the original input.
9614 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9616 // First we need to zero all the dropped bytes.
9617 assert(NumEvenDrops <= 3 &&
9618 "No support for dropping even elements more than 3 times.");
9619 // We use the mask type to pick which bytes are preserved based on how many
9620 // elements are dropped.
9621 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9622 SDValue ByteClearMask =
9623 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9624 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9625 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9627 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9629 // Now pack things back together.
9630 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9631 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9632 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9633 for (int i = 1; i < NumEvenDrops; ++i) {
9634 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9635 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9641 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9642 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9643 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9644 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9646 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9647 MutableArrayRef<int> V1HalfBlendMask,
9648 MutableArrayRef<int> V2HalfBlendMask) {
9649 for (int i = 0; i < 8; ++i)
9650 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9651 V1HalfBlendMask[i] = HalfMask[i];
9653 } else if (HalfMask[i] >= 16) {
9654 V2HalfBlendMask[i] = HalfMask[i] - 16;
9655 HalfMask[i] = i + 8;
9658 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9659 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9661 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9663 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9664 MutableArrayRef<int> HiBlendMask) {
9666 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9667 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9669 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9670 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9671 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9672 [](int M) { return M >= 0 && M % 2 == 1; })) {
9673 // Use a mask to drop the high bytes.
9674 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9675 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9676 DAG.getConstant(0x00FF, MVT::v8i16));
9678 // This will be a single vector shuffle instead of a blend so nuke V2.
9679 V2 = DAG.getUNDEF(MVT::v8i16);
9681 // Squash the masks to point directly into V1.
9682 for (int &M : LoBlendMask)
9685 for (int &M : HiBlendMask)
9689 // Otherwise just unpack the low half of V into V1 and the high half into
9690 // V2 so that we can blend them as i16s.
9691 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9692 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9693 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9694 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9697 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9698 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9699 return std::make_pair(BlendedLo, BlendedHi);
9701 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9702 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9703 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9705 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9706 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9708 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9711 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9713 /// This routine breaks down the specific type of 128-bit shuffle and
9714 /// dispatches to the lowering routines accordingly.
9715 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9716 MVT VT, const X86Subtarget *Subtarget,
9717 SelectionDAG &DAG) {
9718 switch (VT.SimpleTy) {
9720 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9722 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9724 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9726 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9728 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9730 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9733 llvm_unreachable("Unimplemented!");
9737 /// \brief Helper function to test whether a shuffle mask could be
9738 /// simplified by widening the elements being shuffled.
9740 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9741 /// leaves it in an unspecified state.
9743 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9744 /// shuffle masks. The latter have the special property of a '-2' representing
9745 /// a zero-ed lane of a vector.
9746 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9747 SmallVectorImpl<int> &WidenedMask) {
9748 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9749 // If both elements are undef, its trivial.
9750 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9751 WidenedMask.push_back(SM_SentinelUndef);
9755 // Check for an undef mask and a mask value properly aligned to fit with
9756 // a pair of values. If we find such a case, use the non-undef mask's value.
9757 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9758 WidenedMask.push_back(Mask[i + 1] / 2);
9761 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9762 WidenedMask.push_back(Mask[i] / 2);
9766 // When zeroing, we need to spread the zeroing across both lanes to widen.
9767 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9768 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9769 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9770 WidenedMask.push_back(SM_SentinelZero);
9776 // Finally check if the two mask values are adjacent and aligned with
9778 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9779 WidenedMask.push_back(Mask[i] / 2);
9783 // Otherwise we can't safely widen the elements used in this shuffle.
9786 assert(WidenedMask.size() == Mask.size() / 2 &&
9787 "Incorrect size of mask after widening the elements!");
9792 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9794 /// This routine just extracts two subvectors, shuffles them independently, and
9795 /// then concatenates them back together. This should work effectively with all
9796 /// AVX vector shuffle types.
9797 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9798 SDValue V2, ArrayRef<int> Mask,
9799 SelectionDAG &DAG) {
9800 assert(VT.getSizeInBits() >= 256 &&
9801 "Only for 256-bit or wider vector shuffles!");
9802 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9803 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9805 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9806 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9808 int NumElements = VT.getVectorNumElements();
9809 int SplitNumElements = NumElements / 2;
9810 MVT ScalarVT = VT.getScalarType();
9811 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9813 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9814 DAG.getIntPtrConstant(0));
9815 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9816 DAG.getIntPtrConstant(SplitNumElements));
9817 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9818 DAG.getIntPtrConstant(0));
9819 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9820 DAG.getIntPtrConstant(SplitNumElements));
9822 // Now create two 4-way blends of these half-width vectors.
9823 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9824 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9825 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9826 for (int i = 0; i < SplitNumElements; ++i) {
9827 int M = HalfMask[i];
9828 if (M >= NumElements) {
9829 if (M >= NumElements + SplitNumElements)
9833 V2BlendMask.push_back(M - NumElements);
9834 V1BlendMask.push_back(-1);
9835 BlendMask.push_back(SplitNumElements + i);
9836 } else if (M >= 0) {
9837 if (M >= SplitNumElements)
9841 V2BlendMask.push_back(-1);
9842 V1BlendMask.push_back(M);
9843 BlendMask.push_back(i);
9845 V2BlendMask.push_back(-1);
9846 V1BlendMask.push_back(-1);
9847 BlendMask.push_back(-1);
9851 // Because the lowering happens after all combining takes place, we need to
9852 // manually combine these blend masks as much as possible so that we create
9853 // a minimal number of high-level vector shuffle nodes.
9855 // First try just blending the halves of V1 or V2.
9856 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9857 return DAG.getUNDEF(SplitVT);
9858 if (!UseLoV2 && !UseHiV2)
9859 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9860 if (!UseLoV1 && !UseHiV1)
9861 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9863 SDValue V1Blend, V2Blend;
9864 if (UseLoV1 && UseHiV1) {
9866 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9868 // We only use half of V1 so map the usage down into the final blend mask.
9869 V1Blend = UseLoV1 ? LoV1 : HiV1;
9870 for (int i = 0; i < SplitNumElements; ++i)
9871 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9872 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9874 if (UseLoV2 && UseHiV2) {
9876 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9878 // We only use half of V2 so map the usage down into the final blend mask.
9879 V2Blend = UseLoV2 ? LoV2 : HiV2;
9880 for (int i = 0; i < SplitNumElements; ++i)
9881 if (BlendMask[i] >= SplitNumElements)
9882 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9884 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9886 SDValue Lo = HalfBlend(LoMask);
9887 SDValue Hi = HalfBlend(HiMask);
9888 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9891 /// \brief Either split a vector in halves or decompose the shuffles and the
9894 /// This is provided as a good fallback for many lowerings of non-single-input
9895 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9896 /// between splitting the shuffle into 128-bit components and stitching those
9897 /// back together vs. extracting the single-input shuffles and blending those
9899 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9900 SDValue V2, ArrayRef<int> Mask,
9901 SelectionDAG &DAG) {
9902 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9903 "lower single-input shuffles as it "
9904 "could then recurse on itself.");
9905 int Size = Mask.size();
9907 // If this can be modeled as a broadcast of two elements followed by a blend,
9908 // prefer that lowering. This is especially important because broadcasts can
9909 // often fold with memory operands.
9910 auto DoBothBroadcast = [&] {
9911 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9914 if (V2BroadcastIdx == -1)
9915 V2BroadcastIdx = M - Size;
9916 else if (M - Size != V2BroadcastIdx)
9918 } else if (M >= 0) {
9919 if (V1BroadcastIdx == -1)
9921 else if (M != V1BroadcastIdx)
9926 if (DoBothBroadcast())
9927 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9930 // If the inputs all stem from a single 128-bit lane of each input, then we
9931 // split them rather than blending because the split will decompose to
9932 // unusually few instructions.
9933 int LaneCount = VT.getSizeInBits() / 128;
9934 int LaneSize = Size / LaneCount;
9935 SmallBitVector LaneInputs[2];
9936 LaneInputs[0].resize(LaneCount, false);
9937 LaneInputs[1].resize(LaneCount, false);
9938 for (int i = 0; i < Size; ++i)
9940 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9941 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9942 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9944 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9945 // that the decomposed single-input shuffles don't end up here.
9946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9949 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9950 /// a permutation and blend of those lanes.
9952 /// This essentially blends the out-of-lane inputs to each lane into the lane
9953 /// from a permuted copy of the vector. This lowering strategy results in four
9954 /// instructions in the worst case for a single-input cross lane shuffle which
9955 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9956 /// of. Special cases for each particular shuffle pattern should be handled
9957 /// prior to trying this lowering.
9958 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9959 SDValue V1, SDValue V2,
9961 SelectionDAG &DAG) {
9962 // FIXME: This should probably be generalized for 512-bit vectors as well.
9963 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9964 int LaneSize = Mask.size() / 2;
9966 // If there are only inputs from one 128-bit lane, splitting will in fact be
9967 // less expensive. The flags track wether the given lane contains an element
9968 // that crosses to another lane.
9969 bool LaneCrossing[2] = {false, false};
9970 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9971 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9972 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9973 if (!LaneCrossing[0] || !LaneCrossing[1])
9974 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9976 if (isSingleInputShuffleMask(Mask)) {
9977 SmallVector<int, 32> FlippedBlendMask;
9978 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9979 FlippedBlendMask.push_back(
9980 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9982 : Mask[i] % LaneSize +
9983 (i / LaneSize) * LaneSize + Size));
9985 // Flip the vector, and blend the results which should now be in-lane. The
9986 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9987 // 5 for the high source. The value 3 selects the high half of source 2 and
9988 // the value 2 selects the low half of source 2. We only use source 2 to
9989 // allow folding it into a memory operand.
9990 unsigned PERMMask = 3 | 2 << 4;
9991 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9992 V1, DAG.getConstant(PERMMask, MVT::i8));
9993 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9996 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9997 // will be handled by the above logic and a blend of the results, much like
9998 // other patterns in AVX.
9999 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10002 /// \brief Handle lowering 2-lane 128-bit shuffles.
10003 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10004 SDValue V2, ArrayRef<int> Mask,
10005 const X86Subtarget *Subtarget,
10006 SelectionDAG &DAG) {
10007 // Blends are faster and handle all the non-lane-crossing cases.
10008 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10012 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10013 VT.getVectorNumElements() / 2);
10014 // Check for patterns which can be matched with a single insert of a 128-bit
10016 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10017 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10018 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10019 DAG.getIntPtrConstant(0));
10020 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10021 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10022 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10024 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10025 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10026 DAG.getIntPtrConstant(0));
10027 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10028 DAG.getIntPtrConstant(2));
10029 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10032 // Otherwise form a 128-bit permutation.
10033 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10034 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10035 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10036 DAG.getConstant(PermMask, MVT::i8));
10039 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10040 /// shuffling each lane.
10042 /// This will only succeed when the result of fixing the 128-bit lanes results
10043 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10044 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10045 /// the lane crosses early and then use simpler shuffles within each lane.
10047 /// FIXME: It might be worthwhile at some point to support this without
10048 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10049 /// in x86 only floating point has interesting non-repeating shuffles, and even
10050 /// those are still *marginally* more expensive.
10051 static SDValue lowerVectorShuffleByMerging128BitLanes(
10052 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10053 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10054 assert(!isSingleInputShuffleMask(Mask) &&
10055 "This is only useful with multiple inputs.");
10057 int Size = Mask.size();
10058 int LaneSize = 128 / VT.getScalarSizeInBits();
10059 int NumLanes = Size / LaneSize;
10060 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10062 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10063 // check whether the in-128-bit lane shuffles share a repeating pattern.
10064 SmallVector<int, 4> Lanes;
10065 Lanes.resize(NumLanes, -1);
10066 SmallVector<int, 4> InLaneMask;
10067 InLaneMask.resize(LaneSize, -1);
10068 for (int i = 0; i < Size; ++i) {
10072 int j = i / LaneSize;
10074 if (Lanes[j] < 0) {
10075 // First entry we've seen for this lane.
10076 Lanes[j] = Mask[i] / LaneSize;
10077 } else if (Lanes[j] != Mask[i] / LaneSize) {
10078 // This doesn't match the lane selected previously!
10082 // Check that within each lane we have a consistent shuffle mask.
10083 int k = i % LaneSize;
10084 if (InLaneMask[k] < 0) {
10085 InLaneMask[k] = Mask[i] % LaneSize;
10086 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10087 // This doesn't fit a repeating in-lane mask.
10092 // First shuffle the lanes into place.
10093 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10094 VT.getSizeInBits() / 64);
10095 SmallVector<int, 8> LaneMask;
10096 LaneMask.resize(NumLanes * 2, -1);
10097 for (int i = 0; i < NumLanes; ++i)
10098 if (Lanes[i] >= 0) {
10099 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10100 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10103 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10104 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10105 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10107 // Cast it back to the type we actually want.
10108 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10110 // Now do a simple shuffle that isn't lane crossing.
10111 SmallVector<int, 8> NewMask;
10112 NewMask.resize(Size, -1);
10113 for (int i = 0; i < Size; ++i)
10115 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10116 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10117 "Must not introduce lane crosses at this point!");
10119 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10122 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10125 /// This returns true if the elements from a particular input are already in the
10126 /// slot required by the given mask and require no permutation.
10127 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10128 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10129 int Size = Mask.size();
10130 for (int i = 0; i < Size; ++i)
10131 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10137 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10139 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10140 /// isn't available.
10141 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10142 const X86Subtarget *Subtarget,
10143 SelectionDAG &DAG) {
10145 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10146 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10147 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10148 ArrayRef<int> Mask = SVOp->getMask();
10149 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10151 SmallVector<int, 4> WidenedMask;
10152 if (canWidenShuffleElements(Mask, WidenedMask))
10153 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10156 if (isSingleInputShuffleMask(Mask)) {
10157 // Check for being able to broadcast a single element.
10158 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10159 Mask, Subtarget, DAG))
10162 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10163 // Non-half-crossing single input shuffles can be lowerid with an
10164 // interleaved permutation.
10165 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10166 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10167 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10168 DAG.getConstant(VPERMILPMask, MVT::i8));
10171 // With AVX2 we have direct support for this permutation.
10172 if (Subtarget->hasAVX2())
10173 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10174 getV4X86ShuffleImm8ForMask(Mask, DAG));
10176 // Otherwise, fall back.
10177 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10181 // X86 has dedicated unpack instructions that can handle specific blend
10182 // operations: UNPCKH and UNPCKL.
10183 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10184 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10185 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10186 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10188 // If we have a single input to the zero element, insert that into V1 if we
10189 // can do so cheaply.
10190 int NumV2Elements =
10191 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10192 if (NumV2Elements == 1 && Mask[0] >= 4)
10193 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10194 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10197 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10201 // Check if the blend happens to exactly fit that of SHUFPD.
10202 if ((Mask[0] == -1 || Mask[0] < 2) &&
10203 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10204 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10205 (Mask[3] == -1 || Mask[3] >= 6)) {
10206 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10207 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10208 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10209 DAG.getConstant(SHUFPDMask, MVT::i8));
10211 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10212 (Mask[1] == -1 || Mask[1] < 2) &&
10213 (Mask[2] == -1 || Mask[2] >= 6) &&
10214 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10215 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10216 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10217 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10218 DAG.getConstant(SHUFPDMask, MVT::i8));
10221 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10222 // shuffle. However, if we have AVX2 and either inputs are already in place,
10223 // we will be able to shuffle even across lanes the other input in a single
10224 // instruction so skip this pattern.
10225 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10226 isShuffleMaskInputInPlace(1, Mask))))
10227 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10228 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10231 // If we have AVX2 then we always want to lower with a blend because an v4 we
10232 // can fully permute the elements.
10233 if (Subtarget->hasAVX2())
10234 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10237 // Otherwise fall back on generic lowering.
10238 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10241 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10243 /// This routine is only called when we have AVX2 and thus a reasonable
10244 /// instruction set for v4i64 shuffling..
10245 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10246 const X86Subtarget *Subtarget,
10247 SelectionDAG &DAG) {
10249 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10250 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10251 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10252 ArrayRef<int> Mask = SVOp->getMask();
10253 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10254 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10256 SmallVector<int, 4> WidenedMask;
10257 if (canWidenShuffleElements(Mask, WidenedMask))
10258 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10261 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10265 // Check for being able to broadcast a single element.
10266 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10267 Mask, Subtarget, DAG))
10270 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10271 // use lower latency instructions that will operate on both 128-bit lanes.
10272 SmallVector<int, 2> RepeatedMask;
10273 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10274 if (isSingleInputShuffleMask(Mask)) {
10275 int PSHUFDMask[] = {-1, -1, -1, -1};
10276 for (int i = 0; i < 2; ++i)
10277 if (RepeatedMask[i] >= 0) {
10278 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10279 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10281 return DAG.getNode(
10282 ISD::BITCAST, DL, MVT::v4i64,
10283 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10284 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10285 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10288 // Use dedicated unpack instructions for masks that match their pattern.
10289 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10290 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10291 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10292 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10295 // AVX2 provides a direct instruction for permuting a single input across
10297 if (isSingleInputShuffleMask(Mask))
10298 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10299 getV4X86ShuffleImm8ForMask(Mask, DAG));
10301 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10302 // shuffle. However, if we have AVX2 and either inputs are already in place,
10303 // we will be able to shuffle even across lanes the other input in a single
10304 // instruction so skip this pattern.
10305 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10306 isShuffleMaskInputInPlace(1, Mask))))
10307 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10308 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10311 // Otherwise fall back on generic blend lowering.
10312 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10316 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10318 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10319 /// isn't available.
10320 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10321 const X86Subtarget *Subtarget,
10322 SelectionDAG &DAG) {
10324 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10325 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10327 ArrayRef<int> Mask = SVOp->getMask();
10328 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10330 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10334 // Check for being able to broadcast a single element.
10335 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10336 Mask, Subtarget, DAG))
10339 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10340 // options to efficiently lower the shuffle.
10341 SmallVector<int, 4> RepeatedMask;
10342 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10343 assert(RepeatedMask.size() == 4 &&
10344 "Repeated masks must be half the mask width!");
10345 if (isSingleInputShuffleMask(Mask))
10346 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10347 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10349 // Use dedicated unpack instructions for masks that match their pattern.
10350 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10351 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10352 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10353 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10355 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10356 // have already handled any direct blends. We also need to squash the
10357 // repeated mask into a simulated v4f32 mask.
10358 for (int i = 0; i < 4; ++i)
10359 if (RepeatedMask[i] >= 8)
10360 RepeatedMask[i] -= 4;
10361 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10364 // If we have a single input shuffle with different shuffle patterns in the
10365 // two 128-bit lanes use the variable mask to VPERMILPS.
10366 if (isSingleInputShuffleMask(Mask)) {
10367 SDValue VPermMask[8];
10368 for (int i = 0; i < 8; ++i)
10369 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10370 : DAG.getConstant(Mask[i], MVT::i32);
10371 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10372 return DAG.getNode(
10373 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10374 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10376 if (Subtarget->hasAVX2())
10377 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10378 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10379 DAG.getNode(ISD::BUILD_VECTOR, DL,
10380 MVT::v8i32, VPermMask)),
10383 // Otherwise, fall back.
10384 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10388 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10390 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10391 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10394 // If we have AVX2 then we always want to lower with a blend because at v8 we
10395 // can fully permute the elements.
10396 if (Subtarget->hasAVX2())
10397 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10400 // Otherwise fall back on generic lowering.
10401 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10404 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10406 /// This routine is only called when we have AVX2 and thus a reasonable
10407 /// instruction set for v8i32 shuffling..
10408 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10409 const X86Subtarget *Subtarget,
10410 SelectionDAG &DAG) {
10412 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10413 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10415 ArrayRef<int> Mask = SVOp->getMask();
10416 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10417 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10419 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10423 // Check for being able to broadcast a single element.
10424 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10425 Mask, Subtarget, DAG))
10428 // If the shuffle mask is repeated in each 128-bit lane we can use more
10429 // efficient instructions that mirror the shuffles across the two 128-bit
10431 SmallVector<int, 4> RepeatedMask;
10432 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10433 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10434 if (isSingleInputShuffleMask(Mask))
10435 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10436 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10438 // Use dedicated unpack instructions for masks that match their pattern.
10439 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10440 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10441 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10442 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10445 // If the shuffle patterns aren't repeated but it is a single input, directly
10446 // generate a cross-lane VPERMD instruction.
10447 if (isSingleInputShuffleMask(Mask)) {
10448 SDValue VPermMask[8];
10449 for (int i = 0; i < 8; ++i)
10450 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10451 : DAG.getConstant(Mask[i], MVT::i32);
10452 return DAG.getNode(
10453 X86ISD::VPERMV, DL, MVT::v8i32,
10454 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10457 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10459 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10460 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10463 // Otherwise fall back on generic blend lowering.
10464 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10468 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10470 /// This routine is only called when we have AVX2 and thus a reasonable
10471 /// instruction set for v16i16 shuffling..
10472 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10473 const X86Subtarget *Subtarget,
10474 SelectionDAG &DAG) {
10476 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10477 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10479 ArrayRef<int> Mask = SVOp->getMask();
10480 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10481 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10483 // Check for being able to broadcast a single element.
10484 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10485 Mask, Subtarget, DAG))
10488 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10492 // Use dedicated unpack instructions for masks that match their pattern.
10493 if (isShuffleEquivalent(Mask,
10494 // First 128-bit lane:
10495 0, 16, 1, 17, 2, 18, 3, 19,
10496 // Second 128-bit lane:
10497 8, 24, 9, 25, 10, 26, 11, 27))
10498 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10499 if (isShuffleEquivalent(Mask,
10500 // First 128-bit lane:
10501 4, 20, 5, 21, 6, 22, 7, 23,
10502 // Second 128-bit lane:
10503 12, 28, 13, 29, 14, 30, 15, 31))
10504 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10506 if (isSingleInputShuffleMask(Mask)) {
10507 // There are no generalized cross-lane shuffle operations available on i16
10509 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10510 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10513 SDValue PSHUFBMask[32];
10514 for (int i = 0; i < 16; ++i) {
10515 if (Mask[i] == -1) {
10516 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10520 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10521 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10522 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10523 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10525 return DAG.getNode(
10526 ISD::BITCAST, DL, MVT::v16i16,
10528 X86ISD::PSHUFB, DL, MVT::v32i8,
10529 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10530 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10533 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10535 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10536 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10539 // Otherwise fall back on generic lowering.
10540 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10543 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10545 /// This routine is only called when we have AVX2 and thus a reasonable
10546 /// instruction set for v32i8 shuffling..
10547 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10548 const X86Subtarget *Subtarget,
10549 SelectionDAG &DAG) {
10551 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10552 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10554 ArrayRef<int> Mask = SVOp->getMask();
10555 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10556 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10558 // Check for being able to broadcast a single element.
10559 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10560 Mask, Subtarget, DAG))
10563 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10567 // Use dedicated unpack instructions for masks that match their pattern.
10568 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10570 if (isShuffleEquivalent(
10572 // First 128-bit lane:
10573 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10574 // Second 128-bit lane:
10575 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10576 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10577 if (isShuffleEquivalent(
10579 // First 128-bit lane:
10580 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10581 // Second 128-bit lane:
10582 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10583 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10585 if (isSingleInputShuffleMask(Mask)) {
10586 // There are no generalized cross-lane shuffle operations available on i8
10588 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10589 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10592 SDValue PSHUFBMask[32];
10593 for (int i = 0; i < 32; ++i)
10596 ? DAG.getUNDEF(MVT::i8)
10597 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10599 return DAG.getNode(
10600 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10601 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10604 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10606 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10607 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10610 // Otherwise fall back on generic lowering.
10611 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10614 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10616 /// This routine either breaks down the specific type of a 256-bit x86 vector
10617 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10618 /// together based on the available instructions.
10619 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10620 MVT VT, const X86Subtarget *Subtarget,
10621 SelectionDAG &DAG) {
10623 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10624 ArrayRef<int> Mask = SVOp->getMask();
10626 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10627 // check for those subtargets here and avoid much of the subtarget querying in
10628 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10629 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10630 // floating point types there eventually, just immediately cast everything to
10631 // a float and operate entirely in that domain.
10632 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10633 int ElementBits = VT.getScalarSizeInBits();
10634 if (ElementBits < 32)
10635 // No floating point type available, decompose into 128-bit vectors.
10636 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10638 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10639 VT.getVectorNumElements());
10640 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10641 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10642 return DAG.getNode(ISD::BITCAST, DL, VT,
10643 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10646 switch (VT.SimpleTy) {
10648 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10650 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10652 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10654 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10656 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10658 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10661 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10665 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10666 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10667 const X86Subtarget *Subtarget,
10668 SelectionDAG &DAG) {
10670 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10671 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10673 ArrayRef<int> Mask = SVOp->getMask();
10674 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10676 // FIXME: Implement direct support for this type!
10677 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10680 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10681 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10682 const X86Subtarget *Subtarget,
10683 SelectionDAG &DAG) {
10685 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10686 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10688 ArrayRef<int> Mask = SVOp->getMask();
10689 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10691 // FIXME: Implement direct support for this type!
10692 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10695 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10696 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10697 const X86Subtarget *Subtarget,
10698 SelectionDAG &DAG) {
10700 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10701 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10703 ArrayRef<int> Mask = SVOp->getMask();
10704 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10706 // FIXME: Implement direct support for this type!
10707 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10710 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10711 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10712 const X86Subtarget *Subtarget,
10713 SelectionDAG &DAG) {
10715 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10716 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10718 ArrayRef<int> Mask = SVOp->getMask();
10719 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10721 // FIXME: Implement direct support for this type!
10722 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10725 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10726 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10727 const X86Subtarget *Subtarget,
10728 SelectionDAG &DAG) {
10730 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10731 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10732 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10733 ArrayRef<int> Mask = SVOp->getMask();
10734 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10735 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10737 // FIXME: Implement direct support for this type!
10738 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10741 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10742 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10743 const X86Subtarget *Subtarget,
10744 SelectionDAG &DAG) {
10746 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10747 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10748 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10749 ArrayRef<int> Mask = SVOp->getMask();
10750 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10751 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10753 // FIXME: Implement direct support for this type!
10754 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10757 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10759 /// This routine either breaks down the specific type of a 512-bit x86 vector
10760 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10761 /// together based on the available instructions.
10762 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10763 MVT VT, const X86Subtarget *Subtarget,
10764 SelectionDAG &DAG) {
10766 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10767 ArrayRef<int> Mask = SVOp->getMask();
10768 assert(Subtarget->hasAVX512() &&
10769 "Cannot lower 512-bit vectors w/ basic ISA!");
10771 // Check for being able to broadcast a single element.
10772 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10773 Mask, Subtarget, DAG))
10776 // Dispatch to each element type for lowering. If we don't have supprot for
10777 // specific element type shuffles at 512 bits, immediately split them and
10778 // lower them. Each lowering routine of a given type is allowed to assume that
10779 // the requisite ISA extensions for that element type are available.
10780 switch (VT.SimpleTy) {
10782 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10784 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10786 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10788 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10790 if (Subtarget->hasBWI())
10791 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10794 if (Subtarget->hasBWI())
10795 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10799 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10802 // Otherwise fall back on splitting.
10803 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10806 /// \brief Top-level lowering for x86 vector shuffles.
10808 /// This handles decomposition, canonicalization, and lowering of all x86
10809 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10810 /// above in helper routines. The canonicalization attempts to widen shuffles
10811 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10812 /// s.t. only one of the two inputs needs to be tested, etc.
10813 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10814 SelectionDAG &DAG) {
10815 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10816 ArrayRef<int> Mask = SVOp->getMask();
10817 SDValue V1 = Op.getOperand(0);
10818 SDValue V2 = Op.getOperand(1);
10819 MVT VT = Op.getSimpleValueType();
10820 int NumElements = VT.getVectorNumElements();
10823 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10825 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10826 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10827 if (V1IsUndef && V2IsUndef)
10828 return DAG.getUNDEF(VT);
10830 // When we create a shuffle node we put the UNDEF node to second operand,
10831 // but in some cases the first operand may be transformed to UNDEF.
10832 // In this case we should just commute the node.
10834 return DAG.getCommutedVectorShuffle(*SVOp);
10836 // Check for non-undef masks pointing at an undef vector and make the masks
10837 // undef as well. This makes it easier to match the shuffle based solely on
10841 if (M >= NumElements) {
10842 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10843 for (int &M : NewMask)
10844 if (M >= NumElements)
10846 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10849 // Try to collapse shuffles into using a vector type with fewer elements but
10850 // wider element types. We cap this to not form integers or floating point
10851 // elements wider than 64 bits, but it might be interesting to form i128
10852 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10853 SmallVector<int, 16> WidenedMask;
10854 if (VT.getScalarSizeInBits() < 64 &&
10855 canWidenShuffleElements(Mask, WidenedMask)) {
10856 MVT NewEltVT = VT.isFloatingPoint()
10857 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10858 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10859 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10860 // Make sure that the new vector type is legal. For example, v2f64 isn't
10862 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10863 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10864 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10865 return DAG.getNode(ISD::BITCAST, dl, VT,
10866 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10870 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10871 for (int M : SVOp->getMask())
10873 ++NumUndefElements;
10874 else if (M < NumElements)
10879 // Commute the shuffle as needed such that more elements come from V1 than
10880 // V2. This allows us to match the shuffle pattern strictly on how many
10881 // elements come from V1 without handling the symmetric cases.
10882 if (NumV2Elements > NumV1Elements)
10883 return DAG.getCommutedVectorShuffle(*SVOp);
10885 // When the number of V1 and V2 elements are the same, try to minimize the
10886 // number of uses of V2 in the low half of the vector. When that is tied,
10887 // ensure that the sum of indices for V1 is equal to or lower than the sum
10888 // indices for V2. When those are equal, try to ensure that the number of odd
10889 // indices for V1 is lower than the number of odd indices for V2.
10890 if (NumV1Elements == NumV2Elements) {
10891 int LowV1Elements = 0, LowV2Elements = 0;
10892 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10893 if (M >= NumElements)
10897 if (LowV2Elements > LowV1Elements) {
10898 return DAG.getCommutedVectorShuffle(*SVOp);
10899 } else if (LowV2Elements == LowV1Elements) {
10900 int SumV1Indices = 0, SumV2Indices = 0;
10901 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10902 if (SVOp->getMask()[i] >= NumElements)
10904 else if (SVOp->getMask()[i] >= 0)
10906 if (SumV2Indices < SumV1Indices) {
10907 return DAG.getCommutedVectorShuffle(*SVOp);
10908 } else if (SumV2Indices == SumV1Indices) {
10909 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10910 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10911 if (SVOp->getMask()[i] >= NumElements)
10912 NumV2OddIndices += i % 2;
10913 else if (SVOp->getMask()[i] >= 0)
10914 NumV1OddIndices += i % 2;
10915 if (NumV2OddIndices < NumV1OddIndices)
10916 return DAG.getCommutedVectorShuffle(*SVOp);
10921 // For each vector width, delegate to a specialized lowering routine.
10922 if (VT.getSizeInBits() == 128)
10923 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10925 if (VT.getSizeInBits() == 256)
10926 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10928 // Force AVX-512 vectors to be scalarized for now.
10929 // FIXME: Implement AVX-512 support!
10930 if (VT.getSizeInBits() == 512)
10931 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10933 llvm_unreachable("Unimplemented!");
10937 //===----------------------------------------------------------------------===//
10938 // Legacy vector shuffle lowering
10940 // This code is the legacy code handling vector shuffles until the above
10941 // replaces its functionality and performance.
10942 //===----------------------------------------------------------------------===//
10944 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10945 bool hasInt256, unsigned *MaskOut = nullptr) {
10946 MVT EltVT = VT.getVectorElementType();
10948 // There is no blend with immediate in AVX-512.
10949 if (VT.is512BitVector())
10952 if (!hasSSE41 || EltVT == MVT::i8)
10954 if (!hasInt256 && VT == MVT::v16i16)
10957 unsigned MaskValue = 0;
10958 unsigned NumElems = VT.getVectorNumElements();
10959 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10960 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10961 unsigned NumElemsInLane = NumElems / NumLanes;
10963 // Blend for v16i16 should be symetric for the both lanes.
10964 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10966 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10967 int EltIdx = MaskVals[i];
10969 if ((EltIdx < 0 || EltIdx == (int)i) &&
10970 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10973 if (((unsigned)EltIdx == (i + NumElems)) &&
10974 (SndLaneEltIdx < 0 ||
10975 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10976 MaskValue |= (1 << i);
10982 *MaskOut = MaskValue;
10986 // Try to lower a shuffle node into a simple blend instruction.
10987 // This function assumes isBlendMask returns true for this
10988 // SuffleVectorSDNode
10989 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10990 unsigned MaskValue,
10991 const X86Subtarget *Subtarget,
10992 SelectionDAG &DAG) {
10993 MVT VT = SVOp->getSimpleValueType(0);
10994 MVT EltVT = VT.getVectorElementType();
10995 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10996 Subtarget->hasInt256() && "Trying to lower a "
10997 "VECTOR_SHUFFLE to a Blend but "
10998 "with the wrong mask"));
10999 SDValue V1 = SVOp->getOperand(0);
11000 SDValue V2 = SVOp->getOperand(1);
11002 unsigned NumElems = VT.getVectorNumElements();
11004 // Convert i32 vectors to floating point if it is not AVX2.
11005 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11007 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11008 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11010 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11011 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11014 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11015 DAG.getConstant(MaskValue, MVT::i32));
11016 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11019 /// In vector type \p VT, return true if the element at index \p InputIdx
11020 /// falls on a different 128-bit lane than \p OutputIdx.
11021 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11022 unsigned OutputIdx) {
11023 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11024 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11027 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11028 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11029 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11030 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11032 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11033 SelectionDAG &DAG) {
11034 MVT VT = V1.getSimpleValueType();
11035 assert(VT.is128BitVector() || VT.is256BitVector());
11037 MVT EltVT = VT.getVectorElementType();
11038 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11039 unsigned NumElts = VT.getVectorNumElements();
11041 SmallVector<SDValue, 32> PshufbMask;
11042 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11043 int InputIdx = MaskVals[OutputIdx];
11044 unsigned InputByteIdx;
11046 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11047 InputByteIdx = 0x80;
11049 // Cross lane is not allowed.
11050 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11052 InputByteIdx = InputIdx * EltSizeInBytes;
11053 // Index is an byte offset within the 128-bit lane.
11054 InputByteIdx &= 0xf;
11057 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11058 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11059 if (InputByteIdx != 0x80)
11064 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11066 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11067 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11068 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11071 // v8i16 shuffles - Prefer shuffles in the following order:
11072 // 1. [all] pshuflw, pshufhw, optional move
11073 // 2. [ssse3] 1 x pshufb
11074 // 3. [ssse3] 2 x pshufb + 1 x por
11075 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11077 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11078 SelectionDAG &DAG) {
11079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11080 SDValue V1 = SVOp->getOperand(0);
11081 SDValue V2 = SVOp->getOperand(1);
11083 SmallVector<int, 8> MaskVals;
11085 // Determine if more than 1 of the words in each of the low and high quadwords
11086 // of the result come from the same quadword of one of the two inputs. Undef
11087 // mask values count as coming from any quadword, for better codegen.
11089 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11090 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11091 unsigned LoQuad[] = { 0, 0, 0, 0 };
11092 unsigned HiQuad[] = { 0, 0, 0, 0 };
11093 // Indices of quads used.
11094 std::bitset<4> InputQuads;
11095 for (unsigned i = 0; i < 8; ++i) {
11096 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11097 int EltIdx = SVOp->getMaskElt(i);
11098 MaskVals.push_back(EltIdx);
11106 ++Quad[EltIdx / 4];
11107 InputQuads.set(EltIdx / 4);
11110 int BestLoQuad = -1;
11111 unsigned MaxQuad = 1;
11112 for (unsigned i = 0; i < 4; ++i) {
11113 if (LoQuad[i] > MaxQuad) {
11115 MaxQuad = LoQuad[i];
11119 int BestHiQuad = -1;
11121 for (unsigned i = 0; i < 4; ++i) {
11122 if (HiQuad[i] > MaxQuad) {
11124 MaxQuad = HiQuad[i];
11128 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11129 // of the two input vectors, shuffle them into one input vector so only a
11130 // single pshufb instruction is necessary. If there are more than 2 input
11131 // quads, disable the next transformation since it does not help SSSE3.
11132 bool V1Used = InputQuads[0] || InputQuads[1];
11133 bool V2Used = InputQuads[2] || InputQuads[3];
11134 if (Subtarget->hasSSSE3()) {
11135 if (InputQuads.count() == 2 && V1Used && V2Used) {
11136 BestLoQuad = InputQuads[0] ? 0 : 1;
11137 BestHiQuad = InputQuads[2] ? 2 : 3;
11139 if (InputQuads.count() > 2) {
11145 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11146 // the shuffle mask. If a quad is scored as -1, that means that it contains
11147 // words from all 4 input quadwords.
11149 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11151 BestLoQuad < 0 ? 0 : BestLoQuad,
11152 BestHiQuad < 0 ? 1 : BestHiQuad
11154 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11155 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11156 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11157 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11159 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11160 // source words for the shuffle, to aid later transformations.
11161 bool AllWordsInNewV = true;
11162 bool InOrder[2] = { true, true };
11163 for (unsigned i = 0; i != 8; ++i) {
11164 int idx = MaskVals[i];
11166 InOrder[i/4] = false;
11167 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11169 AllWordsInNewV = false;
11173 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11174 if (AllWordsInNewV) {
11175 for (int i = 0; i != 8; ++i) {
11176 int idx = MaskVals[i];
11179 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11180 if ((idx != i) && idx < 4)
11182 if ((idx != i) && idx > 3)
11191 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11192 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11193 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11194 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11195 unsigned TargetMask = 0;
11196 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11197 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11198 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11199 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11200 getShufflePSHUFLWImmediate(SVOp);
11201 V1 = NewV.getOperand(0);
11202 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11206 // Promote splats to a larger type which usually leads to more efficient code.
11207 // FIXME: Is this true if pshufb is available?
11208 if (SVOp->isSplat())
11209 return PromoteSplat(SVOp, DAG);
11211 // If we have SSSE3, and all words of the result are from 1 input vector,
11212 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11213 // is present, fall back to case 4.
11214 if (Subtarget->hasSSSE3()) {
11215 SmallVector<SDValue,16> pshufbMask;
11217 // If we have elements from both input vectors, set the high bit of the
11218 // shuffle mask element to zero out elements that come from V2 in the V1
11219 // mask, and elements that come from V1 in the V2 mask, so that the two
11220 // results can be OR'd together.
11221 bool TwoInputs = V1Used && V2Used;
11222 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11224 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11226 // Calculate the shuffle mask for the second input, shuffle it, and
11227 // OR it with the first shuffled input.
11228 CommuteVectorShuffleMask(MaskVals, 8);
11229 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11230 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11231 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11234 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11235 // and update MaskVals with new element order.
11236 std::bitset<8> InOrder;
11237 if (BestLoQuad >= 0) {
11238 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11239 for (int i = 0; i != 4; ++i) {
11240 int idx = MaskVals[i];
11243 } else if ((idx / 4) == BestLoQuad) {
11244 MaskV[i] = idx & 3;
11248 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11251 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11252 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11253 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11254 NewV.getOperand(0),
11255 getShufflePSHUFLWImmediate(SVOp), DAG);
11259 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11260 // and update MaskVals with the new element order.
11261 if (BestHiQuad >= 0) {
11262 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11263 for (unsigned i = 4; i != 8; ++i) {
11264 int idx = MaskVals[i];
11267 } else if ((idx / 4) == BestHiQuad) {
11268 MaskV[i] = (idx & 3) + 4;
11272 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11275 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11277 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11278 NewV.getOperand(0),
11279 getShufflePSHUFHWImmediate(SVOp), DAG);
11283 // In case BestHi & BestLo were both -1, which means each quadword has a word
11284 // from each of the four input quadwords, calculate the InOrder bitvector now
11285 // before falling through to the insert/extract cleanup.
11286 if (BestLoQuad == -1 && BestHiQuad == -1) {
11288 for (int i = 0; i != 8; ++i)
11289 if (MaskVals[i] < 0 || MaskVals[i] == i)
11293 // The other elements are put in the right place using pextrw and pinsrw.
11294 for (unsigned i = 0; i != 8; ++i) {
11297 int EltIdx = MaskVals[i];
11300 SDValue ExtOp = (EltIdx < 8) ?
11301 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11302 DAG.getIntPtrConstant(EltIdx)) :
11303 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11304 DAG.getIntPtrConstant(EltIdx - 8));
11305 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11306 DAG.getIntPtrConstant(i));
11311 /// \brief v16i16 shuffles
11313 /// FIXME: We only support generation of a single pshufb currently. We can
11314 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11315 /// well (e.g 2 x pshufb + 1 x por).
11317 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11319 SDValue V1 = SVOp->getOperand(0);
11320 SDValue V2 = SVOp->getOperand(1);
11323 if (V2.getOpcode() != ISD::UNDEF)
11326 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11327 return getPSHUFB(MaskVals, V1, dl, DAG);
11330 // v16i8 shuffles - Prefer shuffles in the following order:
11331 // 1. [ssse3] 1 x pshufb
11332 // 2. [ssse3] 2 x pshufb + 1 x por
11333 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11334 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11335 const X86Subtarget* Subtarget,
11336 SelectionDAG &DAG) {
11337 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11338 SDValue V1 = SVOp->getOperand(0);
11339 SDValue V2 = SVOp->getOperand(1);
11341 ArrayRef<int> MaskVals = SVOp->getMask();
11343 // Promote splats to a larger type which usually leads to more efficient code.
11344 // FIXME: Is this true if pshufb is available?
11345 if (SVOp->isSplat())
11346 return PromoteSplat(SVOp, DAG);
11348 // If we have SSSE3, case 1 is generated when all result bytes come from
11349 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11350 // present, fall back to case 3.
11352 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11353 if (Subtarget->hasSSSE3()) {
11354 SmallVector<SDValue,16> pshufbMask;
11356 // If all result elements are from one input vector, then only translate
11357 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11359 // Otherwise, we have elements from both input vectors, and must zero out
11360 // elements that come from V2 in the first mask, and V1 in the second mask
11361 // so that we can OR them together.
11362 for (unsigned i = 0; i != 16; ++i) {
11363 int EltIdx = MaskVals[i];
11364 if (EltIdx < 0 || EltIdx >= 16)
11366 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11368 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11369 DAG.getNode(ISD::BUILD_VECTOR, dl,
11370 MVT::v16i8, pshufbMask));
11372 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11373 // the 2nd operand if it's undefined or zero.
11374 if (V2.getOpcode() == ISD::UNDEF ||
11375 ISD::isBuildVectorAllZeros(V2.getNode()))
11378 // Calculate the shuffle mask for the second input, shuffle it, and
11379 // OR it with the first shuffled input.
11380 pshufbMask.clear();
11381 for (unsigned i = 0; i != 16; ++i) {
11382 int EltIdx = MaskVals[i];
11383 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11384 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11386 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11387 DAG.getNode(ISD::BUILD_VECTOR, dl,
11388 MVT::v16i8, pshufbMask));
11389 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11392 // No SSSE3 - Calculate in place words and then fix all out of place words
11393 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11394 // the 16 different words that comprise the two doublequadword input vectors.
11395 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11396 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11398 for (int i = 0; i != 8; ++i) {
11399 int Elt0 = MaskVals[i*2];
11400 int Elt1 = MaskVals[i*2+1];
11402 // This word of the result is all undef, skip it.
11403 if (Elt0 < 0 && Elt1 < 0)
11406 // This word of the result is already in the correct place, skip it.
11407 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11410 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11411 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11414 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11415 // using a single extract together, load it and store it.
11416 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11417 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11418 DAG.getIntPtrConstant(Elt1 / 2));
11419 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11420 DAG.getIntPtrConstant(i));
11424 // If Elt1 is defined, extract it from the appropriate source. If the
11425 // source byte is not also odd, shift the extracted word left 8 bits
11426 // otherwise clear the bottom 8 bits if we need to do an or.
11428 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11429 DAG.getIntPtrConstant(Elt1 / 2));
11430 if ((Elt1 & 1) == 0)
11431 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11433 TLI.getShiftAmountTy(InsElt.getValueType())));
11434 else if (Elt0 >= 0)
11435 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11436 DAG.getConstant(0xFF00, MVT::i16));
11438 // If Elt0 is defined, extract it from the appropriate source. If the
11439 // source byte is not also even, shift the extracted word right 8 bits. If
11440 // Elt1 was also defined, OR the extracted values together before
11441 // inserting them in the result.
11443 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11444 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11445 if ((Elt0 & 1) != 0)
11446 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11448 TLI.getShiftAmountTy(InsElt0.getValueType())));
11449 else if (Elt1 >= 0)
11450 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11451 DAG.getConstant(0x00FF, MVT::i16));
11452 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11455 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11456 DAG.getIntPtrConstant(i));
11458 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11461 // v32i8 shuffles - Translate to VPSHUFB if possible.
11463 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11464 const X86Subtarget *Subtarget,
11465 SelectionDAG &DAG) {
11466 MVT VT = SVOp->getSimpleValueType(0);
11467 SDValue V1 = SVOp->getOperand(0);
11468 SDValue V2 = SVOp->getOperand(1);
11470 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11472 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11473 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11474 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11476 // VPSHUFB may be generated if
11477 // (1) one of input vector is undefined or zeroinitializer.
11478 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11479 // And (2) the mask indexes don't cross the 128-bit lane.
11480 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11481 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11484 if (V1IsAllZero && !V2IsAllZero) {
11485 CommuteVectorShuffleMask(MaskVals, 32);
11488 return getPSHUFB(MaskVals, V1, dl, DAG);
11491 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11492 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11493 /// done when every pair / quad of shuffle mask elements point to elements in
11494 /// the right sequence. e.g.
11495 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11497 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11498 SelectionDAG &DAG) {
11499 MVT VT = SVOp->getSimpleValueType(0);
11501 unsigned NumElems = VT.getVectorNumElements();
11504 switch (VT.SimpleTy) {
11505 default: llvm_unreachable("Unexpected!");
11508 return SDValue(SVOp, 0);
11509 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11510 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11511 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11512 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11513 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11514 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11517 SmallVector<int, 8> MaskVec;
11518 for (unsigned i = 0; i != NumElems; i += Scale) {
11520 for (unsigned j = 0; j != Scale; ++j) {
11521 int EltIdx = SVOp->getMaskElt(i+j);
11525 StartIdx = (EltIdx / Scale);
11526 if (EltIdx != (int)(StartIdx*Scale + j))
11529 MaskVec.push_back(StartIdx);
11532 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11533 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11534 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11537 /// getVZextMovL - Return a zero-extending vector move low node.
11539 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11540 SDValue SrcOp, SelectionDAG &DAG,
11541 const X86Subtarget *Subtarget, SDLoc dl) {
11542 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11543 LoadSDNode *LD = nullptr;
11544 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11545 LD = dyn_cast<LoadSDNode>(SrcOp);
11547 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11549 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11550 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11551 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11552 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11553 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11555 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11556 return DAG.getNode(ISD::BITCAST, dl, VT,
11557 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11558 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11560 SrcOp.getOperand(0)
11566 return DAG.getNode(ISD::BITCAST, dl, VT,
11567 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11568 DAG.getNode(ISD::BITCAST, dl,
11572 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11573 /// which could not be matched by any known target speficic shuffle
11575 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11577 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11578 if (NewOp.getNode())
11581 MVT VT = SVOp->getSimpleValueType(0);
11583 unsigned NumElems = VT.getVectorNumElements();
11584 unsigned NumLaneElems = NumElems / 2;
11587 MVT EltVT = VT.getVectorElementType();
11588 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11591 SmallVector<int, 16> Mask;
11592 for (unsigned l = 0; l < 2; ++l) {
11593 // Build a shuffle mask for the output, discovering on the fly which
11594 // input vectors to use as shuffle operands (recorded in InputUsed).
11595 // If building a suitable shuffle vector proves too hard, then bail
11596 // out with UseBuildVector set.
11597 bool UseBuildVector = false;
11598 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11599 unsigned LaneStart = l * NumLaneElems;
11600 for (unsigned i = 0; i != NumLaneElems; ++i) {
11601 // The mask element. This indexes into the input.
11602 int Idx = SVOp->getMaskElt(i+LaneStart);
11604 // the mask element does not index into any input vector.
11605 Mask.push_back(-1);
11609 // The input vector this mask element indexes into.
11610 int Input = Idx / NumLaneElems;
11612 // Turn the index into an offset from the start of the input vector.
11613 Idx -= Input * NumLaneElems;
11615 // Find or create a shuffle vector operand to hold this input.
11617 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11618 if (InputUsed[OpNo] == Input)
11619 // This input vector is already an operand.
11621 if (InputUsed[OpNo] < 0) {
11622 // Create a new operand for this input vector.
11623 InputUsed[OpNo] = Input;
11628 if (OpNo >= array_lengthof(InputUsed)) {
11629 // More than two input vectors used! Give up on trying to create a
11630 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11631 UseBuildVector = true;
11635 // Add the mask index for the new shuffle vector.
11636 Mask.push_back(Idx + OpNo * NumLaneElems);
11639 if (UseBuildVector) {
11640 SmallVector<SDValue, 16> SVOps;
11641 for (unsigned i = 0; i != NumLaneElems; ++i) {
11642 // The mask element. This indexes into the input.
11643 int Idx = SVOp->getMaskElt(i+LaneStart);
11645 SVOps.push_back(DAG.getUNDEF(EltVT));
11649 // The input vector this mask element indexes into.
11650 int Input = Idx / NumElems;
11652 // Turn the index into an offset from the start of the input vector.
11653 Idx -= Input * NumElems;
11655 // Extract the vector element by hand.
11656 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11657 SVOp->getOperand(Input),
11658 DAG.getIntPtrConstant(Idx)));
11661 // Construct the output using a BUILD_VECTOR.
11662 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11663 } else if (InputUsed[0] < 0) {
11664 // No input vectors were used! The result is undefined.
11665 Output[l] = DAG.getUNDEF(NVT);
11667 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11668 (InputUsed[0] % 2) * NumLaneElems,
11670 // If only one input was used, use an undefined vector for the other.
11671 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11672 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11673 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11674 // At least one input vector was used. Create a new shuffle vector.
11675 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11681 // Concatenate the result back
11682 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11685 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11686 /// 4 elements, and match them with several different shuffle types.
11688 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11689 SDValue V1 = SVOp->getOperand(0);
11690 SDValue V2 = SVOp->getOperand(1);
11692 MVT VT = SVOp->getSimpleValueType(0);
11694 assert(VT.is128BitVector() && "Unsupported vector size");
11696 std::pair<int, int> Locs[4];
11697 int Mask1[] = { -1, -1, -1, -1 };
11698 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11700 unsigned NumHi = 0;
11701 unsigned NumLo = 0;
11702 for (unsigned i = 0; i != 4; ++i) {
11703 int Idx = PermMask[i];
11705 Locs[i] = std::make_pair(-1, -1);
11707 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11709 Locs[i] = std::make_pair(0, NumLo);
11710 Mask1[NumLo] = Idx;
11713 Locs[i] = std::make_pair(1, NumHi);
11715 Mask1[2+NumHi] = Idx;
11721 if (NumLo <= 2 && NumHi <= 2) {
11722 // If no more than two elements come from either vector. This can be
11723 // implemented with two shuffles. First shuffle gather the elements.
11724 // The second shuffle, which takes the first shuffle as both of its
11725 // vector operands, put the elements into the right order.
11726 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11728 int Mask2[] = { -1, -1, -1, -1 };
11730 for (unsigned i = 0; i != 4; ++i)
11731 if (Locs[i].first != -1) {
11732 unsigned Idx = (i < 2) ? 0 : 4;
11733 Idx += Locs[i].first * 2 + Locs[i].second;
11737 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11740 if (NumLo == 3 || NumHi == 3) {
11741 // Otherwise, we must have three elements from one vector, call it X, and
11742 // one element from the other, call it Y. First, use a shufps to build an
11743 // intermediate vector with the one element from Y and the element from X
11744 // that will be in the same half in the final destination (the indexes don't
11745 // matter). Then, use a shufps to build the final vector, taking the half
11746 // containing the element from Y from the intermediate, and the other half
11749 // Normalize it so the 3 elements come from V1.
11750 CommuteVectorShuffleMask(PermMask, 4);
11754 // Find the element from V2.
11756 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11757 int Val = PermMask[HiIndex];
11764 Mask1[0] = PermMask[HiIndex];
11766 Mask1[2] = PermMask[HiIndex^1];
11768 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11770 if (HiIndex >= 2) {
11771 Mask1[0] = PermMask[0];
11772 Mask1[1] = PermMask[1];
11773 Mask1[2] = HiIndex & 1 ? 6 : 4;
11774 Mask1[3] = HiIndex & 1 ? 4 : 6;
11775 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11778 Mask1[0] = HiIndex & 1 ? 2 : 0;
11779 Mask1[1] = HiIndex & 1 ? 0 : 2;
11780 Mask1[2] = PermMask[2];
11781 Mask1[3] = PermMask[3];
11786 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11789 // Break it into (shuffle shuffle_hi, shuffle_lo).
11790 int LoMask[] = { -1, -1, -1, -1 };
11791 int HiMask[] = { -1, -1, -1, -1 };
11793 int *MaskPtr = LoMask;
11794 unsigned MaskIdx = 0;
11795 unsigned LoIdx = 0;
11796 unsigned HiIdx = 2;
11797 for (unsigned i = 0; i != 4; ++i) {
11804 int Idx = PermMask[i];
11806 Locs[i] = std::make_pair(-1, -1);
11807 } else if (Idx < 4) {
11808 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11809 MaskPtr[LoIdx] = Idx;
11812 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11813 MaskPtr[HiIdx] = Idx;
11818 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11819 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11820 int MaskOps[] = { -1, -1, -1, -1 };
11821 for (unsigned i = 0; i != 4; ++i)
11822 if (Locs[i].first != -1)
11823 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11824 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11827 static bool MayFoldVectorLoad(SDValue V) {
11828 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11829 V = V.getOperand(0);
11831 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11832 V = V.getOperand(0);
11833 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11834 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11835 // BUILD_VECTOR (load), undef
11836 V = V.getOperand(0);
11838 return MayFoldLoad(V);
11842 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11843 MVT VT = Op.getSimpleValueType();
11845 // Canonizalize to v2f64.
11846 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11847 return DAG.getNode(ISD::BITCAST, dl, VT,
11848 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11853 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11855 SDValue V1 = Op.getOperand(0);
11856 SDValue V2 = Op.getOperand(1);
11857 MVT VT = Op.getSimpleValueType();
11859 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11861 if (HasSSE2 && VT == MVT::v2f64)
11862 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11864 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11865 return DAG.getNode(ISD::BITCAST, dl, VT,
11866 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11867 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11868 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11872 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11873 SDValue V1 = Op.getOperand(0);
11874 SDValue V2 = Op.getOperand(1);
11875 MVT VT = Op.getSimpleValueType();
11877 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11878 "unsupported shuffle type");
11880 if (V2.getOpcode() == ISD::UNDEF)
11884 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11888 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11889 SDValue V1 = Op.getOperand(0);
11890 SDValue V2 = Op.getOperand(1);
11891 MVT VT = Op.getSimpleValueType();
11892 unsigned NumElems = VT.getVectorNumElements();
11894 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11895 // operand of these instructions is only memory, so check if there's a
11896 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11898 bool CanFoldLoad = false;
11900 // Trivial case, when V2 comes from a load.
11901 if (MayFoldVectorLoad(V2))
11902 CanFoldLoad = true;
11904 // When V1 is a load, it can be folded later into a store in isel, example:
11905 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11907 // (MOVLPSmr addr:$src1, VR128:$src2)
11908 // So, recognize this potential and also use MOVLPS or MOVLPD
11909 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11910 CanFoldLoad = true;
11912 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11914 if (HasSSE2 && NumElems == 2)
11915 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11918 // If we don't care about the second element, proceed to use movss.
11919 if (SVOp->getMaskElt(1) != -1)
11920 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11923 // movl and movlp will both match v2i64, but v2i64 is never matched by
11924 // movl earlier because we make it strict to avoid messing with the movlp load
11925 // folding logic (see the code above getMOVLP call). Match it here then,
11926 // this is horrible, but will stay like this until we move all shuffle
11927 // matching to x86 specific nodes. Note that for the 1st condition all
11928 // types are matched with movsd.
11930 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11931 // as to remove this logic from here, as much as possible
11932 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11933 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11934 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11937 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11939 // Invert the operand order and use SHUFPS to match it.
11940 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11941 getShuffleSHUFImmediate(SVOp), DAG);
11944 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11945 SelectionDAG &DAG) {
11947 MVT VT = Load->getSimpleValueType(0);
11948 MVT EVT = VT.getVectorElementType();
11949 SDValue Addr = Load->getOperand(1);
11950 SDValue NewAddr = DAG.getNode(
11951 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11952 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11955 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11956 DAG.getMachineFunction().getMachineMemOperand(
11957 Load->getMemOperand(), 0, EVT.getStoreSize()));
11961 // It is only safe to call this function if isINSERTPSMask is true for
11962 // this shufflevector mask.
11963 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11964 SelectionDAG &DAG) {
11965 // Generate an insertps instruction when inserting an f32 from memory onto a
11966 // v4f32 or when copying a member from one v4f32 to another.
11967 // We also use it for transferring i32 from one register to another,
11968 // since it simply copies the same bits.
11969 // If we're transferring an i32 from memory to a specific element in a
11970 // register, we output a generic DAG that will match the PINSRD
11972 MVT VT = SVOp->getSimpleValueType(0);
11973 MVT EVT = VT.getVectorElementType();
11974 SDValue V1 = SVOp->getOperand(0);
11975 SDValue V2 = SVOp->getOperand(1);
11976 auto Mask = SVOp->getMask();
11977 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11978 "unsupported vector type for insertps/pinsrd");
11980 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11981 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11982 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11986 unsigned DestIndex;
11990 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11993 // If we have 1 element from each vector, we have to check if we're
11994 // changing V1's element's place. If so, we're done. Otherwise, we
11995 // should assume we're changing V2's element's place and behave
11997 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11998 assert(DestIndex <= INT32_MAX && "truncated destination index");
11999 if (FromV1 == FromV2 &&
12000 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12004 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12007 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12008 "More than one element from V1 and from V2, or no elements from one "
12009 "of the vectors. This case should not have returned true from "
12014 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12017 // Get an index into the source vector in the range [0,4) (the mask is
12018 // in the range [0,8) because it can address V1 and V2)
12019 unsigned SrcIndex = Mask[DestIndex] % 4;
12020 if (MayFoldLoad(From)) {
12021 // Trivial case, when From comes from a load and is only used by the
12022 // shuffle. Make it use insertps from the vector that we need from that
12025 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12026 if (!NewLoad.getNode())
12029 if (EVT == MVT::f32) {
12030 // Create this as a scalar to vector to match the instruction pattern.
12031 SDValue LoadScalarToVector =
12032 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12033 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12034 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12036 } else { // EVT == MVT::i32
12037 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12038 // instruction, to match the PINSRD instruction, which loads an i32 to a
12039 // certain vector element.
12040 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12041 DAG.getConstant(DestIndex, MVT::i32));
12045 // Vector-element-to-vector
12046 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12047 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12050 // Reduce a vector shuffle to zext.
12051 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12052 SelectionDAG &DAG) {
12053 // PMOVZX is only available from SSE41.
12054 if (!Subtarget->hasSSE41())
12057 MVT VT = Op.getSimpleValueType();
12059 // Only AVX2 support 256-bit vector integer extending.
12060 if (!Subtarget->hasInt256() && VT.is256BitVector())
12063 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12065 SDValue V1 = Op.getOperand(0);
12066 SDValue V2 = Op.getOperand(1);
12067 unsigned NumElems = VT.getVectorNumElements();
12069 // Extending is an unary operation and the element type of the source vector
12070 // won't be equal to or larger than i64.
12071 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12072 VT.getVectorElementType() == MVT::i64)
12075 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12076 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12077 while ((1U << Shift) < NumElems) {
12078 if (SVOp->getMaskElt(1U << Shift) == 1)
12081 // The maximal ratio is 8, i.e. from i8 to i64.
12086 // Check the shuffle mask.
12087 unsigned Mask = (1U << Shift) - 1;
12088 for (unsigned i = 0; i != NumElems; ++i) {
12089 int EltIdx = SVOp->getMaskElt(i);
12090 if ((i & Mask) != 0 && EltIdx != -1)
12092 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12096 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12097 MVT NeVT = MVT::getIntegerVT(NBits);
12098 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12100 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12103 return DAG.getNode(ISD::BITCAST, DL, VT,
12104 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12107 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12108 SelectionDAG &DAG) {
12109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12110 MVT VT = Op.getSimpleValueType();
12112 SDValue V1 = Op.getOperand(0);
12113 SDValue V2 = Op.getOperand(1);
12115 if (isZeroShuffle(SVOp))
12116 return getZeroVector(VT, Subtarget, DAG, dl);
12118 // Handle splat operations
12119 if (SVOp->isSplat()) {
12120 // Use vbroadcast whenever the splat comes from a foldable load
12121 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12122 if (Broadcast.getNode())
12126 // Check integer expanding shuffles.
12127 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12128 if (NewOp.getNode())
12131 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12133 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12134 VT == MVT::v32i8) {
12135 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12136 if (NewOp.getNode())
12137 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12138 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12139 // FIXME: Figure out a cleaner way to do this.
12140 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12141 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12142 if (NewOp.getNode()) {
12143 MVT NewVT = NewOp.getSimpleValueType();
12144 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12145 NewVT, true, false))
12146 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12149 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12150 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12151 if (NewOp.getNode()) {
12152 MVT NewVT = NewOp.getSimpleValueType();
12153 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12154 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12163 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12165 SDValue V1 = Op.getOperand(0);
12166 SDValue V2 = Op.getOperand(1);
12167 MVT VT = Op.getSimpleValueType();
12169 unsigned NumElems = VT.getVectorNumElements();
12170 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12171 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12172 bool V1IsSplat = false;
12173 bool V2IsSplat = false;
12174 bool HasSSE2 = Subtarget->hasSSE2();
12175 bool HasFp256 = Subtarget->hasFp256();
12176 bool HasInt256 = Subtarget->hasInt256();
12177 MachineFunction &MF = DAG.getMachineFunction();
12178 bool OptForSize = MF.getFunction()->getAttributes().
12179 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12181 // Check if we should use the experimental vector shuffle lowering. If so,
12182 // delegate completely to that code path.
12183 if (ExperimentalVectorShuffleLowering)
12184 return lowerVectorShuffle(Op, Subtarget, DAG);
12186 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12188 if (V1IsUndef && V2IsUndef)
12189 return DAG.getUNDEF(VT);
12191 // When we create a shuffle node we put the UNDEF node to second operand,
12192 // but in some cases the first operand may be transformed to UNDEF.
12193 // In this case we should just commute the node.
12195 return DAG.getCommutedVectorShuffle(*SVOp);
12197 // Vector shuffle lowering takes 3 steps:
12199 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12200 // narrowing and commutation of operands should be handled.
12201 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12203 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12204 // so the shuffle can be broken into other shuffles and the legalizer can
12205 // try the lowering again.
12207 // The general idea is that no vector_shuffle operation should be left to
12208 // be matched during isel, all of them must be converted to a target specific
12211 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12212 // narrowing and commutation of operands should be handled. The actual code
12213 // doesn't include all of those, work in progress...
12214 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12215 if (NewOp.getNode())
12218 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12220 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12221 // unpckh_undef). Only use pshufd if speed is more important than size.
12222 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12223 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12224 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12225 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12227 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12228 V2IsUndef && MayFoldVectorLoad(V1))
12229 return getMOVDDup(Op, dl, V1, DAG);
12231 if (isMOVHLPS_v_undef_Mask(M, VT))
12232 return getMOVHighToLow(Op, dl, DAG);
12234 // Use to match splats
12235 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12236 (VT == MVT::v2f64 || VT == MVT::v2i64))
12237 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12239 if (isPSHUFDMask(M, VT)) {
12240 // The actual implementation will match the mask in the if above and then
12241 // during isel it can match several different instructions, not only pshufd
12242 // as its name says, sad but true, emulate the behavior for now...
12243 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12244 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12246 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12248 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12249 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12251 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12252 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12255 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12259 if (isPALIGNRMask(M, VT, Subtarget))
12260 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12261 getShufflePALIGNRImmediate(SVOp),
12264 if (isVALIGNMask(M, VT, Subtarget))
12265 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12266 getShuffleVALIGNImmediate(SVOp),
12269 // Check if this can be converted into a logical shift.
12270 bool isLeft = false;
12271 unsigned ShAmt = 0;
12273 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12274 if (isShift && ShVal.hasOneUse()) {
12275 // If the shifted value has multiple uses, it may be cheaper to use
12276 // v_set0 + movlhps or movhlps, etc.
12277 MVT EltVT = VT.getVectorElementType();
12278 ShAmt *= EltVT.getSizeInBits();
12279 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12282 if (isMOVLMask(M, VT)) {
12283 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12284 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12285 if (!isMOVLPMask(M, VT)) {
12286 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12287 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12289 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12290 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12294 // FIXME: fold these into legal mask.
12295 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12296 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12298 if (isMOVHLPSMask(M, VT))
12299 return getMOVHighToLow(Op, dl, DAG);
12301 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12302 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12304 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12305 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12307 if (isMOVLPMask(M, VT))
12308 return getMOVLP(Op, dl, DAG, HasSSE2);
12310 if (ShouldXformToMOVHLPS(M, VT) ||
12311 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12312 return DAG.getCommutedVectorShuffle(*SVOp);
12315 // No better options. Use a vshldq / vsrldq.
12316 MVT EltVT = VT.getVectorElementType();
12317 ShAmt *= EltVT.getSizeInBits();
12318 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12321 bool Commuted = false;
12322 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12323 // 1,1,1,1 -> v8i16 though.
12324 BitVector UndefElements;
12325 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12326 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12328 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12329 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12332 // Canonicalize the splat or undef, if present, to be on the RHS.
12333 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12334 CommuteVectorShuffleMask(M, NumElems);
12336 std::swap(V1IsSplat, V2IsSplat);
12340 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12341 // Shuffling low element of v1 into undef, just return v1.
12344 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12345 // the instruction selector will not match, so get a canonical MOVL with
12346 // swapped operands to undo the commute.
12347 return getMOVL(DAG, dl, VT, V2, V1);
12350 if (isUNPCKLMask(M, VT, HasInt256))
12351 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12353 if (isUNPCKHMask(M, VT, HasInt256))
12354 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12357 // Normalize mask so all entries that point to V2 points to its first
12358 // element then try to match unpck{h|l} again. If match, return a
12359 // new vector_shuffle with the corrected mask.p
12360 SmallVector<int, 8> NewMask(M.begin(), M.end());
12361 NormalizeMask(NewMask, NumElems);
12362 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12363 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12364 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12365 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12369 // Commute is back and try unpck* again.
12370 // FIXME: this seems wrong.
12371 CommuteVectorShuffleMask(M, NumElems);
12373 std::swap(V1IsSplat, V2IsSplat);
12375 if (isUNPCKLMask(M, VT, HasInt256))
12376 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12378 if (isUNPCKHMask(M, VT, HasInt256))
12379 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12382 // Normalize the node to match x86 shuffle ops if needed
12383 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12384 return DAG.getCommutedVectorShuffle(*SVOp);
12386 // The checks below are all present in isShuffleMaskLegal, but they are
12387 // inlined here right now to enable us to directly emit target specific
12388 // nodes, and remove one by one until they don't return Op anymore.
12390 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12391 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12392 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12393 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12396 if (isPSHUFHWMask(M, VT, HasInt256))
12397 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12398 getShufflePSHUFHWImmediate(SVOp),
12401 if (isPSHUFLWMask(M, VT, HasInt256))
12402 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12403 getShufflePSHUFLWImmediate(SVOp),
12406 unsigned MaskValue;
12407 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12409 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12411 if (isSHUFPMask(M, VT))
12412 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12413 getShuffleSHUFImmediate(SVOp), DAG);
12415 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12416 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12417 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12418 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12420 //===--------------------------------------------------------------------===//
12421 // Generate target specific nodes for 128 or 256-bit shuffles only
12422 // supported in the AVX instruction set.
12425 // Handle VMOVDDUPY permutations
12426 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12427 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12429 // Handle VPERMILPS/D* permutations
12430 if (isVPERMILPMask(M, VT)) {
12431 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12432 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12433 getShuffleSHUFImmediate(SVOp), DAG);
12434 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12435 getShuffleSHUFImmediate(SVOp), DAG);
12439 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12440 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12441 Idx*(NumElems/2), DAG, dl);
12443 // Handle VPERM2F128/VPERM2I128 permutations
12444 if (isVPERM2X128Mask(M, VT, HasFp256))
12445 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12446 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12448 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12449 return getINSERTPS(SVOp, dl, DAG);
12452 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12453 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12455 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12456 VT.is512BitVector()) {
12457 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12458 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12459 SmallVector<SDValue, 16> permclMask;
12460 for (unsigned i = 0; i != NumElems; ++i) {
12461 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12464 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12466 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12467 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12468 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12469 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12470 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12473 //===--------------------------------------------------------------------===//
12474 // Since no target specific shuffle was selected for this generic one,
12475 // lower it into other known shuffles. FIXME: this isn't true yet, but
12476 // this is the plan.
12479 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12480 if (VT == MVT::v8i16) {
12481 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12482 if (NewOp.getNode())
12486 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12487 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12488 if (NewOp.getNode())
12492 if (VT == MVT::v16i8) {
12493 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12494 if (NewOp.getNode())
12498 if (VT == MVT::v32i8) {
12499 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12500 if (NewOp.getNode())
12504 // Handle all 128-bit wide vectors with 4 elements, and match them with
12505 // several different shuffle types.
12506 if (NumElems == 4 && VT.is128BitVector())
12507 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12509 // Handle general 256-bit shuffles
12510 if (VT.is256BitVector())
12511 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12516 // This function assumes its argument is a BUILD_VECTOR of constants or
12517 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12519 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12520 unsigned &MaskValue) {
12522 unsigned NumElems = BuildVector->getNumOperands();
12523 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12524 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12525 unsigned NumElemsInLane = NumElems / NumLanes;
12527 // Blend for v16i16 should be symetric for the both lanes.
12528 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12529 SDValue EltCond = BuildVector->getOperand(i);
12530 SDValue SndLaneEltCond =
12531 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12533 int Lane1Cond = -1, Lane2Cond = -1;
12534 if (isa<ConstantSDNode>(EltCond))
12535 Lane1Cond = !isZero(EltCond);
12536 if (isa<ConstantSDNode>(SndLaneEltCond))
12537 Lane2Cond = !isZero(SndLaneEltCond);
12539 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12540 // Lane1Cond != 0, means we want the first argument.
12541 // Lane1Cond == 0, means we want the second argument.
12542 // The encoding of this argument is 0 for the first argument, 1
12543 // for the second. Therefore, invert the condition.
12544 MaskValue |= !Lane1Cond << i;
12545 else if (Lane1Cond < 0)
12546 MaskValue |= !Lane2Cond << i;
12553 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12555 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12556 SelectionDAG &DAG) {
12557 SDValue Cond = Op.getOperand(0);
12558 SDValue LHS = Op.getOperand(1);
12559 SDValue RHS = Op.getOperand(2);
12561 MVT VT = Op.getSimpleValueType();
12562 MVT EltVT = VT.getVectorElementType();
12563 unsigned NumElems = VT.getVectorNumElements();
12565 // There is no blend with immediate in AVX-512.
12566 if (VT.is512BitVector())
12569 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12571 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12574 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12577 // Check the mask for BLEND and build the value.
12578 unsigned MaskValue = 0;
12579 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12582 // Convert i32 vectors to floating point if it is not AVX2.
12583 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12585 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12586 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12588 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12589 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12592 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12593 DAG.getConstant(MaskValue, MVT::i32));
12594 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12597 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12598 // A vselect where all conditions and data are constants can be optimized into
12599 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12600 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12601 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12602 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12605 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12606 if (BlendOp.getNode())
12609 // Some types for vselect were previously set to Expand, not Legal or
12610 // Custom. Return an empty SDValue so we fall-through to Expand, after
12611 // the Custom lowering phase.
12612 MVT VT = Op.getSimpleValueType();
12613 switch (VT.SimpleTy) {
12618 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12623 // We couldn't create a "Blend with immediate" node.
12624 // This node should still be legal, but we'll have to emit a blendv*
12629 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12630 MVT VT = Op.getSimpleValueType();
12633 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12636 if (VT.getSizeInBits() == 8) {
12637 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12638 Op.getOperand(0), Op.getOperand(1));
12639 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12640 DAG.getValueType(VT));
12641 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12644 if (VT.getSizeInBits() == 16) {
12645 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12646 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12648 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12650 DAG.getNode(ISD::BITCAST, dl,
12653 Op.getOperand(1)));
12654 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12655 Op.getOperand(0), Op.getOperand(1));
12656 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12657 DAG.getValueType(VT));
12658 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12661 if (VT == MVT::f32) {
12662 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12663 // the result back to FR32 register. It's only worth matching if the
12664 // result has a single use which is a store or a bitcast to i32. And in
12665 // the case of a store, it's not worth it if the index is a constant 0,
12666 // because a MOVSSmr can be used instead, which is smaller and faster.
12667 if (!Op.hasOneUse())
12669 SDNode *User = *Op.getNode()->use_begin();
12670 if ((User->getOpcode() != ISD::STORE ||
12671 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12672 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12673 (User->getOpcode() != ISD::BITCAST ||
12674 User->getValueType(0) != MVT::i32))
12676 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12677 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12680 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12683 if (VT == MVT::i32 || VT == MVT::i64) {
12684 // ExtractPS/pextrq works with constant index.
12685 if (isa<ConstantSDNode>(Op.getOperand(1)))
12691 /// Extract one bit from mask vector, like v16i1 or v8i1.
12692 /// AVX-512 feature.
12694 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12695 SDValue Vec = Op.getOperand(0);
12697 MVT VecVT = Vec.getSimpleValueType();
12698 SDValue Idx = Op.getOperand(1);
12699 MVT EltVT = Op.getSimpleValueType();
12701 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12703 // variable index can't be handled in mask registers,
12704 // extend vector to VR512
12705 if (!isa<ConstantSDNode>(Idx)) {
12706 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12707 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12708 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12709 ExtVT.getVectorElementType(), Ext, Idx);
12710 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12713 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12714 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12715 unsigned MaxSift = rc->getSize()*8 - 1;
12716 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12717 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12718 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12719 DAG.getConstant(MaxSift, MVT::i8));
12720 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12721 DAG.getIntPtrConstant(0));
12725 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12726 SelectionDAG &DAG) const {
12728 SDValue Vec = Op.getOperand(0);
12729 MVT VecVT = Vec.getSimpleValueType();
12730 SDValue Idx = Op.getOperand(1);
12732 if (Op.getSimpleValueType() == MVT::i1)
12733 return ExtractBitFromMaskVector(Op, DAG);
12735 if (!isa<ConstantSDNode>(Idx)) {
12736 if (VecVT.is512BitVector() ||
12737 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12738 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12741 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12742 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12743 MaskEltVT.getSizeInBits());
12745 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12746 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12747 getZeroVector(MaskVT, Subtarget, DAG, dl),
12748 Idx, DAG.getConstant(0, getPointerTy()));
12749 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12750 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12751 Perm, DAG.getConstant(0, getPointerTy()));
12756 // If this is a 256-bit vector result, first extract the 128-bit vector and
12757 // then extract the element from the 128-bit vector.
12758 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12760 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12761 // Get the 128-bit vector.
12762 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12763 MVT EltVT = VecVT.getVectorElementType();
12765 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12767 //if (IdxVal >= NumElems/2)
12768 // IdxVal -= NumElems/2;
12769 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12770 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12771 DAG.getConstant(IdxVal, MVT::i32));
12774 assert(VecVT.is128BitVector() && "Unexpected vector length");
12776 if (Subtarget->hasSSE41()) {
12777 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12782 MVT VT = Op.getSimpleValueType();
12783 // TODO: handle v16i8.
12784 if (VT.getSizeInBits() == 16) {
12785 SDValue Vec = Op.getOperand(0);
12786 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12788 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12790 DAG.getNode(ISD::BITCAST, dl,
12792 Op.getOperand(1)));
12793 // Transform it so it match pextrw which produces a 32-bit result.
12794 MVT EltVT = MVT::i32;
12795 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12796 Op.getOperand(0), Op.getOperand(1));
12797 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12798 DAG.getValueType(VT));
12799 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12802 if (VT.getSizeInBits() == 32) {
12803 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12807 // SHUFPS the element to the lowest double word, then movss.
12808 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12809 MVT VVT = Op.getOperand(0).getSimpleValueType();
12810 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12811 DAG.getUNDEF(VVT), Mask);
12812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12813 DAG.getIntPtrConstant(0));
12816 if (VT.getSizeInBits() == 64) {
12817 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12818 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12819 // to match extract_elt for f64.
12820 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12824 // UNPCKHPD the element to the lowest double word, then movsd.
12825 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12826 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12827 int Mask[2] = { 1, -1 };
12828 MVT VVT = Op.getOperand(0).getSimpleValueType();
12829 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12830 DAG.getUNDEF(VVT), Mask);
12831 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12832 DAG.getIntPtrConstant(0));
12838 /// Insert one bit to mask vector, like v16i1 or v8i1.
12839 /// AVX-512 feature.
12841 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12843 SDValue Vec = Op.getOperand(0);
12844 SDValue Elt = Op.getOperand(1);
12845 SDValue Idx = Op.getOperand(2);
12846 MVT VecVT = Vec.getSimpleValueType();
12848 if (!isa<ConstantSDNode>(Idx)) {
12849 // Non constant index. Extend source and destination,
12850 // insert element and then truncate the result.
12851 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12852 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12853 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12854 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12855 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12856 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12859 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12860 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12861 if (Vec.getOpcode() == ISD::UNDEF)
12862 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12863 DAG.getConstant(IdxVal, MVT::i8));
12864 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12865 unsigned MaxSift = rc->getSize()*8 - 1;
12866 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12867 DAG.getConstant(MaxSift, MVT::i8));
12868 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12869 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12870 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12873 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12874 SelectionDAG &DAG) const {
12875 MVT VT = Op.getSimpleValueType();
12876 MVT EltVT = VT.getVectorElementType();
12878 if (EltVT == MVT::i1)
12879 return InsertBitToMaskVector(Op, DAG);
12882 SDValue N0 = Op.getOperand(0);
12883 SDValue N1 = Op.getOperand(1);
12884 SDValue N2 = Op.getOperand(2);
12885 if (!isa<ConstantSDNode>(N2))
12887 auto *N2C = cast<ConstantSDNode>(N2);
12888 unsigned IdxVal = N2C->getZExtValue();
12890 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12891 // into that, and then insert the subvector back into the result.
12892 if (VT.is256BitVector() || VT.is512BitVector()) {
12893 // Get the desired 128-bit vector half.
12894 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12896 // Insert the element into the desired half.
12897 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12898 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12900 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12901 DAG.getConstant(IdxIn128, MVT::i32));
12903 // Insert the changed part back to the 256-bit vector
12904 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12906 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12908 if (Subtarget->hasSSE41()) {
12909 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12911 if (VT == MVT::v8i16) {
12912 Opc = X86ISD::PINSRW;
12914 assert(VT == MVT::v16i8);
12915 Opc = X86ISD::PINSRB;
12918 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12920 if (N1.getValueType() != MVT::i32)
12921 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12922 if (N2.getValueType() != MVT::i32)
12923 N2 = DAG.getIntPtrConstant(IdxVal);
12924 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12927 if (EltVT == MVT::f32) {
12928 // Bits [7:6] of the constant are the source select. This will always be
12929 // zero here. The DAG Combiner may combine an extract_elt index into
12931 // bits. For example (insert (extract, 3), 2) could be matched by
12933 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12934 // Bits [5:4] of the constant are the destination select. This is the
12935 // value of the incoming immediate.
12936 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12937 // combine either bitwise AND or insert of float 0.0 to set these bits.
12938 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12939 // Create this as a scalar to vector..
12940 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12941 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12944 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12945 // PINSR* works with constant index.
12950 if (EltVT == MVT::i8)
12953 if (EltVT.getSizeInBits() == 16) {
12954 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12955 // as its second argument.
12956 if (N1.getValueType() != MVT::i32)
12957 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12958 if (N2.getValueType() != MVT::i32)
12959 N2 = DAG.getIntPtrConstant(IdxVal);
12960 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12965 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12967 MVT OpVT = Op.getSimpleValueType();
12969 // If this is a 256-bit vector result, first insert into a 128-bit
12970 // vector and then insert into the 256-bit vector.
12971 if (!OpVT.is128BitVector()) {
12972 // Insert into a 128-bit vector.
12973 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12974 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12975 OpVT.getVectorNumElements() / SizeFactor);
12977 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12979 // Insert the 128-bit vector.
12980 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12983 if (OpVT == MVT::v1i64 &&
12984 Op.getOperand(0).getValueType() == MVT::i64)
12985 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12987 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12988 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12989 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12990 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12993 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12994 // a simple subregister reference or explicit instructions to grab
12995 // upper bits of a vector.
12996 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12997 SelectionDAG &DAG) {
12999 SDValue In = Op.getOperand(0);
13000 SDValue Idx = Op.getOperand(1);
13001 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13002 MVT ResVT = Op.getSimpleValueType();
13003 MVT InVT = In.getSimpleValueType();
13005 if (Subtarget->hasFp256()) {
13006 if (ResVT.is128BitVector() &&
13007 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13008 isa<ConstantSDNode>(Idx)) {
13009 return Extract128BitVector(In, IdxVal, DAG, dl);
13011 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13012 isa<ConstantSDNode>(Idx)) {
13013 return Extract256BitVector(In, IdxVal, DAG, dl);
13019 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13020 // simple superregister reference or explicit instructions to insert
13021 // the upper bits of a vector.
13022 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13023 SelectionDAG &DAG) {
13024 if (Subtarget->hasFp256()) {
13025 SDLoc dl(Op.getNode());
13026 SDValue Vec = Op.getNode()->getOperand(0);
13027 SDValue SubVec = Op.getNode()->getOperand(1);
13028 SDValue Idx = Op.getNode()->getOperand(2);
13030 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13031 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13032 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13033 isa<ConstantSDNode>(Idx)) {
13034 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13035 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13038 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13039 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13040 isa<ConstantSDNode>(Idx)) {
13041 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13042 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13048 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13049 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13050 // one of the above mentioned nodes. It has to be wrapped because otherwise
13051 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13052 // be used to form addressing mode. These wrapped nodes will be selected
13055 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13056 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13058 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13059 // global base reg.
13060 unsigned char OpFlag = 0;
13061 unsigned WrapperKind = X86ISD::Wrapper;
13062 CodeModel::Model M = DAG.getTarget().getCodeModel();
13064 if (Subtarget->isPICStyleRIPRel() &&
13065 (M == CodeModel::Small || M == CodeModel::Kernel))
13066 WrapperKind = X86ISD::WrapperRIP;
13067 else if (Subtarget->isPICStyleGOT())
13068 OpFlag = X86II::MO_GOTOFF;
13069 else if (Subtarget->isPICStyleStubPIC())
13070 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13072 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13073 CP->getAlignment(),
13074 CP->getOffset(), OpFlag);
13076 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13077 // With PIC, the address is actually $g + Offset.
13079 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13080 DAG.getNode(X86ISD::GlobalBaseReg,
13081 SDLoc(), getPointerTy()),
13088 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13089 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13091 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13092 // global base reg.
13093 unsigned char OpFlag = 0;
13094 unsigned WrapperKind = X86ISD::Wrapper;
13095 CodeModel::Model M = DAG.getTarget().getCodeModel();
13097 if (Subtarget->isPICStyleRIPRel() &&
13098 (M == CodeModel::Small || M == CodeModel::Kernel))
13099 WrapperKind = X86ISD::WrapperRIP;
13100 else if (Subtarget->isPICStyleGOT())
13101 OpFlag = X86II::MO_GOTOFF;
13102 else if (Subtarget->isPICStyleStubPIC())
13103 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13105 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13110 // With PIC, the address is actually $g + Offset.
13112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13113 DAG.getNode(X86ISD::GlobalBaseReg,
13114 SDLoc(), getPointerTy()),
13121 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13122 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13124 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13125 // global base reg.
13126 unsigned char OpFlag = 0;
13127 unsigned WrapperKind = X86ISD::Wrapper;
13128 CodeModel::Model M = DAG.getTarget().getCodeModel();
13130 if (Subtarget->isPICStyleRIPRel() &&
13131 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13132 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13133 OpFlag = X86II::MO_GOTPCREL;
13134 WrapperKind = X86ISD::WrapperRIP;
13135 } else if (Subtarget->isPICStyleGOT()) {
13136 OpFlag = X86II::MO_GOT;
13137 } else if (Subtarget->isPICStyleStubPIC()) {
13138 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13139 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13140 OpFlag = X86II::MO_DARWIN_NONLAZY;
13143 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13146 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13148 // With PIC, the address is actually $g + Offset.
13149 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13150 !Subtarget->is64Bit()) {
13151 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13152 DAG.getNode(X86ISD::GlobalBaseReg,
13153 SDLoc(), getPointerTy()),
13157 // For symbols that require a load from a stub to get the address, emit the
13159 if (isGlobalStubReference(OpFlag))
13160 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13161 MachinePointerInfo::getGOT(), false, false, false, 0);
13167 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13168 // Create the TargetBlockAddressAddress node.
13169 unsigned char OpFlags =
13170 Subtarget->ClassifyBlockAddressReference();
13171 CodeModel::Model M = DAG.getTarget().getCodeModel();
13172 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13173 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13175 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13178 if (Subtarget->isPICStyleRIPRel() &&
13179 (M == CodeModel::Small || M == CodeModel::Kernel))
13180 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13182 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13184 // With PIC, the address is actually $g + Offset.
13185 if (isGlobalRelativeToPICBase(OpFlags)) {
13186 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13187 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13195 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13196 int64_t Offset, SelectionDAG &DAG) const {
13197 // Create the TargetGlobalAddress node, folding in the constant
13198 // offset if it is legal.
13199 unsigned char OpFlags =
13200 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13201 CodeModel::Model M = DAG.getTarget().getCodeModel();
13203 if (OpFlags == X86II::MO_NO_FLAG &&
13204 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13205 // A direct static reference to a global.
13206 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13209 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13212 if (Subtarget->isPICStyleRIPRel() &&
13213 (M == CodeModel::Small || M == CodeModel::Kernel))
13214 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13216 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13218 // With PIC, the address is actually $g + Offset.
13219 if (isGlobalRelativeToPICBase(OpFlags)) {
13220 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13221 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13225 // For globals that require a load from a stub to get the address, emit the
13227 if (isGlobalStubReference(OpFlags))
13228 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13229 MachinePointerInfo::getGOT(), false, false, false, 0);
13231 // If there was a non-zero offset that we didn't fold, create an explicit
13232 // addition for it.
13234 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13235 DAG.getConstant(Offset, getPointerTy()));
13241 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13242 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13243 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13244 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13248 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13249 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13250 unsigned char OperandFlags, bool LocalDynamic = false) {
13251 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13252 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13254 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13255 GA->getValueType(0),
13259 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13263 SDValue Ops[] = { Chain, TGA, *InFlag };
13264 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13266 SDValue Ops[] = { Chain, TGA };
13267 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13270 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13271 MFI->setAdjustsStack(true);
13272 MFI->setHasCalls(true);
13274 SDValue Flag = Chain.getValue(1);
13275 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13278 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13280 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13283 SDLoc dl(GA); // ? function entry point might be better
13284 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13285 DAG.getNode(X86ISD::GlobalBaseReg,
13286 SDLoc(), PtrVT), InFlag);
13287 InFlag = Chain.getValue(1);
13289 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13292 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13294 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13296 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13297 X86::RAX, X86II::MO_TLSGD);
13300 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13306 // Get the start address of the TLS block for this module.
13307 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13308 .getInfo<X86MachineFunctionInfo>();
13309 MFI->incNumLocalDynamicTLSAccesses();
13313 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13314 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13317 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13318 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13319 InFlag = Chain.getValue(1);
13320 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13321 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13324 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13328 unsigned char OperandFlags = X86II::MO_DTPOFF;
13329 unsigned WrapperKind = X86ISD::Wrapper;
13330 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13331 GA->getValueType(0),
13332 GA->getOffset(), OperandFlags);
13333 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13335 // Add x@dtpoff with the base.
13336 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13339 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13340 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13341 const EVT PtrVT, TLSModel::Model model,
13342 bool is64Bit, bool isPIC) {
13345 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13346 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13347 is64Bit ? 257 : 256));
13349 SDValue ThreadPointer =
13350 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13351 MachinePointerInfo(Ptr), false, false, false, 0);
13353 unsigned char OperandFlags = 0;
13354 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13356 unsigned WrapperKind = X86ISD::Wrapper;
13357 if (model == TLSModel::LocalExec) {
13358 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13359 } else if (model == TLSModel::InitialExec) {
13361 OperandFlags = X86II::MO_GOTTPOFF;
13362 WrapperKind = X86ISD::WrapperRIP;
13364 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13367 llvm_unreachable("Unexpected model");
13370 // emit "addl x@ntpoff,%eax" (local exec)
13371 // or "addl x@indntpoff,%eax" (initial exec)
13372 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13374 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13375 GA->getOffset(), OperandFlags);
13376 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13378 if (model == TLSModel::InitialExec) {
13379 if (isPIC && !is64Bit) {
13380 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13381 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13385 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13386 MachinePointerInfo::getGOT(), false, false, false, 0);
13389 // The address of the thread local variable is the add of the thread
13390 // pointer with the offset of the variable.
13391 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13395 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13397 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13398 const GlobalValue *GV = GA->getGlobal();
13400 if (Subtarget->isTargetELF()) {
13401 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13404 case TLSModel::GeneralDynamic:
13405 if (Subtarget->is64Bit())
13406 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13407 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13408 case TLSModel::LocalDynamic:
13409 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13410 Subtarget->is64Bit());
13411 case TLSModel::InitialExec:
13412 case TLSModel::LocalExec:
13413 return LowerToTLSExecModel(
13414 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13415 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13417 llvm_unreachable("Unknown TLS model.");
13420 if (Subtarget->isTargetDarwin()) {
13421 // Darwin only has one model of TLS. Lower to that.
13422 unsigned char OpFlag = 0;
13423 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13424 X86ISD::WrapperRIP : X86ISD::Wrapper;
13426 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13427 // global base reg.
13428 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13429 !Subtarget->is64Bit();
13431 OpFlag = X86II::MO_TLVP_PIC_BASE;
13433 OpFlag = X86II::MO_TLVP;
13435 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13436 GA->getValueType(0),
13437 GA->getOffset(), OpFlag);
13438 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13440 // With PIC32, the address is actually $g + Offset.
13442 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13443 DAG.getNode(X86ISD::GlobalBaseReg,
13444 SDLoc(), getPointerTy()),
13447 // Lowering the machine isd will make sure everything is in the right
13449 SDValue Chain = DAG.getEntryNode();
13450 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13451 SDValue Args[] = { Chain, Offset };
13452 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13454 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13455 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13456 MFI->setAdjustsStack(true);
13458 // And our return value (tls address) is in the standard call return value
13460 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13461 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13462 Chain.getValue(1));
13465 if (Subtarget->isTargetKnownWindowsMSVC() ||
13466 Subtarget->isTargetWindowsGNU()) {
13467 // Just use the implicit TLS architecture
13468 // Need to generate someting similar to:
13469 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13471 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13472 // mov rcx, qword [rdx+rcx*8]
13473 // mov eax, .tls$:tlsvar
13474 // [rax+rcx] contains the address
13475 // Windows 64bit: gs:0x58
13476 // Windows 32bit: fs:__tls_array
13479 SDValue Chain = DAG.getEntryNode();
13481 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13482 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13483 // use its literal value of 0x2C.
13484 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13485 ? Type::getInt8PtrTy(*DAG.getContext(),
13487 : Type::getInt32PtrTy(*DAG.getContext(),
13491 Subtarget->is64Bit()
13492 ? DAG.getIntPtrConstant(0x58)
13493 : (Subtarget->isTargetWindowsGNU()
13494 ? DAG.getIntPtrConstant(0x2C)
13495 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13497 SDValue ThreadPointer =
13498 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13499 MachinePointerInfo(Ptr), false, false, false, 0);
13501 // Load the _tls_index variable
13502 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13503 if (Subtarget->is64Bit())
13504 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13505 IDX, MachinePointerInfo(), MVT::i32,
13506 false, false, false, 0);
13508 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13509 false, false, false, 0);
13511 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13513 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13515 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13516 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13517 false, false, false, 0);
13519 // Get the offset of start of .tls section
13520 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13521 GA->getValueType(0),
13522 GA->getOffset(), X86II::MO_SECREL);
13523 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13525 // The address of the thread local variable is the add of the thread
13526 // pointer with the offset of the variable.
13527 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13530 llvm_unreachable("TLS not implemented for this target.");
13533 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13534 /// and take a 2 x i32 value to shift plus a shift amount.
13535 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13536 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13537 MVT VT = Op.getSimpleValueType();
13538 unsigned VTBits = VT.getSizeInBits();
13540 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13541 SDValue ShOpLo = Op.getOperand(0);
13542 SDValue ShOpHi = Op.getOperand(1);
13543 SDValue ShAmt = Op.getOperand(2);
13544 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13545 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13547 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13548 DAG.getConstant(VTBits - 1, MVT::i8));
13549 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13550 DAG.getConstant(VTBits - 1, MVT::i8))
13551 : DAG.getConstant(0, VT);
13553 SDValue Tmp2, Tmp3;
13554 if (Op.getOpcode() == ISD::SHL_PARTS) {
13555 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13556 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13558 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13559 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13562 // If the shift amount is larger or equal than the width of a part we can't
13563 // rely on the results of shld/shrd. Insert a test and select the appropriate
13564 // values for large shift amounts.
13565 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13566 DAG.getConstant(VTBits, MVT::i8));
13567 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13568 AndNode, DAG.getConstant(0, MVT::i8));
13571 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13572 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13573 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13575 if (Op.getOpcode() == ISD::SHL_PARTS) {
13576 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13577 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13579 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13580 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13583 SDValue Ops[2] = { Lo, Hi };
13584 return DAG.getMergeValues(Ops, dl);
13587 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13588 SelectionDAG &DAG) const {
13589 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13592 if (SrcVT.isVector()) {
13593 if (SrcVT.getVectorElementType() == MVT::i1) {
13594 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13595 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13596 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13597 Op.getOperand(0)));
13602 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13603 "Unknown SINT_TO_FP to lower!");
13605 // These are really Legal; return the operand so the caller accepts it as
13607 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13609 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13610 Subtarget->is64Bit()) {
13614 unsigned Size = SrcVT.getSizeInBits()/8;
13615 MachineFunction &MF = DAG.getMachineFunction();
13616 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13617 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13618 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13620 MachinePointerInfo::getFixedStack(SSFI),
13622 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13625 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13627 SelectionDAG &DAG) const {
13631 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13633 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13635 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13637 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13639 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13640 MachineMemOperand *MMO;
13642 int SSFI = FI->getIndex();
13644 DAG.getMachineFunction()
13645 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13646 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13648 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13649 StackSlot = StackSlot.getOperand(1);
13651 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13652 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13654 Tys, Ops, SrcVT, MMO);
13657 Chain = Result.getValue(1);
13658 SDValue InFlag = Result.getValue(2);
13660 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13661 // shouldn't be necessary except that RFP cannot be live across
13662 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13663 MachineFunction &MF = DAG.getMachineFunction();
13664 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13665 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13666 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13667 Tys = DAG.getVTList(MVT::Other);
13669 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13671 MachineMemOperand *MMO =
13672 DAG.getMachineFunction()
13673 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13674 MachineMemOperand::MOStore, SSFISize, SSFISize);
13676 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13677 Ops, Op.getValueType(), MMO);
13678 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13679 MachinePointerInfo::getFixedStack(SSFI),
13680 false, false, false, 0);
13686 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13687 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13688 SelectionDAG &DAG) const {
13689 // This algorithm is not obvious. Here it is what we're trying to output:
13692 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13693 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13695 haddpd %xmm0, %xmm0
13697 pshufd $0x4e, %xmm0, %xmm1
13703 LLVMContext *Context = DAG.getContext();
13705 // Build some magic constants.
13706 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13707 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13708 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13710 SmallVector<Constant*,2> CV1;
13712 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13713 APInt(64, 0x4330000000000000ULL))));
13715 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13716 APInt(64, 0x4530000000000000ULL))));
13717 Constant *C1 = ConstantVector::get(CV1);
13718 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13720 // Load the 64-bit value into an XMM register.
13721 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13723 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13724 MachinePointerInfo::getConstantPool(),
13725 false, false, false, 16);
13726 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13727 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13730 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13731 MachinePointerInfo::getConstantPool(),
13732 false, false, false, 16);
13733 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13734 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13737 if (Subtarget->hasSSE3()) {
13738 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13739 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13741 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13742 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13744 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13745 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13749 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13750 DAG.getIntPtrConstant(0));
13753 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13754 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13755 SelectionDAG &DAG) const {
13757 // FP constant to bias correct the final result.
13758 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13761 // Load the 32-bit value into an XMM register.
13762 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13765 // Zero out the upper parts of the register.
13766 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13768 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13769 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13770 DAG.getIntPtrConstant(0));
13772 // Or the load with the bias.
13773 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13774 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13775 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13776 MVT::v2f64, Load)),
13777 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13778 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13779 MVT::v2f64, Bias)));
13780 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13781 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13782 DAG.getIntPtrConstant(0));
13784 // Subtract the bias.
13785 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13787 // Handle final rounding.
13788 EVT DestVT = Op.getValueType();
13790 if (DestVT.bitsLT(MVT::f64))
13791 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13792 DAG.getIntPtrConstant(0));
13793 if (DestVT.bitsGT(MVT::f64))
13794 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13796 // Handle final rounding.
13800 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13801 const X86Subtarget &Subtarget) {
13802 // The algorithm is the following:
13803 // #ifdef __SSE4_1__
13804 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13805 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13806 // (uint4) 0x53000000, 0xaa);
13808 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13809 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13811 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13812 // return (float4) lo + fhi;
13815 SDValue V = Op->getOperand(0);
13816 EVT VecIntVT = V.getValueType();
13817 bool Is128 = VecIntVT == MVT::v4i32;
13818 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13819 // If we convert to something else than the supported type, e.g., to v4f64,
13821 if (VecFloatVT != Op->getValueType(0))
13824 unsigned NumElts = VecIntVT.getVectorNumElements();
13825 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13826 "Unsupported custom type");
13827 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13829 // In the #idef/#else code, we have in common:
13830 // - The vector of constants:
13836 // Create the splat vector for 0x4b000000.
13837 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13838 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13839 CstLow, CstLow, CstLow, CstLow};
13840 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13841 makeArrayRef(&CstLowArray[0], NumElts));
13842 // Create the splat vector for 0x53000000.
13843 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13844 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13845 CstHigh, CstHigh, CstHigh, CstHigh};
13846 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13847 makeArrayRef(&CstHighArray[0], NumElts));
13849 // Create the right shift.
13850 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13851 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13852 CstShift, CstShift, CstShift, CstShift};
13853 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13854 makeArrayRef(&CstShiftArray[0], NumElts));
13855 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13858 if (Subtarget.hasSSE41()) {
13859 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13860 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13861 SDValue VecCstLowBitcast =
13862 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13863 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13864 // Low will be bitcasted right away, so do not bother bitcasting back to its
13866 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13867 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13868 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13869 // (uint4) 0x53000000, 0xaa);
13870 SDValue VecCstHighBitcast =
13871 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13872 SDValue VecShiftBitcast =
13873 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13874 // High will be bitcasted right away, so do not bother bitcasting back to
13875 // its original type.
13876 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13877 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13879 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13880 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13881 CstMask, CstMask, CstMask);
13882 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13883 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13884 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13886 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13887 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13890 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13891 SDValue CstFAdd = DAG.getConstantFP(
13892 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13893 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13894 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13895 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13896 makeArrayRef(&CstFAddArray[0], NumElts));
13898 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13899 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13901 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13902 // return (float4) lo + fhi;
13903 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13904 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13907 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13908 SelectionDAG &DAG) const {
13909 SDValue N0 = Op.getOperand(0);
13910 MVT SVT = N0.getSimpleValueType();
13913 switch (SVT.SimpleTy) {
13915 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13920 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13921 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13922 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13926 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13928 llvm_unreachable(nullptr);
13931 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13932 SelectionDAG &DAG) const {
13933 SDValue N0 = Op.getOperand(0);
13936 if (Op.getValueType().isVector())
13937 return lowerUINT_TO_FP_vec(Op, DAG);
13939 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13940 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13941 // the optimization here.
13942 if (DAG.SignBitIsZero(N0))
13943 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13945 MVT SrcVT = N0.getSimpleValueType();
13946 MVT DstVT = Op.getSimpleValueType();
13947 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13948 return LowerUINT_TO_FP_i64(Op, DAG);
13949 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13950 return LowerUINT_TO_FP_i32(Op, DAG);
13951 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13954 // Make a 64-bit buffer, and use it to build an FILD.
13955 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13956 if (SrcVT == MVT::i32) {
13957 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13958 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13959 getPointerTy(), StackSlot, WordOff);
13960 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13961 StackSlot, MachinePointerInfo(),
13963 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13964 OffsetSlot, MachinePointerInfo(),
13966 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13970 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13971 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13972 StackSlot, MachinePointerInfo(),
13974 // For i64 source, we need to add the appropriate power of 2 if the input
13975 // was negative. This is the same as the optimization in
13976 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13977 // we must be careful to do the computation in x87 extended precision, not
13978 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13979 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13980 MachineMemOperand *MMO =
13981 DAG.getMachineFunction()
13982 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13983 MachineMemOperand::MOLoad, 8, 8);
13985 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13986 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13987 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13990 APInt FF(32, 0x5F800000ULL);
13992 // Check whether the sign bit is set.
13993 SDValue SignSet = DAG.getSetCC(dl,
13994 getSetCCResultType(*DAG.getContext(), MVT::i64),
13995 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13998 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13999 SDValue FudgePtr = DAG.getConstantPool(
14000 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14003 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14004 SDValue Zero = DAG.getIntPtrConstant(0);
14005 SDValue Four = DAG.getIntPtrConstant(4);
14006 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14008 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14010 // Load the value out, extending it from f32 to f80.
14011 // FIXME: Avoid the extend by constructing the right constant pool?
14012 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14013 FudgePtr, MachinePointerInfo::getConstantPool(),
14014 MVT::f32, false, false, false, 4);
14015 // Extend everything to 80 bits to force it to be done on x87.
14016 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14017 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14020 std::pair<SDValue,SDValue>
14021 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14022 bool IsSigned, bool IsReplace) const {
14025 EVT DstTy = Op.getValueType();
14027 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14028 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14032 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14033 DstTy.getSimpleVT() >= MVT::i16 &&
14034 "Unknown FP_TO_INT to lower!");
14036 // These are really Legal.
14037 if (DstTy == MVT::i32 &&
14038 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14039 return std::make_pair(SDValue(), SDValue());
14040 if (Subtarget->is64Bit() &&
14041 DstTy == MVT::i64 &&
14042 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14043 return std::make_pair(SDValue(), SDValue());
14045 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14046 // stack slot, or into the FTOL runtime function.
14047 MachineFunction &MF = DAG.getMachineFunction();
14048 unsigned MemSize = DstTy.getSizeInBits()/8;
14049 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14050 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14053 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14054 Opc = X86ISD::WIN_FTOL;
14056 switch (DstTy.getSimpleVT().SimpleTy) {
14057 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14058 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14059 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14060 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14063 SDValue Chain = DAG.getEntryNode();
14064 SDValue Value = Op.getOperand(0);
14065 EVT TheVT = Op.getOperand(0).getValueType();
14066 // FIXME This causes a redundant load/store if the SSE-class value is already
14067 // in memory, such as if it is on the callstack.
14068 if (isScalarFPTypeInSSEReg(TheVT)) {
14069 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14070 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14071 MachinePointerInfo::getFixedStack(SSFI),
14073 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14075 Chain, StackSlot, DAG.getValueType(TheVT)
14078 MachineMemOperand *MMO =
14079 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14080 MachineMemOperand::MOLoad, MemSize, MemSize);
14081 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14082 Chain = Value.getValue(1);
14083 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14084 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14087 MachineMemOperand *MMO =
14088 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14089 MachineMemOperand::MOStore, MemSize, MemSize);
14091 if (Opc != X86ISD::WIN_FTOL) {
14092 // Build the FP_TO_INT*_IN_MEM
14093 SDValue Ops[] = { Chain, Value, StackSlot };
14094 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14096 return std::make_pair(FIST, StackSlot);
14098 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14099 DAG.getVTList(MVT::Other, MVT::Glue),
14101 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14102 MVT::i32, ftol.getValue(1));
14103 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14104 MVT::i32, eax.getValue(2));
14105 SDValue Ops[] = { eax, edx };
14106 SDValue pair = IsReplace
14107 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14108 : DAG.getMergeValues(Ops, DL);
14109 return std::make_pair(pair, SDValue());
14113 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14114 const X86Subtarget *Subtarget) {
14115 MVT VT = Op->getSimpleValueType(0);
14116 SDValue In = Op->getOperand(0);
14117 MVT InVT = In.getSimpleValueType();
14120 // Optimize vectors in AVX mode:
14123 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14124 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14125 // Concat upper and lower parts.
14128 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14129 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14130 // Concat upper and lower parts.
14133 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14134 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14135 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14138 if (Subtarget->hasInt256())
14139 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14141 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14142 SDValue Undef = DAG.getUNDEF(InVT);
14143 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14144 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14145 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14147 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14148 VT.getVectorNumElements()/2);
14150 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14151 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14156 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14157 SelectionDAG &DAG) {
14158 MVT VT = Op->getSimpleValueType(0);
14159 SDValue In = Op->getOperand(0);
14160 MVT InVT = In.getSimpleValueType();
14162 unsigned int NumElts = VT.getVectorNumElements();
14163 if (NumElts != 8 && NumElts != 16)
14166 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14167 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14169 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14171 // Now we have only mask extension
14172 assert(InVT.getVectorElementType() == MVT::i1);
14173 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14174 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14175 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14176 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14177 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14178 MachinePointerInfo::getConstantPool(),
14179 false, false, false, Alignment);
14181 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14182 if (VT.is512BitVector())
14184 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14187 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14188 SelectionDAG &DAG) {
14189 if (Subtarget->hasFp256()) {
14190 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14198 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14199 SelectionDAG &DAG) {
14201 MVT VT = Op.getSimpleValueType();
14202 SDValue In = Op.getOperand(0);
14203 MVT SVT = In.getSimpleValueType();
14205 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14206 return LowerZERO_EXTEND_AVX512(Op, DAG);
14208 if (Subtarget->hasFp256()) {
14209 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14214 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14215 VT.getVectorNumElements() != SVT.getVectorNumElements());
14219 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14221 MVT VT = Op.getSimpleValueType();
14222 SDValue In = Op.getOperand(0);
14223 MVT InVT = In.getSimpleValueType();
14225 if (VT == MVT::i1) {
14226 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14227 "Invalid scalar TRUNCATE operation");
14228 if (InVT.getSizeInBits() >= 32)
14230 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14231 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14233 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14234 "Invalid TRUNCATE operation");
14236 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14237 if (VT.getVectorElementType().getSizeInBits() >=8)
14238 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14240 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14241 unsigned NumElts = InVT.getVectorNumElements();
14242 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14243 if (InVT.getSizeInBits() < 512) {
14244 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14245 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14249 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14250 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14251 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14252 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14253 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14254 MachinePointerInfo::getConstantPool(),
14255 false, false, false, Alignment);
14256 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14257 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14258 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14261 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14262 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14263 if (Subtarget->hasInt256()) {
14264 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14265 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14266 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14268 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14269 DAG.getIntPtrConstant(0));
14272 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14273 DAG.getIntPtrConstant(0));
14274 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14275 DAG.getIntPtrConstant(2));
14276 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14277 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14278 static const int ShufMask[] = {0, 2, 4, 6};
14279 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14282 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14283 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14284 if (Subtarget->hasInt256()) {
14285 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14287 SmallVector<SDValue,32> pshufbMask;
14288 for (unsigned i = 0; i < 2; ++i) {
14289 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14290 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14291 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14292 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14293 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14294 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14295 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14296 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14297 for (unsigned j = 0; j < 8; ++j)
14298 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14300 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14301 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14302 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14304 static const int ShufMask[] = {0, 2, -1, -1};
14305 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14307 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14308 DAG.getIntPtrConstant(0));
14309 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14312 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14313 DAG.getIntPtrConstant(0));
14315 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14316 DAG.getIntPtrConstant(4));
14318 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14319 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14321 // The PSHUFB mask:
14322 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14323 -1, -1, -1, -1, -1, -1, -1, -1};
14325 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14326 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14327 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14329 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14330 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14332 // The MOVLHPS Mask:
14333 static const int ShufMask2[] = {0, 1, 4, 5};
14334 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14335 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14338 // Handle truncation of V256 to V128 using shuffles.
14339 if (!VT.is128BitVector() || !InVT.is256BitVector())
14342 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14344 unsigned NumElems = VT.getVectorNumElements();
14345 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14347 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14348 // Prepare truncation shuffle mask
14349 for (unsigned i = 0; i != NumElems; ++i)
14350 MaskVec[i] = i * 2;
14351 SDValue V = DAG.getVectorShuffle(NVT, DL,
14352 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14353 DAG.getUNDEF(NVT), &MaskVec[0]);
14354 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14355 DAG.getIntPtrConstant(0));
14358 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14359 SelectionDAG &DAG) const {
14360 assert(!Op.getSimpleValueType().isVector());
14362 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14363 /*IsSigned=*/ true, /*IsReplace=*/ false);
14364 SDValue FIST = Vals.first, StackSlot = Vals.second;
14365 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14366 if (!FIST.getNode()) return Op;
14368 if (StackSlot.getNode())
14369 // Load the result.
14370 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14371 FIST, StackSlot, MachinePointerInfo(),
14372 false, false, false, 0);
14374 // The node is the result.
14378 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14379 SelectionDAG &DAG) const {
14380 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14381 /*IsSigned=*/ false, /*IsReplace=*/ false);
14382 SDValue FIST = Vals.first, StackSlot = Vals.second;
14383 assert(FIST.getNode() && "Unexpected failure");
14385 if (StackSlot.getNode())
14386 // Load the result.
14387 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14388 FIST, StackSlot, MachinePointerInfo(),
14389 false, false, false, 0);
14391 // The node is the result.
14395 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14397 MVT VT = Op.getSimpleValueType();
14398 SDValue In = Op.getOperand(0);
14399 MVT SVT = In.getSimpleValueType();
14401 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14403 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14404 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14405 In, DAG.getUNDEF(SVT)));
14408 /// The only differences between FABS and FNEG are the mask and the logic op.
14409 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14410 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14411 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14412 "Wrong opcode for lowering FABS or FNEG.");
14414 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14416 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14417 // into an FNABS. We'll lower the FABS after that if it is still in use.
14419 for (SDNode *User : Op->uses())
14420 if (User->getOpcode() == ISD::FNEG)
14423 SDValue Op0 = Op.getOperand(0);
14424 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14427 MVT VT = Op.getSimpleValueType();
14428 // Assume scalar op for initialization; update for vector if needed.
14429 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14430 // generate a 16-byte vector constant and logic op even for the scalar case.
14431 // Using a 16-byte mask allows folding the load of the mask with
14432 // the logic op, so it can save (~4 bytes) on code size.
14434 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14435 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14436 // decide if we should generate a 16-byte constant mask when we only need 4 or
14437 // 8 bytes for the scalar case.
14438 if (VT.isVector()) {
14439 EltVT = VT.getVectorElementType();
14440 NumElts = VT.getVectorNumElements();
14443 unsigned EltBits = EltVT.getSizeInBits();
14444 LLVMContext *Context = DAG.getContext();
14445 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14447 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14448 Constant *C = ConstantInt::get(*Context, MaskElt);
14449 C = ConstantVector::getSplat(NumElts, C);
14450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14451 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14452 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14453 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14454 MachinePointerInfo::getConstantPool(),
14455 false, false, false, Alignment);
14457 if (VT.isVector()) {
14458 // For a vector, cast operands to a vector type, perform the logic op,
14459 // and cast the result back to the original value type.
14460 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14461 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14462 SDValue Operand = IsFNABS ?
14463 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14464 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14465 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14466 return DAG.getNode(ISD::BITCAST, dl, VT,
14467 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14470 // If not vector, then scalar.
14471 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14472 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14473 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14476 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14478 LLVMContext *Context = DAG.getContext();
14479 SDValue Op0 = Op.getOperand(0);
14480 SDValue Op1 = Op.getOperand(1);
14482 MVT VT = Op.getSimpleValueType();
14483 MVT SrcVT = Op1.getSimpleValueType();
14485 // If second operand is smaller, extend it first.
14486 if (SrcVT.bitsLT(VT)) {
14487 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14490 // And if it is bigger, shrink it first.
14491 if (SrcVT.bitsGT(VT)) {
14492 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14496 // At this point the operands and the result should have the same
14497 // type, and that won't be f80 since that is not custom lowered.
14499 const fltSemantics &Sem =
14500 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14501 const unsigned SizeInBits = VT.getSizeInBits();
14503 SmallVector<Constant *, 4> CV(
14504 VT == MVT::f64 ? 2 : 4,
14505 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14507 // First, clear all bits but the sign bit from the second operand (sign).
14508 CV[0] = ConstantFP::get(*Context,
14509 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14510 Constant *C = ConstantVector::get(CV);
14511 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14512 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14513 MachinePointerInfo::getConstantPool(),
14514 false, false, false, 16);
14515 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14517 // Next, clear the sign bit from the first operand (magnitude).
14518 CV[0] = ConstantFP::get(
14519 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14520 C = ConstantVector::get(CV);
14521 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14522 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14523 MachinePointerInfo::getConstantPool(),
14524 false, false, false, 16);
14525 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14527 // OR the magnitude value with the sign bit.
14528 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14531 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14532 SDValue N0 = Op.getOperand(0);
14534 MVT VT = Op.getSimpleValueType();
14536 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14537 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14538 DAG.getConstant(1, VT));
14539 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14542 // Check whether an OR'd tree is PTEST-able.
14543 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14544 SelectionDAG &DAG) {
14545 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14547 if (!Subtarget->hasSSE41())
14550 if (!Op->hasOneUse())
14553 SDNode *N = Op.getNode();
14556 SmallVector<SDValue, 8> Opnds;
14557 DenseMap<SDValue, unsigned> VecInMap;
14558 SmallVector<SDValue, 8> VecIns;
14559 EVT VT = MVT::Other;
14561 // Recognize a special case where a vector is casted into wide integer to
14563 Opnds.push_back(N->getOperand(0));
14564 Opnds.push_back(N->getOperand(1));
14566 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14567 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14568 // BFS traverse all OR'd operands.
14569 if (I->getOpcode() == ISD::OR) {
14570 Opnds.push_back(I->getOperand(0));
14571 Opnds.push_back(I->getOperand(1));
14572 // Re-evaluate the number of nodes to be traversed.
14573 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14577 // Quit if a non-EXTRACT_VECTOR_ELT
14578 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14581 // Quit if without a constant index.
14582 SDValue Idx = I->getOperand(1);
14583 if (!isa<ConstantSDNode>(Idx))
14586 SDValue ExtractedFromVec = I->getOperand(0);
14587 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14588 if (M == VecInMap.end()) {
14589 VT = ExtractedFromVec.getValueType();
14590 // Quit if not 128/256-bit vector.
14591 if (!VT.is128BitVector() && !VT.is256BitVector())
14593 // Quit if not the same type.
14594 if (VecInMap.begin() != VecInMap.end() &&
14595 VT != VecInMap.begin()->first.getValueType())
14597 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14598 VecIns.push_back(ExtractedFromVec);
14600 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14603 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14604 "Not extracted from 128-/256-bit vector.");
14606 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14608 for (DenseMap<SDValue, unsigned>::const_iterator
14609 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14610 // Quit if not all elements are used.
14611 if (I->second != FullMask)
14615 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14617 // Cast all vectors into TestVT for PTEST.
14618 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14619 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14621 // If more than one full vectors are evaluated, OR them first before PTEST.
14622 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14623 // Each iteration will OR 2 nodes and append the result until there is only
14624 // 1 node left, i.e. the final OR'd value of all vectors.
14625 SDValue LHS = VecIns[Slot];
14626 SDValue RHS = VecIns[Slot + 1];
14627 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14630 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14631 VecIns.back(), VecIns.back());
14634 /// \brief return true if \c Op has a use that doesn't just read flags.
14635 static bool hasNonFlagsUse(SDValue Op) {
14636 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14638 SDNode *User = *UI;
14639 unsigned UOpNo = UI.getOperandNo();
14640 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14641 // Look pass truncate.
14642 UOpNo = User->use_begin().getOperandNo();
14643 User = *User->use_begin();
14646 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14647 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14653 /// Emit nodes that will be selected as "test Op0,Op0", or something
14655 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14656 SelectionDAG &DAG) const {
14657 if (Op.getValueType() == MVT::i1)
14658 // KORTEST instruction should be selected
14659 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14660 DAG.getConstant(0, Op.getValueType()));
14662 // CF and OF aren't always set the way we want. Determine which
14663 // of these we need.
14664 bool NeedCF = false;
14665 bool NeedOF = false;
14668 case X86::COND_A: case X86::COND_AE:
14669 case X86::COND_B: case X86::COND_BE:
14672 case X86::COND_G: case X86::COND_GE:
14673 case X86::COND_L: case X86::COND_LE:
14674 case X86::COND_O: case X86::COND_NO: {
14675 // Check if we really need to set the
14676 // Overflow flag. If NoSignedWrap is present
14677 // that is not actually needed.
14678 switch (Op->getOpcode()) {
14683 const BinaryWithFlagsSDNode *BinNode =
14684 cast<BinaryWithFlagsSDNode>(Op.getNode());
14685 if (BinNode->hasNoSignedWrap())
14695 // See if we can use the EFLAGS value from the operand instead of
14696 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14697 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14698 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14699 // Emit a CMP with 0, which is the TEST pattern.
14700 //if (Op.getValueType() == MVT::i1)
14701 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14702 // DAG.getConstant(0, MVT::i1));
14703 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14704 DAG.getConstant(0, Op.getValueType()));
14706 unsigned Opcode = 0;
14707 unsigned NumOperands = 0;
14709 // Truncate operations may prevent the merge of the SETCC instruction
14710 // and the arithmetic instruction before it. Attempt to truncate the operands
14711 // of the arithmetic instruction and use a reduced bit-width instruction.
14712 bool NeedTruncation = false;
14713 SDValue ArithOp = Op;
14714 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14715 SDValue Arith = Op->getOperand(0);
14716 // Both the trunc and the arithmetic op need to have one user each.
14717 if (Arith->hasOneUse())
14718 switch (Arith.getOpcode()) {
14725 NeedTruncation = true;
14731 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14732 // which may be the result of a CAST. We use the variable 'Op', which is the
14733 // non-casted variable when we check for possible users.
14734 switch (ArithOp.getOpcode()) {
14736 // Due to an isel shortcoming, be conservative if this add is likely to be
14737 // selected as part of a load-modify-store instruction. When the root node
14738 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14739 // uses of other nodes in the match, such as the ADD in this case. This
14740 // leads to the ADD being left around and reselected, with the result being
14741 // two adds in the output. Alas, even if none our users are stores, that
14742 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14743 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14744 // climbing the DAG back to the root, and it doesn't seem to be worth the
14746 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14747 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14748 if (UI->getOpcode() != ISD::CopyToReg &&
14749 UI->getOpcode() != ISD::SETCC &&
14750 UI->getOpcode() != ISD::STORE)
14753 if (ConstantSDNode *C =
14754 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14755 // An add of one will be selected as an INC.
14756 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14757 Opcode = X86ISD::INC;
14762 // An add of negative one (subtract of one) will be selected as a DEC.
14763 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14764 Opcode = X86ISD::DEC;
14770 // Otherwise use a regular EFLAGS-setting add.
14771 Opcode = X86ISD::ADD;
14776 // If we have a constant logical shift that's only used in a comparison
14777 // against zero turn it into an equivalent AND. This allows turning it into
14778 // a TEST instruction later.
14779 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14780 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14781 EVT VT = Op.getValueType();
14782 unsigned BitWidth = VT.getSizeInBits();
14783 unsigned ShAmt = Op->getConstantOperandVal(1);
14784 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14786 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14787 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14788 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14789 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14791 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14792 DAG.getConstant(Mask, VT));
14793 DAG.ReplaceAllUsesWith(Op, New);
14799 // If the primary and result isn't used, don't bother using X86ISD::AND,
14800 // because a TEST instruction will be better.
14801 if (!hasNonFlagsUse(Op))
14807 // Due to the ISEL shortcoming noted above, be conservative if this op is
14808 // likely to be selected as part of a load-modify-store instruction.
14809 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14810 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14811 if (UI->getOpcode() == ISD::STORE)
14814 // Otherwise use a regular EFLAGS-setting instruction.
14815 switch (ArithOp.getOpcode()) {
14816 default: llvm_unreachable("unexpected operator!");
14817 case ISD::SUB: Opcode = X86ISD::SUB; break;
14818 case ISD::XOR: Opcode = X86ISD::XOR; break;
14819 case ISD::AND: Opcode = X86ISD::AND; break;
14821 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14822 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14823 if (EFLAGS.getNode())
14826 Opcode = X86ISD::OR;
14840 return SDValue(Op.getNode(), 1);
14846 // If we found that truncation is beneficial, perform the truncation and
14848 if (NeedTruncation) {
14849 EVT VT = Op.getValueType();
14850 SDValue WideVal = Op->getOperand(0);
14851 EVT WideVT = WideVal.getValueType();
14852 unsigned ConvertedOp = 0;
14853 // Use a target machine opcode to prevent further DAGCombine
14854 // optimizations that may separate the arithmetic operations
14855 // from the setcc node.
14856 switch (WideVal.getOpcode()) {
14858 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14859 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14860 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14861 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14862 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14866 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14867 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14868 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14869 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14870 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14876 // Emit a CMP with 0, which is the TEST pattern.
14877 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14878 DAG.getConstant(0, Op.getValueType()));
14880 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14881 SmallVector<SDValue, 4> Ops;
14882 for (unsigned i = 0; i != NumOperands; ++i)
14883 Ops.push_back(Op.getOperand(i));
14885 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14886 DAG.ReplaceAllUsesWith(Op, New);
14887 return SDValue(New.getNode(), 1);
14890 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14892 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14893 SDLoc dl, SelectionDAG &DAG) const {
14894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14895 if (C->getAPIntValue() == 0)
14896 return EmitTest(Op0, X86CC, dl, DAG);
14898 if (Op0.getValueType() == MVT::i1)
14899 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14902 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14903 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14904 // Do the comparison at i32 if it's smaller, besides the Atom case.
14905 // This avoids subregister aliasing issues. Keep the smaller reference
14906 // if we're optimizing for size, however, as that'll allow better folding
14907 // of memory operations.
14908 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14909 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14910 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14911 !Subtarget->isAtom()) {
14912 unsigned ExtendOp =
14913 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14914 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14915 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14917 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14918 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14919 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14921 return SDValue(Sub.getNode(), 1);
14923 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14926 /// Convert a comparison if required by the subtarget.
14927 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14928 SelectionDAG &DAG) const {
14929 // If the subtarget does not support the FUCOMI instruction, floating-point
14930 // comparisons have to be converted.
14931 if (Subtarget->hasCMov() ||
14932 Cmp.getOpcode() != X86ISD::CMP ||
14933 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14934 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14937 // The instruction selector will select an FUCOM instruction instead of
14938 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14939 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14940 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14942 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14943 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14944 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14945 DAG.getConstant(8, MVT::i8));
14946 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14947 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14950 /// The minimum architected relative accuracy is 2^-12. We need one
14951 /// Newton-Raphson step to have a good float result (24 bits of precision).
14952 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14953 DAGCombinerInfo &DCI,
14954 unsigned &RefinementSteps,
14955 bool &UseOneConstNR) const {
14956 // FIXME: We should use instruction latency models to calculate the cost of
14957 // each potential sequence, but this is very hard to do reliably because
14958 // at least Intel's Core* chips have variable timing based on the number of
14959 // significant digits in the divisor and/or sqrt operand.
14960 if (!Subtarget->useSqrtEst())
14963 EVT VT = Op.getValueType();
14965 // SSE1 has rsqrtss and rsqrtps.
14966 // TODO: Add support for AVX512 (v16f32).
14967 // It is likely not profitable to do this for f64 because a double-precision
14968 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14969 // instructions: convert to single, rsqrtss, convert back to double, refine
14970 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14971 // along with FMA, this could be a throughput win.
14972 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14973 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14974 RefinementSteps = 1;
14975 UseOneConstNR = false;
14976 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14981 /// The minimum architected relative accuracy is 2^-12. We need one
14982 /// Newton-Raphson step to have a good float result (24 bits of precision).
14983 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14984 DAGCombinerInfo &DCI,
14985 unsigned &RefinementSteps) const {
14986 // FIXME: We should use instruction latency models to calculate the cost of
14987 // each potential sequence, but this is very hard to do reliably because
14988 // at least Intel's Core* chips have variable timing based on the number of
14989 // significant digits in the divisor.
14990 if (!Subtarget->useReciprocalEst())
14993 EVT VT = Op.getValueType();
14995 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14996 // TODO: Add support for AVX512 (v16f32).
14997 // It is likely not profitable to do this for f64 because a double-precision
14998 // reciprocal estimate with refinement on x86 prior to FMA requires
14999 // 15 instructions: convert to single, rcpss, convert back to double, refine
15000 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15001 // along with FMA, this could be a throughput win.
15002 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15003 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15004 RefinementSteps = ReciprocalEstimateRefinementSteps;
15005 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15010 static bool isAllOnes(SDValue V) {
15011 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15012 return C && C->isAllOnesValue();
15015 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15016 /// if it's possible.
15017 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15018 SDLoc dl, SelectionDAG &DAG) const {
15019 SDValue Op0 = And.getOperand(0);
15020 SDValue Op1 = And.getOperand(1);
15021 if (Op0.getOpcode() == ISD::TRUNCATE)
15022 Op0 = Op0.getOperand(0);
15023 if (Op1.getOpcode() == ISD::TRUNCATE)
15024 Op1 = Op1.getOperand(0);
15027 if (Op1.getOpcode() == ISD::SHL)
15028 std::swap(Op0, Op1);
15029 if (Op0.getOpcode() == ISD::SHL) {
15030 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15031 if (And00C->getZExtValue() == 1) {
15032 // If we looked past a truncate, check that it's only truncating away
15034 unsigned BitWidth = Op0.getValueSizeInBits();
15035 unsigned AndBitWidth = And.getValueSizeInBits();
15036 if (BitWidth > AndBitWidth) {
15038 DAG.computeKnownBits(Op0, Zeros, Ones);
15039 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15043 RHS = Op0.getOperand(1);
15045 } else if (Op1.getOpcode() == ISD::Constant) {
15046 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15047 uint64_t AndRHSVal = AndRHS->getZExtValue();
15048 SDValue AndLHS = Op0;
15050 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15051 LHS = AndLHS.getOperand(0);
15052 RHS = AndLHS.getOperand(1);
15055 // Use BT if the immediate can't be encoded in a TEST instruction.
15056 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15058 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15062 if (LHS.getNode()) {
15063 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15064 // instruction. Since the shift amount is in-range-or-undefined, we know
15065 // that doing a bittest on the i32 value is ok. We extend to i32 because
15066 // the encoding for the i16 version is larger than the i32 version.
15067 // Also promote i16 to i32 for performance / code size reason.
15068 if (LHS.getValueType() == MVT::i8 ||
15069 LHS.getValueType() == MVT::i16)
15070 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15072 // If the operand types disagree, extend the shift amount to match. Since
15073 // BT ignores high bits (like shifts) we can use anyextend.
15074 if (LHS.getValueType() != RHS.getValueType())
15075 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15077 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15078 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15079 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15080 DAG.getConstant(Cond, MVT::i8), BT);
15086 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15088 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15093 // SSE Condition code mapping:
15102 switch (SetCCOpcode) {
15103 default: llvm_unreachable("Unexpected SETCC condition");
15105 case ISD::SETEQ: SSECC = 0; break;
15107 case ISD::SETGT: Swap = true; // Fallthrough
15109 case ISD::SETOLT: SSECC = 1; break;
15111 case ISD::SETGE: Swap = true; // Fallthrough
15113 case ISD::SETOLE: SSECC = 2; break;
15114 case ISD::SETUO: SSECC = 3; break;
15116 case ISD::SETNE: SSECC = 4; break;
15117 case ISD::SETULE: Swap = true; // Fallthrough
15118 case ISD::SETUGE: SSECC = 5; break;
15119 case ISD::SETULT: Swap = true; // Fallthrough
15120 case ISD::SETUGT: SSECC = 6; break;
15121 case ISD::SETO: SSECC = 7; break;
15123 case ISD::SETONE: SSECC = 8; break;
15126 std::swap(Op0, Op1);
15131 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15132 // ones, and then concatenate the result back.
15133 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15134 MVT VT = Op.getSimpleValueType();
15136 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15137 "Unsupported value type for operation");
15139 unsigned NumElems = VT.getVectorNumElements();
15141 SDValue CC = Op.getOperand(2);
15143 // Extract the LHS vectors
15144 SDValue LHS = Op.getOperand(0);
15145 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15146 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15148 // Extract the RHS vectors
15149 SDValue RHS = Op.getOperand(1);
15150 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15151 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15153 // Issue the operation on the smaller types and concatenate the result back
15154 MVT EltVT = VT.getVectorElementType();
15155 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15156 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15157 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15158 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15161 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15162 const X86Subtarget *Subtarget) {
15163 SDValue Op0 = Op.getOperand(0);
15164 SDValue Op1 = Op.getOperand(1);
15165 SDValue CC = Op.getOperand(2);
15166 MVT VT = Op.getSimpleValueType();
15169 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15170 Op.getValueType().getScalarType() == MVT::i1 &&
15171 "Cannot set masked compare for this operation");
15173 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15175 bool Unsigned = false;
15178 switch (SetCCOpcode) {
15179 default: llvm_unreachable("Unexpected SETCC condition");
15180 case ISD::SETNE: SSECC = 4; break;
15181 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15182 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15183 case ISD::SETLT: Swap = true; //fall-through
15184 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15185 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15186 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15187 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15188 case ISD::SETULE: Unsigned = true; //fall-through
15189 case ISD::SETLE: SSECC = 2; break;
15193 std::swap(Op0, Op1);
15195 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15196 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15197 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15198 DAG.getConstant(SSECC, MVT::i8));
15201 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15202 /// operand \p Op1. If non-trivial (for example because it's not constant)
15203 /// return an empty value.
15204 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15206 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15210 MVT VT = Op1.getSimpleValueType();
15211 MVT EVT = VT.getVectorElementType();
15212 unsigned n = VT.getVectorNumElements();
15213 SmallVector<SDValue, 8> ULTOp1;
15215 for (unsigned i = 0; i < n; ++i) {
15216 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15217 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15220 // Avoid underflow.
15221 APInt Val = Elt->getAPIntValue();
15225 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15228 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15231 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15232 SelectionDAG &DAG) {
15233 SDValue Op0 = Op.getOperand(0);
15234 SDValue Op1 = Op.getOperand(1);
15235 SDValue CC = Op.getOperand(2);
15236 MVT VT = Op.getSimpleValueType();
15237 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15238 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15243 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15244 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15247 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15248 unsigned Opc = X86ISD::CMPP;
15249 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15250 assert(VT.getVectorNumElements() <= 16);
15251 Opc = X86ISD::CMPM;
15253 // In the two special cases we can't handle, emit two comparisons.
15256 unsigned CombineOpc;
15257 if (SetCCOpcode == ISD::SETUEQ) {
15258 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15260 assert(SetCCOpcode == ISD::SETONE);
15261 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15264 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15265 DAG.getConstant(CC0, MVT::i8));
15266 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15267 DAG.getConstant(CC1, MVT::i8));
15268 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15270 // Handle all other FP comparisons here.
15271 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15272 DAG.getConstant(SSECC, MVT::i8));
15275 // Break 256-bit integer vector compare into smaller ones.
15276 if (VT.is256BitVector() && !Subtarget->hasInt256())
15277 return Lower256IntVSETCC(Op, DAG);
15279 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15280 EVT OpVT = Op1.getValueType();
15281 if (Subtarget->hasAVX512()) {
15282 if (Op1.getValueType().is512BitVector() ||
15283 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15284 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15285 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15287 // In AVX-512 architecture setcc returns mask with i1 elements,
15288 // But there is no compare instruction for i8 and i16 elements in KNL.
15289 // We are not talking about 512-bit operands in this case, these
15290 // types are illegal.
15292 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15293 OpVT.getVectorElementType().getSizeInBits() >= 8))
15294 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15295 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15298 // We are handling one of the integer comparisons here. Since SSE only has
15299 // GT and EQ comparisons for integer, swapping operands and multiple
15300 // operations may be required for some comparisons.
15302 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15303 bool Subus = false;
15305 switch (SetCCOpcode) {
15306 default: llvm_unreachable("Unexpected SETCC condition");
15307 case ISD::SETNE: Invert = true;
15308 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15309 case ISD::SETLT: Swap = true;
15310 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15311 case ISD::SETGE: Swap = true;
15312 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15313 Invert = true; break;
15314 case ISD::SETULT: Swap = true;
15315 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15316 FlipSigns = true; break;
15317 case ISD::SETUGE: Swap = true;
15318 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15319 FlipSigns = true; Invert = true; break;
15322 // Special case: Use min/max operations for SETULE/SETUGE
15323 MVT VET = VT.getVectorElementType();
15325 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15326 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15329 switch (SetCCOpcode) {
15331 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15332 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15335 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15338 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15339 if (!MinMax && hasSubus) {
15340 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15342 // t = psubus Op0, Op1
15343 // pcmpeq t, <0..0>
15344 switch (SetCCOpcode) {
15346 case ISD::SETULT: {
15347 // If the comparison is against a constant we can turn this into a
15348 // setule. With psubus, setule does not require a swap. This is
15349 // beneficial because the constant in the register is no longer
15350 // destructed as the destination so it can be hoisted out of a loop.
15351 // Only do this pre-AVX since vpcmp* is no longer destructive.
15352 if (Subtarget->hasAVX())
15354 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15355 if (ULEOp1.getNode()) {
15357 Subus = true; Invert = false; Swap = false;
15361 // Psubus is better than flip-sign because it requires no inversion.
15362 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15363 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15367 Opc = X86ISD::SUBUS;
15373 std::swap(Op0, Op1);
15375 // Check that the operation in question is available (most are plain SSE2,
15376 // but PCMPGTQ and PCMPEQQ have different requirements).
15377 if (VT == MVT::v2i64) {
15378 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15379 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15381 // First cast everything to the right type.
15382 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15383 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15385 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15386 // bits of the inputs before performing those operations. The lower
15387 // compare is always unsigned.
15390 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15392 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15393 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15394 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15395 Sign, Zero, Sign, Zero);
15397 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15398 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15400 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15401 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15402 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15404 // Create masks for only the low parts/high parts of the 64 bit integers.
15405 static const int MaskHi[] = { 1, 1, 3, 3 };
15406 static const int MaskLo[] = { 0, 0, 2, 2 };
15407 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15408 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15409 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15411 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15412 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15415 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15417 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15420 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15421 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15422 // pcmpeqd + pshufd + pand.
15423 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15425 // First cast everything to the right type.
15426 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15427 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15430 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15432 // Make sure the lower and upper halves are both all-ones.
15433 static const int Mask[] = { 1, 0, 3, 2 };
15434 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15435 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15438 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15440 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15444 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15445 // bits of the inputs before performing those operations.
15447 EVT EltVT = VT.getVectorElementType();
15448 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15449 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15450 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15453 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15455 // If the logical-not of the result is required, perform that now.
15457 Result = DAG.getNOT(dl, Result, VT);
15460 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15463 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15464 getZeroVector(VT, Subtarget, DAG, dl));
15469 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15471 MVT VT = Op.getSimpleValueType();
15473 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15475 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15476 && "SetCC type must be 8-bit or 1-bit integer");
15477 SDValue Op0 = Op.getOperand(0);
15478 SDValue Op1 = Op.getOperand(1);
15480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15482 // Optimize to BT if possible.
15483 // Lower (X & (1 << N)) == 0 to BT(X, N).
15484 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15485 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15486 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15487 Op1.getOpcode() == ISD::Constant &&
15488 cast<ConstantSDNode>(Op1)->isNullValue() &&
15489 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15490 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15491 if (NewSetCC.getNode()) {
15493 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15498 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15500 if (Op1.getOpcode() == ISD::Constant &&
15501 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15502 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15503 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15505 // If the input is a setcc, then reuse the input setcc or use a new one with
15506 // the inverted condition.
15507 if (Op0.getOpcode() == X86ISD::SETCC) {
15508 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15509 bool Invert = (CC == ISD::SETNE) ^
15510 cast<ConstantSDNode>(Op1)->isNullValue();
15514 CCode = X86::GetOppositeBranchCondition(CCode);
15515 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15516 DAG.getConstant(CCode, MVT::i8),
15517 Op0.getOperand(1));
15519 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15523 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15524 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15525 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15527 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15528 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15531 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15532 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15533 if (X86CC == X86::COND_INVALID)
15536 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15537 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15538 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15539 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15541 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15545 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15546 static bool isX86LogicalCmp(SDValue Op) {
15547 unsigned Opc = Op.getNode()->getOpcode();
15548 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15549 Opc == X86ISD::SAHF)
15551 if (Op.getResNo() == 1 &&
15552 (Opc == X86ISD::ADD ||
15553 Opc == X86ISD::SUB ||
15554 Opc == X86ISD::ADC ||
15555 Opc == X86ISD::SBB ||
15556 Opc == X86ISD::SMUL ||
15557 Opc == X86ISD::UMUL ||
15558 Opc == X86ISD::INC ||
15559 Opc == X86ISD::DEC ||
15560 Opc == X86ISD::OR ||
15561 Opc == X86ISD::XOR ||
15562 Opc == X86ISD::AND))
15565 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15571 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15572 if (V.getOpcode() != ISD::TRUNCATE)
15575 SDValue VOp0 = V.getOperand(0);
15576 unsigned InBits = VOp0.getValueSizeInBits();
15577 unsigned Bits = V.getValueSizeInBits();
15578 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15581 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15582 bool addTest = true;
15583 SDValue Cond = Op.getOperand(0);
15584 SDValue Op1 = Op.getOperand(1);
15585 SDValue Op2 = Op.getOperand(2);
15587 EVT VT = Op1.getValueType();
15590 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15591 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15592 // sequence later on.
15593 if (Cond.getOpcode() == ISD::SETCC &&
15594 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15595 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15596 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15597 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15598 int SSECC = translateX86FSETCC(
15599 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15602 if (Subtarget->hasAVX512()) {
15603 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15604 DAG.getConstant(SSECC, MVT::i8));
15605 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15607 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15608 DAG.getConstant(SSECC, MVT::i8));
15609 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15610 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15611 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15615 if (Cond.getOpcode() == ISD::SETCC) {
15616 SDValue NewCond = LowerSETCC(Cond, DAG);
15617 if (NewCond.getNode())
15621 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15622 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15623 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15624 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15625 if (Cond.getOpcode() == X86ISD::SETCC &&
15626 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15627 isZero(Cond.getOperand(1).getOperand(1))) {
15628 SDValue Cmp = Cond.getOperand(1);
15630 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15632 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15633 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15634 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15636 SDValue CmpOp0 = Cmp.getOperand(0);
15637 // Apply further optimizations for special cases
15638 // (select (x != 0), -1, 0) -> neg & sbb
15639 // (select (x == 0), 0, -1) -> neg & sbb
15640 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15641 if (YC->isNullValue() &&
15642 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15643 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15644 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15645 DAG.getConstant(0, CmpOp0.getValueType()),
15647 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15648 DAG.getConstant(X86::COND_B, MVT::i8),
15649 SDValue(Neg.getNode(), 1));
15653 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15654 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15655 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15657 SDValue Res = // Res = 0 or -1.
15658 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15659 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15661 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15662 Res = DAG.getNOT(DL, Res, Res.getValueType());
15664 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15665 if (!N2C || !N2C->isNullValue())
15666 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15671 // Look past (and (setcc_carry (cmp ...)), 1).
15672 if (Cond.getOpcode() == ISD::AND &&
15673 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15674 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15675 if (C && C->getAPIntValue() == 1)
15676 Cond = Cond.getOperand(0);
15679 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15680 // setting operand in place of the X86ISD::SETCC.
15681 unsigned CondOpcode = Cond.getOpcode();
15682 if (CondOpcode == X86ISD::SETCC ||
15683 CondOpcode == X86ISD::SETCC_CARRY) {
15684 CC = Cond.getOperand(0);
15686 SDValue Cmp = Cond.getOperand(1);
15687 unsigned Opc = Cmp.getOpcode();
15688 MVT VT = Op.getSimpleValueType();
15690 bool IllegalFPCMov = false;
15691 if (VT.isFloatingPoint() && !VT.isVector() &&
15692 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15693 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15695 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15696 Opc == X86ISD::BT) { // FIXME
15700 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15701 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15702 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15703 Cond.getOperand(0).getValueType() != MVT::i8)) {
15704 SDValue LHS = Cond.getOperand(0);
15705 SDValue RHS = Cond.getOperand(1);
15706 unsigned X86Opcode;
15709 switch (CondOpcode) {
15710 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15711 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15712 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15713 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15714 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15715 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15716 default: llvm_unreachable("unexpected overflowing operator");
15718 if (CondOpcode == ISD::UMULO)
15719 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15722 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15724 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15726 if (CondOpcode == ISD::UMULO)
15727 Cond = X86Op.getValue(2);
15729 Cond = X86Op.getValue(1);
15731 CC = DAG.getConstant(X86Cond, MVT::i8);
15736 // Look pass the truncate if the high bits are known zero.
15737 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15738 Cond = Cond.getOperand(0);
15740 // We know the result of AND is compared against zero. Try to match
15742 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15743 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15744 if (NewSetCC.getNode()) {
15745 CC = NewSetCC.getOperand(0);
15746 Cond = NewSetCC.getOperand(1);
15753 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15754 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15757 // a < b ? -1 : 0 -> RES = ~setcc_carry
15758 // a < b ? 0 : -1 -> RES = setcc_carry
15759 // a >= b ? -1 : 0 -> RES = setcc_carry
15760 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15761 if (Cond.getOpcode() == X86ISD::SUB) {
15762 Cond = ConvertCmpIfNecessary(Cond, DAG);
15763 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15765 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15766 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15767 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15768 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15769 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15770 return DAG.getNOT(DL, Res, Res.getValueType());
15775 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15776 // widen the cmov and push the truncate through. This avoids introducing a new
15777 // branch during isel and doesn't add any extensions.
15778 if (Op.getValueType() == MVT::i8 &&
15779 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15780 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15781 if (T1.getValueType() == T2.getValueType() &&
15782 // Blacklist CopyFromReg to avoid partial register stalls.
15783 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15784 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15785 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15786 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15790 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15791 // condition is true.
15792 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15793 SDValue Ops[] = { Op2, Op1, CC, Cond };
15794 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15797 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15798 SelectionDAG &DAG) {
15799 MVT VT = Op->getSimpleValueType(0);
15800 SDValue In = Op->getOperand(0);
15801 MVT InVT = In.getSimpleValueType();
15802 MVT VTElt = VT.getVectorElementType();
15803 MVT InVTElt = InVT.getVectorElementType();
15807 if ((InVTElt == MVT::i1) &&
15808 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15809 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15811 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15812 VTElt.getSizeInBits() <= 16)) ||
15814 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15815 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15817 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15818 VTElt.getSizeInBits() >= 32))))
15819 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15821 unsigned int NumElts = VT.getVectorNumElements();
15823 if (NumElts != 8 && NumElts != 16)
15826 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15827 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15828 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15829 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15833 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15835 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15836 Constant *C = ConstantInt::get(*DAG.getContext(),
15837 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15839 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15840 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15841 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15842 MachinePointerInfo::getConstantPool(),
15843 false, false, false, Alignment);
15844 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15845 if (VT.is512BitVector())
15847 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15850 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15851 SelectionDAG &DAG) {
15852 MVT VT = Op->getSimpleValueType(0);
15853 SDValue In = Op->getOperand(0);
15854 MVT InVT = In.getSimpleValueType();
15857 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15858 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15860 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15861 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15862 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15865 if (Subtarget->hasInt256())
15866 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15868 // Optimize vectors in AVX mode
15869 // Sign extend v8i16 to v8i32 and
15872 // Divide input vector into two parts
15873 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15874 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15875 // concat the vectors to original VT
15877 unsigned NumElems = InVT.getVectorNumElements();
15878 SDValue Undef = DAG.getUNDEF(InVT);
15880 SmallVector<int,8> ShufMask1(NumElems, -1);
15881 for (unsigned i = 0; i != NumElems/2; ++i)
15884 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15886 SmallVector<int,8> ShufMask2(NumElems, -1);
15887 for (unsigned i = 0; i != NumElems/2; ++i)
15888 ShufMask2[i] = i + NumElems/2;
15890 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15892 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15893 VT.getVectorNumElements()/2);
15895 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15896 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15898 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15901 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15902 // may emit an illegal shuffle but the expansion is still better than scalar
15903 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15904 // we'll emit a shuffle and a arithmetic shift.
15905 // TODO: It is possible to support ZExt by zeroing the undef values during
15906 // the shuffle phase or after the shuffle.
15907 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15908 SelectionDAG &DAG) {
15909 MVT RegVT = Op.getSimpleValueType();
15910 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15911 assert(RegVT.isInteger() &&
15912 "We only custom lower integer vector sext loads.");
15914 // Nothing useful we can do without SSE2 shuffles.
15915 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15917 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15919 EVT MemVT = Ld->getMemoryVT();
15920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15921 unsigned RegSz = RegVT.getSizeInBits();
15923 ISD::LoadExtType Ext = Ld->getExtensionType();
15925 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15926 && "Only anyext and sext are currently implemented.");
15927 assert(MemVT != RegVT && "Cannot extend to the same type");
15928 assert(MemVT.isVector() && "Must load a vector from memory");
15930 unsigned NumElems = RegVT.getVectorNumElements();
15931 unsigned MemSz = MemVT.getSizeInBits();
15932 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15934 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15935 // The only way in which we have a legal 256-bit vector result but not the
15936 // integer 256-bit operations needed to directly lower a sextload is if we
15937 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15938 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15939 // correctly legalized. We do this late to allow the canonical form of
15940 // sextload to persist throughout the rest of the DAG combiner -- it wants
15941 // to fold together any extensions it can, and so will fuse a sign_extend
15942 // of an sextload into a sextload targeting a wider value.
15944 if (MemSz == 128) {
15945 // Just switch this to a normal load.
15946 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15947 "it must be a legal 128-bit vector "
15949 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15950 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15951 Ld->isInvariant(), Ld->getAlignment());
15953 assert(MemSz < 128 &&
15954 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15955 // Do an sext load to a 128-bit vector type. We want to use the same
15956 // number of elements, but elements half as wide. This will end up being
15957 // recursively lowered by this routine, but will succeed as we definitely
15958 // have all the necessary features if we're using AVX1.
15960 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15961 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15963 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15964 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15965 Ld->isNonTemporal(), Ld->isInvariant(),
15966 Ld->getAlignment());
15969 // Replace chain users with the new chain.
15970 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15971 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15973 // Finally, do a normal sign-extend to the desired register.
15974 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15977 // All sizes must be a power of two.
15978 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15979 "Non-power-of-two elements are not custom lowered!");
15981 // Attempt to load the original value using scalar loads.
15982 // Find the largest scalar type that divides the total loaded size.
15983 MVT SclrLoadTy = MVT::i8;
15984 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15985 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15986 MVT Tp = (MVT::SimpleValueType)tp;
15987 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15992 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15993 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15995 SclrLoadTy = MVT::f64;
15997 // Calculate the number of scalar loads that we need to perform
15998 // in order to load our vector from memory.
15999 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16001 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16002 "Can only lower sext loads with a single scalar load!");
16004 unsigned loadRegZize = RegSz;
16005 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16008 // Represent our vector as a sequence of elements which are the
16009 // largest scalar that we can load.
16010 EVT LoadUnitVecVT = EVT::getVectorVT(
16011 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16013 // Represent the data using the same element type that is stored in
16014 // memory. In practice, we ''widen'' MemVT.
16016 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16017 loadRegZize / MemVT.getScalarType().getSizeInBits());
16019 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16020 "Invalid vector type");
16022 // We can't shuffle using an illegal type.
16023 assert(TLI.isTypeLegal(WideVecVT) &&
16024 "We only lower types that form legal widened vector types");
16026 SmallVector<SDValue, 8> Chains;
16027 SDValue Ptr = Ld->getBasePtr();
16028 SDValue Increment =
16029 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16030 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16032 for (unsigned i = 0; i < NumLoads; ++i) {
16033 // Perform a single load.
16034 SDValue ScalarLoad =
16035 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16036 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16037 Ld->getAlignment());
16038 Chains.push_back(ScalarLoad.getValue(1));
16039 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16040 // another round of DAGCombining.
16042 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16044 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16045 ScalarLoad, DAG.getIntPtrConstant(i));
16047 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16050 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16052 // Bitcast the loaded value to a vector of the original element type, in
16053 // the size of the target vector type.
16054 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16055 unsigned SizeRatio = RegSz / MemSz;
16057 if (Ext == ISD::SEXTLOAD) {
16058 // If we have SSE4.1, we can directly emit a VSEXT node.
16059 if (Subtarget->hasSSE41()) {
16060 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16061 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16065 // Otherwise we'll shuffle the small elements in the high bits of the
16066 // larger type and perform an arithmetic shift. If the shift is not legal
16067 // it's better to scalarize.
16068 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16069 "We can't implement a sext load without an arithmetic right shift!");
16071 // Redistribute the loaded elements into the different locations.
16072 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16073 for (unsigned i = 0; i != NumElems; ++i)
16074 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16076 SDValue Shuff = DAG.getVectorShuffle(
16077 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16079 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16081 // Build the arithmetic shift.
16082 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16083 MemVT.getVectorElementType().getSizeInBits();
16085 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16087 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16091 // Redistribute the loaded elements into the different locations.
16092 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16093 for (unsigned i = 0; i != NumElems; ++i)
16094 ShuffleVec[i * SizeRatio] = i;
16096 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16097 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16099 // Bitcast to the requested type.
16100 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16101 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16105 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16106 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16107 // from the AND / OR.
16108 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16109 Opc = Op.getOpcode();
16110 if (Opc != ISD::OR && Opc != ISD::AND)
16112 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16113 Op.getOperand(0).hasOneUse() &&
16114 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16115 Op.getOperand(1).hasOneUse());
16118 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16119 // 1 and that the SETCC node has a single use.
16120 static bool isXor1OfSetCC(SDValue Op) {
16121 if (Op.getOpcode() != ISD::XOR)
16123 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16124 if (N1C && N1C->getAPIntValue() == 1) {
16125 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16126 Op.getOperand(0).hasOneUse();
16131 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16132 bool addTest = true;
16133 SDValue Chain = Op.getOperand(0);
16134 SDValue Cond = Op.getOperand(1);
16135 SDValue Dest = Op.getOperand(2);
16138 bool Inverted = false;
16140 if (Cond.getOpcode() == ISD::SETCC) {
16141 // Check for setcc([su]{add,sub,mul}o == 0).
16142 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16143 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16144 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16145 Cond.getOperand(0).getResNo() == 1 &&
16146 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16147 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16148 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16149 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16150 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16151 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16153 Cond = Cond.getOperand(0);
16155 SDValue NewCond = LowerSETCC(Cond, DAG);
16156 if (NewCond.getNode())
16161 // FIXME: LowerXALUO doesn't handle these!!
16162 else if (Cond.getOpcode() == X86ISD::ADD ||
16163 Cond.getOpcode() == X86ISD::SUB ||
16164 Cond.getOpcode() == X86ISD::SMUL ||
16165 Cond.getOpcode() == X86ISD::UMUL)
16166 Cond = LowerXALUO(Cond, DAG);
16169 // Look pass (and (setcc_carry (cmp ...)), 1).
16170 if (Cond.getOpcode() == ISD::AND &&
16171 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16172 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16173 if (C && C->getAPIntValue() == 1)
16174 Cond = Cond.getOperand(0);
16177 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16178 // setting operand in place of the X86ISD::SETCC.
16179 unsigned CondOpcode = Cond.getOpcode();
16180 if (CondOpcode == X86ISD::SETCC ||
16181 CondOpcode == X86ISD::SETCC_CARRY) {
16182 CC = Cond.getOperand(0);
16184 SDValue Cmp = Cond.getOperand(1);
16185 unsigned Opc = Cmp.getOpcode();
16186 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16187 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16191 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16195 // These can only come from an arithmetic instruction with overflow,
16196 // e.g. SADDO, UADDO.
16197 Cond = Cond.getNode()->getOperand(1);
16203 CondOpcode = Cond.getOpcode();
16204 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16205 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16206 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16207 Cond.getOperand(0).getValueType() != MVT::i8)) {
16208 SDValue LHS = Cond.getOperand(0);
16209 SDValue RHS = Cond.getOperand(1);
16210 unsigned X86Opcode;
16213 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16214 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16216 switch (CondOpcode) {
16217 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16221 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16224 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16225 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16229 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16232 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16233 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16234 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16235 default: llvm_unreachable("unexpected overflowing operator");
16238 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16239 if (CondOpcode == ISD::UMULO)
16240 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16243 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16245 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16247 if (CondOpcode == ISD::UMULO)
16248 Cond = X86Op.getValue(2);
16250 Cond = X86Op.getValue(1);
16252 CC = DAG.getConstant(X86Cond, MVT::i8);
16256 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16257 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16258 if (CondOpc == ISD::OR) {
16259 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16260 // two branches instead of an explicit OR instruction with a
16262 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16263 isX86LogicalCmp(Cmp)) {
16264 CC = Cond.getOperand(0).getOperand(0);
16265 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16266 Chain, Dest, CC, Cmp);
16267 CC = Cond.getOperand(1).getOperand(0);
16271 } else { // ISD::AND
16272 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16273 // two branches instead of an explicit AND instruction with a
16274 // separate test. However, we only do this if this block doesn't
16275 // have a fall-through edge, because this requires an explicit
16276 // jmp when the condition is false.
16277 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16278 isX86LogicalCmp(Cmp) &&
16279 Op.getNode()->hasOneUse()) {
16280 X86::CondCode CCode =
16281 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16282 CCode = X86::GetOppositeBranchCondition(CCode);
16283 CC = DAG.getConstant(CCode, MVT::i8);
16284 SDNode *User = *Op.getNode()->use_begin();
16285 // Look for an unconditional branch following this conditional branch.
16286 // We need this because we need to reverse the successors in order
16287 // to implement FCMP_OEQ.
16288 if (User->getOpcode() == ISD::BR) {
16289 SDValue FalseBB = User->getOperand(1);
16291 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16292 assert(NewBR == User);
16296 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16297 Chain, Dest, CC, Cmp);
16298 X86::CondCode CCode =
16299 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16300 CCode = X86::GetOppositeBranchCondition(CCode);
16301 CC = DAG.getConstant(CCode, MVT::i8);
16307 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16308 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16309 // It should be transformed during dag combiner except when the condition
16310 // is set by a arithmetics with overflow node.
16311 X86::CondCode CCode =
16312 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16313 CCode = X86::GetOppositeBranchCondition(CCode);
16314 CC = DAG.getConstant(CCode, MVT::i8);
16315 Cond = Cond.getOperand(0).getOperand(1);
16317 } else if (Cond.getOpcode() == ISD::SETCC &&
16318 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16319 // For FCMP_OEQ, we can emit
16320 // two branches instead of an explicit AND instruction with a
16321 // separate test. However, we only do this if this block doesn't
16322 // have a fall-through edge, because this requires an explicit
16323 // jmp when the condition is false.
16324 if (Op.getNode()->hasOneUse()) {
16325 SDNode *User = *Op.getNode()->use_begin();
16326 // Look for an unconditional branch following this conditional branch.
16327 // We need this because we need to reverse the successors in order
16328 // to implement FCMP_OEQ.
16329 if (User->getOpcode() == ISD::BR) {
16330 SDValue FalseBB = User->getOperand(1);
16332 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16333 assert(NewBR == User);
16337 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16338 Cond.getOperand(0), Cond.getOperand(1));
16339 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16340 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16341 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16342 Chain, Dest, CC, Cmp);
16343 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16348 } else if (Cond.getOpcode() == ISD::SETCC &&
16349 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16350 // For FCMP_UNE, we can emit
16351 // two branches instead of an explicit AND instruction with a
16352 // separate test. However, we only do this if this block doesn't
16353 // have a fall-through edge, because this requires an explicit
16354 // jmp when the condition is false.
16355 if (Op.getNode()->hasOneUse()) {
16356 SDNode *User = *Op.getNode()->use_begin();
16357 // Look for an unconditional branch following this conditional branch.
16358 // We need this because we need to reverse the successors in order
16359 // to implement FCMP_UNE.
16360 if (User->getOpcode() == ISD::BR) {
16361 SDValue FalseBB = User->getOperand(1);
16363 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16364 assert(NewBR == User);
16367 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16368 Cond.getOperand(0), Cond.getOperand(1));
16369 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16370 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16371 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16372 Chain, Dest, CC, Cmp);
16373 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16383 // Look pass the truncate if the high bits are known zero.
16384 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16385 Cond = Cond.getOperand(0);
16387 // We know the result of AND is compared against zero. Try to match
16389 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16390 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16391 if (NewSetCC.getNode()) {
16392 CC = NewSetCC.getOperand(0);
16393 Cond = NewSetCC.getOperand(1);
16400 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16401 CC = DAG.getConstant(X86Cond, MVT::i8);
16402 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16404 Cond = ConvertCmpIfNecessary(Cond, DAG);
16405 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16406 Chain, Dest, CC, Cond);
16409 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16410 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16411 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16412 // that the guard pages used by the OS virtual memory manager are allocated in
16413 // correct sequence.
16415 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16416 SelectionDAG &DAG) const {
16417 MachineFunction &MF = DAG.getMachineFunction();
16418 bool SplitStack = MF.shouldSplitStack();
16419 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16425 SDNode* Node = Op.getNode();
16427 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16428 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16429 " not tell us which reg is the stack pointer!");
16430 EVT VT = Node->getValueType(0);
16431 SDValue Tmp1 = SDValue(Node, 0);
16432 SDValue Tmp2 = SDValue(Node, 1);
16433 SDValue Tmp3 = Node->getOperand(2);
16434 SDValue Chain = Tmp1.getOperand(0);
16436 // Chain the dynamic stack allocation so that it doesn't modify the stack
16437 // pointer when other instructions are using the stack.
16438 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16441 SDValue Size = Tmp2.getOperand(1);
16442 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16443 Chain = SP.getValue(1);
16444 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16445 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16446 unsigned StackAlign = TFI.getStackAlignment();
16447 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16448 if (Align > StackAlign)
16449 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16450 DAG.getConstant(-(uint64_t)Align, VT));
16451 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16453 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16454 DAG.getIntPtrConstant(0, true), SDValue(),
16457 SDValue Ops[2] = { Tmp1, Tmp2 };
16458 return DAG.getMergeValues(Ops, dl);
16462 SDValue Chain = Op.getOperand(0);
16463 SDValue Size = Op.getOperand(1);
16464 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16465 EVT VT = Op.getNode()->getValueType(0);
16467 bool Is64Bit = Subtarget->is64Bit();
16468 EVT SPTy = getPointerTy();
16471 MachineRegisterInfo &MRI = MF.getRegInfo();
16474 // The 64 bit implementation of segmented stacks needs to clobber both r10
16475 // r11. This makes it impossible to use it along with nested parameters.
16476 const Function *F = MF.getFunction();
16478 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16480 if (I->hasNestAttr())
16481 report_fatal_error("Cannot use segmented stacks with functions that "
16482 "have nested arguments.");
16485 const TargetRegisterClass *AddrRegClass =
16486 getRegClassFor(getPointerTy());
16487 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16488 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16489 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16490 DAG.getRegister(Vreg, SPTy));
16491 SDValue Ops1[2] = { Value, Chain };
16492 return DAG.getMergeValues(Ops1, dl);
16495 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16497 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16498 Flag = Chain.getValue(1);
16499 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16501 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16503 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16504 DAG.getSubtarget().getRegisterInfo());
16505 unsigned SPReg = RegInfo->getStackRegister();
16506 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16507 Chain = SP.getValue(1);
16510 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16511 DAG.getConstant(-(uint64_t)Align, VT));
16512 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16515 SDValue Ops1[2] = { SP, Chain };
16516 return DAG.getMergeValues(Ops1, dl);
16520 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16521 MachineFunction &MF = DAG.getMachineFunction();
16522 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16524 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16527 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16528 // vastart just stores the address of the VarArgsFrameIndex slot into the
16529 // memory location argument.
16530 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16532 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16533 MachinePointerInfo(SV), false, false, 0);
16537 // gp_offset (0 - 6 * 8)
16538 // fp_offset (48 - 48 + 8 * 16)
16539 // overflow_arg_area (point to parameters coming in memory).
16541 SmallVector<SDValue, 8> MemOps;
16542 SDValue FIN = Op.getOperand(1);
16544 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16545 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16547 FIN, MachinePointerInfo(SV), false, false, 0);
16548 MemOps.push_back(Store);
16551 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16552 FIN, DAG.getIntPtrConstant(4));
16553 Store = DAG.getStore(Op.getOperand(0), DL,
16554 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16556 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16557 MemOps.push_back(Store);
16559 // Store ptr to overflow_arg_area
16560 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16561 FIN, DAG.getIntPtrConstant(4));
16562 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16564 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16565 MachinePointerInfo(SV, 8),
16567 MemOps.push_back(Store);
16569 // Store ptr to reg_save_area.
16570 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16571 FIN, DAG.getIntPtrConstant(8));
16572 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16574 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16575 MachinePointerInfo(SV, 16), false, false, 0);
16576 MemOps.push_back(Store);
16577 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16580 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16581 assert(Subtarget->is64Bit() &&
16582 "LowerVAARG only handles 64-bit va_arg!");
16583 assert((Subtarget->isTargetLinux() ||
16584 Subtarget->isTargetDarwin()) &&
16585 "Unhandled target in LowerVAARG");
16586 assert(Op.getNode()->getNumOperands() == 4);
16587 SDValue Chain = Op.getOperand(0);
16588 SDValue SrcPtr = Op.getOperand(1);
16589 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16590 unsigned Align = Op.getConstantOperandVal(3);
16593 EVT ArgVT = Op.getNode()->getValueType(0);
16594 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16595 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16598 // Decide which area this value should be read from.
16599 // TODO: Implement the AMD64 ABI in its entirety. This simple
16600 // selection mechanism works only for the basic types.
16601 if (ArgVT == MVT::f80) {
16602 llvm_unreachable("va_arg for f80 not yet implemented");
16603 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16604 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16605 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16606 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16608 llvm_unreachable("Unhandled argument type in LowerVAARG");
16611 if (ArgMode == 2) {
16612 // Sanity Check: Make sure using fp_offset makes sense.
16613 assert(!DAG.getTarget().Options.UseSoftFloat &&
16614 !(DAG.getMachineFunction()
16615 .getFunction()->getAttributes()
16616 .hasAttribute(AttributeSet::FunctionIndex,
16617 Attribute::NoImplicitFloat)) &&
16618 Subtarget->hasSSE1());
16621 // Insert VAARG_64 node into the DAG
16622 // VAARG_64 returns two values: Variable Argument Address, Chain
16623 SmallVector<SDValue, 11> InstOps;
16624 InstOps.push_back(Chain);
16625 InstOps.push_back(SrcPtr);
16626 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16627 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16628 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16629 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16630 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16631 VTs, InstOps, MVT::i64,
16632 MachinePointerInfo(SV),
16634 /*Volatile=*/false,
16636 /*WriteMem=*/true);
16637 Chain = VAARG.getValue(1);
16639 // Load the next argument and return it
16640 return DAG.getLoad(ArgVT, dl,
16643 MachinePointerInfo(),
16644 false, false, false, 0);
16647 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16648 SelectionDAG &DAG) {
16649 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16650 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16651 SDValue Chain = Op.getOperand(0);
16652 SDValue DstPtr = Op.getOperand(1);
16653 SDValue SrcPtr = Op.getOperand(2);
16654 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16655 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16658 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16659 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16661 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16664 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16665 // amount is a constant. Takes immediate version of shift as input.
16666 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16667 SDValue SrcOp, uint64_t ShiftAmt,
16668 SelectionDAG &DAG) {
16669 MVT ElementType = VT.getVectorElementType();
16671 // Fold this packed shift into its first operand if ShiftAmt is 0.
16675 // Check for ShiftAmt >= element width
16676 if (ShiftAmt >= ElementType.getSizeInBits()) {
16677 if (Opc == X86ISD::VSRAI)
16678 ShiftAmt = ElementType.getSizeInBits() - 1;
16680 return DAG.getConstant(0, VT);
16683 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16684 && "Unknown target vector shift-by-constant node");
16686 // Fold this packed vector shift into a build vector if SrcOp is a
16687 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16688 if (VT == SrcOp.getSimpleValueType() &&
16689 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16690 SmallVector<SDValue, 8> Elts;
16691 unsigned NumElts = SrcOp->getNumOperands();
16692 ConstantSDNode *ND;
16695 default: llvm_unreachable(nullptr);
16696 case X86ISD::VSHLI:
16697 for (unsigned i=0; i!=NumElts; ++i) {
16698 SDValue CurrentOp = SrcOp->getOperand(i);
16699 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16700 Elts.push_back(CurrentOp);
16703 ND = cast<ConstantSDNode>(CurrentOp);
16704 const APInt &C = ND->getAPIntValue();
16705 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16708 case X86ISD::VSRLI:
16709 for (unsigned i=0; i!=NumElts; ++i) {
16710 SDValue CurrentOp = SrcOp->getOperand(i);
16711 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16712 Elts.push_back(CurrentOp);
16715 ND = cast<ConstantSDNode>(CurrentOp);
16716 const APInt &C = ND->getAPIntValue();
16717 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16720 case X86ISD::VSRAI:
16721 for (unsigned i=0; i!=NumElts; ++i) {
16722 SDValue CurrentOp = SrcOp->getOperand(i);
16723 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16724 Elts.push_back(CurrentOp);
16727 ND = cast<ConstantSDNode>(CurrentOp);
16728 const APInt &C = ND->getAPIntValue();
16729 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16734 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16737 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16740 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16741 // may or may not be a constant. Takes immediate version of shift as input.
16742 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16743 SDValue SrcOp, SDValue ShAmt,
16744 SelectionDAG &DAG) {
16745 MVT SVT = ShAmt.getSimpleValueType();
16746 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16748 // Catch shift-by-constant.
16749 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16750 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16751 CShAmt->getZExtValue(), DAG);
16753 // Change opcode to non-immediate version
16755 default: llvm_unreachable("Unknown target vector shift node");
16756 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16757 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16758 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16761 const X86Subtarget &Subtarget =
16762 DAG.getTarget().getSubtarget<X86Subtarget>();
16763 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16764 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16765 // Let the shuffle legalizer expand this shift amount node.
16766 SDValue Op0 = ShAmt.getOperand(0);
16767 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16768 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16770 // Need to build a vector containing shift amount.
16771 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16772 SmallVector<SDValue, 4> ShOps;
16773 ShOps.push_back(ShAmt);
16774 if (SVT == MVT::i32) {
16775 ShOps.push_back(DAG.getConstant(0, SVT));
16776 ShOps.push_back(DAG.getUNDEF(SVT));
16778 ShOps.push_back(DAG.getUNDEF(SVT));
16780 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16781 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16784 // The return type has to be a 128-bit type with the same element
16785 // type as the input type.
16786 MVT EltVT = VT.getVectorElementType();
16787 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16789 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16790 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16793 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16794 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16795 /// necessary casting for \p Mask when lowering masking intrinsics.
16796 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16797 SDValue PreservedSrc,
16798 const X86Subtarget *Subtarget,
16799 SelectionDAG &DAG) {
16800 EVT VT = Op.getValueType();
16801 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16802 MVT::i1, VT.getVectorNumElements());
16803 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16804 Mask.getValueType().getSizeInBits());
16807 assert(MaskVT.isSimple() && "invalid mask type");
16809 if (isAllOnes(Mask))
16812 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16813 // are extracted by EXTRACT_SUBVECTOR.
16814 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16815 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16816 DAG.getIntPtrConstant(0));
16818 switch (Op.getOpcode()) {
16820 case X86ISD::PCMPEQM:
16821 case X86ISD::PCMPGTM:
16823 case X86ISD::CMPMU:
16824 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16826 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16827 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16828 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16831 /// \brief Creates an SDNode for a predicated scalar operation.
16832 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16833 /// The mask is comming as MVT::i8 and it should be truncated
16834 /// to MVT::i1 while lowering masking intrinsics.
16835 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16836 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16837 /// a scalar instruction.
16838 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16839 SDValue PreservedSrc,
16840 const X86Subtarget *Subtarget,
16841 SelectionDAG &DAG) {
16842 if (isAllOnes(Mask))
16845 EVT VT = Op.getValueType();
16847 // The mask should be of type MVT::i1
16848 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16850 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16851 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16852 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16855 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16857 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16858 case Intrinsic::x86_fma_vfmadd_ps:
16859 case Intrinsic::x86_fma_vfmadd_pd:
16860 case Intrinsic::x86_fma_vfmadd_ps_256:
16861 case Intrinsic::x86_fma_vfmadd_pd_256:
16862 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16863 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16864 return X86ISD::FMADD;
16865 case Intrinsic::x86_fma_vfmsub_ps:
16866 case Intrinsic::x86_fma_vfmsub_pd:
16867 case Intrinsic::x86_fma_vfmsub_ps_256:
16868 case Intrinsic::x86_fma_vfmsub_pd_256:
16869 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16870 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16871 return X86ISD::FMSUB;
16872 case Intrinsic::x86_fma_vfnmadd_ps:
16873 case Intrinsic::x86_fma_vfnmadd_pd:
16874 case Intrinsic::x86_fma_vfnmadd_ps_256:
16875 case Intrinsic::x86_fma_vfnmadd_pd_256:
16876 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16877 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16878 return X86ISD::FNMADD;
16879 case Intrinsic::x86_fma_vfnmsub_ps:
16880 case Intrinsic::x86_fma_vfnmsub_pd:
16881 case Intrinsic::x86_fma_vfnmsub_ps_256:
16882 case Intrinsic::x86_fma_vfnmsub_pd_256:
16883 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16884 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16885 return X86ISD::FNMSUB;
16886 case Intrinsic::x86_fma_vfmaddsub_ps:
16887 case Intrinsic::x86_fma_vfmaddsub_pd:
16888 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16889 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16890 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16891 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16892 return X86ISD::FMADDSUB;
16893 case Intrinsic::x86_fma_vfmsubadd_ps:
16894 case Intrinsic::x86_fma_vfmsubadd_pd:
16895 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16896 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16897 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16898 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16899 return X86ISD::FMSUBADD;
16903 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16904 SelectionDAG &DAG) {
16906 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16907 EVT VT = Op.getValueType();
16908 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16910 switch(IntrData->Type) {
16911 case INTR_TYPE_1OP:
16912 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16913 case INTR_TYPE_2OP:
16914 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16916 case INTR_TYPE_3OP:
16917 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16918 Op.getOperand(2), Op.getOperand(3));
16919 case INTR_TYPE_1OP_MASK_RM: {
16920 SDValue Src = Op.getOperand(1);
16921 SDValue Src0 = Op.getOperand(2);
16922 SDValue Mask = Op.getOperand(3);
16923 SDValue RoundingMode = Op.getOperand(4);
16924 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16926 Mask, Src0, Subtarget, DAG);
16928 case INTR_TYPE_SCALAR_MASK_RM: {
16929 SDValue Src1 = Op.getOperand(1);
16930 SDValue Src2 = Op.getOperand(2);
16931 SDValue Src0 = Op.getOperand(3);
16932 SDValue Mask = Op.getOperand(4);
16933 SDValue RoundingMode = Op.getOperand(5);
16934 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16936 Mask, Src0, Subtarget, DAG);
16938 case INTR_TYPE_2OP_MASK: {
16939 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16941 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16944 case CMP_MASK_CC: {
16945 // Comparison intrinsics with masks.
16946 // Example of transformation:
16947 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16948 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16950 // (v8i1 (insert_subvector undef,
16951 // (v2i1 (and (PCMPEQM %a, %b),
16952 // (extract_subvector
16953 // (v8i1 (bitcast %mask)), 0))), 0))))
16954 EVT VT = Op.getOperand(1).getValueType();
16955 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16956 VT.getVectorNumElements());
16957 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16958 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16959 Mask.getValueType().getSizeInBits());
16961 if (IntrData->Type == CMP_MASK_CC) {
16962 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16963 Op.getOperand(2), Op.getOperand(3));
16965 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16966 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16969 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16970 DAG.getTargetConstant(0, MaskVT),
16972 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16973 DAG.getUNDEF(BitcastVT), CmpMask,
16974 DAG.getIntPtrConstant(0));
16975 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16977 case COMI: { // Comparison intrinsics
16978 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16979 SDValue LHS = Op.getOperand(1);
16980 SDValue RHS = Op.getOperand(2);
16981 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16982 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16983 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16984 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16985 DAG.getConstant(X86CC, MVT::i8), Cond);
16986 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16989 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16990 Op.getOperand(1), Op.getOperand(2), DAG);
16992 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16993 Op.getSimpleValueType(),
16995 Op.getOperand(2), DAG),
16996 Op.getOperand(4), Op.getOperand(3), Subtarget,
16998 case COMPRESS_EXPAND_IN_REG: {
16999 SDValue Mask = Op.getOperand(3);
17000 SDValue DataToCompress = Op.getOperand(1);
17001 SDValue PassThru = Op.getOperand(2);
17002 if (isAllOnes(Mask)) // return data as is
17003 return Op.getOperand(1);
17004 EVT VT = Op.getValueType();
17005 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17006 VT.getVectorNumElements());
17007 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17008 Mask.getValueType().getSizeInBits());
17010 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17011 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17012 DAG.getIntPtrConstant(0));
17014 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17018 SDValue Mask = Op.getOperand(3);
17019 EVT VT = Op.getValueType();
17020 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17021 VT.getVectorNumElements());
17022 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17023 Mask.getValueType().getSizeInBits());
17025 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17026 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17027 DAG.getIntPtrConstant(0));
17028 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17033 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17034 dl, Op.getValueType(),
17038 Op.getOperand(4), Op.getOperand(1),
17047 default: return SDValue(); // Don't custom lower most intrinsics.
17049 case Intrinsic::x86_avx512_mask_valign_q_512:
17050 case Intrinsic::x86_avx512_mask_valign_d_512:
17051 // Vector source operands are swapped.
17052 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17053 Op.getValueType(), Op.getOperand(2),
17056 Op.getOperand(5), Op.getOperand(4),
17059 // ptest and testp intrinsics. The intrinsic these come from are designed to
17060 // return an integer value, not just an instruction so lower it to the ptest
17061 // or testp pattern and a setcc for the result.
17062 case Intrinsic::x86_sse41_ptestz:
17063 case Intrinsic::x86_sse41_ptestc:
17064 case Intrinsic::x86_sse41_ptestnzc:
17065 case Intrinsic::x86_avx_ptestz_256:
17066 case Intrinsic::x86_avx_ptestc_256:
17067 case Intrinsic::x86_avx_ptestnzc_256:
17068 case Intrinsic::x86_avx_vtestz_ps:
17069 case Intrinsic::x86_avx_vtestc_ps:
17070 case Intrinsic::x86_avx_vtestnzc_ps:
17071 case Intrinsic::x86_avx_vtestz_pd:
17072 case Intrinsic::x86_avx_vtestc_pd:
17073 case Intrinsic::x86_avx_vtestnzc_pd:
17074 case Intrinsic::x86_avx_vtestz_ps_256:
17075 case Intrinsic::x86_avx_vtestc_ps_256:
17076 case Intrinsic::x86_avx_vtestnzc_ps_256:
17077 case Intrinsic::x86_avx_vtestz_pd_256:
17078 case Intrinsic::x86_avx_vtestc_pd_256:
17079 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17080 bool IsTestPacked = false;
17083 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17084 case Intrinsic::x86_avx_vtestz_ps:
17085 case Intrinsic::x86_avx_vtestz_pd:
17086 case Intrinsic::x86_avx_vtestz_ps_256:
17087 case Intrinsic::x86_avx_vtestz_pd_256:
17088 IsTestPacked = true; // Fallthrough
17089 case Intrinsic::x86_sse41_ptestz:
17090 case Intrinsic::x86_avx_ptestz_256:
17092 X86CC = X86::COND_E;
17094 case Intrinsic::x86_avx_vtestc_ps:
17095 case Intrinsic::x86_avx_vtestc_pd:
17096 case Intrinsic::x86_avx_vtestc_ps_256:
17097 case Intrinsic::x86_avx_vtestc_pd_256:
17098 IsTestPacked = true; // Fallthrough
17099 case Intrinsic::x86_sse41_ptestc:
17100 case Intrinsic::x86_avx_ptestc_256:
17102 X86CC = X86::COND_B;
17104 case Intrinsic::x86_avx_vtestnzc_ps:
17105 case Intrinsic::x86_avx_vtestnzc_pd:
17106 case Intrinsic::x86_avx_vtestnzc_ps_256:
17107 case Intrinsic::x86_avx_vtestnzc_pd_256:
17108 IsTestPacked = true; // Fallthrough
17109 case Intrinsic::x86_sse41_ptestnzc:
17110 case Intrinsic::x86_avx_ptestnzc_256:
17112 X86CC = X86::COND_A;
17116 SDValue LHS = Op.getOperand(1);
17117 SDValue RHS = Op.getOperand(2);
17118 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17119 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17120 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17121 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17122 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17124 case Intrinsic::x86_avx512_kortestz_w:
17125 case Intrinsic::x86_avx512_kortestc_w: {
17126 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17127 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17128 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17129 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17130 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17131 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17132 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17135 case Intrinsic::x86_sse42_pcmpistria128:
17136 case Intrinsic::x86_sse42_pcmpestria128:
17137 case Intrinsic::x86_sse42_pcmpistric128:
17138 case Intrinsic::x86_sse42_pcmpestric128:
17139 case Intrinsic::x86_sse42_pcmpistrio128:
17140 case Intrinsic::x86_sse42_pcmpestrio128:
17141 case Intrinsic::x86_sse42_pcmpistris128:
17142 case Intrinsic::x86_sse42_pcmpestris128:
17143 case Intrinsic::x86_sse42_pcmpistriz128:
17144 case Intrinsic::x86_sse42_pcmpestriz128: {
17148 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17149 case Intrinsic::x86_sse42_pcmpistria128:
17150 Opcode = X86ISD::PCMPISTRI;
17151 X86CC = X86::COND_A;
17153 case Intrinsic::x86_sse42_pcmpestria128:
17154 Opcode = X86ISD::PCMPESTRI;
17155 X86CC = X86::COND_A;
17157 case Intrinsic::x86_sse42_pcmpistric128:
17158 Opcode = X86ISD::PCMPISTRI;
17159 X86CC = X86::COND_B;
17161 case Intrinsic::x86_sse42_pcmpestric128:
17162 Opcode = X86ISD::PCMPESTRI;
17163 X86CC = X86::COND_B;
17165 case Intrinsic::x86_sse42_pcmpistrio128:
17166 Opcode = X86ISD::PCMPISTRI;
17167 X86CC = X86::COND_O;
17169 case Intrinsic::x86_sse42_pcmpestrio128:
17170 Opcode = X86ISD::PCMPESTRI;
17171 X86CC = X86::COND_O;
17173 case Intrinsic::x86_sse42_pcmpistris128:
17174 Opcode = X86ISD::PCMPISTRI;
17175 X86CC = X86::COND_S;
17177 case Intrinsic::x86_sse42_pcmpestris128:
17178 Opcode = X86ISD::PCMPESTRI;
17179 X86CC = X86::COND_S;
17181 case Intrinsic::x86_sse42_pcmpistriz128:
17182 Opcode = X86ISD::PCMPISTRI;
17183 X86CC = X86::COND_E;
17185 case Intrinsic::x86_sse42_pcmpestriz128:
17186 Opcode = X86ISD::PCMPESTRI;
17187 X86CC = X86::COND_E;
17190 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17191 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17192 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17193 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17194 DAG.getConstant(X86CC, MVT::i8),
17195 SDValue(PCMP.getNode(), 1));
17196 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17199 case Intrinsic::x86_sse42_pcmpistri128:
17200 case Intrinsic::x86_sse42_pcmpestri128: {
17202 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17203 Opcode = X86ISD::PCMPISTRI;
17205 Opcode = X86ISD::PCMPESTRI;
17207 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17208 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17209 return DAG.getNode(Opcode, dl, VTs, NewOps);
17212 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17213 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17214 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17215 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17216 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17217 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17218 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17219 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17220 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17221 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17222 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17223 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17224 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17225 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17226 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17227 dl, Op.getValueType(),
17231 Op.getOperand(4), Op.getOperand(1),
17237 case Intrinsic::x86_fma_vfmadd_ps:
17238 case Intrinsic::x86_fma_vfmadd_pd:
17239 case Intrinsic::x86_fma_vfmsub_ps:
17240 case Intrinsic::x86_fma_vfmsub_pd:
17241 case Intrinsic::x86_fma_vfnmadd_ps:
17242 case Intrinsic::x86_fma_vfnmadd_pd:
17243 case Intrinsic::x86_fma_vfnmsub_ps:
17244 case Intrinsic::x86_fma_vfnmsub_pd:
17245 case Intrinsic::x86_fma_vfmaddsub_ps:
17246 case Intrinsic::x86_fma_vfmaddsub_pd:
17247 case Intrinsic::x86_fma_vfmsubadd_ps:
17248 case Intrinsic::x86_fma_vfmsubadd_pd:
17249 case Intrinsic::x86_fma_vfmadd_ps_256:
17250 case Intrinsic::x86_fma_vfmadd_pd_256:
17251 case Intrinsic::x86_fma_vfmsub_ps_256:
17252 case Intrinsic::x86_fma_vfmsub_pd_256:
17253 case Intrinsic::x86_fma_vfnmadd_ps_256:
17254 case Intrinsic::x86_fma_vfnmadd_pd_256:
17255 case Intrinsic::x86_fma_vfnmsub_ps_256:
17256 case Intrinsic::x86_fma_vfnmsub_pd_256:
17257 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17258 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17259 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17260 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17261 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17262 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17266 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17267 SDValue Src, SDValue Mask, SDValue Base,
17268 SDValue Index, SDValue ScaleOp, SDValue Chain,
17269 const X86Subtarget * Subtarget) {
17271 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17272 assert(C && "Invalid scale type");
17273 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17274 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17275 Index.getSimpleValueType().getVectorNumElements());
17277 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17279 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17281 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17282 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17283 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17284 SDValue Segment = DAG.getRegister(0, MVT::i32);
17285 if (Src.getOpcode() == ISD::UNDEF)
17286 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17287 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17288 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17289 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17290 return DAG.getMergeValues(RetOps, dl);
17293 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17294 SDValue Src, SDValue Mask, SDValue Base,
17295 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17297 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17298 assert(C && "Invalid scale type");
17299 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17300 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17301 SDValue Segment = DAG.getRegister(0, MVT::i32);
17302 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17303 Index.getSimpleValueType().getVectorNumElements());
17305 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17307 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17309 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17310 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17311 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17312 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17313 return SDValue(Res, 1);
17316 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17317 SDValue Mask, SDValue Base, SDValue Index,
17318 SDValue ScaleOp, SDValue Chain) {
17320 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17321 assert(C && "Invalid scale type");
17322 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17323 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17324 SDValue Segment = DAG.getRegister(0, MVT::i32);
17326 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17328 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17330 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17332 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17333 //SDVTList VTs = DAG.getVTList(MVT::Other);
17334 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17335 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17336 return SDValue(Res, 0);
17339 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17340 // read performance monitor counters (x86_rdpmc).
17341 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17342 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17343 SmallVectorImpl<SDValue> &Results) {
17344 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17345 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17348 // The ECX register is used to select the index of the performance counter
17350 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17352 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17354 // Reads the content of a 64-bit performance counter and returns it in the
17355 // registers EDX:EAX.
17356 if (Subtarget->is64Bit()) {
17357 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17358 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17361 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17362 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17365 Chain = HI.getValue(1);
17367 if (Subtarget->is64Bit()) {
17368 // The EAX register is loaded with the low-order 32 bits. The EDX register
17369 // is loaded with the supported high-order bits of the counter.
17370 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17371 DAG.getConstant(32, MVT::i8));
17372 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17373 Results.push_back(Chain);
17377 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17378 SDValue Ops[] = { LO, HI };
17379 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17380 Results.push_back(Pair);
17381 Results.push_back(Chain);
17384 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17385 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17386 // also used to custom lower READCYCLECOUNTER nodes.
17387 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17388 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17389 SmallVectorImpl<SDValue> &Results) {
17390 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17391 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17394 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17395 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17396 // and the EAX register is loaded with the low-order 32 bits.
17397 if (Subtarget->is64Bit()) {
17398 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17399 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17402 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17403 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17406 SDValue Chain = HI.getValue(1);
17408 if (Opcode == X86ISD::RDTSCP_DAG) {
17409 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17411 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17412 // the ECX register. Add 'ecx' explicitly to the chain.
17413 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17415 // Explicitly store the content of ECX at the location passed in input
17416 // to the 'rdtscp' intrinsic.
17417 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17418 MachinePointerInfo(), false, false, 0);
17421 if (Subtarget->is64Bit()) {
17422 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17423 // the EAX register is loaded with the low-order 32 bits.
17424 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17425 DAG.getConstant(32, MVT::i8));
17426 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17427 Results.push_back(Chain);
17431 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17432 SDValue Ops[] = { LO, HI };
17433 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17434 Results.push_back(Pair);
17435 Results.push_back(Chain);
17438 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17439 SelectionDAG &DAG) {
17440 SmallVector<SDValue, 2> Results;
17442 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17444 return DAG.getMergeValues(Results, DL);
17448 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17449 SelectionDAG &DAG) {
17450 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17452 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17457 switch(IntrData->Type) {
17459 llvm_unreachable("Unknown Intrinsic Type");
17463 // Emit the node with the right value type.
17464 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17465 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17467 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17468 // Otherwise return the value from Rand, which is always 0, casted to i32.
17469 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17470 DAG.getConstant(1, Op->getValueType(1)),
17471 DAG.getConstant(X86::COND_B, MVT::i32),
17472 SDValue(Result.getNode(), 1) };
17473 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17474 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17477 // Return { result, isValid, chain }.
17478 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17479 SDValue(Result.getNode(), 2));
17482 //gather(v1, mask, index, base, scale);
17483 SDValue Chain = Op.getOperand(0);
17484 SDValue Src = Op.getOperand(2);
17485 SDValue Base = Op.getOperand(3);
17486 SDValue Index = Op.getOperand(4);
17487 SDValue Mask = Op.getOperand(5);
17488 SDValue Scale = Op.getOperand(6);
17489 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17493 //scatter(base, mask, index, v1, scale);
17494 SDValue Chain = Op.getOperand(0);
17495 SDValue Base = Op.getOperand(2);
17496 SDValue Mask = Op.getOperand(3);
17497 SDValue Index = Op.getOperand(4);
17498 SDValue Src = Op.getOperand(5);
17499 SDValue Scale = Op.getOperand(6);
17500 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17503 SDValue Hint = Op.getOperand(6);
17505 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17506 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17507 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17508 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17509 SDValue Chain = Op.getOperand(0);
17510 SDValue Mask = Op.getOperand(2);
17511 SDValue Index = Op.getOperand(3);
17512 SDValue Base = Op.getOperand(4);
17513 SDValue Scale = Op.getOperand(5);
17514 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17516 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17518 SmallVector<SDValue, 2> Results;
17519 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17520 return DAG.getMergeValues(Results, dl);
17522 // Read Performance Monitoring Counters.
17524 SmallVector<SDValue, 2> Results;
17525 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17526 return DAG.getMergeValues(Results, dl);
17528 // XTEST intrinsics.
17530 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17531 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17532 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17533 DAG.getConstant(X86::COND_NE, MVT::i8),
17535 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17536 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17537 Ret, SDValue(InTrans.getNode(), 1));
17541 SmallVector<SDValue, 2> Results;
17542 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17543 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17544 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17545 DAG.getConstant(-1, MVT::i8));
17546 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17547 Op.getOperand(4), GenCF.getValue(1));
17548 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17549 Op.getOperand(5), MachinePointerInfo(),
17551 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17552 DAG.getConstant(X86::COND_B, MVT::i8),
17554 Results.push_back(SetCC);
17555 Results.push_back(Store);
17556 return DAG.getMergeValues(Results, dl);
17558 case COMPRESS_TO_MEM: {
17560 SDValue Mask = Op.getOperand(4);
17561 SDValue DataToCompress = Op.getOperand(3);
17562 SDValue Addr = Op.getOperand(2);
17563 SDValue Chain = Op.getOperand(0);
17565 if (isAllOnes(Mask)) // return just a store
17566 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17567 MachinePointerInfo(), false, false, 0);
17569 EVT VT = DataToCompress.getValueType();
17570 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17571 VT.getVectorNumElements());
17572 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17573 Mask.getValueType().getSizeInBits());
17574 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17575 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17576 DAG.getIntPtrConstant(0));
17578 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17579 DataToCompress, DAG.getUNDEF(VT));
17580 return DAG.getStore(Chain, dl, Compressed, Addr,
17581 MachinePointerInfo(), false, false, 0);
17583 case EXPAND_FROM_MEM: {
17585 SDValue Mask = Op.getOperand(4);
17586 SDValue PathThru = Op.getOperand(3);
17587 SDValue Addr = Op.getOperand(2);
17588 SDValue Chain = Op.getOperand(0);
17589 EVT VT = Op.getValueType();
17591 if (isAllOnes(Mask)) // return just a load
17592 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17594 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17595 VT.getVectorNumElements());
17596 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17597 Mask.getValueType().getSizeInBits());
17598 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17599 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17600 DAG.getIntPtrConstant(0));
17602 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17603 false, false, false, 0);
17605 SmallVector<SDValue, 2> Results;
17606 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17608 Results.push_back(Chain);
17609 return DAG.getMergeValues(Results, dl);
17614 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17615 SelectionDAG &DAG) const {
17616 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17617 MFI->setReturnAddressIsTaken(true);
17619 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17622 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17624 EVT PtrVT = getPointerTy();
17627 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17628 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17629 DAG.getSubtarget().getRegisterInfo());
17630 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17631 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17632 DAG.getNode(ISD::ADD, dl, PtrVT,
17633 FrameAddr, Offset),
17634 MachinePointerInfo(), false, false, false, 0);
17637 // Just load the return address.
17638 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17639 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17640 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17643 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17644 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17645 MFI->setFrameAddressIsTaken(true);
17647 EVT VT = Op.getValueType();
17648 SDLoc dl(Op); // FIXME probably not meaningful
17649 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17650 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17651 DAG.getSubtarget().getRegisterInfo());
17652 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17653 DAG.getMachineFunction());
17654 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17655 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17656 "Invalid Frame Register!");
17657 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17659 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17660 MachinePointerInfo(),
17661 false, false, false, 0);
17665 // FIXME? Maybe this could be a TableGen attribute on some registers and
17666 // this table could be generated automatically from RegInfo.
17667 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17669 unsigned Reg = StringSwitch<unsigned>(RegName)
17670 .Case("esp", X86::ESP)
17671 .Case("rsp", X86::RSP)
17675 report_fatal_error("Invalid register name global variable");
17678 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17679 SelectionDAG &DAG) const {
17680 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17681 DAG.getSubtarget().getRegisterInfo());
17682 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17685 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17686 SDValue Chain = Op.getOperand(0);
17687 SDValue Offset = Op.getOperand(1);
17688 SDValue Handler = Op.getOperand(2);
17691 EVT PtrVT = getPointerTy();
17692 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17693 DAG.getSubtarget().getRegisterInfo());
17694 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17695 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17696 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17697 "Invalid Frame Register!");
17698 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17699 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17701 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17702 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17703 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17704 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17706 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17708 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17709 DAG.getRegister(StoreAddrReg, PtrVT));
17712 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17713 SelectionDAG &DAG) const {
17715 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17716 DAG.getVTList(MVT::i32, MVT::Other),
17717 Op.getOperand(0), Op.getOperand(1));
17720 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17721 SelectionDAG &DAG) const {
17723 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17724 Op.getOperand(0), Op.getOperand(1));
17727 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17728 return Op.getOperand(0);
17731 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17732 SelectionDAG &DAG) const {
17733 SDValue Root = Op.getOperand(0);
17734 SDValue Trmp = Op.getOperand(1); // trampoline
17735 SDValue FPtr = Op.getOperand(2); // nested function
17736 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17739 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17740 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17742 if (Subtarget->is64Bit()) {
17743 SDValue OutChains[6];
17745 // Large code-model.
17746 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17747 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17749 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17750 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17752 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17754 // Load the pointer to the nested function into R11.
17755 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17756 SDValue Addr = Trmp;
17757 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17758 Addr, MachinePointerInfo(TrmpAddr),
17761 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17762 DAG.getConstant(2, MVT::i64));
17763 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17764 MachinePointerInfo(TrmpAddr, 2),
17767 // Load the 'nest' parameter value into R10.
17768 // R10 is specified in X86CallingConv.td
17769 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17771 DAG.getConstant(10, MVT::i64));
17772 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17773 Addr, MachinePointerInfo(TrmpAddr, 10),
17776 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17777 DAG.getConstant(12, MVT::i64));
17778 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17779 MachinePointerInfo(TrmpAddr, 12),
17782 // Jump to the nested function.
17783 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17784 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17785 DAG.getConstant(20, MVT::i64));
17786 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17787 Addr, MachinePointerInfo(TrmpAddr, 20),
17790 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17792 DAG.getConstant(22, MVT::i64));
17793 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17794 MachinePointerInfo(TrmpAddr, 22),
17797 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17799 const Function *Func =
17800 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17801 CallingConv::ID CC = Func->getCallingConv();
17806 llvm_unreachable("Unsupported calling convention");
17807 case CallingConv::C:
17808 case CallingConv::X86_StdCall: {
17809 // Pass 'nest' parameter in ECX.
17810 // Must be kept in sync with X86CallingConv.td
17811 NestReg = X86::ECX;
17813 // Check that ECX wasn't needed by an 'inreg' parameter.
17814 FunctionType *FTy = Func->getFunctionType();
17815 const AttributeSet &Attrs = Func->getAttributes();
17817 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17818 unsigned InRegCount = 0;
17821 for (FunctionType::param_iterator I = FTy->param_begin(),
17822 E = FTy->param_end(); I != E; ++I, ++Idx)
17823 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17824 // FIXME: should only count parameters that are lowered to integers.
17825 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17827 if (InRegCount > 2) {
17828 report_fatal_error("Nest register in use - reduce number of inreg"
17834 case CallingConv::X86_FastCall:
17835 case CallingConv::X86_ThisCall:
17836 case CallingConv::Fast:
17837 // Pass 'nest' parameter in EAX.
17838 // Must be kept in sync with X86CallingConv.td
17839 NestReg = X86::EAX;
17843 SDValue OutChains[4];
17844 SDValue Addr, Disp;
17846 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17847 DAG.getConstant(10, MVT::i32));
17848 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17850 // This is storing the opcode for MOV32ri.
17851 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17852 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17853 OutChains[0] = DAG.getStore(Root, dl,
17854 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17855 Trmp, MachinePointerInfo(TrmpAddr),
17858 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17859 DAG.getConstant(1, MVT::i32));
17860 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17861 MachinePointerInfo(TrmpAddr, 1),
17864 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17865 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17866 DAG.getConstant(5, MVT::i32));
17867 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17868 MachinePointerInfo(TrmpAddr, 5),
17871 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17872 DAG.getConstant(6, MVT::i32));
17873 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17874 MachinePointerInfo(TrmpAddr, 6),
17877 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17881 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17882 SelectionDAG &DAG) const {
17884 The rounding mode is in bits 11:10 of FPSR, and has the following
17886 00 Round to nearest
17891 FLT_ROUNDS, on the other hand, expects the following:
17898 To perform the conversion, we do:
17899 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17902 MachineFunction &MF = DAG.getMachineFunction();
17903 const TargetMachine &TM = MF.getTarget();
17904 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17905 unsigned StackAlignment = TFI.getStackAlignment();
17906 MVT VT = Op.getSimpleValueType();
17909 // Save FP Control Word to stack slot
17910 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17911 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17913 MachineMemOperand *MMO =
17914 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17915 MachineMemOperand::MOStore, 2, 2);
17917 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17918 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17919 DAG.getVTList(MVT::Other),
17920 Ops, MVT::i16, MMO);
17922 // Load FP Control Word from stack slot
17923 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17924 MachinePointerInfo(), false, false, false, 0);
17926 // Transform as necessary
17928 DAG.getNode(ISD::SRL, DL, MVT::i16,
17929 DAG.getNode(ISD::AND, DL, MVT::i16,
17930 CWD, DAG.getConstant(0x800, MVT::i16)),
17931 DAG.getConstant(11, MVT::i8));
17933 DAG.getNode(ISD::SRL, DL, MVT::i16,
17934 DAG.getNode(ISD::AND, DL, MVT::i16,
17935 CWD, DAG.getConstant(0x400, MVT::i16)),
17936 DAG.getConstant(9, MVT::i8));
17939 DAG.getNode(ISD::AND, DL, MVT::i16,
17940 DAG.getNode(ISD::ADD, DL, MVT::i16,
17941 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17942 DAG.getConstant(1, MVT::i16)),
17943 DAG.getConstant(3, MVT::i16));
17945 return DAG.getNode((VT.getSizeInBits() < 16 ?
17946 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17949 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17950 MVT VT = Op.getSimpleValueType();
17952 unsigned NumBits = VT.getSizeInBits();
17955 Op = Op.getOperand(0);
17956 if (VT == MVT::i8) {
17957 // Zero extend to i32 since there is not an i8 bsr.
17959 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17962 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17963 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17964 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17966 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17969 DAG.getConstant(NumBits+NumBits-1, OpVT),
17970 DAG.getConstant(X86::COND_E, MVT::i8),
17973 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17975 // Finally xor with NumBits-1.
17976 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17979 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17983 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17984 MVT VT = Op.getSimpleValueType();
17986 unsigned NumBits = VT.getSizeInBits();
17989 Op = Op.getOperand(0);
17990 if (VT == MVT::i8) {
17991 // Zero extend to i32 since there is not an i8 bsr.
17993 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17996 // Issue a bsr (scan bits in reverse).
17997 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17998 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18000 // And xor with NumBits-1.
18001 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18004 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18008 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18009 MVT VT = Op.getSimpleValueType();
18010 unsigned NumBits = VT.getSizeInBits();
18012 Op = Op.getOperand(0);
18014 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18015 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18016 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18018 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18021 DAG.getConstant(NumBits, VT),
18022 DAG.getConstant(X86::COND_E, MVT::i8),
18025 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18028 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18029 // ones, and then concatenate the result back.
18030 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18031 MVT VT = Op.getSimpleValueType();
18033 assert(VT.is256BitVector() && VT.isInteger() &&
18034 "Unsupported value type for operation");
18036 unsigned NumElems = VT.getVectorNumElements();
18039 // Extract the LHS vectors
18040 SDValue LHS = Op.getOperand(0);
18041 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18042 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18044 // Extract the RHS vectors
18045 SDValue RHS = Op.getOperand(1);
18046 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18047 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18049 MVT EltVT = VT.getVectorElementType();
18050 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18052 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18053 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18054 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18057 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18058 assert(Op.getSimpleValueType().is256BitVector() &&
18059 Op.getSimpleValueType().isInteger() &&
18060 "Only handle AVX 256-bit vector integer operation");
18061 return Lower256IntArith(Op, DAG);
18064 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18065 assert(Op.getSimpleValueType().is256BitVector() &&
18066 Op.getSimpleValueType().isInteger() &&
18067 "Only handle AVX 256-bit vector integer operation");
18068 return Lower256IntArith(Op, DAG);
18071 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18072 SelectionDAG &DAG) {
18074 MVT VT = Op.getSimpleValueType();
18076 // Decompose 256-bit ops into smaller 128-bit ops.
18077 if (VT.is256BitVector() && !Subtarget->hasInt256())
18078 return Lower256IntArith(Op, DAG);
18080 SDValue A = Op.getOperand(0);
18081 SDValue B = Op.getOperand(1);
18083 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18084 if (VT == MVT::v4i32) {
18085 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18086 "Should not custom lower when pmuldq is available!");
18088 // Extract the odd parts.
18089 static const int UnpackMask[] = { 1, -1, 3, -1 };
18090 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18091 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18093 // Multiply the even parts.
18094 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18095 // Now multiply odd parts.
18096 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18098 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18099 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18101 // Merge the two vectors back together with a shuffle. This expands into 2
18103 static const int ShufMask[] = { 0, 4, 2, 6 };
18104 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18107 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18108 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18110 // Ahi = psrlqi(a, 32);
18111 // Bhi = psrlqi(b, 32);
18113 // AloBlo = pmuludq(a, b);
18114 // AloBhi = pmuludq(a, Bhi);
18115 // AhiBlo = pmuludq(Ahi, b);
18117 // AloBhi = psllqi(AloBhi, 32);
18118 // AhiBlo = psllqi(AhiBlo, 32);
18119 // return AloBlo + AloBhi + AhiBlo;
18121 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18122 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18124 // Bit cast to 32-bit vectors for MULUDQ
18125 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18126 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18127 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18128 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18129 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18130 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18132 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18133 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18134 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18136 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18137 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18139 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18140 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18143 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18144 assert(Subtarget->isTargetWin64() && "Unexpected target");
18145 EVT VT = Op.getValueType();
18146 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18147 "Unexpected return type for lowering");
18151 switch (Op->getOpcode()) {
18152 default: llvm_unreachable("Unexpected request for libcall!");
18153 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18154 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18155 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18156 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18157 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18158 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18162 SDValue InChain = DAG.getEntryNode();
18164 TargetLowering::ArgListTy Args;
18165 TargetLowering::ArgListEntry Entry;
18166 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18167 EVT ArgVT = Op->getOperand(i).getValueType();
18168 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18169 "Unexpected argument type for lowering");
18170 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18171 Entry.Node = StackPtr;
18172 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18174 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18175 Entry.Ty = PointerType::get(ArgTy,0);
18176 Entry.isSExt = false;
18177 Entry.isZExt = false;
18178 Args.push_back(Entry);
18181 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18184 TargetLowering::CallLoweringInfo CLI(DAG);
18185 CLI.setDebugLoc(dl).setChain(InChain)
18186 .setCallee(getLibcallCallingConv(LC),
18187 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18188 Callee, std::move(Args), 0)
18189 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18191 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18192 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18195 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18196 SelectionDAG &DAG) {
18197 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18198 EVT VT = Op0.getValueType();
18201 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18202 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18204 // PMULxD operations multiply each even value (starting at 0) of LHS with
18205 // the related value of RHS and produce a widen result.
18206 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18207 // => <2 x i64> <ae|cg>
18209 // In other word, to have all the results, we need to perform two PMULxD:
18210 // 1. one with the even values.
18211 // 2. one with the odd values.
18212 // To achieve #2, with need to place the odd values at an even position.
18214 // Place the odd value at an even position (basically, shift all values 1
18215 // step to the left):
18216 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18217 // <a|b|c|d> => <b|undef|d|undef>
18218 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18219 // <e|f|g|h> => <f|undef|h|undef>
18220 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18222 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18224 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18225 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18227 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18228 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18229 // => <2 x i64> <ae|cg>
18230 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18231 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18232 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18233 // => <2 x i64> <bf|dh>
18234 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18235 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18237 // Shuffle it back into the right order.
18238 SDValue Highs, Lows;
18239 if (VT == MVT::v8i32) {
18240 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18241 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18242 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18243 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18245 const int HighMask[] = {1, 5, 3, 7};
18246 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18247 const int LowMask[] = {0, 4, 2, 6};
18248 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18251 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18252 // unsigned multiply.
18253 if (IsSigned && !Subtarget->hasSSE41()) {
18255 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18256 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18257 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18258 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18259 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18261 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18262 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18265 // The first result of MUL_LOHI is actually the low value, followed by the
18267 SDValue Ops[] = {Lows, Highs};
18268 return DAG.getMergeValues(Ops, dl);
18271 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18272 const X86Subtarget *Subtarget) {
18273 MVT VT = Op.getSimpleValueType();
18275 SDValue R = Op.getOperand(0);
18276 SDValue Amt = Op.getOperand(1);
18278 // Optimize shl/srl/sra with constant shift amount.
18279 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18280 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18281 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18283 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18284 (Subtarget->hasInt256() &&
18285 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18286 (Subtarget->hasAVX512() &&
18287 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18288 if (Op.getOpcode() == ISD::SHL)
18289 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18291 if (Op.getOpcode() == ISD::SRL)
18292 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18294 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18295 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18299 if (VT == MVT::v16i8) {
18300 if (Op.getOpcode() == ISD::SHL) {
18301 // Make a large shift.
18302 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18303 MVT::v8i16, R, ShiftAmt,
18305 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18306 // Zero out the rightmost bits.
18307 SmallVector<SDValue, 16> V(16,
18308 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18310 return DAG.getNode(ISD::AND, dl, VT, SHL,
18311 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18313 if (Op.getOpcode() == ISD::SRL) {
18314 // Make a large shift.
18315 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18316 MVT::v8i16, R, ShiftAmt,
18318 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18319 // Zero out the leftmost bits.
18320 SmallVector<SDValue, 16> V(16,
18321 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18323 return DAG.getNode(ISD::AND, dl, VT, SRL,
18324 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18326 if (Op.getOpcode() == ISD::SRA) {
18327 if (ShiftAmt == 7) {
18328 // R s>> 7 === R s< 0
18329 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18330 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18333 // R s>> a === ((R u>> a) ^ m) - m
18334 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18335 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18337 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18338 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18339 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18342 llvm_unreachable("Unknown shift opcode.");
18345 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18346 if (Op.getOpcode() == ISD::SHL) {
18347 // Make a large shift.
18348 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18349 MVT::v16i16, R, ShiftAmt,
18351 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18352 // Zero out the rightmost bits.
18353 SmallVector<SDValue, 32> V(32,
18354 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18356 return DAG.getNode(ISD::AND, dl, VT, SHL,
18357 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18359 if (Op.getOpcode() == ISD::SRL) {
18360 // Make a large shift.
18361 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18362 MVT::v16i16, R, ShiftAmt,
18364 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18365 // Zero out the leftmost bits.
18366 SmallVector<SDValue, 32> V(32,
18367 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18369 return DAG.getNode(ISD::AND, dl, VT, SRL,
18370 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18372 if (Op.getOpcode() == ISD::SRA) {
18373 if (ShiftAmt == 7) {
18374 // R s>> 7 === R s< 0
18375 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18376 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18379 // R s>> a === ((R u>> a) ^ m) - m
18380 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18381 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18383 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18384 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18385 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18388 llvm_unreachable("Unknown shift opcode.");
18393 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18394 if (!Subtarget->is64Bit() &&
18395 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18396 Amt.getOpcode() == ISD::BITCAST &&
18397 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18398 Amt = Amt.getOperand(0);
18399 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18400 VT.getVectorNumElements();
18401 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18402 uint64_t ShiftAmt = 0;
18403 for (unsigned i = 0; i != Ratio; ++i) {
18404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18408 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18410 // Check remaining shift amounts.
18411 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18412 uint64_t ShAmt = 0;
18413 for (unsigned j = 0; j != Ratio; ++j) {
18414 ConstantSDNode *C =
18415 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18419 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18421 if (ShAmt != ShiftAmt)
18424 switch (Op.getOpcode()) {
18426 llvm_unreachable("Unknown shift opcode!");
18428 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18431 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18434 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18442 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18443 const X86Subtarget* Subtarget) {
18444 MVT VT = Op.getSimpleValueType();
18446 SDValue R = Op.getOperand(0);
18447 SDValue Amt = Op.getOperand(1);
18449 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18450 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18451 (Subtarget->hasInt256() &&
18452 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18453 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18454 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18456 EVT EltVT = VT.getVectorElementType();
18458 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18459 // Check if this build_vector node is doing a splat.
18460 // If so, then set BaseShAmt equal to the splat value.
18461 BaseShAmt = BV->getSplatValue();
18462 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18463 BaseShAmt = SDValue();
18465 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18466 Amt = Amt.getOperand(0);
18468 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18469 if (SVN && SVN->isSplat()) {
18470 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18471 SDValue InVec = Amt.getOperand(0);
18472 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18473 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18474 "Unexpected shuffle index found!");
18475 BaseShAmt = InVec.getOperand(SplatIdx);
18476 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18477 if (ConstantSDNode *C =
18478 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18479 if (C->getZExtValue() == SplatIdx)
18480 BaseShAmt = InVec.getOperand(1);
18485 // Avoid introducing an extract element from a shuffle.
18486 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18487 DAG.getIntPtrConstant(SplatIdx));
18491 if (BaseShAmt.getNode()) {
18492 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18493 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18494 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18495 else if (EltVT.bitsLT(MVT::i32))
18496 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18498 switch (Op.getOpcode()) {
18500 llvm_unreachable("Unknown shift opcode!");
18502 switch (VT.SimpleTy) {
18503 default: return SDValue();
18512 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18515 switch (VT.SimpleTy) {
18516 default: return SDValue();
18523 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18526 switch (VT.SimpleTy) {
18527 default: return SDValue();
18536 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18542 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18543 if (!Subtarget->is64Bit() &&
18544 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18545 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18546 Amt.getOpcode() == ISD::BITCAST &&
18547 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18548 Amt = Amt.getOperand(0);
18549 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18550 VT.getVectorNumElements();
18551 std::vector<SDValue> Vals(Ratio);
18552 for (unsigned i = 0; i != Ratio; ++i)
18553 Vals[i] = Amt.getOperand(i);
18554 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18555 for (unsigned j = 0; j != Ratio; ++j)
18556 if (Vals[j] != Amt.getOperand(i + j))
18559 switch (Op.getOpcode()) {
18561 llvm_unreachable("Unknown shift opcode!");
18563 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18565 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18567 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18574 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18575 SelectionDAG &DAG) {
18576 MVT VT = Op.getSimpleValueType();
18578 SDValue R = Op.getOperand(0);
18579 SDValue Amt = Op.getOperand(1);
18582 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18583 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18585 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18589 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18593 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18595 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18596 if (Subtarget->hasInt256()) {
18597 if (Op.getOpcode() == ISD::SRL &&
18598 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18599 VT == MVT::v4i64 || VT == MVT::v8i32))
18601 if (Op.getOpcode() == ISD::SHL &&
18602 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18603 VT == MVT::v4i64 || VT == MVT::v8i32))
18605 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18609 // If possible, lower this packed shift into a vector multiply instead of
18610 // expanding it into a sequence of scalar shifts.
18611 // Do this only if the vector shift count is a constant build_vector.
18612 if (Op.getOpcode() == ISD::SHL &&
18613 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18614 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18615 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18616 SmallVector<SDValue, 8> Elts;
18617 EVT SVT = VT.getScalarType();
18618 unsigned SVTBits = SVT.getSizeInBits();
18619 const APInt &One = APInt(SVTBits, 1);
18620 unsigned NumElems = VT.getVectorNumElements();
18622 for (unsigned i=0; i !=NumElems; ++i) {
18623 SDValue Op = Amt->getOperand(i);
18624 if (Op->getOpcode() == ISD::UNDEF) {
18625 Elts.push_back(Op);
18629 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18630 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18631 uint64_t ShAmt = C.getZExtValue();
18632 if (ShAmt >= SVTBits) {
18633 Elts.push_back(DAG.getUNDEF(SVT));
18636 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18638 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18639 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18642 // Lower SHL with variable shift amount.
18643 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18644 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18646 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18647 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18648 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18649 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18652 // If possible, lower this shift as a sequence of two shifts by
18653 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18655 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18657 // Could be rewritten as:
18658 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18660 // The advantage is that the two shifts from the example would be
18661 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18662 // the vector shift into four scalar shifts plus four pairs of vector
18664 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18665 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18666 unsigned TargetOpcode = X86ISD::MOVSS;
18667 bool CanBeSimplified;
18668 // The splat value for the first packed shift (the 'X' from the example).
18669 SDValue Amt1 = Amt->getOperand(0);
18670 // The splat value for the second packed shift (the 'Y' from the example).
18671 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18672 Amt->getOperand(2);
18674 // See if it is possible to replace this node with a sequence of
18675 // two shifts followed by a MOVSS/MOVSD
18676 if (VT == MVT::v4i32) {
18677 // Check if it is legal to use a MOVSS.
18678 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18679 Amt2 == Amt->getOperand(3);
18680 if (!CanBeSimplified) {
18681 // Otherwise, check if we can still simplify this node using a MOVSD.
18682 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18683 Amt->getOperand(2) == Amt->getOperand(3);
18684 TargetOpcode = X86ISD::MOVSD;
18685 Amt2 = Amt->getOperand(2);
18688 // Do similar checks for the case where the machine value type
18690 CanBeSimplified = Amt1 == Amt->getOperand(1);
18691 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18692 CanBeSimplified = Amt2 == Amt->getOperand(i);
18694 if (!CanBeSimplified) {
18695 TargetOpcode = X86ISD::MOVSD;
18696 CanBeSimplified = true;
18697 Amt2 = Amt->getOperand(4);
18698 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18699 CanBeSimplified = Amt1 == Amt->getOperand(i);
18700 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18701 CanBeSimplified = Amt2 == Amt->getOperand(j);
18705 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18706 isa<ConstantSDNode>(Amt2)) {
18707 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18708 EVT CastVT = MVT::v4i32;
18710 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18711 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18713 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18714 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18715 if (TargetOpcode == X86ISD::MOVSD)
18716 CastVT = MVT::v2i64;
18717 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18718 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18719 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18721 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18725 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18726 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18729 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18730 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18732 // Turn 'a' into a mask suitable for VSELECT
18733 SDValue VSelM = DAG.getConstant(0x80, VT);
18734 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18735 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18737 SDValue CM1 = DAG.getConstant(0x0f, VT);
18738 SDValue CM2 = DAG.getConstant(0x3f, VT);
18740 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18741 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18742 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18743 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18744 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18747 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18748 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18749 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18751 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18752 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18753 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18754 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18755 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18758 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18759 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18760 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18762 // return VSELECT(r, r+r, a);
18763 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18764 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18768 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18769 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18770 // solution better.
18771 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18772 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18774 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18775 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18776 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18777 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18778 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18781 // Decompose 256-bit shifts into smaller 128-bit shifts.
18782 if (VT.is256BitVector()) {
18783 unsigned NumElems = VT.getVectorNumElements();
18784 MVT EltVT = VT.getVectorElementType();
18785 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18787 // Extract the two vectors
18788 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18789 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18791 // Recreate the shift amount vectors
18792 SDValue Amt1, Amt2;
18793 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18794 // Constant shift amount
18795 SmallVector<SDValue, 4> Amt1Csts;
18796 SmallVector<SDValue, 4> Amt2Csts;
18797 for (unsigned i = 0; i != NumElems/2; ++i)
18798 Amt1Csts.push_back(Amt->getOperand(i));
18799 for (unsigned i = NumElems/2; i != NumElems; ++i)
18800 Amt2Csts.push_back(Amt->getOperand(i));
18802 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18803 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18805 // Variable shift amount
18806 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18807 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18810 // Issue new vector shifts for the smaller types
18811 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18812 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18814 // Concatenate the result back
18815 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18821 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18822 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18823 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18824 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18825 // has only one use.
18826 SDNode *N = Op.getNode();
18827 SDValue LHS = N->getOperand(0);
18828 SDValue RHS = N->getOperand(1);
18829 unsigned BaseOp = 0;
18832 switch (Op.getOpcode()) {
18833 default: llvm_unreachable("Unknown ovf instruction!");
18835 // A subtract of one will be selected as a INC. Note that INC doesn't
18836 // set CF, so we can't do this for UADDO.
18837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18839 BaseOp = X86ISD::INC;
18840 Cond = X86::COND_O;
18843 BaseOp = X86ISD::ADD;
18844 Cond = X86::COND_O;
18847 BaseOp = X86ISD::ADD;
18848 Cond = X86::COND_B;
18851 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18852 // set CF, so we can't do this for USUBO.
18853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18855 BaseOp = X86ISD::DEC;
18856 Cond = X86::COND_O;
18859 BaseOp = X86ISD::SUB;
18860 Cond = X86::COND_O;
18863 BaseOp = X86ISD::SUB;
18864 Cond = X86::COND_B;
18867 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18868 Cond = X86::COND_O;
18870 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18871 if (N->getValueType(0) == MVT::i8) {
18872 BaseOp = X86ISD::UMUL8;
18873 Cond = X86::COND_O;
18876 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18878 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18881 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18882 DAG.getConstant(X86::COND_O, MVT::i32),
18883 SDValue(Sum.getNode(), 2));
18885 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18889 // Also sets EFLAGS.
18890 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18891 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18894 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18895 DAG.getConstant(Cond, MVT::i32),
18896 SDValue(Sum.getNode(), 1));
18898 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18901 // Sign extension of the low part of vector elements. This may be used either
18902 // when sign extend instructions are not available or if the vector element
18903 // sizes already match the sign-extended size. If the vector elements are in
18904 // their pre-extended size and sign extend instructions are available, that will
18905 // be handled by LowerSIGN_EXTEND.
18906 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18907 SelectionDAG &DAG) const {
18909 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18910 MVT VT = Op.getSimpleValueType();
18912 if (!Subtarget->hasSSE2() || !VT.isVector())
18915 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18916 ExtraVT.getScalarType().getSizeInBits();
18918 switch (VT.SimpleTy) {
18919 default: return SDValue();
18922 if (!Subtarget->hasFp256())
18924 if (!Subtarget->hasInt256()) {
18925 // needs to be split
18926 unsigned NumElems = VT.getVectorNumElements();
18928 // Extract the LHS vectors
18929 SDValue LHS = Op.getOperand(0);
18930 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18931 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18933 MVT EltVT = VT.getVectorElementType();
18934 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18936 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18937 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18938 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18940 SDValue Extra = DAG.getValueType(ExtraVT);
18942 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18943 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18945 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18950 SDValue Op0 = Op.getOperand(0);
18952 // This is a sign extension of some low part of vector elements without
18953 // changing the size of the vector elements themselves:
18954 // Shift-Left + Shift-Right-Algebraic.
18955 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18957 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18963 /// Returns true if the operand type is exactly twice the native width, and
18964 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18965 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18966 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18967 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18968 const X86Subtarget &Subtarget =
18969 getTargetMachine().getSubtarget<X86Subtarget>();
18970 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18973 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18974 else if (OpWidth == 128)
18975 return Subtarget.hasCmpxchg16b();
18980 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18981 return needsCmpXchgNb(SI->getValueOperand()->getType());
18984 // Note: this turns large loads into lock cmpxchg8b/16b.
18985 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18986 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18987 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18988 return needsCmpXchgNb(PTy->getElementType());
18991 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18992 const X86Subtarget &Subtarget =
18993 getTargetMachine().getSubtarget<X86Subtarget>();
18994 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18995 const Type *MemType = AI->getType();
18997 // If the operand is too big, we must see if cmpxchg8/16b is available
18998 // and default to library calls otherwise.
18999 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19000 return needsCmpXchgNb(MemType);
19002 AtomicRMWInst::BinOp Op = AI->getOperation();
19005 llvm_unreachable("Unknown atomic operation");
19006 case AtomicRMWInst::Xchg:
19007 case AtomicRMWInst::Add:
19008 case AtomicRMWInst::Sub:
19009 // It's better to use xadd, xsub or xchg for these in all cases.
19011 case AtomicRMWInst::Or:
19012 case AtomicRMWInst::And:
19013 case AtomicRMWInst::Xor:
19014 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19015 // prefix to a normal instruction for these operations.
19016 return !AI->use_empty();
19017 case AtomicRMWInst::Nand:
19018 case AtomicRMWInst::Max:
19019 case AtomicRMWInst::Min:
19020 case AtomicRMWInst::UMax:
19021 case AtomicRMWInst::UMin:
19022 // These always require a non-trivial set of data operations on x86. We must
19023 // use a cmpxchg loop.
19028 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19029 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19030 // no-sse2). There isn't any reason to disable it if the target processor
19032 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19036 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19037 const X86Subtarget &Subtarget =
19038 getTargetMachine().getSubtarget<X86Subtarget>();
19039 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19040 const Type *MemType = AI->getType();
19041 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19042 // there is no benefit in turning such RMWs into loads, and it is actually
19043 // harmful as it introduces a mfence.
19044 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19047 auto Builder = IRBuilder<>(AI);
19048 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19049 auto SynchScope = AI->getSynchScope();
19050 // We must restrict the ordering to avoid generating loads with Release or
19051 // ReleaseAcquire orderings.
19052 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19053 auto Ptr = AI->getPointerOperand();
19055 // Before the load we need a fence. Here is an example lifted from
19056 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19059 // x.store(1, relaxed);
19060 // r1 = y.fetch_add(0, release);
19062 // y.fetch_add(42, acquire);
19063 // r2 = x.load(relaxed);
19064 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19065 // lowered to just a load without a fence. A mfence flushes the store buffer,
19066 // making the optimization clearly correct.
19067 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19068 // otherwise, we might be able to be more agressive on relaxed idempotent
19069 // rmw. In practice, they do not look useful, so we don't try to be
19070 // especially clever.
19071 if (SynchScope == SingleThread) {
19072 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19073 // the IR level, so we must wrap it in an intrinsic.
19075 } else if (hasMFENCE(Subtarget)) {
19076 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19077 Intrinsic::x86_sse2_mfence);
19078 Builder.CreateCall(MFence);
19080 // FIXME: it might make sense to use a locked operation here but on a
19081 // different cache-line to prevent cache-line bouncing. In practice it
19082 // is probably a small win, and x86 processors without mfence are rare
19083 // enough that we do not bother.
19087 // Finally we can emit the atomic load.
19088 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19089 AI->getType()->getPrimitiveSizeInBits());
19090 Loaded->setAtomic(Order, SynchScope);
19091 AI->replaceAllUsesWith(Loaded);
19092 AI->eraseFromParent();
19096 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19097 SelectionDAG &DAG) {
19099 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19100 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19101 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19102 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19104 // The only fence that needs an instruction is a sequentially-consistent
19105 // cross-thread fence.
19106 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19107 if (hasMFENCE(*Subtarget))
19108 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19110 SDValue Chain = Op.getOperand(0);
19111 SDValue Zero = DAG.getConstant(0, MVT::i32);
19113 DAG.getRegister(X86::ESP, MVT::i32), // Base
19114 DAG.getTargetConstant(1, MVT::i8), // Scale
19115 DAG.getRegister(0, MVT::i32), // Index
19116 DAG.getTargetConstant(0, MVT::i32), // Disp
19117 DAG.getRegister(0, MVT::i32), // Segment.
19121 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19122 return SDValue(Res, 0);
19125 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19126 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19129 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19130 SelectionDAG &DAG) {
19131 MVT T = Op.getSimpleValueType();
19135 switch(T.SimpleTy) {
19136 default: llvm_unreachable("Invalid value type!");
19137 case MVT::i8: Reg = X86::AL; size = 1; break;
19138 case MVT::i16: Reg = X86::AX; size = 2; break;
19139 case MVT::i32: Reg = X86::EAX; size = 4; break;
19141 assert(Subtarget->is64Bit() && "Node not type legal!");
19142 Reg = X86::RAX; size = 8;
19145 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19146 Op.getOperand(2), SDValue());
19147 SDValue Ops[] = { cpIn.getValue(0),
19150 DAG.getTargetConstant(size, MVT::i8),
19151 cpIn.getValue(1) };
19152 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19153 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19154 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19158 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19159 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19160 MVT::i32, cpOut.getValue(2));
19161 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19162 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19164 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19165 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19166 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19170 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19171 SelectionDAG &DAG) {
19172 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19173 MVT DstVT = Op.getSimpleValueType();
19175 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19176 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19177 if (DstVT != MVT::f64)
19178 // This conversion needs to be expanded.
19181 SDValue InVec = Op->getOperand(0);
19183 unsigned NumElts = SrcVT.getVectorNumElements();
19184 EVT SVT = SrcVT.getVectorElementType();
19186 // Widen the vector in input in the case of MVT::v2i32.
19187 // Example: from MVT::v2i32 to MVT::v4i32.
19188 SmallVector<SDValue, 16> Elts;
19189 for (unsigned i = 0, e = NumElts; i != e; ++i)
19190 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19191 DAG.getIntPtrConstant(i)));
19193 // Explicitly mark the extra elements as Undef.
19194 SDValue Undef = DAG.getUNDEF(SVT);
19195 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19196 Elts.push_back(Undef);
19198 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19199 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19200 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19201 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19202 DAG.getIntPtrConstant(0));
19205 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19206 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19207 assert((DstVT == MVT::i64 ||
19208 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19209 "Unexpected custom BITCAST");
19210 // i64 <=> MMX conversions are Legal.
19211 if (SrcVT==MVT::i64 && DstVT.isVector())
19213 if (DstVT==MVT::i64 && SrcVT.isVector())
19215 // MMX <=> MMX conversions are Legal.
19216 if (SrcVT.isVector() && DstVT.isVector())
19218 // All other conversions need to be expanded.
19222 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19223 SelectionDAG &DAG) {
19224 SDNode *Node = Op.getNode();
19227 Op = Op.getOperand(0);
19228 EVT VT = Op.getValueType();
19229 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19230 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19232 unsigned NumElts = VT.getVectorNumElements();
19233 EVT EltVT = VT.getVectorElementType();
19234 unsigned Len = EltVT.getSizeInBits();
19236 // This is the vectorized version of the "best" algorithm from
19237 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19238 // with a minor tweak to use a series of adds + shifts instead of vector
19239 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19241 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19242 // v8i32 => Always profitable
19244 // FIXME: There a couple of possible improvements:
19246 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19247 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19249 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19250 "CTPOP not implemented for this vector element type.");
19252 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19253 // extra legalization.
19254 bool NeedsBitcast = EltVT == MVT::i32;
19255 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19257 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19258 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19259 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19261 // v = v - ((v >> 1) & 0x55555555...)
19262 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19263 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19264 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19266 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19268 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19269 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19271 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19273 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19274 if (VT != And.getValueType())
19275 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19276 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19278 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19279 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19280 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19281 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19282 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19284 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19285 if (NeedsBitcast) {
19286 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19287 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19288 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19291 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19292 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19293 if (VT != AndRHS.getValueType()) {
19294 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19295 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19297 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19299 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19300 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19301 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19302 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19303 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19305 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19306 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19307 if (NeedsBitcast) {
19308 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19309 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19311 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19312 if (VT != And.getValueType())
19313 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19315 // The algorithm mentioned above uses:
19316 // v = (v * 0x01010101...) >> (Len - 8)
19318 // Change it to use vector adds + vector shifts which yield faster results on
19319 // Haswell than using vector integer multiplication.
19321 // For i32 elements:
19322 // v = v + (v >> 8)
19323 // v = v + (v >> 16)
19325 // For i64 elements:
19326 // v = v + (v >> 8)
19327 // v = v + (v >> 16)
19328 // v = v + (v >> 32)
19331 SmallVector<SDValue, 8> Csts;
19332 for (unsigned i = 8; i <= Len/2; i *= 2) {
19333 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19334 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19335 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19336 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19340 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19341 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19342 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19343 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19344 if (NeedsBitcast) {
19345 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19346 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19348 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19349 if (VT != And.getValueType())
19350 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19355 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19356 SDNode *Node = Op.getNode();
19358 EVT T = Node->getValueType(0);
19359 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19360 DAG.getConstant(0, T), Node->getOperand(2));
19361 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19362 cast<AtomicSDNode>(Node)->getMemoryVT(),
19363 Node->getOperand(0),
19364 Node->getOperand(1), negOp,
19365 cast<AtomicSDNode>(Node)->getMemOperand(),
19366 cast<AtomicSDNode>(Node)->getOrdering(),
19367 cast<AtomicSDNode>(Node)->getSynchScope());
19370 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19371 SDNode *Node = Op.getNode();
19373 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19375 // Convert seq_cst store -> xchg
19376 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19377 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19378 // (The only way to get a 16-byte store is cmpxchg16b)
19379 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19380 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19381 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19382 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19383 cast<AtomicSDNode>(Node)->getMemoryVT(),
19384 Node->getOperand(0),
19385 Node->getOperand(1), Node->getOperand(2),
19386 cast<AtomicSDNode>(Node)->getMemOperand(),
19387 cast<AtomicSDNode>(Node)->getOrdering(),
19388 cast<AtomicSDNode>(Node)->getSynchScope());
19389 return Swap.getValue(1);
19391 // Other atomic stores have a simple pattern.
19395 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19396 EVT VT = Op.getNode()->getSimpleValueType(0);
19398 // Let legalize expand this if it isn't a legal type yet.
19399 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19402 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19405 bool ExtraOp = false;
19406 switch (Op.getOpcode()) {
19407 default: llvm_unreachable("Invalid code");
19408 case ISD::ADDC: Opc = X86ISD::ADD; break;
19409 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19410 case ISD::SUBC: Opc = X86ISD::SUB; break;
19411 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19415 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19417 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19418 Op.getOperand(1), Op.getOperand(2));
19421 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19422 SelectionDAG &DAG) {
19423 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19425 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19426 // which returns the values as { float, float } (in XMM0) or
19427 // { double, double } (which is returned in XMM0, XMM1).
19429 SDValue Arg = Op.getOperand(0);
19430 EVT ArgVT = Arg.getValueType();
19431 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19433 TargetLowering::ArgListTy Args;
19434 TargetLowering::ArgListEntry Entry;
19438 Entry.isSExt = false;
19439 Entry.isZExt = false;
19440 Args.push_back(Entry);
19442 bool isF64 = ArgVT == MVT::f64;
19443 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19444 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19445 // the results are returned via SRet in memory.
19446 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19448 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19450 Type *RetTy = isF64
19451 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19452 : (Type*)VectorType::get(ArgTy, 4);
19454 TargetLowering::CallLoweringInfo CLI(DAG);
19455 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19456 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19458 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19461 // Returned in xmm0 and xmm1.
19462 return CallResult.first;
19464 // Returned in bits 0:31 and 32:64 xmm0.
19465 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19466 CallResult.first, DAG.getIntPtrConstant(0));
19467 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19468 CallResult.first, DAG.getIntPtrConstant(1));
19469 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19470 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19473 /// LowerOperation - Provide custom lowering hooks for some operations.
19475 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19476 switch (Op.getOpcode()) {
19477 default: llvm_unreachable("Should not custom lower this!");
19478 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19479 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19480 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19481 return LowerCMP_SWAP(Op, Subtarget, DAG);
19482 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19483 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19484 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19485 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19486 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19487 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19488 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19489 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19490 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19491 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19492 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19493 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19494 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19495 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19496 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19497 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19498 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19499 case ISD::SHL_PARTS:
19500 case ISD::SRA_PARTS:
19501 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19502 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19503 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19504 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19505 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19506 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19507 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19508 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19509 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19510 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19511 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19513 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19514 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19515 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19516 case ISD::SETCC: return LowerSETCC(Op, DAG);
19517 case ISD::SELECT: return LowerSELECT(Op, DAG);
19518 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19519 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19520 case ISD::VASTART: return LowerVASTART(Op, DAG);
19521 case ISD::VAARG: return LowerVAARG(Op, DAG);
19522 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19523 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19524 case ISD::INTRINSIC_VOID:
19525 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19526 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19527 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19528 case ISD::FRAME_TO_ARGS_OFFSET:
19529 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19530 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19531 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19532 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19533 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19534 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19535 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19536 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19537 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19538 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19539 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19540 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19541 case ISD::UMUL_LOHI:
19542 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19545 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19551 case ISD::UMULO: return LowerXALUO(Op, DAG);
19552 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19553 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19557 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19558 case ISD::ADD: return LowerADD(Op, DAG);
19559 case ISD::SUB: return LowerSUB(Op, DAG);
19560 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19564 /// ReplaceNodeResults - Replace a node with an illegal result type
19565 /// with a new node built out of custom code.
19566 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19567 SmallVectorImpl<SDValue>&Results,
19568 SelectionDAG &DAG) const {
19570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19571 switch (N->getOpcode()) {
19573 llvm_unreachable("Do not know how to custom type legalize this operation!");
19574 case ISD::SIGN_EXTEND_INREG:
19579 // We don't want to expand or promote these.
19586 case ISD::UDIVREM: {
19587 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19588 Results.push_back(V);
19591 case ISD::FP_TO_SINT:
19592 case ISD::FP_TO_UINT: {
19593 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19595 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19598 std::pair<SDValue,SDValue> Vals =
19599 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19600 SDValue FIST = Vals.first, StackSlot = Vals.second;
19601 if (FIST.getNode()) {
19602 EVT VT = N->getValueType(0);
19603 // Return a load from the stack slot.
19604 if (StackSlot.getNode())
19605 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19606 MachinePointerInfo(),
19607 false, false, false, 0));
19609 Results.push_back(FIST);
19613 case ISD::UINT_TO_FP: {
19614 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19615 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19616 N->getValueType(0) != MVT::v2f32)
19618 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19620 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19622 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19623 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19624 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19625 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19626 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19627 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19630 case ISD::FP_ROUND: {
19631 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19633 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19634 Results.push_back(V);
19637 case ISD::INTRINSIC_W_CHAIN: {
19638 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19640 default : llvm_unreachable("Do not know how to custom type "
19641 "legalize this intrinsic operation!");
19642 case Intrinsic::x86_rdtsc:
19643 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19645 case Intrinsic::x86_rdtscp:
19646 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19648 case Intrinsic::x86_rdpmc:
19649 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19652 case ISD::READCYCLECOUNTER: {
19653 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19656 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19657 EVT T = N->getValueType(0);
19658 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19659 bool Regs64bit = T == MVT::i128;
19660 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19661 SDValue cpInL, cpInH;
19662 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19663 DAG.getConstant(0, HalfT));
19664 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19665 DAG.getConstant(1, HalfT));
19666 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19667 Regs64bit ? X86::RAX : X86::EAX,
19669 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19670 Regs64bit ? X86::RDX : X86::EDX,
19671 cpInH, cpInL.getValue(1));
19672 SDValue swapInL, swapInH;
19673 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19674 DAG.getConstant(0, HalfT));
19675 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19676 DAG.getConstant(1, HalfT));
19677 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19678 Regs64bit ? X86::RBX : X86::EBX,
19679 swapInL, cpInH.getValue(1));
19680 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19681 Regs64bit ? X86::RCX : X86::ECX,
19682 swapInH, swapInL.getValue(1));
19683 SDValue Ops[] = { swapInH.getValue(0),
19685 swapInH.getValue(1) };
19686 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19687 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19688 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19689 X86ISD::LCMPXCHG8_DAG;
19690 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19691 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19692 Regs64bit ? X86::RAX : X86::EAX,
19693 HalfT, Result.getValue(1));
19694 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19695 Regs64bit ? X86::RDX : X86::EDX,
19696 HalfT, cpOutL.getValue(2));
19697 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19699 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19700 MVT::i32, cpOutH.getValue(2));
19702 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19703 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19704 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19706 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19707 Results.push_back(Success);
19708 Results.push_back(EFLAGS.getValue(1));
19711 case ISD::ATOMIC_SWAP:
19712 case ISD::ATOMIC_LOAD_ADD:
19713 case ISD::ATOMIC_LOAD_SUB:
19714 case ISD::ATOMIC_LOAD_AND:
19715 case ISD::ATOMIC_LOAD_OR:
19716 case ISD::ATOMIC_LOAD_XOR:
19717 case ISD::ATOMIC_LOAD_NAND:
19718 case ISD::ATOMIC_LOAD_MIN:
19719 case ISD::ATOMIC_LOAD_MAX:
19720 case ISD::ATOMIC_LOAD_UMIN:
19721 case ISD::ATOMIC_LOAD_UMAX:
19722 case ISD::ATOMIC_LOAD: {
19723 // Delegate to generic TypeLegalization. Situations we can really handle
19724 // should have already been dealt with by AtomicExpandPass.cpp.
19727 case ISD::BITCAST: {
19728 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19729 EVT DstVT = N->getValueType(0);
19730 EVT SrcVT = N->getOperand(0)->getValueType(0);
19732 if (SrcVT != MVT::f64 ||
19733 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19736 unsigned NumElts = DstVT.getVectorNumElements();
19737 EVT SVT = DstVT.getVectorElementType();
19738 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19739 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19740 MVT::v2f64, N->getOperand(0));
19741 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19743 if (ExperimentalVectorWideningLegalization) {
19744 // If we are legalizing vectors by widening, we already have the desired
19745 // legal vector type, just return it.
19746 Results.push_back(ToVecInt);
19750 SmallVector<SDValue, 8> Elts;
19751 for (unsigned i = 0, e = NumElts; i != e; ++i)
19752 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19753 ToVecInt, DAG.getIntPtrConstant(i)));
19755 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19760 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19762 default: return nullptr;
19763 case X86ISD::BSF: return "X86ISD::BSF";
19764 case X86ISD::BSR: return "X86ISD::BSR";
19765 case X86ISD::SHLD: return "X86ISD::SHLD";
19766 case X86ISD::SHRD: return "X86ISD::SHRD";
19767 case X86ISD::FAND: return "X86ISD::FAND";
19768 case X86ISD::FANDN: return "X86ISD::FANDN";
19769 case X86ISD::FOR: return "X86ISD::FOR";
19770 case X86ISD::FXOR: return "X86ISD::FXOR";
19771 case X86ISD::FSRL: return "X86ISD::FSRL";
19772 case X86ISD::FILD: return "X86ISD::FILD";
19773 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19774 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19775 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19776 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19777 case X86ISD::FLD: return "X86ISD::FLD";
19778 case X86ISD::FST: return "X86ISD::FST";
19779 case X86ISD::CALL: return "X86ISD::CALL";
19780 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19781 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19782 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19783 case X86ISD::BT: return "X86ISD::BT";
19784 case X86ISD::CMP: return "X86ISD::CMP";
19785 case X86ISD::COMI: return "X86ISD::COMI";
19786 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19787 case X86ISD::CMPM: return "X86ISD::CMPM";
19788 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19789 case X86ISD::SETCC: return "X86ISD::SETCC";
19790 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19791 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19792 case X86ISD::CMOV: return "X86ISD::CMOV";
19793 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19794 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19795 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19796 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19797 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19798 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19799 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19800 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19801 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19802 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19803 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19804 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19805 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19806 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19807 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19808 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19809 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19810 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19811 case X86ISD::HADD: return "X86ISD::HADD";
19812 case X86ISD::HSUB: return "X86ISD::HSUB";
19813 case X86ISD::FHADD: return "X86ISD::FHADD";
19814 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19815 case X86ISD::UMAX: return "X86ISD::UMAX";
19816 case X86ISD::UMIN: return "X86ISD::UMIN";
19817 case X86ISD::SMAX: return "X86ISD::SMAX";
19818 case X86ISD::SMIN: return "X86ISD::SMIN";
19819 case X86ISD::FMAX: return "X86ISD::FMAX";
19820 case X86ISD::FMIN: return "X86ISD::FMIN";
19821 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19822 case X86ISD::FMINC: return "X86ISD::FMINC";
19823 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19824 case X86ISD::FRCP: return "X86ISD::FRCP";
19825 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19826 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19827 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19828 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19829 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19830 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19831 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19832 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19833 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19834 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19835 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19836 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19837 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19838 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19839 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19840 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19841 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19842 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19843 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19844 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19845 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19846 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19847 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19848 case X86ISD::VSHL: return "X86ISD::VSHL";
19849 case X86ISD::VSRL: return "X86ISD::VSRL";
19850 case X86ISD::VSRA: return "X86ISD::VSRA";
19851 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19852 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19853 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19854 case X86ISD::CMPP: return "X86ISD::CMPP";
19855 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19856 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19857 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19858 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19859 case X86ISD::ADD: return "X86ISD::ADD";
19860 case X86ISD::SUB: return "X86ISD::SUB";
19861 case X86ISD::ADC: return "X86ISD::ADC";
19862 case X86ISD::SBB: return "X86ISD::SBB";
19863 case X86ISD::SMUL: return "X86ISD::SMUL";
19864 case X86ISD::UMUL: return "X86ISD::UMUL";
19865 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19866 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19867 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19868 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19869 case X86ISD::INC: return "X86ISD::INC";
19870 case X86ISD::DEC: return "X86ISD::DEC";
19871 case X86ISD::OR: return "X86ISD::OR";
19872 case X86ISD::XOR: return "X86ISD::XOR";
19873 case X86ISD::AND: return "X86ISD::AND";
19874 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19875 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19876 case X86ISD::PTEST: return "X86ISD::PTEST";
19877 case X86ISD::TESTP: return "X86ISD::TESTP";
19878 case X86ISD::TESTM: return "X86ISD::TESTM";
19879 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19880 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19881 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19882 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19883 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19884 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19885 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19886 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19887 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19888 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19889 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19890 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19891 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19892 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19893 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19894 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19895 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19896 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19897 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19898 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19899 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19900 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19901 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19902 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19903 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19904 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19905 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19906 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19907 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19908 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19909 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19910 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19911 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19912 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19913 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19914 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19915 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19916 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19917 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19918 case X86ISD::SAHF: return "X86ISD::SAHF";
19919 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19920 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19921 case X86ISD::FMADD: return "X86ISD::FMADD";
19922 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19923 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19924 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19925 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19926 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19927 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19928 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19929 case X86ISD::XTEST: return "X86ISD::XTEST";
19930 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19931 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19932 case X86ISD::SELECT: return "X86ISD::SELECT";
19936 // isLegalAddressingMode - Return true if the addressing mode represented
19937 // by AM is legal for this target, for a load/store of the specified type.
19938 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19940 // X86 supports extremely general addressing modes.
19941 CodeModel::Model M = getTargetMachine().getCodeModel();
19942 Reloc::Model R = getTargetMachine().getRelocationModel();
19944 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19945 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19950 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19952 // If a reference to this global requires an extra load, we can't fold it.
19953 if (isGlobalStubReference(GVFlags))
19956 // If BaseGV requires a register for the PIC base, we cannot also have a
19957 // BaseReg specified.
19958 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19961 // If lower 4G is not available, then we must use rip-relative addressing.
19962 if ((M != CodeModel::Small || R != Reloc::Static) &&
19963 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19967 switch (AM.Scale) {
19973 // These scales always work.
19978 // These scales are formed with basereg+scalereg. Only accept if there is
19983 default: // Other stuff never works.
19990 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19991 unsigned Bits = Ty->getScalarSizeInBits();
19993 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19994 // particularly cheaper than those without.
19998 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19999 // variable shifts just as cheap as scalar ones.
20000 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20003 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20004 // fully general vector.
20008 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20009 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20011 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20012 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20013 return NumBits1 > NumBits2;
20016 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20017 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20020 if (!isTypeLegal(EVT::getEVT(Ty1)))
20023 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20025 // Assuming the caller doesn't have a zeroext or signext return parameter,
20026 // truncation all the way down to i1 is valid.
20030 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20031 return isInt<32>(Imm);
20034 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20035 // Can also use sub to handle negated immediates.
20036 return isInt<32>(Imm);
20039 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20040 if (!VT1.isInteger() || !VT2.isInteger())
20042 unsigned NumBits1 = VT1.getSizeInBits();
20043 unsigned NumBits2 = VT2.getSizeInBits();
20044 return NumBits1 > NumBits2;
20047 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20048 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20049 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20052 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20053 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20054 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20057 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20058 EVT VT1 = Val.getValueType();
20059 if (isZExtFree(VT1, VT2))
20062 if (Val.getOpcode() != ISD::LOAD)
20065 if (!VT1.isSimple() || !VT1.isInteger() ||
20066 !VT2.isSimple() || !VT2.isInteger())
20069 switch (VT1.getSimpleVT().SimpleTy) {
20074 // X86 has 8, 16, and 32-bit zero-extending loads.
20082 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20083 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20086 VT = VT.getScalarType();
20088 if (!VT.isSimple())
20091 switch (VT.getSimpleVT().SimpleTy) {
20102 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20103 // i16 instructions are longer (0x66 prefix) and potentially slower.
20104 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20107 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20108 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20109 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20110 /// are assumed to be legal.
20112 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20114 if (!VT.isSimple())
20117 MVT SVT = VT.getSimpleVT();
20119 // Very little shuffling can be done for 64-bit vectors right now.
20120 if (VT.getSizeInBits() == 64)
20123 // If this is a single-input shuffle with no 128 bit lane crossings we can
20124 // lower it into pshufb.
20125 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20126 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20127 bool isLegal = true;
20128 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20129 if (M[I] >= (int)SVT.getVectorNumElements() ||
20130 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20139 // FIXME: blends, shifts.
20140 return (SVT.getVectorNumElements() == 2 ||
20141 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20142 isMOVLMask(M, SVT) ||
20143 isCommutedMOVLMask(M, SVT) ||
20144 isMOVHLPSMask(M, SVT) ||
20145 isSHUFPMask(M, SVT) ||
20146 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20147 isPSHUFDMask(M, SVT) ||
20148 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20149 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20150 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20151 isPALIGNRMask(M, SVT, Subtarget) ||
20152 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20153 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20154 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20155 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20156 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20157 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20161 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20163 if (!VT.isSimple())
20166 MVT SVT = VT.getSimpleVT();
20167 unsigned NumElts = SVT.getVectorNumElements();
20168 // FIXME: This collection of masks seems suspect.
20171 if (NumElts == 4 && SVT.is128BitVector()) {
20172 return (isMOVLMask(Mask, SVT) ||
20173 isCommutedMOVLMask(Mask, SVT, true) ||
20174 isSHUFPMask(Mask, SVT) ||
20175 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20176 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20177 Subtarget->hasInt256()));
20182 //===----------------------------------------------------------------------===//
20183 // X86 Scheduler Hooks
20184 //===----------------------------------------------------------------------===//
20186 /// Utility function to emit xbegin specifying the start of an RTM region.
20187 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20188 const TargetInstrInfo *TII) {
20189 DebugLoc DL = MI->getDebugLoc();
20191 const BasicBlock *BB = MBB->getBasicBlock();
20192 MachineFunction::iterator I = MBB;
20195 // For the v = xbegin(), we generate
20206 MachineBasicBlock *thisMBB = MBB;
20207 MachineFunction *MF = MBB->getParent();
20208 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20209 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20210 MF->insert(I, mainMBB);
20211 MF->insert(I, sinkMBB);
20213 // Transfer the remainder of BB and its successor edges to sinkMBB.
20214 sinkMBB->splice(sinkMBB->begin(), MBB,
20215 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20216 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20220 // # fallthrough to mainMBB
20221 // # abortion to sinkMBB
20222 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20223 thisMBB->addSuccessor(mainMBB);
20224 thisMBB->addSuccessor(sinkMBB);
20228 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20229 mainMBB->addSuccessor(sinkMBB);
20232 // EAX is live into the sinkMBB
20233 sinkMBB->addLiveIn(X86::EAX);
20234 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20235 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20238 MI->eraseFromParent();
20242 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20243 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20244 // in the .td file.
20245 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20246 const TargetInstrInfo *TII) {
20248 switch (MI->getOpcode()) {
20249 default: llvm_unreachable("illegal opcode!");
20250 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20251 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20252 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20253 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20254 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20255 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20256 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20257 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20260 DebugLoc dl = MI->getDebugLoc();
20261 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20263 unsigned NumArgs = MI->getNumOperands();
20264 for (unsigned i = 1; i < NumArgs; ++i) {
20265 MachineOperand &Op = MI->getOperand(i);
20266 if (!(Op.isReg() && Op.isImplicit()))
20267 MIB.addOperand(Op);
20269 if (MI->hasOneMemOperand())
20270 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20272 BuildMI(*BB, MI, dl,
20273 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20274 .addReg(X86::XMM0);
20276 MI->eraseFromParent();
20280 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20281 // defs in an instruction pattern
20282 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20283 const TargetInstrInfo *TII) {
20285 switch (MI->getOpcode()) {
20286 default: llvm_unreachable("illegal opcode!");
20287 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20288 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20289 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20290 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20291 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20292 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20293 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20294 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20297 DebugLoc dl = MI->getDebugLoc();
20298 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20300 unsigned NumArgs = MI->getNumOperands(); // remove the results
20301 for (unsigned i = 1; i < NumArgs; ++i) {
20302 MachineOperand &Op = MI->getOperand(i);
20303 if (!(Op.isReg() && Op.isImplicit()))
20304 MIB.addOperand(Op);
20306 if (MI->hasOneMemOperand())
20307 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20309 BuildMI(*BB, MI, dl,
20310 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20313 MI->eraseFromParent();
20317 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20318 const TargetInstrInfo *TII,
20319 const X86Subtarget* Subtarget) {
20320 DebugLoc dl = MI->getDebugLoc();
20322 // Address into RAX/EAX, other two args into ECX, EDX.
20323 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20324 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20325 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20326 for (int i = 0; i < X86::AddrNumOperands; ++i)
20327 MIB.addOperand(MI->getOperand(i));
20329 unsigned ValOps = X86::AddrNumOperands;
20330 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20331 .addReg(MI->getOperand(ValOps).getReg());
20332 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20333 .addReg(MI->getOperand(ValOps+1).getReg());
20335 // The instruction doesn't actually take any operands though.
20336 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20338 MI->eraseFromParent(); // The pseudo is gone now.
20342 MachineBasicBlock *
20343 X86TargetLowering::EmitVAARG64WithCustomInserter(
20345 MachineBasicBlock *MBB) const {
20346 // Emit va_arg instruction on X86-64.
20348 // Operands to this pseudo-instruction:
20349 // 0 ) Output : destination address (reg)
20350 // 1-5) Input : va_list address (addr, i64mem)
20351 // 6 ) ArgSize : Size (in bytes) of vararg type
20352 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20353 // 8 ) Align : Alignment of type
20354 // 9 ) EFLAGS (implicit-def)
20356 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20357 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20359 unsigned DestReg = MI->getOperand(0).getReg();
20360 MachineOperand &Base = MI->getOperand(1);
20361 MachineOperand &Scale = MI->getOperand(2);
20362 MachineOperand &Index = MI->getOperand(3);
20363 MachineOperand &Disp = MI->getOperand(4);
20364 MachineOperand &Segment = MI->getOperand(5);
20365 unsigned ArgSize = MI->getOperand(6).getImm();
20366 unsigned ArgMode = MI->getOperand(7).getImm();
20367 unsigned Align = MI->getOperand(8).getImm();
20369 // Memory Reference
20370 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20371 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20372 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20374 // Machine Information
20375 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20376 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20377 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20378 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20379 DebugLoc DL = MI->getDebugLoc();
20381 // struct va_list {
20384 // i64 overflow_area (address)
20385 // i64 reg_save_area (address)
20387 // sizeof(va_list) = 24
20388 // alignment(va_list) = 8
20390 unsigned TotalNumIntRegs = 6;
20391 unsigned TotalNumXMMRegs = 8;
20392 bool UseGPOffset = (ArgMode == 1);
20393 bool UseFPOffset = (ArgMode == 2);
20394 unsigned MaxOffset = TotalNumIntRegs * 8 +
20395 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20397 /* Align ArgSize to a multiple of 8 */
20398 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20399 bool NeedsAlign = (Align > 8);
20401 MachineBasicBlock *thisMBB = MBB;
20402 MachineBasicBlock *overflowMBB;
20403 MachineBasicBlock *offsetMBB;
20404 MachineBasicBlock *endMBB;
20406 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20407 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20408 unsigned OffsetReg = 0;
20410 if (!UseGPOffset && !UseFPOffset) {
20411 // If we only pull from the overflow region, we don't create a branch.
20412 // We don't need to alter control flow.
20413 OffsetDestReg = 0; // unused
20414 OverflowDestReg = DestReg;
20416 offsetMBB = nullptr;
20417 overflowMBB = thisMBB;
20420 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20421 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20422 // If not, pull from overflow_area. (branch to overflowMBB)
20427 // offsetMBB overflowMBB
20432 // Registers for the PHI in endMBB
20433 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20434 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20436 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20437 MachineFunction *MF = MBB->getParent();
20438 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20439 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20440 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20442 MachineFunction::iterator MBBIter = MBB;
20445 // Insert the new basic blocks
20446 MF->insert(MBBIter, offsetMBB);
20447 MF->insert(MBBIter, overflowMBB);
20448 MF->insert(MBBIter, endMBB);
20450 // Transfer the remainder of MBB and its successor edges to endMBB.
20451 endMBB->splice(endMBB->begin(), thisMBB,
20452 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20453 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20455 // Make offsetMBB and overflowMBB successors of thisMBB
20456 thisMBB->addSuccessor(offsetMBB);
20457 thisMBB->addSuccessor(overflowMBB);
20459 // endMBB is a successor of both offsetMBB and overflowMBB
20460 offsetMBB->addSuccessor(endMBB);
20461 overflowMBB->addSuccessor(endMBB);
20463 // Load the offset value into a register
20464 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20465 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20469 .addDisp(Disp, UseFPOffset ? 4 : 0)
20470 .addOperand(Segment)
20471 .setMemRefs(MMOBegin, MMOEnd);
20473 // Check if there is enough room left to pull this argument.
20474 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20476 .addImm(MaxOffset + 8 - ArgSizeA8);
20478 // Branch to "overflowMBB" if offset >= max
20479 // Fall through to "offsetMBB" otherwise
20480 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20481 .addMBB(overflowMBB);
20484 // In offsetMBB, emit code to use the reg_save_area.
20486 assert(OffsetReg != 0);
20488 // Read the reg_save_area address.
20489 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20490 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20495 .addOperand(Segment)
20496 .setMemRefs(MMOBegin, MMOEnd);
20498 // Zero-extend the offset
20499 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20500 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20503 .addImm(X86::sub_32bit);
20505 // Add the offset to the reg_save_area to get the final address.
20506 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20507 .addReg(OffsetReg64)
20508 .addReg(RegSaveReg);
20510 // Compute the offset for the next argument
20511 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20512 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20514 .addImm(UseFPOffset ? 16 : 8);
20516 // Store it back into the va_list.
20517 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20521 .addDisp(Disp, UseFPOffset ? 4 : 0)
20522 .addOperand(Segment)
20523 .addReg(NextOffsetReg)
20524 .setMemRefs(MMOBegin, MMOEnd);
20527 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20532 // Emit code to use overflow area
20535 // Load the overflow_area address into a register.
20536 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20537 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20542 .addOperand(Segment)
20543 .setMemRefs(MMOBegin, MMOEnd);
20545 // If we need to align it, do so. Otherwise, just copy the address
20546 // to OverflowDestReg.
20548 // Align the overflow address
20549 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20550 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20552 // aligned_addr = (addr + (align-1)) & ~(align-1)
20553 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20554 .addReg(OverflowAddrReg)
20557 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20559 .addImm(~(uint64_t)(Align-1));
20561 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20562 .addReg(OverflowAddrReg);
20565 // Compute the next overflow address after this argument.
20566 // (the overflow address should be kept 8-byte aligned)
20567 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20568 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20569 .addReg(OverflowDestReg)
20570 .addImm(ArgSizeA8);
20572 // Store the new overflow address.
20573 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20578 .addOperand(Segment)
20579 .addReg(NextAddrReg)
20580 .setMemRefs(MMOBegin, MMOEnd);
20582 // If we branched, emit the PHI to the front of endMBB.
20584 BuildMI(*endMBB, endMBB->begin(), DL,
20585 TII->get(X86::PHI), DestReg)
20586 .addReg(OffsetDestReg).addMBB(offsetMBB)
20587 .addReg(OverflowDestReg).addMBB(overflowMBB);
20590 // Erase the pseudo instruction
20591 MI->eraseFromParent();
20596 MachineBasicBlock *
20597 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20599 MachineBasicBlock *MBB) const {
20600 // Emit code to save XMM registers to the stack. The ABI says that the
20601 // number of registers to save is given in %al, so it's theoretically
20602 // possible to do an indirect jump trick to avoid saving all of them,
20603 // however this code takes a simpler approach and just executes all
20604 // of the stores if %al is non-zero. It's less code, and it's probably
20605 // easier on the hardware branch predictor, and stores aren't all that
20606 // expensive anyway.
20608 // Create the new basic blocks. One block contains all the XMM stores,
20609 // and one block is the final destination regardless of whether any
20610 // stores were performed.
20611 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20612 MachineFunction *F = MBB->getParent();
20613 MachineFunction::iterator MBBIter = MBB;
20615 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20616 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20617 F->insert(MBBIter, XMMSaveMBB);
20618 F->insert(MBBIter, EndMBB);
20620 // Transfer the remainder of MBB and its successor edges to EndMBB.
20621 EndMBB->splice(EndMBB->begin(), MBB,
20622 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20623 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20625 // The original block will now fall through to the XMM save block.
20626 MBB->addSuccessor(XMMSaveMBB);
20627 // The XMMSaveMBB will fall through to the end block.
20628 XMMSaveMBB->addSuccessor(EndMBB);
20630 // Now add the instructions.
20631 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20632 DebugLoc DL = MI->getDebugLoc();
20634 unsigned CountReg = MI->getOperand(0).getReg();
20635 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20636 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20638 if (!Subtarget->isTargetWin64()) {
20639 // If %al is 0, branch around the XMM save block.
20640 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20641 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20642 MBB->addSuccessor(EndMBB);
20645 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20646 // that was just emitted, but clearly shouldn't be "saved".
20647 assert((MI->getNumOperands() <= 3 ||
20648 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20649 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20650 && "Expected last argument to be EFLAGS");
20651 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20652 // In the XMM save block, save all the XMM argument registers.
20653 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20654 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20655 MachineMemOperand *MMO =
20656 F->getMachineMemOperand(
20657 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20658 MachineMemOperand::MOStore,
20659 /*Size=*/16, /*Align=*/16);
20660 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20661 .addFrameIndex(RegSaveFrameIndex)
20662 .addImm(/*Scale=*/1)
20663 .addReg(/*IndexReg=*/0)
20664 .addImm(/*Disp=*/Offset)
20665 .addReg(/*Segment=*/0)
20666 .addReg(MI->getOperand(i).getReg())
20667 .addMemOperand(MMO);
20670 MI->eraseFromParent(); // The pseudo instruction is gone now.
20675 // The EFLAGS operand of SelectItr might be missing a kill marker
20676 // because there were multiple uses of EFLAGS, and ISel didn't know
20677 // which to mark. Figure out whether SelectItr should have had a
20678 // kill marker, and set it if it should. Returns the correct kill
20680 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20681 MachineBasicBlock* BB,
20682 const TargetRegisterInfo* TRI) {
20683 // Scan forward through BB for a use/def of EFLAGS.
20684 MachineBasicBlock::iterator miI(std::next(SelectItr));
20685 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20686 const MachineInstr& mi = *miI;
20687 if (mi.readsRegister(X86::EFLAGS))
20689 if (mi.definesRegister(X86::EFLAGS))
20690 break; // Should have kill-flag - update below.
20693 // If we hit the end of the block, check whether EFLAGS is live into a
20695 if (miI == BB->end()) {
20696 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20697 sEnd = BB->succ_end();
20698 sItr != sEnd; ++sItr) {
20699 MachineBasicBlock* succ = *sItr;
20700 if (succ->isLiveIn(X86::EFLAGS))
20705 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20706 // out. SelectMI should have a kill flag on EFLAGS.
20707 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20711 MachineBasicBlock *
20712 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20713 MachineBasicBlock *BB) const {
20714 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20715 DebugLoc DL = MI->getDebugLoc();
20717 // To "insert" a SELECT_CC instruction, we actually have to insert the
20718 // diamond control-flow pattern. The incoming instruction knows the
20719 // destination vreg to set, the condition code register to branch on, the
20720 // true/false values to select between, and a branch opcode to use.
20721 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20722 MachineFunction::iterator It = BB;
20728 // cmpTY ccX, r1, r2
20730 // fallthrough --> copy0MBB
20731 MachineBasicBlock *thisMBB = BB;
20732 MachineFunction *F = BB->getParent();
20733 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20734 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20735 F->insert(It, copy0MBB);
20736 F->insert(It, sinkMBB);
20738 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20739 // live into the sink and copy blocks.
20740 const TargetRegisterInfo *TRI =
20741 BB->getParent()->getSubtarget().getRegisterInfo();
20742 if (!MI->killsRegister(X86::EFLAGS) &&
20743 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20744 copy0MBB->addLiveIn(X86::EFLAGS);
20745 sinkMBB->addLiveIn(X86::EFLAGS);
20748 // Transfer the remainder of BB and its successor edges to sinkMBB.
20749 sinkMBB->splice(sinkMBB->begin(), BB,
20750 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20751 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20753 // Add the true and fallthrough blocks as its successors.
20754 BB->addSuccessor(copy0MBB);
20755 BB->addSuccessor(sinkMBB);
20757 // Create the conditional branch instruction.
20759 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20760 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20763 // %FalseValue = ...
20764 // # fallthrough to sinkMBB
20765 copy0MBB->addSuccessor(sinkMBB);
20768 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20770 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20771 TII->get(X86::PHI), MI->getOperand(0).getReg())
20772 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20773 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20775 MI->eraseFromParent(); // The pseudo instruction is gone now.
20779 MachineBasicBlock *
20780 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20781 MachineBasicBlock *BB) const {
20782 MachineFunction *MF = BB->getParent();
20783 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20784 DebugLoc DL = MI->getDebugLoc();
20785 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20787 assert(MF->shouldSplitStack());
20789 const bool Is64Bit = Subtarget->is64Bit();
20790 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20792 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20793 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20796 // ... [Till the alloca]
20797 // If stacklet is not large enough, jump to mallocMBB
20800 // Allocate by subtracting from RSP
20801 // Jump to continueMBB
20804 // Allocate by call to runtime
20808 // [rest of original BB]
20811 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20812 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20813 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20815 MachineRegisterInfo &MRI = MF->getRegInfo();
20816 const TargetRegisterClass *AddrRegClass =
20817 getRegClassFor(getPointerTy());
20819 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20820 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20821 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20822 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20823 sizeVReg = MI->getOperand(1).getReg(),
20824 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20826 MachineFunction::iterator MBBIter = BB;
20829 MF->insert(MBBIter, bumpMBB);
20830 MF->insert(MBBIter, mallocMBB);
20831 MF->insert(MBBIter, continueMBB);
20833 continueMBB->splice(continueMBB->begin(), BB,
20834 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20835 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20837 // Add code to the main basic block to check if the stack limit has been hit,
20838 // and if so, jump to mallocMBB otherwise to bumpMBB.
20839 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20840 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20841 .addReg(tmpSPVReg).addReg(sizeVReg);
20842 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20843 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20844 .addReg(SPLimitVReg);
20845 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20847 // bumpMBB simply decreases the stack pointer, since we know the current
20848 // stacklet has enough space.
20849 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20850 .addReg(SPLimitVReg);
20851 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20852 .addReg(SPLimitVReg);
20853 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20855 // Calls into a routine in libgcc to allocate more space from the heap.
20856 const uint32_t *RegMask = MF->getTarget()
20857 .getSubtargetImpl()
20858 ->getRegisterInfo()
20859 ->getCallPreservedMask(CallingConv::C);
20861 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20863 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20864 .addExternalSymbol("__morestack_allocate_stack_space")
20865 .addRegMask(RegMask)
20866 .addReg(X86::RDI, RegState::Implicit)
20867 .addReg(X86::RAX, RegState::ImplicitDefine);
20868 } else if (Is64Bit) {
20869 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20871 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20872 .addExternalSymbol("__morestack_allocate_stack_space")
20873 .addRegMask(RegMask)
20874 .addReg(X86::EDI, RegState::Implicit)
20875 .addReg(X86::EAX, RegState::ImplicitDefine);
20877 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20879 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20880 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20881 .addExternalSymbol("__morestack_allocate_stack_space")
20882 .addRegMask(RegMask)
20883 .addReg(X86::EAX, RegState::ImplicitDefine);
20887 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20890 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20891 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20892 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20894 // Set up the CFG correctly.
20895 BB->addSuccessor(bumpMBB);
20896 BB->addSuccessor(mallocMBB);
20897 mallocMBB->addSuccessor(continueMBB);
20898 bumpMBB->addSuccessor(continueMBB);
20900 // Take care of the PHI nodes.
20901 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20902 MI->getOperand(0).getReg())
20903 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20904 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20906 // Delete the original pseudo instruction.
20907 MI->eraseFromParent();
20910 return continueMBB;
20913 MachineBasicBlock *
20914 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20915 MachineBasicBlock *BB) const {
20916 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20917 DebugLoc DL = MI->getDebugLoc();
20919 assert(!Subtarget->isTargetMachO());
20921 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20922 // non-trivial part is impdef of ESP.
20924 if (Subtarget->isTargetWin64()) {
20925 if (Subtarget->isTargetCygMing()) {
20926 // ___chkstk(Mingw64):
20927 // Clobbers R10, R11, RAX and EFLAGS.
20929 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20930 .addExternalSymbol("___chkstk")
20931 .addReg(X86::RAX, RegState::Implicit)
20932 .addReg(X86::RSP, RegState::Implicit)
20933 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20934 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20935 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20937 // __chkstk(MSVCRT): does not update stack pointer.
20938 // Clobbers R10, R11 and EFLAGS.
20939 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20940 .addExternalSymbol("__chkstk")
20941 .addReg(X86::RAX, RegState::Implicit)
20942 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20943 // RAX has the offset to be subtracted from RSP.
20944 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20949 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20950 Subtarget->isTargetWindowsItanium())
20954 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20955 .addExternalSymbol(StackProbeSymbol)
20956 .addReg(X86::EAX, RegState::Implicit)
20957 .addReg(X86::ESP, RegState::Implicit)
20958 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20959 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20960 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20963 MI->eraseFromParent(); // The pseudo instruction is gone now.
20967 MachineBasicBlock *
20968 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20969 MachineBasicBlock *BB) const {
20970 // This is pretty easy. We're taking the value that we received from
20971 // our load from the relocation, sticking it in either RDI (x86-64)
20972 // or EAX and doing an indirect call. The return value will then
20973 // be in the normal return register.
20974 MachineFunction *F = BB->getParent();
20975 const X86InstrInfo *TII =
20976 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20977 DebugLoc DL = MI->getDebugLoc();
20979 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20980 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20982 // Get a register mask for the lowered call.
20983 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20984 // proper register mask.
20985 const uint32_t *RegMask = F->getTarget()
20986 .getSubtargetImpl()
20987 ->getRegisterInfo()
20988 ->getCallPreservedMask(CallingConv::C);
20989 if (Subtarget->is64Bit()) {
20990 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20991 TII->get(X86::MOV64rm), X86::RDI)
20993 .addImm(0).addReg(0)
20994 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20995 MI->getOperand(3).getTargetFlags())
20997 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20998 addDirectMem(MIB, X86::RDI);
20999 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21000 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21001 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21002 TII->get(X86::MOV32rm), X86::EAX)
21004 .addImm(0).addReg(0)
21005 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21006 MI->getOperand(3).getTargetFlags())
21008 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21009 addDirectMem(MIB, X86::EAX);
21010 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21012 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21013 TII->get(X86::MOV32rm), X86::EAX)
21014 .addReg(TII->getGlobalBaseReg(F))
21015 .addImm(0).addReg(0)
21016 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21017 MI->getOperand(3).getTargetFlags())
21019 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21020 addDirectMem(MIB, X86::EAX);
21021 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21024 MI->eraseFromParent(); // The pseudo instruction is gone now.
21028 MachineBasicBlock *
21029 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21030 MachineBasicBlock *MBB) const {
21031 DebugLoc DL = MI->getDebugLoc();
21032 MachineFunction *MF = MBB->getParent();
21033 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21034 MachineRegisterInfo &MRI = MF->getRegInfo();
21036 const BasicBlock *BB = MBB->getBasicBlock();
21037 MachineFunction::iterator I = MBB;
21040 // Memory Reference
21041 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21042 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21045 unsigned MemOpndSlot = 0;
21047 unsigned CurOp = 0;
21049 DstReg = MI->getOperand(CurOp++).getReg();
21050 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21051 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21052 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21053 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21055 MemOpndSlot = CurOp;
21057 MVT PVT = getPointerTy();
21058 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21059 "Invalid Pointer Size!");
21061 // For v = setjmp(buf), we generate
21064 // buf[LabelOffset] = restoreMBB
21065 // SjLjSetup restoreMBB
21071 // v = phi(main, restore)
21074 // if base pointer being used, load it from frame
21077 MachineBasicBlock *thisMBB = MBB;
21078 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21079 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21080 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21081 MF->insert(I, mainMBB);
21082 MF->insert(I, sinkMBB);
21083 MF->push_back(restoreMBB);
21085 MachineInstrBuilder MIB;
21087 // Transfer the remainder of BB and its successor edges to sinkMBB.
21088 sinkMBB->splice(sinkMBB->begin(), MBB,
21089 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21090 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21093 unsigned PtrStoreOpc = 0;
21094 unsigned LabelReg = 0;
21095 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21096 Reloc::Model RM = MF->getTarget().getRelocationModel();
21097 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21098 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21100 // Prepare IP either in reg or imm.
21101 if (!UseImmLabel) {
21102 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21103 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21104 LabelReg = MRI.createVirtualRegister(PtrRC);
21105 if (Subtarget->is64Bit()) {
21106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21110 .addMBB(restoreMBB)
21113 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21114 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21115 .addReg(XII->getGlobalBaseReg(MF))
21118 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21122 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21124 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21125 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21126 if (i == X86::AddrDisp)
21127 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21129 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21132 MIB.addReg(LabelReg);
21134 MIB.addMBB(restoreMBB);
21135 MIB.setMemRefs(MMOBegin, MMOEnd);
21137 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21138 .addMBB(restoreMBB);
21140 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21141 MF->getSubtarget().getRegisterInfo());
21142 MIB.addRegMask(RegInfo->getNoPreservedMask());
21143 thisMBB->addSuccessor(mainMBB);
21144 thisMBB->addSuccessor(restoreMBB);
21148 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21149 mainMBB->addSuccessor(sinkMBB);
21152 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21153 TII->get(X86::PHI), DstReg)
21154 .addReg(mainDstReg).addMBB(mainMBB)
21155 .addReg(restoreDstReg).addMBB(restoreMBB);
21158 if (RegInfo->hasBasePointer(*MF)) {
21159 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21160 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21161 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21162 X86FI->setRestoreBasePointer(MF);
21163 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21164 unsigned BasePtr = RegInfo->getBaseRegister();
21165 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21166 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21167 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21168 .setMIFlag(MachineInstr::FrameSetup);
21170 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21171 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21172 restoreMBB->addSuccessor(sinkMBB);
21174 MI->eraseFromParent();
21178 MachineBasicBlock *
21179 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21180 MachineBasicBlock *MBB) const {
21181 DebugLoc DL = MI->getDebugLoc();
21182 MachineFunction *MF = MBB->getParent();
21183 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21184 MachineRegisterInfo &MRI = MF->getRegInfo();
21186 // Memory Reference
21187 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21188 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21190 MVT PVT = getPointerTy();
21191 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21192 "Invalid Pointer Size!");
21194 const TargetRegisterClass *RC =
21195 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21196 unsigned Tmp = MRI.createVirtualRegister(RC);
21197 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21198 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21199 MF->getSubtarget().getRegisterInfo());
21200 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21201 unsigned SP = RegInfo->getStackRegister();
21203 MachineInstrBuilder MIB;
21205 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21206 const int64_t SPOffset = 2 * PVT.getStoreSize();
21208 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21209 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21212 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21213 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21214 MIB.addOperand(MI->getOperand(i));
21215 MIB.setMemRefs(MMOBegin, MMOEnd);
21217 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21218 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21219 if (i == X86::AddrDisp)
21220 MIB.addDisp(MI->getOperand(i), LabelOffset);
21222 MIB.addOperand(MI->getOperand(i));
21224 MIB.setMemRefs(MMOBegin, MMOEnd);
21226 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21227 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21228 if (i == X86::AddrDisp)
21229 MIB.addDisp(MI->getOperand(i), SPOffset);
21231 MIB.addOperand(MI->getOperand(i));
21233 MIB.setMemRefs(MMOBegin, MMOEnd);
21235 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21237 MI->eraseFromParent();
21241 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21242 // accumulator loops. Writing back to the accumulator allows the coalescer
21243 // to remove extra copies in the loop.
21244 MachineBasicBlock *
21245 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21246 MachineBasicBlock *MBB) const {
21247 MachineOperand &AddendOp = MI->getOperand(3);
21249 // Bail out early if the addend isn't a register - we can't switch these.
21250 if (!AddendOp.isReg())
21253 MachineFunction &MF = *MBB->getParent();
21254 MachineRegisterInfo &MRI = MF.getRegInfo();
21256 // Check whether the addend is defined by a PHI:
21257 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21258 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21259 if (!AddendDef.isPHI())
21262 // Look for the following pattern:
21264 // %addend = phi [%entry, 0], [%loop, %result]
21266 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21270 // %addend = phi [%entry, 0], [%loop, %result]
21272 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21274 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21275 assert(AddendDef.getOperand(i).isReg());
21276 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21277 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21278 if (&PHISrcInst == MI) {
21279 // Found a matching instruction.
21280 unsigned NewFMAOpc = 0;
21281 switch (MI->getOpcode()) {
21282 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21283 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21284 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21285 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21286 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21287 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21288 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21289 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21290 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21291 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21292 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21293 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21294 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21295 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21296 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21297 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21298 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21299 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21300 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21301 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21303 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21304 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21305 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21306 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21307 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21308 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21309 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21310 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21311 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21312 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21313 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21314 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21315 default: llvm_unreachable("Unrecognized FMA variant.");
21318 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21319 MachineInstrBuilder MIB =
21320 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21321 .addOperand(MI->getOperand(0))
21322 .addOperand(MI->getOperand(3))
21323 .addOperand(MI->getOperand(2))
21324 .addOperand(MI->getOperand(1));
21325 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21326 MI->eraseFromParent();
21333 MachineBasicBlock *
21334 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21335 MachineBasicBlock *BB) const {
21336 switch (MI->getOpcode()) {
21337 default: llvm_unreachable("Unexpected instr type to insert");
21338 case X86::TAILJMPd64:
21339 case X86::TAILJMPr64:
21340 case X86::TAILJMPm64:
21341 llvm_unreachable("TAILJMP64 would not be touched here.");
21342 case X86::TCRETURNdi64:
21343 case X86::TCRETURNri64:
21344 case X86::TCRETURNmi64:
21346 case X86::WIN_ALLOCA:
21347 return EmitLoweredWinAlloca(MI, BB);
21348 case X86::SEG_ALLOCA_32:
21349 case X86::SEG_ALLOCA_64:
21350 return EmitLoweredSegAlloca(MI, BB);
21351 case X86::TLSCall_32:
21352 case X86::TLSCall_64:
21353 return EmitLoweredTLSCall(MI, BB);
21354 case X86::CMOV_GR8:
21355 case X86::CMOV_FR32:
21356 case X86::CMOV_FR64:
21357 case X86::CMOV_V4F32:
21358 case X86::CMOV_V2F64:
21359 case X86::CMOV_V2I64:
21360 case X86::CMOV_V8F32:
21361 case X86::CMOV_V4F64:
21362 case X86::CMOV_V4I64:
21363 case X86::CMOV_V16F32:
21364 case X86::CMOV_V8F64:
21365 case X86::CMOV_V8I64:
21366 case X86::CMOV_GR16:
21367 case X86::CMOV_GR32:
21368 case X86::CMOV_RFP32:
21369 case X86::CMOV_RFP64:
21370 case X86::CMOV_RFP80:
21371 return EmitLoweredSelect(MI, BB);
21373 case X86::FP32_TO_INT16_IN_MEM:
21374 case X86::FP32_TO_INT32_IN_MEM:
21375 case X86::FP32_TO_INT64_IN_MEM:
21376 case X86::FP64_TO_INT16_IN_MEM:
21377 case X86::FP64_TO_INT32_IN_MEM:
21378 case X86::FP64_TO_INT64_IN_MEM:
21379 case X86::FP80_TO_INT16_IN_MEM:
21380 case X86::FP80_TO_INT32_IN_MEM:
21381 case X86::FP80_TO_INT64_IN_MEM: {
21382 MachineFunction *F = BB->getParent();
21383 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21384 DebugLoc DL = MI->getDebugLoc();
21386 // Change the floating point control register to use "round towards zero"
21387 // mode when truncating to an integer value.
21388 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21389 addFrameReference(BuildMI(*BB, MI, DL,
21390 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21392 // Load the old value of the high byte of the control word...
21394 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21395 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21398 // Set the high part to be round to zero...
21399 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21402 // Reload the modified control word now...
21403 addFrameReference(BuildMI(*BB, MI, DL,
21404 TII->get(X86::FLDCW16m)), CWFrameIdx);
21406 // Restore the memory image of control word to original value
21407 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21410 // Get the X86 opcode to use.
21412 switch (MI->getOpcode()) {
21413 default: llvm_unreachable("illegal opcode!");
21414 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21415 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21416 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21417 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21418 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21419 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21420 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21421 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21422 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21426 MachineOperand &Op = MI->getOperand(0);
21428 AM.BaseType = X86AddressMode::RegBase;
21429 AM.Base.Reg = Op.getReg();
21431 AM.BaseType = X86AddressMode::FrameIndexBase;
21432 AM.Base.FrameIndex = Op.getIndex();
21434 Op = MI->getOperand(1);
21436 AM.Scale = Op.getImm();
21437 Op = MI->getOperand(2);
21439 AM.IndexReg = Op.getImm();
21440 Op = MI->getOperand(3);
21441 if (Op.isGlobal()) {
21442 AM.GV = Op.getGlobal();
21444 AM.Disp = Op.getImm();
21446 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21447 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21449 // Reload the original control word now.
21450 addFrameReference(BuildMI(*BB, MI, DL,
21451 TII->get(X86::FLDCW16m)), CWFrameIdx);
21453 MI->eraseFromParent(); // The pseudo instruction is gone now.
21456 // String/text processing lowering.
21457 case X86::PCMPISTRM128REG:
21458 case X86::VPCMPISTRM128REG:
21459 case X86::PCMPISTRM128MEM:
21460 case X86::VPCMPISTRM128MEM:
21461 case X86::PCMPESTRM128REG:
21462 case X86::VPCMPESTRM128REG:
21463 case X86::PCMPESTRM128MEM:
21464 case X86::VPCMPESTRM128MEM:
21465 assert(Subtarget->hasSSE42() &&
21466 "Target must have SSE4.2 or AVX features enabled");
21467 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21469 // String/text processing lowering.
21470 case X86::PCMPISTRIREG:
21471 case X86::VPCMPISTRIREG:
21472 case X86::PCMPISTRIMEM:
21473 case X86::VPCMPISTRIMEM:
21474 case X86::PCMPESTRIREG:
21475 case X86::VPCMPESTRIREG:
21476 case X86::PCMPESTRIMEM:
21477 case X86::VPCMPESTRIMEM:
21478 assert(Subtarget->hasSSE42() &&
21479 "Target must have SSE4.2 or AVX features enabled");
21480 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21482 // Thread synchronization.
21484 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21489 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21491 case X86::VASTART_SAVE_XMM_REGS:
21492 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21494 case X86::VAARG_64:
21495 return EmitVAARG64WithCustomInserter(MI, BB);
21497 case X86::EH_SjLj_SetJmp32:
21498 case X86::EH_SjLj_SetJmp64:
21499 return emitEHSjLjSetJmp(MI, BB);
21501 case X86::EH_SjLj_LongJmp32:
21502 case X86::EH_SjLj_LongJmp64:
21503 return emitEHSjLjLongJmp(MI, BB);
21505 case TargetOpcode::STATEPOINT:
21506 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21507 // this point in the process. We diverge later.
21508 return emitPatchPoint(MI, BB);
21510 case TargetOpcode::STACKMAP:
21511 case TargetOpcode::PATCHPOINT:
21512 return emitPatchPoint(MI, BB);
21514 case X86::VFMADDPDr213r:
21515 case X86::VFMADDPSr213r:
21516 case X86::VFMADDSDr213r:
21517 case X86::VFMADDSSr213r:
21518 case X86::VFMSUBPDr213r:
21519 case X86::VFMSUBPSr213r:
21520 case X86::VFMSUBSDr213r:
21521 case X86::VFMSUBSSr213r:
21522 case X86::VFNMADDPDr213r:
21523 case X86::VFNMADDPSr213r:
21524 case X86::VFNMADDSDr213r:
21525 case X86::VFNMADDSSr213r:
21526 case X86::VFNMSUBPDr213r:
21527 case X86::VFNMSUBPSr213r:
21528 case X86::VFNMSUBSDr213r:
21529 case X86::VFNMSUBSSr213r:
21530 case X86::VFMADDSUBPDr213r:
21531 case X86::VFMADDSUBPSr213r:
21532 case X86::VFMSUBADDPDr213r:
21533 case X86::VFMSUBADDPSr213r:
21534 case X86::VFMADDPDr213rY:
21535 case X86::VFMADDPSr213rY:
21536 case X86::VFMSUBPDr213rY:
21537 case X86::VFMSUBPSr213rY:
21538 case X86::VFNMADDPDr213rY:
21539 case X86::VFNMADDPSr213rY:
21540 case X86::VFNMSUBPDr213rY:
21541 case X86::VFNMSUBPSr213rY:
21542 case X86::VFMADDSUBPDr213rY:
21543 case X86::VFMADDSUBPSr213rY:
21544 case X86::VFMSUBADDPDr213rY:
21545 case X86::VFMSUBADDPSr213rY:
21546 return emitFMA3Instr(MI, BB);
21550 //===----------------------------------------------------------------------===//
21551 // X86 Optimization Hooks
21552 //===----------------------------------------------------------------------===//
21554 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21557 const SelectionDAG &DAG,
21558 unsigned Depth) const {
21559 unsigned BitWidth = KnownZero.getBitWidth();
21560 unsigned Opc = Op.getOpcode();
21561 assert((Opc >= ISD::BUILTIN_OP_END ||
21562 Opc == ISD::INTRINSIC_WO_CHAIN ||
21563 Opc == ISD::INTRINSIC_W_CHAIN ||
21564 Opc == ISD::INTRINSIC_VOID) &&
21565 "Should use MaskedValueIsZero if you don't know whether Op"
21566 " is a target node!");
21568 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21582 // These nodes' second result is a boolean.
21583 if (Op.getResNo() == 0)
21586 case X86ISD::SETCC:
21587 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21589 case ISD::INTRINSIC_WO_CHAIN: {
21590 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21591 unsigned NumLoBits = 0;
21594 case Intrinsic::x86_sse_movmsk_ps:
21595 case Intrinsic::x86_avx_movmsk_ps_256:
21596 case Intrinsic::x86_sse2_movmsk_pd:
21597 case Intrinsic::x86_avx_movmsk_pd_256:
21598 case Intrinsic::x86_mmx_pmovmskb:
21599 case Intrinsic::x86_sse2_pmovmskb_128:
21600 case Intrinsic::x86_avx2_pmovmskb: {
21601 // High bits of movmskp{s|d}, pmovmskb are known zero.
21603 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21604 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21605 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21606 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21607 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21608 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21609 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21610 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21612 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21621 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21623 const SelectionDAG &,
21624 unsigned Depth) const {
21625 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21626 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21627 return Op.getValueType().getScalarType().getSizeInBits();
21633 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21634 /// node is a GlobalAddress + offset.
21635 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21636 const GlobalValue* &GA,
21637 int64_t &Offset) const {
21638 if (N->getOpcode() == X86ISD::Wrapper) {
21639 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21640 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21641 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21645 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21648 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21649 /// same as extracting the high 128-bit part of 256-bit vector and then
21650 /// inserting the result into the low part of a new 256-bit vector
21651 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21652 EVT VT = SVOp->getValueType(0);
21653 unsigned NumElems = VT.getVectorNumElements();
21655 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21656 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21657 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21658 SVOp->getMaskElt(j) >= 0)
21664 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21665 /// same as extracting the low 128-bit part of 256-bit vector and then
21666 /// inserting the result into the high part of a new 256-bit vector
21667 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21668 EVT VT = SVOp->getValueType(0);
21669 unsigned NumElems = VT.getVectorNumElements();
21671 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21672 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21673 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21674 SVOp->getMaskElt(j) >= 0)
21680 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21681 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21682 TargetLowering::DAGCombinerInfo &DCI,
21683 const X86Subtarget* Subtarget) {
21685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21686 SDValue V1 = SVOp->getOperand(0);
21687 SDValue V2 = SVOp->getOperand(1);
21688 EVT VT = SVOp->getValueType(0);
21689 unsigned NumElems = VT.getVectorNumElements();
21691 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21692 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21696 // V UNDEF BUILD_VECTOR UNDEF
21698 // CONCAT_VECTOR CONCAT_VECTOR
21701 // RESULT: V + zero extended
21703 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21704 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21705 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21708 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21711 // To match the shuffle mask, the first half of the mask should
21712 // be exactly the first vector, and all the rest a splat with the
21713 // first element of the second one.
21714 for (unsigned i = 0; i != NumElems/2; ++i)
21715 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21716 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21719 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21720 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21721 if (Ld->hasNUsesOfValue(1, 0)) {
21722 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21723 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21725 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21727 Ld->getPointerInfo(),
21728 Ld->getAlignment(),
21729 false/*isVolatile*/, true/*ReadMem*/,
21730 false/*WriteMem*/);
21732 // Make sure the newly-created LOAD is in the same position as Ld in
21733 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21734 // and update uses of Ld's output chain to use the TokenFactor.
21735 if (Ld->hasAnyUseOfValue(1)) {
21736 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21737 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21738 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21739 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21740 SDValue(ResNode.getNode(), 1));
21743 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21747 // Emit a zeroed vector and insert the desired subvector on its
21749 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21750 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21751 return DCI.CombineTo(N, InsV);
21754 //===--------------------------------------------------------------------===//
21755 // Combine some shuffles into subvector extracts and inserts:
21758 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21759 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21760 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21761 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21762 return DCI.CombineTo(N, InsV);
21765 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21766 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21767 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21768 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21769 return DCI.CombineTo(N, InsV);
21775 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21778 /// This is the leaf of the recursive combinine below. When we have found some
21779 /// chain of single-use x86 shuffle instructions and accumulated the combined
21780 /// shuffle mask represented by them, this will try to pattern match that mask
21781 /// into either a single instruction if there is a special purpose instruction
21782 /// for this operation, or into a PSHUFB instruction which is a fully general
21783 /// instruction but should only be used to replace chains over a certain depth.
21784 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21785 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21786 TargetLowering::DAGCombinerInfo &DCI,
21787 const X86Subtarget *Subtarget) {
21788 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21790 // Find the operand that enters the chain. Note that multiple uses are OK
21791 // here, we're not going to remove the operand we find.
21792 SDValue Input = Op.getOperand(0);
21793 while (Input.getOpcode() == ISD::BITCAST)
21794 Input = Input.getOperand(0);
21796 MVT VT = Input.getSimpleValueType();
21797 MVT RootVT = Root.getSimpleValueType();
21800 // Just remove no-op shuffle masks.
21801 if (Mask.size() == 1) {
21802 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21807 // Use the float domain if the operand type is a floating point type.
21808 bool FloatDomain = VT.isFloatingPoint();
21810 // For floating point shuffles, we don't have free copies in the shuffle
21811 // instructions or the ability to load as part of the instruction, so
21812 // canonicalize their shuffles to UNPCK or MOV variants.
21814 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21815 // vectors because it can have a load folded into it that UNPCK cannot. This
21816 // doesn't preclude something switching to the shorter encoding post-RA.
21818 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21819 bool Lo = Mask.equals(0, 0);
21822 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21823 // is no slower than UNPCKLPD but has the option to fold the input operand
21824 // into even an unaligned memory load.
21825 if (Lo && Subtarget->hasSSE3()) {
21826 Shuffle = X86ISD::MOVDDUP;
21827 ShuffleVT = MVT::v2f64;
21829 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21830 // than the UNPCK variants.
21831 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21832 ShuffleVT = MVT::v4f32;
21834 if (Depth == 1 && Root->getOpcode() == Shuffle)
21835 return false; // Nothing to do!
21836 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21837 DCI.AddToWorklist(Op.getNode());
21838 if (Shuffle == X86ISD::MOVDDUP)
21839 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21841 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21842 DCI.AddToWorklist(Op.getNode());
21843 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21847 if (Subtarget->hasSSE3() &&
21848 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21849 bool Lo = Mask.equals(0, 0, 2, 2);
21850 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21851 MVT ShuffleVT = MVT::v4f32;
21852 if (Depth == 1 && Root->getOpcode() == Shuffle)
21853 return false; // Nothing to do!
21854 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21855 DCI.AddToWorklist(Op.getNode());
21856 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21857 DCI.AddToWorklist(Op.getNode());
21858 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21862 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21863 bool Lo = Mask.equals(0, 0, 1, 1);
21864 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21865 MVT ShuffleVT = MVT::v4f32;
21866 if (Depth == 1 && Root->getOpcode() == Shuffle)
21867 return false; // Nothing to do!
21868 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21869 DCI.AddToWorklist(Op.getNode());
21870 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21871 DCI.AddToWorklist(Op.getNode());
21872 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21878 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21879 // variants as none of these have single-instruction variants that are
21880 // superior to the UNPCK formulation.
21881 if (!FloatDomain &&
21882 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21883 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21884 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21885 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21887 bool Lo = Mask[0] == 0;
21888 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21889 if (Depth == 1 && Root->getOpcode() == Shuffle)
21890 return false; // Nothing to do!
21892 switch (Mask.size()) {
21894 ShuffleVT = MVT::v8i16;
21897 ShuffleVT = MVT::v16i8;
21900 llvm_unreachable("Impossible mask size!");
21902 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21903 DCI.AddToWorklist(Op.getNode());
21904 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21905 DCI.AddToWorklist(Op.getNode());
21906 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21911 // Don't try to re-form single instruction chains under any circumstances now
21912 // that we've done encoding canonicalization for them.
21916 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21917 // can replace them with a single PSHUFB instruction profitably. Intel's
21918 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21919 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21920 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21921 SmallVector<SDValue, 16> PSHUFBMask;
21922 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21923 int Ratio = 16 / Mask.size();
21924 for (unsigned i = 0; i < 16; ++i) {
21925 if (Mask[i / Ratio] == SM_SentinelUndef) {
21926 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21929 int M = Mask[i / Ratio] != SM_SentinelZero
21930 ? Ratio * Mask[i / Ratio] + i % Ratio
21932 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21934 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21935 DCI.AddToWorklist(Op.getNode());
21936 SDValue PSHUFBMaskOp =
21937 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21938 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21939 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21940 DCI.AddToWorklist(Op.getNode());
21941 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21946 // Failed to find any combines.
21950 /// \brief Fully generic combining of x86 shuffle instructions.
21952 /// This should be the last combine run over the x86 shuffle instructions. Once
21953 /// they have been fully optimized, this will recursively consider all chains
21954 /// of single-use shuffle instructions, build a generic model of the cumulative
21955 /// shuffle operation, and check for simpler instructions which implement this
21956 /// operation. We use this primarily for two purposes:
21958 /// 1) Collapse generic shuffles to specialized single instructions when
21959 /// equivalent. In most cases, this is just an encoding size win, but
21960 /// sometimes we will collapse multiple generic shuffles into a single
21961 /// special-purpose shuffle.
21962 /// 2) Look for sequences of shuffle instructions with 3 or more total
21963 /// instructions, and replace them with the slightly more expensive SSSE3
21964 /// PSHUFB instruction if available. We do this as the last combining step
21965 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21966 /// a suitable short sequence of other instructions. The PHUFB will either
21967 /// use a register or have to read from memory and so is slightly (but only
21968 /// slightly) more expensive than the other shuffle instructions.
21970 /// Because this is inherently a quadratic operation (for each shuffle in
21971 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21972 /// This should never be an issue in practice as the shuffle lowering doesn't
21973 /// produce sequences of more than 8 instructions.
21975 /// FIXME: We will currently miss some cases where the redundant shuffling
21976 /// would simplify under the threshold for PSHUFB formation because of
21977 /// combine-ordering. To fix this, we should do the redundant instruction
21978 /// combining in this recursive walk.
21979 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21980 ArrayRef<int> RootMask,
21981 int Depth, bool HasPSHUFB,
21983 TargetLowering::DAGCombinerInfo &DCI,
21984 const X86Subtarget *Subtarget) {
21985 // Bound the depth of our recursive combine because this is ultimately
21986 // quadratic in nature.
21990 // Directly rip through bitcasts to find the underlying operand.
21991 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21992 Op = Op.getOperand(0);
21994 MVT VT = Op.getSimpleValueType();
21995 if (!VT.isVector())
21996 return false; // Bail if we hit a non-vector.
21997 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21998 // version should be added.
21999 if (VT.getSizeInBits() != 128)
22002 assert(Root.getSimpleValueType().isVector() &&
22003 "Shuffles operate on vector types!");
22004 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22005 "Can only combine shuffles of the same vector register size.");
22007 if (!isTargetShuffle(Op.getOpcode()))
22009 SmallVector<int, 16> OpMask;
22011 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22012 // We only can combine unary shuffles which we can decode the mask for.
22013 if (!HaveMask || !IsUnary)
22016 assert(VT.getVectorNumElements() == OpMask.size() &&
22017 "Different mask size from vector size!");
22018 assert(((RootMask.size() > OpMask.size() &&
22019 RootMask.size() % OpMask.size() == 0) ||
22020 (OpMask.size() > RootMask.size() &&
22021 OpMask.size() % RootMask.size() == 0) ||
22022 OpMask.size() == RootMask.size()) &&
22023 "The smaller number of elements must divide the larger.");
22024 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22025 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22026 assert(((RootRatio == 1 && OpRatio == 1) ||
22027 (RootRatio == 1) != (OpRatio == 1)) &&
22028 "Must not have a ratio for both incoming and op masks!");
22030 SmallVector<int, 16> Mask;
22031 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22033 // Merge this shuffle operation's mask into our accumulated mask. Note that
22034 // this shuffle's mask will be the first applied to the input, followed by the
22035 // root mask to get us all the way to the root value arrangement. The reason
22036 // for this order is that we are recursing up the operation chain.
22037 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22038 int RootIdx = i / RootRatio;
22039 if (RootMask[RootIdx] < 0) {
22040 // This is a zero or undef lane, we're done.
22041 Mask.push_back(RootMask[RootIdx]);
22045 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22046 int OpIdx = RootMaskedIdx / OpRatio;
22047 if (OpMask[OpIdx] < 0) {
22048 // The incoming lanes are zero or undef, it doesn't matter which ones we
22050 Mask.push_back(OpMask[OpIdx]);
22054 // Ok, we have non-zero lanes, map them through.
22055 Mask.push_back(OpMask[OpIdx] * OpRatio +
22056 RootMaskedIdx % OpRatio);
22059 // See if we can recurse into the operand to combine more things.
22060 switch (Op.getOpcode()) {
22061 case X86ISD::PSHUFB:
22063 case X86ISD::PSHUFD:
22064 case X86ISD::PSHUFHW:
22065 case X86ISD::PSHUFLW:
22066 if (Op.getOperand(0).hasOneUse() &&
22067 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22068 HasPSHUFB, DAG, DCI, Subtarget))
22072 case X86ISD::UNPCKL:
22073 case X86ISD::UNPCKH:
22074 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22075 // We can't check for single use, we have to check that this shuffle is the only user.
22076 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22077 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22078 HasPSHUFB, DAG, DCI, Subtarget))
22083 // Minor canonicalization of the accumulated shuffle mask to make it easier
22084 // to match below. All this does is detect masks with squential pairs of
22085 // elements, and shrink them to the half-width mask. It does this in a loop
22086 // so it will reduce the size of the mask to the minimal width mask which
22087 // performs an equivalent shuffle.
22088 SmallVector<int, 16> WidenedMask;
22089 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22090 Mask = std::move(WidenedMask);
22091 WidenedMask.clear();
22094 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22098 /// \brief Get the PSHUF-style mask from PSHUF node.
22100 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22101 /// PSHUF-style masks that can be reused with such instructions.
22102 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22103 SmallVector<int, 4> Mask;
22105 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22109 switch (N.getOpcode()) {
22110 case X86ISD::PSHUFD:
22112 case X86ISD::PSHUFLW:
22115 case X86ISD::PSHUFHW:
22116 Mask.erase(Mask.begin(), Mask.begin() + 4);
22117 for (int &M : Mask)
22121 llvm_unreachable("No valid shuffle instruction found!");
22125 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22127 /// We walk up the chain and look for a combinable shuffle, skipping over
22128 /// shuffles that we could hoist this shuffle's transformation past without
22129 /// altering anything.
22131 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22133 TargetLowering::DAGCombinerInfo &DCI) {
22134 assert(N.getOpcode() == X86ISD::PSHUFD &&
22135 "Called with something other than an x86 128-bit half shuffle!");
22138 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22139 // of the shuffles in the chain so that we can form a fresh chain to replace
22141 SmallVector<SDValue, 8> Chain;
22142 SDValue V = N.getOperand(0);
22143 for (; V.hasOneUse(); V = V.getOperand(0)) {
22144 switch (V.getOpcode()) {
22146 return SDValue(); // Nothing combined!
22149 // Skip bitcasts as we always know the type for the target specific
22153 case X86ISD::PSHUFD:
22154 // Found another dword shuffle.
22157 case X86ISD::PSHUFLW:
22158 // Check that the low words (being shuffled) are the identity in the
22159 // dword shuffle, and the high words are self-contained.
22160 if (Mask[0] != 0 || Mask[1] != 1 ||
22161 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22164 Chain.push_back(V);
22167 case X86ISD::PSHUFHW:
22168 // Check that the high words (being shuffled) are the identity in the
22169 // dword shuffle, and the low words are self-contained.
22170 if (Mask[2] != 2 || Mask[3] != 3 ||
22171 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22174 Chain.push_back(V);
22177 case X86ISD::UNPCKL:
22178 case X86ISD::UNPCKH:
22179 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22180 // shuffle into a preceding word shuffle.
22181 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22184 // Search for a half-shuffle which we can combine with.
22185 unsigned CombineOp =
22186 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22187 if (V.getOperand(0) != V.getOperand(1) ||
22188 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22190 Chain.push_back(V);
22191 V = V.getOperand(0);
22193 switch (V.getOpcode()) {
22195 return SDValue(); // Nothing to combine.
22197 case X86ISD::PSHUFLW:
22198 case X86ISD::PSHUFHW:
22199 if (V.getOpcode() == CombineOp)
22202 Chain.push_back(V);
22206 V = V.getOperand(0);
22210 } while (V.hasOneUse());
22213 // Break out of the loop if we break out of the switch.
22217 if (!V.hasOneUse())
22218 // We fell out of the loop without finding a viable combining instruction.
22221 // Merge this node's mask and our incoming mask.
22222 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22223 for (int &M : Mask)
22225 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22226 getV4X86ShuffleImm8ForMask(Mask, DAG));
22228 // Rebuild the chain around this new shuffle.
22229 while (!Chain.empty()) {
22230 SDValue W = Chain.pop_back_val();
22232 if (V.getValueType() != W.getOperand(0).getValueType())
22233 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22235 switch (W.getOpcode()) {
22237 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22239 case X86ISD::UNPCKL:
22240 case X86ISD::UNPCKH:
22241 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22244 case X86ISD::PSHUFD:
22245 case X86ISD::PSHUFLW:
22246 case X86ISD::PSHUFHW:
22247 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22251 if (V.getValueType() != N.getValueType())
22252 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22254 // Return the new chain to replace N.
22258 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22260 /// We walk up the chain, skipping shuffles of the other half and looking
22261 /// through shuffles which switch halves trying to find a shuffle of the same
22262 /// pair of dwords.
22263 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22265 TargetLowering::DAGCombinerInfo &DCI) {
22267 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22268 "Called with something other than an x86 128-bit half shuffle!");
22270 unsigned CombineOpcode = N.getOpcode();
22272 // Walk up a single-use chain looking for a combinable shuffle.
22273 SDValue V = N.getOperand(0);
22274 for (; V.hasOneUse(); V = V.getOperand(0)) {
22275 switch (V.getOpcode()) {
22277 return false; // Nothing combined!
22280 // Skip bitcasts as we always know the type for the target specific
22284 case X86ISD::PSHUFLW:
22285 case X86ISD::PSHUFHW:
22286 if (V.getOpcode() == CombineOpcode)
22289 // Other-half shuffles are no-ops.
22292 // Break out of the loop if we break out of the switch.
22296 if (!V.hasOneUse())
22297 // We fell out of the loop without finding a viable combining instruction.
22300 // Combine away the bottom node as its shuffle will be accumulated into
22301 // a preceding shuffle.
22302 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22304 // Record the old value.
22307 // Merge this node's mask and our incoming mask (adjusted to account for all
22308 // the pshufd instructions encountered).
22309 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22310 for (int &M : Mask)
22312 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22313 getV4X86ShuffleImm8ForMask(Mask, DAG));
22315 // Check that the shuffles didn't cancel each other out. If not, we need to
22316 // combine to the new one.
22318 // Replace the combinable shuffle with the combined one, updating all users
22319 // so that we re-evaluate the chain here.
22320 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22325 /// \brief Try to combine x86 target specific shuffles.
22326 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22327 TargetLowering::DAGCombinerInfo &DCI,
22328 const X86Subtarget *Subtarget) {
22330 MVT VT = N.getSimpleValueType();
22331 SmallVector<int, 4> Mask;
22333 switch (N.getOpcode()) {
22334 case X86ISD::PSHUFD:
22335 case X86ISD::PSHUFLW:
22336 case X86ISD::PSHUFHW:
22337 Mask = getPSHUFShuffleMask(N);
22338 assert(Mask.size() == 4);
22344 // Nuke no-op shuffles that show up after combining.
22345 if (isNoopShuffleMask(Mask))
22346 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22348 // Look for simplifications involving one or two shuffle instructions.
22349 SDValue V = N.getOperand(0);
22350 switch (N.getOpcode()) {
22353 case X86ISD::PSHUFLW:
22354 case X86ISD::PSHUFHW:
22355 assert(VT == MVT::v8i16);
22358 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22359 return SDValue(); // We combined away this shuffle, so we're done.
22361 // See if this reduces to a PSHUFD which is no more expensive and can
22362 // combine with more operations. Note that it has to at least flip the
22363 // dwords as otherwise it would have been removed as a no-op.
22364 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22365 int DMask[] = {0, 1, 2, 3};
22366 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22367 DMask[DOffset + 0] = DOffset + 1;
22368 DMask[DOffset + 1] = DOffset + 0;
22369 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22370 DCI.AddToWorklist(V.getNode());
22371 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22372 getV4X86ShuffleImm8ForMask(DMask, DAG));
22373 DCI.AddToWorklist(V.getNode());
22374 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22377 // Look for shuffle patterns which can be implemented as a single unpack.
22378 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22379 // only works when we have a PSHUFD followed by two half-shuffles.
22380 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22381 (V.getOpcode() == X86ISD::PSHUFLW ||
22382 V.getOpcode() == X86ISD::PSHUFHW) &&
22383 V.getOpcode() != N.getOpcode() &&
22385 SDValue D = V.getOperand(0);
22386 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22387 D = D.getOperand(0);
22388 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22389 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22390 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22391 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22392 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22394 for (int i = 0; i < 4; ++i) {
22395 WordMask[i + NOffset] = Mask[i] + NOffset;
22396 WordMask[i + VOffset] = VMask[i] + VOffset;
22398 // Map the word mask through the DWord mask.
22400 for (int i = 0; i < 8; ++i)
22401 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22402 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22403 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22404 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22405 std::begin(UnpackLoMask)) ||
22406 std::equal(std::begin(MappedMask), std::end(MappedMask),
22407 std::begin(UnpackHiMask))) {
22408 // We can replace all three shuffles with an unpack.
22409 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22410 DCI.AddToWorklist(V.getNode());
22411 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22413 DL, MVT::v8i16, V, V);
22420 case X86ISD::PSHUFD:
22421 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22430 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22432 /// We combine this directly on the abstract vector shuffle nodes so it is
22433 /// easier to generically match. We also insert dummy vector shuffle nodes for
22434 /// the operands which explicitly discard the lanes which are unused by this
22435 /// operation to try to flow through the rest of the combiner the fact that
22436 /// they're unused.
22437 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22439 EVT VT = N->getValueType(0);
22441 // We only handle target-independent shuffles.
22442 // FIXME: It would be easy and harmless to use the target shuffle mask
22443 // extraction tool to support more.
22444 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22447 auto *SVN = cast<ShuffleVectorSDNode>(N);
22448 ArrayRef<int> Mask = SVN->getMask();
22449 SDValue V1 = N->getOperand(0);
22450 SDValue V2 = N->getOperand(1);
22452 // We require the first shuffle operand to be the SUB node, and the second to
22453 // be the ADD node.
22454 // FIXME: We should support the commuted patterns.
22455 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22458 // If there are other uses of these operations we can't fold them.
22459 if (!V1->hasOneUse() || !V2->hasOneUse())
22462 // Ensure that both operations have the same operands. Note that we can
22463 // commute the FADD operands.
22464 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22465 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22466 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22469 // We're looking for blends between FADD and FSUB nodes. We insist on these
22470 // nodes being lined up in a specific expected pattern.
22471 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22472 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22473 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22476 // Only specific types are legal at this point, assert so we notice if and
22477 // when these change.
22478 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22479 VT == MVT::v4f64) &&
22480 "Unknown vector type encountered!");
22482 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22485 /// PerformShuffleCombine - Performs several different shuffle combines.
22486 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22487 TargetLowering::DAGCombinerInfo &DCI,
22488 const X86Subtarget *Subtarget) {
22490 SDValue N0 = N->getOperand(0);
22491 SDValue N1 = N->getOperand(1);
22492 EVT VT = N->getValueType(0);
22494 // Don't create instructions with illegal types after legalize types has run.
22495 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22496 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22499 // If we have legalized the vector types, look for blends of FADD and FSUB
22500 // nodes that we can fuse into an ADDSUB node.
22501 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22502 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22505 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22506 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22507 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22508 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22510 // During Type Legalization, when promoting illegal vector types,
22511 // the backend might introduce new shuffle dag nodes and bitcasts.
22513 // This code performs the following transformation:
22514 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22515 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22517 // We do this only if both the bitcast and the BINOP dag nodes have
22518 // one use. Also, perform this transformation only if the new binary
22519 // operation is legal. This is to avoid introducing dag nodes that
22520 // potentially need to be further expanded (or custom lowered) into a
22521 // less optimal sequence of dag nodes.
22522 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22523 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22524 N0.getOpcode() == ISD::BITCAST) {
22525 SDValue BC0 = N0.getOperand(0);
22526 EVT SVT = BC0.getValueType();
22527 unsigned Opcode = BC0.getOpcode();
22528 unsigned NumElts = VT.getVectorNumElements();
22530 if (BC0.hasOneUse() && SVT.isVector() &&
22531 SVT.getVectorNumElements() * 2 == NumElts &&
22532 TLI.isOperationLegal(Opcode, VT)) {
22533 bool CanFold = false;
22545 unsigned SVTNumElts = SVT.getVectorNumElements();
22546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22547 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22548 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22549 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22550 CanFold = SVOp->getMaskElt(i) < 0;
22553 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22554 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22555 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22556 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22561 // Only handle 128 wide vector from here on.
22562 if (!VT.is128BitVector())
22565 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22566 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22567 // consecutive, non-overlapping, and in the right order.
22568 SmallVector<SDValue, 16> Elts;
22569 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22570 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22572 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22576 if (isTargetShuffle(N->getOpcode())) {
22578 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22579 if (Shuffle.getNode())
22582 // Try recursively combining arbitrary sequences of x86 shuffle
22583 // instructions into higher-order shuffles. We do this after combining
22584 // specific PSHUF instruction sequences into their minimal form so that we
22585 // can evaluate how many specialized shuffle instructions are involved in
22586 // a particular chain.
22587 SmallVector<int, 1> NonceMask; // Just a placeholder.
22588 NonceMask.push_back(0);
22589 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22590 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22592 return SDValue(); // This routine will use CombineTo to replace N.
22598 /// PerformTruncateCombine - Converts truncate operation to
22599 /// a sequence of vector shuffle operations.
22600 /// It is possible when we truncate 256-bit vector to 128-bit vector
22601 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22602 TargetLowering::DAGCombinerInfo &DCI,
22603 const X86Subtarget *Subtarget) {
22607 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22608 /// specific shuffle of a load can be folded into a single element load.
22609 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22610 /// shuffles have been custom lowered so we need to handle those here.
22611 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22612 TargetLowering::DAGCombinerInfo &DCI) {
22613 if (DCI.isBeforeLegalizeOps())
22616 SDValue InVec = N->getOperand(0);
22617 SDValue EltNo = N->getOperand(1);
22619 if (!isa<ConstantSDNode>(EltNo))
22622 EVT OriginalVT = InVec.getValueType();
22624 if (InVec.getOpcode() == ISD::BITCAST) {
22625 // Don't duplicate a load with other uses.
22626 if (!InVec.hasOneUse())
22628 EVT BCVT = InVec.getOperand(0).getValueType();
22629 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22631 InVec = InVec.getOperand(0);
22634 EVT CurrentVT = InVec.getValueType();
22636 if (!isTargetShuffle(InVec.getOpcode()))
22639 // Don't duplicate a load with other uses.
22640 if (!InVec.hasOneUse())
22643 SmallVector<int, 16> ShuffleMask;
22645 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22646 ShuffleMask, UnaryShuffle))
22649 // Select the input vector, guarding against out of range extract vector.
22650 unsigned NumElems = CurrentVT.getVectorNumElements();
22651 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22652 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22653 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22654 : InVec.getOperand(1);
22656 // If inputs to shuffle are the same for both ops, then allow 2 uses
22657 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22659 if (LdNode.getOpcode() == ISD::BITCAST) {
22660 // Don't duplicate a load with other uses.
22661 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22664 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22665 LdNode = LdNode.getOperand(0);
22668 if (!ISD::isNormalLoad(LdNode.getNode()))
22671 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22673 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22676 EVT EltVT = N->getValueType(0);
22677 // If there's a bitcast before the shuffle, check if the load type and
22678 // alignment is valid.
22679 unsigned Align = LN0->getAlignment();
22680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22681 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22682 EltVT.getTypeForEVT(*DAG.getContext()));
22684 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22687 // All checks match so transform back to vector_shuffle so that DAG combiner
22688 // can finish the job
22691 // Create shuffle node taking into account the case that its a unary shuffle
22692 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22693 : InVec.getOperand(1);
22694 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22695 InVec.getOperand(0), Shuffle,
22697 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22702 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22703 /// generation and convert it from being a bunch of shuffles and extracts
22704 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22705 /// storing the value and loading scalars back, while for x64 we should
22706 /// use 64-bit extracts and shifts.
22707 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22708 TargetLowering::DAGCombinerInfo &DCI) {
22709 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22710 if (NewOp.getNode())
22713 SDValue InputVector = N->getOperand(0);
22715 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22716 // from mmx to v2i32 has a single usage.
22717 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22718 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22719 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22720 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22721 N->getValueType(0),
22722 InputVector.getNode()->getOperand(0));
22724 // Only operate on vectors of 4 elements, where the alternative shuffling
22725 // gets to be more expensive.
22726 if (InputVector.getValueType() != MVT::v4i32)
22729 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22730 // single use which is a sign-extend or zero-extend, and all elements are
22732 SmallVector<SDNode *, 4> Uses;
22733 unsigned ExtractedElements = 0;
22734 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22735 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22736 if (UI.getUse().getResNo() != InputVector.getResNo())
22739 SDNode *Extract = *UI;
22740 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22743 if (Extract->getValueType(0) != MVT::i32)
22745 if (!Extract->hasOneUse())
22747 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22748 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22750 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22753 // Record which element was extracted.
22754 ExtractedElements |=
22755 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22757 Uses.push_back(Extract);
22760 // If not all the elements were used, this may not be worthwhile.
22761 if (ExtractedElements != 15)
22764 // Ok, we've now decided to do the transformation.
22765 // If 64-bit shifts are legal, use the extract-shift sequence,
22766 // otherwise bounce the vector off the cache.
22767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22769 SDLoc dl(InputVector);
22771 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22772 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22773 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22774 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22775 DAG.getConstant(0, VecIdxTy));
22776 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22777 DAG.getConstant(1, VecIdxTy));
22779 SDValue ShAmt = DAG.getConstant(32,
22780 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22781 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22782 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22783 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22784 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22785 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22786 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22788 // Store the value to a temporary stack slot.
22789 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22790 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22791 MachinePointerInfo(), false, false, 0);
22793 EVT ElementType = InputVector.getValueType().getVectorElementType();
22794 unsigned EltSize = ElementType.getSizeInBits() / 8;
22796 // Replace each use (extract) with a load of the appropriate element.
22797 for (unsigned i = 0; i < 4; ++i) {
22798 uint64_t Offset = EltSize * i;
22799 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22801 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22802 StackPtr, OffsetVal);
22804 // Load the scalar.
22805 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22806 ScalarAddr, MachinePointerInfo(),
22807 false, false, false, 0);
22812 // Replace the extracts
22813 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22814 UE = Uses.end(); UI != UE; ++UI) {
22815 SDNode *Extract = *UI;
22817 SDValue Idx = Extract->getOperand(1);
22818 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22819 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22822 // The replacement was made in place; don't return anything.
22826 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22827 static std::pair<unsigned, bool>
22828 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22829 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22830 if (!VT.isVector())
22831 return std::make_pair(0, false);
22833 bool NeedSplit = false;
22834 switch (VT.getSimpleVT().SimpleTy) {
22835 default: return std::make_pair(0, false);
22838 if (!Subtarget->hasVLX())
22839 return std::make_pair(0, false);
22843 if (!Subtarget->hasBWI())
22844 return std::make_pair(0, false);
22848 if (!Subtarget->hasAVX512())
22849 return std::make_pair(0, false);
22854 if (!Subtarget->hasAVX2())
22856 if (!Subtarget->hasAVX())
22857 return std::make_pair(0, false);
22862 if (!Subtarget->hasSSE2())
22863 return std::make_pair(0, false);
22866 // SSE2 has only a small subset of the operations.
22867 bool hasUnsigned = Subtarget->hasSSE41() ||
22868 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22869 bool hasSigned = Subtarget->hasSSE41() ||
22870 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22872 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22875 // Check for x CC y ? x : y.
22876 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22877 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22882 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22885 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22888 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22891 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22893 // Check for x CC y ? y : x -- a min/max with reversed arms.
22894 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22895 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22900 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22903 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22906 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22909 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22913 return std::make_pair(Opc, NeedSplit);
22917 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22918 const X86Subtarget *Subtarget) {
22920 SDValue Cond = N->getOperand(0);
22921 SDValue LHS = N->getOperand(1);
22922 SDValue RHS = N->getOperand(2);
22924 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22925 SDValue CondSrc = Cond->getOperand(0);
22926 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22927 Cond = CondSrc->getOperand(0);
22930 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22933 // A vselect where all conditions and data are constants can be optimized into
22934 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22935 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22936 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22939 unsigned MaskValue = 0;
22940 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22943 MVT VT = N->getSimpleValueType(0);
22944 unsigned NumElems = VT.getVectorNumElements();
22945 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22946 for (unsigned i = 0; i < NumElems; ++i) {
22947 // Be sure we emit undef where we can.
22948 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22949 ShuffleMask[i] = -1;
22951 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22955 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22957 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22960 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22962 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22963 TargetLowering::DAGCombinerInfo &DCI,
22964 const X86Subtarget *Subtarget) {
22966 SDValue Cond = N->getOperand(0);
22967 // Get the LHS/RHS of the select.
22968 SDValue LHS = N->getOperand(1);
22969 SDValue RHS = N->getOperand(2);
22970 EVT VT = LHS.getValueType();
22971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22973 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22974 // instructions match the semantics of the common C idiom x<y?x:y but not
22975 // x<=y?x:y, because of how they handle negative zero (which can be
22976 // ignored in unsafe-math mode).
22977 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22978 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22979 (Subtarget->hasSSE2() ||
22980 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22981 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22983 unsigned Opcode = 0;
22984 // Check for x CC y ? x : y.
22985 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22986 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22990 // Converting this to a min would handle NaNs incorrectly, and swapping
22991 // the operands would cause it to handle comparisons between positive
22992 // and negative zero incorrectly.
22993 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22994 if (!DAG.getTarget().Options.UnsafeFPMath &&
22995 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22997 std::swap(LHS, RHS);
22999 Opcode = X86ISD::FMIN;
23002 // Converting this to a min would handle comparisons between positive
23003 // and negative zero incorrectly.
23004 if (!DAG.getTarget().Options.UnsafeFPMath &&
23005 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23007 Opcode = X86ISD::FMIN;
23010 // Converting this to a min would handle both negative zeros and NaNs
23011 // incorrectly, but we can swap the operands to fix both.
23012 std::swap(LHS, RHS);
23016 Opcode = X86ISD::FMIN;
23020 // Converting this to a max would handle comparisons between positive
23021 // and negative zero incorrectly.
23022 if (!DAG.getTarget().Options.UnsafeFPMath &&
23023 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23025 Opcode = X86ISD::FMAX;
23028 // Converting this to a max would handle NaNs incorrectly, and swapping
23029 // the operands would cause it to handle comparisons between positive
23030 // and negative zero incorrectly.
23031 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23032 if (!DAG.getTarget().Options.UnsafeFPMath &&
23033 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23035 std::swap(LHS, RHS);
23037 Opcode = X86ISD::FMAX;
23040 // Converting this to a max would handle both negative zeros and NaNs
23041 // incorrectly, but we can swap the operands to fix both.
23042 std::swap(LHS, RHS);
23046 Opcode = X86ISD::FMAX;
23049 // Check for x CC y ? y : x -- a min/max with reversed arms.
23050 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23051 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23055 // Converting this to a min would handle comparisons between positive
23056 // and negative zero incorrectly, and swapping the operands would
23057 // cause it to handle NaNs incorrectly.
23058 if (!DAG.getTarget().Options.UnsafeFPMath &&
23059 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23060 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23062 std::swap(LHS, RHS);
23064 Opcode = X86ISD::FMIN;
23067 // Converting this to a min would handle NaNs incorrectly.
23068 if (!DAG.getTarget().Options.UnsafeFPMath &&
23069 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23071 Opcode = X86ISD::FMIN;
23074 // Converting this to a min would handle both negative zeros and NaNs
23075 // incorrectly, but we can swap the operands to fix both.
23076 std::swap(LHS, RHS);
23080 Opcode = X86ISD::FMIN;
23084 // Converting this to a max would handle NaNs incorrectly.
23085 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23087 Opcode = X86ISD::FMAX;
23090 // Converting this to a max would handle comparisons between positive
23091 // and negative zero incorrectly, and swapping the operands would
23092 // cause it to handle NaNs incorrectly.
23093 if (!DAG.getTarget().Options.UnsafeFPMath &&
23094 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23095 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23097 std::swap(LHS, RHS);
23099 Opcode = X86ISD::FMAX;
23102 // Converting this to a max would handle both negative zeros and NaNs
23103 // incorrectly, but we can swap the operands to fix both.
23104 std::swap(LHS, RHS);
23108 Opcode = X86ISD::FMAX;
23114 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23117 EVT CondVT = Cond.getValueType();
23118 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23119 CondVT.getVectorElementType() == MVT::i1) {
23120 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23121 // lowering on KNL. In this case we convert it to
23122 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23123 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23124 // Since SKX these selects have a proper lowering.
23125 EVT OpVT = LHS.getValueType();
23126 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23127 (OpVT.getVectorElementType() == MVT::i8 ||
23128 OpVT.getVectorElementType() == MVT::i16) &&
23129 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23130 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23131 DCI.AddToWorklist(Cond.getNode());
23132 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23135 // If this is a select between two integer constants, try to do some
23137 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23138 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23139 // Don't do this for crazy integer types.
23140 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23141 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23142 // so that TrueC (the true value) is larger than FalseC.
23143 bool NeedsCondInvert = false;
23145 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23146 // Efficiently invertible.
23147 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23148 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23149 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23150 NeedsCondInvert = true;
23151 std::swap(TrueC, FalseC);
23154 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23155 if (FalseC->getAPIntValue() == 0 &&
23156 TrueC->getAPIntValue().isPowerOf2()) {
23157 if (NeedsCondInvert) // Invert the condition if needed.
23158 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23159 DAG.getConstant(1, Cond.getValueType()));
23161 // Zero extend the condition if needed.
23162 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23164 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23165 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23166 DAG.getConstant(ShAmt, MVT::i8));
23169 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23170 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23171 if (NeedsCondInvert) // Invert the condition if needed.
23172 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23173 DAG.getConstant(1, Cond.getValueType()));
23175 // Zero extend the condition if needed.
23176 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23177 FalseC->getValueType(0), Cond);
23178 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23179 SDValue(FalseC, 0));
23182 // Optimize cases that will turn into an LEA instruction. This requires
23183 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23184 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23185 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23186 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23188 bool isFastMultiplier = false;
23190 switch ((unsigned char)Diff) {
23192 case 1: // result = add base, cond
23193 case 2: // result = lea base( , cond*2)
23194 case 3: // result = lea base(cond, cond*2)
23195 case 4: // result = lea base( , cond*4)
23196 case 5: // result = lea base(cond, cond*4)
23197 case 8: // result = lea base( , cond*8)
23198 case 9: // result = lea base(cond, cond*8)
23199 isFastMultiplier = true;
23204 if (isFastMultiplier) {
23205 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23206 if (NeedsCondInvert) // Invert the condition if needed.
23207 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23208 DAG.getConstant(1, Cond.getValueType()));
23210 // Zero extend the condition if needed.
23211 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23213 // Scale the condition by the difference.
23215 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23216 DAG.getConstant(Diff, Cond.getValueType()));
23218 // Add the base if non-zero.
23219 if (FalseC->getAPIntValue() != 0)
23220 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23221 SDValue(FalseC, 0));
23228 // Canonicalize max and min:
23229 // (x > y) ? x : y -> (x >= y) ? x : y
23230 // (x < y) ? x : y -> (x <= y) ? x : y
23231 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23232 // the need for an extra compare
23233 // against zero. e.g.
23234 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23236 // testl %edi, %edi
23238 // cmovgl %edi, %eax
23242 // cmovsl %eax, %edi
23243 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23244 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23245 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23246 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23251 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23252 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23253 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23254 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23259 // Early exit check
23260 if (!TLI.isTypeLegal(VT))
23263 // Match VSELECTs into subs with unsigned saturation.
23264 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23265 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23266 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23267 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23268 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23270 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23271 // left side invert the predicate to simplify logic below.
23273 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23275 CC = ISD::getSetCCInverse(CC, true);
23276 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23280 if (Other.getNode() && Other->getNumOperands() == 2 &&
23281 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23282 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23283 SDValue CondRHS = Cond->getOperand(1);
23285 // Look for a general sub with unsigned saturation first.
23286 // x >= y ? x-y : 0 --> subus x, y
23287 // x > y ? x-y : 0 --> subus x, y
23288 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23289 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23290 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23292 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23293 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23294 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23295 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23296 // If the RHS is a constant we have to reverse the const
23297 // canonicalization.
23298 // x > C-1 ? x+-C : 0 --> subus x, C
23299 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23300 CondRHSConst->getAPIntValue() ==
23301 (-OpRHSConst->getAPIntValue() - 1))
23302 return DAG.getNode(
23303 X86ISD::SUBUS, DL, VT, OpLHS,
23304 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23306 // Another special case: If C was a sign bit, the sub has been
23307 // canonicalized into a xor.
23308 // FIXME: Would it be better to use computeKnownBits to determine
23309 // whether it's safe to decanonicalize the xor?
23310 // x s< 0 ? x^C : 0 --> subus x, C
23311 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23312 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23313 OpRHSConst->getAPIntValue().isSignBit())
23314 // Note that we have to rebuild the RHS constant here to ensure we
23315 // don't rely on particular values of undef lanes.
23316 return DAG.getNode(
23317 X86ISD::SUBUS, DL, VT, OpLHS,
23318 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23323 // Try to match a min/max vector operation.
23324 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23325 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23326 unsigned Opc = ret.first;
23327 bool NeedSplit = ret.second;
23329 if (Opc && NeedSplit) {
23330 unsigned NumElems = VT.getVectorNumElements();
23331 // Extract the LHS vectors
23332 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23333 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23335 // Extract the RHS vectors
23336 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23337 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23339 // Create min/max for each subvector
23340 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23341 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23343 // Merge the result
23344 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23346 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23349 // Simplify vector selection if condition value type matches vselect
23351 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23352 assert(Cond.getValueType().isVector() &&
23353 "vector select expects a vector selector!");
23355 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23356 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23358 // Try invert the condition if true value is not all 1s and false value
23360 if (!TValIsAllOnes && !FValIsAllZeros &&
23361 // Check if the selector will be produced by CMPP*/PCMP*
23362 Cond.getOpcode() == ISD::SETCC &&
23363 // Check if SETCC has already been promoted
23364 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23365 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23366 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23368 if (TValIsAllZeros || FValIsAllOnes) {
23369 SDValue CC = Cond.getOperand(2);
23370 ISD::CondCode NewCC =
23371 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23372 Cond.getOperand(0).getValueType().isInteger());
23373 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23374 std::swap(LHS, RHS);
23375 TValIsAllOnes = FValIsAllOnes;
23376 FValIsAllZeros = TValIsAllZeros;
23380 if (TValIsAllOnes || FValIsAllZeros) {
23383 if (TValIsAllOnes && FValIsAllZeros)
23385 else if (TValIsAllOnes)
23386 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23387 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23388 else if (FValIsAllZeros)
23389 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23390 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23392 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23396 // If we know that this node is legal then we know that it is going to be
23397 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23398 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23399 // to simplify previous instructions.
23400 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23401 !DCI.isBeforeLegalize() &&
23402 // We explicitly check against v8i16 and v16i16 because, although
23403 // they're marked as Custom, they might only be legal when Cond is a
23404 // build_vector of constants. This will be taken care in a later
23406 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23407 VT != MVT::v8i16) &&
23408 // Don't optimize vector of constants. Those are handled by
23409 // the generic code and all the bits must be properly set for
23410 // the generic optimizer.
23411 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23412 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23414 // Don't optimize vector selects that map to mask-registers.
23418 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23419 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23421 APInt KnownZero, KnownOne;
23422 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23423 DCI.isBeforeLegalizeOps());
23424 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23425 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23427 // If we changed the computation somewhere in the DAG, this change
23428 // will affect all users of Cond.
23429 // Make sure it is fine and update all the nodes so that we do not
23430 // use the generic VSELECT anymore. Otherwise, we may perform
23431 // wrong optimizations as we messed up with the actual expectation
23432 // for the vector boolean values.
23433 if (Cond != TLO.Old) {
23434 // Check all uses of that condition operand to check whether it will be
23435 // consumed by non-BLEND instructions, which may depend on all bits are
23437 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23439 if (I->getOpcode() != ISD::VSELECT)
23440 // TODO: Add other opcodes eventually lowered into BLEND.
23443 // Update all the users of the condition, before committing the change,
23444 // so that the VSELECT optimizations that expect the correct vector
23445 // boolean value will not be triggered.
23446 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23448 DAG.ReplaceAllUsesOfValueWith(
23450 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23451 Cond, I->getOperand(1), I->getOperand(2)));
23452 DCI.CommitTargetLoweringOpt(TLO);
23455 // At this point, only Cond is changed. Change the condition
23456 // just for N to keep the opportunity to optimize all other
23457 // users their own way.
23458 DAG.ReplaceAllUsesOfValueWith(
23460 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23461 TLO.New, N->getOperand(1), N->getOperand(2)));
23466 // We should generate an X86ISD::BLENDI from a vselect if its argument
23467 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23468 // constants. This specific pattern gets generated when we split a
23469 // selector for a 512 bit vector in a machine without AVX512 (but with
23470 // 256-bit vectors), during legalization:
23472 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23474 // Iff we find this pattern and the build_vectors are built from
23475 // constants, we translate the vselect into a shuffle_vector that we
23476 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23477 if ((N->getOpcode() == ISD::VSELECT ||
23478 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23479 !DCI.isBeforeLegalize()) {
23480 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23481 if (Shuffle.getNode())
23488 // Check whether a boolean test is testing a boolean value generated by
23489 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23492 // Simplify the following patterns:
23493 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23494 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23495 // to (Op EFLAGS Cond)
23497 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23498 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23499 // to (Op EFLAGS !Cond)
23501 // where Op could be BRCOND or CMOV.
23503 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23504 // Quit if not CMP and SUB with its value result used.
23505 if (Cmp.getOpcode() != X86ISD::CMP &&
23506 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23509 // Quit if not used as a boolean value.
23510 if (CC != X86::COND_E && CC != X86::COND_NE)
23513 // Check CMP operands. One of them should be 0 or 1 and the other should be
23514 // an SetCC or extended from it.
23515 SDValue Op1 = Cmp.getOperand(0);
23516 SDValue Op2 = Cmp.getOperand(1);
23519 const ConstantSDNode* C = nullptr;
23520 bool needOppositeCond = (CC == X86::COND_E);
23521 bool checkAgainstTrue = false; // Is it a comparison against 1?
23523 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23525 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23527 else // Quit if all operands are not constants.
23530 if (C->getZExtValue() == 1) {
23531 needOppositeCond = !needOppositeCond;
23532 checkAgainstTrue = true;
23533 } else if (C->getZExtValue() != 0)
23534 // Quit if the constant is neither 0 or 1.
23537 bool truncatedToBoolWithAnd = false;
23538 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23539 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23540 SetCC.getOpcode() == ISD::TRUNCATE ||
23541 SetCC.getOpcode() == ISD::AND) {
23542 if (SetCC.getOpcode() == ISD::AND) {
23544 ConstantSDNode *CS;
23545 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23546 CS->getZExtValue() == 1)
23548 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23549 CS->getZExtValue() == 1)
23553 SetCC = SetCC.getOperand(OpIdx);
23554 truncatedToBoolWithAnd = true;
23556 SetCC = SetCC.getOperand(0);
23559 switch (SetCC.getOpcode()) {
23560 case X86ISD::SETCC_CARRY:
23561 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23562 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23563 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23564 // truncated to i1 using 'and'.
23565 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23567 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23568 "Invalid use of SETCC_CARRY!");
23570 case X86ISD::SETCC:
23571 // Set the condition code or opposite one if necessary.
23572 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23573 if (needOppositeCond)
23574 CC = X86::GetOppositeBranchCondition(CC);
23575 return SetCC.getOperand(1);
23576 case X86ISD::CMOV: {
23577 // Check whether false/true value has canonical one, i.e. 0 or 1.
23578 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23579 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23580 // Quit if true value is not a constant.
23583 // Quit if false value is not a constant.
23585 SDValue Op = SetCC.getOperand(0);
23586 // Skip 'zext' or 'trunc' node.
23587 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23588 Op.getOpcode() == ISD::TRUNCATE)
23589 Op = Op.getOperand(0);
23590 // A special case for rdrand/rdseed, where 0 is set if false cond is
23592 if ((Op.getOpcode() != X86ISD::RDRAND &&
23593 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23596 // Quit if false value is not the constant 0 or 1.
23597 bool FValIsFalse = true;
23598 if (FVal && FVal->getZExtValue() != 0) {
23599 if (FVal->getZExtValue() != 1)
23601 // If FVal is 1, opposite cond is needed.
23602 needOppositeCond = !needOppositeCond;
23603 FValIsFalse = false;
23605 // Quit if TVal is not the constant opposite of FVal.
23606 if (FValIsFalse && TVal->getZExtValue() != 1)
23608 if (!FValIsFalse && TVal->getZExtValue() != 0)
23610 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23611 if (needOppositeCond)
23612 CC = X86::GetOppositeBranchCondition(CC);
23613 return SetCC.getOperand(3);
23620 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23621 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23622 TargetLowering::DAGCombinerInfo &DCI,
23623 const X86Subtarget *Subtarget) {
23626 // If the flag operand isn't dead, don't touch this CMOV.
23627 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23630 SDValue FalseOp = N->getOperand(0);
23631 SDValue TrueOp = N->getOperand(1);
23632 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23633 SDValue Cond = N->getOperand(3);
23635 if (CC == X86::COND_E || CC == X86::COND_NE) {
23636 switch (Cond.getOpcode()) {
23640 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23641 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23642 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23648 Flags = checkBoolTestSetCCCombine(Cond, CC);
23649 if (Flags.getNode() &&
23650 // Extra check as FCMOV only supports a subset of X86 cond.
23651 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23652 SDValue Ops[] = { FalseOp, TrueOp,
23653 DAG.getConstant(CC, MVT::i8), Flags };
23654 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23657 // If this is a select between two integer constants, try to do some
23658 // optimizations. Note that the operands are ordered the opposite of SELECT
23660 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23661 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23662 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23663 // larger than FalseC (the false value).
23664 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23665 CC = X86::GetOppositeBranchCondition(CC);
23666 std::swap(TrueC, FalseC);
23667 std::swap(TrueOp, FalseOp);
23670 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23671 // This is efficient for any integer data type (including i8/i16) and
23673 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23674 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23675 DAG.getConstant(CC, MVT::i8), Cond);
23677 // Zero extend the condition if needed.
23678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23680 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23681 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23682 DAG.getConstant(ShAmt, MVT::i8));
23683 if (N->getNumValues() == 2) // Dead flag value?
23684 return DCI.CombineTo(N, Cond, SDValue());
23688 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23689 // for any integer data type, including i8/i16.
23690 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23691 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23692 DAG.getConstant(CC, MVT::i8), Cond);
23694 // Zero extend the condition if needed.
23695 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23696 FalseC->getValueType(0), Cond);
23697 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23698 SDValue(FalseC, 0));
23700 if (N->getNumValues() == 2) // Dead flag value?
23701 return DCI.CombineTo(N, Cond, SDValue());
23705 // Optimize cases that will turn into an LEA instruction. This requires
23706 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23707 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23708 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23709 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23711 bool isFastMultiplier = false;
23713 switch ((unsigned char)Diff) {
23715 case 1: // result = add base, cond
23716 case 2: // result = lea base( , cond*2)
23717 case 3: // result = lea base(cond, cond*2)
23718 case 4: // result = lea base( , cond*4)
23719 case 5: // result = lea base(cond, cond*4)
23720 case 8: // result = lea base( , cond*8)
23721 case 9: // result = lea base(cond, cond*8)
23722 isFastMultiplier = true;
23727 if (isFastMultiplier) {
23728 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23729 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23730 DAG.getConstant(CC, MVT::i8), Cond);
23731 // Zero extend the condition if needed.
23732 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23734 // Scale the condition by the difference.
23736 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23737 DAG.getConstant(Diff, Cond.getValueType()));
23739 // Add the base if non-zero.
23740 if (FalseC->getAPIntValue() != 0)
23741 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23742 SDValue(FalseC, 0));
23743 if (N->getNumValues() == 2) // Dead flag value?
23744 return DCI.CombineTo(N, Cond, SDValue());
23751 // Handle these cases:
23752 // (select (x != c), e, c) -> select (x != c), e, x),
23753 // (select (x == c), c, e) -> select (x == c), x, e)
23754 // where the c is an integer constant, and the "select" is the combination
23755 // of CMOV and CMP.
23757 // The rationale for this change is that the conditional-move from a constant
23758 // needs two instructions, however, conditional-move from a register needs
23759 // only one instruction.
23761 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23762 // some instruction-combining opportunities. This opt needs to be
23763 // postponed as late as possible.
23765 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23766 // the DCI.xxxx conditions are provided to postpone the optimization as
23767 // late as possible.
23769 ConstantSDNode *CmpAgainst = nullptr;
23770 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23771 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23772 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23774 if (CC == X86::COND_NE &&
23775 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23776 CC = X86::GetOppositeBranchCondition(CC);
23777 std::swap(TrueOp, FalseOp);
23780 if (CC == X86::COND_E &&
23781 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23782 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23783 DAG.getConstant(CC, MVT::i8), Cond };
23784 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23792 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23793 const X86Subtarget *Subtarget) {
23794 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23796 default: return SDValue();
23797 // SSE/AVX/AVX2 blend intrinsics.
23798 case Intrinsic::x86_avx2_pblendvb:
23799 case Intrinsic::x86_avx2_pblendw:
23800 case Intrinsic::x86_avx2_pblendd_128:
23801 case Intrinsic::x86_avx2_pblendd_256:
23802 // Don't try to simplify this intrinsic if we don't have AVX2.
23803 if (!Subtarget->hasAVX2())
23806 case Intrinsic::x86_avx_blend_pd_256:
23807 case Intrinsic::x86_avx_blend_ps_256:
23808 case Intrinsic::x86_avx_blendv_pd_256:
23809 case Intrinsic::x86_avx_blendv_ps_256:
23810 // Don't try to simplify this intrinsic if we don't have AVX.
23811 if (!Subtarget->hasAVX())
23814 case Intrinsic::x86_sse41_pblendw:
23815 case Intrinsic::x86_sse41_blendpd:
23816 case Intrinsic::x86_sse41_blendps:
23817 case Intrinsic::x86_sse41_blendvps:
23818 case Intrinsic::x86_sse41_blendvpd:
23819 case Intrinsic::x86_sse41_pblendvb: {
23820 SDValue Op0 = N->getOperand(1);
23821 SDValue Op1 = N->getOperand(2);
23822 SDValue Mask = N->getOperand(3);
23824 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23825 if (!Subtarget->hasSSE41())
23828 // fold (blend A, A, Mask) -> A
23831 // fold (blend A, B, allZeros) -> A
23832 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23834 // fold (blend A, B, allOnes) -> B
23835 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23838 // Simplify the case where the mask is a constant i32 value.
23839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23840 if (C->isNullValue())
23842 if (C->isAllOnesValue())
23849 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23850 case Intrinsic::x86_sse2_psrai_w:
23851 case Intrinsic::x86_sse2_psrai_d:
23852 case Intrinsic::x86_avx2_psrai_w:
23853 case Intrinsic::x86_avx2_psrai_d:
23854 case Intrinsic::x86_sse2_psra_w:
23855 case Intrinsic::x86_sse2_psra_d:
23856 case Intrinsic::x86_avx2_psra_w:
23857 case Intrinsic::x86_avx2_psra_d: {
23858 SDValue Op0 = N->getOperand(1);
23859 SDValue Op1 = N->getOperand(2);
23860 EVT VT = Op0.getValueType();
23861 assert(VT.isVector() && "Expected a vector type!");
23863 if (isa<BuildVectorSDNode>(Op1))
23864 Op1 = Op1.getOperand(0);
23866 if (!isa<ConstantSDNode>(Op1))
23869 EVT SVT = VT.getVectorElementType();
23870 unsigned SVTBits = SVT.getSizeInBits();
23872 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23873 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23874 uint64_t ShAmt = C.getZExtValue();
23876 // Don't try to convert this shift into a ISD::SRA if the shift
23877 // count is bigger than or equal to the element size.
23878 if (ShAmt >= SVTBits)
23881 // Trivial case: if the shift count is zero, then fold this
23882 // into the first operand.
23886 // Replace this packed shift intrinsic with a target independent
23888 SDValue Splat = DAG.getConstant(C, VT);
23889 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23894 /// PerformMulCombine - Optimize a single multiply with constant into two
23895 /// in order to implement it with two cheaper instructions, e.g.
23896 /// LEA + SHL, LEA + LEA.
23897 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23898 TargetLowering::DAGCombinerInfo &DCI) {
23899 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23902 EVT VT = N->getValueType(0);
23903 if (VT != MVT::i64)
23906 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23909 uint64_t MulAmt = C->getZExtValue();
23910 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23913 uint64_t MulAmt1 = 0;
23914 uint64_t MulAmt2 = 0;
23915 if ((MulAmt % 9) == 0) {
23917 MulAmt2 = MulAmt / 9;
23918 } else if ((MulAmt % 5) == 0) {
23920 MulAmt2 = MulAmt / 5;
23921 } else if ((MulAmt % 3) == 0) {
23923 MulAmt2 = MulAmt / 3;
23926 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23929 if (isPowerOf2_64(MulAmt2) &&
23930 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23931 // If second multiplifer is pow2, issue it first. We want the multiply by
23932 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23934 std::swap(MulAmt1, MulAmt2);
23937 if (isPowerOf2_64(MulAmt1))
23938 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23939 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23941 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23942 DAG.getConstant(MulAmt1, VT));
23944 if (isPowerOf2_64(MulAmt2))
23945 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23946 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23948 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23949 DAG.getConstant(MulAmt2, VT));
23951 // Do not add new nodes to DAG combiner worklist.
23952 DCI.CombineTo(N, NewMul, false);
23957 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23958 SDValue N0 = N->getOperand(0);
23959 SDValue N1 = N->getOperand(1);
23960 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23961 EVT VT = N0.getValueType();
23963 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23964 // since the result of setcc_c is all zero's or all ones.
23965 if (VT.isInteger() && !VT.isVector() &&
23966 N1C && N0.getOpcode() == ISD::AND &&
23967 N0.getOperand(1).getOpcode() == ISD::Constant) {
23968 SDValue N00 = N0.getOperand(0);
23969 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23970 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23971 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23972 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23973 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23974 APInt ShAmt = N1C->getAPIntValue();
23975 Mask = Mask.shl(ShAmt);
23977 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23978 N00, DAG.getConstant(Mask, VT));
23982 // Hardware support for vector shifts is sparse which makes us scalarize the
23983 // vector operations in many cases. Also, on sandybridge ADD is faster than
23985 // (shl V, 1) -> add V,V
23986 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23987 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23988 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23989 // We shift all of the values by one. In many cases we do not have
23990 // hardware support for this operation. This is better expressed as an ADD
23992 if (N1SplatC->getZExtValue() == 1)
23993 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23999 /// \brief Returns a vector of 0s if the node in input is a vector logical
24000 /// shift by a constant amount which is known to be bigger than or equal
24001 /// to the vector element size in bits.
24002 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24003 const X86Subtarget *Subtarget) {
24004 EVT VT = N->getValueType(0);
24006 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24007 (!Subtarget->hasInt256() ||
24008 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24011 SDValue Amt = N->getOperand(1);
24013 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24014 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24015 APInt ShiftAmt = AmtSplat->getAPIntValue();
24016 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24018 // SSE2/AVX2 logical shifts always return a vector of 0s
24019 // if the shift amount is bigger than or equal to
24020 // the element size. The constant shift amount will be
24021 // encoded as a 8-bit immediate.
24022 if (ShiftAmt.trunc(8).uge(MaxAmount))
24023 return getZeroVector(VT, Subtarget, DAG, DL);
24029 /// PerformShiftCombine - Combine shifts.
24030 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24031 TargetLowering::DAGCombinerInfo &DCI,
24032 const X86Subtarget *Subtarget) {
24033 if (N->getOpcode() == ISD::SHL) {
24034 SDValue V = PerformSHLCombine(N, DAG);
24035 if (V.getNode()) return V;
24038 if (N->getOpcode() != ISD::SRA) {
24039 // Try to fold this logical shift into a zero vector.
24040 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24041 if (V.getNode()) return V;
24047 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24048 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24049 // and friends. Likewise for OR -> CMPNEQSS.
24050 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24051 TargetLowering::DAGCombinerInfo &DCI,
24052 const X86Subtarget *Subtarget) {
24055 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24056 // we're requiring SSE2 for both.
24057 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24058 SDValue N0 = N->getOperand(0);
24059 SDValue N1 = N->getOperand(1);
24060 SDValue CMP0 = N0->getOperand(1);
24061 SDValue CMP1 = N1->getOperand(1);
24064 // The SETCCs should both refer to the same CMP.
24065 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24068 SDValue CMP00 = CMP0->getOperand(0);
24069 SDValue CMP01 = CMP0->getOperand(1);
24070 EVT VT = CMP00.getValueType();
24072 if (VT == MVT::f32 || VT == MVT::f64) {
24073 bool ExpectingFlags = false;
24074 // Check for any users that want flags:
24075 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24076 !ExpectingFlags && UI != UE; ++UI)
24077 switch (UI->getOpcode()) {
24082 ExpectingFlags = true;
24084 case ISD::CopyToReg:
24085 case ISD::SIGN_EXTEND:
24086 case ISD::ZERO_EXTEND:
24087 case ISD::ANY_EXTEND:
24091 if (!ExpectingFlags) {
24092 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24093 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24095 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24096 X86::CondCode tmp = cc0;
24101 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24102 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24103 // FIXME: need symbolic constants for these magic numbers.
24104 // See X86ATTInstPrinter.cpp:printSSECC().
24105 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24106 if (Subtarget->hasAVX512()) {
24107 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24108 CMP01, DAG.getConstant(x86cc, MVT::i8));
24109 if (N->getValueType(0) != MVT::i1)
24110 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24114 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24115 CMP00.getValueType(), CMP00, CMP01,
24116 DAG.getConstant(x86cc, MVT::i8));
24118 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24119 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24121 if (is64BitFP && !Subtarget->is64Bit()) {
24122 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24123 // 64-bit integer, since that's not a legal type. Since
24124 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24125 // bits, but can do this little dance to extract the lowest 32 bits
24126 // and work with those going forward.
24127 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24129 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24131 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24132 Vector32, DAG.getIntPtrConstant(0));
24136 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24137 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24138 DAG.getConstant(1, IntVT));
24139 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24140 return OneBitOfTruth;
24148 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24149 /// so it can be folded inside ANDNP.
24150 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24151 EVT VT = N->getValueType(0);
24153 // Match direct AllOnes for 128 and 256-bit vectors
24154 if (ISD::isBuildVectorAllOnes(N))
24157 // Look through a bit convert.
24158 if (N->getOpcode() == ISD::BITCAST)
24159 N = N->getOperand(0).getNode();
24161 // Sometimes the operand may come from a insert_subvector building a 256-bit
24163 if (VT.is256BitVector() &&
24164 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24165 SDValue V1 = N->getOperand(0);
24166 SDValue V2 = N->getOperand(1);
24168 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24169 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24170 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24171 ISD::isBuildVectorAllOnes(V2.getNode()))
24178 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24179 // register. In most cases we actually compare or select YMM-sized registers
24180 // and mixing the two types creates horrible code. This method optimizes
24181 // some of the transition sequences.
24182 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24183 TargetLowering::DAGCombinerInfo &DCI,
24184 const X86Subtarget *Subtarget) {
24185 EVT VT = N->getValueType(0);
24186 if (!VT.is256BitVector())
24189 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24190 N->getOpcode() == ISD::ZERO_EXTEND ||
24191 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24193 SDValue Narrow = N->getOperand(0);
24194 EVT NarrowVT = Narrow->getValueType(0);
24195 if (!NarrowVT.is128BitVector())
24198 if (Narrow->getOpcode() != ISD::XOR &&
24199 Narrow->getOpcode() != ISD::AND &&
24200 Narrow->getOpcode() != ISD::OR)
24203 SDValue N0 = Narrow->getOperand(0);
24204 SDValue N1 = Narrow->getOperand(1);
24207 // The Left side has to be a trunc.
24208 if (N0.getOpcode() != ISD::TRUNCATE)
24211 // The type of the truncated inputs.
24212 EVT WideVT = N0->getOperand(0)->getValueType(0);
24216 // The right side has to be a 'trunc' or a constant vector.
24217 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24218 ConstantSDNode *RHSConstSplat = nullptr;
24219 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24220 RHSConstSplat = RHSBV->getConstantSplatNode();
24221 if (!RHSTrunc && !RHSConstSplat)
24224 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24226 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24229 // Set N0 and N1 to hold the inputs to the new wide operation.
24230 N0 = N0->getOperand(0);
24231 if (RHSConstSplat) {
24232 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24233 SDValue(RHSConstSplat, 0));
24234 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24235 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24236 } else if (RHSTrunc) {
24237 N1 = N1->getOperand(0);
24240 // Generate the wide operation.
24241 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24242 unsigned Opcode = N->getOpcode();
24244 case ISD::ANY_EXTEND:
24246 case ISD::ZERO_EXTEND: {
24247 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24248 APInt Mask = APInt::getAllOnesValue(InBits);
24249 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24250 return DAG.getNode(ISD::AND, DL, VT,
24251 Op, DAG.getConstant(Mask, VT));
24253 case ISD::SIGN_EXTEND:
24254 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24255 Op, DAG.getValueType(NarrowVT));
24257 llvm_unreachable("Unexpected opcode");
24261 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24262 TargetLowering::DAGCombinerInfo &DCI,
24263 const X86Subtarget *Subtarget) {
24264 EVT VT = N->getValueType(0);
24265 if (DCI.isBeforeLegalizeOps())
24268 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24272 // Create BEXTR instructions
24273 // BEXTR is ((X >> imm) & (2**size-1))
24274 if (VT == MVT::i32 || VT == MVT::i64) {
24275 SDValue N0 = N->getOperand(0);
24276 SDValue N1 = N->getOperand(1);
24279 // Check for BEXTR.
24280 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24281 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24282 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24283 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24284 if (MaskNode && ShiftNode) {
24285 uint64_t Mask = MaskNode->getZExtValue();
24286 uint64_t Shift = ShiftNode->getZExtValue();
24287 if (isMask_64(Mask)) {
24288 uint64_t MaskSize = CountPopulation_64(Mask);
24289 if (Shift + MaskSize <= VT.getSizeInBits())
24290 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24291 DAG.getConstant(Shift | (MaskSize << 8), VT));
24299 // Want to form ANDNP nodes:
24300 // 1) In the hopes of then easily combining them with OR and AND nodes
24301 // to form PBLEND/PSIGN.
24302 // 2) To match ANDN packed intrinsics
24303 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24306 SDValue N0 = N->getOperand(0);
24307 SDValue N1 = N->getOperand(1);
24310 // Check LHS for vnot
24311 if (N0.getOpcode() == ISD::XOR &&
24312 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24313 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24314 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24316 // Check RHS for vnot
24317 if (N1.getOpcode() == ISD::XOR &&
24318 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24319 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24320 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24325 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24326 TargetLowering::DAGCombinerInfo &DCI,
24327 const X86Subtarget *Subtarget) {
24328 if (DCI.isBeforeLegalizeOps())
24331 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24335 SDValue N0 = N->getOperand(0);
24336 SDValue N1 = N->getOperand(1);
24337 EVT VT = N->getValueType(0);
24339 // look for psign/blend
24340 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24341 if (!Subtarget->hasSSSE3() ||
24342 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24345 // Canonicalize pandn to RHS
24346 if (N0.getOpcode() == X86ISD::ANDNP)
24348 // or (and (m, y), (pandn m, x))
24349 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24350 SDValue Mask = N1.getOperand(0);
24351 SDValue X = N1.getOperand(1);
24353 if (N0.getOperand(0) == Mask)
24354 Y = N0.getOperand(1);
24355 if (N0.getOperand(1) == Mask)
24356 Y = N0.getOperand(0);
24358 // Check to see if the mask appeared in both the AND and ANDNP and
24362 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24363 // Look through mask bitcast.
24364 if (Mask.getOpcode() == ISD::BITCAST)
24365 Mask = Mask.getOperand(0);
24366 if (X.getOpcode() == ISD::BITCAST)
24367 X = X.getOperand(0);
24368 if (Y.getOpcode() == ISD::BITCAST)
24369 Y = Y.getOperand(0);
24371 EVT MaskVT = Mask.getValueType();
24373 // Validate that the Mask operand is a vector sra node.
24374 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24375 // there is no psrai.b
24376 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24377 unsigned SraAmt = ~0;
24378 if (Mask.getOpcode() == ISD::SRA) {
24379 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24380 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24381 SraAmt = AmtConst->getZExtValue();
24382 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24383 SDValue SraC = Mask.getOperand(1);
24384 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24386 if ((SraAmt + 1) != EltBits)
24391 // Now we know we at least have a plendvb with the mask val. See if
24392 // we can form a psignb/w/d.
24393 // psign = x.type == y.type == mask.type && y = sub(0, x);
24394 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24395 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24396 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24397 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24398 "Unsupported VT for PSIGN");
24399 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24400 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24402 // PBLENDVB only available on SSE 4.1
24403 if (!Subtarget->hasSSE41())
24406 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24408 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24409 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24410 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24411 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24412 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24416 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24419 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24420 MachineFunction &MF = DAG.getMachineFunction();
24421 bool OptForSize = MF.getFunction()->getAttributes().
24422 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24424 // SHLD/SHRD instructions have lower register pressure, but on some
24425 // platforms they have higher latency than the equivalent
24426 // series of shifts/or that would otherwise be generated.
24427 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24428 // have higher latencies and we are not optimizing for size.
24429 if (!OptForSize && Subtarget->isSHLDSlow())
24432 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24434 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24436 if (!N0.hasOneUse() || !N1.hasOneUse())
24439 SDValue ShAmt0 = N0.getOperand(1);
24440 if (ShAmt0.getValueType() != MVT::i8)
24442 SDValue ShAmt1 = N1.getOperand(1);
24443 if (ShAmt1.getValueType() != MVT::i8)
24445 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24446 ShAmt0 = ShAmt0.getOperand(0);
24447 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24448 ShAmt1 = ShAmt1.getOperand(0);
24451 unsigned Opc = X86ISD::SHLD;
24452 SDValue Op0 = N0.getOperand(0);
24453 SDValue Op1 = N1.getOperand(0);
24454 if (ShAmt0.getOpcode() == ISD::SUB) {
24455 Opc = X86ISD::SHRD;
24456 std::swap(Op0, Op1);
24457 std::swap(ShAmt0, ShAmt1);
24460 unsigned Bits = VT.getSizeInBits();
24461 if (ShAmt1.getOpcode() == ISD::SUB) {
24462 SDValue Sum = ShAmt1.getOperand(0);
24463 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24464 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24465 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24466 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24467 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24468 return DAG.getNode(Opc, DL, VT,
24470 DAG.getNode(ISD::TRUNCATE, DL,
24473 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24474 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24476 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24477 return DAG.getNode(Opc, DL, VT,
24478 N0.getOperand(0), N1.getOperand(0),
24479 DAG.getNode(ISD::TRUNCATE, DL,
24486 // Generate NEG and CMOV for integer abs.
24487 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24488 EVT VT = N->getValueType(0);
24490 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24491 // 8-bit integer abs to NEG and CMOV.
24492 if (VT.isInteger() && VT.getSizeInBits() == 8)
24495 SDValue N0 = N->getOperand(0);
24496 SDValue N1 = N->getOperand(1);
24499 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24500 // and change it to SUB and CMOV.
24501 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24502 N0.getOpcode() == ISD::ADD &&
24503 N0.getOperand(1) == N1 &&
24504 N1.getOpcode() == ISD::SRA &&
24505 N1.getOperand(0) == N0.getOperand(0))
24506 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24507 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24508 // Generate SUB & CMOV.
24509 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24510 DAG.getConstant(0, VT), N0.getOperand(0));
24512 SDValue Ops[] = { N0.getOperand(0), Neg,
24513 DAG.getConstant(X86::COND_GE, MVT::i8),
24514 SDValue(Neg.getNode(), 1) };
24515 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24520 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24521 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24522 TargetLowering::DAGCombinerInfo &DCI,
24523 const X86Subtarget *Subtarget) {
24524 if (DCI.isBeforeLegalizeOps())
24527 if (Subtarget->hasCMov()) {
24528 SDValue RV = performIntegerAbsCombine(N, DAG);
24536 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24537 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24538 TargetLowering::DAGCombinerInfo &DCI,
24539 const X86Subtarget *Subtarget) {
24540 LoadSDNode *Ld = cast<LoadSDNode>(N);
24541 EVT RegVT = Ld->getValueType(0);
24542 EVT MemVT = Ld->getMemoryVT();
24544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24546 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24547 // into two 16-byte operations.
24548 ISD::LoadExtType Ext = Ld->getExtensionType();
24549 unsigned Alignment = Ld->getAlignment();
24550 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24551 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24552 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24553 unsigned NumElems = RegVT.getVectorNumElements();
24557 SDValue Ptr = Ld->getBasePtr();
24558 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24560 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24562 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24563 Ld->getPointerInfo(), Ld->isVolatile(),
24564 Ld->isNonTemporal(), Ld->isInvariant(),
24566 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24567 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24568 Ld->getPointerInfo(), Ld->isVolatile(),
24569 Ld->isNonTemporal(), Ld->isInvariant(),
24570 std::min(16U, Alignment));
24571 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24573 Load2.getValue(1));
24575 SDValue NewVec = DAG.getUNDEF(RegVT);
24576 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24577 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24578 return DCI.CombineTo(N, NewVec, TF, true);
24584 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24585 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24586 const X86Subtarget *Subtarget) {
24587 StoreSDNode *St = cast<StoreSDNode>(N);
24588 EVT VT = St->getValue().getValueType();
24589 EVT StVT = St->getMemoryVT();
24591 SDValue StoredVal = St->getOperand(1);
24592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24594 // If we are saving a concatenation of two XMM registers and 32-byte stores
24595 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24596 unsigned Alignment = St->getAlignment();
24597 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24598 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24599 StVT == VT && !IsAligned) {
24600 unsigned NumElems = VT.getVectorNumElements();
24604 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24605 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24607 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24608 SDValue Ptr0 = St->getBasePtr();
24609 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24611 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24612 St->getPointerInfo(), St->isVolatile(),
24613 St->isNonTemporal(), Alignment);
24614 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24615 St->getPointerInfo(), St->isVolatile(),
24616 St->isNonTemporal(),
24617 std::min(16U, Alignment));
24618 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24621 // Optimize trunc store (of multiple scalars) to shuffle and store.
24622 // First, pack all of the elements in one place. Next, store to memory
24623 // in fewer chunks.
24624 if (St->isTruncatingStore() && VT.isVector()) {
24625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24626 unsigned NumElems = VT.getVectorNumElements();
24627 assert(StVT != VT && "Cannot truncate to the same type");
24628 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24629 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24631 // From, To sizes and ElemCount must be pow of two
24632 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24633 // We are going to use the original vector elt for storing.
24634 // Accumulated smaller vector elements must be a multiple of the store size.
24635 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24637 unsigned SizeRatio = FromSz / ToSz;
24639 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24641 // Create a type on which we perform the shuffle
24642 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24643 StVT.getScalarType(), NumElems*SizeRatio);
24645 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24647 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24648 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24649 for (unsigned i = 0; i != NumElems; ++i)
24650 ShuffleVec[i] = i * SizeRatio;
24652 // Can't shuffle using an illegal type.
24653 if (!TLI.isTypeLegal(WideVecVT))
24656 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24657 DAG.getUNDEF(WideVecVT),
24659 // At this point all of the data is stored at the bottom of the
24660 // register. We now need to save it to mem.
24662 // Find the largest store unit
24663 MVT StoreType = MVT::i8;
24664 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24665 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24666 MVT Tp = (MVT::SimpleValueType)tp;
24667 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24671 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24672 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24673 (64 <= NumElems * ToSz))
24674 StoreType = MVT::f64;
24676 // Bitcast the original vector into a vector of store-size units
24677 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24678 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24679 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24680 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24681 SmallVector<SDValue, 8> Chains;
24682 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24683 TLI.getPointerTy());
24684 SDValue Ptr = St->getBasePtr();
24686 // Perform one or more big stores into memory.
24687 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24688 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24689 StoreType, ShuffWide,
24690 DAG.getIntPtrConstant(i));
24691 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24692 St->getPointerInfo(), St->isVolatile(),
24693 St->isNonTemporal(), St->getAlignment());
24694 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24695 Chains.push_back(Ch);
24698 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24701 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24702 // the FP state in cases where an emms may be missing.
24703 // A preferable solution to the general problem is to figure out the right
24704 // places to insert EMMS. This qualifies as a quick hack.
24706 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24707 if (VT.getSizeInBits() != 64)
24710 const Function *F = DAG.getMachineFunction().getFunction();
24711 bool NoImplicitFloatOps = F->getAttributes().
24712 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24713 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24714 && Subtarget->hasSSE2();
24715 if ((VT.isVector() ||
24716 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24717 isa<LoadSDNode>(St->getValue()) &&
24718 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24719 St->getChain().hasOneUse() && !St->isVolatile()) {
24720 SDNode* LdVal = St->getValue().getNode();
24721 LoadSDNode *Ld = nullptr;
24722 int TokenFactorIndex = -1;
24723 SmallVector<SDValue, 8> Ops;
24724 SDNode* ChainVal = St->getChain().getNode();
24725 // Must be a store of a load. We currently handle two cases: the load
24726 // is a direct child, and it's under an intervening TokenFactor. It is
24727 // possible to dig deeper under nested TokenFactors.
24728 if (ChainVal == LdVal)
24729 Ld = cast<LoadSDNode>(St->getChain());
24730 else if (St->getValue().hasOneUse() &&
24731 ChainVal->getOpcode() == ISD::TokenFactor) {
24732 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24733 if (ChainVal->getOperand(i).getNode() == LdVal) {
24734 TokenFactorIndex = i;
24735 Ld = cast<LoadSDNode>(St->getValue());
24737 Ops.push_back(ChainVal->getOperand(i));
24741 if (!Ld || !ISD::isNormalLoad(Ld))
24744 // If this is not the MMX case, i.e. we are just turning i64 load/store
24745 // into f64 load/store, avoid the transformation if there are multiple
24746 // uses of the loaded value.
24747 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24752 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24753 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24755 if (Subtarget->is64Bit() || F64IsLegal) {
24756 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24757 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24758 Ld->getPointerInfo(), Ld->isVolatile(),
24759 Ld->isNonTemporal(), Ld->isInvariant(),
24760 Ld->getAlignment());
24761 SDValue NewChain = NewLd.getValue(1);
24762 if (TokenFactorIndex != -1) {
24763 Ops.push_back(NewChain);
24764 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24766 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24767 St->getPointerInfo(),
24768 St->isVolatile(), St->isNonTemporal(),
24769 St->getAlignment());
24772 // Otherwise, lower to two pairs of 32-bit loads / stores.
24773 SDValue LoAddr = Ld->getBasePtr();
24774 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24775 DAG.getConstant(4, MVT::i32));
24777 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24778 Ld->getPointerInfo(),
24779 Ld->isVolatile(), Ld->isNonTemporal(),
24780 Ld->isInvariant(), Ld->getAlignment());
24781 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24782 Ld->getPointerInfo().getWithOffset(4),
24783 Ld->isVolatile(), Ld->isNonTemporal(),
24785 MinAlign(Ld->getAlignment(), 4));
24787 SDValue NewChain = LoLd.getValue(1);
24788 if (TokenFactorIndex != -1) {
24789 Ops.push_back(LoLd);
24790 Ops.push_back(HiLd);
24791 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24794 LoAddr = St->getBasePtr();
24795 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24796 DAG.getConstant(4, MVT::i32));
24798 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24799 St->getPointerInfo(),
24800 St->isVolatile(), St->isNonTemporal(),
24801 St->getAlignment());
24802 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24803 St->getPointerInfo().getWithOffset(4),
24805 St->isNonTemporal(),
24806 MinAlign(St->getAlignment(), 4));
24807 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24812 /// Return 'true' if this vector operation is "horizontal"
24813 /// and return the operands for the horizontal operation in LHS and RHS. A
24814 /// horizontal operation performs the binary operation on successive elements
24815 /// of its first operand, then on successive elements of its second operand,
24816 /// returning the resulting values in a vector. For example, if
24817 /// A = < float a0, float a1, float a2, float a3 >
24819 /// B = < float b0, float b1, float b2, float b3 >
24820 /// then the result of doing a horizontal operation on A and B is
24821 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24822 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24823 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24824 /// set to A, RHS to B, and the routine returns 'true'.
24825 /// Note that the binary operation should have the property that if one of the
24826 /// operands is UNDEF then the result is UNDEF.
24827 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24828 // Look for the following pattern: if
24829 // A = < float a0, float a1, float a2, float a3 >
24830 // B = < float b0, float b1, float b2, float b3 >
24832 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24833 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24834 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24835 // which is A horizontal-op B.
24837 // At least one of the operands should be a vector shuffle.
24838 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24839 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24842 MVT VT = LHS.getSimpleValueType();
24844 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24845 "Unsupported vector type for horizontal add/sub");
24847 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24848 // operate independently on 128-bit lanes.
24849 unsigned NumElts = VT.getVectorNumElements();
24850 unsigned NumLanes = VT.getSizeInBits()/128;
24851 unsigned NumLaneElts = NumElts / NumLanes;
24852 assert((NumLaneElts % 2 == 0) &&
24853 "Vector type should have an even number of elements in each lane");
24854 unsigned HalfLaneElts = NumLaneElts/2;
24856 // View LHS in the form
24857 // LHS = VECTOR_SHUFFLE A, B, LMask
24858 // If LHS is not a shuffle then pretend it is the shuffle
24859 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24860 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24863 SmallVector<int, 16> LMask(NumElts);
24864 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24865 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24866 A = LHS.getOperand(0);
24867 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24868 B = LHS.getOperand(1);
24869 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24870 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24872 if (LHS.getOpcode() != ISD::UNDEF)
24874 for (unsigned i = 0; i != NumElts; ++i)
24878 // Likewise, view RHS in the form
24879 // RHS = VECTOR_SHUFFLE C, D, RMask
24881 SmallVector<int, 16> RMask(NumElts);
24882 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24883 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24884 C = RHS.getOperand(0);
24885 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24886 D = RHS.getOperand(1);
24887 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24888 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24890 if (RHS.getOpcode() != ISD::UNDEF)
24892 for (unsigned i = 0; i != NumElts; ++i)
24896 // Check that the shuffles are both shuffling the same vectors.
24897 if (!(A == C && B == D) && !(A == D && B == C))
24900 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24901 if (!A.getNode() && !B.getNode())
24904 // If A and B occur in reverse order in RHS, then "swap" them (which means
24905 // rewriting the mask).
24907 CommuteVectorShuffleMask(RMask, NumElts);
24909 // At this point LHS and RHS are equivalent to
24910 // LHS = VECTOR_SHUFFLE A, B, LMask
24911 // RHS = VECTOR_SHUFFLE A, B, RMask
24912 // Check that the masks correspond to performing a horizontal operation.
24913 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24914 for (unsigned i = 0; i != NumLaneElts; ++i) {
24915 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24917 // Ignore any UNDEF components.
24918 if (LIdx < 0 || RIdx < 0 ||
24919 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24920 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24923 // Check that successive elements are being operated on. If not, this is
24924 // not a horizontal operation.
24925 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24926 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24927 if (!(LIdx == Index && RIdx == Index + 1) &&
24928 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24933 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24934 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24938 /// Do target-specific dag combines on floating point adds.
24939 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24940 const X86Subtarget *Subtarget) {
24941 EVT VT = N->getValueType(0);
24942 SDValue LHS = N->getOperand(0);
24943 SDValue RHS = N->getOperand(1);
24945 // Try to synthesize horizontal adds from adds of shuffles.
24946 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24947 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24948 isHorizontalBinOp(LHS, RHS, true))
24949 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24953 /// Do target-specific dag combines on floating point subs.
24954 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24955 const X86Subtarget *Subtarget) {
24956 EVT VT = N->getValueType(0);
24957 SDValue LHS = N->getOperand(0);
24958 SDValue RHS = N->getOperand(1);
24960 // Try to synthesize horizontal subs from subs of shuffles.
24961 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24962 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24963 isHorizontalBinOp(LHS, RHS, false))
24964 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24968 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24969 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24970 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24971 // F[X]OR(0.0, x) -> x
24972 // F[X]OR(x, 0.0) -> x
24973 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24974 if (C->getValueAPF().isPosZero())
24975 return N->getOperand(1);
24976 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24977 if (C->getValueAPF().isPosZero())
24978 return N->getOperand(0);
24982 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24983 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24984 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24986 // Only perform optimizations if UnsafeMath is used.
24987 if (!DAG.getTarget().Options.UnsafeFPMath)
24990 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24991 // into FMINC and FMAXC, which are Commutative operations.
24992 unsigned NewOp = 0;
24993 switch (N->getOpcode()) {
24994 default: llvm_unreachable("unknown opcode");
24995 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24996 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24999 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25000 N->getOperand(0), N->getOperand(1));
25003 /// Do target-specific dag combines on X86ISD::FAND nodes.
25004 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25005 // FAND(0.0, x) -> 0.0
25006 // FAND(x, 0.0) -> 0.0
25007 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25008 if (C->getValueAPF().isPosZero())
25009 return N->getOperand(0);
25010 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25011 if (C->getValueAPF().isPosZero())
25012 return N->getOperand(1);
25016 /// Do target-specific dag combines on X86ISD::FANDN nodes
25017 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25018 // FANDN(x, 0.0) -> 0.0
25019 // FANDN(0.0, x) -> x
25020 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25021 if (C->getValueAPF().isPosZero())
25022 return N->getOperand(1);
25023 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25024 if (C->getValueAPF().isPosZero())
25025 return N->getOperand(1);
25029 static SDValue PerformBTCombine(SDNode *N,
25031 TargetLowering::DAGCombinerInfo &DCI) {
25032 // BT ignores high bits in the bit index operand.
25033 SDValue Op1 = N->getOperand(1);
25034 if (Op1.hasOneUse()) {
25035 unsigned BitWidth = Op1.getValueSizeInBits();
25036 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25037 APInt KnownZero, KnownOne;
25038 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25039 !DCI.isBeforeLegalizeOps());
25040 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25041 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25042 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25043 DCI.CommitTargetLoweringOpt(TLO);
25048 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25049 SDValue Op = N->getOperand(0);
25050 if (Op.getOpcode() == ISD::BITCAST)
25051 Op = Op.getOperand(0);
25052 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25053 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25054 VT.getVectorElementType().getSizeInBits() ==
25055 OpVT.getVectorElementType().getSizeInBits()) {
25056 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25061 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25062 const X86Subtarget *Subtarget) {
25063 EVT VT = N->getValueType(0);
25064 if (!VT.isVector())
25067 SDValue N0 = N->getOperand(0);
25068 SDValue N1 = N->getOperand(1);
25069 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25072 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25073 // both SSE and AVX2 since there is no sign-extended shift right
25074 // operation on a vector with 64-bit elements.
25075 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25076 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25077 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25078 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25079 SDValue N00 = N0.getOperand(0);
25081 // EXTLOAD has a better solution on AVX2,
25082 // it may be replaced with X86ISD::VSEXT node.
25083 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25084 if (!ISD::isNormalLoad(N00.getNode()))
25087 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25088 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25090 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25096 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25097 TargetLowering::DAGCombinerInfo &DCI,
25098 const X86Subtarget *Subtarget) {
25099 SDValue N0 = N->getOperand(0);
25100 EVT VT = N->getValueType(0);
25102 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25103 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25104 // This exposes the sext to the sdivrem lowering, so that it directly extends
25105 // from AH (which we otherwise need to do contortions to access).
25106 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25107 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25109 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25110 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25111 N0.getOperand(0), N0.getOperand(1));
25112 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25113 return R.getValue(1);
25116 if (!DCI.isBeforeLegalizeOps())
25119 if (!Subtarget->hasFp256())
25122 if (VT.isVector() && VT.getSizeInBits() == 256) {
25123 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25131 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25132 const X86Subtarget* Subtarget) {
25134 EVT VT = N->getValueType(0);
25136 // Let legalize expand this if it isn't a legal type yet.
25137 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25140 EVT ScalarVT = VT.getScalarType();
25141 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25142 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25145 SDValue A = N->getOperand(0);
25146 SDValue B = N->getOperand(1);
25147 SDValue C = N->getOperand(2);
25149 bool NegA = (A.getOpcode() == ISD::FNEG);
25150 bool NegB = (B.getOpcode() == ISD::FNEG);
25151 bool NegC = (C.getOpcode() == ISD::FNEG);
25153 // Negative multiplication when NegA xor NegB
25154 bool NegMul = (NegA != NegB);
25156 A = A.getOperand(0);
25158 B = B.getOperand(0);
25160 C = C.getOperand(0);
25164 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25166 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25168 return DAG.getNode(Opcode, dl, VT, A, B, C);
25171 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25172 TargetLowering::DAGCombinerInfo &DCI,
25173 const X86Subtarget *Subtarget) {
25174 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25175 // (and (i32 x86isd::setcc_carry), 1)
25176 // This eliminates the zext. This transformation is necessary because
25177 // ISD::SETCC is always legalized to i8.
25179 SDValue N0 = N->getOperand(0);
25180 EVT VT = N->getValueType(0);
25182 if (N0.getOpcode() == ISD::AND &&
25184 N0.getOperand(0).hasOneUse()) {
25185 SDValue N00 = N0.getOperand(0);
25186 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25187 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25188 if (!C || C->getZExtValue() != 1)
25190 return DAG.getNode(ISD::AND, dl, VT,
25191 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25192 N00.getOperand(0), N00.getOperand(1)),
25193 DAG.getConstant(1, VT));
25197 if (N0.getOpcode() == ISD::TRUNCATE &&
25199 N0.getOperand(0).hasOneUse()) {
25200 SDValue N00 = N0.getOperand(0);
25201 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25202 return DAG.getNode(ISD::AND, dl, VT,
25203 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25204 N00.getOperand(0), N00.getOperand(1)),
25205 DAG.getConstant(1, VT));
25208 if (VT.is256BitVector()) {
25209 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25214 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25215 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25216 // This exposes the zext to the udivrem lowering, so that it directly extends
25217 // from AH (which we otherwise need to do contortions to access).
25218 if (N0.getOpcode() == ISD::UDIVREM &&
25219 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25220 (VT == MVT::i32 || VT == MVT::i64)) {
25221 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25222 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25223 N0.getOperand(0), N0.getOperand(1));
25224 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25225 return R.getValue(1);
25231 // Optimize x == -y --> x+y == 0
25232 // x != -y --> x+y != 0
25233 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25234 const X86Subtarget* Subtarget) {
25235 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25236 SDValue LHS = N->getOperand(0);
25237 SDValue RHS = N->getOperand(1);
25238 EVT VT = N->getValueType(0);
25241 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25243 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25244 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25245 LHS.getValueType(), RHS, LHS.getOperand(1));
25246 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25247 addV, DAG.getConstant(0, addV.getValueType()), CC);
25249 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25251 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25252 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25253 RHS.getValueType(), LHS, RHS.getOperand(1));
25254 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25255 addV, DAG.getConstant(0, addV.getValueType()), CC);
25258 if (VT.getScalarType() == MVT::i1) {
25259 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25260 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25261 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25262 if (!IsSEXT0 && !IsVZero0)
25264 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25265 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25266 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25268 if (!IsSEXT1 && !IsVZero1)
25271 if (IsSEXT0 && IsVZero1) {
25272 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25273 if (CC == ISD::SETEQ)
25274 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25275 return LHS.getOperand(0);
25277 if (IsSEXT1 && IsVZero0) {
25278 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25279 if (CC == ISD::SETEQ)
25280 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25281 return RHS.getOperand(0);
25288 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25289 const X86Subtarget *Subtarget) {
25291 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25292 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25293 "X86insertps is only defined for v4x32");
25295 SDValue Ld = N->getOperand(1);
25296 if (MayFoldLoad(Ld)) {
25297 // Extract the countS bits from the immediate so we can get the proper
25298 // address when narrowing the vector load to a specific element.
25299 // When the second source op is a memory address, interps doesn't use
25300 // countS and just gets an f32 from that address.
25301 unsigned DestIndex =
25302 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25303 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25307 // Create this as a scalar to vector to match the instruction pattern.
25308 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25309 // countS bits are ignored when loading from memory on insertps, which
25310 // means we don't need to explicitly set them to 0.
25311 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25312 LoadScalarToVector, N->getOperand(2));
25315 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25316 // as "sbb reg,reg", since it can be extended without zext and produces
25317 // an all-ones bit which is more useful than 0/1 in some cases.
25318 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25321 return DAG.getNode(ISD::AND, DL, VT,
25322 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25323 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25324 DAG.getConstant(1, VT));
25325 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25326 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25327 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25328 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25331 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25332 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25333 TargetLowering::DAGCombinerInfo &DCI,
25334 const X86Subtarget *Subtarget) {
25336 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25337 SDValue EFLAGS = N->getOperand(1);
25339 if (CC == X86::COND_A) {
25340 // Try to convert COND_A into COND_B in an attempt to facilitate
25341 // materializing "setb reg".
25343 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25344 // cannot take an immediate as its first operand.
25346 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25347 EFLAGS.getValueType().isInteger() &&
25348 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25349 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25350 EFLAGS.getNode()->getVTList(),
25351 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25352 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25353 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25357 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25358 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25360 if (CC == X86::COND_B)
25361 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25365 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25366 if (Flags.getNode()) {
25367 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25368 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25374 // Optimize branch condition evaluation.
25376 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25377 TargetLowering::DAGCombinerInfo &DCI,
25378 const X86Subtarget *Subtarget) {
25380 SDValue Chain = N->getOperand(0);
25381 SDValue Dest = N->getOperand(1);
25382 SDValue EFLAGS = N->getOperand(3);
25383 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25387 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25388 if (Flags.getNode()) {
25389 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25390 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25397 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25398 SelectionDAG &DAG) {
25399 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25400 // optimize away operation when it's from a constant.
25402 // The general transformation is:
25403 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25404 // AND(VECTOR_CMP(x,y), constant2)
25405 // constant2 = UNARYOP(constant)
25407 // Early exit if this isn't a vector operation, the operand of the
25408 // unary operation isn't a bitwise AND, or if the sizes of the operations
25409 // aren't the same.
25410 EVT VT = N->getValueType(0);
25411 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25412 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25413 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25416 // Now check that the other operand of the AND is a constant. We could
25417 // make the transformation for non-constant splats as well, but it's unclear
25418 // that would be a benefit as it would not eliminate any operations, just
25419 // perform one more step in scalar code before moving to the vector unit.
25420 if (BuildVectorSDNode *BV =
25421 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25422 // Bail out if the vector isn't a constant.
25423 if (!BV->isConstant())
25426 // Everything checks out. Build up the new and improved node.
25428 EVT IntVT = BV->getValueType(0);
25429 // Create a new constant of the appropriate type for the transformed
25431 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25432 // The AND node needs bitcasts to/from an integer vector type around it.
25433 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25434 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25435 N->getOperand(0)->getOperand(0), MaskConst);
25436 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25443 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25444 const X86TargetLowering *XTLI) {
25445 // First try to optimize away the conversion entirely when it's
25446 // conditionally from a constant. Vectors only.
25447 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25448 if (Res != SDValue())
25451 // Now move on to more general possibilities.
25452 SDValue Op0 = N->getOperand(0);
25453 EVT InVT = Op0->getValueType(0);
25455 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25456 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25458 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25459 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25460 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25463 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25464 // a 32-bit target where SSE doesn't support i64->FP operations.
25465 if (Op0.getOpcode() == ISD::LOAD) {
25466 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25467 EVT VT = Ld->getValueType(0);
25468 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25469 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25470 !XTLI->getSubtarget()->is64Bit() &&
25472 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25473 Ld->getChain(), Op0, DAG);
25474 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25481 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25482 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25483 X86TargetLowering::DAGCombinerInfo &DCI) {
25484 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25485 // the result is either zero or one (depending on the input carry bit).
25486 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25487 if (X86::isZeroNode(N->getOperand(0)) &&
25488 X86::isZeroNode(N->getOperand(1)) &&
25489 // We don't have a good way to replace an EFLAGS use, so only do this when
25491 SDValue(N, 1).use_empty()) {
25493 EVT VT = N->getValueType(0);
25494 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25495 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25496 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25497 DAG.getConstant(X86::COND_B,MVT::i8),
25499 DAG.getConstant(1, VT));
25500 return DCI.CombineTo(N, Res1, CarryOut);
25506 // fold (add Y, (sete X, 0)) -> adc 0, Y
25507 // (add Y, (setne X, 0)) -> sbb -1, Y
25508 // (sub (sete X, 0), Y) -> sbb 0, Y
25509 // (sub (setne X, 0), Y) -> adc -1, Y
25510 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25513 // Look through ZExts.
25514 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25515 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25518 SDValue SetCC = Ext.getOperand(0);
25519 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25522 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25523 if (CC != X86::COND_E && CC != X86::COND_NE)
25526 SDValue Cmp = SetCC.getOperand(1);
25527 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25528 !X86::isZeroNode(Cmp.getOperand(1)) ||
25529 !Cmp.getOperand(0).getValueType().isInteger())
25532 SDValue CmpOp0 = Cmp.getOperand(0);
25533 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25534 DAG.getConstant(1, CmpOp0.getValueType()));
25536 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25537 if (CC == X86::COND_NE)
25538 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25539 DL, OtherVal.getValueType(), OtherVal,
25540 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25541 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25542 DL, OtherVal.getValueType(), OtherVal,
25543 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25546 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25547 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25548 const X86Subtarget *Subtarget) {
25549 EVT VT = N->getValueType(0);
25550 SDValue Op0 = N->getOperand(0);
25551 SDValue Op1 = N->getOperand(1);
25553 // Try to synthesize horizontal adds from adds of shuffles.
25554 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25555 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25556 isHorizontalBinOp(Op0, Op1, true))
25557 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25559 return OptimizeConditionalInDecrement(N, DAG);
25562 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25563 const X86Subtarget *Subtarget) {
25564 SDValue Op0 = N->getOperand(0);
25565 SDValue Op1 = N->getOperand(1);
25567 // X86 can't encode an immediate LHS of a sub. See if we can push the
25568 // negation into a preceding instruction.
25569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25570 // If the RHS of the sub is a XOR with one use and a constant, invert the
25571 // immediate. Then add one to the LHS of the sub so we can turn
25572 // X-Y -> X+~Y+1, saving one register.
25573 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25574 isa<ConstantSDNode>(Op1.getOperand(1))) {
25575 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25576 EVT VT = Op0.getValueType();
25577 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25579 DAG.getConstant(~XorC, VT));
25580 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25581 DAG.getConstant(C->getAPIntValue()+1, VT));
25585 // Try to synthesize horizontal adds from adds of shuffles.
25586 EVT VT = N->getValueType(0);
25587 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25588 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25589 isHorizontalBinOp(Op0, Op1, true))
25590 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25592 return OptimizeConditionalInDecrement(N, DAG);
25595 /// performVZEXTCombine - Performs build vector combines
25596 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25597 TargetLowering::DAGCombinerInfo &DCI,
25598 const X86Subtarget *Subtarget) {
25600 MVT VT = N->getSimpleValueType(0);
25601 SDValue Op = N->getOperand(0);
25602 MVT OpVT = Op.getSimpleValueType();
25603 MVT OpEltVT = OpVT.getVectorElementType();
25604 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25606 // (vzext (bitcast (vzext (x)) -> (vzext x)
25608 while (V.getOpcode() == ISD::BITCAST)
25609 V = V.getOperand(0);
25611 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25612 MVT InnerVT = V.getSimpleValueType();
25613 MVT InnerEltVT = InnerVT.getVectorElementType();
25615 // If the element sizes match exactly, we can just do one larger vzext. This
25616 // is always an exact type match as vzext operates on integer types.
25617 if (OpEltVT == InnerEltVT) {
25618 assert(OpVT == InnerVT && "Types must match for vzext!");
25619 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25622 // The only other way we can combine them is if only a single element of the
25623 // inner vzext is used in the input to the outer vzext.
25624 if (InnerEltVT.getSizeInBits() < InputBits)
25627 // In this case, the inner vzext is completely dead because we're going to
25628 // only look at bits inside of the low element. Just do the outer vzext on
25629 // a bitcast of the input to the inner.
25630 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25631 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25634 // Check if we can bypass extracting and re-inserting an element of an input
25635 // vector. Essentialy:
25636 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25637 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25638 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25639 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25640 SDValue ExtractedV = V.getOperand(0);
25641 SDValue OrigV = ExtractedV.getOperand(0);
25642 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25643 if (ExtractIdx->getZExtValue() == 0) {
25644 MVT OrigVT = OrigV.getSimpleValueType();
25645 // Extract a subvector if necessary...
25646 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25647 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25648 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25649 OrigVT.getVectorNumElements() / Ratio);
25650 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25651 DAG.getIntPtrConstant(0));
25653 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25654 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25661 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25662 DAGCombinerInfo &DCI) const {
25663 SelectionDAG &DAG = DCI.DAG;
25664 switch (N->getOpcode()) {
25666 case ISD::EXTRACT_VECTOR_ELT:
25667 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25670 case X86ISD::SHRUNKBLEND:
25671 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25672 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25673 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25674 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25675 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25676 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25679 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25680 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25681 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25682 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25683 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25684 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25685 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25686 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25687 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25689 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25691 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25692 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25693 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25694 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25695 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25696 case ISD::ANY_EXTEND:
25697 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25698 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25699 case ISD::SIGN_EXTEND_INREG:
25700 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25701 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25702 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25703 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25704 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25705 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25706 case X86ISD::SHUFP: // Handle all target specific shuffles
25707 case X86ISD::PALIGNR:
25708 case X86ISD::UNPCKH:
25709 case X86ISD::UNPCKL:
25710 case X86ISD::MOVHLPS:
25711 case X86ISD::MOVLHPS:
25712 case X86ISD::PSHUFB:
25713 case X86ISD::PSHUFD:
25714 case X86ISD::PSHUFHW:
25715 case X86ISD::PSHUFLW:
25716 case X86ISD::MOVSS:
25717 case X86ISD::MOVSD:
25718 case X86ISD::VPERMILPI:
25719 case X86ISD::VPERM2X128:
25720 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25721 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25722 case ISD::INTRINSIC_WO_CHAIN:
25723 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25724 case X86ISD::INSERTPS:
25725 return PerformINSERTPSCombine(N, DAG, Subtarget);
25726 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25732 /// isTypeDesirableForOp - Return true if the target has native support for
25733 /// the specified value type and it is 'desirable' to use the type for the
25734 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25735 /// instruction encodings are longer and some i16 instructions are slow.
25736 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25737 if (!isTypeLegal(VT))
25739 if (VT != MVT::i16)
25746 case ISD::SIGN_EXTEND:
25747 case ISD::ZERO_EXTEND:
25748 case ISD::ANY_EXTEND:
25761 /// IsDesirableToPromoteOp - This method query the target whether it is
25762 /// beneficial for dag combiner to promote the specified node. If true, it
25763 /// should return the desired promotion type by reference.
25764 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25765 EVT VT = Op.getValueType();
25766 if (VT != MVT::i16)
25769 bool Promote = false;
25770 bool Commute = false;
25771 switch (Op.getOpcode()) {
25774 LoadSDNode *LD = cast<LoadSDNode>(Op);
25775 // If the non-extending load has a single use and it's not live out, then it
25776 // might be folded.
25777 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25778 Op.hasOneUse()*/) {
25779 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25780 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25781 // The only case where we'd want to promote LOAD (rather then it being
25782 // promoted as an operand is when it's only use is liveout.
25783 if (UI->getOpcode() != ISD::CopyToReg)
25790 case ISD::SIGN_EXTEND:
25791 case ISD::ZERO_EXTEND:
25792 case ISD::ANY_EXTEND:
25797 SDValue N0 = Op.getOperand(0);
25798 // Look out for (store (shl (load), x)).
25799 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25812 SDValue N0 = Op.getOperand(0);
25813 SDValue N1 = Op.getOperand(1);
25814 if (!Commute && MayFoldLoad(N1))
25816 // Avoid disabling potential load folding opportunities.
25817 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25819 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25829 //===----------------------------------------------------------------------===//
25830 // X86 Inline Assembly Support
25831 //===----------------------------------------------------------------------===//
25834 // Helper to match a string separated by whitespace.
25835 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25836 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25838 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25839 StringRef piece(*args[i]);
25840 if (!s.startswith(piece)) // Check if the piece matches.
25843 s = s.substr(piece.size());
25844 StringRef::size_type pos = s.find_first_not_of(" \t");
25845 if (pos == 0) // We matched a prefix.
25853 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25856 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25858 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25859 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25860 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25861 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25863 if (AsmPieces.size() == 3)
25865 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25872 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25873 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25875 std::string AsmStr = IA->getAsmString();
25877 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25878 if (!Ty || Ty->getBitWidth() % 16 != 0)
25881 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25882 SmallVector<StringRef, 4> AsmPieces;
25883 SplitString(AsmStr, AsmPieces, ";\n");
25885 switch (AsmPieces.size()) {
25886 default: return false;
25888 // FIXME: this should verify that we are targeting a 486 or better. If not,
25889 // we will turn this bswap into something that will be lowered to logical
25890 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25891 // lower so don't worry about this.
25893 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25894 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25895 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25896 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25897 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25898 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25899 // No need to check constraints, nothing other than the equivalent of
25900 // "=r,0" would be valid here.
25901 return IntrinsicLowering::LowerToByteSwap(CI);
25904 // rorw $$8, ${0:w} --> llvm.bswap.i16
25905 if (CI->getType()->isIntegerTy(16) &&
25906 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25907 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25908 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25910 const std::string &ConstraintsStr = IA->getConstraintString();
25911 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25912 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25913 if (clobbersFlagRegisters(AsmPieces))
25914 return IntrinsicLowering::LowerToByteSwap(CI);
25918 if (CI->getType()->isIntegerTy(32) &&
25919 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25920 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25921 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25922 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25924 const std::string &ConstraintsStr = IA->getConstraintString();
25925 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25926 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25927 if (clobbersFlagRegisters(AsmPieces))
25928 return IntrinsicLowering::LowerToByteSwap(CI);
25931 if (CI->getType()->isIntegerTy(64)) {
25932 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25933 if (Constraints.size() >= 2 &&
25934 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25935 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25936 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25937 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25938 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25939 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25940 return IntrinsicLowering::LowerToByteSwap(CI);
25948 /// getConstraintType - Given a constraint letter, return the type of
25949 /// constraint it is for this target.
25950 X86TargetLowering::ConstraintType
25951 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25952 if (Constraint.size() == 1) {
25953 switch (Constraint[0]) {
25964 return C_RegisterClass;
25988 return TargetLowering::getConstraintType(Constraint);
25991 /// Examine constraint type and operand type and determine a weight value.
25992 /// This object must already have been set up with the operand type
25993 /// and the current alternative constraint selected.
25994 TargetLowering::ConstraintWeight
25995 X86TargetLowering::getSingleConstraintMatchWeight(
25996 AsmOperandInfo &info, const char *constraint) const {
25997 ConstraintWeight weight = CW_Invalid;
25998 Value *CallOperandVal = info.CallOperandVal;
25999 // If we don't have a value, we can't do a match,
26000 // but allow it at the lowest weight.
26001 if (!CallOperandVal)
26003 Type *type = CallOperandVal->getType();
26004 // Look at the constraint type.
26005 switch (*constraint) {
26007 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26018 if (CallOperandVal->getType()->isIntegerTy())
26019 weight = CW_SpecificReg;
26024 if (type->isFloatingPointTy())
26025 weight = CW_SpecificReg;
26028 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26029 weight = CW_SpecificReg;
26033 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26034 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26035 weight = CW_Register;
26038 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26039 if (C->getZExtValue() <= 31)
26040 weight = CW_Constant;
26044 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26045 if (C->getZExtValue() <= 63)
26046 weight = CW_Constant;
26050 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26051 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26052 weight = CW_Constant;
26056 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26057 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26058 weight = CW_Constant;
26062 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26063 if (C->getZExtValue() <= 3)
26064 weight = CW_Constant;
26068 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26069 if (C->getZExtValue() <= 0xff)
26070 weight = CW_Constant;
26075 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26076 weight = CW_Constant;
26080 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26081 if ((C->getSExtValue() >= -0x80000000LL) &&
26082 (C->getSExtValue() <= 0x7fffffffLL))
26083 weight = CW_Constant;
26087 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26088 if (C->getZExtValue() <= 0xffffffff)
26089 weight = CW_Constant;
26096 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26097 /// with another that has more specific requirements based on the type of the
26098 /// corresponding operand.
26099 const char *X86TargetLowering::
26100 LowerXConstraint(EVT ConstraintVT) const {
26101 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26102 // 'f' like normal targets.
26103 if (ConstraintVT.isFloatingPoint()) {
26104 if (Subtarget->hasSSE2())
26106 if (Subtarget->hasSSE1())
26110 return TargetLowering::LowerXConstraint(ConstraintVT);
26113 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26114 /// vector. If it is invalid, don't add anything to Ops.
26115 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26116 std::string &Constraint,
26117 std::vector<SDValue>&Ops,
26118 SelectionDAG &DAG) const {
26121 // Only support length 1 constraints for now.
26122 if (Constraint.length() > 1) return;
26124 char ConstraintLetter = Constraint[0];
26125 switch (ConstraintLetter) {
26128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26129 if (C->getZExtValue() <= 31) {
26130 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26137 if (C->getZExtValue() <= 63) {
26138 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26145 if (isInt<8>(C->getSExtValue())) {
26146 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26153 if (C->getZExtValue() <= 255) {
26154 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26160 // 32-bit signed value
26161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26162 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26163 C->getSExtValue())) {
26164 // Widen to 64 bits here to get it sign extended.
26165 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26168 // FIXME gcc accepts some relocatable values here too, but only in certain
26169 // memory models; it's complicated.
26174 // 32-bit unsigned value
26175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26176 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26177 C->getZExtValue())) {
26178 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26182 // FIXME gcc accepts some relocatable values here too, but only in certain
26183 // memory models; it's complicated.
26187 // Literal immediates are always ok.
26188 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26189 // Widen to 64 bits here to get it sign extended.
26190 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26194 // In any sort of PIC mode addresses need to be computed at runtime by
26195 // adding in a register or some sort of table lookup. These can't
26196 // be used as immediates.
26197 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26200 // If we are in non-pic codegen mode, we allow the address of a global (with
26201 // an optional displacement) to be used with 'i'.
26202 GlobalAddressSDNode *GA = nullptr;
26203 int64_t Offset = 0;
26205 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26207 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26208 Offset += GA->getOffset();
26210 } else if (Op.getOpcode() == ISD::ADD) {
26211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26212 Offset += C->getZExtValue();
26213 Op = Op.getOperand(0);
26216 } else if (Op.getOpcode() == ISD::SUB) {
26217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26218 Offset += -C->getZExtValue();
26219 Op = Op.getOperand(0);
26224 // Otherwise, this isn't something we can handle, reject it.
26228 const GlobalValue *GV = GA->getGlobal();
26229 // If we require an extra load to get this address, as in PIC mode, we
26230 // can't accept it.
26231 if (isGlobalStubReference(
26232 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26235 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26236 GA->getValueType(0), Offset);
26241 if (Result.getNode()) {
26242 Ops.push_back(Result);
26245 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26248 std::pair<unsigned, const TargetRegisterClass*>
26249 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26251 // First, see if this is a constraint that directly corresponds to an LLVM
26253 if (Constraint.size() == 1) {
26254 // GCC Constraint Letters
26255 switch (Constraint[0]) {
26257 // TODO: Slight differences here in allocation order and leaving
26258 // RIP in the class. Do they matter any more here than they do
26259 // in the normal allocation?
26260 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26261 if (Subtarget->is64Bit()) {
26262 if (VT == MVT::i32 || VT == MVT::f32)
26263 return std::make_pair(0U, &X86::GR32RegClass);
26264 if (VT == MVT::i16)
26265 return std::make_pair(0U, &X86::GR16RegClass);
26266 if (VT == MVT::i8 || VT == MVT::i1)
26267 return std::make_pair(0U, &X86::GR8RegClass);
26268 if (VT == MVT::i64 || VT == MVT::f64)
26269 return std::make_pair(0U, &X86::GR64RegClass);
26272 // 32-bit fallthrough
26273 case 'Q': // Q_REGS
26274 if (VT == MVT::i32 || VT == MVT::f32)
26275 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26276 if (VT == MVT::i16)
26277 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26278 if (VT == MVT::i8 || VT == MVT::i1)
26279 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26280 if (VT == MVT::i64)
26281 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26283 case 'r': // GENERAL_REGS
26284 case 'l': // INDEX_REGS
26285 if (VT == MVT::i8 || VT == MVT::i1)
26286 return std::make_pair(0U, &X86::GR8RegClass);
26287 if (VT == MVT::i16)
26288 return std::make_pair(0U, &X86::GR16RegClass);
26289 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26290 return std::make_pair(0U, &X86::GR32RegClass);
26291 return std::make_pair(0U, &X86::GR64RegClass);
26292 case 'R': // LEGACY_REGS
26293 if (VT == MVT::i8 || VT == MVT::i1)
26294 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26295 if (VT == MVT::i16)
26296 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26297 if (VT == MVT::i32 || !Subtarget->is64Bit())
26298 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26299 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26300 case 'f': // FP Stack registers.
26301 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26302 // value to the correct fpstack register class.
26303 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26304 return std::make_pair(0U, &X86::RFP32RegClass);
26305 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26306 return std::make_pair(0U, &X86::RFP64RegClass);
26307 return std::make_pair(0U, &X86::RFP80RegClass);
26308 case 'y': // MMX_REGS if MMX allowed.
26309 if (!Subtarget->hasMMX()) break;
26310 return std::make_pair(0U, &X86::VR64RegClass);
26311 case 'Y': // SSE_REGS if SSE2 allowed
26312 if (!Subtarget->hasSSE2()) break;
26314 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26315 if (!Subtarget->hasSSE1()) break;
26317 switch (VT.SimpleTy) {
26319 // Scalar SSE types.
26322 return std::make_pair(0U, &X86::FR32RegClass);
26325 return std::make_pair(0U, &X86::FR64RegClass);
26333 return std::make_pair(0U, &X86::VR128RegClass);
26341 return std::make_pair(0U, &X86::VR256RegClass);
26346 return std::make_pair(0U, &X86::VR512RegClass);
26352 // Use the default implementation in TargetLowering to convert the register
26353 // constraint into a member of a register class.
26354 std::pair<unsigned, const TargetRegisterClass*> Res;
26355 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26357 // Not found as a standard register?
26359 // Map st(0) -> st(7) -> ST0
26360 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26361 tolower(Constraint[1]) == 's' &&
26362 tolower(Constraint[2]) == 't' &&
26363 Constraint[3] == '(' &&
26364 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26365 Constraint[5] == ')' &&
26366 Constraint[6] == '}') {
26368 Res.first = X86::FP0+Constraint[4]-'0';
26369 Res.second = &X86::RFP80RegClass;
26373 // GCC allows "st(0)" to be called just plain "st".
26374 if (StringRef("{st}").equals_lower(Constraint)) {
26375 Res.first = X86::FP0;
26376 Res.second = &X86::RFP80RegClass;
26381 if (StringRef("{flags}").equals_lower(Constraint)) {
26382 Res.first = X86::EFLAGS;
26383 Res.second = &X86::CCRRegClass;
26387 // 'A' means EAX + EDX.
26388 if (Constraint == "A") {
26389 Res.first = X86::EAX;
26390 Res.second = &X86::GR32_ADRegClass;
26396 // Otherwise, check to see if this is a register class of the wrong value
26397 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26398 // turn into {ax},{dx}.
26399 if (Res.second->hasType(VT))
26400 return Res; // Correct type already, nothing to do.
26402 // All of the single-register GCC register classes map their values onto
26403 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26404 // really want an 8-bit or 32-bit register, map to the appropriate register
26405 // class and return the appropriate register.
26406 if (Res.second == &X86::GR16RegClass) {
26407 if (VT == MVT::i8 || VT == MVT::i1) {
26408 unsigned DestReg = 0;
26409 switch (Res.first) {
26411 case X86::AX: DestReg = X86::AL; break;
26412 case X86::DX: DestReg = X86::DL; break;
26413 case X86::CX: DestReg = X86::CL; break;
26414 case X86::BX: DestReg = X86::BL; break;
26417 Res.first = DestReg;
26418 Res.second = &X86::GR8RegClass;
26420 } else if (VT == MVT::i32 || VT == MVT::f32) {
26421 unsigned DestReg = 0;
26422 switch (Res.first) {
26424 case X86::AX: DestReg = X86::EAX; break;
26425 case X86::DX: DestReg = X86::EDX; break;
26426 case X86::CX: DestReg = X86::ECX; break;
26427 case X86::BX: DestReg = X86::EBX; break;
26428 case X86::SI: DestReg = X86::ESI; break;
26429 case X86::DI: DestReg = X86::EDI; break;
26430 case X86::BP: DestReg = X86::EBP; break;
26431 case X86::SP: DestReg = X86::ESP; break;
26434 Res.first = DestReg;
26435 Res.second = &X86::GR32RegClass;
26437 } else if (VT == MVT::i64 || VT == MVT::f64) {
26438 unsigned DestReg = 0;
26439 switch (Res.first) {
26441 case X86::AX: DestReg = X86::RAX; break;
26442 case X86::DX: DestReg = X86::RDX; break;
26443 case X86::CX: DestReg = X86::RCX; break;
26444 case X86::BX: DestReg = X86::RBX; break;
26445 case X86::SI: DestReg = X86::RSI; break;
26446 case X86::DI: DestReg = X86::RDI; break;
26447 case X86::BP: DestReg = X86::RBP; break;
26448 case X86::SP: DestReg = X86::RSP; break;
26451 Res.first = DestReg;
26452 Res.second = &X86::GR64RegClass;
26455 } else if (Res.second == &X86::FR32RegClass ||
26456 Res.second == &X86::FR64RegClass ||
26457 Res.second == &X86::VR128RegClass ||
26458 Res.second == &X86::VR256RegClass ||
26459 Res.second == &X86::FR32XRegClass ||
26460 Res.second == &X86::FR64XRegClass ||
26461 Res.second == &X86::VR128XRegClass ||
26462 Res.second == &X86::VR256XRegClass ||
26463 Res.second == &X86::VR512RegClass) {
26464 // Handle references to XMM physical registers that got mapped into the
26465 // wrong class. This can happen with constraints like {xmm0} where the
26466 // target independent register mapper will just pick the first match it can
26467 // find, ignoring the required type.
26469 if (VT == MVT::f32 || VT == MVT::i32)
26470 Res.second = &X86::FR32RegClass;
26471 else if (VT == MVT::f64 || VT == MVT::i64)
26472 Res.second = &X86::FR64RegClass;
26473 else if (X86::VR128RegClass.hasType(VT))
26474 Res.second = &X86::VR128RegClass;
26475 else if (X86::VR256RegClass.hasType(VT))
26476 Res.second = &X86::VR256RegClass;
26477 else if (X86::VR512RegClass.hasType(VT))
26478 Res.second = &X86::VR512RegClass;
26484 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26486 // Scaling factors are not free at all.
26487 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26488 // will take 2 allocations in the out of order engine instead of 1
26489 // for plain addressing mode, i.e. inst (reg1).
26491 // vaddps (%rsi,%drx), %ymm0, %ymm1
26492 // Requires two allocations (one for the load, one for the computation)
26494 // vaddps (%rsi), %ymm0, %ymm1
26495 // Requires just 1 allocation, i.e., freeing allocations for other operations
26496 // and having less micro operations to execute.
26498 // For some X86 architectures, this is even worse because for instance for
26499 // stores, the complex addressing mode forces the instruction to use the
26500 // "load" ports instead of the dedicated "store" port.
26501 // E.g., on Haswell:
26502 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26503 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26504 if (isLegalAddressingMode(AM, Ty))
26505 // Scale represents reg2 * scale, thus account for 1
26506 // as soon as we use a second register.
26507 return AM.Scale != 0;
26511 bool X86TargetLowering::isTargetFTOL() const {
26512 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();