1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 static cl::opt<bool> UseRegMask("x86-use-regmask",
61 cl::desc("Use register masks for x86 calls"));
63 // Forward declarations.
64 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
67 static SDValue Insert128BitVector(SDValue Result,
73 static SDValue Extract128BitVector(SDValue Vec,
78 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
79 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
80 /// simple subregister reference. Idx is an index in the 128 bits we
81 /// want. It need not be aligned to a 128-bit bounday. That makes
82 /// lowering EXTRACT_VECTOR_ELT operations easier.
83 static SDValue Extract128BitVector(SDValue Vec,
87 EVT VT = Vec.getValueType();
88 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
89 EVT ElVT = VT.getVectorElementType();
90 int Factor = VT.getSizeInBits()/128;
91 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
92 VT.getVectorNumElements()/Factor);
94 // Extract from UNDEF is UNDEF.
95 if (Vec.getOpcode() == ISD::UNDEF)
96 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
98 if (isa<ConstantSDNode>(Idx)) {
99 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
101 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
102 // we can match to VEXTRACTF128.
103 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
105 // This is the index of the first element of the 128-bit chunk
107 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
110 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
111 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
121 /// sets things up to match to an AVX VINSERTF128 instruction or a
122 /// simple superregister reference. Idx is an index in the 128 bits
123 /// we want. It need not be aligned to a 128-bit bounday. That makes
124 /// lowering INSERT_VECTOR_ELT operations easier.
125 static SDValue Insert128BitVector(SDValue Result,
130 if (isa<ConstantSDNode>(Idx)) {
131 EVT VT = Vec.getValueType();
132 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
134 EVT ElVT = VT.getVectorElementType();
135 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
136 EVT ResultVT = Result.getValueType();
138 // Insert the relevant 128 bits.
139 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
141 // This is the index of the first element of the 128-bit chunk
143 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
146 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
147 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
155 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
156 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
157 bool is64Bit = Subtarget->is64Bit();
159 if (Subtarget->isTargetEnvMacho()) {
161 return new X8664_MachoTargetObjectFile();
162 return new TargetLoweringObjectFileMachO();
165 if (Subtarget->isTargetELF())
166 return new TargetLoweringObjectFileELF();
167 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
168 return new TargetLoweringObjectFileCOFF();
169 llvm_unreachable("unknown subtarget type");
172 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
173 : TargetLowering(TM, createTLOF(TM)) {
174 Subtarget = &TM.getSubtarget<X86Subtarget>();
175 X86ScalarSSEf64 = Subtarget->hasSSE2();
176 X86ScalarSSEf32 = Subtarget->hasSSE1();
177 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
179 RegInfo = TM.getRegisterInfo();
180 TD = getTargetData();
182 // Set up the TargetLowering object.
183 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
185 // X86 is weird, it always uses i8 for shift amounts and setcc results.
186 setBooleanContents(ZeroOrOneBooleanContent);
187 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
188 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
190 // For 64-bit since we have so many registers use the ILP scheduler, for
191 // 32-bit code use the register pressure specific scheduling.
192 if (Subtarget->is64Bit())
193 setSchedulingPreference(Sched::ILP);
195 setSchedulingPreference(Sched::RegPressure);
196 setStackPointerRegisterToSaveRestore(X86StackPtr);
198 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
199 // Setup Windows compiler runtime calls.
200 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
201 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
202 setLibcallName(RTLIB::SREM_I64, "_allrem");
203 setLibcallName(RTLIB::UREM_I64, "_aullrem");
204 setLibcallName(RTLIB::MUL_I64, "_allmul");
205 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
206 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
207 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
210 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
211 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
212 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
213 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
216 if (Subtarget->isTargetDarwin()) {
217 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
218 setUseUnderscoreSetJmp(false);
219 setUseUnderscoreLongJmp(false);
220 } else if (Subtarget->isTargetMingw()) {
221 // MS runtime is weird: it exports _setjmp, but longjmp!
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(false);
225 setUseUnderscoreSetJmp(true);
226 setUseUnderscoreLongJmp(true);
229 // Set up the register classes.
230 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
231 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
232 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
233 if (Subtarget->is64Bit())
234 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
236 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
238 // We don't accept any truncstore of integer registers.
239 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
240 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
241 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
242 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
243 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
244 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
246 // SETOEQ and SETUNE require checking two conditions.
247 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
250 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
251 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
252 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
254 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
256 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
257 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
263 } else if (!TM.Options.UseSoftFloat) {
264 // We have an algorithm for SSE2->double, and we turn this into a
265 // 64-bit FILD followed by conditional FADD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
267 // We have an algorithm for SSE2, and we turn this into a 64-bit
268 // FILD for other targets.
269 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
272 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
274 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
277 if (!TM.Options.UseSoftFloat) {
278 // SSE has no i16 to fp conversion, only i32
279 if (X86ScalarSSEf32) {
280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
281 // f32 and f64 cases are Legal, f80 case is not
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
292 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
293 // are Legal, f80 is custom lowered.
294 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
295 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
297 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
299 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
302 if (X86ScalarSSEf32) {
303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
304 // f32 and f64 cases are Legal, f80 case is not
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
307 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
308 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
311 // Handle FP_TO_UINT by promoting the destination to a larger signed
313 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
314 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
320 } else if (!TM.Options.UseSoftFloat) {
321 // Since AVX is a superset of SSE3, only check for SSE here.
322 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
323 // Expand FP_TO_UINT into a select.
324 // FIXME: We would like to use a Custom expander here eventually to do
325 // the optimal thing for SSE vs. the default expansion in the legalizer.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
328 // With SSE3 we can use fisttpll to convert to a signed i64; without
329 // SSE, we're stuck with a fistpll.
330 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
333 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
334 if (!X86ScalarSSEf64) {
335 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
336 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
339 // Without SSE, i64->f64 goes through memory.
340 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
344 // Scalar integer divide and remainder are lowered to use operations that
345 // produce two results, to match the available instructions. This exposes
346 // the two-result form to trivial CSE, which is able to combine x/y and x%y
347 // into a single instruction.
349 // Scalar integer multiply-high is also lowered to use two-result
350 // operations, to match the available instructions. However, plain multiply
351 // (low) operations are left as Legal, as there are single-result
352 // instructions for this in x86. Using the two-result multiply instructions
353 // when both high and low results are needed must be arranged by dagcombine.
354 for (unsigned i = 0, e = 4; i != e; ++i) {
356 setOperationAction(ISD::MULHS, VT, Expand);
357 setOperationAction(ISD::MULHU, VT, Expand);
358 setOperationAction(ISD::SDIV, VT, Expand);
359 setOperationAction(ISD::UDIV, VT, Expand);
360 setOperationAction(ISD::SREM, VT, Expand);
361 setOperationAction(ISD::UREM, VT, Expand);
363 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
364 setOperationAction(ISD::ADDC, VT, Custom);
365 setOperationAction(ISD::ADDE, VT, Custom);
366 setOperationAction(ISD::SUBC, VT, Custom);
367 setOperationAction(ISD::SUBE, VT, Custom);
370 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
371 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
372 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
373 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
374 if (Subtarget->is64Bit())
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
379 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f32 , Expand);
381 setOperationAction(ISD::FREM , MVT::f64 , Expand);
382 setOperationAction(ISD::FREM , MVT::f80 , Expand);
383 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
385 // Promote the i8 variants and force them on up to i32 which has a shorter
387 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
388 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
390 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
391 if (Subtarget->hasBMI()) {
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
393 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
397 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
398 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
399 if (Subtarget->is64Bit())
400 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
403 if (Subtarget->hasLZCNT()) {
404 // When promoting the i8 variants, force them to i32 for a shorter
406 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
407 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
409 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
412 if (Subtarget->is64Bit())
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
417 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
421 if (Subtarget->is64Bit()) {
422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
427 if (Subtarget->hasPOPCNT()) {
428 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
430 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
432 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
433 if (Subtarget->is64Bit())
434 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
437 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
438 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
440 // These should be promoted to a larger select which is supported.
441 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
442 // X86 wants to expand cmov itself.
443 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
445 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
448 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
455 if (Subtarget->is64Bit()) {
456 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
459 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
462 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
463 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
464 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
465 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
468 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
470 if (Subtarget->is64Bit()) {
471 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
472 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
473 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
474 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
475 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
478 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
481 if (Subtarget->is64Bit()) {
482 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
483 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
484 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
487 if (Subtarget->hasSSE1())
488 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
490 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
491 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
493 // On X86 and X86-64, atomic operations are lowered to locked instructions.
494 // Locked instructions, in turn, have implicit fence semantics (all memory
495 // operations are flushed before issuing the locked instruction, and they
496 // are not buffered), so we can fold away the common pattern of
497 // fence-atomic-fence.
498 setShouldFoldAtomicFences(true);
500 // Expand certain atomics
501 for (unsigned i = 0, e = 4; i != e; ++i) {
503 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
505 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
508 if (!Subtarget->is64Bit()) {
509 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
513 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
514 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
515 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
516 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
519 if (Subtarget->hasCmpxchg16b()) {
520 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
523 // FIXME - use subtarget debug flags
524 if (!Subtarget->isTargetDarwin() &&
525 !Subtarget->isTargetELF() &&
526 !Subtarget->isTargetCygMing()) {
527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
530 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
531 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
532 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
533 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
534 if (Subtarget->is64Bit()) {
535 setExceptionPointerRegister(X86::RAX);
536 setExceptionSelectorRegister(X86::RDX);
538 setExceptionPointerRegister(X86::EAX);
539 setExceptionSelectorRegister(X86::EDX);
541 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
542 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
544 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
545 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
547 setOperationAction(ISD::TRAP, MVT::Other, Legal);
549 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
550 setOperationAction(ISD::VASTART , MVT::Other, Custom);
551 setOperationAction(ISD::VAEND , MVT::Other, Expand);
552 if (Subtarget->is64Bit()) {
553 setOperationAction(ISD::VAARG , MVT::Other, Custom);
554 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
556 setOperationAction(ISD::VAARG , MVT::Other, Expand);
557 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
560 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
561 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
563 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Custom);
566 else if (TM.Options.EnableSegmentedStacks)
567 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
568 MVT::i64 : MVT::i32, Custom);
570 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
571 MVT::i64 : MVT::i32, Expand);
573 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
574 // f32 and f64 use SSE.
575 // Set up the FP register classes.
576 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
577 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
579 // Use ANDPD to simulate FABS.
580 setOperationAction(ISD::FABS , MVT::f64, Custom);
581 setOperationAction(ISD::FABS , MVT::f32, Custom);
583 // Use XORP to simulate FNEG.
584 setOperationAction(ISD::FNEG , MVT::f64, Custom);
585 setOperationAction(ISD::FNEG , MVT::f32, Custom);
587 // Use ANDPD and ORPD to simulate FCOPYSIGN.
588 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
589 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
591 // Lower this to FGETSIGNx86 plus an AND.
592 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
593 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
595 // We don't support sin/cos/fmod
596 setOperationAction(ISD::FSIN , MVT::f64, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 // Expand FP immediates into loads from the stack, except for the special
603 addLegalFPImmediate(APFloat(+0.0)); // xorpd
604 addLegalFPImmediate(APFloat(+0.0f)); // xorps
605 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
606 // Use SSE for f32, x87 for f64.
607 // Set up the FP register classes.
608 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
609 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
611 // Use ANDPS to simulate FABS.
612 setOperationAction(ISD::FABS , MVT::f32, Custom);
614 // Use XORP to simulate FNEG.
615 setOperationAction(ISD::FNEG , MVT::f32, Custom);
617 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
619 // Use ANDPS and ORPS to simulate FCOPYSIGN.
620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
623 // We don't support sin/cos/fmod
624 setOperationAction(ISD::FSIN , MVT::f32, Expand);
625 setOperationAction(ISD::FCOS , MVT::f32, Expand);
627 // Special cases we handle for FP constants.
628 addLegalFPImmediate(APFloat(+0.0f)); // xorps
629 addLegalFPImmediate(APFloat(+0.0)); // FLD0
630 addLegalFPImmediate(APFloat(+1.0)); // FLD1
631 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
632 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
634 if (!TM.Options.UnsafeFPMath) {
635 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
636 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
638 } else if (!TM.Options.UseSoftFloat) {
639 // f32 and f64 in x87.
640 // Set up the FP register classes.
641 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
642 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
644 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
645 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
649 if (!TM.Options.UnsafeFPMath) {
650 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
651 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
653 addLegalFPImmediate(APFloat(+0.0)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
657 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
658 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
659 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
660 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
663 // We don't support FMA.
664 setOperationAction(ISD::FMA, MVT::f64, Expand);
665 setOperationAction(ISD::FMA, MVT::f32, Expand);
667 // Long double always uses X87.
668 if (!TM.Options.UseSoftFloat) {
669 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
670 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
673 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
674 addLegalFPImmediate(TmpFlt); // FLD0
676 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
679 APFloat TmpFlt2(+1.0);
680 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
682 addLegalFPImmediate(TmpFlt2); // FLD1
683 TmpFlt2.changeSign();
684 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
687 if (!TM.Options.UnsafeFPMath) {
688 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
689 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
692 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
693 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
694 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
695 setOperationAction(ISD::FRINT, MVT::f80, Expand);
696 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
697 setOperationAction(ISD::FMA, MVT::f80, Expand);
700 // Always use a library call for pow.
701 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
702 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
703 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
705 setOperationAction(ISD::FLOG, MVT::f80, Expand);
706 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
707 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
708 setOperationAction(ISD::FEXP, MVT::f80, Expand);
709 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
711 // First set operation action for all vector types to either promote
712 // (for widening) or expand (for scalarization). Then we will selectively
713 // turn on ones that can be effectively codegen'd.
714 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
715 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
716 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
731 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
733 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
734 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
768 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
770 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
771 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
772 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
773 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
774 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
775 setTruncStoreAction((MVT::SimpleValueType)VT,
776 (MVT::SimpleValueType)InnerVT, Expand);
777 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
778 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
782 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
783 // with -msoft-float, disable use of MMX as well.
784 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
785 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
786 // No operations on x86mmx supported, everything uses intrinsics.
789 // MMX-sized vectors (other than x86mmx) are expected to be expanded
790 // into smaller operations.
791 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
792 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
793 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
794 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
795 setOperationAction(ISD::AND, MVT::v8i8, Expand);
796 setOperationAction(ISD::AND, MVT::v4i16, Expand);
797 setOperationAction(ISD::AND, MVT::v2i32, Expand);
798 setOperationAction(ISD::AND, MVT::v1i64, Expand);
799 setOperationAction(ISD::OR, MVT::v8i8, Expand);
800 setOperationAction(ISD::OR, MVT::v4i16, Expand);
801 setOperationAction(ISD::OR, MVT::v2i32, Expand);
802 setOperationAction(ISD::OR, MVT::v1i64, Expand);
803 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
804 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
805 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
806 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
808 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
809 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
810 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
811 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
812 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
813 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
814 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
815 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
817 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
818 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
819 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
821 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
822 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
824 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
826 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
827 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
828 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
829 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
830 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
831 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
832 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
833 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
834 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
835 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
838 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
839 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
841 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
842 // registers cannot be used even for integer operations.
843 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
844 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
845 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
846 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
848 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
849 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
850 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
851 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
853 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
854 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
855 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
856 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
857 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
858 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
859 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
860 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
861 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
862 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
863 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
865 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
866 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
867 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
868 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
870 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
871 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
872 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
877 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
878 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
879 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
880 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
882 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
883 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
884 EVT VT = (MVT::SimpleValueType)i;
885 // Do not attempt to custom lower non-power-of-2 vectors
886 if (!isPowerOf2_32(VT.getVectorNumElements()))
888 // Do not attempt to custom lower non-128-bit vectors
889 if (!VT.is128BitVector())
891 setOperationAction(ISD::BUILD_VECTOR,
892 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::VECTOR_SHUFFLE,
894 VT.getSimpleVT().SimpleTy, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
896 VT.getSimpleVT().SimpleTy, Custom);
899 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
900 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
901 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
902 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
906 if (Subtarget->is64Bit()) {
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
911 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
912 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
913 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
916 // Do not attempt to promote non-128-bit vectors
917 if (!VT.is128BitVector())
920 setOperationAction(ISD::AND, SVT, Promote);
921 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
922 setOperationAction(ISD::OR, SVT, Promote);
923 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
924 setOperationAction(ISD::XOR, SVT, Promote);
925 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
926 setOperationAction(ISD::LOAD, SVT, Promote);
927 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
928 setOperationAction(ISD::SELECT, SVT, Promote);
929 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
932 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
934 // Custom lower v2i64 and v2f64 selects.
935 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
936 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
937 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
938 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
940 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
941 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
944 if (Subtarget->hasSSE41()) {
945 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
948 setOperationAction(ISD::FRINT, MVT::f32, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
950 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
951 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
952 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
953 setOperationAction(ISD::FRINT, MVT::f64, Legal);
954 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
956 // FIXME: Do we need to handle scalar-to-vector here?
957 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
959 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
960 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
961 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
962 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
963 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
965 // i8 and i16 vectors are custom , because the source register and source
966 // source memory operand types are not the same width. f32 vectors are
967 // custom since the immediate controlling the insert encodes additional
969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
974 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
979 // FIXME: these should be Legal but thats only for the case where
980 // the index is constant. For now custom expand to deal with that.
981 if (Subtarget->is64Bit()) {
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
987 if (Subtarget->hasSSE2()) {
988 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
991 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
992 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
994 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
995 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
997 if (Subtarget->hasAVX2()) {
998 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
999 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1002 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1004 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1006 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1007 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1009 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1010 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1016 if (Subtarget->hasSSE42())
1017 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1019 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1020 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1021 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1022 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1023 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1024 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1025 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1027 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1028 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1031 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1038 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1039 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1040 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1041 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1042 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1043 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1045 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1046 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1047 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1051 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1052 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1053 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1054 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1060 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1062 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1063 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1065 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1066 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1067 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1068 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1070 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1071 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1072 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1074 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1075 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1076 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1077 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1079 if (Subtarget->hasAVX2()) {
1080 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1081 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1082 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1083 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1085 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1087 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1088 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1090 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1091 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1092 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1093 // Don't lower v32i8 because there is no 128-bit byte mul
1095 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1097 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1098 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1100 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1101 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1103 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1105 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1106 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1107 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1108 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1112 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1115 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1118 // Don't lower v32i8 because there is no 128-bit byte mul
1120 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1123 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1124 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1129 // Custom lower several nodes for 256-bit types.
1130 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1131 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1132 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1135 // Extract subvector is special because the value type
1136 // (result) is 128-bit but the source is 256-bit wide.
1137 if (VT.is128BitVector())
1138 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1140 // Do not attempt to custom lower other non-256-bit vectors
1141 if (!VT.is256BitVector())
1144 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1145 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1147 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1148 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1149 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1152 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1153 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1154 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1157 // Do not attempt to promote non-256-bit vectors
1158 if (!VT.is256BitVector())
1161 setOperationAction(ISD::AND, SVT, Promote);
1162 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1163 setOperationAction(ISD::OR, SVT, Promote);
1164 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1165 setOperationAction(ISD::XOR, SVT, Promote);
1166 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1167 setOperationAction(ISD::LOAD, SVT, Promote);
1168 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1169 setOperationAction(ISD::SELECT, SVT, Promote);
1170 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1174 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1175 // of this type with custom code.
1176 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1177 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1178 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1182 // We want to custom lower some of our intrinsics.
1183 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1186 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1187 // handle type legalization for these operations here.
1189 // FIXME: We really should do custom legalization for addition and
1190 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1191 // than generic legalization for 64-bit multiplication-with-overflow, though.
1192 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1193 // Add/Sub/Mul with overflow operations are custom lowered.
1195 setOperationAction(ISD::SADDO, VT, Custom);
1196 setOperationAction(ISD::UADDO, VT, Custom);
1197 setOperationAction(ISD::SSUBO, VT, Custom);
1198 setOperationAction(ISD::USUBO, VT, Custom);
1199 setOperationAction(ISD::SMULO, VT, Custom);
1200 setOperationAction(ISD::UMULO, VT, Custom);
1203 // There are no 8-bit 3-address imul/mul instructions
1204 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1205 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1207 if (!Subtarget->is64Bit()) {
1208 // These libcalls are not available in 32-bit.
1209 setLibcallName(RTLIB::SHL_I128, 0);
1210 setLibcallName(RTLIB::SRL_I128, 0);
1211 setLibcallName(RTLIB::SRA_I128, 0);
1214 // We have target-specific dag combine patterns for the following nodes:
1215 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1216 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1217 setTargetDAGCombine(ISD::VSELECT);
1218 setTargetDAGCombine(ISD::SELECT);
1219 setTargetDAGCombine(ISD::SHL);
1220 setTargetDAGCombine(ISD::SRA);
1221 setTargetDAGCombine(ISD::SRL);
1222 setTargetDAGCombine(ISD::OR);
1223 setTargetDAGCombine(ISD::AND);
1224 setTargetDAGCombine(ISD::ADD);
1225 setTargetDAGCombine(ISD::FADD);
1226 setTargetDAGCombine(ISD::FSUB);
1227 setTargetDAGCombine(ISD::SUB);
1228 setTargetDAGCombine(ISD::LOAD);
1229 setTargetDAGCombine(ISD::STORE);
1230 setTargetDAGCombine(ISD::ZERO_EXTEND);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 if (Subtarget->is64Bit())
1233 setTargetDAGCombine(ISD::MUL);
1234 if (Subtarget->hasBMI())
1235 setTargetDAGCombine(ISD::XOR);
1237 computeRegisterProperties();
1239 // On Darwin, -Os means optimize for size without hurting performance,
1240 // do not reduce the limit.
1241 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1242 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1243 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1244 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1245 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1246 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1247 setPrefLoopAlignment(4); // 2^4 bytes.
1248 benefitFromCodePlacementOpt = true;
1250 setPrefFunctionAlignment(4); // 2^4 bytes.
1254 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1255 if (!VT.isVector()) return MVT::i8;
1256 return VT.changeVectorElementTypeToInteger();
1260 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1261 /// the desired ByVal argument alignment.
1262 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1265 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1266 if (VTy->getBitWidth() == 128)
1268 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(ATy->getElementType(), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1273 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1274 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1275 unsigned EltAlign = 0;
1276 getMaxByValAlign(STy->getElementType(i), EltAlign);
1277 if (EltAlign > MaxAlign)
1278 MaxAlign = EltAlign;
1286 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1287 /// function arguments in the caller parameter area. For X86, aggregates
1288 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1289 /// are at 4-byte boundaries.
1290 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1291 if (Subtarget->is64Bit()) {
1292 // Max of 8 and alignment of type.
1293 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1300 if (Subtarget->hasSSE1())
1301 getMaxByValAlign(Ty, Align);
1305 /// getOptimalMemOpType - Returns the target specific optimal type for load
1306 /// and store operations as a result of memset, memcpy, and memmove
1307 /// lowering. If DstAlign is zero that means it's safe to destination
1308 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1309 /// means there isn't a need to check it against alignment requirement,
1310 /// probably because the source does not need to be loaded. If
1311 /// 'IsZeroVal' is true, that means it's safe to return a
1312 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1313 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1314 /// constant so it does not need to be loaded.
1315 /// It returns EVT::Other if the type should be determined using generic
1316 /// target-independent logic.
1318 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1319 unsigned DstAlign, unsigned SrcAlign,
1322 MachineFunction &MF) const {
1323 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1324 // linux. This is because the stack realignment code can't handle certain
1325 // cases like PR2962. This should be removed when PR2962 is fixed.
1326 const Function *F = MF.getFunction();
1328 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1330 (Subtarget->isUnalignedMemAccessFast() ||
1331 ((DstAlign == 0 || DstAlign >= 16) &&
1332 (SrcAlign == 0 || SrcAlign >= 16))) &&
1333 Subtarget->getStackAlignment() >= 16) {
1334 if (Subtarget->getStackAlignment() >= 32) {
1335 if (Subtarget->hasAVX2())
1337 if (Subtarget->hasAVX())
1340 if (Subtarget->hasSSE2())
1342 if (Subtarget->hasSSE1())
1344 } else if (!MemcpyStrSrc && Size >= 8 &&
1345 !Subtarget->is64Bit() &&
1346 Subtarget->getStackAlignment() >= 8 &&
1347 Subtarget->hasSSE2()) {
1348 // Do not use f64 to lower memcpy if source is string constant. It's
1349 // better to use i32 to avoid the loads.
1353 if (Subtarget->is64Bit() && Size >= 8)
1358 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1359 /// current function. The returned value is a member of the
1360 /// MachineJumpTableInfo::JTEntryKind enum.
1361 unsigned X86TargetLowering::getJumpTableEncoding() const {
1362 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1364 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1365 Subtarget->isPICStyleGOT())
1366 return MachineJumpTableInfo::EK_Custom32;
1368 // Otherwise, use the normal jump table encoding heuristics.
1369 return TargetLowering::getJumpTableEncoding();
1373 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1374 const MachineBasicBlock *MBB,
1375 unsigned uid,MCContext &Ctx) const{
1376 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1377 Subtarget->isPICStyleGOT());
1378 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1380 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1381 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1384 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1386 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1387 SelectionDAG &DAG) const {
1388 if (!Subtarget->is64Bit())
1389 // This doesn't have DebugLoc associated with it, but is not really the
1390 // same as a Register.
1391 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1395 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1396 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1398 const MCExpr *X86TargetLowering::
1399 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1400 MCContext &Ctx) const {
1401 // X86-64 uses RIP relative addressing based on the jump table label.
1402 if (Subtarget->isPICStyleRIPRel())
1403 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1405 // Otherwise, the reference is relative to the PIC base.
1406 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1409 // FIXME: Why this routine is here? Move to RegInfo!
1410 std::pair<const TargetRegisterClass*, uint8_t>
1411 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1412 const TargetRegisterClass *RRC = 0;
1414 switch (VT.getSimpleVT().SimpleTy) {
1416 return TargetLowering::findRepresentativeClass(VT);
1417 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1418 RRC = (Subtarget->is64Bit()
1419 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1422 RRC = X86::VR64RegisterClass;
1424 case MVT::f32: case MVT::f64:
1425 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1426 case MVT::v4f32: case MVT::v2f64:
1427 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1429 RRC = X86::VR128RegisterClass;
1432 return std::make_pair(RRC, Cost);
1435 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1436 unsigned &Offset) const {
1437 if (!Subtarget->isTargetLinux())
1440 if (Subtarget->is64Bit()) {
1441 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1443 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1456 //===----------------------------------------------------------------------===//
1457 // Return Value Calling Convention Implementation
1458 //===----------------------------------------------------------------------===//
1460 #include "X86GenCallingConv.inc"
1463 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1464 MachineFunction &MF, bool isVarArg,
1465 const SmallVectorImpl<ISD::OutputArg> &Outs,
1466 LLVMContext &Context) const {
1467 SmallVector<CCValAssign, 16> RVLocs;
1468 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1470 return CCInfo.CheckReturn(Outs, RetCC_X86);
1474 X86TargetLowering::LowerReturn(SDValue Chain,
1475 CallingConv::ID CallConv, bool isVarArg,
1476 const SmallVectorImpl<ISD::OutputArg> &Outs,
1477 const SmallVectorImpl<SDValue> &OutVals,
1478 DebugLoc dl, SelectionDAG &DAG) const {
1479 MachineFunction &MF = DAG.getMachineFunction();
1480 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1482 SmallVector<CCValAssign, 16> RVLocs;
1483 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1484 RVLocs, *DAG.getContext());
1485 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1487 // Add the regs to the liveout set for the function.
1488 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1489 for (unsigned i = 0; i != RVLocs.size(); ++i)
1490 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1491 MRI.addLiveOut(RVLocs[i].getLocReg());
1495 SmallVector<SDValue, 6> RetOps;
1496 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1497 // Operand #1 = Bytes To Pop
1498 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1501 // Copy the result values into the output registers.
1502 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1503 CCValAssign &VA = RVLocs[i];
1504 assert(VA.isRegLoc() && "Can only return in registers!");
1505 SDValue ValToCopy = OutVals[i];
1506 EVT ValVT = ValToCopy.getValueType();
1508 // If this is x86-64, and we disabled SSE, we can't return FP values,
1509 // or SSE or MMX vectors.
1510 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1511 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1512 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1513 report_fatal_error("SSE register return with SSE disabled");
1515 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1516 // llvm-gcc has never done it right and no one has noticed, so this
1517 // should be OK for now.
1518 if (ValVT == MVT::f64 &&
1519 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1520 report_fatal_error("SSE2 register return with SSE2 disabled");
1522 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1523 // the RET instruction and handled by the FP Stackifier.
1524 if (VA.getLocReg() == X86::ST0 ||
1525 VA.getLocReg() == X86::ST1) {
1526 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1527 // change the value to the FP stack register class.
1528 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1529 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1530 RetOps.push_back(ValToCopy);
1531 // Don't emit a copytoreg.
1535 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1536 // which is returned in RAX / RDX.
1537 if (Subtarget->is64Bit()) {
1538 if (ValVT == MVT::x86mmx) {
1539 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1540 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1541 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1543 // If we don't have SSE2 available, convert to v4f32 so the generated
1544 // register is legal.
1545 if (!Subtarget->hasSSE2())
1546 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1551 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1552 Flag = Chain.getValue(1);
1555 // The x86-64 ABI for returning structs by value requires that we copy
1556 // the sret argument into %rax for the return. We saved the argument into
1557 // a virtual register in the entry block, so now we copy the value out
1559 if (Subtarget->is64Bit() &&
1560 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1561 MachineFunction &MF = DAG.getMachineFunction();
1562 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1563 unsigned Reg = FuncInfo->getSRetReturnReg();
1565 "SRetReturnReg should have been set in LowerFormalArguments().");
1566 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1568 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1569 Flag = Chain.getValue(1);
1571 // RAX now acts like a return value.
1572 MRI.addLiveOut(X86::RAX);
1575 RetOps[0] = Chain; // Update chain.
1577 // Add the flag if we have it.
1579 RetOps.push_back(Flag);
1581 return DAG.getNode(X86ISD::RET_FLAG, dl,
1582 MVT::Other, &RetOps[0], RetOps.size());
1585 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1586 if (N->getNumValues() != 1)
1588 if (!N->hasNUsesOfValue(1, 0))
1591 SDNode *Copy = *N->use_begin();
1592 if (Copy->getOpcode() != ISD::CopyToReg &&
1593 Copy->getOpcode() != ISD::FP_EXTEND)
1596 bool HasRet = false;
1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1599 if (UI->getOpcode() != X86ISD::RET_FLAG)
1608 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1609 ISD::NodeType ExtendKind) const {
1611 // TODO: Is this also valid on 32-bit?
1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1613 ReturnMVT = MVT::i8;
1615 ReturnMVT = MVT::i32;
1617 EVT MinVT = getRegisterType(Context, ReturnMVT);
1618 return VT.bitsLT(MinVT) ? MinVT : VT;
1621 /// LowerCallResult - Lower the result values of a call into the
1622 /// appropriate copies out of appropriate physical registers.
1625 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1626 CallingConv::ID CallConv, bool isVarArg,
1627 const SmallVectorImpl<ISD::InputArg> &Ins,
1628 DebugLoc dl, SelectionDAG &DAG,
1629 SmallVectorImpl<SDValue> &InVals) const {
1631 // Assign locations to each value returned by this call.
1632 SmallVector<CCValAssign, 16> RVLocs;
1633 bool Is64Bit = Subtarget->is64Bit();
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1635 getTargetMachine(), RVLocs, *DAG.getContext());
1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1638 // Copy all of the result registers out of their specified physreg.
1639 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1640 CCValAssign &VA = RVLocs[i];
1641 EVT CopyVT = VA.getValVT();
1643 // If this is x86-64, and we disabled SSE, we can't return FP values
1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1646 report_fatal_error("SSE register return with SSE disabled");
1651 // If this is a call to a function that returns an fp value on the floating
1652 // point stack, we must guarantee the the value is popped from the stack, so
1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1654 // if the return value is not used. We use the FpPOP_RETVAL instruction
1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1657 // If we prefer to use the value in xmm registers, copy it out as f80 and
1658 // use a truncate to move it from fp stack reg to xmm reg.
1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1660 SDValue Ops[] = { Chain, InFlag };
1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1662 MVT::Other, MVT::Glue, Ops, 2), 1);
1663 Val = Chain.getValue(0);
1665 // Round the f80 to the right size, which also moves it to the appropriate
1667 if (CopyVT != VA.getValVT())
1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1669 // This truncation won't change the value.
1670 DAG.getIntPtrConstant(1));
1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1673 CopyVT, InFlag).getValue(1);
1674 Val = Chain.getValue(0);
1676 InFlag = Chain.getValue(2);
1677 InVals.push_back(Val);
1684 //===----------------------------------------------------------------------===//
1685 // C & StdCall & Fast Calling Convention implementation
1686 //===----------------------------------------------------------------------===//
1687 // StdCall calling convention seems to be standard for many Windows' API
1688 // routines and around. It differs from C calling convention just a little:
1689 // callee should clean up the stack, not caller. Symbols should be also
1690 // decorated in some fancy way :) It doesn't support any vector arguments.
1691 // For info on fast calling convention see Fast Calling Convention (tail call)
1692 // implementation LowerX86_32FastCCCallTo.
1694 /// CallIsStructReturn - Determines whether a call uses struct return
1696 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1700 return Outs[0].Flags.isSRet();
1703 /// ArgsAreStructReturn - Determines whether a function uses struct
1704 /// return semantics.
1706 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1710 return Ins[0].Flags.isSRet();
1713 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1714 /// by "Src" to address "Dst" with size and alignment information specified by
1715 /// the specific parameter attribute. The copy will be passed as a byval
1716 /// function parameter.
1718 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1724 /*isVolatile*/false, /*AlwaysInline=*/true,
1725 MachinePointerInfo(), MachinePointerInfo());
1728 /// IsTailCallConvention - Return true if the calling convention is one that
1729 /// supports tail call optimization.
1730 static bool IsTailCallConvention(CallingConv::ID CC) {
1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1734 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1739 CallingConv::ID CalleeCC = CS.getCallingConv();
1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1746 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1747 /// a tailcall target by changing its ABI.
1748 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1749 bool GuaranteedTailCallOpt) {
1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1754 X86TargetLowering::LowerMemArgument(SDValue Chain,
1755 CallingConv::ID CallConv,
1756 const SmallVectorImpl<ISD::InputArg> &Ins,
1757 DebugLoc dl, SelectionDAG &DAG,
1758 const CCValAssign &VA,
1759 MachineFrameInfo *MFI,
1761 // Create the nodes corresponding to a load from this parameter slot.
1762 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1764 getTargetMachine().Options.GuaranteedTailCallOpt);
1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1768 // If value is passed by pointer we have address passed instead of the value
1770 if (VA.getLocInfo() == CCValAssign::Indirect)
1771 ValVT = VA.getLocVT();
1773 ValVT = VA.getValVT();
1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1776 // changed with more analysis.
1777 // In case of tail call optimization mark all arguments mutable. Since they
1778 // could be overwritten by lowering of arguments in case of a tail call.
1779 if (Flags.isByVal()) {
1780 unsigned Bytes = Flags.getByValSize();
1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1783 return DAG.getFrameIndex(FI, getPointerTy());
1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1786 VA.getLocMemOffset(), isImmutable);
1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1788 return DAG.getLoad(ValVT, dl, Chain, FIN,
1789 MachinePointerInfo::getFixedStack(FI),
1790 false, false, false, 0);
1795 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1796 CallingConv::ID CallConv,
1798 const SmallVectorImpl<ISD::InputArg> &Ins,
1801 SmallVectorImpl<SDValue> &InVals)
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 const Function* Fn = MF.getFunction();
1807 if (Fn->hasExternalLinkage() &&
1808 Subtarget->isTargetCygMing() &&
1809 Fn->getName() == "main")
1810 FuncInfo->setForceFramePointer(true);
1812 MachineFrameInfo *MFI = MF.getFrameInfo();
1813 bool Is64Bit = Subtarget->is64Bit();
1814 bool IsWindows = Subtarget->isTargetWindows();
1815 bool IsWin64 = Subtarget->isTargetWin64();
1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1818 "Var args not supported with calling convention fastcc or ghc");
1820 // Assign locations to all of the incoming arguments.
1821 SmallVector<CCValAssign, 16> ArgLocs;
1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1823 ArgLocs, *DAG.getContext());
1825 // Allocate shadow area for Win64
1827 CCInfo.AllocateStack(32, 8);
1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1832 unsigned LastVal = ~0U;
1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1835 CCValAssign &VA = ArgLocs[i];
1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1838 assert(VA.getValNo() != LastVal &&
1839 "Don't support value assigned to multiple locs yet");
1841 LastVal = VA.getValNo();
1843 if (VA.isRegLoc()) {
1844 EVT RegVT = VA.getLocVT();
1845 TargetRegisterClass *RC = NULL;
1846 if (RegVT == MVT::i32)
1847 RC = X86::GR32RegisterClass;
1848 else if (Is64Bit && RegVT == MVT::i64)
1849 RC = X86::GR64RegisterClass;
1850 else if (RegVT == MVT::f32)
1851 RC = X86::FR32RegisterClass;
1852 else if (RegVT == MVT::f64)
1853 RC = X86::FR64RegisterClass;
1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1855 RC = X86::VR256RegisterClass;
1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1857 RC = X86::VR128RegisterClass;
1858 else if (RegVT == MVT::x86mmx)
1859 RC = X86::VR64RegisterClass;
1861 llvm_unreachable("Unknown argument type!");
1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1869 if (VA.getLocInfo() == CCValAssign::SExt)
1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1871 DAG.getValueType(VA.getValVT()));
1872 else if (VA.getLocInfo() == CCValAssign::ZExt)
1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1874 DAG.getValueType(VA.getValVT()));
1875 else if (VA.getLocInfo() == CCValAssign::BCvt)
1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1878 if (VA.isExtInLoc()) {
1879 // Handle MMX values passed in XMM regs.
1880 if (RegVT.isVector()) {
1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1887 assert(VA.isMemLoc());
1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1891 // If value is passed via pointer - do a load.
1892 if (VA.getLocInfo() == CCValAssign::Indirect)
1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1894 MachinePointerInfo(), false, false, false, 0);
1896 InVals.push_back(ArgValue);
1899 // The x86-64 ABI for returning structs by value requires that we copy
1900 // the sret argument into %rax for the return. Save the argument into
1901 // a virtual register so that we can access it from the return points.
1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1904 unsigned Reg = FuncInfo->getSRetReturnReg();
1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1907 FuncInfo->setSRetReturnReg(Reg);
1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1913 unsigned StackSize = CCInfo.getNextStackOffset();
1914 // Align stack specially for tail calls.
1915 if (FuncIsMadeTailCallSafe(CallConv,
1916 MF.getTarget().Options.GuaranteedTailCallOpt))
1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1919 // If the function takes variable number of arguments, make a frame index for
1920 // the start of the first vararg value... for expansion of llvm.va_start.
1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1923 CallConv != CallingConv::X86_ThisCall)) {
1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1929 // FIXME: We should really autogenerate these arrays
1930 static const unsigned GPR64ArgRegsWin64[] = {
1931 X86::RCX, X86::RDX, X86::R8, X86::R9
1933 static const unsigned GPR64ArgRegs64Bit[] = {
1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1936 static const unsigned XMMArgRegs64Bit[] = {
1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1940 const unsigned *GPR64ArgRegs;
1941 unsigned NumXMMRegs = 0;
1944 // The XMM registers which might contain var arg parameters are shadowed
1945 // in their paired GPR. So we only need to save the GPR to their home
1947 TotalNumIntRegs = 4;
1948 GPR64ArgRegs = GPR64ArgRegsWin64;
1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1951 GPR64ArgRegs = GPR64ArgRegs64Bit;
1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1961 "SSE register cannot be used when SSE is disabled!");
1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1963 NoImplicitFloatOps) &&
1964 "SSE register cannot be used when SSE is disabled!");
1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1966 !Subtarget->hasSSE1())
1967 // Kernel mode asks for SSE to be disabled, so don't push them
1969 TotalNumXMMRegs = 0;
1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1973 // Get to the caller-allocated home save location. Add 8 to account
1974 // for the return address.
1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1976 FuncInfo->setRegSaveFrameIndex(
1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1978 // Fixup to set vararg frame on shadow area (4 x i64).
1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1982 // For X86-64, if there are vararg parameters that are passed via
1983 // registers, then we must store them to their spots on the stack so
1984 // they may be loaded by deferencing the result of va_next.
1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1987 FuncInfo->setRegSaveFrameIndex(
1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1992 // Store the integer parameter registers.
1993 SmallVector<SDValue, 8> MemOps;
1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1996 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1999 DAG.getIntPtrConstant(Offset));
2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2001 X86::GR64RegisterClass);
2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2004 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2005 MachinePointerInfo::getFixedStack(
2006 FuncInfo->getRegSaveFrameIndex(), Offset),
2008 MemOps.push_back(Store);
2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2013 // Now store the XMM (fp + vector) parameter registers.
2014 SmallVector<SDValue, 11> SaveXMMOps;
2015 SaveXMMOps.push_back(Chain);
2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2019 SaveXMMOps.push_back(ALVal);
2021 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2022 FuncInfo->getRegSaveFrameIndex()));
2023 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2024 FuncInfo->getVarArgsFPOffset()));
2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2028 X86::VR128RegisterClass);
2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2030 SaveXMMOps.push_back(Val);
2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2034 &SaveXMMOps[0], SaveXMMOps.size()));
2037 if (!MemOps.empty())
2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2039 &MemOps[0], MemOps.size());
2043 // Some CCs need callee pop.
2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2045 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2049 // If this is an sret function, the return should pop the hidden pointer.
2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2051 ArgsAreStructReturn(Ins))
2052 FuncInfo->setBytesToPopOnReturn(4);
2056 // RegSaveFrameIndex is X86-64 only.
2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2058 if (CallConv == CallingConv::X86_FastCall ||
2059 CallConv == CallingConv::X86_ThisCall)
2060 // fastcc functions can't have varargs.
2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2064 FuncInfo->setArgumentStackSize(StackSize);
2070 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2071 SDValue StackPtr, SDValue Arg,
2072 DebugLoc dl, SelectionDAG &DAG,
2073 const CCValAssign &VA,
2074 ISD::ArgFlagsTy Flags) const {
2075 unsigned LocMemOffset = VA.getLocMemOffset();
2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2078 if (Flags.isByVal())
2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2081 return DAG.getStore(Chain, dl, Arg, PtrOff,
2082 MachinePointerInfo::getStack(LocMemOffset),
2086 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2087 /// optimization is performed and it is required.
2089 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2090 SDValue &OutRetAddr, SDValue Chain,
2091 bool IsTailCall, bool Is64Bit,
2092 int FPDiff, DebugLoc dl) const {
2093 // Adjust the Return address stack slot.
2094 EVT VT = getPointerTy();
2095 OutRetAddr = getReturnAddressFrameIndex(DAG);
2097 // Load the "old" Return address.
2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2099 false, false, false, 0);
2100 return SDValue(OutRetAddr.getNode(), 1);
2103 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2104 /// optimization is performed and it is required (FPDiff!=0).
2106 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2107 SDValue Chain, SDValue RetAddrFrIdx,
2108 bool Is64Bit, int FPDiff, DebugLoc dl) {
2109 // Store the return address to the appropriate stack slot.
2110 if (!FPDiff) return Chain;
2111 // Calculate the new stack slot for the return address.
2112 int SlotSize = Is64Bit ? 8 : 4;
2113 int NewReturnAddrFI =
2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2124 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2125 CallingConv::ID CallConv, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs,
2128 const SmallVectorImpl<SDValue> &OutVals,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2130 DebugLoc dl, SelectionDAG &DAG,
2131 SmallVectorImpl<SDValue> &InVals) const {
2132 MachineFunction &MF = DAG.getMachineFunction();
2133 bool Is64Bit = Subtarget->is64Bit();
2134 bool IsWin64 = Subtarget->isTargetWin64();
2135 bool IsWindows = Subtarget->isTargetWindows();
2136 bool IsStructRet = CallIsStructReturn(Outs);
2137 bool IsSibcall = false;
2139 if (MF.getTarget().Options.DisableTailCalls)
2143 // Check if it's really possible to do a tail call.
2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2146 Outs, OutVals, Ins, DAG);
2148 // Sibcalls are automatically detected tailcalls which do not require
2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2158 "Var args not supported with calling convention fastcc or ghc");
2160 // Analyze operands of the call, assigning locations to each operand.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2163 ArgLocs, *DAG.getContext());
2165 // Allocate shadow area for Win64
2167 CCInfo.AllocateStack(32, 8);
2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2172 // Get a count of how many bytes are to be pushed on the stack.
2173 unsigned NumBytes = CCInfo.getNextStackOffset();
2175 // This is a sibcall. The memory operands are available in caller's
2176 // own caller's stack.
2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2179 IsTailCallConvention(CallConv))
2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2183 if (isTailCall && !IsSibcall) {
2184 // Lower arguments at fp - stackoffset + fpdiff.
2185 unsigned NumBytesCallerPushed =
2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2187 FPDiff = NumBytesCallerPushed - NumBytes;
2189 // Set the delta of movement of the returnaddr stackslot.
2190 // But only set if delta is greater than previous delta.
2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2198 SDValue RetAddrFrIdx;
2199 // Load return address for tail calls.
2200 if (isTailCall && FPDiff)
2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2202 Is64Bit, FPDiff, dl);
2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2205 SmallVector<SDValue, 8> MemOpChains;
2208 // Walk the register/memloc assignments, inserting copies/loads. In the case
2209 // of tail call optimization arguments are handle later.
2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2211 CCValAssign &VA = ArgLocs[i];
2212 EVT RegVT = VA.getLocVT();
2213 SDValue Arg = OutVals[i];
2214 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2215 bool isByVal = Flags.isByVal();
2217 // Promote the value if needed.
2218 switch (VA.getLocInfo()) {
2219 default: llvm_unreachable("Unknown loc info!");
2220 case CCValAssign::Full: break;
2221 case CCValAssign::SExt:
2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2224 case CCValAssign::ZExt:
2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::AExt:
2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2229 // Special case: passing MMX values in XMM registers.
2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2236 case CCValAssign::BCvt:
2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2239 case CCValAssign::Indirect: {
2240 // Store the argument.
2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2244 MachinePointerInfo::getFixedStack(FI),
2251 if (VA.isRegLoc()) {
2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2253 if (isVarArg && IsWin64) {
2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2255 // shadow reg if callee is a varargs function.
2256 unsigned ShadowReg = 0;
2257 switch (VA.getLocReg()) {
2258 case X86::XMM0: ShadowReg = X86::RCX; break;
2259 case X86::XMM1: ShadowReg = X86::RDX; break;
2260 case X86::XMM2: ShadowReg = X86::R8; break;
2261 case X86::XMM3: ShadowReg = X86::R9; break;
2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2266 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2267 assert(VA.isMemLoc());
2268 if (StackPtr.getNode() == 0)
2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2271 dl, DAG, VA, Flags));
2275 if (!MemOpChains.empty())
2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2277 &MemOpChains[0], MemOpChains.size());
2279 // Build a sequence of copy-to-reg nodes chained together with token chain
2280 // and flag operands which copy the outgoing args into registers.
2282 // Tail call byval lowering might overwrite argument registers so in case of
2283 // tail call optimization the copies to registers are lowered later.
2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2287 RegsToPass[i].second, InFlag);
2288 InFlag = Chain.getValue(1);
2291 if (Subtarget->isPICStyleGOT()) {
2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2296 DAG.getNode(X86ISD::GlobalBaseReg,
2297 DebugLoc(), getPointerTy()),
2299 InFlag = Chain.getValue(1);
2301 // If we are tail calling and generating PIC/GOT style code load the
2302 // address of the callee into ECX. The value in ecx is used as target of
2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2304 // for tail calls on PIC/GOT architectures. Normally we would just put the
2305 // address of GOT into ebx and then call target@PLT. But for tail calls
2306 // ebx would be restored (since ebx is callee saved) before jumping to the
2309 // Note: The actual moving to ECX is done further down.
2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2311 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2312 !G->getGlobal()->hasProtectedVisibility())
2313 Callee = LowerGlobalAddress(Callee, DAG);
2314 else if (isa<ExternalSymbolSDNode>(Callee))
2315 Callee = LowerExternalSymbol(Callee, DAG);
2319 if (Is64Bit && isVarArg && !IsWin64) {
2320 // From AMD64 ABI document:
2321 // For calls that may call functions that use varargs or stdargs
2322 // (prototype-less calls or calls to functions containing ellipsis (...) in
2323 // the declaration) %al is used as hidden argument to specify the number
2324 // of SSE registers used. The contents of %al do not need to match exactly
2325 // the number of registers, but must be an ubound on the number of SSE
2326 // registers used and is in the range 0 - 8 inclusive.
2328 // Count the number of XMM registers allocated.
2329 static const unsigned XMMArgRegs[] = {
2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2334 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2335 && "SSE registers cannot be used when SSE is disabled");
2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2339 InFlag = Chain.getValue(1);
2343 // For tail calls lower the arguments to the 'real' stack slot.
2345 // Force all the incoming stack arguments to be loaded from the stack
2346 // before any new outgoing arguments are stored to the stack, because the
2347 // outgoing stack slots may alias the incoming argument stack slots, and
2348 // the alias isn't otherwise explicit. This is slightly more conservative
2349 // than necessary, because it means that each store effectively depends
2350 // on every argument instead of just those arguments it would clobber.
2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2353 SmallVector<SDValue, 8> MemOpChains2;
2356 // Do not flag preceding copytoreg stuff together with the following stuff.
2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2360 CCValAssign &VA = ArgLocs[i];
2363 assert(VA.isMemLoc());
2364 SDValue Arg = OutVals[i];
2365 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2366 // Create frame index.
2367 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2370 FIN = DAG.getFrameIndex(FI, getPointerTy());
2372 if (Flags.isByVal()) {
2373 // Copy relative to framepointer.
2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2375 if (StackPtr.getNode() == 0)
2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2384 // Store relative to framepointer.
2385 MemOpChains2.push_back(
2386 DAG.getStore(ArgChain, dl, Arg, FIN,
2387 MachinePointerInfo::getFixedStack(FI),
2393 if (!MemOpChains2.empty())
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2395 &MemOpChains2[0], MemOpChains2.size());
2397 // Copy arguments to their registers.
2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2400 RegsToPass[i].second, InFlag);
2401 InFlag = Chain.getValue(1);
2405 // Store the return address to the appropriate stack slot.
2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2412 // In the 64-bit large code model, we have to make all calls
2413 // through a register, since the call instruction's 32-bit
2414 // pc-relative offset may not be large enough to hold the whole
2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2417 // If the callee is a GlobalAddress node (quite common, every direct call
2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2421 // We should use extra load for direct calls to dllimported functions in
2423 const GlobalValue *GV = G->getGlobal();
2424 if (!GV->hasDLLImportLinkage()) {
2425 unsigned char OpFlags = 0;
2426 bool ExtraLoad = false;
2427 unsigned WrapperKind = ISD::DELETED_NODE;
2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2430 // external symbols most go through the PLT in PIC mode. If the symbol
2431 // has hidden or protected visibility, or if it is static or local, then
2432 // we don't need to use the PLT - we can directly call it.
2433 if (Subtarget->isTargetELF() &&
2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2436 OpFlags = X86II::MO_PLT;
2437 } else if (Subtarget->isPICStyleStubAny() &&
2438 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2439 (!Subtarget->getTargetTriple().isMacOSX() ||
2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2441 // PC-relative references to external symbols should go through $stub,
2442 // unless we're building with the leopard linker or later, which
2443 // automatically synthesizes these stubs.
2444 OpFlags = X86II::MO_DARWIN_STUB;
2445 } else if (Subtarget->isPICStyleRIPRel() &&
2446 isa<Function>(GV) &&
2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2448 // If the function is marked as non-lazy, generate an indirect call
2449 // which loads from the GOT directly. This avoids runtime overhead
2450 // at the cost of eager binding (and one extra byte of encoding).
2451 OpFlags = X86II::MO_GOTPCREL;
2452 WrapperKind = X86ISD::WrapperRIP;
2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2457 G->getOffset(), OpFlags);
2459 // Add a wrapper if needed.
2460 if (WrapperKind != ISD::DELETED_NODE)
2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2462 // Add extra indirection if needed.
2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2465 MachinePointerInfo::getGOT(),
2466 false, false, false, 0);
2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2469 unsigned char OpFlags = 0;
2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2472 // external symbols should go through the PLT.
2473 if (Subtarget->isTargetELF() &&
2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2475 OpFlags = X86II::MO_PLT;
2476 } else if (Subtarget->isPICStyleStubAny() &&
2477 (!Subtarget->getTargetTriple().isMacOSX() ||
2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2479 // PC-relative references to external symbols should go through $stub,
2480 // unless we're building with the leopard linker or later, which
2481 // automatically synthesizes these stubs.
2482 OpFlags = X86II::MO_DARWIN_STUB;
2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2489 // Returns a chain & a flag for retval copy to use.
2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2491 SmallVector<SDValue, 8> Ops;
2493 if (!IsSibcall && isTailCall) {
2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2495 DAG.getIntPtrConstant(0, true), InFlag);
2496 InFlag = Chain.getValue(1);
2499 Ops.push_back(Chain);
2500 Ops.push_back(Callee);
2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2505 // Add argument registers to the end of the list so that they are known live
2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2509 RegsToPass[i].second.getValueType()));
2511 // Add an implicit use GOT pointer in EBX.
2512 if (!isTailCall && Subtarget->isPICStyleGOT())
2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2516 if (Is64Bit && isVarArg && !IsWin64)
2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2519 // Experimental: Add a register mask operand representing the call-preserved
2522 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2523 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2524 Ops.push_back(DAG.getRegisterMask(Mask));
2527 if (InFlag.getNode())
2528 Ops.push_back(InFlag);
2532 //// If this is the first return lowered for this function, add the regs
2533 //// to the liveout set for the function.
2534 // This isn't right, although it's probably harmless on x86; liveouts
2535 // should be computed from returns not tail calls. Consider a void
2536 // function making a tail call to a function returning int.
2537 return DAG.getNode(X86ISD::TC_RETURN, dl,
2538 NodeTys, &Ops[0], Ops.size());
2541 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2542 InFlag = Chain.getValue(1);
2544 // Create the CALLSEQ_END node.
2545 unsigned NumBytesForCalleeToPush;
2546 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2547 getTargetMachine().Options.GuaranteedTailCallOpt))
2548 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2549 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2551 // If this is a call to a struct-return function, the callee
2552 // pops the hidden struct pointer, so we have to push it back.
2553 // This is common for Darwin/X86, Linux & Mingw32 targets.
2554 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2555 NumBytesForCalleeToPush = 4;
2557 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2559 // Returns a flag for retval copy to use.
2561 Chain = DAG.getCALLSEQ_END(Chain,
2562 DAG.getIntPtrConstant(NumBytes, true),
2563 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2566 InFlag = Chain.getValue(1);
2569 // Handle result values, copying them out of physregs into vregs that we
2571 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2572 Ins, dl, DAG, InVals);
2576 //===----------------------------------------------------------------------===//
2577 // Fast Calling Convention (tail call) implementation
2578 //===----------------------------------------------------------------------===//
2580 // Like std call, callee cleans arguments, convention except that ECX is
2581 // reserved for storing the tail called function address. Only 2 registers are
2582 // free for argument passing (inreg). Tail call optimization is performed
2584 // * tailcallopt is enabled
2585 // * caller/callee are fastcc
2586 // On X86_64 architecture with GOT-style position independent code only local
2587 // (within module) calls are supported at the moment.
2588 // To keep the stack aligned according to platform abi the function
2589 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2590 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2591 // If a tail called function callee has more arguments than the caller the
2592 // caller needs to make sure that there is room to move the RETADDR to. This is
2593 // achieved by reserving an area the size of the argument delta right after the
2594 // original REtADDR, but before the saved framepointer or the spilled registers
2595 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2607 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2608 /// for a 16 byte align requirement.
2610 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2611 SelectionDAG& DAG) const {
2612 MachineFunction &MF = DAG.getMachineFunction();
2613 const TargetMachine &TM = MF.getTarget();
2614 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2615 unsigned StackAlignment = TFI.getStackAlignment();
2616 uint64_t AlignMask = StackAlignment - 1;
2617 int64_t Offset = StackSize;
2618 uint64_t SlotSize = TD->getPointerSize();
2619 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2620 // Number smaller than 12 so just add the difference.
2621 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2623 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2624 Offset = ((~AlignMask) & Offset) + StackAlignment +
2625 (StackAlignment-SlotSize);
2630 /// MatchingStackOffset - Return true if the given stack call argument is
2631 /// already available in the same position (relatively) of the caller's
2632 /// incoming argument stack.
2634 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2635 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2636 const X86InstrInfo *TII) {
2637 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2639 if (Arg.getOpcode() == ISD::CopyFromReg) {
2640 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2641 if (!TargetRegisterInfo::isVirtualRegister(VR))
2643 MachineInstr *Def = MRI->getVRegDef(VR);
2646 if (!Flags.isByVal()) {
2647 if (!TII->isLoadFromStackSlot(Def, FI))
2650 unsigned Opcode = Def->getOpcode();
2651 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2652 Def->getOperand(1).isFI()) {
2653 FI = Def->getOperand(1).getIndex();
2654 Bytes = Flags.getByValSize();
2658 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2659 if (Flags.isByVal())
2660 // ByVal argument is passed in as a pointer but it's now being
2661 // dereferenced. e.g.
2662 // define @foo(%struct.X* %A) {
2663 // tail call @bar(%struct.X* byval %A)
2666 SDValue Ptr = Ld->getBasePtr();
2667 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2670 FI = FINode->getIndex();
2671 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2672 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2673 FI = FINode->getIndex();
2674 Bytes = Flags.getByValSize();
2678 assert(FI != INT_MAX);
2679 if (!MFI->isFixedObjectIndex(FI))
2681 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2684 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2685 /// for tail call optimization. Targets which want to do tail call
2686 /// optimization should implement this function.
2688 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2689 CallingConv::ID CalleeCC,
2691 bool isCalleeStructRet,
2692 bool isCallerStructRet,
2693 const SmallVectorImpl<ISD::OutputArg> &Outs,
2694 const SmallVectorImpl<SDValue> &OutVals,
2695 const SmallVectorImpl<ISD::InputArg> &Ins,
2696 SelectionDAG& DAG) const {
2697 if (!IsTailCallConvention(CalleeCC) &&
2698 CalleeCC != CallingConv::C)
2701 // If -tailcallopt is specified, make fastcc functions tail-callable.
2702 const MachineFunction &MF = DAG.getMachineFunction();
2703 const Function *CallerF = DAG.getMachineFunction().getFunction();
2704 CallingConv::ID CallerCC = CallerF->getCallingConv();
2705 bool CCMatch = CallerCC == CalleeCC;
2707 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2708 if (IsTailCallConvention(CalleeCC) && CCMatch)
2713 // Look for obvious safe cases to perform tail call optimization that do not
2714 // require ABI changes. This is what gcc calls sibcall.
2716 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2717 // emit a special epilogue.
2718 if (RegInfo->needsStackRealignment(MF))
2721 // Also avoid sibcall optimization if either caller or callee uses struct
2722 // return semantics.
2723 if (isCalleeStructRet || isCallerStructRet)
2726 // An stdcall caller is expected to clean up its arguments; the callee
2727 // isn't going to do that.
2728 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2731 // Do not sibcall optimize vararg calls unless all arguments are passed via
2733 if (isVarArg && !Outs.empty()) {
2735 // Optimizing for varargs on Win64 is unlikely to be safe without
2736 // additional testing.
2737 if (Subtarget->isTargetWin64())
2740 SmallVector<CCValAssign, 16> ArgLocs;
2741 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2742 getTargetMachine(), ArgLocs, *DAG.getContext());
2744 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2746 if (!ArgLocs[i].isRegLoc())
2750 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2751 // stack. Therefore, if it's not used by the call it is not safe to optimize
2752 // this into a sibcall.
2753 bool Unused = false;
2754 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2761 SmallVector<CCValAssign, 16> RVLocs;
2762 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2763 getTargetMachine(), RVLocs, *DAG.getContext());
2764 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2765 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2766 CCValAssign &VA = RVLocs[i];
2767 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2772 // If the calling conventions do not match, then we'd better make sure the
2773 // results are returned in the same way as what the caller expects.
2775 SmallVector<CCValAssign, 16> RVLocs1;
2776 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2777 getTargetMachine(), RVLocs1, *DAG.getContext());
2778 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2780 SmallVector<CCValAssign, 16> RVLocs2;
2781 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2782 getTargetMachine(), RVLocs2, *DAG.getContext());
2783 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2785 if (RVLocs1.size() != RVLocs2.size())
2787 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2788 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2790 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2792 if (RVLocs1[i].isRegLoc()) {
2793 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2796 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2802 // If the callee takes no arguments then go on to check the results of the
2804 if (!Outs.empty()) {
2805 // Check if stack adjustment is needed. For now, do not do this if any
2806 // argument is passed on the stack.
2807 SmallVector<CCValAssign, 16> ArgLocs;
2808 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2809 getTargetMachine(), ArgLocs, *DAG.getContext());
2811 // Allocate shadow area for Win64
2812 if (Subtarget->isTargetWin64()) {
2813 CCInfo.AllocateStack(32, 8);
2816 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2817 if (CCInfo.getNextStackOffset()) {
2818 MachineFunction &MF = DAG.getMachineFunction();
2819 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2822 // Check if the arguments are already laid out in the right way as
2823 // the caller's fixed stack objects.
2824 MachineFrameInfo *MFI = MF.getFrameInfo();
2825 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2826 const X86InstrInfo *TII =
2827 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2829 CCValAssign &VA = ArgLocs[i];
2830 SDValue Arg = OutVals[i];
2831 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2832 if (VA.getLocInfo() == CCValAssign::Indirect)
2834 if (!VA.isRegLoc()) {
2835 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2842 // If the tailcall address may be in a register, then make sure it's
2843 // possible to register allocate for it. In 32-bit, the call address can
2844 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2845 // callee-saved registers are restored. These happen to be the same
2846 // registers used to pass 'inreg' arguments so watch out for those.
2847 if (!Subtarget->is64Bit() &&
2848 !isa<GlobalAddressSDNode>(Callee) &&
2849 !isa<ExternalSymbolSDNode>(Callee)) {
2850 unsigned NumInRegs = 0;
2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2852 CCValAssign &VA = ArgLocs[i];
2855 unsigned Reg = VA.getLocReg();
2858 case X86::EAX: case X86::EDX: case X86::ECX:
2859 if (++NumInRegs == 3)
2871 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2872 return X86::createFastISel(funcInfo);
2876 //===----------------------------------------------------------------------===//
2877 // Other Lowering Hooks
2878 //===----------------------------------------------------------------------===//
2880 static bool MayFoldLoad(SDValue Op) {
2881 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2884 static bool MayFoldIntoStore(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2888 static bool isTargetShuffle(unsigned Opcode) {
2890 default: return false;
2891 case X86ISD::PSHUFD:
2892 case X86ISD::PSHUFHW:
2893 case X86ISD::PSHUFLW:
2895 case X86ISD::PALIGN:
2896 case X86ISD::MOVLHPS:
2897 case X86ISD::MOVLHPD:
2898 case X86ISD::MOVHLPS:
2899 case X86ISD::MOVLPS:
2900 case X86ISD::MOVLPD:
2901 case X86ISD::MOVSHDUP:
2902 case X86ISD::MOVSLDUP:
2903 case X86ISD::MOVDDUP:
2906 case X86ISD::UNPCKL:
2907 case X86ISD::UNPCKH:
2908 case X86ISD::VPERMILP:
2909 case X86ISD::VPERM2X128:
2915 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2916 SDValue V1, SelectionDAG &DAG) {
2918 default: llvm_unreachable("Unknown x86 shuffle node");
2919 case X86ISD::MOVSHDUP:
2920 case X86ISD::MOVSLDUP:
2921 case X86ISD::MOVDDUP:
2922 return DAG.getNode(Opc, dl, VT, V1);
2928 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2929 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2931 default: llvm_unreachable("Unknown x86 shuffle node");
2932 case X86ISD::PSHUFD:
2933 case X86ISD::PSHUFHW:
2934 case X86ISD::PSHUFLW:
2935 case X86ISD::VPERMILP:
2936 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2942 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2943 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2945 default: llvm_unreachable("Unknown x86 shuffle node");
2946 case X86ISD::PALIGN:
2948 case X86ISD::VPERM2X128:
2949 return DAG.getNode(Opc, dl, VT, V1, V2,
2950 DAG.getConstant(TargetMask, MVT::i8));
2955 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2956 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2958 default: llvm_unreachable("Unknown x86 shuffle node");
2959 case X86ISD::MOVLHPS:
2960 case X86ISD::MOVLHPD:
2961 case X86ISD::MOVHLPS:
2962 case X86ISD::MOVLPS:
2963 case X86ISD::MOVLPD:
2966 case X86ISD::UNPCKL:
2967 case X86ISD::UNPCKH:
2968 return DAG.getNode(Opc, dl, VT, V1, V2);
2973 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2976 int ReturnAddrIndex = FuncInfo->getRAIndex();
2978 if (ReturnAddrIndex == 0) {
2979 // Set up a frame object for the return address.
2980 uint64_t SlotSize = TD->getPointerSize();
2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2983 FuncInfo->setRAIndex(ReturnAddrIndex);
2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2990 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2991 bool hasSymbolicDisplacement) {
2992 // Offset should fit into 32 bit immediate field.
2993 if (!isInt<32>(Offset))
2996 // If we don't have a symbolic displacement - we don't have any extra
2998 if (!hasSymbolicDisplacement)
3001 // FIXME: Some tweaks might be needed for medium code model.
3002 if (M != CodeModel::Small && M != CodeModel::Kernel)
3005 // For small code model we assume that latest object is 16MB before end of 31
3006 // bits boundary. We may also accept pretty large negative constants knowing
3007 // that all objects are in the positive half of address space.
3008 if (M == CodeModel::Small && Offset < 16*1024*1024)
3011 // For kernel code model we know that all object resist in the negative half
3012 // of 32bits address space. We may not accept negative offsets, since they may
3013 // be just off and we may accept pretty large positive ones.
3014 if (M == CodeModel::Kernel && Offset > 0)
3020 /// isCalleePop - Determines whether the callee is required to pop its
3021 /// own arguments. Callee pop is necessary to support tail calls.
3022 bool X86::isCalleePop(CallingConv::ID CallingConv,
3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3027 switch (CallingConv) {
3030 case CallingConv::X86_StdCall:
3032 case CallingConv::X86_FastCall:
3034 case CallingConv::X86_ThisCall:
3036 case CallingConv::Fast:
3038 case CallingConv::GHC:
3043 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3044 /// specific condition code, returning the condition code and the LHS/RHS of the
3045 /// comparison to make.
3046 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3051 // X > -1 -> X == 0, jump !sign.
3052 RHS = DAG.getConstant(0, RHS.getValueType());
3053 return X86::COND_NS;
3054 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3055 // X < 0 -> X == 0, jump on sign.
3057 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3059 RHS = DAG.getConstant(0, RHS.getValueType());
3060 return X86::COND_LE;
3064 switch (SetCCOpcode) {
3065 default: llvm_unreachable("Invalid integer condition!");
3066 case ISD::SETEQ: return X86::COND_E;
3067 case ISD::SETGT: return X86::COND_G;
3068 case ISD::SETGE: return X86::COND_GE;
3069 case ISD::SETLT: return X86::COND_L;
3070 case ISD::SETLE: return X86::COND_LE;
3071 case ISD::SETNE: return X86::COND_NE;
3072 case ISD::SETULT: return X86::COND_B;
3073 case ISD::SETUGT: return X86::COND_A;
3074 case ISD::SETULE: return X86::COND_BE;
3075 case ISD::SETUGE: return X86::COND_AE;
3079 // First determine if it is required or is profitable to flip the operands.
3081 // If LHS is a foldable load, but RHS is not, flip the condition.
3082 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3083 !ISD::isNON_EXTLoad(RHS.getNode())) {
3084 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3085 std::swap(LHS, RHS);
3088 switch (SetCCOpcode) {
3094 std::swap(LHS, RHS);
3098 // On a floating point condition, the flags are set as follows:
3100 // 0 | 0 | 0 | X > Y
3101 // 0 | 0 | 1 | X < Y
3102 // 1 | 0 | 0 | X == Y
3103 // 1 | 1 | 1 | unordered
3104 switch (SetCCOpcode) {
3105 default: llvm_unreachable("Condcode should be pre-legalized away");
3107 case ISD::SETEQ: return X86::COND_E;
3108 case ISD::SETOLT: // flipped
3110 case ISD::SETGT: return X86::COND_A;
3111 case ISD::SETOLE: // flipped
3113 case ISD::SETGE: return X86::COND_AE;
3114 case ISD::SETUGT: // flipped
3116 case ISD::SETLT: return X86::COND_B;
3117 case ISD::SETUGE: // flipped
3119 case ISD::SETLE: return X86::COND_BE;
3121 case ISD::SETNE: return X86::COND_NE;
3122 case ISD::SETUO: return X86::COND_P;
3123 case ISD::SETO: return X86::COND_NP;
3125 case ISD::SETUNE: return X86::COND_INVALID;
3129 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3130 /// code. Current x86 isa includes the following FP cmov instructions:
3131 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3132 static bool hasFPCMov(unsigned X86CC) {
3148 /// isFPImmLegal - Returns true if the target can instruction select the
3149 /// specified FP immediate natively. If false, the legalizer will
3150 /// materialize the FP immediate as a load from a constant pool.
3151 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3152 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3153 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3159 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3160 /// the specified range (L, H].
3161 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3162 return (Val < 0) || (Val >= Low && Val < Hi);
3165 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3166 /// specified value.
3167 static bool isUndefOrEqual(int Val, int CmpVal) {
3168 if (Val < 0 || Val == CmpVal)
3173 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3174 /// from position Pos and ending in Pos+Size, falls within the specified
3175 /// sequential range (L, L+Pos]. or is undef.
3176 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3177 int Pos, int Size, int Low) {
3178 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3179 if (!isUndefOrEqual(Mask[i], Low))
3184 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3185 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3186 /// the second operand.
3187 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3188 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3189 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3190 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3191 return (Mask[0] < 2 && Mask[1] < 2);
3195 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3196 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3199 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3200 /// is suitable for input to PSHUFHW.
3201 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3202 if (VT != MVT::v8i16)
3205 // Lower quadword copied in order or undef.
3206 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3209 // Upper quadword shuffled.
3210 for (unsigned i = 4; i != 8; ++i)
3211 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3217 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3218 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3221 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3222 /// is suitable for input to PSHUFLW.
3223 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3224 if (VT != MVT::v8i16)
3227 // Upper quadword copied in order.
3228 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3231 // Lower quadword shuffled.
3232 for (unsigned i = 0; i != 4; ++i)
3239 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3240 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3243 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3244 /// is suitable for input to PALIGNR.
3245 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3246 const X86Subtarget *Subtarget) {
3247 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3248 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3251 unsigned NumElts = VT.getVectorNumElements();
3252 unsigned NumLanes = VT.getSizeInBits()/128;
3253 unsigned NumLaneElts = NumElts/NumLanes;
3255 // Do not handle 64-bit element shuffles with palignr.
3256 if (NumLaneElts == 2)
3259 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3261 for (i = 0; i != NumLaneElts; ++i) {
3266 // Lane is all undef, go to next lane
3267 if (i == NumLaneElts)
3270 int Start = Mask[i+l];
3272 // Make sure its in this lane in one of the sources
3273 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3274 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3277 // If not lane 0, then we must match lane 0
3278 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3281 // Correct second source to be contiguous with first source
3282 if (Start >= (int)NumElts)
3283 Start -= NumElts - NumLaneElts;
3285 // Make sure we're shifting in the right direction.
3286 if (Start <= (int)(i+l))
3291 // Check the rest of the elements to see if they are consecutive.
3292 for (++i; i != NumLaneElts; ++i) {
3293 int Idx = Mask[i+l];
3295 // Make sure its in this lane
3296 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3297 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3300 // If not lane 0, then we must match lane 0
3301 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3304 if (Idx >= (int)NumElts)
3305 Idx -= NumElts - NumLaneElts;
3307 if (!isUndefOrEqual(Idx, Start+i))
3316 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3317 /// the two vector operands have swapped position.
3318 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3319 unsigned NumElems) {
3320 for (unsigned i = 0; i != NumElems; ++i) {
3324 else if (idx < (int)NumElems)
3325 Mask[i] = idx + NumElems;
3327 Mask[i] = idx - NumElems;
3331 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3332 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3333 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3334 /// reverse of what x86 shuffles want.
3335 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3336 bool Commuted = false) {
3337 if (!HasAVX && VT.getSizeInBits() == 256)
3340 unsigned NumElems = VT.getVectorNumElements();
3341 unsigned NumLanes = VT.getSizeInBits()/128;
3342 unsigned NumLaneElems = NumElems/NumLanes;
3344 if (NumLaneElems != 2 && NumLaneElems != 4)
3347 // VSHUFPSY divides the resulting vector into 4 chunks.
3348 // The sources are also splitted into 4 chunks, and each destination
3349 // chunk must come from a different source chunk.
3351 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3352 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3354 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3355 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3357 // VSHUFPDY divides the resulting vector into 4 chunks.
3358 // The sources are also splitted into 4 chunks, and each destination
3359 // chunk must come from a different source chunk.
3361 // SRC1 => X3 X2 X1 X0
3362 // SRC2 => Y3 Y2 Y1 Y0
3364 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3366 unsigned HalfLaneElems = NumLaneElems/2;
3367 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3368 for (unsigned i = 0; i != NumLaneElems; ++i) {
3369 int Idx = Mask[i+l];
3370 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3371 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3373 // For VSHUFPSY, the mask of the second half must be the same as the
3374 // first but with the appropriate offsets. This works in the same way as
3375 // VPERMILPS works with masks.
3376 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3378 if (!isUndefOrEqual(Idx, Mask[i]+l))
3386 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3387 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3390 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3391 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3392 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3393 EVT VT = N->getValueType(0);
3394 unsigned NumElems = VT.getVectorNumElements();
3396 if (VT.getSizeInBits() != 128)
3402 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3403 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3404 isUndefOrEqual(N->getMaskElt(1), 7) &&
3405 isUndefOrEqual(N->getMaskElt(2), 2) &&
3406 isUndefOrEqual(N->getMaskElt(3), 3);
3409 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3410 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3412 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3413 EVT VT = N->getValueType(0);
3414 unsigned NumElems = VT.getVectorNumElements();
3416 if (VT.getSizeInBits() != 128)
3422 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3423 isUndefOrEqual(N->getMaskElt(1), 3) &&
3424 isUndefOrEqual(N->getMaskElt(2), 2) &&
3425 isUndefOrEqual(N->getMaskElt(3), 3);
3428 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3429 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3430 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3431 EVT VT = N->getValueType(0);
3433 if (VT.getSizeInBits() != 128)
3436 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3438 if (NumElems != 2 && NumElems != 4)
3441 for (unsigned i = 0; i < NumElems/2; ++i)
3442 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3445 for (unsigned i = NumElems/2; i < NumElems; ++i)
3446 if (!isUndefOrEqual(N->getMaskElt(i), i))
3452 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3453 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3454 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3455 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3457 if ((NumElems != 2 && NumElems != 4)
3458 || N->getValueType(0).getSizeInBits() > 128)
3461 for (unsigned i = 0; i < NumElems/2; ++i)
3462 if (!isUndefOrEqual(N->getMaskElt(i), i))
3465 for (unsigned i = 0; i < NumElems/2; ++i)
3466 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3472 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3473 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3474 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3475 bool HasAVX2, bool V2IsSplat = false) {
3476 unsigned NumElts = VT.getVectorNumElements();
3478 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3479 "Unsupported vector type for unpckh");
3481 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3482 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3485 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3486 // independently on 128-bit lanes.
3487 unsigned NumLanes = VT.getSizeInBits()/128;
3488 unsigned NumLaneElts = NumElts/NumLanes;
3490 for (unsigned l = 0; l != NumLanes; ++l) {
3491 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3492 i != (l+1)*NumLaneElts;
3495 int BitI1 = Mask[i+1];
3496 if (!isUndefOrEqual(BitI, j))
3499 if (!isUndefOrEqual(BitI1, NumElts))
3502 if (!isUndefOrEqual(BitI1, j + NumElts))
3511 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3512 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3515 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3516 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3517 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3518 bool HasAVX2, bool V2IsSplat = false) {
3519 unsigned NumElts = VT.getVectorNumElements();
3521 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3522 "Unsupported vector type for unpckh");
3524 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3525 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3528 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3529 // independently on 128-bit lanes.
3530 unsigned NumLanes = VT.getSizeInBits()/128;
3531 unsigned NumLaneElts = NumElts/NumLanes;
3533 for (unsigned l = 0; l != NumLanes; ++l) {
3534 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3535 i != (l+1)*NumLaneElts; i += 2, ++j) {
3537 int BitI1 = Mask[i+1];
3538 if (!isUndefOrEqual(BitI, j))
3541 if (isUndefOrEqual(BitI1, NumElts))
3544 if (!isUndefOrEqual(BitI1, j+NumElts))
3552 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3553 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3556 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3557 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3559 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3561 unsigned NumElts = VT.getVectorNumElements();
3563 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3564 "Unsupported vector type for unpckh");
3566 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3567 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3570 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3571 // FIXME: Need a better way to get rid of this, there's no latency difference
3572 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3573 // the former later. We should also remove the "_undef" special mask.
3574 if (NumElts == 4 && VT.getSizeInBits() == 256)
3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3578 // independently on 128-bit lanes.
3579 unsigned NumLanes = VT.getSizeInBits()/128;
3580 unsigned NumLaneElts = NumElts/NumLanes;
3582 for (unsigned l = 0; l != NumLanes; ++l) {
3583 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3584 i != (l+1)*NumLaneElts;
3587 int BitI1 = Mask[i+1];
3589 if (!isUndefOrEqual(BitI, j))
3591 if (!isUndefOrEqual(BitI1, j))
3599 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3600 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3603 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3604 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3606 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3607 unsigned NumElts = VT.getVectorNumElements();
3609 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3610 "Unsupported vector type for unpckh");
3612 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3613 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3616 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3617 // independently on 128-bit lanes.
3618 unsigned NumLanes = VT.getSizeInBits()/128;
3619 unsigned NumLaneElts = NumElts/NumLanes;
3621 for (unsigned l = 0; l != NumLanes; ++l) {
3622 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3623 i != (l+1)*NumLaneElts; i += 2, ++j) {
3625 int BitI1 = Mask[i+1];
3626 if (!isUndefOrEqual(BitI, j))
3628 if (!isUndefOrEqual(BitI1, j))
3635 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3636 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3639 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3640 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3641 /// MOVSD, and MOVD, i.e. setting the lowest element.
3642 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3643 if (VT.getVectorElementType().getSizeInBits() < 32)
3645 if (VT.getSizeInBits() == 256)
3648 unsigned NumElts = VT.getVectorNumElements();
3650 if (!isUndefOrEqual(Mask[0], NumElts))
3653 for (unsigned i = 1; i != NumElts; ++i)
3654 if (!isUndefOrEqual(Mask[i], i))
3660 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3661 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3664 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3665 /// as permutations between 128-bit chunks or halves. As an example: this
3667 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3668 /// The first half comes from the second half of V1 and the second half from the
3669 /// the second half of V2.
3670 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3671 if (!HasAVX || VT.getSizeInBits() != 256)
3674 // The shuffle result is divided into half A and half B. In total the two
3675 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3676 // B must come from C, D, E or F.
3677 unsigned HalfSize = VT.getVectorNumElements()/2;
3678 bool MatchA = false, MatchB = false;
3680 // Check if A comes from one of C, D, E, F.
3681 for (unsigned Half = 0; Half != 4; ++Half) {
3682 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3688 // Check if B comes from one of C, D, E, F.
3689 for (unsigned Half = 0; Half != 4; ++Half) {
3690 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3696 return MatchA && MatchB;
3699 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3700 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3701 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3702 EVT VT = SVOp->getValueType(0);
3704 unsigned HalfSize = VT.getVectorNumElements()/2;
3706 unsigned FstHalf = 0, SndHalf = 0;
3707 for (unsigned i = 0; i < HalfSize; ++i) {
3708 if (SVOp->getMaskElt(i) > 0) {
3709 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3713 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3714 if (SVOp->getMaskElt(i) > 0) {
3715 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3720 return (FstHalf | (SndHalf << 4));
3723 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3724 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3725 /// Note that VPERMIL mask matching is different depending whether theunderlying
3726 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3727 /// to the same elements of the low, but to the higher half of the source.
3728 /// In VPERMILPD the two lanes could be shuffled independently of each other
3729 /// with the same restriction that lanes can't be crossed.
3730 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3734 unsigned NumElts = VT.getVectorNumElements();
3735 // Only match 256-bit with 32/64-bit types
3736 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3739 unsigned NumLanes = VT.getSizeInBits()/128;
3740 unsigned LaneSize = NumElts/NumLanes;
3741 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3742 for (unsigned i = 0; i != LaneSize; ++i) {
3743 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3745 if (NumElts != 8 || l == 0)
3747 // VPERMILPS handling
3750 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3758 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3759 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3760 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3761 EVT VT = SVOp->getValueType(0);
3763 unsigned NumElts = VT.getVectorNumElements();
3764 unsigned NumLanes = VT.getSizeInBits()/128;
3765 unsigned LaneSize = NumElts/NumLanes;
3767 // Although the mask is equal for both lanes do it twice to get the cases
3768 // where a mask will match because the same mask element is undef on the
3769 // first half but valid on the second. This would get pathological cases
3770 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3771 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3773 for (unsigned i = 0; i != NumElts; ++i) {
3774 int MaskElt = SVOp->getMaskElt(i);
3777 MaskElt %= LaneSize;
3779 // VPERMILPSY, the mask of the first half must be equal to the second one
3780 if (NumElts == 8) Shamt %= LaneSize;
3781 Mask |= MaskElt << (Shamt*Shift);
3787 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3788 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3789 /// element of vector 2 and the other elements to come from vector 1 in order.
3790 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3791 bool V2IsSplat = false, bool V2IsUndef = false) {
3792 unsigned NumOps = VT.getVectorNumElements();
3793 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3796 if (!isUndefOrEqual(Mask[0], 0))
3799 for (unsigned i = 1; i != NumOps; ++i)
3800 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3801 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3802 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3808 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3809 bool V2IsUndef = false) {
3810 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3811 V2IsSplat, V2IsUndef);
3814 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3815 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3816 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3817 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3818 const X86Subtarget *Subtarget) {
3819 if (!Subtarget->hasSSE3())
3822 // The second vector must be undef
3823 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3826 EVT VT = N->getValueType(0);
3827 unsigned NumElems = VT.getVectorNumElements();
3829 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3830 (VT.getSizeInBits() == 256 && NumElems != 8))
3833 // "i+1" is the value the indexed mask element must have
3834 for (unsigned i = 0; i < NumElems; i += 2)
3835 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3836 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3842 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3843 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3844 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3845 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3846 const X86Subtarget *Subtarget) {
3847 if (!Subtarget->hasSSE3())
3850 // The second vector must be undef
3851 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3854 EVT VT = N->getValueType(0);
3855 unsigned NumElems = VT.getVectorNumElements();
3857 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3858 (VT.getSizeInBits() == 256 && NumElems != 8))
3861 // "i" is the value the indexed mask element must have
3862 for (unsigned i = 0; i != NumElems; i += 2)
3863 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3864 !isUndefOrEqual(N->getMaskElt(i+1), i))
3870 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3871 /// specifies a shuffle of elements that is suitable for input to 256-bit
3872 /// version of MOVDDUP.
3873 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3874 unsigned NumElts = VT.getVectorNumElements();
3876 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3879 for (unsigned i = 0; i != NumElts/2; ++i)
3880 if (!isUndefOrEqual(Mask[i], 0))
3882 for (unsigned i = NumElts/2; i != NumElts; ++i)
3883 if (!isUndefOrEqual(Mask[i], NumElts/2))
3888 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3889 /// specifies a shuffle of elements that is suitable for input to 128-bit
3890 /// version of MOVDDUP.
3891 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3892 EVT VT = N->getValueType(0);
3894 if (VT.getSizeInBits() != 128)
3897 unsigned e = VT.getVectorNumElements() / 2;
3898 for (unsigned i = 0; i != e; ++i)
3899 if (!isUndefOrEqual(N->getMaskElt(i), i))
3901 for (unsigned i = 0; i != e; ++i)
3902 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3907 /// isVEXTRACTF128Index - Return true if the specified
3908 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3909 /// suitable for input to VEXTRACTF128.
3910 bool X86::isVEXTRACTF128Index(SDNode *N) {
3911 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3914 // The index should be aligned on a 128-bit boundary.
3916 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3918 unsigned VL = N->getValueType(0).getVectorNumElements();
3919 unsigned VBits = N->getValueType(0).getSizeInBits();
3920 unsigned ElSize = VBits / VL;
3921 bool Result = (Index * ElSize) % 128 == 0;
3926 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3927 /// operand specifies a subvector insert that is suitable for input to
3929 bool X86::isVINSERTF128Index(SDNode *N) {
3930 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3933 // The index should be aligned on a 128-bit boundary.
3935 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3937 unsigned VL = N->getValueType(0).getVectorNumElements();
3938 unsigned VBits = N->getValueType(0).getSizeInBits();
3939 unsigned ElSize = VBits / VL;
3940 bool Result = (Index * ElSize) % 128 == 0;
3945 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3946 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3947 /// Handles 128-bit and 256-bit.
3948 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3949 EVT VT = N->getValueType(0);
3951 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3952 "Unsupported vector type for PSHUF/SHUFP");
3954 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3955 // independently on 128-bit lanes.
3956 unsigned NumElts = VT.getVectorNumElements();
3957 unsigned NumLanes = VT.getSizeInBits()/128;
3958 unsigned NumLaneElts = NumElts/NumLanes;
3960 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3961 "Only supports 2 or 4 elements per lane");
3963 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3965 for (unsigned i = 0; i != NumElts; ++i) {
3966 int Elt = N->getMaskElt(i);
3967 if (Elt < 0) continue;
3969 unsigned ShAmt = i << Shift;
3970 if (ShAmt >= 8) ShAmt -= 8;
3971 Mask |= Elt << ShAmt;
3977 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3978 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3979 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3980 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3982 // 8 nodes, but we only care about the last 4.
3983 for (unsigned i = 7; i >= 4; --i) {
3984 int Val = SVOp->getMaskElt(i);
3993 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3994 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3995 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3998 // 8 nodes, but we only care about the first 4.
3999 for (int i = 3; i >= 0; --i) {
4000 int Val = SVOp->getMaskElt(i);
4009 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4010 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4011 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4012 EVT VT = SVOp->getValueType(0);
4013 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4015 unsigned NumElts = VT.getVectorNumElements();
4016 unsigned NumLanes = VT.getSizeInBits()/128;
4017 unsigned NumLaneElts = NumElts/NumLanes;
4021 for (i = 0; i != NumElts; ++i) {
4022 Val = SVOp->getMaskElt(i);
4026 if (Val >= (int)NumElts)
4027 Val -= NumElts - NumLaneElts;
4029 assert(Val - i > 0 && "PALIGNR imm should be positive");
4030 return (Val - i) * EltSize;
4033 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4034 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4036 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4037 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4038 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4041 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4043 EVT VecVT = N->getOperand(0).getValueType();
4044 EVT ElVT = VecVT.getVectorElementType();
4046 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4047 return Index / NumElemsPerChunk;
4050 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4051 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4053 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4054 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4055 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4058 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4060 EVT VecVT = N->getValueType(0);
4061 EVT ElVT = VecVT.getVectorElementType();
4063 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4064 return Index / NumElemsPerChunk;
4067 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4069 bool X86::isZeroNode(SDValue Elt) {
4070 return ((isa<ConstantSDNode>(Elt) &&
4071 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4072 (isa<ConstantFPSDNode>(Elt) &&
4073 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4076 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4077 /// their permute mask.
4078 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4079 SelectionDAG &DAG) {
4080 EVT VT = SVOp->getValueType(0);
4081 unsigned NumElems = VT.getVectorNumElements();
4082 SmallVector<int, 8> MaskVec;
4084 for (unsigned i = 0; i != NumElems; ++i) {
4085 int idx = SVOp->getMaskElt(i);
4087 MaskVec.push_back(idx);
4088 else if (idx < (int)NumElems)
4089 MaskVec.push_back(idx + NumElems);
4091 MaskVec.push_back(idx - NumElems);
4093 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4094 SVOp->getOperand(0), &MaskVec[0]);
4097 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4098 /// match movhlps. The lower half elements should come from upper half of
4099 /// V1 (and in order), and the upper half elements should come from the upper
4100 /// half of V2 (and in order).
4101 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4102 EVT VT = Op->getValueType(0);
4103 if (VT.getSizeInBits() != 128)
4105 if (VT.getVectorNumElements() != 4)
4107 for (unsigned i = 0, e = 2; i != e; ++i)
4108 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4110 for (unsigned i = 2; i != 4; ++i)
4111 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4116 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4117 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4119 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4120 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4122 N = N->getOperand(0).getNode();
4123 if (!ISD::isNON_EXTLoad(N))
4126 *LD = cast<LoadSDNode>(N);
4130 // Test whether the given value is a vector value which will be legalized
4132 static bool WillBeConstantPoolLoad(SDNode *N) {
4133 if (N->getOpcode() != ISD::BUILD_VECTOR)
4136 // Check for any non-constant elements.
4137 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4138 switch (N->getOperand(i).getNode()->getOpcode()) {
4140 case ISD::ConstantFP:
4147 // Vectors of all-zeros and all-ones are materialized with special
4148 // instructions rather than being loaded.
4149 return !ISD::isBuildVectorAllZeros(N) &&
4150 !ISD::isBuildVectorAllOnes(N);
4153 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4154 /// match movlp{s|d}. The lower half elements should come from lower half of
4155 /// V1 (and in order), and the upper half elements should come from the upper
4156 /// half of V2 (and in order). And since V1 will become the source of the
4157 /// MOVLP, it must be either a vector load or a scalar load to vector.
4158 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4159 ShuffleVectorSDNode *Op) {
4160 EVT VT = Op->getValueType(0);
4161 if (VT.getSizeInBits() != 128)
4164 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4166 // Is V2 is a vector load, don't do this transformation. We will try to use
4167 // load folding shufps op.
4168 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4171 unsigned NumElems = VT.getVectorNumElements();
4173 if (NumElems != 2 && NumElems != 4)
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4178 for (unsigned i = NumElems/2; i != NumElems; ++i)
4179 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4184 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4186 static bool isSplatVector(SDNode *N) {
4187 if (N->getOpcode() != ISD::BUILD_VECTOR)
4190 SDValue SplatValue = N->getOperand(0);
4191 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4192 if (N->getOperand(i) != SplatValue)
4197 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4198 /// to an zero vector.
4199 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4200 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4201 SDValue V1 = N->getOperand(0);
4202 SDValue V2 = N->getOperand(1);
4203 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4204 for (unsigned i = 0; i != NumElems; ++i) {
4205 int Idx = N->getMaskElt(i);
4206 if (Idx >= (int)NumElems) {
4207 unsigned Opc = V2.getOpcode();
4208 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4210 if (Opc != ISD::BUILD_VECTOR ||
4211 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4213 } else if (Idx >= 0) {
4214 unsigned Opc = V1.getOpcode();
4215 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4217 if (Opc != ISD::BUILD_VECTOR ||
4218 !X86::isZeroNode(V1.getOperand(Idx)))
4225 /// getZeroVector - Returns a vector of specified type with all zero elements.
4227 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4228 SelectionDAG &DAG, DebugLoc dl) {
4229 assert(VT.isVector() && "Expected a vector type");
4231 // Always build SSE zero vectors as <4 x i32> bitcasted
4232 // to their dest type. This ensures they get CSE'd.
4234 if (VT.getSizeInBits() == 128) { // SSE
4235 if (HasSSE2) { // SSE2
4236 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4237 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4239 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4240 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4242 } else if (VT.getSizeInBits() == 256) { // AVX
4243 if (HasAVX2) { // AVX2
4244 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4245 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4246 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4248 // 256-bit logic and arithmetic instructions in AVX are all
4249 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4250 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4251 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4255 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4258 /// getOnesVector - Returns a vector of specified type with all bits set.
4259 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4260 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4261 /// Then bitcast to their original type, ensuring they get CSE'd.
4262 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4264 assert(VT.isVector() && "Expected a vector type");
4265 assert((VT.is128BitVector() || VT.is256BitVector())
4266 && "Expected a 128-bit or 256-bit vector type");
4268 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4270 if (VT.getSizeInBits() == 256) {
4271 if (HasAVX2) { // AVX2
4272 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4273 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4275 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4276 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4277 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4278 Vec = Insert128BitVector(InsV, Vec,
4279 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4282 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4285 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4288 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4289 /// that point to V2 points to its first element.
4290 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4291 EVT VT = SVOp->getValueType(0);
4292 unsigned NumElems = VT.getVectorNumElements();
4294 bool Changed = false;
4295 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4297 for (unsigned i = 0; i != NumElems; ++i) {
4298 if (MaskVec[i] > (int)NumElems) {
4299 MaskVec[i] = NumElems;
4304 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4305 SVOp->getOperand(1), &MaskVec[0]);
4306 return SDValue(SVOp, 0);
4309 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4310 /// operation of specified width.
4311 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4313 unsigned NumElems = VT.getVectorNumElements();
4314 SmallVector<int, 8> Mask;
4315 Mask.push_back(NumElems);
4316 for (unsigned i = 1; i != NumElems; ++i)
4318 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4321 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4322 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4324 unsigned NumElems = VT.getVectorNumElements();
4325 SmallVector<int, 8> Mask;
4326 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4328 Mask.push_back(i + NumElems);
4330 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4333 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4334 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4336 unsigned NumElems = VT.getVectorNumElements();
4337 unsigned Half = NumElems/2;
4338 SmallVector<int, 8> Mask;
4339 for (unsigned i = 0; i != Half; ++i) {
4340 Mask.push_back(i + Half);
4341 Mask.push_back(i + NumElems + Half);
4343 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4346 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4347 // a generic shuffle instruction because the target has no such instructions.
4348 // Generate shuffles which repeat i16 and i8 several times until they can be
4349 // represented by v4f32 and then be manipulated by target suported shuffles.
4350 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4351 EVT VT = V.getValueType();
4352 int NumElems = VT.getVectorNumElements();
4353 DebugLoc dl = V.getDebugLoc();
4355 while (NumElems > 4) {
4356 if (EltNo < NumElems/2) {
4357 V = getUnpackl(DAG, dl, VT, V, V);
4359 V = getUnpackh(DAG, dl, VT, V, V);
4360 EltNo -= NumElems/2;
4367 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4368 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4369 EVT VT = V.getValueType();
4370 DebugLoc dl = V.getDebugLoc();
4371 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4372 && "Vector size not supported");
4374 if (VT.getSizeInBits() == 128) {
4375 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4376 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4377 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4380 // To use VPERMILPS to splat scalars, the second half of indicies must
4381 // refer to the higher part, which is a duplication of the lower one,
4382 // because VPERMILPS can only handle in-lane permutations.
4383 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4384 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4386 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4387 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4391 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4394 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4395 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4396 EVT SrcVT = SV->getValueType(0);
4397 SDValue V1 = SV->getOperand(0);
4398 DebugLoc dl = SV->getDebugLoc();
4400 int EltNo = SV->getSplatIndex();
4401 int NumElems = SrcVT.getVectorNumElements();
4402 unsigned Size = SrcVT.getSizeInBits();
4404 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4405 "Unknown how to promote splat for type");
4407 // Extract the 128-bit part containing the splat element and update
4408 // the splat element index when it refers to the higher register.
4410 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4411 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4413 EltNo -= NumElems/2;
4416 // All i16 and i8 vector types can't be used directly by a generic shuffle
4417 // instruction because the target has no such instruction. Generate shuffles
4418 // which repeat i16 and i8 several times until they fit in i32, and then can
4419 // be manipulated by target suported shuffles.
4420 EVT EltVT = SrcVT.getVectorElementType();
4421 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4422 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4424 // Recreate the 256-bit vector and place the same 128-bit vector
4425 // into the low and high part. This is necessary because we want
4426 // to use VPERM* to shuffle the vectors
4428 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4429 DAG.getConstant(0, MVT::i32), DAG, dl);
4430 V1 = Insert128BitVector(InsV, V1,
4431 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4434 return getLegalSplat(DAG, V1, EltNo);
4437 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4438 /// vector of zero or undef vector. This produces a shuffle where the low
4439 /// element of V2 is swizzled into the zero/undef vector, landing at element
4440 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4441 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4443 const X86Subtarget *Subtarget,
4444 SelectionDAG &DAG) {
4445 EVT VT = V2.getValueType();
4447 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4448 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4449 unsigned NumElems = VT.getVectorNumElements();
4450 SmallVector<int, 16> MaskVec;
4451 for (unsigned i = 0; i != NumElems; ++i)
4452 // If this is the insertion idx, put the low elt of V2 here.
4453 MaskVec.push_back(i == Idx ? NumElems : i);
4454 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4457 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4458 /// element of the result of the vector shuffle.
4459 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4462 return SDValue(); // Limit search depth.
4464 SDValue V = SDValue(N, 0);
4465 EVT VT = V.getValueType();
4466 unsigned Opcode = V.getOpcode();
4468 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4469 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4470 Index = SV->getMaskElt(Index);
4473 return DAG.getUNDEF(VT.getVectorElementType());
4475 int NumElems = VT.getVectorNumElements();
4476 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4477 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4480 // Recurse into target specific vector shuffles to find scalars.
4481 if (isTargetShuffle(Opcode)) {
4482 int NumElems = VT.getVectorNumElements();
4483 SmallVector<unsigned, 16> ShuffleMask;
4488 ImmN = N->getOperand(N->getNumOperands()-1);
4489 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4492 case X86ISD::UNPCKH:
4493 DecodeUNPCKHMask(VT, ShuffleMask);
4495 case X86ISD::UNPCKL:
4496 DecodeUNPCKLMask(VT, ShuffleMask);
4498 case X86ISD::MOVHLPS:
4499 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4501 case X86ISD::MOVLHPS:
4502 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4504 case X86ISD::PSHUFD:
4505 ImmN = N->getOperand(N->getNumOperands()-1);
4506 DecodePSHUFMask(NumElems,
4507 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4510 case X86ISD::PSHUFHW:
4511 ImmN = N->getOperand(N->getNumOperands()-1);
4512 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4515 case X86ISD::PSHUFLW:
4516 ImmN = N->getOperand(N->getNumOperands()-1);
4517 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4521 case X86ISD::MOVSD: {
4522 // The index 0 always comes from the first element of the second source,
4523 // this is why MOVSS and MOVSD are used in the first place. The other
4524 // elements come from the other positions of the first source vector.
4525 unsigned OpNum = (Index == 0) ? 1 : 0;
4526 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4529 case X86ISD::VPERMILP:
4530 ImmN = N->getOperand(N->getNumOperands()-1);
4531 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4534 case X86ISD::VPERM2X128:
4535 ImmN = N->getOperand(N->getNumOperands()-1);
4536 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4539 case X86ISD::MOVDDUP:
4540 case X86ISD::MOVLHPD:
4541 case X86ISD::MOVLPD:
4542 case X86ISD::MOVLPS:
4543 case X86ISD::MOVSHDUP:
4544 case X86ISD::MOVSLDUP:
4545 case X86ISD::PALIGN:
4546 return SDValue(); // Not yet implemented.
4548 assert(0 && "unknown target shuffle node");
4552 Index = ShuffleMask[Index];
4554 return DAG.getUNDEF(VT.getVectorElementType());
4556 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4557 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4561 // Actual nodes that may contain scalar elements
4562 if (Opcode == ISD::BITCAST) {
4563 V = V.getOperand(0);
4564 EVT SrcVT = V.getValueType();
4565 unsigned NumElems = VT.getVectorNumElements();
4567 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4571 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4572 return (Index == 0) ? V.getOperand(0)
4573 : DAG.getUNDEF(VT.getVectorElementType());
4575 if (V.getOpcode() == ISD::BUILD_VECTOR)
4576 return V.getOperand(Index);
4581 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4582 /// shuffle operation which come from a consecutively from a zero. The
4583 /// search can start in two different directions, from left or right.
4585 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4586 bool ZerosFromLeft, SelectionDAG &DAG) {
4589 while (i < NumElems) {
4590 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4591 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4592 if (!(Elt.getNode() &&
4593 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4601 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4602 /// MaskE correspond consecutively to elements from one of the vector operands,
4603 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4605 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4606 int OpIdx, int NumElems, unsigned &OpNum) {
4607 bool SeenV1 = false;
4608 bool SeenV2 = false;
4610 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4611 int Idx = SVOp->getMaskElt(i);
4612 // Ignore undef indicies
4621 // Only accept consecutive elements from the same vector
4622 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4626 OpNum = SeenV1 ? 0 : 1;
4630 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4631 /// logical left shift of a vector.
4632 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4634 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4635 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4636 false /* check zeros from right */, DAG);
4642 // Considering the elements in the mask that are not consecutive zeros,
4643 // check if they consecutively come from only one of the source vectors.
4645 // V1 = {X, A, B, C} 0
4647 // vector_shuffle V1, V2 <1, 2, 3, X>
4649 if (!isShuffleMaskConsecutive(SVOp,
4650 0, // Mask Start Index
4651 NumElems-NumZeros-1, // Mask End Index
4652 NumZeros, // Where to start looking in the src vector
4653 NumElems, // Number of elements in vector
4654 OpSrc)) // Which source operand ?
4659 ShVal = SVOp->getOperand(OpSrc);
4663 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4664 /// logical left shift of a vector.
4665 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4666 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4667 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4668 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4669 true /* check zeros from left */, DAG);
4675 // Considering the elements in the mask that are not consecutive zeros,
4676 // check if they consecutively come from only one of the source vectors.
4678 // 0 { A, B, X, X } = V2
4680 // vector_shuffle V1, V2 <X, X, 4, 5>
4682 if (!isShuffleMaskConsecutive(SVOp,
4683 NumZeros, // Mask Start Index
4684 NumElems-1, // Mask End Index
4685 0, // Where to start looking in the src vector
4686 NumElems, // Number of elements in vector
4687 OpSrc)) // Which source operand ?
4692 ShVal = SVOp->getOperand(OpSrc);
4696 /// isVectorShift - Returns true if the shuffle can be implemented as a
4697 /// logical left or right shift of a vector.
4698 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4699 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4700 // Although the logic below support any bitwidth size, there are no
4701 // shift instructions which handle more than 128-bit vectors.
4702 if (SVOp->getValueType(0).getSizeInBits() > 128)
4705 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4706 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4712 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4714 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4715 unsigned NumNonZero, unsigned NumZero,
4717 const TargetLowering &TLI) {
4721 DebugLoc dl = Op.getDebugLoc();
4724 for (unsigned i = 0; i < 16; ++i) {
4725 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4726 if (ThisIsNonZero && First) {
4728 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4731 V = DAG.getUNDEF(MVT::v8i16);
4736 SDValue ThisElt(0, 0), LastElt(0, 0);
4737 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4738 if (LastIsNonZero) {
4739 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4740 MVT::i16, Op.getOperand(i-1));
4742 if (ThisIsNonZero) {
4743 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4744 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4745 ThisElt, DAG.getConstant(8, MVT::i8));
4747 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4751 if (ThisElt.getNode())
4752 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4753 DAG.getIntPtrConstant(i/2));
4757 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4760 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4762 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4763 unsigned NumNonZero, unsigned NumZero,
4765 const TargetLowering &TLI) {
4769 DebugLoc dl = Op.getDebugLoc();
4772 for (unsigned i = 0; i < 8; ++i) {
4773 bool isNonZero = (NonZeros & (1 << i)) != 0;
4777 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4780 V = DAG.getUNDEF(MVT::v8i16);
4783 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4784 MVT::v8i16, V, Op.getOperand(i),
4785 DAG.getIntPtrConstant(i));
4792 /// getVShift - Return a vector logical shift node.
4794 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4795 unsigned NumBits, SelectionDAG &DAG,
4796 const TargetLowering &TLI, DebugLoc dl) {
4797 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4798 EVT ShVT = MVT::v2i64;
4799 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4800 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4801 return DAG.getNode(ISD::BITCAST, dl, VT,
4802 DAG.getNode(Opc, dl, ShVT, SrcOp,
4803 DAG.getConstant(NumBits,
4804 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4808 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4809 SelectionDAG &DAG) const {
4811 // Check if the scalar load can be widened into a vector load. And if
4812 // the address is "base + cst" see if the cst can be "absorbed" into
4813 // the shuffle mask.
4814 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4815 SDValue Ptr = LD->getBasePtr();
4816 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4818 EVT PVT = LD->getValueType(0);
4819 if (PVT != MVT::i32 && PVT != MVT::f32)
4824 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4825 FI = FINode->getIndex();
4827 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4828 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4829 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4830 Offset = Ptr.getConstantOperandVal(1);
4831 Ptr = Ptr.getOperand(0);
4836 // FIXME: 256-bit vector instructions don't require a strict alignment,
4837 // improve this code to support it better.
4838 unsigned RequiredAlign = VT.getSizeInBits()/8;
4839 SDValue Chain = LD->getChain();
4840 // Make sure the stack object alignment is at least 16 or 32.
4841 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4842 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4843 if (MFI->isFixedObjectIndex(FI)) {
4844 // Can't change the alignment. FIXME: It's possible to compute
4845 // the exact stack offset and reference FI + adjust offset instead.
4846 // If someone *really* cares about this. That's the way to implement it.
4849 MFI->setObjectAlignment(FI, RequiredAlign);
4853 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4854 // Ptr + (Offset & ~15).
4857 if ((Offset % RequiredAlign) & 3)
4859 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4861 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4862 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4864 int EltNo = (Offset - StartOffset) >> 2;
4865 int NumElems = VT.getVectorNumElements();
4867 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4868 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4869 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4870 LD->getPointerInfo().getWithOffset(StartOffset),
4871 false, false, false, 0);
4873 // Canonicalize it to a v4i32 or v8i32 shuffle.
4874 SmallVector<int, 8> Mask;
4875 for (int i = 0; i < NumElems; ++i)
4876 Mask.push_back(EltNo);
4878 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4879 return DAG.getNode(ISD::BITCAST, dl, NVT,
4880 DAG.getVectorShuffle(CanonVT, dl, V1,
4881 DAG.getUNDEF(CanonVT),&Mask[0]));
4887 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4888 /// vector of type 'VT', see if the elements can be replaced by a single large
4889 /// load which has the same value as a build_vector whose operands are 'elts'.
4891 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4893 /// FIXME: we'd also like to handle the case where the last elements are zero
4894 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4895 /// There's even a handy isZeroNode for that purpose.
4896 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4897 DebugLoc &DL, SelectionDAG &DAG) {
4898 EVT EltVT = VT.getVectorElementType();
4899 unsigned NumElems = Elts.size();
4901 LoadSDNode *LDBase = NULL;
4902 unsigned LastLoadedElt = -1U;
4904 // For each element in the initializer, see if we've found a load or an undef.
4905 // If we don't find an initial load element, or later load elements are
4906 // non-consecutive, bail out.
4907 for (unsigned i = 0; i < NumElems; ++i) {
4908 SDValue Elt = Elts[i];
4910 if (!Elt.getNode() ||
4911 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4914 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4916 LDBase = cast<LoadSDNode>(Elt.getNode());
4920 if (Elt.getOpcode() == ISD::UNDEF)
4923 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4924 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4929 // If we have found an entire vector of loads and undefs, then return a large
4930 // load of the entire vector width starting at the base pointer. If we found
4931 // consecutive loads for the low half, generate a vzext_load node.
4932 if (LastLoadedElt == NumElems - 1) {
4933 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4934 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4935 LDBase->getPointerInfo(),
4936 LDBase->isVolatile(), LDBase->isNonTemporal(),
4937 LDBase->isInvariant(), 0);
4938 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4939 LDBase->getPointerInfo(),
4940 LDBase->isVolatile(), LDBase->isNonTemporal(),
4941 LDBase->isInvariant(), LDBase->getAlignment());
4942 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4943 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4944 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4945 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4947 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4948 LDBase->getPointerInfo(),
4949 LDBase->getAlignment(),
4950 false/*isVolatile*/, true/*ReadMem*/,
4952 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4957 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4958 /// a vbroadcast node. We support two patterns:
4959 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4960 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4962 /// The scalar load node is returned when a pattern is found,
4963 /// or SDValue() otherwise.
4964 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4965 if (!Subtarget->hasAVX())
4968 EVT VT = Op.getValueType();
4971 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4972 V = V.getOperand(0);
4974 //A suspected load to be broadcasted.
4977 switch (V.getOpcode()) {
4979 // Unknown pattern found.
4982 case ISD::BUILD_VECTOR: {
4983 // The BUILD_VECTOR node must be a splat.
4984 if (!isSplatVector(V.getNode()))
4987 Ld = V.getOperand(0);
4989 // The suspected load node has several users. Make sure that all
4990 // of its users are from the BUILD_VECTOR node.
4991 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4996 case ISD::VECTOR_SHUFFLE: {
4997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4999 // Shuffles must have a splat mask where the first element is
5001 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5004 SDValue Sc = Op.getOperand(0);
5005 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
5008 Ld = Sc.getOperand(0);
5010 // The scalar_to_vector node and the suspected
5011 // load node must have exactly one user.
5012 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5018 // The scalar source must be a normal load.
5019 if (!ISD::isNormalLoad(Ld.getNode()))
5022 bool Is256 = VT.getSizeInBits() == 256;
5023 bool Is128 = VT.getSizeInBits() == 128;
5024 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5026 // VBroadcast to YMM
5027 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5030 // VBroadcast to XMM
5031 if (Is128 && (ScalarSize == 32))
5034 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5035 // double since there is vbroadcastsd xmm
5036 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5037 // VBroadcast to YMM
5038 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5041 // VBroadcast to XMM
5042 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5046 // Unsupported broadcast.
5051 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5052 DebugLoc dl = Op.getDebugLoc();
5054 EVT VT = Op.getValueType();
5055 EVT ExtVT = VT.getVectorElementType();
5056 unsigned NumElems = Op.getNumOperands();
5058 // Vectors containing all zeros can be matched by pxor and xorps later
5059 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5060 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5061 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5062 if (Op.getValueType() == MVT::v4i32 ||
5063 Op.getValueType() == MVT::v8i32)
5066 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(),
5067 Subtarget->hasAVX2(), DAG, dl);
5070 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5071 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5072 // vpcmpeqd on 256-bit vectors.
5073 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5074 if (Op.getValueType() == MVT::v4i32 ||
5075 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5078 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5081 SDValue LD = isVectorBroadcast(Op, Subtarget);
5083 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5085 unsigned EVTBits = ExtVT.getSizeInBits();
5087 unsigned NumZero = 0;
5088 unsigned NumNonZero = 0;
5089 unsigned NonZeros = 0;
5090 bool IsAllConstants = true;
5091 SmallSet<SDValue, 8> Values;
5092 for (unsigned i = 0; i < NumElems; ++i) {
5093 SDValue Elt = Op.getOperand(i);
5094 if (Elt.getOpcode() == ISD::UNDEF)
5097 if (Elt.getOpcode() != ISD::Constant &&
5098 Elt.getOpcode() != ISD::ConstantFP)
5099 IsAllConstants = false;
5100 if (X86::isZeroNode(Elt))
5103 NonZeros |= (1 << i);
5108 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5109 if (NumNonZero == 0)
5110 return DAG.getUNDEF(VT);
5112 // Special case for single non-zero, non-undef, element.
5113 if (NumNonZero == 1) {
5114 unsigned Idx = CountTrailingZeros_32(NonZeros);
5115 SDValue Item = Op.getOperand(Idx);
5117 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5118 // the value are obviously zero, truncate the value to i32 and do the
5119 // insertion that way. Only do this if the value is non-constant or if the
5120 // value is a constant being inserted into element 0. It is cheaper to do
5121 // a constant pool load than it is to do a movd + shuffle.
5122 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5123 (!IsAllConstants || Idx == 0)) {
5124 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5126 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5127 EVT VecVT = MVT::v4i32;
5128 unsigned VecElts = 4;
5130 // Truncate the value (which may itself be a constant) to i32, and
5131 // convert it to a vector with movd (S2V+shuffle to zero extend).
5132 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5133 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5134 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5136 // Now we have our 32-bit value zero extended in the low element of
5137 // a vector. If Idx != 0, swizzle it into place.
5139 SmallVector<int, 4> Mask;
5140 Mask.push_back(Idx);
5141 for (unsigned i = 1; i != VecElts; ++i)
5143 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5144 DAG.getUNDEF(Item.getValueType()),
5147 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5151 // If we have a constant or non-constant insertion into the low element of
5152 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5153 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5154 // depending on what the source datatype is.
5157 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5159 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5160 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5161 if (VT.getSizeInBits() == 256) {
5162 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5163 Subtarget->hasAVX2(), DAG, dl);
5164 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5165 Item, DAG.getIntPtrConstant(0));
5167 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5168 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5169 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5170 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5173 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5174 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5175 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5176 if (VT.getSizeInBits() == 256) {
5177 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5178 Subtarget->hasAVX2(), DAG, dl);
5179 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5182 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5183 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5185 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5189 // Is it a vector logical left shift?
5190 if (NumElems == 2 && Idx == 1 &&
5191 X86::isZeroNode(Op.getOperand(0)) &&
5192 !X86::isZeroNode(Op.getOperand(1))) {
5193 unsigned NumBits = VT.getSizeInBits();
5194 return getVShift(true, VT,
5195 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5196 VT, Op.getOperand(1)),
5197 NumBits/2, DAG, *this, dl);
5200 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5203 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5204 // is a non-constant being inserted into an element other than the low one,
5205 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5206 // movd/movss) to move this into the low element, then shuffle it into
5208 if (EVTBits == 32) {
5209 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5211 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5212 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5213 SmallVector<int, 8> MaskVec;
5214 for (unsigned i = 0; i < NumElems; i++)
5215 MaskVec.push_back(i == Idx ? 0 : 1);
5216 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5220 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5221 if (Values.size() == 1) {
5222 if (EVTBits == 32) {
5223 // Instead of a shuffle like this:
5224 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5225 // Check if it's possible to issue this instead.
5226 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5227 unsigned Idx = CountTrailingZeros_32(NonZeros);
5228 SDValue Item = Op.getOperand(Idx);
5229 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5230 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5235 // A vector full of immediates; various special cases are already
5236 // handled, so this is best done with a single constant-pool load.
5240 // For AVX-length vectors, build the individual 128-bit pieces and use
5241 // shuffles to put them in place.
5242 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5243 SmallVector<SDValue, 32> V;
5244 for (unsigned i = 0; i < NumElems; ++i)
5245 V.push_back(Op.getOperand(i));
5247 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5249 // Build both the lower and upper subvector.
5250 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5251 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5254 // Recreate the wider vector with the lower and upper part.
5255 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5256 DAG.getConstant(0, MVT::i32), DAG, dl);
5257 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5261 // Let legalizer expand 2-wide build_vectors.
5262 if (EVTBits == 64) {
5263 if (NumNonZero == 1) {
5264 // One half is zero or undef.
5265 unsigned Idx = CountTrailingZeros_32(NonZeros);
5266 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5267 Op.getOperand(Idx));
5268 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5273 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5274 if (EVTBits == 8 && NumElems == 16) {
5275 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5277 if (V.getNode()) return V;
5280 if (EVTBits == 16 && NumElems == 8) {
5281 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5283 if (V.getNode()) return V;
5286 // If element VT is == 32 bits, turn it into a number of shuffles.
5287 SmallVector<SDValue, 8> V;
5289 if (NumElems == 4 && NumZero > 0) {
5290 for (unsigned i = 0; i < 4; ++i) {
5291 bool isZero = !(NonZeros & (1 << i));
5293 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5296 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5299 for (unsigned i = 0; i < 2; ++i) {
5300 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5303 V[i] = V[i*2]; // Must be a zero vector.
5306 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5309 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5312 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5317 SmallVector<int, 8> MaskVec;
5318 bool Reverse = (NonZeros & 0x3) == 2;
5319 for (unsigned i = 0; i < 2; ++i)
5320 MaskVec.push_back(Reverse ? 1-i : i);
5321 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5322 for (unsigned i = 0; i < 2; ++i)
5323 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5324 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5327 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5328 // Check for a build vector of consecutive loads.
5329 for (unsigned i = 0; i < NumElems; ++i)
5330 V[i] = Op.getOperand(i);
5332 // Check for elements which are consecutive loads.
5333 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5337 // For SSE 4.1, use insertps to put the high elements into the low element.
5338 if (getSubtarget()->hasSSE41()) {
5340 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5341 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5343 Result = DAG.getUNDEF(VT);
5345 for (unsigned i = 1; i < NumElems; ++i) {
5346 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5347 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5348 Op.getOperand(i), DAG.getIntPtrConstant(i));
5353 // Otherwise, expand into a number of unpckl*, start by extending each of
5354 // our (non-undef) elements to the full vector width with the element in the
5355 // bottom slot of the vector (which generates no code for SSE).
5356 for (unsigned i = 0; i < NumElems; ++i) {
5357 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5358 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5360 V[i] = DAG.getUNDEF(VT);
5363 // Next, we iteratively mix elements, e.g. for v4f32:
5364 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5365 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5366 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5367 unsigned EltStride = NumElems >> 1;
5368 while (EltStride != 0) {
5369 for (unsigned i = 0; i < EltStride; ++i) {
5370 // If V[i+EltStride] is undef and this is the first round of mixing,
5371 // then it is safe to just drop this shuffle: V[i] is already in the
5372 // right place, the one element (since it's the first round) being
5373 // inserted as undef can be dropped. This isn't safe for successive
5374 // rounds because they will permute elements within both vectors.
5375 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5376 EltStride == NumElems/2)
5379 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5388 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5389 // them in a MMX register. This is better than doing a stack convert.
5390 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5391 DebugLoc dl = Op.getDebugLoc();
5392 EVT ResVT = Op.getValueType();
5394 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5395 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5397 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5398 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5399 InVec = Op.getOperand(1);
5400 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5401 unsigned NumElts = ResVT.getVectorNumElements();
5402 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5403 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5404 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5406 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5407 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5408 Mask[0] = 0; Mask[1] = 2;
5409 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5411 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5414 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5415 // to create 256-bit vectors from two other 128-bit ones.
5416 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5417 DebugLoc dl = Op.getDebugLoc();
5418 EVT ResVT = Op.getValueType();
5420 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5422 SDValue V1 = Op.getOperand(0);
5423 SDValue V2 = Op.getOperand(1);
5424 unsigned NumElems = ResVT.getVectorNumElements();
5426 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5427 DAG.getConstant(0, MVT::i32), DAG, dl);
5428 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5433 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5434 EVT ResVT = Op.getValueType();
5436 assert(Op.getNumOperands() == 2);
5437 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5438 "Unsupported CONCAT_VECTORS for value type");
5440 // We support concatenate two MMX registers and place them in a MMX register.
5441 // This is better than doing a stack convert.
5442 if (ResVT.is128BitVector())
5443 return LowerMMXCONCAT_VECTORS(Op, DAG);
5445 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5446 // from two other 128-bit ones.
5447 return LowerAVXCONCAT_VECTORS(Op, DAG);
5450 // v8i16 shuffles - Prefer shuffles in the following order:
5451 // 1. [all] pshuflw, pshufhw, optional move
5452 // 2. [ssse3] 1 x pshufb
5453 // 3. [ssse3] 2 x pshufb + 1 x por
5454 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5456 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5457 SelectionDAG &DAG) const {
5458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5459 SDValue V1 = SVOp->getOperand(0);
5460 SDValue V2 = SVOp->getOperand(1);
5461 DebugLoc dl = SVOp->getDebugLoc();
5462 SmallVector<int, 8> MaskVals;
5464 // Determine if more than 1 of the words in each of the low and high quadwords
5465 // of the result come from the same quadword of one of the two inputs. Undef
5466 // mask values count as coming from any quadword, for better codegen.
5467 unsigned LoQuad[] = { 0, 0, 0, 0 };
5468 unsigned HiQuad[] = { 0, 0, 0, 0 };
5469 BitVector InputQuads(4);
5470 for (unsigned i = 0; i < 8; ++i) {
5471 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5472 int EltIdx = SVOp->getMaskElt(i);
5473 MaskVals.push_back(EltIdx);
5482 InputQuads.set(EltIdx / 4);
5485 int BestLoQuad = -1;
5486 unsigned MaxQuad = 1;
5487 for (unsigned i = 0; i < 4; ++i) {
5488 if (LoQuad[i] > MaxQuad) {
5490 MaxQuad = LoQuad[i];
5494 int BestHiQuad = -1;
5496 for (unsigned i = 0; i < 4; ++i) {
5497 if (HiQuad[i] > MaxQuad) {
5499 MaxQuad = HiQuad[i];
5503 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5504 // of the two input vectors, shuffle them into one input vector so only a
5505 // single pshufb instruction is necessary. If There are more than 2 input
5506 // quads, disable the next transformation since it does not help SSSE3.
5507 bool V1Used = InputQuads[0] || InputQuads[1];
5508 bool V2Used = InputQuads[2] || InputQuads[3];
5509 if (Subtarget->hasSSSE3()) {
5510 if (InputQuads.count() == 2 && V1Used && V2Used) {
5511 BestLoQuad = InputQuads.find_first();
5512 BestHiQuad = InputQuads.find_next(BestLoQuad);
5514 if (InputQuads.count() > 2) {
5520 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5521 // the shuffle mask. If a quad is scored as -1, that means that it contains
5522 // words from all 4 input quadwords.
5524 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5525 SmallVector<int, 8> MaskV;
5526 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5527 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5528 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5529 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5530 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5531 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5533 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5534 // source words for the shuffle, to aid later transformations.
5535 bool AllWordsInNewV = true;
5536 bool InOrder[2] = { true, true };
5537 for (unsigned i = 0; i != 8; ++i) {
5538 int idx = MaskVals[i];
5540 InOrder[i/4] = false;
5541 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5543 AllWordsInNewV = false;
5547 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5548 if (AllWordsInNewV) {
5549 for (int i = 0; i != 8; ++i) {
5550 int idx = MaskVals[i];
5553 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5554 if ((idx != i) && idx < 4)
5556 if ((idx != i) && idx > 3)
5565 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5566 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5567 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5568 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5569 unsigned TargetMask = 0;
5570 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5571 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5572 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5573 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5574 V1 = NewV.getOperand(0);
5575 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5579 // If we have SSSE3, and all words of the result are from 1 input vector,
5580 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5581 // is present, fall back to case 4.
5582 if (Subtarget->hasSSSE3()) {
5583 SmallVector<SDValue,16> pshufbMask;
5585 // If we have elements from both input vectors, set the high bit of the
5586 // shuffle mask element to zero out elements that come from V2 in the V1
5587 // mask, and elements that come from V1 in the V2 mask, so that the two
5588 // results can be OR'd together.
5589 bool TwoInputs = V1Used && V2Used;
5590 for (unsigned i = 0; i != 8; ++i) {
5591 int EltIdx = MaskVals[i] * 2;
5592 if (TwoInputs && (EltIdx >= 16)) {
5593 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5594 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5597 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5598 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5600 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5601 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5602 DAG.getNode(ISD::BUILD_VECTOR, dl,
5603 MVT::v16i8, &pshufbMask[0], 16));
5605 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5607 // Calculate the shuffle mask for the second input, shuffle it, and
5608 // OR it with the first shuffled input.
5610 for (unsigned i = 0; i != 8; ++i) {
5611 int EltIdx = MaskVals[i] * 2;
5613 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5614 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5617 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5618 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5620 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5621 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5622 DAG.getNode(ISD::BUILD_VECTOR, dl,
5623 MVT::v16i8, &pshufbMask[0], 16));
5624 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5625 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5628 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5629 // and update MaskVals with new element order.
5630 BitVector InOrder(8);
5631 if (BestLoQuad >= 0) {
5632 SmallVector<int, 8> MaskV;
5633 for (int i = 0; i != 4; ++i) {
5634 int idx = MaskVals[i];
5636 MaskV.push_back(-1);
5638 } else if ((idx / 4) == BestLoQuad) {
5639 MaskV.push_back(idx & 3);
5642 MaskV.push_back(-1);
5645 for (unsigned i = 4; i != 8; ++i)
5647 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5650 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5651 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5653 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5657 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5658 // and update MaskVals with the new element order.
5659 if (BestHiQuad >= 0) {
5660 SmallVector<int, 8> MaskV;
5661 for (unsigned i = 0; i != 4; ++i)
5663 for (unsigned i = 4; i != 8; ++i) {
5664 int idx = MaskVals[i];
5666 MaskV.push_back(-1);
5668 } else if ((idx / 4) == BestHiQuad) {
5669 MaskV.push_back((idx & 3) + 4);
5672 MaskV.push_back(-1);
5675 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5678 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5679 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5681 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5685 // In case BestHi & BestLo were both -1, which means each quadword has a word
5686 // from each of the four input quadwords, calculate the InOrder bitvector now
5687 // before falling through to the insert/extract cleanup.
5688 if (BestLoQuad == -1 && BestHiQuad == -1) {
5690 for (int i = 0; i != 8; ++i)
5691 if (MaskVals[i] < 0 || MaskVals[i] == i)
5695 // The other elements are put in the right place using pextrw and pinsrw.
5696 for (unsigned i = 0; i != 8; ++i) {
5699 int EltIdx = MaskVals[i];
5702 SDValue ExtOp = (EltIdx < 8)
5703 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5704 DAG.getIntPtrConstant(EltIdx))
5705 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5706 DAG.getIntPtrConstant(EltIdx - 8));
5707 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5708 DAG.getIntPtrConstant(i));
5713 // v16i8 shuffles - Prefer shuffles in the following order:
5714 // 1. [ssse3] 1 x pshufb
5715 // 2. [ssse3] 2 x pshufb + 1 x por
5716 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5718 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5720 const X86TargetLowering &TLI) {
5721 SDValue V1 = SVOp->getOperand(0);
5722 SDValue V2 = SVOp->getOperand(1);
5723 DebugLoc dl = SVOp->getDebugLoc();
5724 ArrayRef<int> MaskVals = SVOp->getMask();
5726 // If we have SSSE3, case 1 is generated when all result bytes come from
5727 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5728 // present, fall back to case 3.
5729 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5732 for (unsigned i = 0; i < 16; ++i) {
5733 int EltIdx = MaskVals[i];
5742 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5743 if (TLI.getSubtarget()->hasSSSE3()) {
5744 SmallVector<SDValue,16> pshufbMask;
5746 // If all result elements are from one input vector, then only translate
5747 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5749 // Otherwise, we have elements from both input vectors, and must zero out
5750 // elements that come from V2 in the first mask, and V1 in the second mask
5751 // so that we can OR them together.
5752 bool TwoInputs = !(V1Only || V2Only);
5753 for (unsigned i = 0; i != 16; ++i) {
5754 int EltIdx = MaskVals[i];
5755 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5756 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5759 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5761 // If all the elements are from V2, assign it to V1 and return after
5762 // building the first pshufb.
5765 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5766 DAG.getNode(ISD::BUILD_VECTOR, dl,
5767 MVT::v16i8, &pshufbMask[0], 16));
5771 // Calculate the shuffle mask for the second input, shuffle it, and
5772 // OR it with the first shuffled input.
5774 for (unsigned i = 0; i != 16; ++i) {
5775 int EltIdx = MaskVals[i];
5777 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5780 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5782 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5783 DAG.getNode(ISD::BUILD_VECTOR, dl,
5784 MVT::v16i8, &pshufbMask[0], 16));
5785 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5788 // No SSSE3 - Calculate in place words and then fix all out of place words
5789 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5790 // the 16 different words that comprise the two doublequadword input vectors.
5791 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5792 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5793 SDValue NewV = V2Only ? V2 : V1;
5794 for (int i = 0; i != 8; ++i) {
5795 int Elt0 = MaskVals[i*2];
5796 int Elt1 = MaskVals[i*2+1];
5798 // This word of the result is all undef, skip it.
5799 if (Elt0 < 0 && Elt1 < 0)
5802 // This word of the result is already in the correct place, skip it.
5803 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5805 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5808 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5809 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5812 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5813 // using a single extract together, load it and store it.
5814 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5815 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5816 DAG.getIntPtrConstant(Elt1 / 2));
5817 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5818 DAG.getIntPtrConstant(i));
5822 // If Elt1 is defined, extract it from the appropriate source. If the
5823 // source byte is not also odd, shift the extracted word left 8 bits
5824 // otherwise clear the bottom 8 bits if we need to do an or.
5826 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5827 DAG.getIntPtrConstant(Elt1 / 2));
5828 if ((Elt1 & 1) == 0)
5829 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5831 TLI.getShiftAmountTy(InsElt.getValueType())));
5833 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5834 DAG.getConstant(0xFF00, MVT::i16));
5836 // If Elt0 is defined, extract it from the appropriate source. If the
5837 // source byte is not also even, shift the extracted word right 8 bits. If
5838 // Elt1 was also defined, OR the extracted values together before
5839 // inserting them in the result.
5841 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5842 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5843 if ((Elt0 & 1) != 0)
5844 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5846 TLI.getShiftAmountTy(InsElt0.getValueType())));
5848 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5849 DAG.getConstant(0x00FF, MVT::i16));
5850 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5853 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5854 DAG.getIntPtrConstant(i));
5856 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5859 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5860 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5861 /// done when every pair / quad of shuffle mask elements point to elements in
5862 /// the right sequence. e.g.
5863 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5865 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5866 SelectionDAG &DAG, DebugLoc dl) {
5867 EVT VT = SVOp->getValueType(0);
5868 SDValue V1 = SVOp->getOperand(0);
5869 SDValue V2 = SVOp->getOperand(1);
5870 unsigned NumElems = VT.getVectorNumElements();
5871 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5873 switch (VT.getSimpleVT().SimpleTy) {
5874 default: assert(false && "Unexpected!");
5875 case MVT::v4f32: NewVT = MVT::v2f64; break;
5876 case MVT::v4i32: NewVT = MVT::v2i64; break;
5877 case MVT::v8i16: NewVT = MVT::v4i32; break;
5878 case MVT::v16i8: NewVT = MVT::v4i32; break;
5881 int Scale = NumElems / NewWidth;
5882 SmallVector<int, 8> MaskVec;
5883 for (unsigned i = 0; i < NumElems; i += Scale) {
5885 for (int j = 0; j < Scale; ++j) {
5886 int EltIdx = SVOp->getMaskElt(i+j);
5890 StartIdx = EltIdx - (EltIdx % Scale);
5891 if (EltIdx != StartIdx + j)
5895 MaskVec.push_back(-1);
5897 MaskVec.push_back(StartIdx / Scale);
5900 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5901 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5902 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5905 /// getVZextMovL - Return a zero-extending vector move low node.
5907 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5908 SDValue SrcOp, SelectionDAG &DAG,
5909 const X86Subtarget *Subtarget, DebugLoc dl) {
5910 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5911 LoadSDNode *LD = NULL;
5912 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5913 LD = dyn_cast<LoadSDNode>(SrcOp);
5915 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5917 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5918 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5919 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5920 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5921 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5923 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5924 return DAG.getNode(ISD::BITCAST, dl, VT,
5925 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5926 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5934 return DAG.getNode(ISD::BITCAST, dl, VT,
5935 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5936 DAG.getNode(ISD::BITCAST, dl,
5940 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5941 /// which could not be matched by any known target speficic shuffle
5943 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5944 EVT VT = SVOp->getValueType(0);
5946 unsigned NumElems = VT.getVectorNumElements();
5947 unsigned NumLaneElems = NumElems / 2;
5949 int MinRange[2][2] = { { static_cast<int>(NumElems),
5950 static_cast<int>(NumElems) },
5951 { static_cast<int>(NumElems),
5952 static_cast<int>(NumElems) } };
5953 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5955 // Collect used ranges for each source in each lane
5956 for (unsigned l = 0; l < 2; ++l) {
5957 unsigned LaneStart = l*NumLaneElems;
5958 for (unsigned i = 0; i != NumLaneElems; ++i) {
5959 int Idx = SVOp->getMaskElt(i+LaneStart);
5964 if (Idx >= (int)NumElems) {
5969 if (Idx > MaxRange[l][Input])
5970 MaxRange[l][Input] = Idx;
5971 if (Idx < MinRange[l][Input])
5972 MinRange[l][Input] = Idx;
5976 // Make sure each range is 128-bits
5977 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5978 for (unsigned l = 0; l < 2; ++l) {
5979 for (unsigned Input = 0; Input < 2; ++Input) {
5980 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5983 if (MinRange[l][Input] >= 0 && MinRange[l][Input] < (int)NumLaneElems)
5984 ExtractIdx[l][Input] = 0;
5985 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5986 MinRange[l][Input] < (int)NumElems)
5987 ExtractIdx[l][Input] = NumLaneElems;
5993 DebugLoc dl = SVOp->getDebugLoc();
5994 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5995 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5998 for (unsigned l = 0; l < 2; ++l) {
5999 for (unsigned Input = 0; Input < 2; ++Input) {
6000 if (ExtractIdx[l][Input] >= 0)
6001 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
6002 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
6005 Ops[l][Input] = DAG.getUNDEF(NVT);
6009 // Generate 128-bit shuffles
6010 SmallVector<int, 16> Mask1, Mask2;
6011 for (unsigned i = 0; i != NumLaneElems; ++i) {
6012 int Elt = SVOp->getMaskElt(i);
6013 if (Elt >= (int)NumElems) {
6014 Elt %= NumLaneElems;
6015 Elt += NumLaneElems;
6016 } else if (Elt >= 0) {
6017 Elt %= NumLaneElems;
6019 Mask1.push_back(Elt);
6021 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
6022 int Elt = SVOp->getMaskElt(i);
6023 if (Elt >= (int)NumElems) {
6024 Elt %= NumLaneElems;
6025 Elt += NumLaneElems;
6026 } else if (Elt >= 0) {
6027 Elt %= NumLaneElems;
6029 Mask2.push_back(Elt);
6032 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
6033 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
6035 // Concatenate the result back
6036 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
6037 DAG.getConstant(0, MVT::i32), DAG, dl);
6038 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
6042 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6043 /// 4 elements, and match them with several different shuffle types.
6045 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6046 SDValue V1 = SVOp->getOperand(0);
6047 SDValue V2 = SVOp->getOperand(1);
6048 DebugLoc dl = SVOp->getDebugLoc();
6049 EVT VT = SVOp->getValueType(0);
6051 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6053 SmallVector<std::pair<int, int>, 8> Locs;
6055 SmallVector<int, 8> Mask1(4U, -1);
6056 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6060 for (unsigned i = 0; i != 4; ++i) {
6061 int Idx = PermMask[i];
6063 Locs[i] = std::make_pair(-1, -1);
6065 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6067 Locs[i] = std::make_pair(0, NumLo);
6071 Locs[i] = std::make_pair(1, NumHi);
6073 Mask1[2+NumHi] = Idx;
6079 if (NumLo <= 2 && NumHi <= 2) {
6080 // If no more than two elements come from either vector. This can be
6081 // implemented with two shuffles. First shuffle gather the elements.
6082 // The second shuffle, which takes the first shuffle as both of its
6083 // vector operands, put the elements into the right order.
6084 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6086 SmallVector<int, 8> Mask2(4U, -1);
6088 for (unsigned i = 0; i != 4; ++i) {
6089 if (Locs[i].first == -1)
6092 unsigned Idx = (i < 2) ? 0 : 4;
6093 Idx += Locs[i].first * 2 + Locs[i].second;
6098 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6099 } else if (NumLo == 3 || NumHi == 3) {
6100 // Otherwise, we must have three elements from one vector, call it X, and
6101 // one element from the other, call it Y. First, use a shufps to build an
6102 // intermediate vector with the one element from Y and the element from X
6103 // that will be in the same half in the final destination (the indexes don't
6104 // matter). Then, use a shufps to build the final vector, taking the half
6105 // containing the element from Y from the intermediate, and the other half
6108 // Normalize it so the 3 elements come from V1.
6109 CommuteVectorShuffleMask(PermMask, 4);
6113 // Find the element from V2.
6115 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6116 int Val = PermMask[HiIndex];
6123 Mask1[0] = PermMask[HiIndex];
6125 Mask1[2] = PermMask[HiIndex^1];
6127 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6130 Mask1[0] = PermMask[0];
6131 Mask1[1] = PermMask[1];
6132 Mask1[2] = HiIndex & 1 ? 6 : 4;
6133 Mask1[3] = HiIndex & 1 ? 4 : 6;
6134 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6136 Mask1[0] = HiIndex & 1 ? 2 : 0;
6137 Mask1[1] = HiIndex & 1 ? 0 : 2;
6138 Mask1[2] = PermMask[2];
6139 Mask1[3] = PermMask[3];
6144 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6148 // Break it into (shuffle shuffle_hi, shuffle_lo).
6151 SmallVector<int,8> LoMask(4U, -1);
6152 SmallVector<int,8> HiMask(4U, -1);
6154 SmallVector<int,8> *MaskPtr = &LoMask;
6155 unsigned MaskIdx = 0;
6158 for (unsigned i = 0; i != 4; ++i) {
6165 int Idx = PermMask[i];
6167 Locs[i] = std::make_pair(-1, -1);
6168 } else if (Idx < 4) {
6169 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6170 (*MaskPtr)[LoIdx] = Idx;
6173 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6174 (*MaskPtr)[HiIdx] = Idx;
6179 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6180 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6181 SmallVector<int, 8> MaskOps;
6182 for (unsigned i = 0; i != 4; ++i) {
6183 if (Locs[i].first == -1) {
6184 MaskOps.push_back(-1);
6186 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6187 MaskOps.push_back(Idx);
6190 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6193 static bool MayFoldVectorLoad(SDValue V) {
6194 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6195 V = V.getOperand(0);
6196 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6197 V = V.getOperand(0);
6198 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6199 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6200 // BUILD_VECTOR (load), undef
6201 V = V.getOperand(0);
6207 // FIXME: the version above should always be used. Since there's
6208 // a bug where several vector shuffles can't be folded because the
6209 // DAG is not updated during lowering and a node claims to have two
6210 // uses while it only has one, use this version, and let isel match
6211 // another instruction if the load really happens to have more than
6212 // one use. Remove this version after this bug get fixed.
6213 // rdar://8434668, PR8156
6214 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6215 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6216 V = V.getOperand(0);
6217 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6218 V = V.getOperand(0);
6219 if (ISD::isNormalLoad(V.getNode()))
6224 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6225 /// a vector extract, and if both can be later optimized into a single load.
6226 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6227 /// here because otherwise a target specific shuffle node is going to be
6228 /// emitted for this shuffle, and the optimization not done.
6229 /// FIXME: This is probably not the best approach, but fix the problem
6230 /// until the right path is decided.
6232 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6233 const TargetLowering &TLI) {
6234 EVT VT = V.getValueType();
6235 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6237 // Be sure that the vector shuffle is present in a pattern like this:
6238 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6242 SDNode *N = *V.getNode()->use_begin();
6243 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6246 SDValue EltNo = N->getOperand(1);
6247 if (!isa<ConstantSDNode>(EltNo))
6250 // If the bit convert changed the number of elements, it is unsafe
6251 // to examine the mask.
6252 bool HasShuffleIntoBitcast = false;
6253 if (V.getOpcode() == ISD::BITCAST) {
6254 EVT SrcVT = V.getOperand(0).getValueType();
6255 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6257 V = V.getOperand(0);
6258 HasShuffleIntoBitcast = true;
6261 // Select the input vector, guarding against out of range extract vector.
6262 unsigned NumElems = VT.getVectorNumElements();
6263 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6264 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6265 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6267 // If we are accessing the upper part of a YMM register
6268 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6269 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6270 // because the legalization of N did not happen yet.
6271 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6274 // Skip one more bit_convert if necessary
6275 if (V.getOpcode() == ISD::BITCAST)
6276 V = V.getOperand(0);
6278 if (!ISD::isNormalLoad(V.getNode()))
6281 // Is the original load suitable?
6282 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6284 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6287 if (!HasShuffleIntoBitcast)
6290 // If there's a bitcast before the shuffle, check if the load type and
6291 // alignment is valid.
6292 unsigned Align = LN0->getAlignment();
6294 TLI.getTargetData()->getABITypeAlignment(
6295 VT.getTypeForEVT(*DAG.getContext()));
6297 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6304 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6305 EVT VT = Op.getValueType();
6307 // Canonizalize to v2f64.
6308 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6309 return DAG.getNode(ISD::BITCAST, dl, VT,
6310 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6315 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6317 SDValue V1 = Op.getOperand(0);
6318 SDValue V2 = Op.getOperand(1);
6319 EVT VT = Op.getValueType();
6321 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6323 if (HasSSE2 && VT == MVT::v2f64)
6324 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6326 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6327 return DAG.getNode(ISD::BITCAST, dl, VT,
6328 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6329 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6330 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6334 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6335 SDValue V1 = Op.getOperand(0);
6336 SDValue V2 = Op.getOperand(1);
6337 EVT VT = Op.getValueType();
6339 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6340 "unsupported shuffle type");
6342 if (V2.getOpcode() == ISD::UNDEF)
6346 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6350 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6351 SDValue V1 = Op.getOperand(0);
6352 SDValue V2 = Op.getOperand(1);
6353 EVT VT = Op.getValueType();
6354 unsigned NumElems = VT.getVectorNumElements();
6356 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6357 // operand of these instructions is only memory, so check if there's a
6358 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6360 bool CanFoldLoad = false;
6362 // Trivial case, when V2 comes from a load.
6363 if (MayFoldVectorLoad(V2))
6366 // When V1 is a load, it can be folded later into a store in isel, example:
6367 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6369 // (MOVLPSmr addr:$src1, VR128:$src2)
6370 // So, recognize this potential and also use MOVLPS or MOVLPD
6371 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6376 if (HasSSE2 && NumElems == 2)
6377 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6380 // If we don't care about the second element, procede to use movss.
6381 if (SVOp->getMaskElt(1) != -1)
6382 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6385 // movl and movlp will both match v2i64, but v2i64 is never matched by
6386 // movl earlier because we make it strict to avoid messing with the movlp load
6387 // folding logic (see the code above getMOVLP call). Match it here then,
6388 // this is horrible, but will stay like this until we move all shuffle
6389 // matching to x86 specific nodes. Note that for the 1st condition all
6390 // types are matched with movsd.
6392 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6393 // as to remove this logic from here, as much as possible
6394 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6395 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6396 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6399 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6401 // Invert the operand order and use SHUFPS to match it.
6402 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6403 X86::getShuffleSHUFImmediate(SVOp), DAG);
6407 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6408 const TargetLowering &TLI,
6409 const X86Subtarget *Subtarget) {
6410 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6411 EVT VT = Op.getValueType();
6412 DebugLoc dl = Op.getDebugLoc();
6413 SDValue V1 = Op.getOperand(0);
6414 SDValue V2 = Op.getOperand(1);
6416 if (isZeroShuffle(SVOp))
6417 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6420 // Handle splat operations
6421 if (SVOp->isSplat()) {
6422 unsigned NumElem = VT.getVectorNumElements();
6423 int Size = VT.getSizeInBits();
6424 // Special case, this is the only place now where it's allowed to return
6425 // a vector_shuffle operation without using a target specific node, because
6426 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6427 // this be moved to DAGCombine instead?
6428 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6431 // Use vbroadcast whenever the splat comes from a foldable load
6432 SDValue LD = isVectorBroadcast(Op, Subtarget);
6434 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6436 // Handle splats by matching through known shuffle masks
6437 if ((Size == 128 && NumElem <= 4) ||
6438 (Size == 256 && NumElem < 8))
6441 // All remaning splats are promoted to target supported vector shuffles.
6442 return PromoteSplat(SVOp, DAG);
6445 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6447 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6448 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6449 if (NewOp.getNode())
6450 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6451 } else if ((VT == MVT::v4i32 ||
6452 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6453 // FIXME: Figure out a cleaner way to do this.
6454 // Try to make use of movq to zero out the top part.
6455 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6456 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6457 if (NewOp.getNode()) {
6458 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6459 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6460 DAG, Subtarget, dl);
6462 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6463 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6464 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6465 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6466 DAG, Subtarget, dl);
6473 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6474 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6475 SDValue V1 = Op.getOperand(0);
6476 SDValue V2 = Op.getOperand(1);
6477 EVT VT = Op.getValueType();
6478 DebugLoc dl = Op.getDebugLoc();
6479 unsigned NumElems = VT.getVectorNumElements();
6480 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6481 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6482 bool V1IsSplat = false;
6483 bool V2IsSplat = false;
6484 bool HasSSE2 = Subtarget->hasSSE2();
6485 bool HasAVX = Subtarget->hasAVX();
6486 bool HasAVX2 = Subtarget->hasAVX2();
6487 MachineFunction &MF = DAG.getMachineFunction();
6488 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6490 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6492 if (V1IsUndef && V2IsUndef)
6493 return DAG.getUNDEF(VT);
6495 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6497 // Vector shuffle lowering takes 3 steps:
6499 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6500 // narrowing and commutation of operands should be handled.
6501 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6503 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6504 // so the shuffle can be broken into other shuffles and the legalizer can
6505 // try the lowering again.
6507 // The general idea is that no vector_shuffle operation should be left to
6508 // be matched during isel, all of them must be converted to a target specific
6511 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6512 // narrowing and commutation of operands should be handled. The actual code
6513 // doesn't include all of those, work in progress...
6514 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6515 if (NewOp.getNode())
6518 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6519 // unpckh_undef). Only use pshufd if speed is more important than size.
6520 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6521 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6522 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6523 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6525 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6526 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6527 return getMOVDDup(Op, dl, V1, DAG);
6529 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6530 return getMOVHighToLow(Op, dl, DAG);
6532 // Use to match splats
6533 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6534 (VT == MVT::v2f64 || VT == MVT::v2i64))
6535 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6537 if (X86::isPSHUFDMask(SVOp)) {
6538 // The actual implementation will match the mask in the if above and then
6539 // during isel it can match several different instructions, not only pshufd
6540 // as its name says, sad but true, emulate the behavior for now...
6541 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6542 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6544 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6546 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6547 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6549 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6553 // Check if this can be converted into a logical shift.
6554 bool isLeft = false;
6557 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6558 if (isShift && ShVal.hasOneUse()) {
6559 // If the shifted value has multiple uses, it may be cheaper to use
6560 // v_set0 + movlhps or movhlps, etc.
6561 EVT EltVT = VT.getVectorElementType();
6562 ShAmt *= EltVT.getSizeInBits();
6563 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6566 if (X86::isMOVLMask(SVOp)) {
6567 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6568 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6569 if (!X86::isMOVLPMask(SVOp)) {
6570 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6571 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6573 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6574 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6578 // FIXME: fold these into legal mask.
6579 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6580 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6582 if (X86::isMOVHLPSMask(SVOp))
6583 return getMOVHighToLow(Op, dl, DAG);
6585 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6586 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6588 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6589 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6591 if (X86::isMOVLPMask(SVOp))
6592 return getMOVLP(Op, dl, DAG, HasSSE2);
6594 if (ShouldXformToMOVHLPS(SVOp) ||
6595 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6596 return CommuteVectorShuffle(SVOp, DAG);
6599 // No better options. Use a vshl / vsrl.
6600 EVT EltVT = VT.getVectorElementType();
6601 ShAmt *= EltVT.getSizeInBits();
6602 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6605 bool Commuted = false;
6606 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6607 // 1,1,1,1 -> v8i16 though.
6608 V1IsSplat = isSplatVector(V1.getNode());
6609 V2IsSplat = isSplatVector(V2.getNode());
6611 // Canonicalize the splat or undef, if present, to be on the RHS.
6612 if (V1IsSplat && !V2IsSplat) {
6613 Op = CommuteVectorShuffle(SVOp, DAG);
6614 SVOp = cast<ShuffleVectorSDNode>(Op);
6615 V1 = SVOp->getOperand(0);
6616 V2 = SVOp->getOperand(1);
6617 std::swap(V1IsSplat, V2IsSplat);
6621 ArrayRef<int> M = SVOp->getMask();
6623 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6624 // Shuffling low element of v1 into undef, just return v1.
6627 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6628 // the instruction selector will not match, so get a canonical MOVL with
6629 // swapped operands to undo the commute.
6630 return getMOVL(DAG, dl, VT, V2, V1);
6633 if (isUNPCKLMask(M, VT, HasAVX2))
6634 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6636 if (isUNPCKHMask(M, VT, HasAVX2))
6637 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6640 // Normalize mask so all entries that point to V2 points to its first
6641 // element then try to match unpck{h|l} again. If match, return a
6642 // new vector_shuffle with the corrected mask.
6643 SDValue NewMask = NormalizeMask(SVOp, DAG);
6644 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6645 if (NSVOp != SVOp) {
6646 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6648 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6655 // Commute is back and try unpck* again.
6656 // FIXME: this seems wrong.
6657 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6658 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6660 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6661 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6663 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6664 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6667 // Normalize the node to match x86 shuffle ops if needed
6668 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6669 return CommuteVectorShuffle(SVOp, DAG);
6671 // The checks below are all present in isShuffleMaskLegal, but they are
6672 // inlined here right now to enable us to directly emit target specific
6673 // nodes, and remove one by one until they don't return Op anymore.
6675 if (isPALIGNRMask(M, VT, Subtarget))
6676 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6677 getShufflePALIGNRImmediate(SVOp),
6680 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6681 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6682 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6683 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6686 if (isPSHUFHWMask(M, VT))
6687 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6688 X86::getShufflePSHUFHWImmediate(SVOp),
6691 if (isPSHUFLWMask(M, VT))
6692 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6693 X86::getShufflePSHUFLWImmediate(SVOp),
6696 if (isSHUFPMask(M, VT, HasAVX))
6697 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6698 X86::getShuffleSHUFImmediate(SVOp), DAG);
6700 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6701 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6702 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6703 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6705 //===--------------------------------------------------------------------===//
6706 // Generate target specific nodes for 128 or 256-bit shuffles only
6707 // supported in the AVX instruction set.
6710 // Handle VMOVDDUPY permutations
6711 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6712 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6714 // Handle VPERMILPS/D* permutations
6715 if (isVPERMILPMask(M, VT, HasAVX))
6716 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6717 getShuffleVPERMILPImmediate(SVOp), DAG);
6719 // Handle VPERM2F128/VPERM2I128 permutations
6720 if (isVPERM2X128Mask(M, VT, HasAVX))
6721 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6722 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6724 //===--------------------------------------------------------------------===//
6725 // Since no target specific shuffle was selected for this generic one,
6726 // lower it into other known shuffles. FIXME: this isn't true yet, but
6727 // this is the plan.
6730 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6731 if (VT == MVT::v8i16) {
6732 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6733 if (NewOp.getNode())
6737 if (VT == MVT::v16i8) {
6738 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6739 if (NewOp.getNode())
6743 // Handle all 128-bit wide vectors with 4 elements, and match them with
6744 // several different shuffle types.
6745 if (NumElems == 4 && VT.getSizeInBits() == 128)
6746 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6748 // Handle general 256-bit shuffles
6749 if (VT.is256BitVector())
6750 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6756 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6757 SelectionDAG &DAG) const {
6758 EVT VT = Op.getValueType();
6759 DebugLoc dl = Op.getDebugLoc();
6761 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6764 if (VT.getSizeInBits() == 8) {
6765 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6766 Op.getOperand(0), Op.getOperand(1));
6767 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6768 DAG.getValueType(VT));
6769 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6770 } else if (VT.getSizeInBits() == 16) {
6771 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6772 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6774 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6775 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6776 DAG.getNode(ISD::BITCAST, dl,
6780 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6781 Op.getOperand(0), Op.getOperand(1));
6782 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6783 DAG.getValueType(VT));
6784 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6785 } else if (VT == MVT::f32) {
6786 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6787 // the result back to FR32 register. It's only worth matching if the
6788 // result has a single use which is a store or a bitcast to i32. And in
6789 // the case of a store, it's not worth it if the index is a constant 0,
6790 // because a MOVSSmr can be used instead, which is smaller and faster.
6791 if (!Op.hasOneUse())
6793 SDNode *User = *Op.getNode()->use_begin();
6794 if ((User->getOpcode() != ISD::STORE ||
6795 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6796 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6797 (User->getOpcode() != ISD::BITCAST ||
6798 User->getValueType(0) != MVT::i32))
6800 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6801 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6804 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6805 } else if (VT == MVT::i32 || VT == MVT::i64) {
6806 // ExtractPS/pextrq works with constant index.
6807 if (isa<ConstantSDNode>(Op.getOperand(1)))
6815 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6816 SelectionDAG &DAG) const {
6817 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6820 SDValue Vec = Op.getOperand(0);
6821 EVT VecVT = Vec.getValueType();
6823 // If this is a 256-bit vector result, first extract the 128-bit vector and
6824 // then extract the element from the 128-bit vector.
6825 if (VecVT.getSizeInBits() == 256) {
6826 DebugLoc dl = Op.getNode()->getDebugLoc();
6827 unsigned NumElems = VecVT.getVectorNumElements();
6828 SDValue Idx = Op.getOperand(1);
6829 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6831 // Get the 128-bit vector.
6832 bool Upper = IdxVal >= NumElems/2;
6833 Vec = Extract128BitVector(Vec,
6834 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6836 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6837 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6840 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6842 if (Subtarget->hasSSE41()) {
6843 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6848 EVT VT = Op.getValueType();
6849 DebugLoc dl = Op.getDebugLoc();
6850 // TODO: handle v16i8.
6851 if (VT.getSizeInBits() == 16) {
6852 SDValue Vec = Op.getOperand(0);
6853 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6855 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6856 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6857 DAG.getNode(ISD::BITCAST, dl,
6860 // Transform it so it match pextrw which produces a 32-bit result.
6861 EVT EltVT = MVT::i32;
6862 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6863 Op.getOperand(0), Op.getOperand(1));
6864 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6865 DAG.getValueType(VT));
6866 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6867 } else if (VT.getSizeInBits() == 32) {
6868 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6872 // SHUFPS the element to the lowest double word, then movss.
6873 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6874 EVT VVT = Op.getOperand(0).getValueType();
6875 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6876 DAG.getUNDEF(VVT), Mask);
6877 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6878 DAG.getIntPtrConstant(0));
6879 } else if (VT.getSizeInBits() == 64) {
6880 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6881 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6882 // to match extract_elt for f64.
6883 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6887 // UNPCKHPD the element to the lowest double word, then movsd.
6888 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6889 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6890 int Mask[2] = { 1, -1 };
6891 EVT VVT = Op.getOperand(0).getValueType();
6892 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6893 DAG.getUNDEF(VVT), Mask);
6894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6895 DAG.getIntPtrConstant(0));
6902 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6903 SelectionDAG &DAG) const {
6904 EVT VT = Op.getValueType();
6905 EVT EltVT = VT.getVectorElementType();
6906 DebugLoc dl = Op.getDebugLoc();
6908 SDValue N0 = Op.getOperand(0);
6909 SDValue N1 = Op.getOperand(1);
6910 SDValue N2 = Op.getOperand(2);
6912 if (VT.getSizeInBits() == 256)
6915 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6916 isa<ConstantSDNode>(N2)) {
6918 if (VT == MVT::v8i16)
6919 Opc = X86ISD::PINSRW;
6920 else if (VT == MVT::v16i8)
6921 Opc = X86ISD::PINSRB;
6923 Opc = X86ISD::PINSRB;
6925 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6927 if (N1.getValueType() != MVT::i32)
6928 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6929 if (N2.getValueType() != MVT::i32)
6930 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6931 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6932 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6933 // Bits [7:6] of the constant are the source select. This will always be
6934 // zero here. The DAG Combiner may combine an extract_elt index into these
6935 // bits. For example (insert (extract, 3), 2) could be matched by putting
6936 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6937 // Bits [5:4] of the constant are the destination select. This is the
6938 // value of the incoming immediate.
6939 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6940 // combine either bitwise AND or insert of float 0.0 to set these bits.
6941 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6942 // Create this as a scalar to vector..
6943 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6944 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6945 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6946 isa<ConstantSDNode>(N2)) {
6947 // PINSR* works with constant index.
6954 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6955 EVT VT = Op.getValueType();
6956 EVT EltVT = VT.getVectorElementType();
6958 DebugLoc dl = Op.getDebugLoc();
6959 SDValue N0 = Op.getOperand(0);
6960 SDValue N1 = Op.getOperand(1);
6961 SDValue N2 = Op.getOperand(2);
6963 // If this is a 256-bit vector result, first extract the 128-bit vector,
6964 // insert the element into the extracted half and then place it back.
6965 if (VT.getSizeInBits() == 256) {
6966 if (!isa<ConstantSDNode>(N2))
6969 // Get the desired 128-bit vector half.
6970 unsigned NumElems = VT.getVectorNumElements();
6971 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6972 bool Upper = IdxVal >= NumElems/2;
6973 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6974 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6976 // Insert the element into the desired half.
6977 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6978 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6980 // Insert the changed part back to the 256-bit vector
6981 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6984 if (Subtarget->hasSSE41())
6985 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6987 if (EltVT == MVT::i8)
6990 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6991 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6992 // as its second argument.
6993 if (N1.getValueType() != MVT::i32)
6994 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6995 if (N2.getValueType() != MVT::i32)
6996 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6997 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7003 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7004 LLVMContext *Context = DAG.getContext();
7005 DebugLoc dl = Op.getDebugLoc();
7006 EVT OpVT = Op.getValueType();
7008 // If this is a 256-bit vector result, first insert into a 128-bit
7009 // vector and then insert into the 256-bit vector.
7010 if (OpVT.getSizeInBits() > 128) {
7011 // Insert into a 128-bit vector.
7012 EVT VT128 = EVT::getVectorVT(*Context,
7013 OpVT.getVectorElementType(),
7014 OpVT.getVectorNumElements() / 2);
7016 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7018 // Insert the 128-bit vector.
7019 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7020 DAG.getConstant(0, MVT::i32),
7024 if (Op.getValueType() == MVT::v1i64 &&
7025 Op.getOperand(0).getValueType() == MVT::i64)
7026 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7028 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7029 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7030 "Expected an SSE type!");
7031 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7032 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7035 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7036 // a simple subregister reference or explicit instructions to grab
7037 // upper bits of a vector.
7039 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7040 if (Subtarget->hasAVX()) {
7041 DebugLoc dl = Op.getNode()->getDebugLoc();
7042 SDValue Vec = Op.getNode()->getOperand(0);
7043 SDValue Idx = Op.getNode()->getOperand(1);
7045 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7046 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7047 return Extract128BitVector(Vec, Idx, DAG, dl);
7053 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7054 // simple superregister reference or explicit instructions to insert
7055 // the upper bits of a vector.
7057 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7058 if (Subtarget->hasAVX()) {
7059 DebugLoc dl = Op.getNode()->getDebugLoc();
7060 SDValue Vec = Op.getNode()->getOperand(0);
7061 SDValue SubVec = Op.getNode()->getOperand(1);
7062 SDValue Idx = Op.getNode()->getOperand(2);
7064 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7065 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7066 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7072 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7073 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7074 // one of the above mentioned nodes. It has to be wrapped because otherwise
7075 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7076 // be used to form addressing mode. These wrapped nodes will be selected
7079 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7080 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7082 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7084 unsigned char OpFlag = 0;
7085 unsigned WrapperKind = X86ISD::Wrapper;
7086 CodeModel::Model M = getTargetMachine().getCodeModel();
7088 if (Subtarget->isPICStyleRIPRel() &&
7089 (M == CodeModel::Small || M == CodeModel::Kernel))
7090 WrapperKind = X86ISD::WrapperRIP;
7091 else if (Subtarget->isPICStyleGOT())
7092 OpFlag = X86II::MO_GOTOFF;
7093 else if (Subtarget->isPICStyleStubPIC())
7094 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7096 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7098 CP->getOffset(), OpFlag);
7099 DebugLoc DL = CP->getDebugLoc();
7100 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7101 // With PIC, the address is actually $g + Offset.
7103 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7104 DAG.getNode(X86ISD::GlobalBaseReg,
7105 DebugLoc(), getPointerTy()),
7112 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7113 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7115 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7117 unsigned char OpFlag = 0;
7118 unsigned WrapperKind = X86ISD::Wrapper;
7119 CodeModel::Model M = getTargetMachine().getCodeModel();
7121 if (Subtarget->isPICStyleRIPRel() &&
7122 (M == CodeModel::Small || M == CodeModel::Kernel))
7123 WrapperKind = X86ISD::WrapperRIP;
7124 else if (Subtarget->isPICStyleGOT())
7125 OpFlag = X86II::MO_GOTOFF;
7126 else if (Subtarget->isPICStyleStubPIC())
7127 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7129 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7131 DebugLoc DL = JT->getDebugLoc();
7132 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7134 // With PIC, the address is actually $g + Offset.
7136 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7137 DAG.getNode(X86ISD::GlobalBaseReg,
7138 DebugLoc(), getPointerTy()),
7145 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7146 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7148 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7150 unsigned char OpFlag = 0;
7151 unsigned WrapperKind = X86ISD::Wrapper;
7152 CodeModel::Model M = getTargetMachine().getCodeModel();
7154 if (Subtarget->isPICStyleRIPRel() &&
7155 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7156 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7157 OpFlag = X86II::MO_GOTPCREL;
7158 WrapperKind = X86ISD::WrapperRIP;
7159 } else if (Subtarget->isPICStyleGOT()) {
7160 OpFlag = X86II::MO_GOT;
7161 } else if (Subtarget->isPICStyleStubPIC()) {
7162 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7163 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7164 OpFlag = X86II::MO_DARWIN_NONLAZY;
7167 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7169 DebugLoc DL = Op.getDebugLoc();
7170 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7173 // With PIC, the address is actually $g + Offset.
7174 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7175 !Subtarget->is64Bit()) {
7176 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7177 DAG.getNode(X86ISD::GlobalBaseReg,
7178 DebugLoc(), getPointerTy()),
7182 // For symbols that require a load from a stub to get the address, emit the
7184 if (isGlobalStubReference(OpFlag))
7185 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7186 MachinePointerInfo::getGOT(), false, false, false, 0);
7192 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7193 // Create the TargetBlockAddressAddress node.
7194 unsigned char OpFlags =
7195 Subtarget->ClassifyBlockAddressReference();
7196 CodeModel::Model M = getTargetMachine().getCodeModel();
7197 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7198 DebugLoc dl = Op.getDebugLoc();
7199 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7200 /*isTarget=*/true, OpFlags);
7202 if (Subtarget->isPICStyleRIPRel() &&
7203 (M == CodeModel::Small || M == CodeModel::Kernel))
7204 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7206 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7208 // With PIC, the address is actually $g + Offset.
7209 if (isGlobalRelativeToPICBase(OpFlags)) {
7210 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7211 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7219 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7221 SelectionDAG &DAG) const {
7222 // Create the TargetGlobalAddress node, folding in the constant
7223 // offset if it is legal.
7224 unsigned char OpFlags =
7225 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7226 CodeModel::Model M = getTargetMachine().getCodeModel();
7228 if (OpFlags == X86II::MO_NO_FLAG &&
7229 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7230 // A direct static reference to a global.
7231 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7234 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7237 if (Subtarget->isPICStyleRIPRel() &&
7238 (M == CodeModel::Small || M == CodeModel::Kernel))
7239 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7241 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7243 // With PIC, the address is actually $g + Offset.
7244 if (isGlobalRelativeToPICBase(OpFlags)) {
7245 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7246 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7250 // For globals that require a load from a stub to get the address, emit the
7252 if (isGlobalStubReference(OpFlags))
7253 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7254 MachinePointerInfo::getGOT(), false, false, false, 0);
7256 // If there was a non-zero offset that we didn't fold, create an explicit
7259 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7260 DAG.getConstant(Offset, getPointerTy()));
7266 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7267 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7268 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7269 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7273 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7274 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7275 unsigned char OperandFlags) {
7276 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7277 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7278 DebugLoc dl = GA->getDebugLoc();
7279 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7280 GA->getValueType(0),
7284 SDValue Ops[] = { Chain, TGA, *InFlag };
7285 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7287 SDValue Ops[] = { Chain, TGA };
7288 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7291 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7292 MFI->setAdjustsStack(true);
7294 SDValue Flag = Chain.getValue(1);
7295 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7298 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7300 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7303 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7304 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7305 DAG.getNode(X86ISD::GlobalBaseReg,
7306 DebugLoc(), PtrVT), InFlag);
7307 InFlag = Chain.getValue(1);
7309 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7312 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7314 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7316 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7317 X86::RAX, X86II::MO_TLSGD);
7320 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7321 // "local exec" model.
7322 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7323 const EVT PtrVT, TLSModel::Model model,
7325 DebugLoc dl = GA->getDebugLoc();
7327 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7328 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7329 is64Bit ? 257 : 256));
7331 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7332 DAG.getIntPtrConstant(0),
7333 MachinePointerInfo(Ptr),
7334 false, false, false, 0);
7336 unsigned char OperandFlags = 0;
7337 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7339 unsigned WrapperKind = X86ISD::Wrapper;
7340 if (model == TLSModel::LocalExec) {
7341 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7342 } else if (is64Bit) {
7343 assert(model == TLSModel::InitialExec);
7344 OperandFlags = X86II::MO_GOTTPOFF;
7345 WrapperKind = X86ISD::WrapperRIP;
7347 assert(model == TLSModel::InitialExec);
7348 OperandFlags = X86II::MO_INDNTPOFF;
7351 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7353 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7354 GA->getValueType(0),
7355 GA->getOffset(), OperandFlags);
7356 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7358 if (model == TLSModel::InitialExec)
7359 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7360 MachinePointerInfo::getGOT(), false, false, false, 0);
7362 // The address of the thread local variable is the add of the thread
7363 // pointer with the offset of the variable.
7364 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7368 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7370 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7371 const GlobalValue *GV = GA->getGlobal();
7373 if (Subtarget->isTargetELF()) {
7374 // TODO: implement the "local dynamic" model
7375 // TODO: implement the "initial exec"model for pic executables
7377 // If GV is an alias then use the aliasee for determining
7378 // thread-localness.
7379 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7380 GV = GA->resolveAliasedGlobal(false);
7382 TLSModel::Model model
7383 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7386 case TLSModel::GeneralDynamic:
7387 case TLSModel::LocalDynamic: // not implemented
7388 if (Subtarget->is64Bit())
7389 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7390 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7392 case TLSModel::InitialExec:
7393 case TLSModel::LocalExec:
7394 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7395 Subtarget->is64Bit());
7397 } else if (Subtarget->isTargetDarwin()) {
7398 // Darwin only has one model of TLS. Lower to that.
7399 unsigned char OpFlag = 0;
7400 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7401 X86ISD::WrapperRIP : X86ISD::Wrapper;
7403 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7405 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7406 !Subtarget->is64Bit();
7408 OpFlag = X86II::MO_TLVP_PIC_BASE;
7410 OpFlag = X86II::MO_TLVP;
7411 DebugLoc DL = Op.getDebugLoc();
7412 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7413 GA->getValueType(0),
7414 GA->getOffset(), OpFlag);
7415 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7417 // With PIC32, the address is actually $g + Offset.
7419 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7420 DAG.getNode(X86ISD::GlobalBaseReg,
7421 DebugLoc(), getPointerTy()),
7424 // Lowering the machine isd will make sure everything is in the right
7426 SDValue Chain = DAG.getEntryNode();
7427 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7428 SDValue Args[] = { Chain, Offset };
7429 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7431 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7432 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7433 MFI->setAdjustsStack(true);
7435 // And our return value (tls address) is in the standard call return value
7437 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7438 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7443 "TLS not implemented for this target.");
7445 llvm_unreachable("Unreachable");
7450 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7451 /// and take a 2 x i32 value to shift plus a shift amount.
7452 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7453 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7454 EVT VT = Op.getValueType();
7455 unsigned VTBits = VT.getSizeInBits();
7456 DebugLoc dl = Op.getDebugLoc();
7457 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7458 SDValue ShOpLo = Op.getOperand(0);
7459 SDValue ShOpHi = Op.getOperand(1);
7460 SDValue ShAmt = Op.getOperand(2);
7461 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7462 DAG.getConstant(VTBits - 1, MVT::i8))
7463 : DAG.getConstant(0, VT);
7466 if (Op.getOpcode() == ISD::SHL_PARTS) {
7467 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7468 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7470 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7471 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7474 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7475 DAG.getConstant(VTBits, MVT::i8));
7476 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7477 AndNode, DAG.getConstant(0, MVT::i8));
7480 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7481 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7482 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7484 if (Op.getOpcode() == ISD::SHL_PARTS) {
7485 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7486 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7488 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7489 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7492 SDValue Ops[2] = { Lo, Hi };
7493 return DAG.getMergeValues(Ops, 2, dl);
7496 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7497 SelectionDAG &DAG) const {
7498 EVT SrcVT = Op.getOperand(0).getValueType();
7500 if (SrcVT.isVector())
7503 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7504 "Unknown SINT_TO_FP to lower!");
7506 // These are really Legal; return the operand so the caller accepts it as
7508 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7510 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7511 Subtarget->is64Bit()) {
7515 DebugLoc dl = Op.getDebugLoc();
7516 unsigned Size = SrcVT.getSizeInBits()/8;
7517 MachineFunction &MF = DAG.getMachineFunction();
7518 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7519 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7520 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7522 MachinePointerInfo::getFixedStack(SSFI),
7524 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7527 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7529 SelectionDAG &DAG) const {
7531 DebugLoc DL = Op.getDebugLoc();
7533 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7535 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7537 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7539 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7541 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7542 MachineMemOperand *MMO;
7544 int SSFI = FI->getIndex();
7546 DAG.getMachineFunction()
7547 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7548 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7550 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7551 StackSlot = StackSlot.getOperand(1);
7553 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7554 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7556 Tys, Ops, array_lengthof(Ops),
7560 Chain = Result.getValue(1);
7561 SDValue InFlag = Result.getValue(2);
7563 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7564 // shouldn't be necessary except that RFP cannot be live across
7565 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7566 MachineFunction &MF = DAG.getMachineFunction();
7567 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7568 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7570 Tys = DAG.getVTList(MVT::Other);
7572 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7574 MachineMemOperand *MMO =
7575 DAG.getMachineFunction()
7576 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7577 MachineMemOperand::MOStore, SSFISize, SSFISize);
7579 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7580 Ops, array_lengthof(Ops),
7581 Op.getValueType(), MMO);
7582 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7583 MachinePointerInfo::getFixedStack(SSFI),
7584 false, false, false, 0);
7590 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7591 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7592 SelectionDAG &DAG) const {
7593 // This algorithm is not obvious. Here it is what we're trying to output:
7596 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7597 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7601 pshufd $0x4e, %xmm0, %xmm1
7606 DebugLoc dl = Op.getDebugLoc();
7607 LLVMContext *Context = DAG.getContext();
7609 // Build some magic constants.
7610 SmallVector<Constant*,4> CV0;
7611 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7612 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7613 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7614 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7615 Constant *C0 = ConstantVector::get(CV0);
7616 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7618 SmallVector<Constant*,2> CV1;
7620 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7622 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7623 Constant *C1 = ConstantVector::get(CV1);
7624 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7626 // Load the 64-bit value into an XMM register.
7627 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7629 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7630 MachinePointerInfo::getConstantPool(),
7631 false, false, false, 16);
7632 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7633 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7636 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7637 MachinePointerInfo::getConstantPool(),
7638 false, false, false, 16);
7639 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7640 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7643 if (Subtarget->hasSSE3()) {
7644 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7645 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7647 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7648 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7650 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7651 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7655 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7656 DAG.getIntPtrConstant(0));
7659 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7660 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7661 SelectionDAG &DAG) const {
7662 DebugLoc dl = Op.getDebugLoc();
7663 // FP constant to bias correct the final result.
7664 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7667 // Load the 32-bit value into an XMM register.
7668 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7671 // Zero out the upper parts of the register.
7672 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7674 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7675 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7676 DAG.getIntPtrConstant(0));
7678 // Or the load with the bias.
7679 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7680 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7681 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7683 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7684 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7685 MVT::v2f64, Bias)));
7686 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7687 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7688 DAG.getIntPtrConstant(0));
7690 // Subtract the bias.
7691 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7693 // Handle final rounding.
7694 EVT DestVT = Op.getValueType();
7696 if (DestVT.bitsLT(MVT::f64)) {
7697 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7698 DAG.getIntPtrConstant(0));
7699 } else if (DestVT.bitsGT(MVT::f64)) {
7700 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7703 // Handle final rounding.
7707 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7708 SelectionDAG &DAG) const {
7709 SDValue N0 = Op.getOperand(0);
7710 DebugLoc dl = Op.getDebugLoc();
7712 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7713 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7714 // the optimization here.
7715 if (DAG.SignBitIsZero(N0))
7716 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7718 EVT SrcVT = N0.getValueType();
7719 EVT DstVT = Op.getValueType();
7720 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7721 return LowerUINT_TO_FP_i64(Op, DAG);
7722 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7723 return LowerUINT_TO_FP_i32(Op, DAG);
7724 else if (Subtarget->is64Bit() &&
7725 SrcVT == MVT::i64 && DstVT == MVT::f32)
7728 // Make a 64-bit buffer, and use it to build an FILD.
7729 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7730 if (SrcVT == MVT::i32) {
7731 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7732 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7733 getPointerTy(), StackSlot, WordOff);
7734 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7735 StackSlot, MachinePointerInfo(),
7737 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7738 OffsetSlot, MachinePointerInfo(),
7740 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7744 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7745 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7746 StackSlot, MachinePointerInfo(),
7748 // For i64 source, we need to add the appropriate power of 2 if the input
7749 // was negative. This is the same as the optimization in
7750 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7751 // we must be careful to do the computation in x87 extended precision, not
7752 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7753 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7754 MachineMemOperand *MMO =
7755 DAG.getMachineFunction()
7756 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7757 MachineMemOperand::MOLoad, 8, 8);
7759 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7760 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7761 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7764 APInt FF(32, 0x5F800000ULL);
7766 // Check whether the sign bit is set.
7767 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7768 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7771 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7772 SDValue FudgePtr = DAG.getConstantPool(
7773 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7776 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7777 SDValue Zero = DAG.getIntPtrConstant(0);
7778 SDValue Four = DAG.getIntPtrConstant(4);
7779 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7781 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7783 // Load the value out, extending it from f32 to f80.
7784 // FIXME: Avoid the extend by constructing the right constant pool?
7785 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7786 FudgePtr, MachinePointerInfo::getConstantPool(),
7787 MVT::f32, false, false, 4);
7788 // Extend everything to 80 bits to force it to be done on x87.
7789 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7790 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7793 std::pair<SDValue,SDValue> X86TargetLowering::
7794 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7795 DebugLoc DL = Op.getDebugLoc();
7797 EVT DstTy = Op.getValueType();
7800 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7804 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7805 DstTy.getSimpleVT() >= MVT::i16 &&
7806 "Unknown FP_TO_SINT to lower!");
7808 // These are really Legal.
7809 if (DstTy == MVT::i32 &&
7810 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7811 return std::make_pair(SDValue(), SDValue());
7812 if (Subtarget->is64Bit() &&
7813 DstTy == MVT::i64 &&
7814 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7815 return std::make_pair(SDValue(), SDValue());
7817 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7819 MachineFunction &MF = DAG.getMachineFunction();
7820 unsigned MemSize = DstTy.getSizeInBits()/8;
7821 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7822 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7827 switch (DstTy.getSimpleVT().SimpleTy) {
7828 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7829 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7830 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7831 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7834 SDValue Chain = DAG.getEntryNode();
7835 SDValue Value = Op.getOperand(0);
7836 EVT TheVT = Op.getOperand(0).getValueType();
7837 if (isScalarFPTypeInSSEReg(TheVT)) {
7838 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7839 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7840 MachinePointerInfo::getFixedStack(SSFI),
7842 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7844 Chain, StackSlot, DAG.getValueType(TheVT)
7847 MachineMemOperand *MMO =
7848 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7849 MachineMemOperand::MOLoad, MemSize, MemSize);
7850 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7852 Chain = Value.getValue(1);
7853 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7854 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7857 MachineMemOperand *MMO =
7858 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7859 MachineMemOperand::MOStore, MemSize, MemSize);
7861 // Build the FP_TO_INT*_IN_MEM
7862 SDValue Ops[] = { Chain, Value, StackSlot };
7863 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7864 Ops, 3, DstTy, MMO);
7866 return std::make_pair(FIST, StackSlot);
7869 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7870 SelectionDAG &DAG) const {
7871 if (Op.getValueType().isVector())
7874 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7875 SDValue FIST = Vals.first, StackSlot = Vals.second;
7876 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7877 if (FIST.getNode() == 0) return Op;
7880 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7881 FIST, StackSlot, MachinePointerInfo(),
7882 false, false, false, 0);
7885 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7886 SelectionDAG &DAG) const {
7887 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7888 SDValue FIST = Vals.first, StackSlot = Vals.second;
7889 assert(FIST.getNode() && "Unexpected failure");
7892 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7893 FIST, StackSlot, MachinePointerInfo(),
7894 false, false, false, 0);
7897 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7898 SelectionDAG &DAG) const {
7899 LLVMContext *Context = DAG.getContext();
7900 DebugLoc dl = Op.getDebugLoc();
7901 EVT VT = Op.getValueType();
7904 EltVT = VT.getVectorElementType();
7905 SmallVector<Constant*,4> CV;
7906 if (EltVT == MVT::f64) {
7907 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7910 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7913 Constant *C = ConstantVector::get(CV);
7914 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7915 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7916 MachinePointerInfo::getConstantPool(),
7917 false, false, false, 16);
7918 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7921 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7922 LLVMContext *Context = DAG.getContext();
7923 DebugLoc dl = Op.getDebugLoc();
7924 EVT VT = Op.getValueType();
7926 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7927 if (VT.isVector()) {
7928 EltVT = VT.getVectorElementType();
7929 NumElts = VT.getVectorNumElements();
7931 SmallVector<Constant*,8> CV;
7932 if (EltVT == MVT::f64) {
7933 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7934 CV.assign(NumElts, C);
7936 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7937 CV.assign(NumElts, C);
7939 Constant *C = ConstantVector::get(CV);
7940 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7941 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7942 MachinePointerInfo::getConstantPool(),
7943 false, false, false, 16);
7944 if (VT.isVector()) {
7945 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7946 return DAG.getNode(ISD::BITCAST, dl, VT,
7947 DAG.getNode(ISD::XOR, dl, XORVT,
7948 DAG.getNode(ISD::BITCAST, dl, XORVT,
7950 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7952 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7956 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7957 LLVMContext *Context = DAG.getContext();
7958 SDValue Op0 = Op.getOperand(0);
7959 SDValue Op1 = Op.getOperand(1);
7960 DebugLoc dl = Op.getDebugLoc();
7961 EVT VT = Op.getValueType();
7962 EVT SrcVT = Op1.getValueType();
7964 // If second operand is smaller, extend it first.
7965 if (SrcVT.bitsLT(VT)) {
7966 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7969 // And if it is bigger, shrink it first.
7970 if (SrcVT.bitsGT(VT)) {
7971 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7975 // At this point the operands and the result should have the same
7976 // type, and that won't be f80 since that is not custom lowered.
7978 // First get the sign bit of second operand.
7979 SmallVector<Constant*,4> CV;
7980 if (SrcVT == MVT::f64) {
7981 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7982 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7984 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7985 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7986 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7987 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7989 Constant *C = ConstantVector::get(CV);
7990 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7991 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7992 MachinePointerInfo::getConstantPool(),
7993 false, false, false, 16);
7994 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7996 // Shift sign bit right or left if the two operands have different types.
7997 if (SrcVT.bitsGT(VT)) {
7998 // Op0 is MVT::f32, Op1 is MVT::f64.
7999 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8000 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8001 DAG.getConstant(32, MVT::i32));
8002 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8003 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8004 DAG.getIntPtrConstant(0));
8007 // Clear first operand sign bit.
8009 if (VT == MVT::f64) {
8010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8011 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8013 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8014 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8015 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8016 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8018 C = ConstantVector::get(CV);
8019 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8020 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8021 MachinePointerInfo::getConstantPool(),
8022 false, false, false, 16);
8023 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8025 // Or the value with the sign bit.
8026 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8029 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8030 SDValue N0 = Op.getOperand(0);
8031 DebugLoc dl = Op.getDebugLoc();
8032 EVT VT = Op.getValueType();
8034 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8035 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8036 DAG.getConstant(1, VT));
8037 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8040 /// Emit nodes that will be selected as "test Op0,Op0", or something
8042 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8043 SelectionDAG &DAG) const {
8044 DebugLoc dl = Op.getDebugLoc();
8046 // CF and OF aren't always set the way we want. Determine which
8047 // of these we need.
8048 bool NeedCF = false;
8049 bool NeedOF = false;
8052 case X86::COND_A: case X86::COND_AE:
8053 case X86::COND_B: case X86::COND_BE:
8056 case X86::COND_G: case X86::COND_GE:
8057 case X86::COND_L: case X86::COND_LE:
8058 case X86::COND_O: case X86::COND_NO:
8063 // See if we can use the EFLAGS value from the operand instead of
8064 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8065 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8066 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8067 // Emit a CMP with 0, which is the TEST pattern.
8068 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8069 DAG.getConstant(0, Op.getValueType()));
8071 unsigned Opcode = 0;
8072 unsigned NumOperands = 0;
8073 switch (Op.getNode()->getOpcode()) {
8075 // Due to an isel shortcoming, be conservative if this add is likely to be
8076 // selected as part of a load-modify-store instruction. When the root node
8077 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8078 // uses of other nodes in the match, such as the ADD in this case. This
8079 // leads to the ADD being left around and reselected, with the result being
8080 // two adds in the output. Alas, even if none our users are stores, that
8081 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8082 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8083 // climbing the DAG back to the root, and it doesn't seem to be worth the
8085 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8086 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8087 if (UI->getOpcode() != ISD::CopyToReg &&
8088 UI->getOpcode() != ISD::SETCC &&
8089 UI->getOpcode() != ISD::STORE)
8092 if (ConstantSDNode *C =
8093 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8094 // An add of one will be selected as an INC.
8095 if (C->getAPIntValue() == 1) {
8096 Opcode = X86ISD::INC;
8101 // An add of negative one (subtract of one) will be selected as a DEC.
8102 if (C->getAPIntValue().isAllOnesValue()) {
8103 Opcode = X86ISD::DEC;
8109 // Otherwise use a regular EFLAGS-setting add.
8110 Opcode = X86ISD::ADD;
8114 // If the primary and result isn't used, don't bother using X86ISD::AND,
8115 // because a TEST instruction will be better.
8116 bool NonFlagUse = false;
8117 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8118 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8120 unsigned UOpNo = UI.getOperandNo();
8121 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8122 // Look pass truncate.
8123 UOpNo = User->use_begin().getOperandNo();
8124 User = *User->use_begin();
8127 if (User->getOpcode() != ISD::BRCOND &&
8128 User->getOpcode() != ISD::SETCC &&
8129 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8142 // Due to the ISEL shortcoming noted above, be conservative if this op is
8143 // likely to be selected as part of a load-modify-store instruction.
8144 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8145 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8146 if (UI->getOpcode() == ISD::STORE)
8149 // Otherwise use a regular EFLAGS-setting instruction.
8150 switch (Op.getNode()->getOpcode()) {
8151 default: llvm_unreachable("unexpected operator!");
8152 case ISD::SUB: Opcode = X86ISD::SUB; break;
8153 case ISD::OR: Opcode = X86ISD::OR; break;
8154 case ISD::XOR: Opcode = X86ISD::XOR; break;
8155 case ISD::AND: Opcode = X86ISD::AND; break;
8167 return SDValue(Op.getNode(), 1);
8174 // Emit a CMP with 0, which is the TEST pattern.
8175 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8176 DAG.getConstant(0, Op.getValueType()));
8178 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8179 SmallVector<SDValue, 4> Ops;
8180 for (unsigned i = 0; i != NumOperands; ++i)
8181 Ops.push_back(Op.getOperand(i));
8183 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8184 DAG.ReplaceAllUsesWith(Op, New);
8185 return SDValue(New.getNode(), 1);
8188 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8190 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8191 SelectionDAG &DAG) const {
8192 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8193 if (C->getAPIntValue() == 0)
8194 return EmitTest(Op0, X86CC, DAG);
8196 DebugLoc dl = Op0.getDebugLoc();
8197 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8200 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8201 /// if it's possible.
8202 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8203 DebugLoc dl, SelectionDAG &DAG) const {
8204 SDValue Op0 = And.getOperand(0);
8205 SDValue Op1 = And.getOperand(1);
8206 if (Op0.getOpcode() == ISD::TRUNCATE)
8207 Op0 = Op0.getOperand(0);
8208 if (Op1.getOpcode() == ISD::TRUNCATE)
8209 Op1 = Op1.getOperand(0);
8212 if (Op1.getOpcode() == ISD::SHL)
8213 std::swap(Op0, Op1);
8214 if (Op0.getOpcode() == ISD::SHL) {
8215 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8216 if (And00C->getZExtValue() == 1) {
8217 // If we looked past a truncate, check that it's only truncating away
8219 unsigned BitWidth = Op0.getValueSizeInBits();
8220 unsigned AndBitWidth = And.getValueSizeInBits();
8221 if (BitWidth > AndBitWidth) {
8222 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8223 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8224 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8228 RHS = Op0.getOperand(1);
8230 } else if (Op1.getOpcode() == ISD::Constant) {
8231 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8232 uint64_t AndRHSVal = AndRHS->getZExtValue();
8233 SDValue AndLHS = Op0;
8235 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8236 LHS = AndLHS.getOperand(0);
8237 RHS = AndLHS.getOperand(1);
8240 // Use BT if the immediate can't be encoded in a TEST instruction.
8241 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8243 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8247 if (LHS.getNode()) {
8248 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8249 // instruction. Since the shift amount is in-range-or-undefined, we know
8250 // that doing a bittest on the i32 value is ok. We extend to i32 because
8251 // the encoding for the i16 version is larger than the i32 version.
8252 // Also promote i16 to i32 for performance / code size reason.
8253 if (LHS.getValueType() == MVT::i8 ||
8254 LHS.getValueType() == MVT::i16)
8255 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8257 // If the operand types disagree, extend the shift amount to match. Since
8258 // BT ignores high bits (like shifts) we can use anyextend.
8259 if (LHS.getValueType() != RHS.getValueType())
8260 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8262 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8263 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8264 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8265 DAG.getConstant(Cond, MVT::i8), BT);
8271 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8273 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8275 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8276 SDValue Op0 = Op.getOperand(0);
8277 SDValue Op1 = Op.getOperand(1);
8278 DebugLoc dl = Op.getDebugLoc();
8279 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8281 // Optimize to BT if possible.
8282 // Lower (X & (1 << N)) == 0 to BT(X, N).
8283 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8284 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8285 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8286 Op1.getOpcode() == ISD::Constant &&
8287 cast<ConstantSDNode>(Op1)->isNullValue() &&
8288 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8289 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8290 if (NewSetCC.getNode())
8294 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8296 if (Op1.getOpcode() == ISD::Constant &&
8297 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8298 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8299 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8301 // If the input is a setcc, then reuse the input setcc or use a new one with
8302 // the inverted condition.
8303 if (Op0.getOpcode() == X86ISD::SETCC) {
8304 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8305 bool Invert = (CC == ISD::SETNE) ^
8306 cast<ConstantSDNode>(Op1)->isNullValue();
8307 if (!Invert) return Op0;
8309 CCode = X86::GetOppositeBranchCondition(CCode);
8310 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8311 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8315 bool isFP = Op1.getValueType().isFloatingPoint();
8316 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8317 if (X86CC == X86::COND_INVALID)
8320 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8321 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8322 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8325 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8326 // ones, and then concatenate the result back.
8327 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8328 EVT VT = Op.getValueType();
8330 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8331 "Unsupported value type for operation");
8333 int NumElems = VT.getVectorNumElements();
8334 DebugLoc dl = Op.getDebugLoc();
8335 SDValue CC = Op.getOperand(2);
8336 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8337 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8339 // Extract the LHS vectors
8340 SDValue LHS = Op.getOperand(0);
8341 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8342 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8344 // Extract the RHS vectors
8345 SDValue RHS = Op.getOperand(1);
8346 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8347 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8349 // Issue the operation on the smaller types and concatenate the result back
8350 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8351 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8352 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8353 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8354 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8358 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8360 SDValue Op0 = Op.getOperand(0);
8361 SDValue Op1 = Op.getOperand(1);
8362 SDValue CC = Op.getOperand(2);
8363 EVT VT = Op.getValueType();
8364 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8365 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8366 DebugLoc dl = Op.getDebugLoc();
8370 EVT EltVT = Op0.getValueType().getVectorElementType();
8371 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8373 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8376 // SSE Condition code mapping:
8385 switch (SetCCOpcode) {
8388 case ISD::SETEQ: SSECC = 0; break;
8390 case ISD::SETGT: Swap = true; // Fallthrough
8392 case ISD::SETOLT: SSECC = 1; break;
8394 case ISD::SETGE: Swap = true; // Fallthrough
8396 case ISD::SETOLE: SSECC = 2; break;
8397 case ISD::SETUO: SSECC = 3; break;
8399 case ISD::SETNE: SSECC = 4; break;
8400 case ISD::SETULE: Swap = true;
8401 case ISD::SETUGE: SSECC = 5; break;
8402 case ISD::SETULT: Swap = true;
8403 case ISD::SETUGT: SSECC = 6; break;
8404 case ISD::SETO: SSECC = 7; break;
8407 std::swap(Op0, Op1);
8409 // In the two special cases we can't handle, emit two comparisons.
8411 if (SetCCOpcode == ISD::SETUEQ) {
8413 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8414 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8415 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8416 } else if (SetCCOpcode == ISD::SETONE) {
8418 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8419 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8420 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8422 llvm_unreachable("Illegal FP comparison");
8424 // Handle all other FP comparisons here.
8425 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8428 // Break 256-bit integer vector compare into smaller ones.
8429 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8430 return Lower256IntVSETCC(Op, DAG);
8432 // We are handling one of the integer comparisons here. Since SSE only has
8433 // GT and EQ comparisons for integer, swapping operands and multiple
8434 // operations may be required for some comparisons.
8435 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8436 bool Swap = false, Invert = false, FlipSigns = false;
8438 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8440 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8441 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8442 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8443 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8446 switch (SetCCOpcode) {
8448 case ISD::SETNE: Invert = true;
8449 case ISD::SETEQ: Opc = EQOpc; break;
8450 case ISD::SETLT: Swap = true;
8451 case ISD::SETGT: Opc = GTOpc; break;
8452 case ISD::SETGE: Swap = true;
8453 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8454 case ISD::SETULT: Swap = true;
8455 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8456 case ISD::SETUGE: Swap = true;
8457 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8460 std::swap(Op0, Op1);
8462 // Check that the operation in question is available (most are plain SSE2,
8463 // but PCMPGTQ and PCMPEQQ have different requirements).
8464 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42())
8466 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41())
8469 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8470 // bits of the inputs before performing those operations.
8472 EVT EltVT = VT.getVectorElementType();
8473 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8475 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8476 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8478 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8479 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8482 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8484 // If the logical-not of the result is required, perform that now.
8486 Result = DAG.getNOT(dl, Result, VT);
8491 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8492 static bool isX86LogicalCmp(SDValue Op) {
8493 unsigned Opc = Op.getNode()->getOpcode();
8494 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8496 if (Op.getResNo() == 1 &&
8497 (Opc == X86ISD::ADD ||
8498 Opc == X86ISD::SUB ||
8499 Opc == X86ISD::ADC ||
8500 Opc == X86ISD::SBB ||
8501 Opc == X86ISD::SMUL ||
8502 Opc == X86ISD::UMUL ||
8503 Opc == X86ISD::INC ||
8504 Opc == X86ISD::DEC ||
8505 Opc == X86ISD::OR ||
8506 Opc == X86ISD::XOR ||
8507 Opc == X86ISD::AND))
8510 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8516 static bool isZero(SDValue V) {
8517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8518 return C && C->isNullValue();
8521 static bool isAllOnes(SDValue V) {
8522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8523 return C && C->isAllOnesValue();
8526 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8527 bool addTest = true;
8528 SDValue Cond = Op.getOperand(0);
8529 SDValue Op1 = Op.getOperand(1);
8530 SDValue Op2 = Op.getOperand(2);
8531 DebugLoc DL = Op.getDebugLoc();
8534 if (Cond.getOpcode() == ISD::SETCC) {
8535 SDValue NewCond = LowerSETCC(Cond, DAG);
8536 if (NewCond.getNode())
8540 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8541 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8542 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8543 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8544 if (Cond.getOpcode() == X86ISD::SETCC &&
8545 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8546 isZero(Cond.getOperand(1).getOperand(1))) {
8547 SDValue Cmp = Cond.getOperand(1);
8549 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8551 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8552 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8553 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8555 SDValue CmpOp0 = Cmp.getOperand(0);
8556 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8557 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8559 SDValue Res = // Res = 0 or -1.
8560 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8561 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8563 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8564 Res = DAG.getNOT(DL, Res, Res.getValueType());
8566 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8567 if (N2C == 0 || !N2C->isNullValue())
8568 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8573 // Look past (and (setcc_carry (cmp ...)), 1).
8574 if (Cond.getOpcode() == ISD::AND &&
8575 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8576 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8577 if (C && C->getAPIntValue() == 1)
8578 Cond = Cond.getOperand(0);
8581 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8582 // setting operand in place of the X86ISD::SETCC.
8583 unsigned CondOpcode = Cond.getOpcode();
8584 if (CondOpcode == X86ISD::SETCC ||
8585 CondOpcode == X86ISD::SETCC_CARRY) {
8586 CC = Cond.getOperand(0);
8588 SDValue Cmp = Cond.getOperand(1);
8589 unsigned Opc = Cmp.getOpcode();
8590 EVT VT = Op.getValueType();
8592 bool IllegalFPCMov = false;
8593 if (VT.isFloatingPoint() && !VT.isVector() &&
8594 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8595 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8597 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8598 Opc == X86ISD::BT) { // FIXME
8602 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8603 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8604 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8605 Cond.getOperand(0).getValueType() != MVT::i8)) {
8606 SDValue LHS = Cond.getOperand(0);
8607 SDValue RHS = Cond.getOperand(1);
8611 switch (CondOpcode) {
8612 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8613 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8614 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8615 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8616 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8617 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8618 default: llvm_unreachable("unexpected overflowing operator");
8620 if (CondOpcode == ISD::UMULO)
8621 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8624 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8626 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8628 if (CondOpcode == ISD::UMULO)
8629 Cond = X86Op.getValue(2);
8631 Cond = X86Op.getValue(1);
8633 CC = DAG.getConstant(X86Cond, MVT::i8);
8638 // Look pass the truncate.
8639 if (Cond.getOpcode() == ISD::TRUNCATE)
8640 Cond = Cond.getOperand(0);
8642 // We know the result of AND is compared against zero. Try to match
8644 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8645 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8646 if (NewSetCC.getNode()) {
8647 CC = NewSetCC.getOperand(0);
8648 Cond = NewSetCC.getOperand(1);
8655 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8656 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8659 // a < b ? -1 : 0 -> RES = ~setcc_carry
8660 // a < b ? 0 : -1 -> RES = setcc_carry
8661 // a >= b ? -1 : 0 -> RES = setcc_carry
8662 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8663 if (Cond.getOpcode() == X86ISD::CMP) {
8664 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8666 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8667 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8668 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8669 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8670 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8671 return DAG.getNOT(DL, Res, Res.getValueType());
8676 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8677 // condition is true.
8678 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8679 SDValue Ops[] = { Op2, Op1, CC, Cond };
8680 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8683 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8684 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8685 // from the AND / OR.
8686 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8687 Opc = Op.getOpcode();
8688 if (Opc != ISD::OR && Opc != ISD::AND)
8690 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8691 Op.getOperand(0).hasOneUse() &&
8692 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8693 Op.getOperand(1).hasOneUse());
8696 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8697 // 1 and that the SETCC node has a single use.
8698 static bool isXor1OfSetCC(SDValue Op) {
8699 if (Op.getOpcode() != ISD::XOR)
8701 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8702 if (N1C && N1C->getAPIntValue() == 1) {
8703 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8704 Op.getOperand(0).hasOneUse();
8709 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8710 bool addTest = true;
8711 SDValue Chain = Op.getOperand(0);
8712 SDValue Cond = Op.getOperand(1);
8713 SDValue Dest = Op.getOperand(2);
8714 DebugLoc dl = Op.getDebugLoc();
8716 bool Inverted = false;
8718 if (Cond.getOpcode() == ISD::SETCC) {
8719 // Check for setcc([su]{add,sub,mul}o == 0).
8720 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8721 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8722 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8723 Cond.getOperand(0).getResNo() == 1 &&
8724 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8725 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8726 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8727 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8728 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8729 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8731 Cond = Cond.getOperand(0);
8733 SDValue NewCond = LowerSETCC(Cond, DAG);
8734 if (NewCond.getNode())
8739 // FIXME: LowerXALUO doesn't handle these!!
8740 else if (Cond.getOpcode() == X86ISD::ADD ||
8741 Cond.getOpcode() == X86ISD::SUB ||
8742 Cond.getOpcode() == X86ISD::SMUL ||
8743 Cond.getOpcode() == X86ISD::UMUL)
8744 Cond = LowerXALUO(Cond, DAG);
8747 // Look pass (and (setcc_carry (cmp ...)), 1).
8748 if (Cond.getOpcode() == ISD::AND &&
8749 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8750 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8751 if (C && C->getAPIntValue() == 1)
8752 Cond = Cond.getOperand(0);
8755 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8756 // setting operand in place of the X86ISD::SETCC.
8757 unsigned CondOpcode = Cond.getOpcode();
8758 if (CondOpcode == X86ISD::SETCC ||
8759 CondOpcode == X86ISD::SETCC_CARRY) {
8760 CC = Cond.getOperand(0);
8762 SDValue Cmp = Cond.getOperand(1);
8763 unsigned Opc = Cmp.getOpcode();
8764 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8765 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8769 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8773 // These can only come from an arithmetic instruction with overflow,
8774 // e.g. SADDO, UADDO.
8775 Cond = Cond.getNode()->getOperand(1);
8781 CondOpcode = Cond.getOpcode();
8782 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8783 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8784 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8785 Cond.getOperand(0).getValueType() != MVT::i8)) {
8786 SDValue LHS = Cond.getOperand(0);
8787 SDValue RHS = Cond.getOperand(1);
8791 switch (CondOpcode) {
8792 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8793 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8794 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8795 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8796 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8797 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8798 default: llvm_unreachable("unexpected overflowing operator");
8801 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8802 if (CondOpcode == ISD::UMULO)
8803 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8806 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8808 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8810 if (CondOpcode == ISD::UMULO)
8811 Cond = X86Op.getValue(2);
8813 Cond = X86Op.getValue(1);
8815 CC = DAG.getConstant(X86Cond, MVT::i8);
8819 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8820 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8821 if (CondOpc == ISD::OR) {
8822 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8823 // two branches instead of an explicit OR instruction with a
8825 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8826 isX86LogicalCmp(Cmp)) {
8827 CC = Cond.getOperand(0).getOperand(0);
8828 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8829 Chain, Dest, CC, Cmp);
8830 CC = Cond.getOperand(1).getOperand(0);
8834 } else { // ISD::AND
8835 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8836 // two branches instead of an explicit AND instruction with a
8837 // separate test. However, we only do this if this block doesn't
8838 // have a fall-through edge, because this requires an explicit
8839 // jmp when the condition is false.
8840 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8841 isX86LogicalCmp(Cmp) &&
8842 Op.getNode()->hasOneUse()) {
8843 X86::CondCode CCode =
8844 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8845 CCode = X86::GetOppositeBranchCondition(CCode);
8846 CC = DAG.getConstant(CCode, MVT::i8);
8847 SDNode *User = *Op.getNode()->use_begin();
8848 // Look for an unconditional branch following this conditional branch.
8849 // We need this because we need to reverse the successors in order
8850 // to implement FCMP_OEQ.
8851 if (User->getOpcode() == ISD::BR) {
8852 SDValue FalseBB = User->getOperand(1);
8854 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8855 assert(NewBR == User);
8859 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8860 Chain, Dest, CC, Cmp);
8861 X86::CondCode CCode =
8862 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8863 CCode = X86::GetOppositeBranchCondition(CCode);
8864 CC = DAG.getConstant(CCode, MVT::i8);
8870 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8871 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8872 // It should be transformed during dag combiner except when the condition
8873 // is set by a arithmetics with overflow node.
8874 X86::CondCode CCode =
8875 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8876 CCode = X86::GetOppositeBranchCondition(CCode);
8877 CC = DAG.getConstant(CCode, MVT::i8);
8878 Cond = Cond.getOperand(0).getOperand(1);
8880 } else if (Cond.getOpcode() == ISD::SETCC &&
8881 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8882 // For FCMP_OEQ, we can emit
8883 // two branches instead of an explicit AND instruction with a
8884 // separate test. However, we only do this if this block doesn't
8885 // have a fall-through edge, because this requires an explicit
8886 // jmp when the condition is false.
8887 if (Op.getNode()->hasOneUse()) {
8888 SDNode *User = *Op.getNode()->use_begin();
8889 // Look for an unconditional branch following this conditional branch.
8890 // We need this because we need to reverse the successors in order
8891 // to implement FCMP_OEQ.
8892 if (User->getOpcode() == ISD::BR) {
8893 SDValue FalseBB = User->getOperand(1);
8895 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8896 assert(NewBR == User);
8900 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8901 Cond.getOperand(0), Cond.getOperand(1));
8902 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8903 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8904 Chain, Dest, CC, Cmp);
8905 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8910 } else if (Cond.getOpcode() == ISD::SETCC &&
8911 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8912 // For FCMP_UNE, we can emit
8913 // two branches instead of an explicit AND instruction with a
8914 // separate test. However, we only do this if this block doesn't
8915 // have a fall-through edge, because this requires an explicit
8916 // jmp when the condition is false.
8917 if (Op.getNode()->hasOneUse()) {
8918 SDNode *User = *Op.getNode()->use_begin();
8919 // Look for an unconditional branch following this conditional branch.
8920 // We need this because we need to reverse the successors in order
8921 // to implement FCMP_UNE.
8922 if (User->getOpcode() == ISD::BR) {
8923 SDValue FalseBB = User->getOperand(1);
8925 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8926 assert(NewBR == User);
8929 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8930 Cond.getOperand(0), Cond.getOperand(1));
8931 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8932 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8933 Chain, Dest, CC, Cmp);
8934 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8944 // Look pass the truncate.
8945 if (Cond.getOpcode() == ISD::TRUNCATE)
8946 Cond = Cond.getOperand(0);
8948 // We know the result of AND is compared against zero. Try to match
8950 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8951 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8952 if (NewSetCC.getNode()) {
8953 CC = NewSetCC.getOperand(0);
8954 Cond = NewSetCC.getOperand(1);
8961 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8962 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8964 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8965 Chain, Dest, CC, Cond);
8969 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8970 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8971 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8972 // that the guard pages used by the OS virtual memory manager are allocated in
8973 // correct sequence.
8975 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8976 SelectionDAG &DAG) const {
8977 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8978 getTargetMachine().Options.EnableSegmentedStacks) &&
8979 "This should be used only on Windows targets or when segmented stacks "
8981 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8982 DebugLoc dl = Op.getDebugLoc();
8985 SDValue Chain = Op.getOperand(0);
8986 SDValue Size = Op.getOperand(1);
8987 // FIXME: Ensure alignment here
8989 bool Is64Bit = Subtarget->is64Bit();
8990 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8992 if (getTargetMachine().Options.EnableSegmentedStacks) {
8993 MachineFunction &MF = DAG.getMachineFunction();
8994 MachineRegisterInfo &MRI = MF.getRegInfo();
8997 // The 64 bit implementation of segmented stacks needs to clobber both r10
8998 // r11. This makes it impossible to use it along with nested parameters.
8999 const Function *F = MF.getFunction();
9001 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9003 if (I->hasNestAttr())
9004 report_fatal_error("Cannot use segmented stacks with functions that "
9005 "have nested arguments.");
9008 const TargetRegisterClass *AddrRegClass =
9009 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9010 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9011 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9012 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9013 DAG.getRegister(Vreg, SPTy));
9014 SDValue Ops1[2] = { Value, Chain };
9015 return DAG.getMergeValues(Ops1, 2, dl);
9018 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9020 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9021 Flag = Chain.getValue(1);
9022 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9024 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9025 Flag = Chain.getValue(1);
9027 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9029 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9030 return DAG.getMergeValues(Ops1, 2, dl);
9034 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9035 MachineFunction &MF = DAG.getMachineFunction();
9036 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9038 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9039 DebugLoc DL = Op.getDebugLoc();
9041 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9042 // vastart just stores the address of the VarArgsFrameIndex slot into the
9043 // memory location argument.
9044 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9046 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9047 MachinePointerInfo(SV), false, false, 0);
9051 // gp_offset (0 - 6 * 8)
9052 // fp_offset (48 - 48 + 8 * 16)
9053 // overflow_arg_area (point to parameters coming in memory).
9055 SmallVector<SDValue, 8> MemOps;
9056 SDValue FIN = Op.getOperand(1);
9058 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9059 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9061 FIN, MachinePointerInfo(SV), false, false, 0);
9062 MemOps.push_back(Store);
9065 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9066 FIN, DAG.getIntPtrConstant(4));
9067 Store = DAG.getStore(Op.getOperand(0), DL,
9068 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9070 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9071 MemOps.push_back(Store);
9073 // Store ptr to overflow_arg_area
9074 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9075 FIN, DAG.getIntPtrConstant(4));
9076 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9078 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9079 MachinePointerInfo(SV, 8),
9081 MemOps.push_back(Store);
9083 // Store ptr to reg_save_area.
9084 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9085 FIN, DAG.getIntPtrConstant(8));
9086 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9088 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9089 MachinePointerInfo(SV, 16), false, false, 0);
9090 MemOps.push_back(Store);
9091 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9092 &MemOps[0], MemOps.size());
9095 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9096 assert(Subtarget->is64Bit() &&
9097 "LowerVAARG only handles 64-bit va_arg!");
9098 assert((Subtarget->isTargetLinux() ||
9099 Subtarget->isTargetDarwin()) &&
9100 "Unhandled target in LowerVAARG");
9101 assert(Op.getNode()->getNumOperands() == 4);
9102 SDValue Chain = Op.getOperand(0);
9103 SDValue SrcPtr = Op.getOperand(1);
9104 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9105 unsigned Align = Op.getConstantOperandVal(3);
9106 DebugLoc dl = Op.getDebugLoc();
9108 EVT ArgVT = Op.getNode()->getValueType(0);
9109 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9110 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9113 // Decide which area this value should be read from.
9114 // TODO: Implement the AMD64 ABI in its entirety. This simple
9115 // selection mechanism works only for the basic types.
9116 if (ArgVT == MVT::f80) {
9117 llvm_unreachable("va_arg for f80 not yet implemented");
9118 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9119 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9120 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9121 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9123 llvm_unreachable("Unhandled argument type in LowerVAARG");
9127 // Sanity Check: Make sure using fp_offset makes sense.
9128 assert(!getTargetMachine().Options.UseSoftFloat &&
9129 !(DAG.getMachineFunction()
9130 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9131 Subtarget->hasSSE1());
9134 // Insert VAARG_64 node into the DAG
9135 // VAARG_64 returns two values: Variable Argument Address, Chain
9136 SmallVector<SDValue, 11> InstOps;
9137 InstOps.push_back(Chain);
9138 InstOps.push_back(SrcPtr);
9139 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9140 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9141 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9142 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9143 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9144 VTs, &InstOps[0], InstOps.size(),
9146 MachinePointerInfo(SV),
9151 Chain = VAARG.getValue(1);
9153 // Load the next argument and return it
9154 return DAG.getLoad(ArgVT, dl,
9157 MachinePointerInfo(),
9158 false, false, false, 0);
9161 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9162 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9163 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9164 SDValue Chain = Op.getOperand(0);
9165 SDValue DstPtr = Op.getOperand(1);
9166 SDValue SrcPtr = Op.getOperand(2);
9167 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9168 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9169 DebugLoc DL = Op.getDebugLoc();
9171 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9172 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9174 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9178 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9179 DebugLoc dl = Op.getDebugLoc();
9180 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9182 default: return SDValue(); // Don't custom lower most intrinsics.
9183 // Comparison intrinsics.
9184 case Intrinsic::x86_sse_comieq_ss:
9185 case Intrinsic::x86_sse_comilt_ss:
9186 case Intrinsic::x86_sse_comile_ss:
9187 case Intrinsic::x86_sse_comigt_ss:
9188 case Intrinsic::x86_sse_comige_ss:
9189 case Intrinsic::x86_sse_comineq_ss:
9190 case Intrinsic::x86_sse_ucomieq_ss:
9191 case Intrinsic::x86_sse_ucomilt_ss:
9192 case Intrinsic::x86_sse_ucomile_ss:
9193 case Intrinsic::x86_sse_ucomigt_ss:
9194 case Intrinsic::x86_sse_ucomige_ss:
9195 case Intrinsic::x86_sse_ucomineq_ss:
9196 case Intrinsic::x86_sse2_comieq_sd:
9197 case Intrinsic::x86_sse2_comilt_sd:
9198 case Intrinsic::x86_sse2_comile_sd:
9199 case Intrinsic::x86_sse2_comigt_sd:
9200 case Intrinsic::x86_sse2_comige_sd:
9201 case Intrinsic::x86_sse2_comineq_sd:
9202 case Intrinsic::x86_sse2_ucomieq_sd:
9203 case Intrinsic::x86_sse2_ucomilt_sd:
9204 case Intrinsic::x86_sse2_ucomile_sd:
9205 case Intrinsic::x86_sse2_ucomigt_sd:
9206 case Intrinsic::x86_sse2_ucomige_sd:
9207 case Intrinsic::x86_sse2_ucomineq_sd: {
9209 ISD::CondCode CC = ISD::SETCC_INVALID;
9212 case Intrinsic::x86_sse_comieq_ss:
9213 case Intrinsic::x86_sse2_comieq_sd:
9217 case Intrinsic::x86_sse_comilt_ss:
9218 case Intrinsic::x86_sse2_comilt_sd:
9222 case Intrinsic::x86_sse_comile_ss:
9223 case Intrinsic::x86_sse2_comile_sd:
9227 case Intrinsic::x86_sse_comigt_ss:
9228 case Intrinsic::x86_sse2_comigt_sd:
9232 case Intrinsic::x86_sse_comige_ss:
9233 case Intrinsic::x86_sse2_comige_sd:
9237 case Intrinsic::x86_sse_comineq_ss:
9238 case Intrinsic::x86_sse2_comineq_sd:
9242 case Intrinsic::x86_sse_ucomieq_ss:
9243 case Intrinsic::x86_sse2_ucomieq_sd:
9244 Opc = X86ISD::UCOMI;
9247 case Intrinsic::x86_sse_ucomilt_ss:
9248 case Intrinsic::x86_sse2_ucomilt_sd:
9249 Opc = X86ISD::UCOMI;
9252 case Intrinsic::x86_sse_ucomile_ss:
9253 case Intrinsic::x86_sse2_ucomile_sd:
9254 Opc = X86ISD::UCOMI;
9257 case Intrinsic::x86_sse_ucomigt_ss:
9258 case Intrinsic::x86_sse2_ucomigt_sd:
9259 Opc = X86ISD::UCOMI;
9262 case Intrinsic::x86_sse_ucomige_ss:
9263 case Intrinsic::x86_sse2_ucomige_sd:
9264 Opc = X86ISD::UCOMI;
9267 case Intrinsic::x86_sse_ucomineq_ss:
9268 case Intrinsic::x86_sse2_ucomineq_sd:
9269 Opc = X86ISD::UCOMI;
9274 SDValue LHS = Op.getOperand(1);
9275 SDValue RHS = Op.getOperand(2);
9276 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9277 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9278 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9279 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9280 DAG.getConstant(X86CC, MVT::i8), Cond);
9281 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9283 // Arithmetic intrinsics.
9284 case Intrinsic::x86_sse3_hadd_ps:
9285 case Intrinsic::x86_sse3_hadd_pd:
9286 case Intrinsic::x86_avx_hadd_ps_256:
9287 case Intrinsic::x86_avx_hadd_pd_256:
9288 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9289 Op.getOperand(1), Op.getOperand(2));
9290 case Intrinsic::x86_sse3_hsub_ps:
9291 case Intrinsic::x86_sse3_hsub_pd:
9292 case Intrinsic::x86_avx_hsub_ps_256:
9293 case Intrinsic::x86_avx_hsub_pd_256:
9294 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9295 Op.getOperand(1), Op.getOperand(2));
9296 case Intrinsic::x86_avx2_psllv_d:
9297 case Intrinsic::x86_avx2_psllv_q:
9298 case Intrinsic::x86_avx2_psllv_d_256:
9299 case Intrinsic::x86_avx2_psllv_q_256:
9300 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9301 Op.getOperand(1), Op.getOperand(2));
9302 case Intrinsic::x86_avx2_psrlv_d:
9303 case Intrinsic::x86_avx2_psrlv_q:
9304 case Intrinsic::x86_avx2_psrlv_d_256:
9305 case Intrinsic::x86_avx2_psrlv_q_256:
9306 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9307 Op.getOperand(1), Op.getOperand(2));
9308 case Intrinsic::x86_avx2_psrav_d:
9309 case Intrinsic::x86_avx2_psrav_d_256:
9310 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9311 Op.getOperand(1), Op.getOperand(2));
9313 // ptest and testp intrinsics. The intrinsic these come from are designed to
9314 // return an integer value, not just an instruction so lower it to the ptest
9315 // or testp pattern and a setcc for the result.
9316 case Intrinsic::x86_sse41_ptestz:
9317 case Intrinsic::x86_sse41_ptestc:
9318 case Intrinsic::x86_sse41_ptestnzc:
9319 case Intrinsic::x86_avx_ptestz_256:
9320 case Intrinsic::x86_avx_ptestc_256:
9321 case Intrinsic::x86_avx_ptestnzc_256:
9322 case Intrinsic::x86_avx_vtestz_ps:
9323 case Intrinsic::x86_avx_vtestc_ps:
9324 case Intrinsic::x86_avx_vtestnzc_ps:
9325 case Intrinsic::x86_avx_vtestz_pd:
9326 case Intrinsic::x86_avx_vtestc_pd:
9327 case Intrinsic::x86_avx_vtestnzc_pd:
9328 case Intrinsic::x86_avx_vtestz_ps_256:
9329 case Intrinsic::x86_avx_vtestc_ps_256:
9330 case Intrinsic::x86_avx_vtestnzc_ps_256:
9331 case Intrinsic::x86_avx_vtestz_pd_256:
9332 case Intrinsic::x86_avx_vtestc_pd_256:
9333 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9334 bool IsTestPacked = false;
9337 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9338 case Intrinsic::x86_avx_vtestz_ps:
9339 case Intrinsic::x86_avx_vtestz_pd:
9340 case Intrinsic::x86_avx_vtestz_ps_256:
9341 case Intrinsic::x86_avx_vtestz_pd_256:
9342 IsTestPacked = true; // Fallthrough
9343 case Intrinsic::x86_sse41_ptestz:
9344 case Intrinsic::x86_avx_ptestz_256:
9346 X86CC = X86::COND_E;
9348 case Intrinsic::x86_avx_vtestc_ps:
9349 case Intrinsic::x86_avx_vtestc_pd:
9350 case Intrinsic::x86_avx_vtestc_ps_256:
9351 case Intrinsic::x86_avx_vtestc_pd_256:
9352 IsTestPacked = true; // Fallthrough
9353 case Intrinsic::x86_sse41_ptestc:
9354 case Intrinsic::x86_avx_ptestc_256:
9356 X86CC = X86::COND_B;
9358 case Intrinsic::x86_avx_vtestnzc_ps:
9359 case Intrinsic::x86_avx_vtestnzc_pd:
9360 case Intrinsic::x86_avx_vtestnzc_ps_256:
9361 case Intrinsic::x86_avx_vtestnzc_pd_256:
9362 IsTestPacked = true; // Fallthrough
9363 case Intrinsic::x86_sse41_ptestnzc:
9364 case Intrinsic::x86_avx_ptestnzc_256:
9366 X86CC = X86::COND_A;
9370 SDValue LHS = Op.getOperand(1);
9371 SDValue RHS = Op.getOperand(2);
9372 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9373 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9374 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9375 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9376 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9379 // Fix vector shift instructions where the last operand is a non-immediate
9381 case Intrinsic::x86_avx2_pslli_w:
9382 case Intrinsic::x86_avx2_pslli_d:
9383 case Intrinsic::x86_avx2_pslli_q:
9384 case Intrinsic::x86_avx2_psrli_w:
9385 case Intrinsic::x86_avx2_psrli_d:
9386 case Intrinsic::x86_avx2_psrli_q:
9387 case Intrinsic::x86_avx2_psrai_w:
9388 case Intrinsic::x86_avx2_psrai_d:
9389 case Intrinsic::x86_sse2_pslli_w:
9390 case Intrinsic::x86_sse2_pslli_d:
9391 case Intrinsic::x86_sse2_pslli_q:
9392 case Intrinsic::x86_sse2_psrli_w:
9393 case Intrinsic::x86_sse2_psrli_d:
9394 case Intrinsic::x86_sse2_psrli_q:
9395 case Intrinsic::x86_sse2_psrai_w:
9396 case Intrinsic::x86_sse2_psrai_d:
9397 case Intrinsic::x86_mmx_pslli_w:
9398 case Intrinsic::x86_mmx_pslli_d:
9399 case Intrinsic::x86_mmx_pslli_q:
9400 case Intrinsic::x86_mmx_psrli_w:
9401 case Intrinsic::x86_mmx_psrli_d:
9402 case Intrinsic::x86_mmx_psrli_q:
9403 case Intrinsic::x86_mmx_psrai_w:
9404 case Intrinsic::x86_mmx_psrai_d: {
9405 SDValue ShAmt = Op.getOperand(2);
9406 if (isa<ConstantSDNode>(ShAmt))
9409 unsigned NewIntNo = 0;
9410 EVT ShAmtVT = MVT::v4i32;
9412 case Intrinsic::x86_sse2_pslli_w:
9413 NewIntNo = Intrinsic::x86_sse2_psll_w;
9415 case Intrinsic::x86_sse2_pslli_d:
9416 NewIntNo = Intrinsic::x86_sse2_psll_d;
9418 case Intrinsic::x86_sse2_pslli_q:
9419 NewIntNo = Intrinsic::x86_sse2_psll_q;
9421 case Intrinsic::x86_sse2_psrli_w:
9422 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9424 case Intrinsic::x86_sse2_psrli_d:
9425 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9427 case Intrinsic::x86_sse2_psrli_q:
9428 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9430 case Intrinsic::x86_sse2_psrai_w:
9431 NewIntNo = Intrinsic::x86_sse2_psra_w;
9433 case Intrinsic::x86_sse2_psrai_d:
9434 NewIntNo = Intrinsic::x86_sse2_psra_d;
9436 case Intrinsic::x86_avx2_pslli_w:
9437 NewIntNo = Intrinsic::x86_avx2_psll_w;
9439 case Intrinsic::x86_avx2_pslli_d:
9440 NewIntNo = Intrinsic::x86_avx2_psll_d;
9442 case Intrinsic::x86_avx2_pslli_q:
9443 NewIntNo = Intrinsic::x86_avx2_psll_q;
9445 case Intrinsic::x86_avx2_psrli_w:
9446 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9448 case Intrinsic::x86_avx2_psrli_d:
9449 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9451 case Intrinsic::x86_avx2_psrli_q:
9452 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9454 case Intrinsic::x86_avx2_psrai_w:
9455 NewIntNo = Intrinsic::x86_avx2_psra_w;
9457 case Intrinsic::x86_avx2_psrai_d:
9458 NewIntNo = Intrinsic::x86_avx2_psra_d;
9461 ShAmtVT = MVT::v2i32;
9463 case Intrinsic::x86_mmx_pslli_w:
9464 NewIntNo = Intrinsic::x86_mmx_psll_w;
9466 case Intrinsic::x86_mmx_pslli_d:
9467 NewIntNo = Intrinsic::x86_mmx_psll_d;
9469 case Intrinsic::x86_mmx_pslli_q:
9470 NewIntNo = Intrinsic::x86_mmx_psll_q;
9472 case Intrinsic::x86_mmx_psrli_w:
9473 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9475 case Intrinsic::x86_mmx_psrli_d:
9476 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9478 case Intrinsic::x86_mmx_psrli_q:
9479 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9481 case Intrinsic::x86_mmx_psrai_w:
9482 NewIntNo = Intrinsic::x86_mmx_psra_w;
9484 case Intrinsic::x86_mmx_psrai_d:
9485 NewIntNo = Intrinsic::x86_mmx_psra_d;
9487 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9493 // The vector shift intrinsics with scalars uses 32b shift amounts but
9494 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9498 ShOps[1] = DAG.getConstant(0, MVT::i32);
9499 if (ShAmtVT == MVT::v4i32) {
9500 ShOps[2] = DAG.getUNDEF(MVT::i32);
9501 ShOps[3] = DAG.getUNDEF(MVT::i32);
9502 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9504 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9505 // FIXME this must be lowered to get rid of the invalid type.
9508 EVT VT = Op.getValueType();
9509 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9510 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9511 DAG.getConstant(NewIntNo, MVT::i32),
9512 Op.getOperand(1), ShAmt);
9517 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9518 SelectionDAG &DAG) const {
9519 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9520 MFI->setReturnAddressIsTaken(true);
9522 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9523 DebugLoc dl = Op.getDebugLoc();
9526 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9528 DAG.getConstant(TD->getPointerSize(),
9529 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9530 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9531 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9533 MachinePointerInfo(), false, false, false, 0);
9536 // Just load the return address.
9537 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9538 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9539 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9542 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9543 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9544 MFI->setFrameAddressIsTaken(true);
9546 EVT VT = Op.getValueType();
9547 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9548 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9549 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9550 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9552 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9553 MachinePointerInfo(),
9554 false, false, false, 0);
9558 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9559 SelectionDAG &DAG) const {
9560 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9563 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9564 MachineFunction &MF = DAG.getMachineFunction();
9565 SDValue Chain = Op.getOperand(0);
9566 SDValue Offset = Op.getOperand(1);
9567 SDValue Handler = Op.getOperand(2);
9568 DebugLoc dl = Op.getDebugLoc();
9570 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9571 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9573 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9575 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9576 DAG.getIntPtrConstant(TD->getPointerSize()));
9577 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9578 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9580 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9581 MF.getRegInfo().addLiveOut(StoreAddrReg);
9583 return DAG.getNode(X86ISD::EH_RETURN, dl,
9585 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9588 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9589 SelectionDAG &DAG) const {
9590 return Op.getOperand(0);
9593 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9594 SelectionDAG &DAG) const {
9595 SDValue Root = Op.getOperand(0);
9596 SDValue Trmp = Op.getOperand(1); // trampoline
9597 SDValue FPtr = Op.getOperand(2); // nested function
9598 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9599 DebugLoc dl = Op.getDebugLoc();
9601 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9603 if (Subtarget->is64Bit()) {
9604 SDValue OutChains[6];
9606 // Large code-model.
9607 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9608 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9610 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9611 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9613 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9615 // Load the pointer to the nested function into R11.
9616 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9617 SDValue Addr = Trmp;
9618 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9619 Addr, MachinePointerInfo(TrmpAddr),
9622 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9623 DAG.getConstant(2, MVT::i64));
9624 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9625 MachinePointerInfo(TrmpAddr, 2),
9628 // Load the 'nest' parameter value into R10.
9629 // R10 is specified in X86CallingConv.td
9630 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9631 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9632 DAG.getConstant(10, MVT::i64));
9633 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9634 Addr, MachinePointerInfo(TrmpAddr, 10),
9637 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9638 DAG.getConstant(12, MVT::i64));
9639 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9640 MachinePointerInfo(TrmpAddr, 12),
9643 // Jump to the nested function.
9644 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9645 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9646 DAG.getConstant(20, MVT::i64));
9647 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9648 Addr, MachinePointerInfo(TrmpAddr, 20),
9651 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9652 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9653 DAG.getConstant(22, MVT::i64));
9654 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9655 MachinePointerInfo(TrmpAddr, 22),
9658 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9660 const Function *Func =
9661 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9662 CallingConv::ID CC = Func->getCallingConv();
9667 llvm_unreachable("Unsupported calling convention");
9668 case CallingConv::C:
9669 case CallingConv::X86_StdCall: {
9670 // Pass 'nest' parameter in ECX.
9671 // Must be kept in sync with X86CallingConv.td
9674 // Check that ECX wasn't needed by an 'inreg' parameter.
9675 FunctionType *FTy = Func->getFunctionType();
9676 const AttrListPtr &Attrs = Func->getAttributes();
9678 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9679 unsigned InRegCount = 0;
9682 for (FunctionType::param_iterator I = FTy->param_begin(),
9683 E = FTy->param_end(); I != E; ++I, ++Idx)
9684 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9685 // FIXME: should only count parameters that are lowered to integers.
9686 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9688 if (InRegCount > 2) {
9689 report_fatal_error("Nest register in use - reduce number of inreg"
9695 case CallingConv::X86_FastCall:
9696 case CallingConv::X86_ThisCall:
9697 case CallingConv::Fast:
9698 // Pass 'nest' parameter in EAX.
9699 // Must be kept in sync with X86CallingConv.td
9704 SDValue OutChains[4];
9707 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9708 DAG.getConstant(10, MVT::i32));
9709 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9711 // This is storing the opcode for MOV32ri.
9712 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9713 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9714 OutChains[0] = DAG.getStore(Root, dl,
9715 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9716 Trmp, MachinePointerInfo(TrmpAddr),
9719 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9720 DAG.getConstant(1, MVT::i32));
9721 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9722 MachinePointerInfo(TrmpAddr, 1),
9725 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9726 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9727 DAG.getConstant(5, MVT::i32));
9728 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9729 MachinePointerInfo(TrmpAddr, 5),
9732 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9733 DAG.getConstant(6, MVT::i32));
9734 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9735 MachinePointerInfo(TrmpAddr, 6),
9738 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9742 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9743 SelectionDAG &DAG) const {
9745 The rounding mode is in bits 11:10 of FPSR, and has the following
9752 FLT_ROUNDS, on the other hand, expects the following:
9759 To perform the conversion, we do:
9760 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9763 MachineFunction &MF = DAG.getMachineFunction();
9764 const TargetMachine &TM = MF.getTarget();
9765 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9766 unsigned StackAlignment = TFI.getStackAlignment();
9767 EVT VT = Op.getValueType();
9768 DebugLoc DL = Op.getDebugLoc();
9770 // Save FP Control Word to stack slot
9771 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9772 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9775 MachineMemOperand *MMO =
9776 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9777 MachineMemOperand::MOStore, 2, 2);
9779 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9780 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9781 DAG.getVTList(MVT::Other),
9782 Ops, 2, MVT::i16, MMO);
9784 // Load FP Control Word from stack slot
9785 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9786 MachinePointerInfo(), false, false, false, 0);
9788 // Transform as necessary
9790 DAG.getNode(ISD::SRL, DL, MVT::i16,
9791 DAG.getNode(ISD::AND, DL, MVT::i16,
9792 CWD, DAG.getConstant(0x800, MVT::i16)),
9793 DAG.getConstant(11, MVT::i8));
9795 DAG.getNode(ISD::SRL, DL, MVT::i16,
9796 DAG.getNode(ISD::AND, DL, MVT::i16,
9797 CWD, DAG.getConstant(0x400, MVT::i16)),
9798 DAG.getConstant(9, MVT::i8));
9801 DAG.getNode(ISD::AND, DL, MVT::i16,
9802 DAG.getNode(ISD::ADD, DL, MVT::i16,
9803 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9804 DAG.getConstant(1, MVT::i16)),
9805 DAG.getConstant(3, MVT::i16));
9808 return DAG.getNode((VT.getSizeInBits() < 16 ?
9809 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9812 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9813 EVT VT = Op.getValueType();
9815 unsigned NumBits = VT.getSizeInBits();
9816 DebugLoc dl = Op.getDebugLoc();
9818 Op = Op.getOperand(0);
9819 if (VT == MVT::i8) {
9820 // Zero extend to i32 since there is not an i8 bsr.
9822 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9825 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9826 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9827 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9829 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9832 DAG.getConstant(NumBits+NumBits-1, OpVT),
9833 DAG.getConstant(X86::COND_E, MVT::i8),
9836 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9838 // Finally xor with NumBits-1.
9839 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9842 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9846 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9847 SelectionDAG &DAG) const {
9848 EVT VT = Op.getValueType();
9850 unsigned NumBits = VT.getSizeInBits();
9851 DebugLoc dl = Op.getDebugLoc();
9853 Op = Op.getOperand(0);
9854 if (VT == MVT::i8) {
9855 // Zero extend to i32 since there is not an i8 bsr.
9857 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9860 // Issue a bsr (scan bits in reverse).
9861 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9862 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9864 // And xor with NumBits-1.
9865 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9868 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9872 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9873 EVT VT = Op.getValueType();
9874 unsigned NumBits = VT.getSizeInBits();
9875 DebugLoc dl = Op.getDebugLoc();
9876 Op = Op.getOperand(0);
9878 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9879 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9880 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9882 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9885 DAG.getConstant(NumBits, VT),
9886 DAG.getConstant(X86::COND_E, MVT::i8),
9889 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
9892 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9893 // ones, and then concatenate the result back.
9894 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9895 EVT VT = Op.getValueType();
9897 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9898 "Unsupported value type for operation");
9900 int NumElems = VT.getVectorNumElements();
9901 DebugLoc dl = Op.getDebugLoc();
9902 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9903 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9905 // Extract the LHS vectors
9906 SDValue LHS = Op.getOperand(0);
9907 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9908 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9910 // Extract the RHS vectors
9911 SDValue RHS = Op.getOperand(1);
9912 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9913 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9915 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9916 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9918 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9919 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9920 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9923 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9924 assert(Op.getValueType().getSizeInBits() == 256 &&
9925 Op.getValueType().isInteger() &&
9926 "Only handle AVX 256-bit vector integer operation");
9927 return Lower256IntArith(Op, DAG);
9930 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9931 assert(Op.getValueType().getSizeInBits() == 256 &&
9932 Op.getValueType().isInteger() &&
9933 "Only handle AVX 256-bit vector integer operation");
9934 return Lower256IntArith(Op, DAG);
9937 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9938 EVT VT = Op.getValueType();
9940 // Decompose 256-bit ops into smaller 128-bit ops.
9941 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9942 return Lower256IntArith(Op, DAG);
9944 DebugLoc dl = Op.getDebugLoc();
9946 SDValue A = Op.getOperand(0);
9947 SDValue B = Op.getOperand(1);
9949 if (VT == MVT::v4i64) {
9950 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9952 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9953 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9954 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9955 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9956 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9958 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9959 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9960 // return AloBlo + AloBhi + AhiBlo;
9962 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9963 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9964 A, DAG.getConstant(32, MVT::i32));
9965 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9966 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9967 B, DAG.getConstant(32, MVT::i32));
9968 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9969 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9971 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9972 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9974 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9975 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9977 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9978 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9979 AloBhi, DAG.getConstant(32, MVT::i32));
9980 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9981 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9982 AhiBlo, DAG.getConstant(32, MVT::i32));
9983 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9984 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9988 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9990 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9991 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9992 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9993 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9994 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9996 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9997 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9998 // return AloBlo + AloBhi + AhiBlo;
10000 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10001 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10002 A, DAG.getConstant(32, MVT::i32));
10003 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10004 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10005 B, DAG.getConstant(32, MVT::i32));
10006 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10007 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10009 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10010 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10012 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10013 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10015 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10016 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10017 AloBhi, DAG.getConstant(32, MVT::i32));
10018 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10019 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10020 AhiBlo, DAG.getConstant(32, MVT::i32));
10021 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10022 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10026 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10028 EVT VT = Op.getValueType();
10029 DebugLoc dl = Op.getDebugLoc();
10030 SDValue R = Op.getOperand(0);
10031 SDValue Amt = Op.getOperand(1);
10032 LLVMContext *Context = DAG.getContext();
10034 if (!Subtarget->hasSSE2())
10037 // Optimize shl/srl/sra with constant shift amount.
10038 if (isSplatVector(Amt.getNode())) {
10039 SDValue SclrAmt = Amt->getOperand(0);
10040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10041 uint64_t ShiftAmt = C->getZExtValue();
10043 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10044 // Make a large shift.
10046 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10047 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10048 R, DAG.getConstant(ShiftAmt, MVT::i32));
10049 // Zero out the rightmost bits.
10050 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10052 return DAG.getNode(ISD::AND, dl, VT, SHL,
10053 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10056 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10057 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10058 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10059 R, DAG.getConstant(ShiftAmt, MVT::i32));
10061 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10062 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10063 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10064 R, DAG.getConstant(ShiftAmt, MVT::i32));
10066 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10067 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10068 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10069 R, DAG.getConstant(ShiftAmt, MVT::i32));
10071 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10072 // Make a large shift.
10074 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10075 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10076 R, DAG.getConstant(ShiftAmt, MVT::i32));
10077 // Zero out the leftmost bits.
10078 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10080 return DAG.getNode(ISD::AND, dl, VT, SRL,
10081 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10084 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10086 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10087 R, DAG.getConstant(ShiftAmt, MVT::i32));
10089 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10090 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10091 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10092 R, DAG.getConstant(ShiftAmt, MVT::i32));
10094 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10096 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10097 R, DAG.getConstant(ShiftAmt, MVT::i32));
10099 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10100 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10101 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10102 R, DAG.getConstant(ShiftAmt, MVT::i32));
10104 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10106 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10107 R, DAG.getConstant(ShiftAmt, MVT::i32));
10109 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10110 if (ShiftAmt == 7) {
10111 // R s>> 7 === R s< 0
10112 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10113 /* HasAVX2 */false, DAG, dl);
10114 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10117 // R s>> a === ((R u>> a) ^ m) - m
10118 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10119 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10121 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10122 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10123 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10127 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10128 if (Op.getOpcode() == ISD::SHL) {
10129 // Make a large shift.
10131 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10132 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10133 R, DAG.getConstant(ShiftAmt, MVT::i32));
10134 // Zero out the rightmost bits.
10135 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10137 return DAG.getNode(ISD::AND, dl, VT, SHL,
10138 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10140 if (Op.getOpcode() == ISD::SRL) {
10141 // Make a large shift.
10143 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10144 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10145 R, DAG.getConstant(ShiftAmt, MVT::i32));
10146 // Zero out the leftmost bits.
10147 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10149 return DAG.getNode(ISD::AND, dl, VT, SRL,
10150 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10152 if (Op.getOpcode() == ISD::SRA) {
10153 if (ShiftAmt == 7) {
10154 // R s>> 7 === R s< 0
10155 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10156 true /* HasAVX2 */, DAG, dl);
10157 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10160 // R s>> a === ((R u>> a) ^ m) - m
10161 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10162 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10164 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10165 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10166 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10173 // Lower SHL with variable shift amount.
10174 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10175 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10176 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10177 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10179 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10181 std::vector<Constant*> CV(4, CI);
10182 Constant *C = ConstantVector::get(CV);
10183 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10184 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10185 MachinePointerInfo::getConstantPool(),
10186 false, false, false, 16);
10188 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10189 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10190 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10191 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10193 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10194 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10197 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10198 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10199 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10201 // Turn 'a' into a mask suitable for VSELECT
10202 SDValue VSelM = DAG.getConstant(0x80, VT);
10203 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10204 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10205 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10208 SDValue CM1 = DAG.getConstant(0x0f, VT);
10209 SDValue CM2 = DAG.getConstant(0x3f, VT);
10211 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10212 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10213 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10214 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10215 DAG.getConstant(4, MVT::i32));
10216 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10219 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10220 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10221 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10222 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10225 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10226 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10227 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10228 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10229 DAG.getConstant(2, MVT::i32));
10230 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10233 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10234 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10235 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10236 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10239 // return VSELECT(r, r+r, a);
10240 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10241 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10245 // Decompose 256-bit shifts into smaller 128-bit shifts.
10246 if (VT.getSizeInBits() == 256) {
10247 int NumElems = VT.getVectorNumElements();
10248 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10249 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10251 // Extract the two vectors
10252 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10253 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10256 // Recreate the shift amount vectors
10257 SDValue Amt1, Amt2;
10258 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10259 // Constant shift amount
10260 SmallVector<SDValue, 4> Amt1Csts;
10261 SmallVector<SDValue, 4> Amt2Csts;
10262 for (int i = 0; i < NumElems/2; ++i)
10263 Amt1Csts.push_back(Amt->getOperand(i));
10264 for (int i = NumElems/2; i < NumElems; ++i)
10265 Amt2Csts.push_back(Amt->getOperand(i));
10267 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10268 &Amt1Csts[0], NumElems/2);
10269 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10270 &Amt2Csts[0], NumElems/2);
10272 // Variable shift amount
10273 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10274 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10278 // Issue new vector shifts for the smaller types
10279 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10280 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10282 // Concatenate the result back
10283 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10289 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10290 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10291 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10292 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10293 // has only one use.
10294 SDNode *N = Op.getNode();
10295 SDValue LHS = N->getOperand(0);
10296 SDValue RHS = N->getOperand(1);
10297 unsigned BaseOp = 0;
10299 DebugLoc DL = Op.getDebugLoc();
10300 switch (Op.getOpcode()) {
10301 default: llvm_unreachable("Unknown ovf instruction!");
10303 // A subtract of one will be selected as a INC. Note that INC doesn't
10304 // set CF, so we can't do this for UADDO.
10305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10307 BaseOp = X86ISD::INC;
10308 Cond = X86::COND_O;
10311 BaseOp = X86ISD::ADD;
10312 Cond = X86::COND_O;
10315 BaseOp = X86ISD::ADD;
10316 Cond = X86::COND_B;
10319 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10320 // set CF, so we can't do this for USUBO.
10321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10323 BaseOp = X86ISD::DEC;
10324 Cond = X86::COND_O;
10327 BaseOp = X86ISD::SUB;
10328 Cond = X86::COND_O;
10331 BaseOp = X86ISD::SUB;
10332 Cond = X86::COND_B;
10335 BaseOp = X86ISD::SMUL;
10336 Cond = X86::COND_O;
10338 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10339 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10341 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10344 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10345 DAG.getConstant(X86::COND_O, MVT::i32),
10346 SDValue(Sum.getNode(), 2));
10348 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10352 // Also sets EFLAGS.
10353 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10354 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10357 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10358 DAG.getConstant(Cond, MVT::i32),
10359 SDValue(Sum.getNode(), 1));
10361 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10364 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10365 SelectionDAG &DAG) const {
10366 DebugLoc dl = Op.getDebugLoc();
10367 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10368 EVT VT = Op.getValueType();
10370 if (Subtarget->hasSSE2() && VT.isVector()) {
10371 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10372 ExtraVT.getScalarType().getSizeInBits();
10373 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10375 unsigned SHLIntrinsicsID = 0;
10376 unsigned SRAIntrinsicsID = 0;
10377 switch (VT.getSimpleVT().SimpleTy) {
10381 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10382 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10385 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10386 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10390 if (!Subtarget->hasAVX())
10392 if (!Subtarget->hasAVX2()) {
10393 // needs to be split
10394 int NumElems = VT.getVectorNumElements();
10395 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10396 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10398 // Extract the LHS vectors
10399 SDValue LHS = Op.getOperand(0);
10400 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10401 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10403 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10404 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10406 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10407 int ExtraNumElems = ExtraVT.getVectorNumElements();
10408 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10410 SDValue Extra = DAG.getValueType(ExtraVT);
10412 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10413 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10415 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10417 if (VT == MVT::v8i32) {
10418 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10419 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10421 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10422 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10426 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10427 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10428 Op.getOperand(0), ShAmt);
10430 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10431 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10439 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10440 DebugLoc dl = Op.getDebugLoc();
10442 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10443 // There isn't any reason to disable it if the target processor supports it.
10444 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10445 SDValue Chain = Op.getOperand(0);
10446 SDValue Zero = DAG.getConstant(0, MVT::i32);
10448 DAG.getRegister(X86::ESP, MVT::i32), // Base
10449 DAG.getTargetConstant(1, MVT::i8), // Scale
10450 DAG.getRegister(0, MVT::i32), // Index
10451 DAG.getTargetConstant(0, MVT::i32), // Disp
10452 DAG.getRegister(0, MVT::i32), // Segment.
10457 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10458 array_lengthof(Ops));
10459 return SDValue(Res, 0);
10462 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10464 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10466 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10467 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10468 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10469 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10471 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10472 if (!Op1 && !Op2 && !Op3 && Op4)
10473 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10475 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10476 if (Op1 && !Op2 && !Op3 && !Op4)
10477 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10479 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10481 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10484 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10485 SelectionDAG &DAG) const {
10486 DebugLoc dl = Op.getDebugLoc();
10487 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10488 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10489 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10490 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10492 // The only fence that needs an instruction is a sequentially-consistent
10493 // cross-thread fence.
10494 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10495 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10496 // no-sse2). There isn't any reason to disable it if the target processor
10498 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10499 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10501 SDValue Chain = Op.getOperand(0);
10502 SDValue Zero = DAG.getConstant(0, MVT::i32);
10504 DAG.getRegister(X86::ESP, MVT::i32), // Base
10505 DAG.getTargetConstant(1, MVT::i8), // Scale
10506 DAG.getRegister(0, MVT::i32), // Index
10507 DAG.getTargetConstant(0, MVT::i32), // Disp
10508 DAG.getRegister(0, MVT::i32), // Segment.
10513 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10514 array_lengthof(Ops));
10515 return SDValue(Res, 0);
10518 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10519 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10523 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10524 EVT T = Op.getValueType();
10525 DebugLoc DL = Op.getDebugLoc();
10528 switch(T.getSimpleVT().SimpleTy) {
10530 assert(false && "Invalid value type!");
10531 case MVT::i8: Reg = X86::AL; size = 1; break;
10532 case MVT::i16: Reg = X86::AX; size = 2; break;
10533 case MVT::i32: Reg = X86::EAX; size = 4; break;
10535 assert(Subtarget->is64Bit() && "Node not type legal!");
10536 Reg = X86::RAX; size = 8;
10539 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10540 Op.getOperand(2), SDValue());
10541 SDValue Ops[] = { cpIn.getValue(0),
10544 DAG.getTargetConstant(size, MVT::i8),
10545 cpIn.getValue(1) };
10546 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10547 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10548 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10551 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10555 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10556 SelectionDAG &DAG) const {
10557 assert(Subtarget->is64Bit() && "Result not type legalized?");
10558 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10559 SDValue TheChain = Op.getOperand(0);
10560 DebugLoc dl = Op.getDebugLoc();
10561 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10562 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10563 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10565 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10566 DAG.getConstant(32, MVT::i8));
10568 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10571 return DAG.getMergeValues(Ops, 2, dl);
10574 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10575 SelectionDAG &DAG) const {
10576 EVT SrcVT = Op.getOperand(0).getValueType();
10577 EVT DstVT = Op.getValueType();
10578 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10579 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10580 assert((DstVT == MVT::i64 ||
10581 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10582 "Unexpected custom BITCAST");
10583 // i64 <=> MMX conversions are Legal.
10584 if (SrcVT==MVT::i64 && DstVT.isVector())
10586 if (DstVT==MVT::i64 && SrcVT.isVector())
10588 // MMX <=> MMX conversions are Legal.
10589 if (SrcVT.isVector() && DstVT.isVector())
10591 // All other conversions need to be expanded.
10595 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10596 SDNode *Node = Op.getNode();
10597 DebugLoc dl = Node->getDebugLoc();
10598 EVT T = Node->getValueType(0);
10599 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10600 DAG.getConstant(0, T), Node->getOperand(2));
10601 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10602 cast<AtomicSDNode>(Node)->getMemoryVT(),
10603 Node->getOperand(0),
10604 Node->getOperand(1), negOp,
10605 cast<AtomicSDNode>(Node)->getSrcValue(),
10606 cast<AtomicSDNode>(Node)->getAlignment(),
10607 cast<AtomicSDNode>(Node)->getOrdering(),
10608 cast<AtomicSDNode>(Node)->getSynchScope());
10611 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10612 SDNode *Node = Op.getNode();
10613 DebugLoc dl = Node->getDebugLoc();
10614 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10616 // Convert seq_cst store -> xchg
10617 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10618 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10619 // (The only way to get a 16-byte store is cmpxchg16b)
10620 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10621 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10622 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10623 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10624 cast<AtomicSDNode>(Node)->getMemoryVT(),
10625 Node->getOperand(0),
10626 Node->getOperand(1), Node->getOperand(2),
10627 cast<AtomicSDNode>(Node)->getMemOperand(),
10628 cast<AtomicSDNode>(Node)->getOrdering(),
10629 cast<AtomicSDNode>(Node)->getSynchScope());
10630 return Swap.getValue(1);
10632 // Other atomic stores have a simple pattern.
10636 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10637 EVT VT = Op.getNode()->getValueType(0);
10639 // Let legalize expand this if it isn't a legal type yet.
10640 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10643 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10646 bool ExtraOp = false;
10647 switch (Op.getOpcode()) {
10648 default: assert(0 && "Invalid code");
10649 case ISD::ADDC: Opc = X86ISD::ADD; break;
10650 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10651 case ISD::SUBC: Opc = X86ISD::SUB; break;
10652 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10656 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10658 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10659 Op.getOperand(1), Op.getOperand(2));
10662 /// LowerOperation - Provide custom lowering hooks for some operations.
10664 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10665 switch (Op.getOpcode()) {
10666 default: llvm_unreachable("Should not custom lower this!");
10667 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10668 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10669 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10670 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10671 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10672 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10673 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10674 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10675 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10676 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10677 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10678 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10679 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10680 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10681 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10682 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10683 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10684 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10685 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10686 case ISD::SHL_PARTS:
10687 case ISD::SRA_PARTS:
10688 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10689 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10690 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10691 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10692 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10693 case ISD::FABS: return LowerFABS(Op, DAG);
10694 case ISD::FNEG: return LowerFNEG(Op, DAG);
10695 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10696 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10697 case ISD::SETCC: return LowerSETCC(Op, DAG);
10698 case ISD::SELECT: return LowerSELECT(Op, DAG);
10699 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10700 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10701 case ISD::VASTART: return LowerVASTART(Op, DAG);
10702 case ISD::VAARG: return LowerVAARG(Op, DAG);
10703 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10704 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10705 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10706 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10707 case ISD::FRAME_TO_ARGS_OFFSET:
10708 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10709 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10710 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10711 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10712 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10713 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10714 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10715 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10716 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10717 case ISD::MUL: return LowerMUL(Op, DAG);
10720 case ISD::SHL: return LowerShift(Op, DAG);
10726 case ISD::UMULO: return LowerXALUO(Op, DAG);
10727 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10728 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10732 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10733 case ISD::ADD: return LowerADD(Op, DAG);
10734 case ISD::SUB: return LowerSUB(Op, DAG);
10738 static void ReplaceATOMIC_LOAD(SDNode *Node,
10739 SmallVectorImpl<SDValue> &Results,
10740 SelectionDAG &DAG) {
10741 DebugLoc dl = Node->getDebugLoc();
10742 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10744 // Convert wide load -> cmpxchg8b/cmpxchg16b
10745 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10746 // (The only way to get a 16-byte load is cmpxchg16b)
10747 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10748 SDValue Zero = DAG.getConstant(0, VT);
10749 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10750 Node->getOperand(0),
10751 Node->getOperand(1), Zero, Zero,
10752 cast<AtomicSDNode>(Node)->getMemOperand(),
10753 cast<AtomicSDNode>(Node)->getOrdering(),
10754 cast<AtomicSDNode>(Node)->getSynchScope());
10755 Results.push_back(Swap.getValue(0));
10756 Results.push_back(Swap.getValue(1));
10759 void X86TargetLowering::
10760 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10761 SelectionDAG &DAG, unsigned NewOp) const {
10762 DebugLoc dl = Node->getDebugLoc();
10763 assert (Node->getValueType(0) == MVT::i64 &&
10764 "Only know how to expand i64 atomics");
10766 SDValue Chain = Node->getOperand(0);
10767 SDValue In1 = Node->getOperand(1);
10768 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10769 Node->getOperand(2), DAG.getIntPtrConstant(0));
10770 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10771 Node->getOperand(2), DAG.getIntPtrConstant(1));
10772 SDValue Ops[] = { Chain, In1, In2L, In2H };
10773 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10775 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10776 cast<MemSDNode>(Node)->getMemOperand());
10777 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10778 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10779 Results.push_back(Result.getValue(2));
10782 /// ReplaceNodeResults - Replace a node with an illegal result type
10783 /// with a new node built out of custom code.
10784 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10785 SmallVectorImpl<SDValue>&Results,
10786 SelectionDAG &DAG) const {
10787 DebugLoc dl = N->getDebugLoc();
10788 switch (N->getOpcode()) {
10790 assert(false && "Do not know how to custom type legalize this operation!");
10792 case ISD::SIGN_EXTEND_INREG:
10797 // We don't want to expand or promote these.
10799 case ISD::FP_TO_SINT: {
10800 std::pair<SDValue,SDValue> Vals =
10801 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10802 SDValue FIST = Vals.first, StackSlot = Vals.second;
10803 if (FIST.getNode() != 0) {
10804 EVT VT = N->getValueType(0);
10805 // Return a load from the stack slot.
10806 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10807 MachinePointerInfo(),
10808 false, false, false, 0));
10812 case ISD::READCYCLECOUNTER: {
10813 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10814 SDValue TheChain = N->getOperand(0);
10815 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10816 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10818 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10820 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10821 SDValue Ops[] = { eax, edx };
10822 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10823 Results.push_back(edx.getValue(1));
10826 case ISD::ATOMIC_CMP_SWAP: {
10827 EVT T = N->getValueType(0);
10828 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10829 bool Regs64bit = T == MVT::i128;
10830 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10831 SDValue cpInL, cpInH;
10832 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10833 DAG.getConstant(0, HalfT));
10834 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10835 DAG.getConstant(1, HalfT));
10836 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10837 Regs64bit ? X86::RAX : X86::EAX,
10839 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10840 Regs64bit ? X86::RDX : X86::EDX,
10841 cpInH, cpInL.getValue(1));
10842 SDValue swapInL, swapInH;
10843 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10844 DAG.getConstant(0, HalfT));
10845 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10846 DAG.getConstant(1, HalfT));
10847 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10848 Regs64bit ? X86::RBX : X86::EBX,
10849 swapInL, cpInH.getValue(1));
10850 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10851 Regs64bit ? X86::RCX : X86::ECX,
10852 swapInH, swapInL.getValue(1));
10853 SDValue Ops[] = { swapInH.getValue(0),
10855 swapInH.getValue(1) };
10856 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10857 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10858 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10859 X86ISD::LCMPXCHG8_DAG;
10860 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10862 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10863 Regs64bit ? X86::RAX : X86::EAX,
10864 HalfT, Result.getValue(1));
10865 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10866 Regs64bit ? X86::RDX : X86::EDX,
10867 HalfT, cpOutL.getValue(2));
10868 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10869 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10870 Results.push_back(cpOutH.getValue(1));
10873 case ISD::ATOMIC_LOAD_ADD:
10874 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10876 case ISD::ATOMIC_LOAD_AND:
10877 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10879 case ISD::ATOMIC_LOAD_NAND:
10880 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10882 case ISD::ATOMIC_LOAD_OR:
10883 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10885 case ISD::ATOMIC_LOAD_SUB:
10886 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10888 case ISD::ATOMIC_LOAD_XOR:
10889 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10891 case ISD::ATOMIC_SWAP:
10892 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10894 case ISD::ATOMIC_LOAD:
10895 ReplaceATOMIC_LOAD(N, Results, DAG);
10899 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10901 default: return NULL;
10902 case X86ISD::BSF: return "X86ISD::BSF";
10903 case X86ISD::BSR: return "X86ISD::BSR";
10904 case X86ISD::SHLD: return "X86ISD::SHLD";
10905 case X86ISD::SHRD: return "X86ISD::SHRD";
10906 case X86ISD::FAND: return "X86ISD::FAND";
10907 case X86ISD::FOR: return "X86ISD::FOR";
10908 case X86ISD::FXOR: return "X86ISD::FXOR";
10909 case X86ISD::FSRL: return "X86ISD::FSRL";
10910 case X86ISD::FILD: return "X86ISD::FILD";
10911 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10912 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10913 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10914 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10915 case X86ISD::FLD: return "X86ISD::FLD";
10916 case X86ISD::FST: return "X86ISD::FST";
10917 case X86ISD::CALL: return "X86ISD::CALL";
10918 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10919 case X86ISD::BT: return "X86ISD::BT";
10920 case X86ISD::CMP: return "X86ISD::CMP";
10921 case X86ISD::COMI: return "X86ISD::COMI";
10922 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10923 case X86ISD::SETCC: return "X86ISD::SETCC";
10924 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10925 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10926 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10927 case X86ISD::CMOV: return "X86ISD::CMOV";
10928 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10929 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10930 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10931 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10932 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10933 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10934 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10935 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10936 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10937 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10938 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10939 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10940 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10941 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10942 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10943 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10944 case X86ISD::HADD: return "X86ISD::HADD";
10945 case X86ISD::HSUB: return "X86ISD::HSUB";
10946 case X86ISD::FHADD: return "X86ISD::FHADD";
10947 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10948 case X86ISD::FMAX: return "X86ISD::FMAX";
10949 case X86ISD::FMIN: return "X86ISD::FMIN";
10950 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10951 case X86ISD::FRCP: return "X86ISD::FRCP";
10952 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10953 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10954 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10955 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10956 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10957 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10958 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10959 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10960 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10961 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10962 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10963 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10964 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10965 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10966 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10967 case X86ISD::VSHL: return "X86ISD::VSHL";
10968 case X86ISD::VSRL: return "X86ISD::VSRL";
10969 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10970 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10971 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10972 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10973 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10974 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10975 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10976 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10977 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10978 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10979 case X86ISD::ADD: return "X86ISD::ADD";
10980 case X86ISD::SUB: return "X86ISD::SUB";
10981 case X86ISD::ADC: return "X86ISD::ADC";
10982 case X86ISD::SBB: return "X86ISD::SBB";
10983 case X86ISD::SMUL: return "X86ISD::SMUL";
10984 case X86ISD::UMUL: return "X86ISD::UMUL";
10985 case X86ISD::INC: return "X86ISD::INC";
10986 case X86ISD::DEC: return "X86ISD::DEC";
10987 case X86ISD::OR: return "X86ISD::OR";
10988 case X86ISD::XOR: return "X86ISD::XOR";
10989 case X86ISD::AND: return "X86ISD::AND";
10990 case X86ISD::ANDN: return "X86ISD::ANDN";
10991 case X86ISD::BLSI: return "X86ISD::BLSI";
10992 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10993 case X86ISD::BLSR: return "X86ISD::BLSR";
10994 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10995 case X86ISD::PTEST: return "X86ISD::PTEST";
10996 case X86ISD::TESTP: return "X86ISD::TESTP";
10997 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10998 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10999 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11000 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
11001 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11002 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
11003 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11004 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11005 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11006 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11007 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11008 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11009 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11010 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11011 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11012 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
11013 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
11014 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11015 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11016 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11017 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11018 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11019 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11020 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11021 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11022 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11023 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11024 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11025 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11029 // isLegalAddressingMode - Return true if the addressing mode represented
11030 // by AM is legal for this target, for a load/store of the specified type.
11031 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11033 // X86 supports extremely general addressing modes.
11034 CodeModel::Model M = getTargetMachine().getCodeModel();
11035 Reloc::Model R = getTargetMachine().getRelocationModel();
11037 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11038 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11043 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11045 // If a reference to this global requires an extra load, we can't fold it.
11046 if (isGlobalStubReference(GVFlags))
11049 // If BaseGV requires a register for the PIC base, we cannot also have a
11050 // BaseReg specified.
11051 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11054 // If lower 4G is not available, then we must use rip-relative addressing.
11055 if ((M != CodeModel::Small || R != Reloc::Static) &&
11056 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11060 switch (AM.Scale) {
11066 // These scales always work.
11071 // These scales are formed with basereg+scalereg. Only accept if there is
11076 default: // Other stuff never works.
11084 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11085 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11087 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11088 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11089 if (NumBits1 <= NumBits2)
11094 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11095 if (!VT1.isInteger() || !VT2.isInteger())
11097 unsigned NumBits1 = VT1.getSizeInBits();
11098 unsigned NumBits2 = VT2.getSizeInBits();
11099 if (NumBits1 <= NumBits2)
11104 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11105 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11106 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11109 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11110 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11111 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11114 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11115 // i16 instructions are longer (0x66 prefix) and potentially slower.
11116 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11119 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11120 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11121 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11122 /// are assumed to be legal.
11124 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11126 // Very little shuffling can be done for 64-bit vectors right now.
11127 if (VT.getSizeInBits() == 64)
11130 // FIXME: pshufb, blends, shifts.
11131 return (VT.getVectorNumElements() == 2 ||
11132 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11133 isMOVLMask(M, VT) ||
11134 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11135 isPSHUFDMask(M, VT) ||
11136 isPSHUFHWMask(M, VT) ||
11137 isPSHUFLWMask(M, VT) ||
11138 isPALIGNRMask(M, VT, Subtarget) ||
11139 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11140 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11141 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11142 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11146 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11148 unsigned NumElts = VT.getVectorNumElements();
11149 // FIXME: This collection of masks seems suspect.
11152 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11153 return (isMOVLMask(Mask, VT) ||
11154 isCommutedMOVLMask(Mask, VT, true) ||
11155 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11156 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11161 //===----------------------------------------------------------------------===//
11162 // X86 Scheduler Hooks
11163 //===----------------------------------------------------------------------===//
11165 // private utility function
11166 MachineBasicBlock *
11167 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11168 MachineBasicBlock *MBB,
11175 TargetRegisterClass *RC,
11176 bool invSrc) const {
11177 // For the atomic bitwise operator, we generate
11180 // ld t1 = [bitinstr.addr]
11181 // op t2 = t1, [bitinstr.val]
11183 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11185 // fallthrough -->nextMBB
11186 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11187 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11188 MachineFunction::iterator MBBIter = MBB;
11191 /// First build the CFG
11192 MachineFunction *F = MBB->getParent();
11193 MachineBasicBlock *thisMBB = MBB;
11194 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11195 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11196 F->insert(MBBIter, newMBB);
11197 F->insert(MBBIter, nextMBB);
11199 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11200 nextMBB->splice(nextMBB->begin(), thisMBB,
11201 llvm::next(MachineBasicBlock::iterator(bInstr)),
11203 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11205 // Update thisMBB to fall through to newMBB
11206 thisMBB->addSuccessor(newMBB);
11208 // newMBB jumps to itself and fall through to nextMBB
11209 newMBB->addSuccessor(nextMBB);
11210 newMBB->addSuccessor(newMBB);
11212 // Insert instructions into newMBB based on incoming instruction
11213 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11214 "unexpected number of operands");
11215 DebugLoc dl = bInstr->getDebugLoc();
11216 MachineOperand& destOper = bInstr->getOperand(0);
11217 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11218 int numArgs = bInstr->getNumOperands() - 1;
11219 for (int i=0; i < numArgs; ++i)
11220 argOpers[i] = &bInstr->getOperand(i+1);
11222 // x86 address has 4 operands: base, index, scale, and displacement
11223 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11224 int valArgIndx = lastAddrIndx + 1;
11226 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11227 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11228 for (int i=0; i <= lastAddrIndx; ++i)
11229 (*MIB).addOperand(*argOpers[i]);
11231 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11233 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11238 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11239 assert((argOpers[valArgIndx]->isReg() ||
11240 argOpers[valArgIndx]->isImm()) &&
11241 "invalid operand");
11242 if (argOpers[valArgIndx]->isReg())
11243 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11245 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11247 (*MIB).addOperand(*argOpers[valArgIndx]);
11249 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11252 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11253 for (int i=0; i <= lastAddrIndx; ++i)
11254 (*MIB).addOperand(*argOpers[i]);
11256 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11257 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11258 bInstr->memoperands_end());
11260 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11261 MIB.addReg(EAXreg);
11264 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11266 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11270 // private utility function: 64 bit atomics on 32 bit host.
11271 MachineBasicBlock *
11272 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11273 MachineBasicBlock *MBB,
11278 bool invSrc) const {
11279 // For the atomic bitwise operator, we generate
11280 // thisMBB (instructions are in pairs, except cmpxchg8b)
11281 // ld t1,t2 = [bitinstr.addr]
11283 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11284 // op t5, t6 <- out1, out2, [bitinstr.val]
11285 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11286 // mov ECX, EBX <- t5, t6
11287 // mov EAX, EDX <- t1, t2
11288 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11289 // mov t3, t4 <- EAX, EDX
11291 // result in out1, out2
11292 // fallthrough -->nextMBB
11294 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11295 const unsigned LoadOpc = X86::MOV32rm;
11296 const unsigned NotOpc = X86::NOT32r;
11297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11298 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11299 MachineFunction::iterator MBBIter = MBB;
11302 /// First build the CFG
11303 MachineFunction *F = MBB->getParent();
11304 MachineBasicBlock *thisMBB = MBB;
11305 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11306 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11307 F->insert(MBBIter, newMBB);
11308 F->insert(MBBIter, nextMBB);
11310 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11311 nextMBB->splice(nextMBB->begin(), thisMBB,
11312 llvm::next(MachineBasicBlock::iterator(bInstr)),
11314 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11316 // Update thisMBB to fall through to newMBB
11317 thisMBB->addSuccessor(newMBB);
11319 // newMBB jumps to itself and fall through to nextMBB
11320 newMBB->addSuccessor(nextMBB);
11321 newMBB->addSuccessor(newMBB);
11323 DebugLoc dl = bInstr->getDebugLoc();
11324 // Insert instructions into newMBB based on incoming instruction
11325 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11326 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11327 "unexpected number of operands");
11328 MachineOperand& dest1Oper = bInstr->getOperand(0);
11329 MachineOperand& dest2Oper = bInstr->getOperand(1);
11330 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11331 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11332 argOpers[i] = &bInstr->getOperand(i+2);
11334 // We use some of the operands multiple times, so conservatively just
11335 // clear any kill flags that might be present.
11336 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11337 argOpers[i]->setIsKill(false);
11340 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11341 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11343 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11344 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11345 for (int i=0; i <= lastAddrIndx; ++i)
11346 (*MIB).addOperand(*argOpers[i]);
11347 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11348 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11349 // add 4 to displacement.
11350 for (int i=0; i <= lastAddrIndx-2; ++i)
11351 (*MIB).addOperand(*argOpers[i]);
11352 MachineOperand newOp3 = *(argOpers[3]);
11353 if (newOp3.isImm())
11354 newOp3.setImm(newOp3.getImm()+4);
11356 newOp3.setOffset(newOp3.getOffset()+4);
11357 (*MIB).addOperand(newOp3);
11358 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11360 // t3/4 are defined later, at the bottom of the loop
11361 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11362 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11363 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11364 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11365 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11366 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11368 // The subsequent operations should be using the destination registers of
11369 //the PHI instructions.
11371 t1 = F->getRegInfo().createVirtualRegister(RC);
11372 t2 = F->getRegInfo().createVirtualRegister(RC);
11373 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11374 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11376 t1 = dest1Oper.getReg();
11377 t2 = dest2Oper.getReg();
11380 int valArgIndx = lastAddrIndx + 1;
11381 assert((argOpers[valArgIndx]->isReg() ||
11382 argOpers[valArgIndx]->isImm()) &&
11383 "invalid operand");
11384 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11385 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11386 if (argOpers[valArgIndx]->isReg())
11387 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11389 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11390 if (regOpcL != X86::MOV32rr)
11392 (*MIB).addOperand(*argOpers[valArgIndx]);
11393 assert(argOpers[valArgIndx + 1]->isReg() ==
11394 argOpers[valArgIndx]->isReg());
11395 assert(argOpers[valArgIndx + 1]->isImm() ==
11396 argOpers[valArgIndx]->isImm());
11397 if (argOpers[valArgIndx + 1]->isReg())
11398 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11400 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11401 if (regOpcH != X86::MOV32rr)
11403 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11405 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11407 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11410 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11412 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11415 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11416 for (int i=0; i <= lastAddrIndx; ++i)
11417 (*MIB).addOperand(*argOpers[i]);
11419 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11420 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11421 bInstr->memoperands_end());
11423 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11424 MIB.addReg(X86::EAX);
11425 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11426 MIB.addReg(X86::EDX);
11429 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11431 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11435 // private utility function
11436 MachineBasicBlock *
11437 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11438 MachineBasicBlock *MBB,
11439 unsigned cmovOpc) const {
11440 // For the atomic min/max operator, we generate
11443 // ld t1 = [min/max.addr]
11444 // mov t2 = [min/max.val]
11446 // cmov[cond] t2 = t1
11448 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11450 // fallthrough -->nextMBB
11452 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11453 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11454 MachineFunction::iterator MBBIter = MBB;
11457 /// First build the CFG
11458 MachineFunction *F = MBB->getParent();
11459 MachineBasicBlock *thisMBB = MBB;
11460 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11461 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11462 F->insert(MBBIter, newMBB);
11463 F->insert(MBBIter, nextMBB);
11465 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11466 nextMBB->splice(nextMBB->begin(), thisMBB,
11467 llvm::next(MachineBasicBlock::iterator(mInstr)),
11469 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11471 // Update thisMBB to fall through to newMBB
11472 thisMBB->addSuccessor(newMBB);
11474 // newMBB jumps to newMBB and fall through to nextMBB
11475 newMBB->addSuccessor(nextMBB);
11476 newMBB->addSuccessor(newMBB);
11478 DebugLoc dl = mInstr->getDebugLoc();
11479 // Insert instructions into newMBB based on incoming instruction
11480 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11481 "unexpected number of operands");
11482 MachineOperand& destOper = mInstr->getOperand(0);
11483 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11484 int numArgs = mInstr->getNumOperands() - 1;
11485 for (int i=0; i < numArgs; ++i)
11486 argOpers[i] = &mInstr->getOperand(i+1);
11488 // x86 address has 4 operands: base, index, scale, and displacement
11489 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11490 int valArgIndx = lastAddrIndx + 1;
11492 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11493 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11494 for (int i=0; i <= lastAddrIndx; ++i)
11495 (*MIB).addOperand(*argOpers[i]);
11497 // We only support register and immediate values
11498 assert((argOpers[valArgIndx]->isReg() ||
11499 argOpers[valArgIndx]->isImm()) &&
11500 "invalid operand");
11502 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11503 if (argOpers[valArgIndx]->isReg())
11504 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11506 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11507 (*MIB).addOperand(*argOpers[valArgIndx]);
11509 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11512 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11517 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11518 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11522 // Cmp and exchange if none has modified the memory location
11523 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11524 for (int i=0; i <= lastAddrIndx; ++i)
11525 (*MIB).addOperand(*argOpers[i]);
11527 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11528 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11529 mInstr->memoperands_end());
11531 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11532 MIB.addReg(X86::EAX);
11535 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11537 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11541 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11542 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11543 // in the .td file.
11544 MachineBasicBlock *
11545 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11546 unsigned numArgs, bool memArg) const {
11547 assert(Subtarget->hasSSE42() &&
11548 "Target must have SSE4.2 or AVX features enabled");
11550 DebugLoc dl = MI->getDebugLoc();
11551 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11553 if (!Subtarget->hasAVX()) {
11555 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11557 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11560 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11562 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11565 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11566 for (unsigned i = 0; i < numArgs; ++i) {
11567 MachineOperand &Op = MI->getOperand(i+1);
11568 if (!(Op.isReg() && Op.isImplicit()))
11569 MIB.addOperand(Op);
11571 BuildMI(*BB, MI, dl,
11572 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11573 MI->getOperand(0).getReg())
11574 .addReg(X86::XMM0);
11576 MI->eraseFromParent();
11580 MachineBasicBlock *
11581 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11582 DebugLoc dl = MI->getDebugLoc();
11583 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11585 // Address into RAX/EAX, other two args into ECX, EDX.
11586 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11587 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11588 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11589 for (int i = 0; i < X86::AddrNumOperands; ++i)
11590 MIB.addOperand(MI->getOperand(i));
11592 unsigned ValOps = X86::AddrNumOperands;
11593 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11594 .addReg(MI->getOperand(ValOps).getReg());
11595 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11596 .addReg(MI->getOperand(ValOps+1).getReg());
11598 // The instruction doesn't actually take any operands though.
11599 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11601 MI->eraseFromParent(); // The pseudo is gone now.
11605 MachineBasicBlock *
11606 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11607 DebugLoc dl = MI->getDebugLoc();
11608 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11610 // First arg in ECX, the second in EAX.
11611 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11612 .addReg(MI->getOperand(0).getReg());
11613 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11614 .addReg(MI->getOperand(1).getReg());
11616 // The instruction doesn't actually take any operands though.
11617 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11619 MI->eraseFromParent(); // The pseudo is gone now.
11623 MachineBasicBlock *
11624 X86TargetLowering::EmitVAARG64WithCustomInserter(
11626 MachineBasicBlock *MBB) const {
11627 // Emit va_arg instruction on X86-64.
11629 // Operands to this pseudo-instruction:
11630 // 0 ) Output : destination address (reg)
11631 // 1-5) Input : va_list address (addr, i64mem)
11632 // 6 ) ArgSize : Size (in bytes) of vararg type
11633 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11634 // 8 ) Align : Alignment of type
11635 // 9 ) EFLAGS (implicit-def)
11637 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11638 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11640 unsigned DestReg = MI->getOperand(0).getReg();
11641 MachineOperand &Base = MI->getOperand(1);
11642 MachineOperand &Scale = MI->getOperand(2);
11643 MachineOperand &Index = MI->getOperand(3);
11644 MachineOperand &Disp = MI->getOperand(4);
11645 MachineOperand &Segment = MI->getOperand(5);
11646 unsigned ArgSize = MI->getOperand(6).getImm();
11647 unsigned ArgMode = MI->getOperand(7).getImm();
11648 unsigned Align = MI->getOperand(8).getImm();
11650 // Memory Reference
11651 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11652 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11653 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11655 // Machine Information
11656 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11657 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11658 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11659 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11660 DebugLoc DL = MI->getDebugLoc();
11662 // struct va_list {
11665 // i64 overflow_area (address)
11666 // i64 reg_save_area (address)
11668 // sizeof(va_list) = 24
11669 // alignment(va_list) = 8
11671 unsigned TotalNumIntRegs = 6;
11672 unsigned TotalNumXMMRegs = 8;
11673 bool UseGPOffset = (ArgMode == 1);
11674 bool UseFPOffset = (ArgMode == 2);
11675 unsigned MaxOffset = TotalNumIntRegs * 8 +
11676 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11678 /* Align ArgSize to a multiple of 8 */
11679 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11680 bool NeedsAlign = (Align > 8);
11682 MachineBasicBlock *thisMBB = MBB;
11683 MachineBasicBlock *overflowMBB;
11684 MachineBasicBlock *offsetMBB;
11685 MachineBasicBlock *endMBB;
11687 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11688 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11689 unsigned OffsetReg = 0;
11691 if (!UseGPOffset && !UseFPOffset) {
11692 // If we only pull from the overflow region, we don't create a branch.
11693 // We don't need to alter control flow.
11694 OffsetDestReg = 0; // unused
11695 OverflowDestReg = DestReg;
11698 overflowMBB = thisMBB;
11701 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11702 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11703 // If not, pull from overflow_area. (branch to overflowMBB)
11708 // offsetMBB overflowMBB
11713 // Registers for the PHI in endMBB
11714 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11715 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11717 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11718 MachineFunction *MF = MBB->getParent();
11719 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11720 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11721 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11723 MachineFunction::iterator MBBIter = MBB;
11726 // Insert the new basic blocks
11727 MF->insert(MBBIter, offsetMBB);
11728 MF->insert(MBBIter, overflowMBB);
11729 MF->insert(MBBIter, endMBB);
11731 // Transfer the remainder of MBB and its successor edges to endMBB.
11732 endMBB->splice(endMBB->begin(), thisMBB,
11733 llvm::next(MachineBasicBlock::iterator(MI)),
11735 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11737 // Make offsetMBB and overflowMBB successors of thisMBB
11738 thisMBB->addSuccessor(offsetMBB);
11739 thisMBB->addSuccessor(overflowMBB);
11741 // endMBB is a successor of both offsetMBB and overflowMBB
11742 offsetMBB->addSuccessor(endMBB);
11743 overflowMBB->addSuccessor(endMBB);
11745 // Load the offset value into a register
11746 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11747 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11751 .addDisp(Disp, UseFPOffset ? 4 : 0)
11752 .addOperand(Segment)
11753 .setMemRefs(MMOBegin, MMOEnd);
11755 // Check if there is enough room left to pull this argument.
11756 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11758 .addImm(MaxOffset + 8 - ArgSizeA8);
11760 // Branch to "overflowMBB" if offset >= max
11761 // Fall through to "offsetMBB" otherwise
11762 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11763 .addMBB(overflowMBB);
11766 // In offsetMBB, emit code to use the reg_save_area.
11768 assert(OffsetReg != 0);
11770 // Read the reg_save_area address.
11771 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11772 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11777 .addOperand(Segment)
11778 .setMemRefs(MMOBegin, MMOEnd);
11780 // Zero-extend the offset
11781 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11782 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11785 .addImm(X86::sub_32bit);
11787 // Add the offset to the reg_save_area to get the final address.
11788 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11789 .addReg(OffsetReg64)
11790 .addReg(RegSaveReg);
11792 // Compute the offset for the next argument
11793 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11794 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11796 .addImm(UseFPOffset ? 16 : 8);
11798 // Store it back into the va_list.
11799 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11803 .addDisp(Disp, UseFPOffset ? 4 : 0)
11804 .addOperand(Segment)
11805 .addReg(NextOffsetReg)
11806 .setMemRefs(MMOBegin, MMOEnd);
11809 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11814 // Emit code to use overflow area
11817 // Load the overflow_area address into a register.
11818 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11819 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11824 .addOperand(Segment)
11825 .setMemRefs(MMOBegin, MMOEnd);
11827 // If we need to align it, do so. Otherwise, just copy the address
11828 // to OverflowDestReg.
11830 // Align the overflow address
11831 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11832 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11834 // aligned_addr = (addr + (align-1)) & ~(align-1)
11835 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11836 .addReg(OverflowAddrReg)
11839 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11841 .addImm(~(uint64_t)(Align-1));
11843 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11844 .addReg(OverflowAddrReg);
11847 // Compute the next overflow address after this argument.
11848 // (the overflow address should be kept 8-byte aligned)
11849 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11850 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11851 .addReg(OverflowDestReg)
11852 .addImm(ArgSizeA8);
11854 // Store the new overflow address.
11855 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11860 .addOperand(Segment)
11861 .addReg(NextAddrReg)
11862 .setMemRefs(MMOBegin, MMOEnd);
11864 // If we branched, emit the PHI to the front of endMBB.
11866 BuildMI(*endMBB, endMBB->begin(), DL,
11867 TII->get(X86::PHI), DestReg)
11868 .addReg(OffsetDestReg).addMBB(offsetMBB)
11869 .addReg(OverflowDestReg).addMBB(overflowMBB);
11872 // Erase the pseudo instruction
11873 MI->eraseFromParent();
11878 MachineBasicBlock *
11879 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11881 MachineBasicBlock *MBB) const {
11882 // Emit code to save XMM registers to the stack. The ABI says that the
11883 // number of registers to save is given in %al, so it's theoretically
11884 // possible to do an indirect jump trick to avoid saving all of them,
11885 // however this code takes a simpler approach and just executes all
11886 // of the stores if %al is non-zero. It's less code, and it's probably
11887 // easier on the hardware branch predictor, and stores aren't all that
11888 // expensive anyway.
11890 // Create the new basic blocks. One block contains all the XMM stores,
11891 // and one block is the final destination regardless of whether any
11892 // stores were performed.
11893 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11894 MachineFunction *F = MBB->getParent();
11895 MachineFunction::iterator MBBIter = MBB;
11897 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11898 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11899 F->insert(MBBIter, XMMSaveMBB);
11900 F->insert(MBBIter, EndMBB);
11902 // Transfer the remainder of MBB and its successor edges to EndMBB.
11903 EndMBB->splice(EndMBB->begin(), MBB,
11904 llvm::next(MachineBasicBlock::iterator(MI)),
11906 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11908 // The original block will now fall through to the XMM save block.
11909 MBB->addSuccessor(XMMSaveMBB);
11910 // The XMMSaveMBB will fall through to the end block.
11911 XMMSaveMBB->addSuccessor(EndMBB);
11913 // Now add the instructions.
11914 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11915 DebugLoc DL = MI->getDebugLoc();
11917 unsigned CountReg = MI->getOperand(0).getReg();
11918 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11919 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11921 if (!Subtarget->isTargetWin64()) {
11922 // If %al is 0, branch around the XMM save block.
11923 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11924 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11925 MBB->addSuccessor(EndMBB);
11928 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11929 // In the XMM save block, save all the XMM argument registers.
11930 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11931 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11932 MachineMemOperand *MMO =
11933 F->getMachineMemOperand(
11934 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11935 MachineMemOperand::MOStore,
11936 /*Size=*/16, /*Align=*/16);
11937 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11938 .addFrameIndex(RegSaveFrameIndex)
11939 .addImm(/*Scale=*/1)
11940 .addReg(/*IndexReg=*/0)
11941 .addImm(/*Disp=*/Offset)
11942 .addReg(/*Segment=*/0)
11943 .addReg(MI->getOperand(i).getReg())
11944 .addMemOperand(MMO);
11947 MI->eraseFromParent(); // The pseudo instruction is gone now.
11952 MachineBasicBlock *
11953 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11954 MachineBasicBlock *BB) const {
11955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11956 DebugLoc DL = MI->getDebugLoc();
11958 // To "insert" a SELECT_CC instruction, we actually have to insert the
11959 // diamond control-flow pattern. The incoming instruction knows the
11960 // destination vreg to set, the condition code register to branch on, the
11961 // true/false values to select between, and a branch opcode to use.
11962 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11963 MachineFunction::iterator It = BB;
11969 // cmpTY ccX, r1, r2
11971 // fallthrough --> copy0MBB
11972 MachineBasicBlock *thisMBB = BB;
11973 MachineFunction *F = BB->getParent();
11974 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11975 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11976 F->insert(It, copy0MBB);
11977 F->insert(It, sinkMBB);
11979 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11980 // live into the sink and copy blocks.
11981 if (!MI->killsRegister(X86::EFLAGS)) {
11982 copy0MBB->addLiveIn(X86::EFLAGS);
11983 sinkMBB->addLiveIn(X86::EFLAGS);
11986 // Transfer the remainder of BB and its successor edges to sinkMBB.
11987 sinkMBB->splice(sinkMBB->begin(), BB,
11988 llvm::next(MachineBasicBlock::iterator(MI)),
11990 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11992 // Add the true and fallthrough blocks as its successors.
11993 BB->addSuccessor(copy0MBB);
11994 BB->addSuccessor(sinkMBB);
11996 // Create the conditional branch instruction.
11998 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11999 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12002 // %FalseValue = ...
12003 // # fallthrough to sinkMBB
12004 copy0MBB->addSuccessor(sinkMBB);
12007 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12009 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12010 TII->get(X86::PHI), MI->getOperand(0).getReg())
12011 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12012 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12014 MI->eraseFromParent(); // The pseudo instruction is gone now.
12018 MachineBasicBlock *
12019 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12020 bool Is64Bit) const {
12021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12022 DebugLoc DL = MI->getDebugLoc();
12023 MachineFunction *MF = BB->getParent();
12024 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12026 assert(getTargetMachine().Options.EnableSegmentedStacks);
12028 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12029 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12032 // ... [Till the alloca]
12033 // If stacklet is not large enough, jump to mallocMBB
12036 // Allocate by subtracting from RSP
12037 // Jump to continueMBB
12040 // Allocate by call to runtime
12044 // [rest of original BB]
12047 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12048 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12049 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12051 MachineRegisterInfo &MRI = MF->getRegInfo();
12052 const TargetRegisterClass *AddrRegClass =
12053 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12055 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12056 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12057 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12058 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12059 sizeVReg = MI->getOperand(1).getReg(),
12060 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12062 MachineFunction::iterator MBBIter = BB;
12065 MF->insert(MBBIter, bumpMBB);
12066 MF->insert(MBBIter, mallocMBB);
12067 MF->insert(MBBIter, continueMBB);
12069 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12070 (MachineBasicBlock::iterator(MI)), BB->end());
12071 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12073 // Add code to the main basic block to check if the stack limit has been hit,
12074 // and if so, jump to mallocMBB otherwise to bumpMBB.
12075 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12076 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12077 .addReg(tmpSPVReg).addReg(sizeVReg);
12078 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12079 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12080 .addReg(SPLimitVReg);
12081 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12083 // bumpMBB simply decreases the stack pointer, since we know the current
12084 // stacklet has enough space.
12085 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12086 .addReg(SPLimitVReg);
12087 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12088 .addReg(SPLimitVReg);
12089 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12091 // Calls into a routine in libgcc to allocate more space from the heap.
12093 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12095 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12096 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12098 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12100 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12101 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12102 .addExternalSymbol("__morestack_allocate_stack_space");
12106 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12109 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12110 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12111 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12113 // Set up the CFG correctly.
12114 BB->addSuccessor(bumpMBB);
12115 BB->addSuccessor(mallocMBB);
12116 mallocMBB->addSuccessor(continueMBB);
12117 bumpMBB->addSuccessor(continueMBB);
12119 // Take care of the PHI nodes.
12120 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12121 MI->getOperand(0).getReg())
12122 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12123 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12125 // Delete the original pseudo instruction.
12126 MI->eraseFromParent();
12129 return continueMBB;
12132 MachineBasicBlock *
12133 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12134 MachineBasicBlock *BB) const {
12135 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12136 DebugLoc DL = MI->getDebugLoc();
12138 assert(!Subtarget->isTargetEnvMacho());
12140 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12141 // non-trivial part is impdef of ESP.
12143 if (Subtarget->isTargetWin64()) {
12144 if (Subtarget->isTargetCygMing()) {
12145 // ___chkstk(Mingw64):
12146 // Clobbers R10, R11, RAX and EFLAGS.
12148 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12149 .addExternalSymbol("___chkstk")
12150 .addReg(X86::RAX, RegState::Implicit)
12151 .addReg(X86::RSP, RegState::Implicit)
12152 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12153 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12154 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12156 // __chkstk(MSVCRT): does not update stack pointer.
12157 // Clobbers R10, R11 and EFLAGS.
12158 // FIXME: RAX(allocated size) might be reused and not killed.
12159 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12160 .addExternalSymbol("__chkstk")
12161 .addReg(X86::RAX, RegState::Implicit)
12162 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12163 // RAX has the offset to subtracted from RSP.
12164 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12169 const char *StackProbeSymbol =
12170 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12172 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12173 .addExternalSymbol(StackProbeSymbol)
12174 .addReg(X86::EAX, RegState::Implicit)
12175 .addReg(X86::ESP, RegState::Implicit)
12176 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12177 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12178 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12181 MI->eraseFromParent(); // The pseudo instruction is gone now.
12185 MachineBasicBlock *
12186 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12187 MachineBasicBlock *BB) const {
12188 // This is pretty easy. We're taking the value that we received from
12189 // our load from the relocation, sticking it in either RDI (x86-64)
12190 // or EAX and doing an indirect call. The return value will then
12191 // be in the normal return register.
12192 const X86InstrInfo *TII
12193 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12194 DebugLoc DL = MI->getDebugLoc();
12195 MachineFunction *F = BB->getParent();
12197 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12198 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12200 if (Subtarget->is64Bit()) {
12201 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12202 TII->get(X86::MOV64rm), X86::RDI)
12204 .addImm(0).addReg(0)
12205 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12206 MI->getOperand(3).getTargetFlags())
12208 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12209 addDirectMem(MIB, X86::RDI);
12210 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12211 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12212 TII->get(X86::MOV32rm), X86::EAX)
12214 .addImm(0).addReg(0)
12215 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12216 MI->getOperand(3).getTargetFlags())
12218 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12219 addDirectMem(MIB, X86::EAX);
12221 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12222 TII->get(X86::MOV32rm), X86::EAX)
12223 .addReg(TII->getGlobalBaseReg(F))
12224 .addImm(0).addReg(0)
12225 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12226 MI->getOperand(3).getTargetFlags())
12228 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12229 addDirectMem(MIB, X86::EAX);
12232 MI->eraseFromParent(); // The pseudo instruction is gone now.
12236 MachineBasicBlock *
12237 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12238 MachineBasicBlock *BB) const {
12239 switch (MI->getOpcode()) {
12240 default: assert(0 && "Unexpected instr type to insert");
12241 case X86::TAILJMPd64:
12242 case X86::TAILJMPr64:
12243 case X86::TAILJMPm64:
12244 assert(0 && "TAILJMP64 would not be touched here.");
12245 case X86::TCRETURNdi64:
12246 case X86::TCRETURNri64:
12247 case X86::TCRETURNmi64:
12248 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12249 // On AMD64, additional defs should be added before register allocation.
12250 if (!Subtarget->isTargetWin64()) {
12251 MI->addRegisterDefined(X86::RSI);
12252 MI->addRegisterDefined(X86::RDI);
12253 MI->addRegisterDefined(X86::XMM6);
12254 MI->addRegisterDefined(X86::XMM7);
12255 MI->addRegisterDefined(X86::XMM8);
12256 MI->addRegisterDefined(X86::XMM9);
12257 MI->addRegisterDefined(X86::XMM10);
12258 MI->addRegisterDefined(X86::XMM11);
12259 MI->addRegisterDefined(X86::XMM12);
12260 MI->addRegisterDefined(X86::XMM13);
12261 MI->addRegisterDefined(X86::XMM14);
12262 MI->addRegisterDefined(X86::XMM15);
12265 case X86::WIN_ALLOCA:
12266 return EmitLoweredWinAlloca(MI, BB);
12267 case X86::SEG_ALLOCA_32:
12268 return EmitLoweredSegAlloca(MI, BB, false);
12269 case X86::SEG_ALLOCA_64:
12270 return EmitLoweredSegAlloca(MI, BB, true);
12271 case X86::TLSCall_32:
12272 case X86::TLSCall_64:
12273 return EmitLoweredTLSCall(MI, BB);
12274 case X86::CMOV_GR8:
12275 case X86::CMOV_FR32:
12276 case X86::CMOV_FR64:
12277 case X86::CMOV_V4F32:
12278 case X86::CMOV_V2F64:
12279 case X86::CMOV_V2I64:
12280 case X86::CMOV_V8F32:
12281 case X86::CMOV_V4F64:
12282 case X86::CMOV_V4I64:
12283 case X86::CMOV_GR16:
12284 case X86::CMOV_GR32:
12285 case X86::CMOV_RFP32:
12286 case X86::CMOV_RFP64:
12287 case X86::CMOV_RFP80:
12288 return EmitLoweredSelect(MI, BB);
12290 case X86::FP32_TO_INT16_IN_MEM:
12291 case X86::FP32_TO_INT32_IN_MEM:
12292 case X86::FP32_TO_INT64_IN_MEM:
12293 case X86::FP64_TO_INT16_IN_MEM:
12294 case X86::FP64_TO_INT32_IN_MEM:
12295 case X86::FP64_TO_INT64_IN_MEM:
12296 case X86::FP80_TO_INT16_IN_MEM:
12297 case X86::FP80_TO_INT32_IN_MEM:
12298 case X86::FP80_TO_INT64_IN_MEM: {
12299 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12300 DebugLoc DL = MI->getDebugLoc();
12302 // Change the floating point control register to use "round towards zero"
12303 // mode when truncating to an integer value.
12304 MachineFunction *F = BB->getParent();
12305 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12306 addFrameReference(BuildMI(*BB, MI, DL,
12307 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12309 // Load the old value of the high byte of the control word...
12311 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12312 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12315 // Set the high part to be round to zero...
12316 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12319 // Reload the modified control word now...
12320 addFrameReference(BuildMI(*BB, MI, DL,
12321 TII->get(X86::FLDCW16m)), CWFrameIdx);
12323 // Restore the memory image of control word to original value
12324 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12327 // Get the X86 opcode to use.
12329 switch (MI->getOpcode()) {
12330 default: llvm_unreachable("illegal opcode!");
12331 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12332 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12333 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12334 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12335 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12336 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12337 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12338 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12339 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12343 MachineOperand &Op = MI->getOperand(0);
12345 AM.BaseType = X86AddressMode::RegBase;
12346 AM.Base.Reg = Op.getReg();
12348 AM.BaseType = X86AddressMode::FrameIndexBase;
12349 AM.Base.FrameIndex = Op.getIndex();
12351 Op = MI->getOperand(1);
12353 AM.Scale = Op.getImm();
12354 Op = MI->getOperand(2);
12356 AM.IndexReg = Op.getImm();
12357 Op = MI->getOperand(3);
12358 if (Op.isGlobal()) {
12359 AM.GV = Op.getGlobal();
12361 AM.Disp = Op.getImm();
12363 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12364 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12366 // Reload the original control word now.
12367 addFrameReference(BuildMI(*BB, MI, DL,
12368 TII->get(X86::FLDCW16m)), CWFrameIdx);
12370 MI->eraseFromParent(); // The pseudo instruction is gone now.
12373 // String/text processing lowering.
12374 case X86::PCMPISTRM128REG:
12375 case X86::VPCMPISTRM128REG:
12376 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12377 case X86::PCMPISTRM128MEM:
12378 case X86::VPCMPISTRM128MEM:
12379 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12380 case X86::PCMPESTRM128REG:
12381 case X86::VPCMPESTRM128REG:
12382 return EmitPCMP(MI, BB, 5, false /* in mem */);
12383 case X86::PCMPESTRM128MEM:
12384 case X86::VPCMPESTRM128MEM:
12385 return EmitPCMP(MI, BB, 5, true /* in mem */);
12387 // Thread synchronization.
12389 return EmitMonitor(MI, BB);
12391 return EmitMwait(MI, BB);
12393 // Atomic Lowering.
12394 case X86::ATOMAND32:
12395 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12396 X86::AND32ri, X86::MOV32rm,
12398 X86::NOT32r, X86::EAX,
12399 X86::GR32RegisterClass);
12400 case X86::ATOMOR32:
12401 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12402 X86::OR32ri, X86::MOV32rm,
12404 X86::NOT32r, X86::EAX,
12405 X86::GR32RegisterClass);
12406 case X86::ATOMXOR32:
12407 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12408 X86::XOR32ri, X86::MOV32rm,
12410 X86::NOT32r, X86::EAX,
12411 X86::GR32RegisterClass);
12412 case X86::ATOMNAND32:
12413 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12414 X86::AND32ri, X86::MOV32rm,
12416 X86::NOT32r, X86::EAX,
12417 X86::GR32RegisterClass, true);
12418 case X86::ATOMMIN32:
12419 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12420 case X86::ATOMMAX32:
12421 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12422 case X86::ATOMUMIN32:
12423 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12424 case X86::ATOMUMAX32:
12425 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12427 case X86::ATOMAND16:
12428 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12429 X86::AND16ri, X86::MOV16rm,
12431 X86::NOT16r, X86::AX,
12432 X86::GR16RegisterClass);
12433 case X86::ATOMOR16:
12434 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12435 X86::OR16ri, X86::MOV16rm,
12437 X86::NOT16r, X86::AX,
12438 X86::GR16RegisterClass);
12439 case X86::ATOMXOR16:
12440 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12441 X86::XOR16ri, X86::MOV16rm,
12443 X86::NOT16r, X86::AX,
12444 X86::GR16RegisterClass);
12445 case X86::ATOMNAND16:
12446 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12447 X86::AND16ri, X86::MOV16rm,
12449 X86::NOT16r, X86::AX,
12450 X86::GR16RegisterClass, true);
12451 case X86::ATOMMIN16:
12452 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12453 case X86::ATOMMAX16:
12454 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12455 case X86::ATOMUMIN16:
12456 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12457 case X86::ATOMUMAX16:
12458 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12460 case X86::ATOMAND8:
12461 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12462 X86::AND8ri, X86::MOV8rm,
12464 X86::NOT8r, X86::AL,
12465 X86::GR8RegisterClass);
12467 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12468 X86::OR8ri, X86::MOV8rm,
12470 X86::NOT8r, X86::AL,
12471 X86::GR8RegisterClass);
12472 case X86::ATOMXOR8:
12473 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12474 X86::XOR8ri, X86::MOV8rm,
12476 X86::NOT8r, X86::AL,
12477 X86::GR8RegisterClass);
12478 case X86::ATOMNAND8:
12479 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12480 X86::AND8ri, X86::MOV8rm,
12482 X86::NOT8r, X86::AL,
12483 X86::GR8RegisterClass, true);
12484 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12485 // This group is for 64-bit host.
12486 case X86::ATOMAND64:
12487 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12488 X86::AND64ri32, X86::MOV64rm,
12490 X86::NOT64r, X86::RAX,
12491 X86::GR64RegisterClass);
12492 case X86::ATOMOR64:
12493 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12494 X86::OR64ri32, X86::MOV64rm,
12496 X86::NOT64r, X86::RAX,
12497 X86::GR64RegisterClass);
12498 case X86::ATOMXOR64:
12499 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12500 X86::XOR64ri32, X86::MOV64rm,
12502 X86::NOT64r, X86::RAX,
12503 X86::GR64RegisterClass);
12504 case X86::ATOMNAND64:
12505 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12506 X86::AND64ri32, X86::MOV64rm,
12508 X86::NOT64r, X86::RAX,
12509 X86::GR64RegisterClass, true);
12510 case X86::ATOMMIN64:
12511 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12512 case X86::ATOMMAX64:
12513 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12514 case X86::ATOMUMIN64:
12515 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12516 case X86::ATOMUMAX64:
12517 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12519 // This group does 64-bit operations on a 32-bit host.
12520 case X86::ATOMAND6432:
12521 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12522 X86::AND32rr, X86::AND32rr,
12523 X86::AND32ri, X86::AND32ri,
12525 case X86::ATOMOR6432:
12526 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12527 X86::OR32rr, X86::OR32rr,
12528 X86::OR32ri, X86::OR32ri,
12530 case X86::ATOMXOR6432:
12531 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12532 X86::XOR32rr, X86::XOR32rr,
12533 X86::XOR32ri, X86::XOR32ri,
12535 case X86::ATOMNAND6432:
12536 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12537 X86::AND32rr, X86::AND32rr,
12538 X86::AND32ri, X86::AND32ri,
12540 case X86::ATOMADD6432:
12541 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12542 X86::ADD32rr, X86::ADC32rr,
12543 X86::ADD32ri, X86::ADC32ri,
12545 case X86::ATOMSUB6432:
12546 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12547 X86::SUB32rr, X86::SBB32rr,
12548 X86::SUB32ri, X86::SBB32ri,
12550 case X86::ATOMSWAP6432:
12551 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12552 X86::MOV32rr, X86::MOV32rr,
12553 X86::MOV32ri, X86::MOV32ri,
12555 case X86::VASTART_SAVE_XMM_REGS:
12556 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12558 case X86::VAARG_64:
12559 return EmitVAARG64WithCustomInserter(MI, BB);
12563 //===----------------------------------------------------------------------===//
12564 // X86 Optimization Hooks
12565 //===----------------------------------------------------------------------===//
12567 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12571 const SelectionDAG &DAG,
12572 unsigned Depth) const {
12573 unsigned Opc = Op.getOpcode();
12574 assert((Opc >= ISD::BUILTIN_OP_END ||
12575 Opc == ISD::INTRINSIC_WO_CHAIN ||
12576 Opc == ISD::INTRINSIC_W_CHAIN ||
12577 Opc == ISD::INTRINSIC_VOID) &&
12578 "Should use MaskedValueIsZero if you don't know whether Op"
12579 " is a target node!");
12581 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12595 // These nodes' second result is a boolean.
12596 if (Op.getResNo() == 0)
12599 case X86ISD::SETCC:
12600 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12601 Mask.getBitWidth() - 1);
12603 case ISD::INTRINSIC_WO_CHAIN: {
12604 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12605 unsigned NumLoBits = 0;
12608 case Intrinsic::x86_sse_movmsk_ps:
12609 case Intrinsic::x86_avx_movmsk_ps_256:
12610 case Intrinsic::x86_sse2_movmsk_pd:
12611 case Intrinsic::x86_avx_movmsk_pd_256:
12612 case Intrinsic::x86_mmx_pmovmskb:
12613 case Intrinsic::x86_sse2_pmovmskb_128:
12614 case Intrinsic::x86_avx2_pmovmskb: {
12615 // High bits of movmskp{s|d}, pmovmskb are known zero.
12617 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12618 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12619 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12620 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12621 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12622 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12623 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12625 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12626 Mask.getBitWidth() - NumLoBits);
12635 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12636 unsigned Depth) const {
12637 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12638 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12639 return Op.getValueType().getScalarType().getSizeInBits();
12645 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12646 /// node is a GlobalAddress + offset.
12647 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12648 const GlobalValue* &GA,
12649 int64_t &Offset) const {
12650 if (N->getOpcode() == X86ISD::Wrapper) {
12651 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12652 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12653 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12657 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12660 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12661 /// same as extracting the high 128-bit part of 256-bit vector and then
12662 /// inserting the result into the low part of a new 256-bit vector
12663 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12664 EVT VT = SVOp->getValueType(0);
12665 int NumElems = VT.getVectorNumElements();
12667 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12668 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12669 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12670 SVOp->getMaskElt(j) >= 0)
12676 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12677 /// same as extracting the low 128-bit part of 256-bit vector and then
12678 /// inserting the result into the high part of a new 256-bit vector
12679 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12680 EVT VT = SVOp->getValueType(0);
12681 int NumElems = VT.getVectorNumElements();
12683 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12684 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12685 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12686 SVOp->getMaskElt(j) >= 0)
12692 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12693 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12694 TargetLowering::DAGCombinerInfo &DCI,
12696 DebugLoc dl = N->getDebugLoc();
12697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12698 SDValue V1 = SVOp->getOperand(0);
12699 SDValue V2 = SVOp->getOperand(1);
12700 EVT VT = SVOp->getValueType(0);
12701 int NumElems = VT.getVectorNumElements();
12703 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12704 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12708 // V UNDEF BUILD_VECTOR UNDEF
12710 // CONCAT_VECTOR CONCAT_VECTOR
12713 // RESULT: V + zero extended
12715 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12716 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12717 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12720 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12723 // To match the shuffle mask, the first half of the mask should
12724 // be exactly the first vector, and all the rest a splat with the
12725 // first element of the second one.
12726 for (int i = 0; i < NumElems/2; ++i)
12727 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12728 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12731 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12732 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12733 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12734 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12736 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12738 Ld->getPointerInfo(),
12739 Ld->getAlignment(),
12740 false/*isVolatile*/, true/*ReadMem*/,
12741 false/*WriteMem*/);
12742 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12745 // Emit a zeroed vector and insert the desired subvector on its
12747 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12748 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12749 DAG.getConstant(0, MVT::i32), DAG, dl);
12750 return DCI.CombineTo(N, InsV);
12753 //===--------------------------------------------------------------------===//
12754 // Combine some shuffles into subvector extracts and inserts:
12757 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12758 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12759 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12761 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12762 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12763 return DCI.CombineTo(N, InsV);
12766 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12767 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12768 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12769 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12770 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12771 return DCI.CombineTo(N, InsV);
12777 /// PerformShuffleCombine - Performs several different shuffle combines.
12778 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12779 TargetLowering::DAGCombinerInfo &DCI,
12780 const X86Subtarget *Subtarget) {
12781 DebugLoc dl = N->getDebugLoc();
12782 EVT VT = N->getValueType(0);
12784 // Don't create instructions with illegal types after legalize types has run.
12785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12786 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12789 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12790 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12791 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12792 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12794 // Only handle 128 wide vector from here on.
12795 if (VT.getSizeInBits() != 128)
12798 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12799 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12800 // consecutive, non-overlapping, and in the right order.
12801 SmallVector<SDValue, 16> Elts;
12802 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12803 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12805 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12808 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12809 /// generation and convert it from being a bunch of shuffles and extracts
12810 /// to a simple store and scalar loads to extract the elements.
12811 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12812 const TargetLowering &TLI) {
12813 SDValue InputVector = N->getOperand(0);
12815 // Only operate on vectors of 4 elements, where the alternative shuffling
12816 // gets to be more expensive.
12817 if (InputVector.getValueType() != MVT::v4i32)
12820 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12821 // single use which is a sign-extend or zero-extend, and all elements are
12823 SmallVector<SDNode *, 4> Uses;
12824 unsigned ExtractedElements = 0;
12825 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12826 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12827 if (UI.getUse().getResNo() != InputVector.getResNo())
12830 SDNode *Extract = *UI;
12831 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12834 if (Extract->getValueType(0) != MVT::i32)
12836 if (!Extract->hasOneUse())
12838 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12839 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12841 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12844 // Record which element was extracted.
12845 ExtractedElements |=
12846 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12848 Uses.push_back(Extract);
12851 // If not all the elements were used, this may not be worthwhile.
12852 if (ExtractedElements != 15)
12855 // Ok, we've now decided to do the transformation.
12856 DebugLoc dl = InputVector.getDebugLoc();
12858 // Store the value to a temporary stack slot.
12859 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12860 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12861 MachinePointerInfo(), false, false, 0);
12863 // Replace each use (extract) with a load of the appropriate element.
12864 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12865 UE = Uses.end(); UI != UE; ++UI) {
12866 SDNode *Extract = *UI;
12868 // cOMpute the element's address.
12869 SDValue Idx = Extract->getOperand(1);
12871 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12872 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12873 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12875 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12876 StackPtr, OffsetVal);
12878 // Load the scalar.
12879 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12880 ScalarAddr, MachinePointerInfo(),
12881 false, false, false, 0);
12883 // Replace the exact with the load.
12884 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12887 // The replacement was made in place; don't return anything.
12891 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12893 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12894 TargetLowering::DAGCombinerInfo &DCI,
12895 const X86Subtarget *Subtarget) {
12896 DebugLoc DL = N->getDebugLoc();
12897 SDValue Cond = N->getOperand(0);
12898 // Get the LHS/RHS of the select.
12899 SDValue LHS = N->getOperand(1);
12900 SDValue RHS = N->getOperand(2);
12901 EVT VT = LHS.getValueType();
12903 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12904 // instructions match the semantics of the common C idiom x<y?x:y but not
12905 // x<=y?x:y, because of how they handle negative zero (which can be
12906 // ignored in unsafe-math mode).
12907 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12908 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12909 (Subtarget->hasSSE2() ||
12910 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12911 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12913 unsigned Opcode = 0;
12914 // Check for x CC y ? x : y.
12915 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12916 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12920 // Converting this to a min would handle NaNs incorrectly, and swapping
12921 // the operands would cause it to handle comparisons between positive
12922 // and negative zero incorrectly.
12923 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12924 if (!DAG.getTarget().Options.UnsafeFPMath &&
12925 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12927 std::swap(LHS, RHS);
12929 Opcode = X86ISD::FMIN;
12932 // Converting this to a min would handle comparisons between positive
12933 // and negative zero incorrectly.
12934 if (!DAG.getTarget().Options.UnsafeFPMath &&
12935 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12937 Opcode = X86ISD::FMIN;
12940 // Converting this to a min would handle both negative zeros and NaNs
12941 // incorrectly, but we can swap the operands to fix both.
12942 std::swap(LHS, RHS);
12946 Opcode = X86ISD::FMIN;
12950 // Converting this to a max would handle comparisons between positive
12951 // and negative zero incorrectly.
12952 if (!DAG.getTarget().Options.UnsafeFPMath &&
12953 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12955 Opcode = X86ISD::FMAX;
12958 // Converting this to a max would handle NaNs incorrectly, and swapping
12959 // the operands would cause it to handle comparisons between positive
12960 // and negative zero incorrectly.
12961 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12962 if (!DAG.getTarget().Options.UnsafeFPMath &&
12963 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12965 std::swap(LHS, RHS);
12967 Opcode = X86ISD::FMAX;
12970 // Converting this to a max would handle both negative zeros and NaNs
12971 // incorrectly, but we can swap the operands to fix both.
12972 std::swap(LHS, RHS);
12976 Opcode = X86ISD::FMAX;
12979 // Check for x CC y ? y : x -- a min/max with reversed arms.
12980 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12981 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12985 // Converting this to a min would handle comparisons between positive
12986 // and negative zero incorrectly, and swapping the operands would
12987 // cause it to handle NaNs incorrectly.
12988 if (!DAG.getTarget().Options.UnsafeFPMath &&
12989 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12990 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12992 std::swap(LHS, RHS);
12994 Opcode = X86ISD::FMIN;
12997 // Converting this to a min would handle NaNs incorrectly.
12998 if (!DAG.getTarget().Options.UnsafeFPMath &&
12999 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13001 Opcode = X86ISD::FMIN;
13004 // Converting this to a min would handle both negative zeros and NaNs
13005 // incorrectly, but we can swap the operands to fix both.
13006 std::swap(LHS, RHS);
13010 Opcode = X86ISD::FMIN;
13014 // Converting this to a max would handle NaNs incorrectly.
13015 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13017 Opcode = X86ISD::FMAX;
13020 // Converting this to a max would handle comparisons between positive
13021 // and negative zero incorrectly, and swapping the operands would
13022 // cause it to handle NaNs incorrectly.
13023 if (!DAG.getTarget().Options.UnsafeFPMath &&
13024 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13025 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13027 std::swap(LHS, RHS);
13029 Opcode = X86ISD::FMAX;
13032 // Converting this to a max would handle both negative zeros and NaNs
13033 // incorrectly, but we can swap the operands to fix both.
13034 std::swap(LHS, RHS);
13038 Opcode = X86ISD::FMAX;
13044 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13047 // If this is a select between two integer constants, try to do some
13049 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13050 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13051 // Don't do this for crazy integer types.
13052 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13053 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13054 // so that TrueC (the true value) is larger than FalseC.
13055 bool NeedsCondInvert = false;
13057 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13058 // Efficiently invertible.
13059 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13060 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13061 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13062 NeedsCondInvert = true;
13063 std::swap(TrueC, FalseC);
13066 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13067 if (FalseC->getAPIntValue() == 0 &&
13068 TrueC->getAPIntValue().isPowerOf2()) {
13069 if (NeedsCondInvert) // Invert the condition if needed.
13070 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13071 DAG.getConstant(1, Cond.getValueType()));
13073 // Zero extend the condition if needed.
13074 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13076 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13077 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13078 DAG.getConstant(ShAmt, MVT::i8));
13081 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13082 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13083 if (NeedsCondInvert) // Invert the condition if needed.
13084 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13085 DAG.getConstant(1, Cond.getValueType()));
13087 // Zero extend the condition if needed.
13088 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13089 FalseC->getValueType(0), Cond);
13090 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13091 SDValue(FalseC, 0));
13094 // Optimize cases that will turn into an LEA instruction. This requires
13095 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13096 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13097 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13098 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13100 bool isFastMultiplier = false;
13102 switch ((unsigned char)Diff) {
13104 case 1: // result = add base, cond
13105 case 2: // result = lea base( , cond*2)
13106 case 3: // result = lea base(cond, cond*2)
13107 case 4: // result = lea base( , cond*4)
13108 case 5: // result = lea base(cond, cond*4)
13109 case 8: // result = lea base( , cond*8)
13110 case 9: // result = lea base(cond, cond*8)
13111 isFastMultiplier = true;
13116 if (isFastMultiplier) {
13117 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13118 if (NeedsCondInvert) // Invert the condition if needed.
13119 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13120 DAG.getConstant(1, Cond.getValueType()));
13122 // Zero extend the condition if needed.
13123 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13125 // Scale the condition by the difference.
13127 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13128 DAG.getConstant(Diff, Cond.getValueType()));
13130 // Add the base if non-zero.
13131 if (FalseC->getAPIntValue() != 0)
13132 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13133 SDValue(FalseC, 0));
13140 // Canonicalize max and min:
13141 // (x > y) ? x : y -> (x >= y) ? x : y
13142 // (x < y) ? x : y -> (x <= y) ? x : y
13143 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13144 // the need for an extra compare
13145 // against zero. e.g.
13146 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13148 // testl %edi, %edi
13150 // cmovgl %edi, %eax
13154 // cmovsl %eax, %edi
13155 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13156 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13157 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13158 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13163 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13164 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13165 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13166 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13171 // If we know that this node is legal then we know that it is going to be
13172 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13173 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13174 // to simplify previous instructions.
13175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13176 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13177 !DCI.isBeforeLegalize() &&
13178 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13179 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13180 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13181 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13183 APInt KnownZero, KnownOne;
13184 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13185 DCI.isBeforeLegalizeOps());
13186 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13187 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13188 DCI.CommitTargetLoweringOpt(TLO);
13194 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13195 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13196 TargetLowering::DAGCombinerInfo &DCI) {
13197 DebugLoc DL = N->getDebugLoc();
13199 // If the flag operand isn't dead, don't touch this CMOV.
13200 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13203 SDValue FalseOp = N->getOperand(0);
13204 SDValue TrueOp = N->getOperand(1);
13205 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13206 SDValue Cond = N->getOperand(3);
13207 if (CC == X86::COND_E || CC == X86::COND_NE) {
13208 switch (Cond.getOpcode()) {
13212 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13213 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13214 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13218 // If this is a select between two integer constants, try to do some
13219 // optimizations. Note that the operands are ordered the opposite of SELECT
13221 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13222 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13223 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13224 // larger than FalseC (the false value).
13225 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13226 CC = X86::GetOppositeBranchCondition(CC);
13227 std::swap(TrueC, FalseC);
13230 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13231 // This is efficient for any integer data type (including i8/i16) and
13233 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13234 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13235 DAG.getConstant(CC, MVT::i8), Cond);
13237 // Zero extend the condition if needed.
13238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13240 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13241 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13242 DAG.getConstant(ShAmt, MVT::i8));
13243 if (N->getNumValues() == 2) // Dead flag value?
13244 return DCI.CombineTo(N, Cond, SDValue());
13248 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13249 // for any integer data type, including i8/i16.
13250 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13251 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13252 DAG.getConstant(CC, MVT::i8), Cond);
13254 // Zero extend the condition if needed.
13255 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13256 FalseC->getValueType(0), Cond);
13257 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13258 SDValue(FalseC, 0));
13260 if (N->getNumValues() == 2) // Dead flag value?
13261 return DCI.CombineTo(N, Cond, SDValue());
13265 // Optimize cases that will turn into an LEA instruction. This requires
13266 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13267 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13268 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13269 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13271 bool isFastMultiplier = false;
13273 switch ((unsigned char)Diff) {
13275 case 1: // result = add base, cond
13276 case 2: // result = lea base( , cond*2)
13277 case 3: // result = lea base(cond, cond*2)
13278 case 4: // result = lea base( , cond*4)
13279 case 5: // result = lea base(cond, cond*4)
13280 case 8: // result = lea base( , cond*8)
13281 case 9: // result = lea base(cond, cond*8)
13282 isFastMultiplier = true;
13287 if (isFastMultiplier) {
13288 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13289 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13290 DAG.getConstant(CC, MVT::i8), Cond);
13291 // Zero extend the condition if needed.
13292 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13294 // Scale the condition by the difference.
13296 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13297 DAG.getConstant(Diff, Cond.getValueType()));
13299 // Add the base if non-zero.
13300 if (FalseC->getAPIntValue() != 0)
13301 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13302 SDValue(FalseC, 0));
13303 if (N->getNumValues() == 2) // Dead flag value?
13304 return DCI.CombineTo(N, Cond, SDValue());
13314 /// PerformMulCombine - Optimize a single multiply with constant into two
13315 /// in order to implement it with two cheaper instructions, e.g.
13316 /// LEA + SHL, LEA + LEA.
13317 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13318 TargetLowering::DAGCombinerInfo &DCI) {
13319 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13322 EVT VT = N->getValueType(0);
13323 if (VT != MVT::i64)
13326 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13329 uint64_t MulAmt = C->getZExtValue();
13330 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13333 uint64_t MulAmt1 = 0;
13334 uint64_t MulAmt2 = 0;
13335 if ((MulAmt % 9) == 0) {
13337 MulAmt2 = MulAmt / 9;
13338 } else if ((MulAmt % 5) == 0) {
13340 MulAmt2 = MulAmt / 5;
13341 } else if ((MulAmt % 3) == 0) {
13343 MulAmt2 = MulAmt / 3;
13346 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13347 DebugLoc DL = N->getDebugLoc();
13349 if (isPowerOf2_64(MulAmt2) &&
13350 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13351 // If second multiplifer is pow2, issue it first. We want the multiply by
13352 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13354 std::swap(MulAmt1, MulAmt2);
13357 if (isPowerOf2_64(MulAmt1))
13358 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13359 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13361 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13362 DAG.getConstant(MulAmt1, VT));
13364 if (isPowerOf2_64(MulAmt2))
13365 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13366 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13368 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13369 DAG.getConstant(MulAmt2, VT));
13371 // Do not add new nodes to DAG combiner worklist.
13372 DCI.CombineTo(N, NewMul, false);
13377 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13378 SDValue N0 = N->getOperand(0);
13379 SDValue N1 = N->getOperand(1);
13380 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13381 EVT VT = N0.getValueType();
13383 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13384 // since the result of setcc_c is all zero's or all ones.
13385 if (VT.isInteger() && !VT.isVector() &&
13386 N1C && N0.getOpcode() == ISD::AND &&
13387 N0.getOperand(1).getOpcode() == ISD::Constant) {
13388 SDValue N00 = N0.getOperand(0);
13389 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13390 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13391 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13392 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13393 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13394 APInt ShAmt = N1C->getAPIntValue();
13395 Mask = Mask.shl(ShAmt);
13397 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13398 N00, DAG.getConstant(Mask, VT));
13403 // Hardware support for vector shifts is sparse which makes us scalarize the
13404 // vector operations in many cases. Also, on sandybridge ADD is faster than
13406 // (shl V, 1) -> add V,V
13407 if (isSplatVector(N1.getNode())) {
13408 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13410 // We shift all of the values by one. In many cases we do not have
13411 // hardware support for this operation. This is better expressed as an ADD
13413 if (N1C && (1 == N1C->getZExtValue())) {
13414 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13421 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13423 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13424 const X86Subtarget *Subtarget) {
13425 EVT VT = N->getValueType(0);
13426 if (N->getOpcode() == ISD::SHL) {
13427 SDValue V = PerformSHLCombine(N, DAG);
13428 if (V.getNode()) return V;
13431 // On X86 with SSE2 support, we can transform this to a vector shift if
13432 // all elements are shifted by the same amount. We can't do this in legalize
13433 // because the a constant vector is typically transformed to a constant pool
13434 // so we have no knowledge of the shift amount.
13435 if (!Subtarget->hasSSE2())
13438 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13439 (!Subtarget->hasAVX2() ||
13440 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13443 SDValue ShAmtOp = N->getOperand(1);
13444 EVT EltVT = VT.getVectorElementType();
13445 DebugLoc DL = N->getDebugLoc();
13446 SDValue BaseShAmt = SDValue();
13447 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13448 unsigned NumElts = VT.getVectorNumElements();
13450 for (; i != NumElts; ++i) {
13451 SDValue Arg = ShAmtOp.getOperand(i);
13452 if (Arg.getOpcode() == ISD::UNDEF) continue;
13456 // Handle the case where the build_vector is all undef
13457 // FIXME: Should DAG allow this?
13461 for (; i != NumElts; ++i) {
13462 SDValue Arg = ShAmtOp.getOperand(i);
13463 if (Arg.getOpcode() == ISD::UNDEF) continue;
13464 if (Arg != BaseShAmt) {
13468 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13469 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13470 SDValue InVec = ShAmtOp.getOperand(0);
13471 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13472 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13474 for (; i != NumElts; ++i) {
13475 SDValue Arg = InVec.getOperand(i);
13476 if (Arg.getOpcode() == ISD::UNDEF) continue;
13480 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13482 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13483 if (C->getZExtValue() == SplatIdx)
13484 BaseShAmt = InVec.getOperand(1);
13487 if (BaseShAmt.getNode() == 0)
13488 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13489 DAG.getIntPtrConstant(0));
13493 // The shift amount is an i32.
13494 if (EltVT.bitsGT(MVT::i32))
13495 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13496 else if (EltVT.bitsLT(MVT::i32))
13497 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13499 // The shift amount is identical so we can do a vector shift.
13500 SDValue ValOp = N->getOperand(0);
13501 switch (N->getOpcode()) {
13503 llvm_unreachable("Unknown shift opcode!");
13506 if (VT == MVT::v2i64)
13507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13508 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13510 if (VT == MVT::v4i32)
13511 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13512 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13514 if (VT == MVT::v8i16)
13515 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13516 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13518 if (VT == MVT::v4i64)
13519 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13520 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13522 if (VT == MVT::v8i32)
13523 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13524 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13526 if (VT == MVT::v16i16)
13527 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13528 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13532 if (VT == MVT::v4i32)
13533 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13534 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13536 if (VT == MVT::v8i16)
13537 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13538 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13540 if (VT == MVT::v8i32)
13541 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13542 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13544 if (VT == MVT::v16i16)
13545 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13546 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13550 if (VT == MVT::v2i64)
13551 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13552 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13554 if (VT == MVT::v4i32)
13555 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13556 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13558 if (VT == MVT::v8i16)
13559 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13560 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13562 if (VT == MVT::v4i64)
13563 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13564 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13566 if (VT == MVT::v8i32)
13567 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13568 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13570 if (VT == MVT::v16i16)
13571 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13572 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13580 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13581 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13582 // and friends. Likewise for OR -> CMPNEQSS.
13583 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13584 TargetLowering::DAGCombinerInfo &DCI,
13585 const X86Subtarget *Subtarget) {
13588 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13589 // we're requiring SSE2 for both.
13590 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13591 SDValue N0 = N->getOperand(0);
13592 SDValue N1 = N->getOperand(1);
13593 SDValue CMP0 = N0->getOperand(1);
13594 SDValue CMP1 = N1->getOperand(1);
13595 DebugLoc DL = N->getDebugLoc();
13597 // The SETCCs should both refer to the same CMP.
13598 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13601 SDValue CMP00 = CMP0->getOperand(0);
13602 SDValue CMP01 = CMP0->getOperand(1);
13603 EVT VT = CMP00.getValueType();
13605 if (VT == MVT::f32 || VT == MVT::f64) {
13606 bool ExpectingFlags = false;
13607 // Check for any users that want flags:
13608 for (SDNode::use_iterator UI = N->use_begin(),
13610 !ExpectingFlags && UI != UE; ++UI)
13611 switch (UI->getOpcode()) {
13616 ExpectingFlags = true;
13618 case ISD::CopyToReg:
13619 case ISD::SIGN_EXTEND:
13620 case ISD::ZERO_EXTEND:
13621 case ISD::ANY_EXTEND:
13625 if (!ExpectingFlags) {
13626 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13627 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13629 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13630 X86::CondCode tmp = cc0;
13635 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13636 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13637 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13638 X86ISD::NodeType NTOperator = is64BitFP ?
13639 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13640 // FIXME: need symbolic constants for these magic numbers.
13641 // See X86ATTInstPrinter.cpp:printSSECC().
13642 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13643 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13644 DAG.getConstant(x86cc, MVT::i8));
13645 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13647 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13648 DAG.getConstant(1, MVT::i32));
13649 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13650 return OneBitOfTruth;
13658 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13659 /// so it can be folded inside ANDNP.
13660 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13661 EVT VT = N->getValueType(0);
13663 // Match direct AllOnes for 128 and 256-bit vectors
13664 if (ISD::isBuildVectorAllOnes(N))
13667 // Look through a bit convert.
13668 if (N->getOpcode() == ISD::BITCAST)
13669 N = N->getOperand(0).getNode();
13671 // Sometimes the operand may come from a insert_subvector building a 256-bit
13673 if (VT.getSizeInBits() == 256 &&
13674 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13675 SDValue V1 = N->getOperand(0);
13676 SDValue V2 = N->getOperand(1);
13678 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13679 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13680 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13681 ISD::isBuildVectorAllOnes(V2.getNode()))
13688 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13689 TargetLowering::DAGCombinerInfo &DCI,
13690 const X86Subtarget *Subtarget) {
13691 if (DCI.isBeforeLegalizeOps())
13694 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13698 EVT VT = N->getValueType(0);
13700 // Create ANDN, BLSI, and BLSR instructions
13701 // BLSI is X & (-X)
13702 // BLSR is X & (X-1)
13703 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13704 SDValue N0 = N->getOperand(0);
13705 SDValue N1 = N->getOperand(1);
13706 DebugLoc DL = N->getDebugLoc();
13708 // Check LHS for not
13709 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13710 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13711 // Check RHS for not
13712 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13713 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13715 // Check LHS for neg
13716 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13717 isZero(N0.getOperand(0)))
13718 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13720 // Check RHS for neg
13721 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13722 isZero(N1.getOperand(0)))
13723 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13725 // Check LHS for X-1
13726 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13727 isAllOnes(N0.getOperand(1)))
13728 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13730 // Check RHS for X-1
13731 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13732 isAllOnes(N1.getOperand(1)))
13733 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13738 // Want to form ANDNP nodes:
13739 // 1) In the hopes of then easily combining them with OR and AND nodes
13740 // to form PBLEND/PSIGN.
13741 // 2) To match ANDN packed intrinsics
13742 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13745 SDValue N0 = N->getOperand(0);
13746 SDValue N1 = N->getOperand(1);
13747 DebugLoc DL = N->getDebugLoc();
13749 // Check LHS for vnot
13750 if (N0.getOpcode() == ISD::XOR &&
13751 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13752 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13753 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13755 // Check RHS for vnot
13756 if (N1.getOpcode() == ISD::XOR &&
13757 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13758 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13759 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13764 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13765 TargetLowering::DAGCombinerInfo &DCI,
13766 const X86Subtarget *Subtarget) {
13767 if (DCI.isBeforeLegalizeOps())
13770 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13774 EVT VT = N->getValueType(0);
13776 SDValue N0 = N->getOperand(0);
13777 SDValue N1 = N->getOperand(1);
13779 // look for psign/blend
13780 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13781 if (!Subtarget->hasSSSE3() ||
13782 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13785 // Canonicalize pandn to RHS
13786 if (N0.getOpcode() == X86ISD::ANDNP)
13788 // or (and (m, y), (pandn m, x))
13789 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13790 SDValue Mask = N1.getOperand(0);
13791 SDValue X = N1.getOperand(1);
13793 if (N0.getOperand(0) == Mask)
13794 Y = N0.getOperand(1);
13795 if (N0.getOperand(1) == Mask)
13796 Y = N0.getOperand(0);
13798 // Check to see if the mask appeared in both the AND and ANDNP and
13802 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13803 if (Mask.getOpcode() != ISD::BITCAST ||
13804 X.getOpcode() != ISD::BITCAST ||
13805 Y.getOpcode() != ISD::BITCAST)
13808 // Look through mask bitcast.
13809 Mask = Mask.getOperand(0);
13810 EVT MaskVT = Mask.getValueType();
13812 // Validate that the Mask operand is a vector sra node. The sra node
13813 // will be an intrinsic.
13814 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13817 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13818 // there is no psrai.b
13819 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13820 case Intrinsic::x86_sse2_psrai_w:
13821 case Intrinsic::x86_sse2_psrai_d:
13822 case Intrinsic::x86_avx2_psrai_w:
13823 case Intrinsic::x86_avx2_psrai_d:
13825 default: return SDValue();
13828 // Check that the SRA is all signbits.
13829 SDValue SraC = Mask.getOperand(2);
13830 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13831 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13832 if ((SraAmt + 1) != EltBits)
13835 DebugLoc DL = N->getDebugLoc();
13837 // Now we know we at least have a plendvb with the mask val. See if
13838 // we can form a psignb/w/d.
13839 // psign = x.type == y.type == mask.type && y = sub(0, x);
13840 X = X.getOperand(0);
13841 Y = Y.getOperand(0);
13842 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13843 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13844 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13845 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13846 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13847 Mask.getOperand(1));
13848 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13850 // PBLENDVB only available on SSE 4.1
13851 if (!Subtarget->hasSSE41())
13854 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13856 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13857 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13858 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13859 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13860 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13864 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13867 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13868 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13870 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13872 if (!N0.hasOneUse() || !N1.hasOneUse())
13875 SDValue ShAmt0 = N0.getOperand(1);
13876 if (ShAmt0.getValueType() != MVT::i8)
13878 SDValue ShAmt1 = N1.getOperand(1);
13879 if (ShAmt1.getValueType() != MVT::i8)
13881 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13882 ShAmt0 = ShAmt0.getOperand(0);
13883 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13884 ShAmt1 = ShAmt1.getOperand(0);
13886 DebugLoc DL = N->getDebugLoc();
13887 unsigned Opc = X86ISD::SHLD;
13888 SDValue Op0 = N0.getOperand(0);
13889 SDValue Op1 = N1.getOperand(0);
13890 if (ShAmt0.getOpcode() == ISD::SUB) {
13891 Opc = X86ISD::SHRD;
13892 std::swap(Op0, Op1);
13893 std::swap(ShAmt0, ShAmt1);
13896 unsigned Bits = VT.getSizeInBits();
13897 if (ShAmt1.getOpcode() == ISD::SUB) {
13898 SDValue Sum = ShAmt1.getOperand(0);
13899 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13900 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13901 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13902 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13903 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13904 return DAG.getNode(Opc, DL, VT,
13906 DAG.getNode(ISD::TRUNCATE, DL,
13909 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13910 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13912 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13913 return DAG.getNode(Opc, DL, VT,
13914 N0.getOperand(0), N1.getOperand(0),
13915 DAG.getNode(ISD::TRUNCATE, DL,
13922 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
13923 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13924 TargetLowering::DAGCombinerInfo &DCI,
13925 const X86Subtarget *Subtarget) {
13926 if (DCI.isBeforeLegalizeOps())
13929 EVT VT = N->getValueType(0);
13931 if (VT != MVT::i32 && VT != MVT::i64)
13934 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
13936 // Create BLSMSK instructions by finding X ^ (X-1)
13937 SDValue N0 = N->getOperand(0);
13938 SDValue N1 = N->getOperand(1);
13939 DebugLoc DL = N->getDebugLoc();
13941 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13942 isAllOnes(N0.getOperand(1)))
13943 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13945 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13946 isAllOnes(N1.getOperand(1)))
13947 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13952 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13953 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13954 const X86Subtarget *Subtarget) {
13955 LoadSDNode *Ld = cast<LoadSDNode>(N);
13956 EVT RegVT = Ld->getValueType(0);
13957 EVT MemVT = Ld->getMemoryVT();
13958 DebugLoc dl = Ld->getDebugLoc();
13959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13961 ISD::LoadExtType Ext = Ld->getExtensionType();
13963 // If this is a vector EXT Load then attempt to optimize it using a
13964 // shuffle. We need SSE4 for the shuffles.
13965 // TODO: It is possible to support ZExt by zeroing the undef values
13966 // during the shuffle phase or after the shuffle.
13967 if (RegVT.isVector() && RegVT.isInteger() &&
13968 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13969 assert(MemVT != RegVT && "Cannot extend to the same type");
13970 assert(MemVT.isVector() && "Must load a vector from memory");
13972 unsigned NumElems = RegVT.getVectorNumElements();
13973 unsigned RegSz = RegVT.getSizeInBits();
13974 unsigned MemSz = MemVT.getSizeInBits();
13975 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13976 // All sizes must be a power of two
13977 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13979 // Attempt to load the original value using a single load op.
13980 // Find a scalar type which is equal to the loaded word size.
13981 MVT SclrLoadTy = MVT::i8;
13982 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13983 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13984 MVT Tp = (MVT::SimpleValueType)tp;
13985 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13991 // Proceed if a load word is found.
13992 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13994 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13995 RegSz/SclrLoadTy.getSizeInBits());
13997 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13998 RegSz/MemVT.getScalarType().getSizeInBits());
13999 // Can't shuffle using an illegal type.
14000 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14002 // Perform a single load.
14003 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14005 Ld->getPointerInfo(), Ld->isVolatile(),
14006 Ld->isNonTemporal(), Ld->isInvariant(),
14007 Ld->getAlignment());
14009 // Insert the word loaded into a vector.
14010 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14011 LoadUnitVecVT, ScalarLoad);
14013 // Bitcast the loaded value to a vector of the original element type, in
14014 // the size of the target vector type.
14015 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14017 unsigned SizeRatio = RegSz/MemSz;
14019 // Redistribute the loaded elements into the different locations.
14020 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14021 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14023 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14024 DAG.getUNDEF(SlicedVec.getValueType()),
14025 ShuffleVec.data());
14027 // Bitcast to the requested type.
14028 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14029 // Replace the original load with the new sequence
14030 // and return the new chain.
14031 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14032 return SDValue(ScalarLoad.getNode(), 1);
14038 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14039 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14040 const X86Subtarget *Subtarget) {
14041 StoreSDNode *St = cast<StoreSDNode>(N);
14042 EVT VT = St->getValue().getValueType();
14043 EVT StVT = St->getMemoryVT();
14044 DebugLoc dl = St->getDebugLoc();
14045 SDValue StoredVal = St->getOperand(1);
14046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14048 // If we are saving a concatenation of two XMM registers, perform two stores.
14049 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14050 // 128-bit ones. If in the future the cost becomes only one memory access the
14051 // first version would be better.
14052 if (VT.getSizeInBits() == 256 &&
14053 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14054 StoredVal.getNumOperands() == 2) {
14056 SDValue Value0 = StoredVal.getOperand(0);
14057 SDValue Value1 = StoredVal.getOperand(1);
14059 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14060 SDValue Ptr0 = St->getBasePtr();
14061 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14063 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14064 St->getPointerInfo(), St->isVolatile(),
14065 St->isNonTemporal(), St->getAlignment());
14066 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14067 St->getPointerInfo(), St->isVolatile(),
14068 St->isNonTemporal(), St->getAlignment());
14069 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14072 // Optimize trunc store (of multiple scalars) to shuffle and store.
14073 // First, pack all of the elements in one place. Next, store to memory
14074 // in fewer chunks.
14075 if (St->isTruncatingStore() && VT.isVector()) {
14076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14077 unsigned NumElems = VT.getVectorNumElements();
14078 assert(StVT != VT && "Cannot truncate to the same type");
14079 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14080 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14082 // From, To sizes and ElemCount must be pow of two
14083 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14084 // We are going to use the original vector elt for storing.
14085 // Accumulated smaller vector elements must be a multiple of the store size.
14086 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14088 unsigned SizeRatio = FromSz / ToSz;
14090 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14092 // Create a type on which we perform the shuffle
14093 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14094 StVT.getScalarType(), NumElems*SizeRatio);
14096 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14098 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14099 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14100 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14102 // Can't shuffle using an illegal type
14103 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14105 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14106 DAG.getUNDEF(WideVec.getValueType()),
14107 ShuffleVec.data());
14108 // At this point all of the data is stored at the bottom of the
14109 // register. We now need to save it to mem.
14111 // Find the largest store unit
14112 MVT StoreType = MVT::i8;
14113 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14114 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14115 MVT Tp = (MVT::SimpleValueType)tp;
14116 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14120 // Bitcast the original vector into a vector of store-size units
14121 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14122 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14123 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14124 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14125 SmallVector<SDValue, 8> Chains;
14126 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14127 TLI.getPointerTy());
14128 SDValue Ptr = St->getBasePtr();
14130 // Perform one or more big stores into memory.
14131 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14132 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14133 StoreType, ShuffWide,
14134 DAG.getIntPtrConstant(i));
14135 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14136 St->getPointerInfo(), St->isVolatile(),
14137 St->isNonTemporal(), St->getAlignment());
14138 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14139 Chains.push_back(Ch);
14142 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14147 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14148 // the FP state in cases where an emms may be missing.
14149 // A preferable solution to the general problem is to figure out the right
14150 // places to insert EMMS. This qualifies as a quick hack.
14152 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14153 if (VT.getSizeInBits() != 64)
14156 const Function *F = DAG.getMachineFunction().getFunction();
14157 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14158 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14159 && Subtarget->hasSSE2();
14160 if ((VT.isVector() ||
14161 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14162 isa<LoadSDNode>(St->getValue()) &&
14163 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14164 St->getChain().hasOneUse() && !St->isVolatile()) {
14165 SDNode* LdVal = St->getValue().getNode();
14166 LoadSDNode *Ld = 0;
14167 int TokenFactorIndex = -1;
14168 SmallVector<SDValue, 8> Ops;
14169 SDNode* ChainVal = St->getChain().getNode();
14170 // Must be a store of a load. We currently handle two cases: the load
14171 // is a direct child, and it's under an intervening TokenFactor. It is
14172 // possible to dig deeper under nested TokenFactors.
14173 if (ChainVal == LdVal)
14174 Ld = cast<LoadSDNode>(St->getChain());
14175 else if (St->getValue().hasOneUse() &&
14176 ChainVal->getOpcode() == ISD::TokenFactor) {
14177 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14178 if (ChainVal->getOperand(i).getNode() == LdVal) {
14179 TokenFactorIndex = i;
14180 Ld = cast<LoadSDNode>(St->getValue());
14182 Ops.push_back(ChainVal->getOperand(i));
14186 if (!Ld || !ISD::isNormalLoad(Ld))
14189 // If this is not the MMX case, i.e. we are just turning i64 load/store
14190 // into f64 load/store, avoid the transformation if there are multiple
14191 // uses of the loaded value.
14192 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14195 DebugLoc LdDL = Ld->getDebugLoc();
14196 DebugLoc StDL = N->getDebugLoc();
14197 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14198 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14200 if (Subtarget->is64Bit() || F64IsLegal) {
14201 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14202 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14203 Ld->getPointerInfo(), Ld->isVolatile(),
14204 Ld->isNonTemporal(), Ld->isInvariant(),
14205 Ld->getAlignment());
14206 SDValue NewChain = NewLd.getValue(1);
14207 if (TokenFactorIndex != -1) {
14208 Ops.push_back(NewChain);
14209 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14212 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14213 St->getPointerInfo(),
14214 St->isVolatile(), St->isNonTemporal(),
14215 St->getAlignment());
14218 // Otherwise, lower to two pairs of 32-bit loads / stores.
14219 SDValue LoAddr = Ld->getBasePtr();
14220 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14221 DAG.getConstant(4, MVT::i32));
14223 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14224 Ld->getPointerInfo(),
14225 Ld->isVolatile(), Ld->isNonTemporal(),
14226 Ld->isInvariant(), Ld->getAlignment());
14227 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14228 Ld->getPointerInfo().getWithOffset(4),
14229 Ld->isVolatile(), Ld->isNonTemporal(),
14231 MinAlign(Ld->getAlignment(), 4));
14233 SDValue NewChain = LoLd.getValue(1);
14234 if (TokenFactorIndex != -1) {
14235 Ops.push_back(LoLd);
14236 Ops.push_back(HiLd);
14237 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14241 LoAddr = St->getBasePtr();
14242 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14243 DAG.getConstant(4, MVT::i32));
14245 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14246 St->getPointerInfo(),
14247 St->isVolatile(), St->isNonTemporal(),
14248 St->getAlignment());
14249 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14250 St->getPointerInfo().getWithOffset(4),
14252 St->isNonTemporal(),
14253 MinAlign(St->getAlignment(), 4));
14254 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14259 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14260 /// and return the operands for the horizontal operation in LHS and RHS. A
14261 /// horizontal operation performs the binary operation on successive elements
14262 /// of its first operand, then on successive elements of its second operand,
14263 /// returning the resulting values in a vector. For example, if
14264 /// A = < float a0, float a1, float a2, float a3 >
14266 /// B = < float b0, float b1, float b2, float b3 >
14267 /// then the result of doing a horizontal operation on A and B is
14268 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14269 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14270 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14271 /// set to A, RHS to B, and the routine returns 'true'.
14272 /// Note that the binary operation should have the property that if one of the
14273 /// operands is UNDEF then the result is UNDEF.
14274 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14275 // Look for the following pattern: if
14276 // A = < float a0, float a1, float a2, float a3 >
14277 // B = < float b0, float b1, float b2, float b3 >
14279 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14280 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14281 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14282 // which is A horizontal-op B.
14284 // At least one of the operands should be a vector shuffle.
14285 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14286 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14289 EVT VT = LHS.getValueType();
14291 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14292 "Unsupported vector type for horizontal add/sub");
14294 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14295 // operate independently on 128-bit lanes.
14296 unsigned NumElts = VT.getVectorNumElements();
14297 unsigned NumLanes = VT.getSizeInBits()/128;
14298 unsigned NumLaneElts = NumElts / NumLanes;
14299 assert((NumLaneElts % 2 == 0) &&
14300 "Vector type should have an even number of elements in each lane");
14301 unsigned HalfLaneElts = NumLaneElts/2;
14303 // View LHS in the form
14304 // LHS = VECTOR_SHUFFLE A, B, LMask
14305 // If LHS is not a shuffle then pretend it is the shuffle
14306 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14307 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14310 SmallVector<int, 16> LMask(NumElts);
14311 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14312 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14313 A = LHS.getOperand(0);
14314 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14315 B = LHS.getOperand(1);
14316 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14317 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14319 if (LHS.getOpcode() != ISD::UNDEF)
14321 for (unsigned i = 0; i != NumElts; ++i)
14325 // Likewise, view RHS in the form
14326 // RHS = VECTOR_SHUFFLE C, D, RMask
14328 SmallVector<int, 16> RMask(NumElts);
14329 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14330 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14331 C = RHS.getOperand(0);
14332 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14333 D = RHS.getOperand(1);
14334 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14335 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14337 if (RHS.getOpcode() != ISD::UNDEF)
14339 for (unsigned i = 0; i != NumElts; ++i)
14343 // Check that the shuffles are both shuffling the same vectors.
14344 if (!(A == C && B == D) && !(A == D && B == C))
14347 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14348 if (!A.getNode() && !B.getNode())
14351 // If A and B occur in reverse order in RHS, then "swap" them (which means
14352 // rewriting the mask).
14354 CommuteVectorShuffleMask(RMask, NumElts);
14356 // At this point LHS and RHS are equivalent to
14357 // LHS = VECTOR_SHUFFLE A, B, LMask
14358 // RHS = VECTOR_SHUFFLE A, B, RMask
14359 // Check that the masks correspond to performing a horizontal operation.
14360 for (unsigned i = 0; i != NumElts; ++i) {
14361 int LIdx = LMask[i], RIdx = RMask[i];
14363 // Ignore any UNDEF components.
14364 if (LIdx < 0 || RIdx < 0 ||
14365 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14366 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14369 // Check that successive elements are being operated on. If not, this is
14370 // not a horizontal operation.
14371 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14372 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14373 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14374 if (!(LIdx == Index && RIdx == Index + 1) &&
14375 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14379 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14380 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14384 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14385 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14386 const X86Subtarget *Subtarget) {
14387 EVT VT = N->getValueType(0);
14388 SDValue LHS = N->getOperand(0);
14389 SDValue RHS = N->getOperand(1);
14391 // Try to synthesize horizontal adds from adds of shuffles.
14392 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14393 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14394 isHorizontalBinOp(LHS, RHS, true))
14395 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14399 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14400 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14401 const X86Subtarget *Subtarget) {
14402 EVT VT = N->getValueType(0);
14403 SDValue LHS = N->getOperand(0);
14404 SDValue RHS = N->getOperand(1);
14406 // Try to synthesize horizontal subs from subs of shuffles.
14407 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14408 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14409 isHorizontalBinOp(LHS, RHS, false))
14410 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14414 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14415 /// X86ISD::FXOR nodes.
14416 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14417 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14418 // F[X]OR(0.0, x) -> x
14419 // F[X]OR(x, 0.0) -> x
14420 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14421 if (C->getValueAPF().isPosZero())
14422 return N->getOperand(1);
14423 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14424 if (C->getValueAPF().isPosZero())
14425 return N->getOperand(0);
14429 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14430 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14431 // FAND(0.0, x) -> 0.0
14432 // FAND(x, 0.0) -> 0.0
14433 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14434 if (C->getValueAPF().isPosZero())
14435 return N->getOperand(0);
14436 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14437 if (C->getValueAPF().isPosZero())
14438 return N->getOperand(1);
14442 static SDValue PerformBTCombine(SDNode *N,
14444 TargetLowering::DAGCombinerInfo &DCI) {
14445 // BT ignores high bits in the bit index operand.
14446 SDValue Op1 = N->getOperand(1);
14447 if (Op1.hasOneUse()) {
14448 unsigned BitWidth = Op1.getValueSizeInBits();
14449 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14450 APInt KnownZero, KnownOne;
14451 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14452 !DCI.isBeforeLegalizeOps());
14453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14454 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14455 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14456 DCI.CommitTargetLoweringOpt(TLO);
14461 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14462 SDValue Op = N->getOperand(0);
14463 if (Op.getOpcode() == ISD::BITCAST)
14464 Op = Op.getOperand(0);
14465 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14466 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14467 VT.getVectorElementType().getSizeInBits() ==
14468 OpVT.getVectorElementType().getSizeInBits()) {
14469 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14474 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14475 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14476 // (and (i32 x86isd::setcc_carry), 1)
14477 // This eliminates the zext. This transformation is necessary because
14478 // ISD::SETCC is always legalized to i8.
14479 DebugLoc dl = N->getDebugLoc();
14480 SDValue N0 = N->getOperand(0);
14481 EVT VT = N->getValueType(0);
14482 if (N0.getOpcode() == ISD::AND &&
14484 N0.getOperand(0).hasOneUse()) {
14485 SDValue N00 = N0.getOperand(0);
14486 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14488 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14489 if (!C || C->getZExtValue() != 1)
14491 return DAG.getNode(ISD::AND, dl, VT,
14492 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14493 N00.getOperand(0), N00.getOperand(1)),
14494 DAG.getConstant(1, VT));
14500 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14501 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14502 unsigned X86CC = N->getConstantOperandVal(0);
14503 SDValue EFLAG = N->getOperand(1);
14504 DebugLoc DL = N->getDebugLoc();
14506 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14507 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14509 if (X86CC == X86::COND_B)
14510 return DAG.getNode(ISD::AND, DL, MVT::i8,
14511 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14512 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14513 DAG.getConstant(1, MVT::i8));
14518 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14519 const X86TargetLowering *XTLI) {
14520 SDValue Op0 = N->getOperand(0);
14521 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14522 // a 32-bit target where SSE doesn't support i64->FP operations.
14523 if (Op0.getOpcode() == ISD::LOAD) {
14524 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14525 EVT VT = Ld->getValueType(0);
14526 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14527 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14528 !XTLI->getSubtarget()->is64Bit() &&
14529 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14530 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14531 Ld->getChain(), Op0, DAG);
14532 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14539 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14540 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14541 X86TargetLowering::DAGCombinerInfo &DCI) {
14542 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14543 // the result is either zero or one (depending on the input carry bit).
14544 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14545 if (X86::isZeroNode(N->getOperand(0)) &&
14546 X86::isZeroNode(N->getOperand(1)) &&
14547 // We don't have a good way to replace an EFLAGS use, so only do this when
14549 SDValue(N, 1).use_empty()) {
14550 DebugLoc DL = N->getDebugLoc();
14551 EVT VT = N->getValueType(0);
14552 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14553 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14554 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14555 DAG.getConstant(X86::COND_B,MVT::i8),
14557 DAG.getConstant(1, VT));
14558 return DCI.CombineTo(N, Res1, CarryOut);
14564 // fold (add Y, (sete X, 0)) -> adc 0, Y
14565 // (add Y, (setne X, 0)) -> sbb -1, Y
14566 // (sub (sete X, 0), Y) -> sbb 0, Y
14567 // (sub (setne X, 0), Y) -> adc -1, Y
14568 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14569 DebugLoc DL = N->getDebugLoc();
14571 // Look through ZExts.
14572 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14573 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14576 SDValue SetCC = Ext.getOperand(0);
14577 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14580 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14581 if (CC != X86::COND_E && CC != X86::COND_NE)
14584 SDValue Cmp = SetCC.getOperand(1);
14585 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14586 !X86::isZeroNode(Cmp.getOperand(1)) ||
14587 !Cmp.getOperand(0).getValueType().isInteger())
14590 SDValue CmpOp0 = Cmp.getOperand(0);
14591 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14592 DAG.getConstant(1, CmpOp0.getValueType()));
14594 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14595 if (CC == X86::COND_NE)
14596 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14597 DL, OtherVal.getValueType(), OtherVal,
14598 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14599 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14600 DL, OtherVal.getValueType(), OtherVal,
14601 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14604 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14605 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14606 const X86Subtarget *Subtarget) {
14607 EVT VT = N->getValueType(0);
14608 SDValue Op0 = N->getOperand(0);
14609 SDValue Op1 = N->getOperand(1);
14611 // Try to synthesize horizontal adds from adds of shuffles.
14612 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14613 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14614 isHorizontalBinOp(Op0, Op1, true))
14615 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14617 return OptimizeConditionalInDecrement(N, DAG);
14620 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14621 const X86Subtarget *Subtarget) {
14622 SDValue Op0 = N->getOperand(0);
14623 SDValue Op1 = N->getOperand(1);
14625 // X86 can't encode an immediate LHS of a sub. See if we can push the
14626 // negation into a preceding instruction.
14627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14628 // If the RHS of the sub is a XOR with one use and a constant, invert the
14629 // immediate. Then add one to the LHS of the sub so we can turn
14630 // X-Y -> X+~Y+1, saving one register.
14631 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14632 isa<ConstantSDNode>(Op1.getOperand(1))) {
14633 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14634 EVT VT = Op0.getValueType();
14635 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14637 DAG.getConstant(~XorC, VT));
14638 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14639 DAG.getConstant(C->getAPIntValue()+1, VT));
14643 // Try to synthesize horizontal adds from adds of shuffles.
14644 EVT VT = N->getValueType(0);
14645 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14646 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14647 isHorizontalBinOp(Op0, Op1, true))
14648 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14650 return OptimizeConditionalInDecrement(N, DAG);
14653 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14654 DAGCombinerInfo &DCI) const {
14655 SelectionDAG &DAG = DCI.DAG;
14656 switch (N->getOpcode()) {
14658 case ISD::EXTRACT_VECTOR_ELT:
14659 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14661 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14662 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14663 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14664 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14665 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14666 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14669 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14670 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14671 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14672 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14673 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14674 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14675 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14676 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14677 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14679 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14680 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14681 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14682 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14683 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14684 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14685 case X86ISD::SHUFP: // Handle all target specific shuffles
14686 case X86ISD::PALIGN:
14687 case X86ISD::UNPCKH:
14688 case X86ISD::UNPCKL:
14689 case X86ISD::MOVHLPS:
14690 case X86ISD::MOVLHPS:
14691 case X86ISD::PSHUFD:
14692 case X86ISD::PSHUFHW:
14693 case X86ISD::PSHUFLW:
14694 case X86ISD::MOVSS:
14695 case X86ISD::MOVSD:
14696 case X86ISD::VPERMILP:
14697 case X86ISD::VPERM2X128:
14698 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14704 /// isTypeDesirableForOp - Return true if the target has native support for
14705 /// the specified value type and it is 'desirable' to use the type for the
14706 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14707 /// instruction encodings are longer and some i16 instructions are slow.
14708 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14709 if (!isTypeLegal(VT))
14711 if (VT != MVT::i16)
14718 case ISD::SIGN_EXTEND:
14719 case ISD::ZERO_EXTEND:
14720 case ISD::ANY_EXTEND:
14733 /// IsDesirableToPromoteOp - This method query the target whether it is
14734 /// beneficial for dag combiner to promote the specified node. If true, it
14735 /// should return the desired promotion type by reference.
14736 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14737 EVT VT = Op.getValueType();
14738 if (VT != MVT::i16)
14741 bool Promote = false;
14742 bool Commute = false;
14743 switch (Op.getOpcode()) {
14746 LoadSDNode *LD = cast<LoadSDNode>(Op);
14747 // If the non-extending load has a single use and it's not live out, then it
14748 // might be folded.
14749 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14750 Op.hasOneUse()*/) {
14751 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14752 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14753 // The only case where we'd want to promote LOAD (rather then it being
14754 // promoted as an operand is when it's only use is liveout.
14755 if (UI->getOpcode() != ISD::CopyToReg)
14762 case ISD::SIGN_EXTEND:
14763 case ISD::ZERO_EXTEND:
14764 case ISD::ANY_EXTEND:
14769 SDValue N0 = Op.getOperand(0);
14770 // Look out for (store (shl (load), x)).
14771 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14784 SDValue N0 = Op.getOperand(0);
14785 SDValue N1 = Op.getOperand(1);
14786 if (!Commute && MayFoldLoad(N1))
14788 // Avoid disabling potential load folding opportunities.
14789 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14791 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14801 //===----------------------------------------------------------------------===//
14802 // X86 Inline Assembly Support
14803 //===----------------------------------------------------------------------===//
14806 // Helper to match a string separated by whitespace.
14807 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14808 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14810 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14811 StringRef piece(*args[i]);
14812 if (!s.startswith(piece)) // Check if the piece matches.
14815 s = s.substr(piece.size());
14816 StringRef::size_type pos = s.find_first_not_of(" \t");
14817 if (pos == 0) // We matched a prefix.
14825 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14828 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14829 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14831 std::string AsmStr = IA->getAsmString();
14833 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14834 if (!Ty || Ty->getBitWidth() % 16 != 0)
14837 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14838 SmallVector<StringRef, 4> AsmPieces;
14839 SplitString(AsmStr, AsmPieces, ";\n");
14841 switch (AsmPieces.size()) {
14842 default: return false;
14844 // FIXME: this should verify that we are targeting a 486 or better. If not,
14845 // we will turn this bswap into something that will be lowered to logical
14846 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14847 // lower so don't worry about this.
14849 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14850 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14851 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14852 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14853 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14854 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14855 // No need to check constraints, nothing other than the equivalent of
14856 // "=r,0" would be valid here.
14857 return IntrinsicLowering::LowerToByteSwap(CI);
14860 // rorw $$8, ${0:w} --> llvm.bswap.i16
14861 if (CI->getType()->isIntegerTy(16) &&
14862 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14863 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14864 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14866 const std::string &ConstraintsStr = IA->getConstraintString();
14867 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14868 std::sort(AsmPieces.begin(), AsmPieces.end());
14869 if (AsmPieces.size() == 4 &&
14870 AsmPieces[0] == "~{cc}" &&
14871 AsmPieces[1] == "~{dirflag}" &&
14872 AsmPieces[2] == "~{flags}" &&
14873 AsmPieces[3] == "~{fpsr}")
14874 return IntrinsicLowering::LowerToByteSwap(CI);
14878 if (CI->getType()->isIntegerTy(32) &&
14879 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14880 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14881 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14882 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14884 const std::string &ConstraintsStr = IA->getConstraintString();
14885 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14886 std::sort(AsmPieces.begin(), AsmPieces.end());
14887 if (AsmPieces.size() == 4 &&
14888 AsmPieces[0] == "~{cc}" &&
14889 AsmPieces[1] == "~{dirflag}" &&
14890 AsmPieces[2] == "~{flags}" &&
14891 AsmPieces[3] == "~{fpsr}")
14892 return IntrinsicLowering::LowerToByteSwap(CI);
14895 if (CI->getType()->isIntegerTy(64)) {
14896 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14897 if (Constraints.size() >= 2 &&
14898 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14899 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14900 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14901 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14902 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14903 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14904 return IntrinsicLowering::LowerToByteSwap(CI);
14914 /// getConstraintType - Given a constraint letter, return the type of
14915 /// constraint it is for this target.
14916 X86TargetLowering::ConstraintType
14917 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14918 if (Constraint.size() == 1) {
14919 switch (Constraint[0]) {
14930 return C_RegisterClass;
14954 return TargetLowering::getConstraintType(Constraint);
14957 /// Examine constraint type and operand type and determine a weight value.
14958 /// This object must already have been set up with the operand type
14959 /// and the current alternative constraint selected.
14960 TargetLowering::ConstraintWeight
14961 X86TargetLowering::getSingleConstraintMatchWeight(
14962 AsmOperandInfo &info, const char *constraint) const {
14963 ConstraintWeight weight = CW_Invalid;
14964 Value *CallOperandVal = info.CallOperandVal;
14965 // If we don't have a value, we can't do a match,
14966 // but allow it at the lowest weight.
14967 if (CallOperandVal == NULL)
14969 Type *type = CallOperandVal->getType();
14970 // Look at the constraint type.
14971 switch (*constraint) {
14973 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14984 if (CallOperandVal->getType()->isIntegerTy())
14985 weight = CW_SpecificReg;
14990 if (type->isFloatingPointTy())
14991 weight = CW_SpecificReg;
14994 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14995 weight = CW_SpecificReg;
14999 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15000 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15001 weight = CW_Register;
15004 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15005 if (C->getZExtValue() <= 31)
15006 weight = CW_Constant;
15010 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15011 if (C->getZExtValue() <= 63)
15012 weight = CW_Constant;
15016 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15017 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15018 weight = CW_Constant;
15022 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15023 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15024 weight = CW_Constant;
15028 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15029 if (C->getZExtValue() <= 3)
15030 weight = CW_Constant;
15034 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15035 if (C->getZExtValue() <= 0xff)
15036 weight = CW_Constant;
15041 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15042 weight = CW_Constant;
15046 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15047 if ((C->getSExtValue() >= -0x80000000LL) &&
15048 (C->getSExtValue() <= 0x7fffffffLL))
15049 weight = CW_Constant;
15053 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15054 if (C->getZExtValue() <= 0xffffffff)
15055 weight = CW_Constant;
15062 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15063 /// with another that has more specific requirements based on the type of the
15064 /// corresponding operand.
15065 const char *X86TargetLowering::
15066 LowerXConstraint(EVT ConstraintVT) const {
15067 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15068 // 'f' like normal targets.
15069 if (ConstraintVT.isFloatingPoint()) {
15070 if (Subtarget->hasSSE2())
15072 if (Subtarget->hasSSE1())
15076 return TargetLowering::LowerXConstraint(ConstraintVT);
15079 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15080 /// vector. If it is invalid, don't add anything to Ops.
15081 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15082 std::string &Constraint,
15083 std::vector<SDValue>&Ops,
15084 SelectionDAG &DAG) const {
15085 SDValue Result(0, 0);
15087 // Only support length 1 constraints for now.
15088 if (Constraint.length() > 1) return;
15090 char ConstraintLetter = Constraint[0];
15091 switch (ConstraintLetter) {
15094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15095 if (C->getZExtValue() <= 31) {
15096 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15103 if (C->getZExtValue() <= 63) {
15104 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15111 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15112 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15119 if (C->getZExtValue() <= 255) {
15120 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15126 // 32-bit signed value
15127 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15128 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15129 C->getSExtValue())) {
15130 // Widen to 64 bits here to get it sign extended.
15131 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15134 // FIXME gcc accepts some relocatable values here too, but only in certain
15135 // memory models; it's complicated.
15140 // 32-bit unsigned value
15141 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15142 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15143 C->getZExtValue())) {
15144 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15148 // FIXME gcc accepts some relocatable values here too, but only in certain
15149 // memory models; it's complicated.
15153 // Literal immediates are always ok.
15154 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15155 // Widen to 64 bits here to get it sign extended.
15156 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15160 // In any sort of PIC mode addresses need to be computed at runtime by
15161 // adding in a register or some sort of table lookup. These can't
15162 // be used as immediates.
15163 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15166 // If we are in non-pic codegen mode, we allow the address of a global (with
15167 // an optional displacement) to be used with 'i'.
15168 GlobalAddressSDNode *GA = 0;
15169 int64_t Offset = 0;
15171 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15173 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15174 Offset += GA->getOffset();
15176 } else if (Op.getOpcode() == ISD::ADD) {
15177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15178 Offset += C->getZExtValue();
15179 Op = Op.getOperand(0);
15182 } else if (Op.getOpcode() == ISD::SUB) {
15183 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15184 Offset += -C->getZExtValue();
15185 Op = Op.getOperand(0);
15190 // Otherwise, this isn't something we can handle, reject it.
15194 const GlobalValue *GV = GA->getGlobal();
15195 // If we require an extra load to get this address, as in PIC mode, we
15196 // can't accept it.
15197 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15198 getTargetMachine())))
15201 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15202 GA->getValueType(0), Offset);
15207 if (Result.getNode()) {
15208 Ops.push_back(Result);
15211 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15214 std::pair<unsigned, const TargetRegisterClass*>
15215 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15217 // First, see if this is a constraint that directly corresponds to an LLVM
15219 if (Constraint.size() == 1) {
15220 // GCC Constraint Letters
15221 switch (Constraint[0]) {
15223 // TODO: Slight differences here in allocation order and leaving
15224 // RIP in the class. Do they matter any more here than they do
15225 // in the normal allocation?
15226 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15227 if (Subtarget->is64Bit()) {
15228 if (VT == MVT::i32 || VT == MVT::f32)
15229 return std::make_pair(0U, X86::GR32RegisterClass);
15230 else if (VT == MVT::i16)
15231 return std::make_pair(0U, X86::GR16RegisterClass);
15232 else if (VT == MVT::i8 || VT == MVT::i1)
15233 return std::make_pair(0U, X86::GR8RegisterClass);
15234 else if (VT == MVT::i64 || VT == MVT::f64)
15235 return std::make_pair(0U, X86::GR64RegisterClass);
15238 // 32-bit fallthrough
15239 case 'Q': // Q_REGS
15240 if (VT == MVT::i32 || VT == MVT::f32)
15241 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15242 else if (VT == MVT::i16)
15243 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15244 else if (VT == MVT::i8 || VT == MVT::i1)
15245 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15246 else if (VT == MVT::i64)
15247 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15249 case 'r': // GENERAL_REGS
15250 case 'l': // INDEX_REGS
15251 if (VT == MVT::i8 || VT == MVT::i1)
15252 return std::make_pair(0U, X86::GR8RegisterClass);
15253 if (VT == MVT::i16)
15254 return std::make_pair(0U, X86::GR16RegisterClass);
15255 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15256 return std::make_pair(0U, X86::GR32RegisterClass);
15257 return std::make_pair(0U, X86::GR64RegisterClass);
15258 case 'R': // LEGACY_REGS
15259 if (VT == MVT::i8 || VT == MVT::i1)
15260 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15261 if (VT == MVT::i16)
15262 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15263 if (VT == MVT::i32 || !Subtarget->is64Bit())
15264 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15265 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15266 case 'f': // FP Stack registers.
15267 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15268 // value to the correct fpstack register class.
15269 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15270 return std::make_pair(0U, X86::RFP32RegisterClass);
15271 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15272 return std::make_pair(0U, X86::RFP64RegisterClass);
15273 return std::make_pair(0U, X86::RFP80RegisterClass);
15274 case 'y': // MMX_REGS if MMX allowed.
15275 if (!Subtarget->hasMMX()) break;
15276 return std::make_pair(0U, X86::VR64RegisterClass);
15277 case 'Y': // SSE_REGS if SSE2 allowed
15278 if (!Subtarget->hasSSE2()) break;
15280 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15281 if (!Subtarget->hasSSE1()) break;
15283 switch (VT.getSimpleVT().SimpleTy) {
15285 // Scalar SSE types.
15288 return std::make_pair(0U, X86::FR32RegisterClass);
15291 return std::make_pair(0U, X86::FR64RegisterClass);
15299 return std::make_pair(0U, X86::VR128RegisterClass);
15307 return std::make_pair(0U, X86::VR256RegisterClass);
15314 // Use the default implementation in TargetLowering to convert the register
15315 // constraint into a member of a register class.
15316 std::pair<unsigned, const TargetRegisterClass*> Res;
15317 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15319 // Not found as a standard register?
15320 if (Res.second == 0) {
15321 // Map st(0) -> st(7) -> ST0
15322 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15323 tolower(Constraint[1]) == 's' &&
15324 tolower(Constraint[2]) == 't' &&
15325 Constraint[3] == '(' &&
15326 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15327 Constraint[5] == ')' &&
15328 Constraint[6] == '}') {
15330 Res.first = X86::ST0+Constraint[4]-'0';
15331 Res.second = X86::RFP80RegisterClass;
15335 // GCC allows "st(0)" to be called just plain "st".
15336 if (StringRef("{st}").equals_lower(Constraint)) {
15337 Res.first = X86::ST0;
15338 Res.second = X86::RFP80RegisterClass;
15343 if (StringRef("{flags}").equals_lower(Constraint)) {
15344 Res.first = X86::EFLAGS;
15345 Res.second = X86::CCRRegisterClass;
15349 // 'A' means EAX + EDX.
15350 if (Constraint == "A") {
15351 Res.first = X86::EAX;
15352 Res.second = X86::GR32_ADRegisterClass;
15358 // Otherwise, check to see if this is a register class of the wrong value
15359 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15360 // turn into {ax},{dx}.
15361 if (Res.second->hasType(VT))
15362 return Res; // Correct type already, nothing to do.
15364 // All of the single-register GCC register classes map their values onto
15365 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15366 // really want an 8-bit or 32-bit register, map to the appropriate register
15367 // class and return the appropriate register.
15368 if (Res.second == X86::GR16RegisterClass) {
15369 if (VT == MVT::i8) {
15370 unsigned DestReg = 0;
15371 switch (Res.first) {
15373 case X86::AX: DestReg = X86::AL; break;
15374 case X86::DX: DestReg = X86::DL; break;
15375 case X86::CX: DestReg = X86::CL; break;
15376 case X86::BX: DestReg = X86::BL; break;
15379 Res.first = DestReg;
15380 Res.second = X86::GR8RegisterClass;
15382 } else if (VT == MVT::i32) {
15383 unsigned DestReg = 0;
15384 switch (Res.first) {
15386 case X86::AX: DestReg = X86::EAX; break;
15387 case X86::DX: DestReg = X86::EDX; break;
15388 case X86::CX: DestReg = X86::ECX; break;
15389 case X86::BX: DestReg = X86::EBX; break;
15390 case X86::SI: DestReg = X86::ESI; break;
15391 case X86::DI: DestReg = X86::EDI; break;
15392 case X86::BP: DestReg = X86::EBP; break;
15393 case X86::SP: DestReg = X86::ESP; break;
15396 Res.first = DestReg;
15397 Res.second = X86::GR32RegisterClass;
15399 } else if (VT == MVT::i64) {
15400 unsigned DestReg = 0;
15401 switch (Res.first) {
15403 case X86::AX: DestReg = X86::RAX; break;
15404 case X86::DX: DestReg = X86::RDX; break;
15405 case X86::CX: DestReg = X86::RCX; break;
15406 case X86::BX: DestReg = X86::RBX; break;
15407 case X86::SI: DestReg = X86::RSI; break;
15408 case X86::DI: DestReg = X86::RDI; break;
15409 case X86::BP: DestReg = X86::RBP; break;
15410 case X86::SP: DestReg = X86::RSP; break;
15413 Res.first = DestReg;
15414 Res.second = X86::GR64RegisterClass;
15417 } else if (Res.second == X86::FR32RegisterClass ||
15418 Res.second == X86::FR64RegisterClass ||
15419 Res.second == X86::VR128RegisterClass) {
15420 // Handle references to XMM physical registers that got mapped into the
15421 // wrong class. This can happen with constraints like {xmm0} where the
15422 // target independent register mapper will just pick the first match it can
15423 // find, ignoring the required type.
15424 if (VT == MVT::f32)
15425 Res.second = X86::FR32RegisterClass;
15426 else if (VT == MVT::f64)
15427 Res.second = X86::FR64RegisterClass;
15428 else if (X86::VR128RegisterClass->hasType(VT))
15429 Res.second = X86::VR128RegisterClass;