1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "X86IntrinsicsInfo.h"
58 #define DEBUG_TYPE "x86-isel"
60 STATISTIC(NumTailCalls, "Number of tail calls");
62 static cl::opt<bool> ExperimentalVectorWideningLegalization(
63 "x86-experimental-vector-widening-legalization", cl::init(false),
64 cl::desc("Enable an experimental vector type legalization through widening "
65 "rather than promotion."),
68 static cl::opt<bool> ExperimentalVectorShuffleLowering(
69 "x86-experimental-vector-shuffle-lowering", cl::init(false),
70 cl::desc("Enable an experimental vector shuffle lowering code path."),
73 // Forward declarations.
74 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
77 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
78 SelectionDAG &DAG, SDLoc dl,
79 unsigned vectorWidth) {
80 assert((vectorWidth == 128 || vectorWidth == 256) &&
81 "Unsupported vector width");
82 EVT VT = Vec.getValueType();
83 EVT ElVT = VT.getVectorElementType();
84 unsigned Factor = VT.getSizeInBits()/vectorWidth;
85 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
86 VT.getVectorNumElements()/Factor);
88 // Extract from UNDEF is UNDEF.
89 if (Vec.getOpcode() == ISD::UNDEF)
90 return DAG.getUNDEF(ResultVT);
92 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
93 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
95 // This is the index of the first element of the vectorWidth-bit chunk
97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
100 // If the input is a buildvector just emit a smaller one.
101 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
102 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
103 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
106 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
113 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
114 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
115 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
116 /// instructions or a simple subregister reference. Idx is an index in the
117 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
118 /// lowering EXTRACT_VECTOR_ELT operations easier.
119 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
120 SelectionDAG &DAG, SDLoc dl) {
121 assert((Vec.getValueType().is256BitVector() ||
122 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
123 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
126 /// Generate a DAG to grab 256-bits from a 512-bit vector.
127 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
128 SelectionDAG &DAG, SDLoc dl) {
129 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
133 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
134 unsigned IdxVal, SelectionDAG &DAG,
135 SDLoc dl, unsigned vectorWidth) {
136 assert((vectorWidth == 128 || vectorWidth == 256) &&
137 "Unsupported vector width");
138 // Inserting UNDEF is Result
139 if (Vec.getOpcode() == ISD::UNDEF)
141 EVT VT = Vec.getValueType();
142 EVT ElVT = VT.getVectorElementType();
143 EVT ResultVT = Result.getValueType();
145 // Insert the relevant vectorWidth bits.
146 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
148 // This is the index of the first element of the vectorWidth-bit chunk
150 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
153 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
154 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
157 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
158 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
159 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
160 /// simple superregister reference. Idx is an index in the 128 bits
161 /// we want. It need not be aligned to a 128-bit bounday. That makes
162 /// lowering INSERT_VECTOR_ELT operations easier.
163 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
164 unsigned IdxVal, SelectionDAG &DAG,
166 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
167 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
170 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
177 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
178 /// instructions. This is used because creating CONCAT_VECTOR nodes of
179 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
180 /// large BUILD_VECTORS.
181 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
182 unsigned NumElems, SelectionDAG &DAG,
184 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
185 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
188 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
195 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
196 if (TT.isOSBinFormatMachO()) {
197 if (TT.getArch() == Triple::x86_64)
198 return new X86_64MachoTargetObjectFile();
199 return new TargetLoweringObjectFileMachO();
203 return new X86LinuxTargetObjectFile();
204 if (TT.isOSBinFormatELF())
205 return new TargetLoweringObjectFileELF();
206 if (TT.isKnownWindowsMSVCEnvironment())
207 return new X86WindowsTargetObjectFile();
208 if (TT.isOSBinFormatCOFF())
209 return new TargetLoweringObjectFileCOFF();
210 llvm_unreachable("unknown subtarget type");
213 // FIXME: This should stop caching the target machine as soon as
214 // we can remove resetOperationActions et al.
215 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
216 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
217 Subtarget = &TM.getSubtarget<X86Subtarget>();
218 X86ScalarSSEf64 = Subtarget->hasSSE2();
219 X86ScalarSSEf32 = Subtarget->hasSSE1();
220 TD = getDataLayout();
222 resetOperationActions();
225 void X86TargetLowering::resetOperationActions() {
226 const TargetMachine &TM = getTargetMachine();
227 static bool FirstTimeThrough = true;
229 // If none of the target options have changed, then we don't need to reset the
230 // operation actions.
231 if (!FirstTimeThrough && TO == TM.Options) return;
233 if (!FirstTimeThrough) {
234 // Reinitialize the actions.
236 FirstTimeThrough = false;
241 // Set up the TargetLowering object.
242 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
244 // X86 is weird, it always uses i8 for shift amounts and setcc results.
245 setBooleanContents(ZeroOrOneBooleanContent);
246 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
247 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
249 // For 64-bit since we have so many registers use the ILP scheduler, for
250 // 32-bit code use the register pressure specific scheduling.
251 // For Atom, always use ILP scheduling.
252 if (Subtarget->isAtom())
253 setSchedulingPreference(Sched::ILP);
254 else if (Subtarget->is64Bit())
255 setSchedulingPreference(Sched::ILP);
257 setSchedulingPreference(Sched::RegPressure);
258 const X86RegisterInfo *RegInfo =
259 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
260 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
262 // Bypass expensive divides on Atom when compiling with O2
263 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
264 addBypassSlowDiv(32, 8);
265 if (Subtarget->is64Bit())
266 addBypassSlowDiv(64, 16);
269 if (Subtarget->isTargetKnownWindowsMSVC()) {
270 // Setup Windows compiler runtime calls.
271 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
272 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
273 setLibcallName(RTLIB::SREM_I64, "_allrem");
274 setLibcallName(RTLIB::UREM_I64, "_aullrem");
275 setLibcallName(RTLIB::MUL_I64, "_allmul");
276 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
282 // The _ftol2 runtime function has an unusual calling conv, which
283 // is modeled by a special pseudo-instruction.
284 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
290 if (Subtarget->isTargetDarwin()) {
291 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
292 setUseUnderscoreSetJmp(false);
293 setUseUnderscoreLongJmp(false);
294 } else if (Subtarget->isTargetWindowsGNU()) {
295 // MS runtime is weird: it exports _setjmp, but longjmp!
296 setUseUnderscoreSetJmp(true);
297 setUseUnderscoreLongJmp(false);
299 setUseUnderscoreSetJmp(true);
300 setUseUnderscoreLongJmp(true);
303 // Set up the register classes.
304 addRegisterClass(MVT::i8, &X86::GR8RegClass);
305 addRegisterClass(MVT::i16, &X86::GR16RegClass);
306 addRegisterClass(MVT::i32, &X86::GR32RegClass);
307 if (Subtarget->is64Bit())
308 addRegisterClass(MVT::i64, &X86::GR64RegClass);
310 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
312 // We don't accept any truncstore of integer registers.
313 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
316 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
317 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
318 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
320 // SETOEQ and SETUNE require checking two conditions.
321 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
323 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
328 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
330 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
332 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
336 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
337 } else if (!TM.Options.UseSoftFloat) {
338 // We have an algorithm for SSE2->double, and we turn this into a
339 // 64-bit FILD followed by conditional FADD for other targets.
340 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
341 // We have an algorithm for SSE2, and we turn this into a 64-bit
342 // FILD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
346 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
348 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
351 if (!TM.Options.UseSoftFloat) {
352 // SSE has no i16 to fp conversion, only i32
353 if (X86ScalarSSEf32) {
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 // f32 and f64 cases are Legal, f80 case is not
356 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
363 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
366 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
367 // are Legal, f80 is custom lowered.
368 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
369 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
371 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
373 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
376 if (X86ScalarSSEf32) {
377 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
378 // f32 and f64 cases are Legal, f80 case is not
379 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
385 // Handle FP_TO_UINT by promoting the destination to a larger signed
387 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
389 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
391 if (Subtarget->is64Bit()) {
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
393 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
394 } else if (!TM.Options.UseSoftFloat) {
395 // Since AVX is a superset of SSE3, only check for SSE here.
396 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
397 // Expand FP_TO_UINT into a select.
398 // FIXME: We would like to use a Custom expander here eventually to do
399 // the optimal thing for SSE vs. the default expansion in the legalizer.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
402 // With SSE3 we can use fisttpll to convert to a signed i64; without
403 // SSE, we're stuck with a fistpll.
404 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
407 if (isTargetFTOL()) {
408 // Use the _ftol2 runtime function, which has a pseudo-instruction
409 // to handle its weird calling convention.
410 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
413 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
414 if (!X86ScalarSSEf64) {
415 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
416 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
419 // Without SSE, i64->f64 goes through memory.
420 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 // Scalar integer divide and remainder are lowered to use operations that
425 // produce two results, to match the available instructions. This exposes
426 // the two-result form to trivial CSE, which is able to combine x/y and x%y
427 // into a single instruction.
429 // Scalar integer multiply-high is also lowered to use two-result
430 // operations, to match the available instructions. However, plain multiply
431 // (low) operations are left as Legal, as there are single-result
432 // instructions for this in x86. Using the two-result multiply instructions
433 // when both high and low results are needed must be arranged by dagcombine.
434 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
436 setOperationAction(ISD::MULHS, VT, Expand);
437 setOperationAction(ISD::MULHU, VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::UDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
443 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
444 setOperationAction(ISD::ADDC, VT, Custom);
445 setOperationAction(ISD::ADDE, VT, Custom);
446 setOperationAction(ISD::SUBC, VT, Custom);
447 setOperationAction(ISD::SUBE, VT, Custom);
450 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
451 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
452 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
454 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
471 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f32 , Expand);
473 setOperationAction(ISD::FREM , MVT::f64 , Expand);
474 setOperationAction(ISD::FREM , MVT::f80 , Expand);
475 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
477 // Promote the i8 variants and force them on up to i32 which has a shorter
479 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
480 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
481 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
482 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
483 if (Subtarget->hasBMI()) {
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
485 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
489 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
490 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
495 if (Subtarget->hasLZCNT()) {
496 // When promoting the i8 variants, force them to i32 for a shorter
498 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
499 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
501 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
504 if (Subtarget->is64Bit())
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
507 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
509 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
513 if (Subtarget->is64Bit()) {
514 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 // Special handling for half-precision floating point conversions.
520 // If we don't have F16C support, then lower half float conversions
521 // into library calls.
522 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
523 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
524 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
527 // There's never any support for operations beyond MVT::f32.
528 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
529 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
531 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
533 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
536 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
538 if (Subtarget->hasPOPCNT()) {
539 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
541 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
543 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
548 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
550 if (!Subtarget->hasMOVBE())
551 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
553 // These should be promoted to a larger select which is supported.
554 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
555 // X86 wants to expand cmov itself.
556 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
558 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
561 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
564 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
568 if (Subtarget->is64Bit()) {
569 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
572 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
573 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
574 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
575 // support continuation, user-level threading, and etc.. As a result, no
576 // other SjLj exception interfaces are implemented and please don't build
577 // your own exception handling based on them.
578 // LLVM/Clang supports zero-cost DWARF exception handling.
579 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
580 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
583 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
586 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
587 if (Subtarget->is64Bit())
588 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
589 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
590 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
591 if (Subtarget->is64Bit()) {
592 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
593 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
594 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
595 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
596 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
598 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
599 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
601 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
602 if (Subtarget->is64Bit()) {
603 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
605 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
608 if (Subtarget->hasSSE1())
609 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
611 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
613 // Expand certain atomics
614 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
616 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
617 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
618 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
621 if (Subtarget->hasCmpxchg16b()) {
622 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
625 // FIXME - use subtarget debug flags
626 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
627 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
628 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
631 if (Subtarget->is64Bit()) {
632 setExceptionPointerRegister(X86::RAX);
633 setExceptionSelectorRegister(X86::RDX);
635 setExceptionPointerRegister(X86::EAX);
636 setExceptionSelectorRegister(X86::EDX);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
639 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
641 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
642 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
644 setOperationAction(ISD::TRAP, MVT::Other, Legal);
645 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
647 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
648 setOperationAction(ISD::VASTART , MVT::Other, Custom);
649 setOperationAction(ISD::VAEND , MVT::Other, Expand);
650 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
651 // TargetInfo::X86_64ABIBuiltinVaList
652 setOperationAction(ISD::VAARG , MVT::Other, Custom);
653 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
655 // TargetInfo::CharPtrBuiltinVaList
656 setOperationAction(ISD::VAARG , MVT::Other, Expand);
657 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
660 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
661 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
663 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 // We support custom legalizing of sext and anyext loads for specific
1015 // memory vector types which we can load as a scalar (or sequence of
1016 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1017 // loads these must work with a single scalar load.
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1028 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1030 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1032 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1033 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1035 if (Subtarget->is64Bit()) {
1036 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1037 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1040 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1041 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1042 MVT VT = (MVT::SimpleValueType)i;
1044 // Do not attempt to promote non-128-bit vectors
1045 if (!VT.is128BitVector())
1048 setOperationAction(ISD::AND, VT, Promote);
1049 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1050 setOperationAction(ISD::OR, VT, Promote);
1051 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1052 setOperationAction(ISD::XOR, VT, Promote);
1053 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1054 setOperationAction(ISD::LOAD, VT, Promote);
1055 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1056 setOperationAction(ISD::SELECT, VT, Promote);
1057 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1060 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1062 // Custom lower v2i64 and v2f64 selects.
1063 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1064 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1065 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1068 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1073 // As there is no 64-bit GPR available, we need build a special custom
1074 // sequence to convert from v2i32 to v2f32.
1075 if (!Subtarget->is64Bit())
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1078 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1081 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1083 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1084 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1088 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1089 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1090 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1091 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1092 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1093 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1106 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1111 // FIXME: Do we need to handle scalar-to-vector here?
1112 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1114 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1115 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1119 // There is no BLENDI for byte vectors. We don't need to custom lower
1120 // some vselects for now.
1121 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1123 // SSE41 brings specific instructions for doing vector sign extend even in
1124 // cases where we don't have SRA.
1125 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1129 // i8 and i16 vectors are custom because the source register and source
1130 // source memory operand types are not the same width. f32 vectors are
1131 // custom since the immediate controlling the insert encodes additional
1133 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1143 // FIXME: these should be Legal, but that's only for the case where
1144 // the index is constant. For now custom expand to deal with that.
1145 if (Subtarget->is64Bit()) {
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1147 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1151 if (Subtarget->hasSSE2()) {
1152 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1153 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1155 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1156 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1158 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1159 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1161 // In the customized shift lowering, the legal cases in AVX2 will be
1163 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1164 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1166 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1167 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1169 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1172 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1173 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1180 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1184 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1195 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1208 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1210 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1211 // even though v8i16 is a legal type.
1212 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1213 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1216 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1218 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1220 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1223 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1225 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1243 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1248 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1251 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1261 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1262 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1265 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1266 setOperationAction(ISD::FMA, MVT::f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::f64, Legal);
1270 if (Subtarget->hasInt256()) {
1271 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1272 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1273 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1274 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1276 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1277 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1278 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1279 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1281 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1282 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1283 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1284 // Don't lower v32i8 because there is no 128-bit byte mul
1286 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1287 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1289 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1291 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1292 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1295 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1296 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1297 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1299 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1300 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1301 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1302 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1304 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1306 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1307 // Don't lower v32i8 because there is no 128-bit byte mul
1310 // In the customized shift lowering, the legal cases in AVX2 will be
1312 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1316 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1320 // Custom lower several nodes for 256-bit types.
1321 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1322 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1323 MVT VT = (MVT::SimpleValueType)i;
1325 // Extract subvector is special because the value type
1326 // (result) is 128-bit but the source is 256-bit wide.
1327 if (VT.is128BitVector())
1328 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1330 // Do not attempt to custom lower other non-256-bit vectors
1331 if (!VT.is256BitVector())
1334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1336 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1339 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1340 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1343 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1344 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1345 MVT VT = (MVT::SimpleValueType)i;
1347 // Do not attempt to promote non-256-bit vectors
1348 if (!VT.is256BitVector())
1351 setOperationAction(ISD::AND, VT, Promote);
1352 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1353 setOperationAction(ISD::OR, VT, Promote);
1354 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1355 setOperationAction(ISD::XOR, VT, Promote);
1356 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1357 setOperationAction(ISD::LOAD, VT, Promote);
1358 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1359 setOperationAction(ISD::SELECT, VT, Promote);
1360 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1365 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1366 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1371 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1372 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1374 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1376 setOperationAction(ISD::XOR, MVT::i1, Legal);
1377 setOperationAction(ISD::OR, MVT::i1, Legal);
1378 setOperationAction(ISD::AND, MVT::i1, Legal);
1379 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1386 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1393 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1399 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1406 if (Subtarget->is64Bit()) {
1407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1564 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1565 // of this type with custom code.
1566 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1567 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1568 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1572 // We want to custom lower some of our intrinsics.
1573 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1574 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1576 if (!Subtarget->is64Bit())
1577 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1579 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1580 // handle type legalization for these operations here.
1582 // FIXME: We really should do custom legalization for addition and
1583 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1584 // than generic legalization for 64-bit multiplication-with-overflow, though.
1585 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1586 // Add/Sub/Mul with overflow operations are custom lowered.
1588 setOperationAction(ISD::SADDO, VT, Custom);
1589 setOperationAction(ISD::UADDO, VT, Custom);
1590 setOperationAction(ISD::SSUBO, VT, Custom);
1591 setOperationAction(ISD::USUBO, VT, Custom);
1592 setOperationAction(ISD::SMULO, VT, Custom);
1593 setOperationAction(ISD::UMULO, VT, Custom);
1596 // There are no 8-bit 3-address imul/mul instructions
1597 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1598 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1600 if (!Subtarget->is64Bit()) {
1601 // These libcalls are not available in 32-bit.
1602 setLibcallName(RTLIB::SHL_I128, nullptr);
1603 setLibcallName(RTLIB::SRL_I128, nullptr);
1604 setLibcallName(RTLIB::SRA_I128, nullptr);
1607 // Combine sin / cos into one node or libcall if possible.
1608 if (Subtarget->hasSinCos()) {
1609 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1610 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1611 if (Subtarget->isTargetDarwin()) {
1612 // For MacOSX, we don't want to the normal expansion of a libcall to
1613 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1615 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1616 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1620 if (Subtarget->isTargetWin64()) {
1621 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1622 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::SREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UREM, MVT::i128, Custom);
1625 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1629 // We have target-specific dag combine patterns for the following nodes:
1630 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1631 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1632 setTargetDAGCombine(ISD::VSELECT);
1633 setTargetDAGCombine(ISD::SELECT);
1634 setTargetDAGCombine(ISD::SHL);
1635 setTargetDAGCombine(ISD::SRA);
1636 setTargetDAGCombine(ISD::SRL);
1637 setTargetDAGCombine(ISD::OR);
1638 setTargetDAGCombine(ISD::AND);
1639 setTargetDAGCombine(ISD::ADD);
1640 setTargetDAGCombine(ISD::FADD);
1641 setTargetDAGCombine(ISD::FSUB);
1642 setTargetDAGCombine(ISD::FMA);
1643 setTargetDAGCombine(ISD::SUB);
1644 setTargetDAGCombine(ISD::LOAD);
1645 setTargetDAGCombine(ISD::STORE);
1646 setTargetDAGCombine(ISD::ZERO_EXTEND);
1647 setTargetDAGCombine(ISD::ANY_EXTEND);
1648 setTargetDAGCombine(ISD::SIGN_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1650 setTargetDAGCombine(ISD::TRUNCATE);
1651 setTargetDAGCombine(ISD::SINT_TO_FP);
1652 setTargetDAGCombine(ISD::SETCC);
1653 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1654 setTargetDAGCombine(ISD::BUILD_VECTOR);
1655 if (Subtarget->is64Bit())
1656 setTargetDAGCombine(ISD::MUL);
1657 setTargetDAGCombine(ISD::XOR);
1659 computeRegisterProperties();
1661 // On Darwin, -Os means optimize for size without hurting performance,
1662 // do not reduce the limit.
1663 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1664 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1665 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1666 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1668 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 setPrefLoopAlignment(4); // 2^4 bytes.
1671 // Predictable cmov don't hurt on atom because it's in-order.
1672 PredictableSelectIsExpensive = !Subtarget->isAtom();
1674 setPrefFunctionAlignment(4); // 2^4 bytes.
1676 InitIntrinsicTables();
1679 // This has so far only been implemented for 64-bit MachO.
1680 bool X86TargetLowering::useLoadStackGuardNode() const {
1681 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1682 Subtarget->is64Bit();
1685 TargetLoweringBase::LegalizeTypeAction
1686 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1687 if (ExperimentalVectorWideningLegalization &&
1688 VT.getVectorNumElements() != 1 &&
1689 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1690 return TypeWidenVector;
1692 return TargetLoweringBase::getPreferredVectorAction(VT);
1695 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1697 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1699 const unsigned NumElts = VT.getVectorNumElements();
1700 const EVT EltVT = VT.getVectorElementType();
1701 if (VT.is512BitVector()) {
1702 if (Subtarget->hasAVX512())
1703 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1704 EltVT == MVT::f32 || EltVT == MVT::f64)
1706 case 8: return MVT::v8i1;
1707 case 16: return MVT::v16i1;
1709 if (Subtarget->hasBWI())
1710 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1712 case 32: return MVT::v32i1;
1713 case 64: return MVT::v64i1;
1717 if (VT.is256BitVector() || VT.is128BitVector()) {
1718 if (Subtarget->hasVLX())
1719 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1720 EltVT == MVT::f32 || EltVT == MVT::f64)
1722 case 2: return MVT::v2i1;
1723 case 4: return MVT::v4i1;
1724 case 8: return MVT::v8i1;
1726 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1727 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1729 case 8: return MVT::v8i1;
1730 case 16: return MVT::v16i1;
1731 case 32: return MVT::v32i1;
1735 return VT.changeVectorElementTypeToInteger();
1738 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1739 /// the desired ByVal argument alignment.
1740 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1743 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1744 if (VTy->getBitWidth() == 128)
1746 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1747 unsigned EltAlign = 0;
1748 getMaxByValAlign(ATy->getElementType(), EltAlign);
1749 if (EltAlign > MaxAlign)
1750 MaxAlign = EltAlign;
1751 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1752 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1753 unsigned EltAlign = 0;
1754 getMaxByValAlign(STy->getElementType(i), EltAlign);
1755 if (EltAlign > MaxAlign)
1756 MaxAlign = EltAlign;
1763 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1764 /// function arguments in the caller parameter area. For X86, aggregates
1765 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1766 /// are at 4-byte boundaries.
1767 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1768 if (Subtarget->is64Bit()) {
1769 // Max of 8 and alignment of type.
1770 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1777 if (Subtarget->hasSSE1())
1778 getMaxByValAlign(Ty, Align);
1782 /// getOptimalMemOpType - Returns the target specific optimal type for load
1783 /// and store operations as a result of memset, memcpy, and memmove
1784 /// lowering. If DstAlign is zero that means it's safe to destination
1785 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1786 /// means there isn't a need to check it against alignment requirement,
1787 /// probably because the source does not need to be loaded. If 'IsMemset' is
1788 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1789 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1790 /// source is constant so it does not need to be loaded.
1791 /// It returns EVT::Other if the type should be determined using generic
1792 /// target-independent logic.
1794 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1795 unsigned DstAlign, unsigned SrcAlign,
1796 bool IsMemset, bool ZeroMemset,
1798 MachineFunction &MF) const {
1799 const Function *F = MF.getFunction();
1800 if ((!IsMemset || ZeroMemset) &&
1801 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1802 Attribute::NoImplicitFloat)) {
1804 (Subtarget->isUnalignedMemAccessFast() ||
1805 ((DstAlign == 0 || DstAlign >= 16) &&
1806 (SrcAlign == 0 || SrcAlign >= 16)))) {
1808 if (Subtarget->hasInt256())
1810 if (Subtarget->hasFp256())
1813 if (Subtarget->hasSSE2())
1815 if (Subtarget->hasSSE1())
1817 } else if (!MemcpyStrSrc && Size >= 8 &&
1818 !Subtarget->is64Bit() &&
1819 Subtarget->hasSSE2()) {
1820 // Do not use f64 to lower memcpy if source is string constant. It's
1821 // better to use i32 to avoid the loads.
1825 if (Subtarget->is64Bit() && Size >= 8)
1830 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1832 return X86ScalarSSEf32;
1833 else if (VT == MVT::f64)
1834 return X86ScalarSSEf64;
1839 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1844 *Fast = Subtarget->isUnalignedMemAccessFast();
1848 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1849 /// current function. The returned value is a member of the
1850 /// MachineJumpTableInfo::JTEntryKind enum.
1851 unsigned X86TargetLowering::getJumpTableEncoding() const {
1852 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1854 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1855 Subtarget->isPICStyleGOT())
1856 return MachineJumpTableInfo::EK_Custom32;
1858 // Otherwise, use the normal jump table encoding heuristics.
1859 return TargetLowering::getJumpTableEncoding();
1863 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1864 const MachineBasicBlock *MBB,
1865 unsigned uid,MCContext &Ctx) const{
1866 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1867 Subtarget->isPICStyleGOT());
1868 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1870 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1871 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1874 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1876 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1877 SelectionDAG &DAG) const {
1878 if (!Subtarget->is64Bit())
1879 // This doesn't have SDLoc associated with it, but is not really the
1880 // same as a Register.
1881 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1885 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1886 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1888 const MCExpr *X86TargetLowering::
1889 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1890 MCContext &Ctx) const {
1891 // X86-64 uses RIP relative addressing based on the jump table label.
1892 if (Subtarget->isPICStyleRIPRel())
1893 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1895 // Otherwise, the reference is relative to the PIC base.
1896 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1899 // FIXME: Why this routine is here? Move to RegInfo!
1900 std::pair<const TargetRegisterClass*, uint8_t>
1901 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1902 const TargetRegisterClass *RRC = nullptr;
1904 switch (VT.SimpleTy) {
1906 return TargetLowering::findRepresentativeClass(VT);
1907 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1908 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1911 RRC = &X86::VR64RegClass;
1913 case MVT::f32: case MVT::f64:
1914 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1915 case MVT::v4f32: case MVT::v2f64:
1916 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1918 RRC = &X86::VR128RegClass;
1921 return std::make_pair(RRC, Cost);
1924 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1925 unsigned &Offset) const {
1926 if (!Subtarget->isTargetLinux())
1929 if (Subtarget->is64Bit()) {
1930 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1932 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1944 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1945 unsigned DestAS) const {
1946 assert(SrcAS != DestAS && "Expected different address spaces!");
1948 return SrcAS < 256 && DestAS < 256;
1951 //===----------------------------------------------------------------------===//
1952 // Return Value Calling Convention Implementation
1953 //===----------------------------------------------------------------------===//
1955 #include "X86GenCallingConv.inc"
1958 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1959 MachineFunction &MF, bool isVarArg,
1960 const SmallVectorImpl<ISD::OutputArg> &Outs,
1961 LLVMContext &Context) const {
1962 SmallVector<CCValAssign, 16> RVLocs;
1963 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1964 return CCInfo.CheckReturn(Outs, RetCC_X86);
1967 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1968 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1973 X86TargetLowering::LowerReturn(SDValue Chain,
1974 CallingConv::ID CallConv, bool isVarArg,
1975 const SmallVectorImpl<ISD::OutputArg> &Outs,
1976 const SmallVectorImpl<SDValue> &OutVals,
1977 SDLoc dl, SelectionDAG &DAG) const {
1978 MachineFunction &MF = DAG.getMachineFunction();
1979 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1981 SmallVector<CCValAssign, 16> RVLocs;
1982 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1983 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1986 SmallVector<SDValue, 6> RetOps;
1987 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1988 // Operand #1 = Bytes To Pop
1989 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1992 // Copy the result values into the output registers.
1993 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1994 CCValAssign &VA = RVLocs[i];
1995 assert(VA.isRegLoc() && "Can only return in registers!");
1996 SDValue ValToCopy = OutVals[i];
1997 EVT ValVT = ValToCopy.getValueType();
1999 // Promote values to the appropriate types
2000 if (VA.getLocInfo() == CCValAssign::SExt)
2001 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::ZExt)
2003 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::AExt)
2005 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::BCvt)
2007 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2009 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2010 "Unexpected FP-extend for return value.");
2012 // If this is x86-64, and we disabled SSE, we can't return FP values,
2013 // or SSE or MMX vectors.
2014 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2015 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2016 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2017 report_fatal_error("SSE register return with SSE disabled");
2019 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2020 // llvm-gcc has never done it right and no one has noticed, so this
2021 // should be OK for now.
2022 if (ValVT == MVT::f64 &&
2023 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2024 report_fatal_error("SSE2 register return with SSE2 disabled");
2026 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2027 // the RET instruction and handled by the FP Stackifier.
2028 if (VA.getLocReg() == X86::FP0 ||
2029 VA.getLocReg() == X86::FP1) {
2030 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2031 // change the value to the FP stack register class.
2032 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2033 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2034 RetOps.push_back(ValToCopy);
2035 // Don't emit a copytoreg.
2039 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2040 // which is returned in RAX / RDX.
2041 if (Subtarget->is64Bit()) {
2042 if (ValVT == MVT::x86mmx) {
2043 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2044 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2045 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2047 // If we don't have SSE2 available, convert to v4f32 so the generated
2048 // register is legal.
2049 if (!Subtarget->hasSSE2())
2050 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2055 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2056 Flag = Chain.getValue(1);
2057 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2060 // The x86-64 ABIs require that for returning structs by value we copy
2061 // the sret argument into %rax/%eax (depending on ABI) for the return.
2062 // Win32 requires us to put the sret argument to %eax as well.
2063 // We saved the argument into a virtual register in the entry block,
2064 // so now we copy the value out and into %rax/%eax.
2065 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2066 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2067 MachineFunction &MF = DAG.getMachineFunction();
2068 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2069 unsigned Reg = FuncInfo->getSRetReturnReg();
2071 "SRetReturnReg should have been set in LowerFormalArguments().");
2072 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2075 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2076 X86::RAX : X86::EAX;
2077 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2078 Flag = Chain.getValue(1);
2080 // RAX/EAX now acts like a return value.
2081 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2084 RetOps[0] = Chain; // Update chain.
2086 // Add the flag if we have it.
2088 RetOps.push_back(Flag);
2090 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2093 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2094 if (N->getNumValues() != 1)
2096 if (!N->hasNUsesOfValue(1, 0))
2099 SDValue TCChain = Chain;
2100 SDNode *Copy = *N->use_begin();
2101 if (Copy->getOpcode() == ISD::CopyToReg) {
2102 // If the copy has a glue operand, we conservatively assume it isn't safe to
2103 // perform a tail call.
2104 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2106 TCChain = Copy->getOperand(0);
2107 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2110 bool HasRet = false;
2111 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2113 if (UI->getOpcode() != X86ISD::RET_FLAG)
2115 // If we are returning more than one value, we can definitely
2116 // not make a tail call see PR19530
2117 if (UI->getNumOperands() > 4)
2119 if (UI->getNumOperands() == 4 &&
2120 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2133 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2134 ISD::NodeType ExtendKind) const {
2136 // TODO: Is this also valid on 32-bit?
2137 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2138 ReturnMVT = MVT::i8;
2140 ReturnMVT = MVT::i32;
2142 EVT MinVT = getRegisterType(Context, ReturnMVT);
2143 return VT.bitsLT(MinVT) ? MinVT : VT;
2146 /// LowerCallResult - Lower the result values of a call into the
2147 /// appropriate copies out of appropriate physical registers.
2150 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::InputArg> &Ins,
2153 SDLoc dl, SelectionDAG &DAG,
2154 SmallVectorImpl<SDValue> &InVals) const {
2156 // Assign locations to each value returned by this call.
2157 SmallVector<CCValAssign, 16> RVLocs;
2158 bool Is64Bit = Subtarget->is64Bit();
2159 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2161 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2163 // Copy all of the result registers out of their specified physreg.
2164 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2165 CCValAssign &VA = RVLocs[i];
2166 EVT CopyVT = VA.getValVT();
2168 // If this is x86-64, and we disabled SSE, we can't return FP values
2169 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2170 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2171 report_fatal_error("SSE register return with SSE disabled");
2174 // If we prefer to use the value in xmm registers, copy it out as f80 and
2175 // use a truncate to move it from fp stack reg to xmm reg.
2176 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2177 isScalarFPTypeInSSEReg(VA.getValVT()))
2180 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2181 CopyVT, InFlag).getValue(1);
2182 SDValue Val = Chain.getValue(0);
2184 if (CopyVT != VA.getValVT())
2185 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2186 // This truncation won't change the value.
2187 DAG.getIntPtrConstant(1));
2189 InFlag = Chain.getValue(2);
2190 InVals.push_back(Val);
2196 //===----------------------------------------------------------------------===//
2197 // C & StdCall & Fast Calling Convention implementation
2198 //===----------------------------------------------------------------------===//
2199 // StdCall calling convention seems to be standard for many Windows' API
2200 // routines and around. It differs from C calling convention just a little:
2201 // callee should clean up the stack, not caller. Symbols should be also
2202 // decorated in some fancy way :) It doesn't support any vector arguments.
2203 // For info on fast calling convention see Fast Calling Convention (tail call)
2204 // implementation LowerX86_32FastCCCallTo.
2206 /// CallIsStructReturn - Determines whether a call uses struct return
2208 enum StructReturnType {
2213 static StructReturnType
2214 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2216 return NotStructReturn;
2218 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2219 if (!Flags.isSRet())
2220 return NotStructReturn;
2221 if (Flags.isInReg())
2222 return RegStructReturn;
2223 return StackStructReturn;
2226 /// ArgsAreStructReturn - Determines whether a function uses struct
2227 /// return semantics.
2228 static StructReturnType
2229 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2231 return NotStructReturn;
2233 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2234 if (!Flags.isSRet())
2235 return NotStructReturn;
2236 if (Flags.isInReg())
2237 return RegStructReturn;
2238 return StackStructReturn;
2241 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2242 /// by "Src" to address "Dst" with size and alignment information specified by
2243 /// the specific parameter attribute. The copy will be passed as a byval
2244 /// function parameter.
2246 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2247 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2249 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2251 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2252 /*isVolatile*/false, /*AlwaysInline=*/true,
2253 MachinePointerInfo(), MachinePointerInfo());
2256 /// IsTailCallConvention - Return true if the calling convention is one that
2257 /// supports tail call optimization.
2258 static bool IsTailCallConvention(CallingConv::ID CC) {
2259 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2260 CC == CallingConv::HiPE);
2263 /// \brief Return true if the calling convention is a C calling convention.
2264 static bool IsCCallConvention(CallingConv::ID CC) {
2265 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2266 CC == CallingConv::X86_64_SysV);
2269 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2270 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2274 CallingConv::ID CalleeCC = CS.getCallingConv();
2275 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2281 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2282 /// a tailcall target by changing its ABI.
2283 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2284 bool GuaranteedTailCallOpt) {
2285 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2289 X86TargetLowering::LowerMemArgument(SDValue Chain,
2290 CallingConv::ID CallConv,
2291 const SmallVectorImpl<ISD::InputArg> &Ins,
2292 SDLoc dl, SelectionDAG &DAG,
2293 const CCValAssign &VA,
2294 MachineFrameInfo *MFI,
2296 // Create the nodes corresponding to a load from this parameter slot.
2297 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2298 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2299 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2300 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2303 // If value is passed by pointer we have address passed instead of the value
2305 if (VA.getLocInfo() == CCValAssign::Indirect)
2306 ValVT = VA.getLocVT();
2308 ValVT = VA.getValVT();
2310 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2311 // changed with more analysis.
2312 // In case of tail call optimization mark all arguments mutable. Since they
2313 // could be overwritten by lowering of arguments in case of a tail call.
2314 if (Flags.isByVal()) {
2315 unsigned Bytes = Flags.getByValSize();
2316 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2317 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2318 return DAG.getFrameIndex(FI, getPointerTy());
2320 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2321 VA.getLocMemOffset(), isImmutable);
2322 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2323 return DAG.getLoad(ValVT, dl, Chain, FIN,
2324 MachinePointerInfo::getFixedStack(FI),
2325 false, false, false, 0);
2329 // FIXME: Get this from tablegen.
2330 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2331 const X86Subtarget *Subtarget) {
2332 assert(Subtarget->is64Bit());
2334 if (Subtarget->isCallingConvWin64(CallConv)) {
2335 static const MCPhysReg GPR64ArgRegsWin64[] = {
2336 X86::RCX, X86::RDX, X86::R8, X86::R9
2338 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2341 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2342 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2344 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2347 // FIXME: Get this from tablegen.
2348 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2349 CallingConv::ID CallConv,
2350 const X86Subtarget *Subtarget) {
2351 assert(Subtarget->is64Bit());
2352 if (Subtarget->isCallingConvWin64(CallConv)) {
2353 // The XMM registers which might contain var arg parameters are shadowed
2354 // in their paired GPR. So we only need to save the GPR to their home
2356 // TODO: __vectorcall will change this.
2360 const Function *Fn = MF.getFunction();
2361 bool NoImplicitFloatOps = Fn->getAttributes().
2362 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2363 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2364 "SSE register cannot be used when SSE is disabled!");
2365 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2366 !Subtarget->hasSSE1())
2367 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2371 static const MCPhysReg XMMArgRegs64Bit[] = {
2372 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2373 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2375 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2379 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2380 CallingConv::ID CallConv,
2382 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SmallVectorImpl<SDValue> &InVals)
2387 MachineFunction &MF = DAG.getMachineFunction();
2388 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2390 const Function* Fn = MF.getFunction();
2391 if (Fn->hasExternalLinkage() &&
2392 Subtarget->isTargetCygMing() &&
2393 Fn->getName() == "main")
2394 FuncInfo->setForceFramePointer(true);
2396 MachineFrameInfo *MFI = MF.getFrameInfo();
2397 bool Is64Bit = Subtarget->is64Bit();
2398 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2400 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2401 "Var args not supported with calling convention fastcc, ghc or hipe");
2403 // Assign locations to all of the incoming arguments.
2404 SmallVector<CCValAssign, 16> ArgLocs;
2405 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2407 // Allocate shadow area for Win64
2409 CCInfo.AllocateStack(32, 8);
2411 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2413 unsigned LastVal = ~0U;
2415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2416 CCValAssign &VA = ArgLocs[i];
2417 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2419 assert(VA.getValNo() != LastVal &&
2420 "Don't support value assigned to multiple locs yet");
2422 LastVal = VA.getValNo();
2424 if (VA.isRegLoc()) {
2425 EVT RegVT = VA.getLocVT();
2426 const TargetRegisterClass *RC;
2427 if (RegVT == MVT::i32)
2428 RC = &X86::GR32RegClass;
2429 else if (Is64Bit && RegVT == MVT::i64)
2430 RC = &X86::GR64RegClass;
2431 else if (RegVT == MVT::f32)
2432 RC = &X86::FR32RegClass;
2433 else if (RegVT == MVT::f64)
2434 RC = &X86::FR64RegClass;
2435 else if (RegVT.is512BitVector())
2436 RC = &X86::VR512RegClass;
2437 else if (RegVT.is256BitVector())
2438 RC = &X86::VR256RegClass;
2439 else if (RegVT.is128BitVector())
2440 RC = &X86::VR128RegClass;
2441 else if (RegVT == MVT::x86mmx)
2442 RC = &X86::VR64RegClass;
2443 else if (RegVT == MVT::i1)
2444 RC = &X86::VK1RegClass;
2445 else if (RegVT == MVT::v8i1)
2446 RC = &X86::VK8RegClass;
2447 else if (RegVT == MVT::v16i1)
2448 RC = &X86::VK16RegClass;
2449 else if (RegVT == MVT::v32i1)
2450 RC = &X86::VK32RegClass;
2451 else if (RegVT == MVT::v64i1)
2452 RC = &X86::VK64RegClass;
2454 llvm_unreachable("Unknown argument type!");
2456 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2457 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2459 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2460 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2462 if (VA.getLocInfo() == CCValAssign::SExt)
2463 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2464 DAG.getValueType(VA.getValVT()));
2465 else if (VA.getLocInfo() == CCValAssign::ZExt)
2466 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2467 DAG.getValueType(VA.getValVT()));
2468 else if (VA.getLocInfo() == CCValAssign::BCvt)
2469 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2471 if (VA.isExtInLoc()) {
2472 // Handle MMX values passed in XMM regs.
2473 if (RegVT.isVector())
2474 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2476 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2479 assert(VA.isMemLoc());
2480 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2483 // If value is passed via pointer - do a load.
2484 if (VA.getLocInfo() == CCValAssign::Indirect)
2485 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2486 MachinePointerInfo(), false, false, false, 0);
2488 InVals.push_back(ArgValue);
2491 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2493 // The x86-64 ABIs require that for returning structs by value we copy
2494 // the sret argument into %rax/%eax (depending on ABI) for the return.
2495 // Win32 requires us to put the sret argument to %eax as well.
2496 // Save the argument into a virtual register so that we can access it
2497 // from the return points.
2498 if (Ins[i].Flags.isSRet()) {
2499 unsigned Reg = FuncInfo->getSRetReturnReg();
2501 MVT PtrTy = getPointerTy();
2502 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2503 FuncInfo->setSRetReturnReg(Reg);
2505 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2512 unsigned StackSize = CCInfo.getNextStackOffset();
2513 // Align stack specially for tail calls.
2514 if (FuncIsMadeTailCallSafe(CallConv,
2515 MF.getTarget().Options.GuaranteedTailCallOpt))
2516 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2518 // If the function takes variable number of arguments, make a frame index for
2519 // the start of the first vararg value... for expansion of llvm.va_start. We
2520 // can skip this if there are no va_start calls.
2521 if (MFI->hasVAStart() &&
2522 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2523 CallConv != CallingConv::X86_ThisCall))) {
2524 FuncInfo->setVarArgsFrameIndex(
2525 MFI->CreateFixedObject(1, StackSize, true));
2528 // 64-bit calling conventions support varargs and register parameters, so we
2529 // have to do extra work to spill them in the prologue or forward them to
2531 if (Is64Bit && isVarArg &&
2532 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2533 // Find the first unallocated argument registers.
2534 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2535 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2536 unsigned NumIntRegs =
2537 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2538 unsigned NumXMMRegs =
2539 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2540 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2541 "SSE register cannot be used when SSE is disabled!");
2543 // Gather all the live in physical registers.
2544 SmallVector<SDValue, 6> LiveGPRs;
2545 SmallVector<SDValue, 8> LiveXMMRegs;
2547 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2548 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2550 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2552 if (!ArgXMMs.empty()) {
2553 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2554 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2555 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2556 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2557 LiveXMMRegs.push_back(
2558 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2562 // Store them to the va_list returned by va_start.
2563 if (MFI->hasVAStart()) {
2565 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2566 // Get to the caller-allocated home save location. Add 8 to account
2567 // for the return address.
2568 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2569 FuncInfo->setRegSaveFrameIndex(
2570 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2571 // Fixup to set vararg frame on shadow area (4 x i64).
2573 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2575 // For X86-64, if there are vararg parameters that are passed via
2576 // registers, then we must store them to their spots on the stack so
2577 // they may be loaded by deferencing the result of va_next.
2578 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2579 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2580 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2581 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2584 // Store the integer parameter registers.
2585 SmallVector<SDValue, 8> MemOps;
2586 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2588 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2589 for (SDValue Val : LiveGPRs) {
2590 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2591 DAG.getIntPtrConstant(Offset));
2593 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2594 MachinePointerInfo::getFixedStack(
2595 FuncInfo->getRegSaveFrameIndex(), Offset),
2597 MemOps.push_back(Store);
2601 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2602 // Now store the XMM (fp + vector) parameter registers.
2603 SmallVector<SDValue, 12> SaveXMMOps;
2604 SaveXMMOps.push_back(Chain);
2605 SaveXMMOps.push_back(ALVal);
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getRegSaveFrameIndex()));
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getVarArgsFPOffset()));
2610 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2612 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2613 MVT::Other, SaveXMMOps));
2616 if (!MemOps.empty())
2617 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2619 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2620 // to the liveout set on a musttail call.
2621 assert(MFI->hasMustTailInVarArgFunc());
2622 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2623 typedef X86MachineFunctionInfo::Forward Forward;
2625 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2627 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2628 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2629 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2632 if (!ArgXMMs.empty()) {
2634 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2635 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2636 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2638 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2640 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2643 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2649 // Some CCs need callee pop.
2650 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2651 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2652 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2654 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2655 // If this is an sret function, the return should pop the hidden pointer.
2656 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2657 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2658 argsAreStructReturn(Ins) == StackStructReturn)
2659 FuncInfo->setBytesToPopOnReturn(4);
2663 // RegSaveFrameIndex is X86-64 only.
2664 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2665 if (CallConv == CallingConv::X86_FastCall ||
2666 CallConv == CallingConv::X86_ThisCall)
2667 // fastcc functions can't have varargs.
2668 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2671 FuncInfo->setArgumentStackSize(StackSize);
2677 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2678 SDValue StackPtr, SDValue Arg,
2679 SDLoc dl, SelectionDAG &DAG,
2680 const CCValAssign &VA,
2681 ISD::ArgFlagsTy Flags) const {
2682 unsigned LocMemOffset = VA.getLocMemOffset();
2683 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2684 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2685 if (Flags.isByVal())
2686 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2688 return DAG.getStore(Chain, dl, Arg, PtrOff,
2689 MachinePointerInfo::getStack(LocMemOffset),
2693 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2694 /// optimization is performed and it is required.
2696 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2697 SDValue &OutRetAddr, SDValue Chain,
2698 bool IsTailCall, bool Is64Bit,
2699 int FPDiff, SDLoc dl) const {
2700 // Adjust the Return address stack slot.
2701 EVT VT = getPointerTy();
2702 OutRetAddr = getReturnAddressFrameIndex(DAG);
2704 // Load the "old" Return address.
2705 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2706 false, false, false, 0);
2707 return SDValue(OutRetAddr.getNode(), 1);
2710 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2711 /// optimization is performed and it is required (FPDiff!=0).
2712 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2713 SDValue Chain, SDValue RetAddrFrIdx,
2714 EVT PtrVT, unsigned SlotSize,
2715 int FPDiff, SDLoc dl) {
2716 // Store the return address to the appropriate stack slot.
2717 if (!FPDiff) return Chain;
2718 // Calculate the new stack slot for the return address.
2719 int NewReturnAddrFI =
2720 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2722 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2723 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2724 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2730 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2731 SmallVectorImpl<SDValue> &InVals) const {
2732 SelectionDAG &DAG = CLI.DAG;
2734 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2735 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2736 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2737 SDValue Chain = CLI.Chain;
2738 SDValue Callee = CLI.Callee;
2739 CallingConv::ID CallConv = CLI.CallConv;
2740 bool &isTailCall = CLI.IsTailCall;
2741 bool isVarArg = CLI.IsVarArg;
2743 MachineFunction &MF = DAG.getMachineFunction();
2744 bool Is64Bit = Subtarget->is64Bit();
2745 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2746 StructReturnType SR = callIsStructReturn(Outs);
2747 bool IsSibcall = false;
2748 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2750 if (MF.getTarget().Options.DisableTailCalls)
2753 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2755 // Force this to be a tail call. The verifier rules are enough to ensure
2756 // that we can lower this successfully without moving the return address
2759 } else if (isTailCall) {
2760 // Check if it's really possible to do a tail call.
2761 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2762 isVarArg, SR != NotStructReturn,
2763 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2764 Outs, OutVals, Ins, DAG);
2766 // Sibcalls are automatically detected tailcalls which do not require
2768 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2775 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2776 "Var args not supported with calling convention fastcc, ghc or hipe");
2778 // Analyze operands of the call, assigning locations to each operand.
2779 SmallVector<CCValAssign, 16> ArgLocs;
2780 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2782 // Allocate shadow area for Win64
2784 CCInfo.AllocateStack(32, 8);
2786 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2788 // Get a count of how many bytes are to be pushed on the stack.
2789 unsigned NumBytes = CCInfo.getNextStackOffset();
2791 // This is a sibcall. The memory operands are available in caller's
2792 // own caller's stack.
2794 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2795 IsTailCallConvention(CallConv))
2796 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2799 if (isTailCall && !IsSibcall && !IsMustTail) {
2800 // Lower arguments at fp - stackoffset + fpdiff.
2801 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2803 FPDiff = NumBytesCallerPushed - NumBytes;
2805 // Set the delta of movement of the returnaddr stackslot.
2806 // But only set if delta is greater than previous delta.
2807 if (FPDiff < X86Info->getTCReturnAddrDelta())
2808 X86Info->setTCReturnAddrDelta(FPDiff);
2811 unsigned NumBytesToPush = NumBytes;
2812 unsigned NumBytesToPop = NumBytes;
2814 // If we have an inalloca argument, all stack space has already been allocated
2815 // for us and be right at the top of the stack. We don't support multiple
2816 // arguments passed in memory when using inalloca.
2817 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2819 if (!ArgLocs.back().isMemLoc())
2820 report_fatal_error("cannot use inalloca attribute on a register "
2822 if (ArgLocs.back().getLocMemOffset() != 0)
2823 report_fatal_error("any parameter with the inalloca attribute must be "
2824 "the only memory argument");
2828 Chain = DAG.getCALLSEQ_START(
2829 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2831 SDValue RetAddrFrIdx;
2832 // Load return address for tail calls.
2833 if (isTailCall && FPDiff)
2834 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2835 Is64Bit, FPDiff, dl);
2837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2838 SmallVector<SDValue, 8> MemOpChains;
2841 // Walk the register/memloc assignments, inserting copies/loads. In the case
2842 // of tail call optimization arguments are handle later.
2843 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2844 DAG.getSubtarget().getRegisterInfo());
2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2846 // Skip inalloca arguments, they have already been written.
2847 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2848 if (Flags.isInAlloca())
2851 CCValAssign &VA = ArgLocs[i];
2852 EVT RegVT = VA.getLocVT();
2853 SDValue Arg = OutVals[i];
2854 bool isByVal = Flags.isByVal();
2856 // Promote the value if needed.
2857 switch (VA.getLocInfo()) {
2858 default: llvm_unreachable("Unknown loc info!");
2859 case CCValAssign::Full: break;
2860 case CCValAssign::SExt:
2861 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2863 case CCValAssign::ZExt:
2864 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2866 case CCValAssign::AExt:
2867 if (RegVT.is128BitVector()) {
2868 // Special case: passing MMX values in XMM registers.
2869 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2870 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2871 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2873 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2875 case CCValAssign::BCvt:
2876 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2878 case CCValAssign::Indirect: {
2879 // Store the argument.
2880 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2881 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2882 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2883 MachinePointerInfo::getFixedStack(FI),
2890 if (VA.isRegLoc()) {
2891 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2892 if (isVarArg && IsWin64) {
2893 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2894 // shadow reg if callee is a varargs function.
2895 unsigned ShadowReg = 0;
2896 switch (VA.getLocReg()) {
2897 case X86::XMM0: ShadowReg = X86::RCX; break;
2898 case X86::XMM1: ShadowReg = X86::RDX; break;
2899 case X86::XMM2: ShadowReg = X86::R8; break;
2900 case X86::XMM3: ShadowReg = X86::R9; break;
2903 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2905 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2906 assert(VA.isMemLoc());
2907 if (!StackPtr.getNode())
2908 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2910 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2911 dl, DAG, VA, Flags));
2915 if (!MemOpChains.empty())
2916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2918 if (Subtarget->isPICStyleGOT()) {
2919 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2922 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2923 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2925 // If we are tail calling and generating PIC/GOT style code load the
2926 // address of the callee into ECX. The value in ecx is used as target of
2927 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2928 // for tail calls on PIC/GOT architectures. Normally we would just put the
2929 // address of GOT into ebx and then call target@PLT. But for tail calls
2930 // ebx would be restored (since ebx is callee saved) before jumping to the
2933 // Note: The actual moving to ECX is done further down.
2934 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2935 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2936 !G->getGlobal()->hasProtectedVisibility())
2937 Callee = LowerGlobalAddress(Callee, DAG);
2938 else if (isa<ExternalSymbolSDNode>(Callee))
2939 Callee = LowerExternalSymbol(Callee, DAG);
2943 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2944 // From AMD64 ABI document:
2945 // For calls that may call functions that use varargs or stdargs
2946 // (prototype-less calls or calls to functions containing ellipsis (...) in
2947 // the declaration) %al is used as hidden argument to specify the number
2948 // of SSE registers used. The contents of %al do not need to match exactly
2949 // the number of registers, but must be an ubound on the number of SSE
2950 // registers used and is in the range 0 - 8 inclusive.
2952 // Count the number of XMM registers allocated.
2953 static const MCPhysReg XMMArgRegs[] = {
2954 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2955 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2957 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2958 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2959 && "SSE registers cannot be used when SSE is disabled");
2961 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2962 DAG.getConstant(NumXMMRegs, MVT::i8)));
2965 if (Is64Bit && isVarArg && IsMustTail) {
2966 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2967 for (const auto &F : Forwards) {
2968 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2969 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2973 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2974 // don't need this because the eligibility check rejects calls that require
2975 // shuffling arguments passed in memory.
2976 if (!IsSibcall && isTailCall) {
2977 // Force all the incoming stack arguments to be loaded from the stack
2978 // before any new outgoing arguments are stored to the stack, because the
2979 // outgoing stack slots may alias the incoming argument stack slots, and
2980 // the alias isn't otherwise explicit. This is slightly more conservative
2981 // than necessary, because it means that each store effectively depends
2982 // on every argument instead of just those arguments it would clobber.
2983 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2985 SmallVector<SDValue, 8> MemOpChains2;
2988 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2989 CCValAssign &VA = ArgLocs[i];
2992 assert(VA.isMemLoc());
2993 SDValue Arg = OutVals[i];
2994 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2995 // Skip inalloca arguments. They don't require any work.
2996 if (Flags.isInAlloca())
2998 // Create frame index.
2999 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3000 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3001 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3002 FIN = DAG.getFrameIndex(FI, getPointerTy());
3004 if (Flags.isByVal()) {
3005 // Copy relative to framepointer.
3006 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3007 if (!StackPtr.getNode())
3008 StackPtr = DAG.getCopyFromReg(Chain, dl,
3009 RegInfo->getStackRegister(),
3011 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3013 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3017 // Store relative to framepointer.
3018 MemOpChains2.push_back(
3019 DAG.getStore(ArgChain, dl, Arg, FIN,
3020 MachinePointerInfo::getFixedStack(FI),
3025 if (!MemOpChains2.empty())
3026 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3028 // Store the return address to the appropriate stack slot.
3029 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3030 getPointerTy(), RegInfo->getSlotSize(),
3034 // Build a sequence of copy-to-reg nodes chained together with token chain
3035 // and flag operands which copy the outgoing args into registers.
3037 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3038 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3039 RegsToPass[i].second, InFlag);
3040 InFlag = Chain.getValue(1);
3043 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3044 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3045 // In the 64-bit large code model, we have to make all calls
3046 // through a register, since the call instruction's 32-bit
3047 // pc-relative offset may not be large enough to hold the whole
3049 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3050 // If the callee is a GlobalAddress node (quite common, every direct call
3051 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3054 // We should use extra load for direct calls to dllimported functions in
3056 const GlobalValue *GV = G->getGlobal();
3057 if (!GV->hasDLLImportStorageClass()) {
3058 unsigned char OpFlags = 0;
3059 bool ExtraLoad = false;
3060 unsigned WrapperKind = ISD::DELETED_NODE;
3062 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3063 // external symbols most go through the PLT in PIC mode. If the symbol
3064 // has hidden or protected visibility, or if it is static or local, then
3065 // we don't need to use the PLT - we can directly call it.
3066 if (Subtarget->isTargetELF() &&
3067 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3068 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3069 OpFlags = X86II::MO_PLT;
3070 } else if (Subtarget->isPICStyleStubAny() &&
3071 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3072 (!Subtarget->getTargetTriple().isMacOSX() ||
3073 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3074 // PC-relative references to external symbols should go through $stub,
3075 // unless we're building with the leopard linker or later, which
3076 // automatically synthesizes these stubs.
3077 OpFlags = X86II::MO_DARWIN_STUB;
3078 } else if (Subtarget->isPICStyleRIPRel() &&
3079 isa<Function>(GV) &&
3080 cast<Function>(GV)->getAttributes().
3081 hasAttribute(AttributeSet::FunctionIndex,
3082 Attribute::NonLazyBind)) {
3083 // If the function is marked as non-lazy, generate an indirect call
3084 // which loads from the GOT directly. This avoids runtime overhead
3085 // at the cost of eager binding (and one extra byte of encoding).
3086 OpFlags = X86II::MO_GOTPCREL;
3087 WrapperKind = X86ISD::WrapperRIP;
3091 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3092 G->getOffset(), OpFlags);
3094 // Add a wrapper if needed.
3095 if (WrapperKind != ISD::DELETED_NODE)
3096 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3097 // Add extra indirection if needed.
3099 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3100 MachinePointerInfo::getGOT(),
3101 false, false, false, 0);
3103 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3104 unsigned char OpFlags = 0;
3106 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3107 // external symbols should go through the PLT.
3108 if (Subtarget->isTargetELF() &&
3109 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3110 OpFlags = X86II::MO_PLT;
3111 } else if (Subtarget->isPICStyleStubAny() &&
3112 (!Subtarget->getTargetTriple().isMacOSX() ||
3113 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3114 // PC-relative references to external symbols should go through $stub,
3115 // unless we're building with the leopard linker or later, which
3116 // automatically synthesizes these stubs.
3117 OpFlags = X86II::MO_DARWIN_STUB;
3120 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 // Returns a chain & a flag for retval copy to use.
3125 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3126 SmallVector<SDValue, 8> Ops;
3128 if (!IsSibcall && isTailCall) {
3129 Chain = DAG.getCALLSEQ_END(Chain,
3130 DAG.getIntPtrConstant(NumBytesToPop, true),
3131 DAG.getIntPtrConstant(0, true), InFlag, dl);
3132 InFlag = Chain.getValue(1);
3135 Ops.push_back(Chain);
3136 Ops.push_back(Callee);
3139 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3141 // Add argument registers to the end of the list so that they are known live
3143 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3144 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3145 RegsToPass[i].second.getValueType()));
3147 // Add a register mask operand representing the call-preserved registers.
3148 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3149 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3150 assert(Mask && "Missing call preserved mask for calling convention");
3151 Ops.push_back(DAG.getRegisterMask(Mask));
3153 if (InFlag.getNode())
3154 Ops.push_back(InFlag);
3158 //// If this is the first return lowered for this function, add the regs
3159 //// to the liveout set for the function.
3160 // This isn't right, although it's probably harmless on x86; liveouts
3161 // should be computed from returns not tail calls. Consider a void
3162 // function making a tail call to a function returning int.
3163 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3166 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3167 InFlag = Chain.getValue(1);
3169 // Create the CALLSEQ_END node.
3170 unsigned NumBytesForCalleeToPop;
3171 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3172 DAG.getTarget().Options.GuaranteedTailCallOpt))
3173 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3174 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3175 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3176 SR == StackStructReturn)
3177 // If this is a call to a struct-return function, the callee
3178 // pops the hidden struct pointer, so we have to push it back.
3179 // This is common for Darwin/X86, Linux & Mingw32 targets.
3180 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3181 NumBytesForCalleeToPop = 4;
3183 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3185 // Returns a flag for retval copy to use.
3187 Chain = DAG.getCALLSEQ_END(Chain,
3188 DAG.getIntPtrConstant(NumBytesToPop, true),
3189 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3192 InFlag = Chain.getValue(1);
3195 // Handle result values, copying them out of physregs into vregs that we
3197 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3198 Ins, dl, DAG, InVals);
3201 //===----------------------------------------------------------------------===//
3202 // Fast Calling Convention (tail call) implementation
3203 //===----------------------------------------------------------------------===//
3205 // Like std call, callee cleans arguments, convention except that ECX is
3206 // reserved for storing the tail called function address. Only 2 registers are
3207 // free for argument passing (inreg). Tail call optimization is performed
3209 // * tailcallopt is enabled
3210 // * caller/callee are fastcc
3211 // On X86_64 architecture with GOT-style position independent code only local
3212 // (within module) calls are supported at the moment.
3213 // To keep the stack aligned according to platform abi the function
3214 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3215 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3216 // If a tail called function callee has more arguments than the caller the
3217 // caller needs to make sure that there is room to move the RETADDR to. This is
3218 // achieved by reserving an area the size of the argument delta right after the
3219 // original RETADDR, but before the saved framepointer or the spilled registers
3220 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3232 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3233 /// for a 16 byte align requirement.
3235 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3236 SelectionDAG& DAG) const {
3237 MachineFunction &MF = DAG.getMachineFunction();
3238 const TargetMachine &TM = MF.getTarget();
3239 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3240 TM.getSubtargetImpl()->getRegisterInfo());
3241 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3242 unsigned StackAlignment = TFI.getStackAlignment();
3243 uint64_t AlignMask = StackAlignment - 1;
3244 int64_t Offset = StackSize;
3245 unsigned SlotSize = RegInfo->getSlotSize();
3246 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3247 // Number smaller than 12 so just add the difference.
3248 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3250 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3251 Offset = ((~AlignMask) & Offset) + StackAlignment +
3252 (StackAlignment-SlotSize);
3257 /// MatchingStackOffset - Return true if the given stack call argument is
3258 /// already available in the same position (relatively) of the caller's
3259 /// incoming argument stack.
3261 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3262 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3263 const X86InstrInfo *TII) {
3264 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3266 if (Arg.getOpcode() == ISD::CopyFromReg) {
3267 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3268 if (!TargetRegisterInfo::isVirtualRegister(VR))
3270 MachineInstr *Def = MRI->getVRegDef(VR);
3273 if (!Flags.isByVal()) {
3274 if (!TII->isLoadFromStackSlot(Def, FI))
3277 unsigned Opcode = Def->getOpcode();
3278 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3279 Def->getOperand(1).isFI()) {
3280 FI = Def->getOperand(1).getIndex();
3281 Bytes = Flags.getByValSize();
3285 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3286 if (Flags.isByVal())
3287 // ByVal argument is passed in as a pointer but it's now being
3288 // dereferenced. e.g.
3289 // define @foo(%struct.X* %A) {
3290 // tail call @bar(%struct.X* byval %A)
3293 SDValue Ptr = Ld->getBasePtr();
3294 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3297 FI = FINode->getIndex();
3298 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3299 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3300 FI = FINode->getIndex();
3301 Bytes = Flags.getByValSize();
3305 assert(FI != INT_MAX);
3306 if (!MFI->isFixedObjectIndex(FI))
3308 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3311 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3312 /// for tail call optimization. Targets which want to do tail call
3313 /// optimization should implement this function.
3315 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3316 CallingConv::ID CalleeCC,
3318 bool isCalleeStructRet,
3319 bool isCallerStructRet,
3321 const SmallVectorImpl<ISD::OutputArg> &Outs,
3322 const SmallVectorImpl<SDValue> &OutVals,
3323 const SmallVectorImpl<ISD::InputArg> &Ins,
3324 SelectionDAG &DAG) const {
3325 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3328 // If -tailcallopt is specified, make fastcc functions tail-callable.
3329 const MachineFunction &MF = DAG.getMachineFunction();
3330 const Function *CallerF = MF.getFunction();
3332 // If the function return type is x86_fp80 and the callee return type is not,
3333 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3334 // perform a tailcall optimization here.
3335 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3338 CallingConv::ID CallerCC = CallerF->getCallingConv();
3339 bool CCMatch = CallerCC == CalleeCC;
3340 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3341 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3343 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3344 if (IsTailCallConvention(CalleeCC) && CCMatch)
3349 // Look for obvious safe cases to perform tail call optimization that do not
3350 // require ABI changes. This is what gcc calls sibcall.
3352 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3353 // emit a special epilogue.
3354 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3355 DAG.getSubtarget().getRegisterInfo());
3356 if (RegInfo->needsStackRealignment(MF))
3359 // Also avoid sibcall optimization if either caller or callee uses struct
3360 // return semantics.
3361 if (isCalleeStructRet || isCallerStructRet)
3364 // An stdcall/thiscall caller is expected to clean up its arguments; the
3365 // callee isn't going to do that.
3366 // FIXME: this is more restrictive than needed. We could produce a tailcall
3367 // when the stack adjustment matches. For example, with a thiscall that takes
3368 // only one argument.
3369 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3370 CallerCC == CallingConv::X86_ThisCall))
3373 // Do not sibcall optimize vararg calls unless all arguments are passed via
3375 if (isVarArg && !Outs.empty()) {
3377 // Optimizing for varargs on Win64 is unlikely to be safe without
3378 // additional testing.
3379 if (IsCalleeWin64 || IsCallerWin64)
3382 SmallVector<CCValAssign, 16> ArgLocs;
3383 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3386 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3387 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3388 if (!ArgLocs[i].isRegLoc())
3392 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3393 // stack. Therefore, if it's not used by the call it is not safe to optimize
3394 // this into a sibcall.
3395 bool Unused = false;
3396 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3403 SmallVector<CCValAssign, 16> RVLocs;
3404 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3406 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3407 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3408 CCValAssign &VA = RVLocs[i];
3409 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3414 // If the calling conventions do not match, then we'd better make sure the
3415 // results are returned in the same way as what the caller expects.
3417 SmallVector<CCValAssign, 16> RVLocs1;
3418 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3420 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3422 SmallVector<CCValAssign, 16> RVLocs2;
3423 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3425 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3427 if (RVLocs1.size() != RVLocs2.size())
3429 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3430 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3432 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3434 if (RVLocs1[i].isRegLoc()) {
3435 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3438 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3444 // If the callee takes no arguments then go on to check the results of the
3446 if (!Outs.empty()) {
3447 // Check if stack adjustment is needed. For now, do not do this if any
3448 // argument is passed on the stack.
3449 SmallVector<CCValAssign, 16> ArgLocs;
3450 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3453 // Allocate shadow area for Win64
3455 CCInfo.AllocateStack(32, 8);
3457 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3458 if (CCInfo.getNextStackOffset()) {
3459 MachineFunction &MF = DAG.getMachineFunction();
3460 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3463 // Check if the arguments are already laid out in the right way as
3464 // the caller's fixed stack objects.
3465 MachineFrameInfo *MFI = MF.getFrameInfo();
3466 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3467 const X86InstrInfo *TII =
3468 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3470 CCValAssign &VA = ArgLocs[i];
3471 SDValue Arg = OutVals[i];
3472 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3473 if (VA.getLocInfo() == CCValAssign::Indirect)
3475 if (!VA.isRegLoc()) {
3476 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3483 // If the tailcall address may be in a register, then make sure it's
3484 // possible to register allocate for it. In 32-bit, the call address can
3485 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3486 // callee-saved registers are restored. These happen to be the same
3487 // registers used to pass 'inreg' arguments so watch out for those.
3488 if (!Subtarget->is64Bit() &&
3489 ((!isa<GlobalAddressSDNode>(Callee) &&
3490 !isa<ExternalSymbolSDNode>(Callee)) ||
3491 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3492 unsigned NumInRegs = 0;
3493 // In PIC we need an extra register to formulate the address computation
3495 unsigned MaxInRegs =
3496 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3499 CCValAssign &VA = ArgLocs[i];
3502 unsigned Reg = VA.getLocReg();
3505 case X86::EAX: case X86::EDX: case X86::ECX:
3506 if (++NumInRegs == MaxInRegs)
3518 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3519 const TargetLibraryInfo *libInfo) const {
3520 return X86::createFastISel(funcInfo, libInfo);
3523 //===----------------------------------------------------------------------===//
3524 // Other Lowering Hooks
3525 //===----------------------------------------------------------------------===//
3527 static bool MayFoldLoad(SDValue Op) {
3528 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3531 static bool MayFoldIntoStore(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3535 static bool isTargetShuffle(unsigned Opcode) {
3537 default: return false;
3538 case X86ISD::PSHUFB:
3539 case X86ISD::PSHUFD:
3540 case X86ISD::PSHUFHW:
3541 case X86ISD::PSHUFLW:
3543 case X86ISD::PALIGNR:
3544 case X86ISD::MOVLHPS:
3545 case X86ISD::MOVLHPD:
3546 case X86ISD::MOVHLPS:
3547 case X86ISD::MOVLPS:
3548 case X86ISD::MOVLPD:
3549 case X86ISD::MOVSHDUP:
3550 case X86ISD::MOVSLDUP:
3551 case X86ISD::MOVDDUP:
3554 case X86ISD::UNPCKL:
3555 case X86ISD::UNPCKH:
3556 case X86ISD::VPERMILP:
3557 case X86ISD::VPERM2X128:
3558 case X86ISD::VPERMI:
3563 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3564 SDValue V1, SelectionDAG &DAG) {
3566 default: llvm_unreachable("Unknown x86 shuffle node");
3567 case X86ISD::MOVSHDUP:
3568 case X86ISD::MOVSLDUP:
3569 case X86ISD::MOVDDUP:
3570 return DAG.getNode(Opc, dl, VT, V1);
3574 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3575 SDValue V1, unsigned TargetMask,
3576 SelectionDAG &DAG) {
3578 default: llvm_unreachable("Unknown x86 shuffle node");
3579 case X86ISD::PSHUFD:
3580 case X86ISD::PSHUFHW:
3581 case X86ISD::PSHUFLW:
3582 case X86ISD::VPERMILP:
3583 case X86ISD::VPERMI:
3584 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3588 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3589 SDValue V1, SDValue V2, unsigned TargetMask,
3590 SelectionDAG &DAG) {
3592 default: llvm_unreachable("Unknown x86 shuffle node");
3593 case X86ISD::PALIGNR:
3594 case X86ISD::VALIGN:
3596 case X86ISD::VPERM2X128:
3597 return DAG.getNode(Opc, dl, VT, V1, V2,
3598 DAG.getConstant(TargetMask, MVT::i8));
3602 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3603 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::MOVLHPS:
3607 case X86ISD::MOVLHPD:
3608 case X86ISD::MOVHLPS:
3609 case X86ISD::MOVLPS:
3610 case X86ISD::MOVLPD:
3613 case X86ISD::UNPCKL:
3614 case X86ISD::UNPCKH:
3615 return DAG.getNode(Opc, dl, VT, V1, V2);
3619 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3620 MachineFunction &MF = DAG.getMachineFunction();
3621 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3622 DAG.getSubtarget().getRegisterInfo());
3623 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3624 int ReturnAddrIndex = FuncInfo->getRAIndex();
3626 if (ReturnAddrIndex == 0) {
3627 // Set up a frame object for the return address.
3628 unsigned SlotSize = RegInfo->getSlotSize();
3629 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3632 FuncInfo->setRAIndex(ReturnAddrIndex);
3635 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3638 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3639 bool hasSymbolicDisplacement) {
3640 // Offset should fit into 32 bit immediate field.
3641 if (!isInt<32>(Offset))
3644 // If we don't have a symbolic displacement - we don't have any extra
3646 if (!hasSymbolicDisplacement)
3649 // FIXME: Some tweaks might be needed for medium code model.
3650 if (M != CodeModel::Small && M != CodeModel::Kernel)
3653 // For small code model we assume that latest object is 16MB before end of 31
3654 // bits boundary. We may also accept pretty large negative constants knowing
3655 // that all objects are in the positive half of address space.
3656 if (M == CodeModel::Small && Offset < 16*1024*1024)
3659 // For kernel code model we know that all object resist in the negative half
3660 // of 32bits address space. We may not accept negative offsets, since they may
3661 // be just off and we may accept pretty large positive ones.
3662 if (M == CodeModel::Kernel && Offset > 0)
3668 /// isCalleePop - Determines whether the callee is required to pop its
3669 /// own arguments. Callee pop is necessary to support tail calls.
3670 bool X86::isCalleePop(CallingConv::ID CallingConv,
3671 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3672 switch (CallingConv) {
3675 case CallingConv::X86_StdCall:
3676 case CallingConv::X86_FastCall:
3677 case CallingConv::X86_ThisCall:
3679 case CallingConv::Fast:
3680 case CallingConv::GHC:
3681 case CallingConv::HiPE:
3688 /// \brief Return true if the condition is an unsigned comparison operation.
3689 static bool isX86CCUnsigned(unsigned X86CC) {
3691 default: llvm_unreachable("Invalid integer condition!");
3692 case X86::COND_E: return true;
3693 case X86::COND_G: return false;
3694 case X86::COND_GE: return false;
3695 case X86::COND_L: return false;
3696 case X86::COND_LE: return false;
3697 case X86::COND_NE: return true;
3698 case X86::COND_B: return true;
3699 case X86::COND_A: return true;
3700 case X86::COND_BE: return true;
3701 case X86::COND_AE: return true;
3703 llvm_unreachable("covered switch fell through?!");
3706 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3707 /// specific condition code, returning the condition code and the LHS/RHS of the
3708 /// comparison to make.
3709 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3710 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3713 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3714 // X > -1 -> X == 0, jump !sign.
3715 RHS = DAG.getConstant(0, RHS.getValueType());
3716 return X86::COND_NS;
3718 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3719 // X < 0 -> X == 0, jump on sign.
3722 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3724 RHS = DAG.getConstant(0, RHS.getValueType());
3725 return X86::COND_LE;
3729 switch (SetCCOpcode) {
3730 default: llvm_unreachable("Invalid integer condition!");
3731 case ISD::SETEQ: return X86::COND_E;
3732 case ISD::SETGT: return X86::COND_G;
3733 case ISD::SETGE: return X86::COND_GE;
3734 case ISD::SETLT: return X86::COND_L;
3735 case ISD::SETLE: return X86::COND_LE;
3736 case ISD::SETNE: return X86::COND_NE;
3737 case ISD::SETULT: return X86::COND_B;
3738 case ISD::SETUGT: return X86::COND_A;
3739 case ISD::SETULE: return X86::COND_BE;
3740 case ISD::SETUGE: return X86::COND_AE;
3744 // First determine if it is required or is profitable to flip the operands.
3746 // If LHS is a foldable load, but RHS is not, flip the condition.
3747 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3748 !ISD::isNON_EXTLoad(RHS.getNode())) {
3749 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3750 std::swap(LHS, RHS);
3753 switch (SetCCOpcode) {
3759 std::swap(LHS, RHS);
3763 // On a floating point condition, the flags are set as follows:
3765 // 0 | 0 | 0 | X > Y
3766 // 0 | 0 | 1 | X < Y
3767 // 1 | 0 | 0 | X == Y
3768 // 1 | 1 | 1 | unordered
3769 switch (SetCCOpcode) {
3770 default: llvm_unreachable("Condcode should be pre-legalized away");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETOLT: // flipped
3775 case ISD::SETGT: return X86::COND_A;
3776 case ISD::SETOLE: // flipped
3778 case ISD::SETGE: return X86::COND_AE;
3779 case ISD::SETUGT: // flipped
3781 case ISD::SETLT: return X86::COND_B;
3782 case ISD::SETUGE: // flipped
3784 case ISD::SETLE: return X86::COND_BE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETUO: return X86::COND_P;
3788 case ISD::SETO: return X86::COND_NP;
3790 case ISD::SETUNE: return X86::COND_INVALID;
3794 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3795 /// code. Current x86 isa includes the following FP cmov instructions:
3796 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3797 static bool hasFPCMov(unsigned X86CC) {
3813 /// isFPImmLegal - Returns true if the target can instruction select the
3814 /// specified FP immediate natively. If false, the legalizer will
3815 /// materialize the FP immediate as a load from a constant pool.
3816 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3817 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3818 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 /// \brief Returns true if it is beneficial to convert a load of a constant
3825 /// to just the constant itself.
3826 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3828 assert(Ty->isIntegerTy());
3830 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3831 if (BitSize == 0 || BitSize > 64)
3836 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3837 /// the specified range (L, H].
3838 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3839 return (Val < 0) || (Val >= Low && Val < Hi);
3842 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3843 /// specified value.
3844 static bool isUndefOrEqual(int Val, int CmpVal) {
3845 return (Val < 0 || Val == CmpVal);
3848 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3849 /// from position Pos and ending in Pos+Size, falls within the specified
3850 /// sequential range (L, L+Pos]. or is undef.
3851 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3852 unsigned Pos, unsigned Size, int Low) {
3853 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3854 if (!isUndefOrEqual(Mask[i], Low))
3859 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3860 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3861 /// the second operand.
3862 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3863 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3864 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3865 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3866 return (Mask[0] < 2 && Mask[1] < 2);
3870 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3871 /// is suitable for input to PSHUFHW.
3872 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3873 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3876 // Lower quadword copied in order or undef.
3877 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3880 // Upper quadword shuffled.
3881 for (unsigned i = 4; i != 8; ++i)
3882 if (!isUndefOrInRange(Mask[i], 4, 8))
3885 if (VT == MVT::v16i16) {
3886 // Lower quadword copied in order or undef.
3887 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3890 // Upper quadword shuffled.
3891 for (unsigned i = 12; i != 16; ++i)
3892 if (!isUndefOrInRange(Mask[i], 12, 16))
3899 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3900 /// is suitable for input to PSHUFLW.
3901 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3902 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3905 // Upper quadword copied in order.
3906 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3909 // Lower quadword shuffled.
3910 for (unsigned i = 0; i != 4; ++i)
3911 if (!isUndefOrInRange(Mask[i], 0, 4))
3914 if (VT == MVT::v16i16) {
3915 // Upper quadword copied in order.
3916 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3919 // Lower quadword shuffled.
3920 for (unsigned i = 8; i != 12; ++i)
3921 if (!isUndefOrInRange(Mask[i], 8, 12))
3928 /// \brief Return true if the mask specifies a shuffle of elements that is
3929 /// suitable for input to intralane (palignr) or interlane (valign) vector
3931 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3932 unsigned NumElts = VT.getVectorNumElements();
3933 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3934 unsigned NumLaneElts = NumElts/NumLanes;
3936 // Do not handle 64-bit element shuffles with palignr.
3937 if (NumLaneElts == 2)
3940 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3942 for (i = 0; i != NumLaneElts; ++i) {
3947 // Lane is all undef, go to next lane
3948 if (i == NumLaneElts)
3951 int Start = Mask[i+l];
3953 // Make sure its in this lane in one of the sources
3954 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3955 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3958 // If not lane 0, then we must match lane 0
3959 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3962 // Correct second source to be contiguous with first source
3963 if (Start >= (int)NumElts)
3964 Start -= NumElts - NumLaneElts;
3966 // Make sure we're shifting in the right direction.
3967 if (Start <= (int)(i+l))
3972 // Check the rest of the elements to see if they are consecutive.
3973 for (++i; i != NumLaneElts; ++i) {
3974 int Idx = Mask[i+l];
3976 // Make sure its in this lane
3977 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3978 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3981 // If not lane 0, then we must match lane 0
3982 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3985 if (Idx >= (int)NumElts)
3986 Idx -= NumElts - NumLaneElts;
3988 if (!isUndefOrEqual(Idx, Start+i))
3997 /// \brief Return true if the node specifies a shuffle of elements that is
3998 /// suitable for input to PALIGNR.
3999 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4000 const X86Subtarget *Subtarget) {
4001 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4002 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4003 VT.is512BitVector())
4004 // FIXME: Add AVX512BW.
4007 return isAlignrMask(Mask, VT, false);
4010 /// \brief Return true if the node specifies a shuffle of elements that is
4011 /// suitable for input to VALIGN.
4012 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4013 const X86Subtarget *Subtarget) {
4014 // FIXME: Add AVX512VL.
4015 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4017 return isAlignrMask(Mask, VT, true);
4020 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4021 /// the two vector operands have swapped position.
4022 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4023 unsigned NumElems) {
4024 for (unsigned i = 0; i != NumElems; ++i) {
4028 else if (idx < (int)NumElems)
4029 Mask[i] = idx + NumElems;
4031 Mask[i] = idx - NumElems;
4035 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4036 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4037 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4038 /// reverse of what x86 shuffles want.
4039 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4041 unsigned NumElems = VT.getVectorNumElements();
4042 unsigned NumLanes = VT.getSizeInBits()/128;
4043 unsigned NumLaneElems = NumElems/NumLanes;
4045 if (NumLaneElems != 2 && NumLaneElems != 4)
4048 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4049 bool symetricMaskRequired =
4050 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4052 // VSHUFPSY divides the resulting vector into 4 chunks.
4053 // The sources are also splitted into 4 chunks, and each destination
4054 // chunk must come from a different source chunk.
4056 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4057 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4059 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4060 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4062 // VSHUFPDY divides the resulting vector into 4 chunks.
4063 // The sources are also splitted into 4 chunks, and each destination
4064 // chunk must come from a different source chunk.
4066 // SRC1 => X3 X2 X1 X0
4067 // SRC2 => Y3 Y2 Y1 Y0
4069 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4071 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4072 unsigned HalfLaneElems = NumLaneElems/2;
4073 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4074 for (unsigned i = 0; i != NumLaneElems; ++i) {
4075 int Idx = Mask[i+l];
4076 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4077 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4079 // For VSHUFPSY, the mask of the second half must be the same as the
4080 // first but with the appropriate offsets. This works in the same way as
4081 // VPERMILPS works with masks.
4082 if (!symetricMaskRequired || Idx < 0)
4084 if (MaskVal[i] < 0) {
4085 MaskVal[i] = Idx - l;
4088 if ((signed)(Idx - l) != MaskVal[i])
4096 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4097 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4098 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4099 if (!VT.is128BitVector())
4102 unsigned NumElems = VT.getVectorNumElements();
4107 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4108 return isUndefOrEqual(Mask[0], 6) &&
4109 isUndefOrEqual(Mask[1], 7) &&
4110 isUndefOrEqual(Mask[2], 2) &&
4111 isUndefOrEqual(Mask[3], 3);
4114 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4115 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4117 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4118 if (!VT.is128BitVector())
4121 unsigned NumElems = VT.getVectorNumElements();
4126 return isUndefOrEqual(Mask[0], 2) &&
4127 isUndefOrEqual(Mask[1], 3) &&
4128 isUndefOrEqual(Mask[2], 2) &&
4129 isUndefOrEqual(Mask[3], 3);
4132 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4133 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4134 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4135 if (!VT.is128BitVector())
4138 unsigned NumElems = VT.getVectorNumElements();
4140 if (NumElems != 2 && NumElems != 4)
4143 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4144 if (!isUndefOrEqual(Mask[i], i + NumElems))
4147 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i))
4154 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4155 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4156 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4157 if (!VT.is128BitVector())
4160 unsigned NumElems = VT.getVectorNumElements();
4162 if (NumElems != 2 && NumElems != 4)
4165 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4166 if (!isUndefOrEqual(Mask[i], i))
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4176 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4177 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4178 /// i. e: If all but one element come from the same vector.
4179 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4180 // TODO: Deal with AVX's VINSERTPS
4181 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4184 unsigned CorrectPosV1 = 0;
4185 unsigned CorrectPosV2 = 0;
4186 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4187 if (Mask[i] == -1) {
4195 else if (Mask[i] == i + 4)
4199 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4200 // We have 3 elements (undefs count as elements from any vector) from one
4201 // vector, and one from another.
4208 // Some special combinations that can be optimized.
4211 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4212 SelectionDAG &DAG) {
4213 MVT VT = SVOp->getSimpleValueType(0);
4216 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4219 ArrayRef<int> Mask = SVOp->getMask();
4221 // These are the special masks that may be optimized.
4222 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4223 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4224 bool MatchEvenMask = true;
4225 bool MatchOddMask = true;
4226 for (int i=0; i<8; ++i) {
4227 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4228 MatchEvenMask = false;
4229 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4230 MatchOddMask = false;
4233 if (!MatchEvenMask && !MatchOddMask)
4236 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4238 SDValue Op0 = SVOp->getOperand(0);
4239 SDValue Op1 = SVOp->getOperand(1);
4241 if (MatchEvenMask) {
4242 // Shift the second operand right to 32 bits.
4243 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4244 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4246 // Shift the first operand left to 32 bits.
4247 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4248 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4250 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4251 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4254 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4255 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4256 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4257 bool HasInt256, bool V2IsSplat = false) {
4259 assert(VT.getSizeInBits() >= 128 &&
4260 "Unsupported vector type for unpckl");
4262 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4264 unsigned NumOf256BitLanes;
4265 unsigned NumElts = VT.getVectorNumElements();
4266 if (VT.is256BitVector()) {
4267 if (NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 NumOf256BitLanes = 1;
4272 } else if (VT.is512BitVector()) {
4273 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4274 "Unsupported vector type for unpckh");
4276 NumOf256BitLanes = 2;
4279 NumOf256BitLanes = 1;
4282 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4283 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4285 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4286 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l256*NumEltsInStride+l+i];
4289 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4290 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4292 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4294 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4302 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4303 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4304 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4305 bool HasInt256, bool V2IsSplat = false) {
4306 assert(VT.getSizeInBits() >= 128 &&
4307 "Unsupported vector type for unpckh");
4309 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4311 unsigned NumOf256BitLanes;
4312 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is256BitVector()) {
4314 if (NumElts != 4 && NumElts != 8 &&
4315 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4318 NumOf256BitLanes = 1;
4319 } else if (VT.is512BitVector()) {
4320 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4321 "Unsupported vector type for unpckh");
4323 NumOf256BitLanes = 2;
4326 NumOf256BitLanes = 1;
4329 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4330 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4332 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4333 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4334 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4335 int BitI = Mask[l256*NumEltsInStride+l+i];
4336 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4337 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4339 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4341 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4349 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4350 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4352 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4353 unsigned NumElts = VT.getVectorNumElements();
4354 bool Is256BitVec = VT.is256BitVector();
4356 if (VT.is512BitVector())
4358 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4359 "Unsupported vector type for unpckh");
4361 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4362 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4365 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4366 // FIXME: Need a better way to get rid of this, there's no latency difference
4367 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4368 // the former later. We should also remove the "_undef" special mask.
4369 if (NumElts == 4 && Is256BitVec)
4372 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4373 // independently on 128-bit lanes.
4374 unsigned NumLanes = VT.getSizeInBits()/128;
4375 unsigned NumLaneElts = NumElts/NumLanes;
4377 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4378 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4379 int BitI = Mask[l+i];
4380 int BitI1 = Mask[l+i+1];
4382 if (!isUndefOrEqual(BitI, j))
4384 if (!isUndefOrEqual(BitI1, j))
4392 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4393 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4395 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4396 unsigned NumElts = VT.getVectorNumElements();
4398 if (VT.is512BitVector())
4401 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4402 "Unsupported vector type for unpckh");
4404 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4405 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4408 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4409 // independently on 128-bit lanes.
4410 unsigned NumLanes = VT.getSizeInBits()/128;
4411 unsigned NumLaneElts = NumElts/NumLanes;
4413 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4414 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4415 int BitI = Mask[l+i];
4416 int BitI1 = Mask[l+i+1];
4417 if (!isUndefOrEqual(BitI, j))
4419 if (!isUndefOrEqual(BitI1, j))
4426 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4427 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4428 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4429 if (!VT.is512BitVector())
4432 unsigned NumElts = VT.getVectorNumElements();
4433 unsigned HalfSize = NumElts/2;
4434 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4435 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4440 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4441 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4449 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4450 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4451 /// MOVSD, and MOVD, i.e. setting the lowest element.
4452 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4453 if (VT.getVectorElementType().getSizeInBits() < 32)
4455 if (!VT.is128BitVector())
4458 unsigned NumElts = VT.getVectorNumElements();
4460 if (!isUndefOrEqual(Mask[0], NumElts))
4463 for (unsigned i = 1; i != NumElts; ++i)
4464 if (!isUndefOrEqual(Mask[i], i))
4470 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4471 /// as permutations between 128-bit chunks or halves. As an example: this
4473 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4474 /// The first half comes from the second half of V1 and the second half from the
4475 /// the second half of V2.
4476 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4477 if (!HasFp256 || !VT.is256BitVector())
4480 // The shuffle result is divided into half A and half B. In total the two
4481 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4482 // B must come from C, D, E or F.
4483 unsigned HalfSize = VT.getVectorNumElements()/2;
4484 bool MatchA = false, MatchB = false;
4486 // Check if A comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4494 // Check if B comes from one of C, D, E, F.
4495 for (unsigned Half = 0; Half != 4; ++Half) {
4496 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4502 return MatchA && MatchB;
4505 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4506 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4507 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4508 MVT VT = SVOp->getSimpleValueType(0);
4510 unsigned HalfSize = VT.getVectorNumElements()/2;
4512 unsigned FstHalf = 0, SndHalf = 0;
4513 for (unsigned i = 0; i < HalfSize; ++i) {
4514 if (SVOp->getMaskElt(i) > 0) {
4515 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4519 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4520 if (SVOp->getMaskElt(i) > 0) {
4521 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4526 return (FstHalf | (SndHalf << 4));
4529 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4530 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4531 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4535 unsigned NumElts = VT.getVectorNumElements();
4537 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4538 for (unsigned i = 0; i != NumElts; ++i) {
4541 Imm8 |= Mask[i] << (i*2);
4546 unsigned LaneSize = 4;
4547 SmallVector<int, 4> MaskVal(LaneSize, -1);
4549 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4550 for (unsigned i = 0; i != LaneSize; ++i) {
4551 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4555 if (MaskVal[i] < 0) {
4556 MaskVal[i] = Mask[i+l] - l;
4557 Imm8 |= MaskVal[i] << (i*2);
4560 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4567 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4568 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4569 /// Note that VPERMIL mask matching is different depending whether theunderlying
4570 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4571 /// to the same elements of the low, but to the higher half of the source.
4572 /// In VPERMILPD the two lanes could be shuffled independently of each other
4573 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4574 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4575 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4576 if (VT.getSizeInBits() < 256 || EltSize < 32)
4578 bool symetricMaskRequired = (EltSize == 32);
4579 unsigned NumElts = VT.getVectorNumElements();
4581 unsigned NumLanes = VT.getSizeInBits()/128;
4582 unsigned LaneSize = NumElts/NumLanes;
4583 // 2 or 4 elements in one lane
4585 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4586 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4587 for (unsigned i = 0; i != LaneSize; ++i) {
4588 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4590 if (symetricMaskRequired) {
4591 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4592 ExpectedMaskVal[i] = Mask[i+l] - l;
4595 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4603 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4604 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4605 /// element of vector 2 and the other elements to come from vector 1 in order.
4606 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4607 bool V2IsSplat = false, bool V2IsUndef = false) {
4608 if (!VT.is128BitVector())
4611 unsigned NumOps = VT.getVectorNumElements();
4612 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4615 if (!isUndefOrEqual(Mask[0], 0))
4618 for (unsigned i = 1; i != NumOps; ++i)
4619 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4620 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4621 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4627 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4628 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4629 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4630 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4631 const X86Subtarget *Subtarget) {
4632 if (!Subtarget->hasSSE3())
4635 unsigned NumElems = VT.getVectorNumElements();
4637 if ((VT.is128BitVector() && NumElems != 4) ||
4638 (VT.is256BitVector() && NumElems != 8) ||
4639 (VT.is512BitVector() && NumElems != 16))
4642 // "i+1" is the value the indexed mask element must have
4643 for (unsigned i = 0; i != NumElems; i += 2)
4644 if (!isUndefOrEqual(Mask[i], i+1) ||
4645 !isUndefOrEqual(Mask[i+1], i+1))
4651 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4652 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4653 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4654 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4655 const X86Subtarget *Subtarget) {
4656 if (!Subtarget->hasSSE3())
4659 unsigned NumElems = VT.getVectorNumElements();
4661 if ((VT.is128BitVector() && NumElems != 4) ||
4662 (VT.is256BitVector() && NumElems != 8) ||
4663 (VT.is512BitVector() && NumElems != 16))
4666 // "i" is the value the indexed mask element must have
4667 for (unsigned i = 0; i != NumElems; i += 2)
4668 if (!isUndefOrEqual(Mask[i], i) ||
4669 !isUndefOrEqual(Mask[i+1], i))
4675 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4676 /// specifies a shuffle of elements that is suitable for input to 256-bit
4677 /// version of MOVDDUP.
4678 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4679 if (!HasFp256 || !VT.is256BitVector())
4682 unsigned NumElts = VT.getVectorNumElements();
4686 for (unsigned i = 0; i != NumElts/2; ++i)
4687 if (!isUndefOrEqual(Mask[i], 0))
4689 for (unsigned i = NumElts/2; i != NumElts; ++i)
4690 if (!isUndefOrEqual(Mask[i], NumElts/2))
4695 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4696 /// specifies a shuffle of elements that is suitable for input to 128-bit
4697 /// version of MOVDDUP.
4698 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4699 if (!VT.is128BitVector())
4702 unsigned e = VT.getVectorNumElements() / 2;
4703 for (unsigned i = 0; i != e; ++i)
4704 if (!isUndefOrEqual(Mask[i], i))
4706 for (unsigned i = 0; i != e; ++i)
4707 if (!isUndefOrEqual(Mask[e+i], i))
4712 /// isVEXTRACTIndex - Return true if the specified
4713 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4714 /// suitable for instruction that extract 128 or 256 bit vectors
4715 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4716 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4717 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4720 // The index should be aligned on a vecWidth-bit boundary.
4722 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4724 MVT VT = N->getSimpleValueType(0);
4725 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4726 bool Result = (Index * ElSize) % vecWidth == 0;
4731 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4732 /// operand specifies a subvector insert that is suitable for input to
4733 /// insertion of 128 or 256-bit subvectors
4734 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4735 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4736 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4738 // The index should be aligned on a vecWidth-bit boundary.
4740 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4742 MVT VT = N->getSimpleValueType(0);
4743 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4744 bool Result = (Index * ElSize) % vecWidth == 0;
4749 bool X86::isVINSERT128Index(SDNode *N) {
4750 return isVINSERTIndex(N, 128);
4753 bool X86::isVINSERT256Index(SDNode *N) {
4754 return isVINSERTIndex(N, 256);
4757 bool X86::isVEXTRACT128Index(SDNode *N) {
4758 return isVEXTRACTIndex(N, 128);
4761 bool X86::isVEXTRACT256Index(SDNode *N) {
4762 return isVEXTRACTIndex(N, 256);
4765 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4766 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4767 /// Handles 128-bit and 256-bit.
4768 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4769 MVT VT = N->getSimpleValueType(0);
4771 assert((VT.getSizeInBits() >= 128) &&
4772 "Unsupported vector type for PSHUF/SHUFP");
4774 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4775 // independently on 128-bit lanes.
4776 unsigned NumElts = VT.getVectorNumElements();
4777 unsigned NumLanes = VT.getSizeInBits()/128;
4778 unsigned NumLaneElts = NumElts/NumLanes;
4780 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4781 "Only supports 2, 4 or 8 elements per lane");
4783 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4785 for (unsigned i = 0; i != NumElts; ++i) {
4786 int Elt = N->getMaskElt(i);
4787 if (Elt < 0) continue;
4788 Elt &= NumLaneElts - 1;
4789 unsigned ShAmt = (i << Shift) % 8;
4790 Mask |= Elt << ShAmt;
4796 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4797 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4798 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4799 MVT VT = N->getSimpleValueType(0);
4801 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4802 "Unsupported vector type for PSHUFHW");
4804 unsigned NumElts = VT.getVectorNumElements();
4807 for (unsigned l = 0; l != NumElts; l += 8) {
4808 // 8 nodes per lane, but we only care about the last 4.
4809 for (unsigned i = 0; i < 4; ++i) {
4810 int Elt = N->getMaskElt(l+i+4);
4811 if (Elt < 0) continue;
4812 Elt &= 0x3; // only 2-bits.
4813 Mask |= Elt << (i * 2);
4820 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4821 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4822 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4823 MVT VT = N->getSimpleValueType(0);
4825 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4826 "Unsupported vector type for PSHUFHW");
4828 unsigned NumElts = VT.getVectorNumElements();
4831 for (unsigned l = 0; l != NumElts; l += 8) {
4832 // 8 nodes per lane, but we only care about the first 4.
4833 for (unsigned i = 0; i < 4; ++i) {
4834 int Elt = N->getMaskElt(l+i);
4835 if (Elt < 0) continue;
4836 Elt &= 0x3; // only 2-bits
4837 Mask |= Elt << (i * 2);
4844 /// \brief Return the appropriate immediate to shuffle the specified
4845 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4846 /// VALIGN (if Interlane is true) instructions.
4847 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4849 MVT VT = SVOp->getSimpleValueType(0);
4850 unsigned EltSize = InterLane ? 1 :
4851 VT.getVectorElementType().getSizeInBits() >> 3;
4853 unsigned NumElts = VT.getVectorNumElements();
4854 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4855 unsigned NumLaneElts = NumElts/NumLanes;
4859 for (i = 0; i != NumElts; ++i) {
4860 Val = SVOp->getMaskElt(i);
4864 if (Val >= (int)NumElts)
4865 Val -= NumElts - NumLaneElts;
4867 assert(Val - i > 0 && "PALIGNR imm should be positive");
4868 return (Val - i) * EltSize;
4871 /// \brief Return the appropriate immediate to shuffle the specified
4872 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4873 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4874 return getShuffleAlignrImmediate(SVOp, false);
4877 /// \brief Return the appropriate immediate to shuffle the specified
4878 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4879 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4880 return getShuffleAlignrImmediate(SVOp, true);
4884 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4887 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4890 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4892 MVT VecVT = N->getOperand(0).getSimpleValueType();
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4900 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4901 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4902 llvm_unreachable("Illegal insert subvector for VINSERT");
4905 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4907 MVT VecVT = N->getSimpleValueType(0);
4908 MVT ElVT = VecVT.getVectorElementType();
4910 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4911 return Index / NumElemsPerChunk;
4914 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 128);
4921 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4922 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4925 return getExtractVEXTRACTImmediate(N, 256);
4928 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4930 /// and VINSERTI128 instructions.
4931 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 128);
4935 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4936 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4937 /// and VINSERTI64x4 instructions.
4938 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4939 return getInsertVINSERTImmediate(N, 256);
4942 /// isZero - Returns true if Elt is a constant integer zero
4943 static bool isZero(SDValue V) {
4944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4945 return C && C->isNullValue();
4948 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4950 bool X86::isZeroNode(SDValue Elt) {
4953 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4954 return CFP->getValueAPF().isPosZero();
4958 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4959 /// match movhlps. The lower half elements should come from upper half of
4960 /// V1 (and in order), and the upper half elements should come from the upper
4961 /// half of V2 (and in order).
4962 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4963 if (!VT.is128BitVector())
4965 if (VT.getVectorNumElements() != 4)
4967 for (unsigned i = 0, e = 2; i != e; ++i)
4968 if (!isUndefOrEqual(Mask[i], i+2))
4970 for (unsigned i = 2; i != 4; ++i)
4971 if (!isUndefOrEqual(Mask[i], i+4))
4976 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4977 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4979 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4980 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4982 N = N->getOperand(0).getNode();
4983 if (!ISD::isNON_EXTLoad(N))
4986 *LD = cast<LoadSDNode>(N);
4990 // Test whether the given value is a vector value which will be legalized
4992 static bool WillBeConstantPoolLoad(SDNode *N) {
4993 if (N->getOpcode() != ISD::BUILD_VECTOR)
4996 // Check for any non-constant elements.
4997 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4998 switch (N->getOperand(i).getNode()->getOpcode()) {
5000 case ISD::ConstantFP:
5007 // Vectors of all-zeros and all-ones are materialized with special
5008 // instructions rather than being loaded.
5009 return !ISD::isBuildVectorAllZeros(N) &&
5010 !ISD::isBuildVectorAllOnes(N);
5013 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5014 /// match movlp{s|d}. The lower half elements should come from lower half of
5015 /// V1 (and in order), and the upper half elements should come from the upper
5016 /// half of V2 (and in order). And since V1 will become the source of the
5017 /// MOVLP, it must be either a vector load or a scalar load to vector.
5018 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5019 ArrayRef<int> Mask, MVT VT) {
5020 if (!VT.is128BitVector())
5023 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5025 // Is V2 is a vector load, don't do this transformation. We will try to use
5026 // load folding shufps op.
5027 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5030 unsigned NumElems = VT.getVectorNumElements();
5032 if (NumElems != 2 && NumElems != 4)
5034 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5035 if (!isUndefOrEqual(Mask[i], i))
5037 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+NumElems))
5043 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5044 /// to an zero vector.
5045 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5046 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5047 SDValue V1 = N->getOperand(0);
5048 SDValue V2 = N->getOperand(1);
5049 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5050 for (unsigned i = 0; i != NumElems; ++i) {
5051 int Idx = N->getMaskElt(i);
5052 if (Idx >= (int)NumElems) {
5053 unsigned Opc = V2.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5059 } else if (Idx >= 0) {
5060 unsigned Opc = V1.getOpcode();
5061 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5063 if (Opc != ISD::BUILD_VECTOR ||
5064 !X86::isZeroNode(V1.getOperand(Idx)))
5071 /// getZeroVector - Returns a vector of specified type with all zero elements.
5073 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5074 SelectionDAG &DAG, SDLoc dl) {
5075 assert(VT.isVector() && "Expected a vector type");
5077 // Always build SSE zero vectors as <4 x i32> bitcasted
5078 // to their dest type. This ensures they get CSE'd.
5080 if (VT.is128BitVector()) { // SSE
5081 if (Subtarget->hasSSE2()) { // SSE2
5082 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5085 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5088 } else if (VT.is256BitVector()) { // AVX
5089 if (Subtarget->hasInt256()) { // AVX2
5090 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5091 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5092 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5094 // 256-bit logic and arithmetic instructions in AVX are all
5095 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5096 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5097 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5098 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5100 } else if (VT.is512BitVector()) { // AVX-512
5101 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5102 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5103 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5104 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5105 } else if (VT.getScalarType() == MVT::i1) {
5106 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5107 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5108 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5109 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5111 llvm_unreachable("Unexpected vector type");
5113 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5116 /// getOnesVector - Returns a vector of specified type with all bits set.
5117 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5118 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5119 /// Then bitcast to their original type, ensuring they get CSE'd.
5120 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5122 assert(VT.isVector() && "Expected a vector type");
5124 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5126 if (VT.is256BitVector()) {
5127 if (HasInt256) { // AVX2
5128 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5132 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5134 } else if (VT.is128BitVector()) {
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5137 llvm_unreachable("Unexpected vector type");
5139 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5142 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5143 /// that point to V2 points to its first element.
5144 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5145 for (unsigned i = 0; i != NumElems; ++i) {
5146 if (Mask[i] > (int)NumElems) {
5152 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5153 /// operation of specified width.
5154 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5156 unsigned NumElems = VT.getVectorNumElements();
5157 SmallVector<int, 8> Mask;
5158 Mask.push_back(NumElems);
5159 for (unsigned i = 1; i != NumElems; ++i)
5161 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5164 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5165 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5167 unsigned NumElems = VT.getVectorNumElements();
5168 SmallVector<int, 8> Mask;
5169 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5171 Mask.push_back(i + NumElems);
5173 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5176 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5177 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5179 unsigned NumElems = VT.getVectorNumElements();
5180 SmallVector<int, 8> Mask;
5181 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5182 Mask.push_back(i + Half);
5183 Mask.push_back(i + NumElems + Half);
5185 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5188 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5189 // a generic shuffle instruction because the target has no such instructions.
5190 // Generate shuffles which repeat i16 and i8 several times until they can be
5191 // represented by v4f32 and then be manipulated by target suported shuffles.
5192 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5193 MVT VT = V.getSimpleValueType();
5194 int NumElems = VT.getVectorNumElements();
5197 while (NumElems > 4) {
5198 if (EltNo < NumElems/2) {
5199 V = getUnpackl(DAG, dl, VT, V, V);
5201 V = getUnpackh(DAG, dl, VT, V, V);
5202 EltNo -= NumElems/2;
5209 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5210 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5211 MVT VT = V.getSimpleValueType();
5214 if (VT.is128BitVector()) {
5215 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5216 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5217 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5219 } else if (VT.is256BitVector()) {
5220 // To use VPERMILPS to splat scalars, the second half of indicies must
5221 // refer to the higher part, which is a duplication of the lower one,
5222 // because VPERMILPS can only handle in-lane permutations.
5223 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5224 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5226 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5227 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5230 llvm_unreachable("Vector size not supported");
5232 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5235 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5236 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5237 MVT SrcVT = SV->getSimpleValueType(0);
5238 SDValue V1 = SV->getOperand(0);
5241 int EltNo = SV->getSplatIndex();
5242 int NumElems = SrcVT.getVectorNumElements();
5243 bool Is256BitVec = SrcVT.is256BitVector();
5245 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5246 "Unknown how to promote splat for type");
5248 // Extract the 128-bit part containing the splat element and update
5249 // the splat element index when it refers to the higher register.
5251 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5252 if (EltNo >= NumElems/2)
5253 EltNo -= NumElems/2;
5256 // All i16 and i8 vector types can't be used directly by a generic shuffle
5257 // instruction because the target has no such instruction. Generate shuffles
5258 // which repeat i16 and i8 several times until they fit in i32, and then can
5259 // be manipulated by target suported shuffles.
5260 MVT EltVT = SrcVT.getVectorElementType();
5261 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5262 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5264 // Recreate the 256-bit vector and place the same 128-bit vector
5265 // into the low and high part. This is necessary because we want
5266 // to use VPERM* to shuffle the vectors
5268 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5271 return getLegalSplat(DAG, V1, EltNo);
5274 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5275 /// vector of zero or undef vector. This produces a shuffle where the low
5276 /// element of V2 is swizzled into the zero/undef vector, landing at element
5277 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5278 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5280 const X86Subtarget *Subtarget,
5281 SelectionDAG &DAG) {
5282 MVT VT = V2.getSimpleValueType();
5284 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5285 unsigned NumElems = VT.getVectorNumElements();
5286 SmallVector<int, 16> MaskVec;
5287 for (unsigned i = 0; i != NumElems; ++i)
5288 // If this is the insertion idx, put the low elt of V2 here.
5289 MaskVec.push_back(i == Idx ? NumElems : i);
5290 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5293 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5294 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5295 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5296 /// shuffles which use a single input multiple times, and in those cases it will
5297 /// adjust the mask to only have indices within that single input.
5298 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5299 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5300 unsigned NumElems = VT.getVectorNumElements();
5304 bool IsFakeUnary = false;
5305 switch(N->getOpcode()) {
5307 ImmN = N->getOperand(N->getNumOperands()-1);
5308 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKH:
5312 DecodeUNPCKHMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::UNPCKL:
5316 DecodeUNPCKLMask(VT, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVHLPS:
5320 DecodeMOVHLPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::MOVLHPS:
5324 DecodeMOVLHPSMask(NumElems, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::PALIGNR:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 case X86ISD::PSHUFD:
5332 case X86ISD::VPERMILP:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFHW:
5338 ImmN = N->getOperand(N->getNumOperands()-1);
5339 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFLW:
5343 ImmN = N->getOperand(N->getNumOperands()-1);
5344 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5347 case X86ISD::PSHUFB: {
5349 SDValue MaskNode = N->getOperand(1);
5350 while (MaskNode->getOpcode() == ISD::BITCAST)
5351 MaskNode = MaskNode->getOperand(0);
5353 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5354 // If we have a build-vector, then things are easy.
5355 EVT VT = MaskNode.getValueType();
5356 assert(VT.isVector() &&
5357 "Can't produce a non-vector with a build_vector!");
5358 if (!VT.isInteger())
5361 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5363 SmallVector<uint64_t, 32> RawMask;
5364 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5365 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5368 APInt MaskElement = CN->getAPIntValue();
5370 // We now have to decode the element which could be any integer size and
5371 // extract each byte of it.
5372 for (int j = 0; j < NumBytesPerElement; ++j) {
5373 // Note that this is x86 and so always little endian: the low byte is
5374 // the first byte of the mask.
5375 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5376 MaskElement = MaskElement.lshr(8);
5379 DecodePSHUFBMask(RawMask, Mask);
5383 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5387 SDValue Ptr = MaskLoad->getBasePtr();
5388 if (Ptr->getOpcode() == X86ISD::Wrapper)
5389 Ptr = Ptr->getOperand(0);
5391 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5392 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5395 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5396 // FIXME: Support AVX-512 here.
5397 if (!C->getType()->isVectorTy() ||
5398 (C->getNumElements() != 16 && C->getNumElements() != 32))
5401 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5402 DecodePSHUFBMask(C, Mask);
5408 case X86ISD::VPERMI:
5409 ImmN = N->getOperand(N->getNumOperands()-1);
5410 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5414 case X86ISD::MOVSD: {
5415 // The index 0 always comes from the first element of the second source,
5416 // this is why MOVSS and MOVSD are used in the first place. The other
5417 // elements come from the other positions of the first source vector
5418 Mask.push_back(NumElems);
5419 for (unsigned i = 1; i != NumElems; ++i) {
5424 case X86ISD::VPERM2X128:
5425 ImmN = N->getOperand(N->getNumOperands()-1);
5426 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5427 if (Mask.empty()) return false;
5429 case X86ISD::MOVDDUP:
5430 case X86ISD::MOVLHPD:
5431 case X86ISD::MOVLPD:
5432 case X86ISD::MOVLPS:
5433 case X86ISD::MOVSHDUP:
5434 case X86ISD::MOVSLDUP:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 if (!Subtarget->hasFp256())
6013 MVT VT = Op.getSimpleValueType();
6016 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6017 "Unsupported vector type for broadcast.");
6022 switch (Op.getOpcode()) {
6024 // Unknown pattern found.
6027 case ISD::BUILD_VECTOR: {
6028 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6029 BitVector UndefElements;
6030 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6032 // We need a splat of a single value to use broadcast, and it doesn't
6033 // make any sense if the value is only in one element of the vector.
6034 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6038 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6039 Ld.getOpcode() == ISD::ConstantFP);
6041 // Make sure that all of the users of a non-constant load are from the
6042 // BUILD_VECTOR node.
6043 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6048 case ISD::VECTOR_SHUFFLE: {
6049 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6051 // Shuffles must have a splat mask where the first element is
6053 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6056 SDValue Sc = Op.getOperand(0);
6057 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6058 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6060 if (!Subtarget->hasInt256())
6063 // Use the register form of the broadcast instruction available on AVX2.
6064 if (VT.getSizeInBits() >= 256)
6065 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6066 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6069 Ld = Sc.getOperand(0);
6070 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6071 Ld.getOpcode() == ISD::ConstantFP);
6073 // The scalar_to_vector node and the suspected
6074 // load node must have exactly one user.
6075 // Constants may have multiple users.
6077 // AVX-512 has register version of the broadcast
6078 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6079 Ld.getValueType().getSizeInBits() >= 32;
6080 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6087 bool IsGE256 = (VT.getSizeInBits() >= 256);
6089 // Handle the broadcasting a single constant scalar from the constant pool
6090 // into a vector. On Sandybridge it is still better to load a constant vector
6091 // from the constant pool and not to broadcast it from a scalar.
6092 if (ConstSplatVal && Subtarget->hasInt256()) {
6093 EVT CVT = Ld.getValueType();
6094 assert(!CVT.isVector() && "Must not broadcast a vector type");
6095 unsigned ScalarSize = CVT.getSizeInBits();
6097 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
6098 const Constant *C = nullptr;
6099 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6100 C = CI->getConstantIntValue();
6101 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6102 C = CF->getConstantFPValue();
6104 assert(C && "Invalid constant type");
6106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6107 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6108 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6109 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6110 MachinePointerInfo::getConstantPool(),
6111 false, false, false, Alignment);
6113 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6117 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6118 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6120 // Handle AVX2 in-register broadcasts.
6121 if (!IsLoad && Subtarget->hasInt256() &&
6122 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6123 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6125 // The scalar source must be a normal load.
6129 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6130 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6132 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6133 // double since there is no vbroadcastsd xmm
6134 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6135 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6136 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6139 // Unsupported broadcast.
6143 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6144 /// underlying vector and index.
6146 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6148 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6150 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6151 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6154 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6156 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6158 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6159 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6162 // In this case the vector is the extract_subvector expression and the index
6163 // is 2, as specified by the shuffle.
6164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6165 SDValue ShuffleVec = SVOp->getOperand(0);
6166 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6167 assert(ShuffleVecVT.getVectorElementType() ==
6168 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6170 int ShuffleIdx = SVOp->getMaskElt(Idx);
6171 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6172 ExtractedFromVec = ShuffleVec;
6178 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6179 MVT VT = Op.getSimpleValueType();
6181 // Skip if insert_vec_elt is not supported.
6182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6183 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6187 unsigned NumElems = Op.getNumOperands();
6191 SmallVector<unsigned, 4> InsertIndices;
6192 SmallVector<int, 8> Mask(NumElems, -1);
6194 for (unsigned i = 0; i != NumElems; ++i) {
6195 unsigned Opc = Op.getOperand(i).getOpcode();
6197 if (Opc == ISD::UNDEF)
6200 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6201 // Quit if more than 1 elements need inserting.
6202 if (InsertIndices.size() > 1)
6205 InsertIndices.push_back(i);
6209 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6210 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6211 // Quit if non-constant index.
6212 if (!isa<ConstantSDNode>(ExtIdx))
6214 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6216 // Quit if extracted from vector of different type.
6217 if (ExtractedFromVec.getValueType() != VT)
6220 if (!VecIn1.getNode())
6221 VecIn1 = ExtractedFromVec;
6222 else if (VecIn1 != ExtractedFromVec) {
6223 if (!VecIn2.getNode())
6224 VecIn2 = ExtractedFromVec;
6225 else if (VecIn2 != ExtractedFromVec)
6226 // Quit if more than 2 vectors to shuffle
6230 if (ExtractedFromVec == VecIn1)
6232 else if (ExtractedFromVec == VecIn2)
6233 Mask[i] = Idx + NumElems;
6236 if (!VecIn1.getNode())
6239 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6240 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6241 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6242 unsigned Idx = InsertIndices[i];
6243 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6244 DAG.getIntPtrConstant(Idx));
6250 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6252 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6254 MVT VT = Op.getSimpleValueType();
6255 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6256 "Unexpected type in LowerBUILD_VECTORvXi1!");
6259 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6260 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6261 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6262 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6265 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6266 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6267 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6268 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6271 bool AllContants = true;
6272 uint64_t Immediate = 0;
6273 int NonConstIdx = -1;
6274 bool IsSplat = true;
6275 unsigned NumNonConsts = 0;
6276 unsigned NumConsts = 0;
6277 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6278 SDValue In = Op.getOperand(idx);
6279 if (In.getOpcode() == ISD::UNDEF)
6281 if (!isa<ConstantSDNode>(In)) {
6282 AllContants = false;
6288 if (cast<ConstantSDNode>(In)->getZExtValue())
6289 Immediate |= (1ULL << idx);
6291 if (In != Op.getOperand(0))
6296 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6297 DAG.getConstant(Immediate, MVT::i16));
6298 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6299 DAG.getIntPtrConstant(0));
6302 if (NumNonConsts == 1 && NonConstIdx != 0) {
6305 SDValue VecAsImm = DAG.getConstant(Immediate,
6306 MVT::getIntegerVT(VT.getSizeInBits()));
6307 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6310 DstVec = DAG.getUNDEF(VT);
6311 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6312 Op.getOperand(NonConstIdx),
6313 DAG.getIntPtrConstant(NonConstIdx));
6315 if (!IsSplat && (NonConstIdx != 0))
6316 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6317 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6320 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6321 DAG.getConstant(-1, SelectVT),
6322 DAG.getConstant(0, SelectVT));
6324 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6325 DAG.getConstant((Immediate | 1), SelectVT),
6326 DAG.getConstant(Immediate, SelectVT));
6327 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6330 /// \brief Return true if \p N implements a horizontal binop and return the
6331 /// operands for the horizontal binop into V0 and V1.
6333 /// This is a helper function of PerformBUILD_VECTORCombine.
6334 /// This function checks that the build_vector \p N in input implements a
6335 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6336 /// operation to match.
6337 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6338 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6339 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6342 /// This function only analyzes elements of \p N whose indices are
6343 /// in range [BaseIdx, LastIdx).
6344 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6346 unsigned BaseIdx, unsigned LastIdx,
6347 SDValue &V0, SDValue &V1) {
6348 EVT VT = N->getValueType(0);
6350 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6351 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6352 "Invalid Vector in input!");
6354 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6355 bool CanFold = true;
6356 unsigned ExpectedVExtractIdx = BaseIdx;
6357 unsigned NumElts = LastIdx - BaseIdx;
6358 V0 = DAG.getUNDEF(VT);
6359 V1 = DAG.getUNDEF(VT);
6361 // Check if N implements a horizontal binop.
6362 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6363 SDValue Op = N->getOperand(i + BaseIdx);
6366 if (Op->getOpcode() == ISD::UNDEF) {
6367 // Update the expected vector extract index.
6368 if (i * 2 == NumElts)
6369 ExpectedVExtractIdx = BaseIdx;
6370 ExpectedVExtractIdx += 2;
6374 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6379 SDValue Op0 = Op.getOperand(0);
6380 SDValue Op1 = Op.getOperand(1);
6382 // Try to match the following pattern:
6383 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6384 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6385 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6386 Op0.getOperand(0) == Op1.getOperand(0) &&
6387 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6388 isa<ConstantSDNode>(Op1.getOperand(1)));
6392 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6393 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6395 if (i * 2 < NumElts) {
6396 if (V0.getOpcode() == ISD::UNDEF)
6397 V0 = Op0.getOperand(0);
6399 if (V1.getOpcode() == ISD::UNDEF)
6400 V1 = Op0.getOperand(0);
6401 if (i * 2 == NumElts)
6402 ExpectedVExtractIdx = BaseIdx;
6405 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6406 if (I0 == ExpectedVExtractIdx)
6407 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6408 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6409 // Try to match the following dag sequence:
6410 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6411 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6415 ExpectedVExtractIdx += 2;
6421 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6422 /// a concat_vector.
6424 /// This is a helper function of PerformBUILD_VECTORCombine.
6425 /// This function expects two 256-bit vectors called V0 and V1.
6426 /// At first, each vector is split into two separate 128-bit vectors.
6427 /// Then, the resulting 128-bit vectors are used to implement two
6428 /// horizontal binary operations.
6430 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6432 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6433 /// the two new horizontal binop.
6434 /// When Mode is set, the first horizontal binop dag node would take as input
6435 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6436 /// horizontal binop dag node would take as input the lower 128-bit of V1
6437 /// and the upper 128-bit of V1.
6439 /// HADD V0_LO, V0_HI
6440 /// HADD V1_LO, V1_HI
6442 /// Otherwise, the first horizontal binop dag node takes as input the lower
6443 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6444 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6446 /// HADD V0_LO, V1_LO
6447 /// HADD V0_HI, V1_HI
6449 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6450 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6451 /// the upper 128-bits of the result.
6452 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6453 SDLoc DL, SelectionDAG &DAG,
6454 unsigned X86Opcode, bool Mode,
6455 bool isUndefLO, bool isUndefHI) {
6456 EVT VT = V0.getValueType();
6457 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6458 "Invalid nodes in input!");
6460 unsigned NumElts = VT.getVectorNumElements();
6461 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6462 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6463 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6464 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6465 EVT NewVT = V0_LO.getValueType();
6467 SDValue LO = DAG.getUNDEF(NewVT);
6468 SDValue HI = DAG.getUNDEF(NewVT);
6471 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6472 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6473 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6474 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6475 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6477 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6478 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6479 V1_LO->getOpcode() != ISD::UNDEF))
6480 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6482 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6483 V1_HI->getOpcode() != ISD::UNDEF))
6484 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6487 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6490 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6491 /// sequence of 'vadd + vsub + blendi'.
6492 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6493 const X86Subtarget *Subtarget) {
6495 EVT VT = BV->getValueType(0);
6496 unsigned NumElts = VT.getVectorNumElements();
6497 SDValue InVec0 = DAG.getUNDEF(VT);
6498 SDValue InVec1 = DAG.getUNDEF(VT);
6500 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6501 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6503 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6504 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6505 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6508 // Odd-numbered elements in the input build vector are obtained from
6509 // adding two integer/float elements.
6510 // Even-numbered elements in the input build vector are obtained from
6511 // subtracting two integer/float elements.
6512 unsigned ExpectedOpcode = ISD::FSUB;
6513 unsigned NextExpectedOpcode = ISD::FADD;
6514 bool AddFound = false;
6515 bool SubFound = false;
6517 for (unsigned i = 0, e = NumElts; i != e; i++) {
6518 SDValue Op = BV->getOperand(i);
6520 // Skip 'undef' values.
6521 unsigned Opcode = Op.getOpcode();
6522 if (Opcode == ISD::UNDEF) {
6523 std::swap(ExpectedOpcode, NextExpectedOpcode);
6527 // Early exit if we found an unexpected opcode.
6528 if (Opcode != ExpectedOpcode)
6531 SDValue Op0 = Op.getOperand(0);
6532 SDValue Op1 = Op.getOperand(1);
6534 // Try to match the following pattern:
6535 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6536 // Early exit if we cannot match that sequence.
6537 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6538 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6539 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6540 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6541 Op0.getOperand(1) != Op1.getOperand(1))
6544 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6548 // We found a valid add/sub node. Update the information accordingly.
6554 // Update InVec0 and InVec1.
6555 if (InVec0.getOpcode() == ISD::UNDEF)
6556 InVec0 = Op0.getOperand(0);
6557 if (InVec1.getOpcode() == ISD::UNDEF)
6558 InVec1 = Op1.getOperand(0);
6560 // Make sure that operands in input to each add/sub node always
6561 // come from a same pair of vectors.
6562 if (InVec0 != Op0.getOperand(0)) {
6563 if (ExpectedOpcode == ISD::FSUB)
6566 // FADD is commutable. Try to commute the operands
6567 // and then test again.
6568 std::swap(Op0, Op1);
6569 if (InVec0 != Op0.getOperand(0))
6573 if (InVec1 != Op1.getOperand(0))
6576 // Update the pair of expected opcodes.
6577 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Don't try to fold this build_vector into a VSELECT if it has
6581 // too many UNDEF operands.
6582 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6583 InVec1.getOpcode() != ISD::UNDEF) {
6584 // Emit a sequence of vector add and sub followed by a VSELECT.
6585 // The new VSELECT will be lowered into a BLENDI.
6586 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6587 // and emit a single ADDSUB instruction.
6588 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6589 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6591 // Construct the VSELECT mask.
6592 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6593 EVT SVT = MaskVT.getVectorElementType();
6594 unsigned SVTBits = SVT.getSizeInBits();
6595 SmallVector<SDValue, 8> Ops;
6597 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6598 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6599 APInt::getAllOnesValue(SVTBits);
6600 SDValue Constant = DAG.getConstant(Value, SVT);
6601 Ops.push_back(Constant);
6604 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6605 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6611 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6612 const X86Subtarget *Subtarget) {
6614 EVT VT = N->getValueType(0);
6615 unsigned NumElts = VT.getVectorNumElements();
6616 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6617 SDValue InVec0, InVec1;
6619 // Try to match an ADDSUB.
6620 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6621 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6622 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6623 if (Value.getNode())
6627 // Try to match horizontal ADD/SUB.
6628 unsigned NumUndefsLO = 0;
6629 unsigned NumUndefsHI = 0;
6630 unsigned Half = NumElts/2;
6632 // Count the number of UNDEF operands in the build_vector in input.
6633 for (unsigned i = 0, e = Half; i != e; ++i)
6634 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6637 for (unsigned i = Half, e = NumElts; i != e; ++i)
6638 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6641 // Early exit if this is either a build_vector of all UNDEFs or all the
6642 // operands but one are UNDEF.
6643 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6646 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6647 // Try to match an SSE3 float HADD/HSUB.
6648 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6651 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6652 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6653 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6654 // Try to match an SSSE3 integer HADD/HSUB.
6655 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6656 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6658 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6659 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6662 if (!Subtarget->hasAVX())
6665 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6666 // Try to match an AVX horizontal add/sub of packed single/double
6667 // precision floating point values from 256-bit vectors.
6668 SDValue InVec2, InVec3;
6669 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6670 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6671 ((InVec0.getOpcode() == ISD::UNDEF ||
6672 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6673 ((InVec1.getOpcode() == ISD::UNDEF ||
6674 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6675 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6677 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6678 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6679 ((InVec0.getOpcode() == ISD::UNDEF ||
6680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6681 ((InVec1.getOpcode() == ISD::UNDEF ||
6682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6683 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6684 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6685 // Try to match an AVX2 horizontal add/sub of signed integers.
6686 SDValue InVec2, InVec3;
6688 bool CanFold = true;
6690 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6691 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6692 ((InVec0.getOpcode() == ISD::UNDEF ||
6693 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6694 ((InVec1.getOpcode() == ISD::UNDEF ||
6695 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6696 X86Opcode = X86ISD::HADD;
6697 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6698 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6699 ((InVec0.getOpcode() == ISD::UNDEF ||
6700 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6701 ((InVec1.getOpcode() == ISD::UNDEF ||
6702 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6703 X86Opcode = X86ISD::HSUB;
6708 // Fold this build_vector into a single horizontal add/sub.
6709 // Do this only if the target has AVX2.
6710 if (Subtarget->hasAVX2())
6711 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6713 // Do not try to expand this build_vector into a pair of horizontal
6714 // add/sub if we can emit a pair of scalar add/sub.
6715 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6718 // Convert this build_vector into a pair of horizontal binop followed by
6720 bool isUndefLO = NumUndefsLO == Half;
6721 bool isUndefHI = NumUndefsHI == Half;
6722 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6723 isUndefLO, isUndefHI);
6727 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6728 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6730 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6731 X86Opcode = X86ISD::HADD;
6732 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6733 X86Opcode = X86ISD::HSUB;
6734 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6735 X86Opcode = X86ISD::FHADD;
6736 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6737 X86Opcode = X86ISD::FHSUB;
6741 // Don't try to expand this build_vector into a pair of horizontal add/sub
6742 // if we can simply emit a pair of scalar add/sub.
6743 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6746 // Convert this build_vector into two horizontal add/sub followed by
6748 bool isUndefLO = NumUndefsLO == Half;
6749 bool isUndefHI = NumUndefsHI == Half;
6750 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6751 isUndefLO, isUndefHI);
6758 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6761 MVT VT = Op.getSimpleValueType();
6762 MVT ExtVT = VT.getVectorElementType();
6763 unsigned NumElems = Op.getNumOperands();
6765 // Generate vectors for predicate vectors.
6766 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6767 return LowerBUILD_VECTORvXi1(Op, DAG);
6769 // Vectors containing all zeros can be matched by pxor and xorps later
6770 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6771 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6772 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6773 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6776 return getZeroVector(VT, Subtarget, DAG, dl);
6779 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6780 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6781 // vpcmpeqd on 256-bit vectors.
6782 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6783 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6786 if (!VT.is512BitVector())
6787 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6790 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6791 if (Broadcast.getNode())
6794 unsigned EVTBits = ExtVT.getSizeInBits();
6796 unsigned NumZero = 0;
6797 unsigned NumNonZero = 0;
6798 unsigned NonZeros = 0;
6799 bool IsAllConstants = true;
6800 SmallSet<SDValue, 8> Values;
6801 for (unsigned i = 0; i < NumElems; ++i) {
6802 SDValue Elt = Op.getOperand(i);
6803 if (Elt.getOpcode() == ISD::UNDEF)
6806 if (Elt.getOpcode() != ISD::Constant &&
6807 Elt.getOpcode() != ISD::ConstantFP)
6808 IsAllConstants = false;
6809 if (X86::isZeroNode(Elt))
6812 NonZeros |= (1 << i);
6817 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6818 if (NumNonZero == 0)
6819 return DAG.getUNDEF(VT);
6821 // Special case for single non-zero, non-undef, element.
6822 if (NumNonZero == 1) {
6823 unsigned Idx = countTrailingZeros(NonZeros);
6824 SDValue Item = Op.getOperand(Idx);
6826 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6827 // the value are obviously zero, truncate the value to i32 and do the
6828 // insertion that way. Only do this if the value is non-constant or if the
6829 // value is a constant being inserted into element 0. It is cheaper to do
6830 // a constant pool load than it is to do a movd + shuffle.
6831 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6832 (!IsAllConstants || Idx == 0)) {
6833 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6835 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6836 EVT VecVT = MVT::v4i32;
6837 unsigned VecElts = 4;
6839 // Truncate the value (which may itself be a constant) to i32, and
6840 // convert it to a vector with movd (S2V+shuffle to zero extend).
6841 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6842 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6843 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6845 // Now we have our 32-bit value zero extended in the low element of
6846 // a vector. If Idx != 0, swizzle it into place.
6848 SmallVector<int, 4> Mask;
6849 Mask.push_back(Idx);
6850 for (unsigned i = 1; i != VecElts; ++i)
6852 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6855 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6859 // If we have a constant or non-constant insertion into the low element of
6860 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6861 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6862 // depending on what the source datatype is.
6865 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6867 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6868 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6869 if (VT.is256BitVector() || VT.is512BitVector()) {
6870 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6871 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6872 Item, DAG.getIntPtrConstant(0));
6874 assert(VT.is128BitVector() && "Expected an SSE value type!");
6875 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6876 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6877 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6880 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6881 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6883 if (VT.is256BitVector()) {
6884 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6885 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6887 assert(VT.is128BitVector() && "Expected an SSE value type!");
6888 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6890 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6894 // Is it a vector logical left shift?
6895 if (NumElems == 2 && Idx == 1 &&
6896 X86::isZeroNode(Op.getOperand(0)) &&
6897 !X86::isZeroNode(Op.getOperand(1))) {
6898 unsigned NumBits = VT.getSizeInBits();
6899 return getVShift(true, VT,
6900 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6901 VT, Op.getOperand(1)),
6902 NumBits/2, DAG, *this, dl);
6905 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6908 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6909 // is a non-constant being inserted into an element other than the low one,
6910 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6911 // movd/movss) to move this into the low element, then shuffle it into
6913 if (EVTBits == 32) {
6914 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6916 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6917 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6918 SmallVector<int, 8> MaskVec;
6919 for (unsigned i = 0; i != NumElems; ++i)
6920 MaskVec.push_back(i == Idx ? 0 : 1);
6921 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6925 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6926 if (Values.size() == 1) {
6927 if (EVTBits == 32) {
6928 // Instead of a shuffle like this:
6929 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6930 // Check if it's possible to issue this instead.
6931 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6932 unsigned Idx = countTrailingZeros(NonZeros);
6933 SDValue Item = Op.getOperand(Idx);
6934 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6935 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6940 // A vector full of immediates; various special cases are already
6941 // handled, so this is best done with a single constant-pool load.
6945 // For AVX-length vectors, build the individual 128-bit pieces and use
6946 // shuffles to put them in place.
6947 if (VT.is256BitVector() || VT.is512BitVector()) {
6948 SmallVector<SDValue, 64> V;
6949 for (unsigned i = 0; i != NumElems; ++i)
6950 V.push_back(Op.getOperand(i));
6952 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6954 // Build both the lower and upper subvector.
6955 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6956 makeArrayRef(&V[0], NumElems/2));
6957 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[NumElems / 2], NumElems/2));
6960 // Recreate the wider vector with the lower and upper part.
6961 if (VT.is256BitVector())
6962 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6963 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6966 // Let legalizer expand 2-wide build_vectors.
6967 if (EVTBits == 64) {
6968 if (NumNonZero == 1) {
6969 // One half is zero or undef.
6970 unsigned Idx = countTrailingZeros(NonZeros);
6971 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6972 Op.getOperand(Idx));
6973 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6978 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6979 if (EVTBits == 8 && NumElems == 16) {
6980 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6982 if (V.getNode()) return V;
6985 if (EVTBits == 16 && NumElems == 8) {
6986 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6988 if (V.getNode()) return V;
6991 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6992 if (EVTBits == 32 && NumElems == 4) {
6993 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6994 NumZero, DAG, Subtarget, *this);
6999 // If element VT is == 32 bits, turn it into a number of shuffles.
7000 SmallVector<SDValue, 8> V(NumElems);
7001 if (NumElems == 4 && NumZero > 0) {
7002 for (unsigned i = 0; i < 4; ++i) {
7003 bool isZero = !(NonZeros & (1 << i));
7005 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7007 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7010 for (unsigned i = 0; i < 2; ++i) {
7011 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7014 V[i] = V[i*2]; // Must be a zero vector.
7017 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7020 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7023 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7028 bool Reverse1 = (NonZeros & 0x3) == 2;
7029 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7033 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7034 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7036 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7039 if (Values.size() > 1 && VT.is128BitVector()) {
7040 // Check for a build vector of consecutive loads.
7041 for (unsigned i = 0; i < NumElems; ++i)
7042 V[i] = Op.getOperand(i);
7044 // Check for elements which are consecutive loads.
7045 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7049 // Check for a build vector from mostly shuffle plus few inserting.
7050 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7054 // For SSE 4.1, use insertps to put the high elements into the low element.
7055 if (getSubtarget()->hasSSE41()) {
7057 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7058 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7060 Result = DAG.getUNDEF(VT);
7062 for (unsigned i = 1; i < NumElems; ++i) {
7063 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7064 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7065 Op.getOperand(i), DAG.getIntPtrConstant(i));
7070 // Otherwise, expand into a number of unpckl*, start by extending each of
7071 // our (non-undef) elements to the full vector width with the element in the
7072 // bottom slot of the vector (which generates no code for SSE).
7073 for (unsigned i = 0; i < NumElems; ++i) {
7074 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7075 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7077 V[i] = DAG.getUNDEF(VT);
7080 // Next, we iteratively mix elements, e.g. for v4f32:
7081 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7082 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7083 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7084 unsigned EltStride = NumElems >> 1;
7085 while (EltStride != 0) {
7086 for (unsigned i = 0; i < EltStride; ++i) {
7087 // If V[i+EltStride] is undef and this is the first round of mixing,
7088 // then it is safe to just drop this shuffle: V[i] is already in the
7089 // right place, the one element (since it's the first round) being
7090 // inserted as undef can be dropped. This isn't safe for successive
7091 // rounds because they will permute elements within both vectors.
7092 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7093 EltStride == NumElems/2)
7096 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7105 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7106 // to create 256-bit vectors from two other 128-bit ones.
7107 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7109 MVT ResVT = Op.getSimpleValueType();
7111 assert((ResVT.is256BitVector() ||
7112 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7114 SDValue V1 = Op.getOperand(0);
7115 SDValue V2 = Op.getOperand(1);
7116 unsigned NumElems = ResVT.getVectorNumElements();
7117 if(ResVT.is256BitVector())
7118 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7120 if (Op.getNumOperands() == 4) {
7121 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7122 ResVT.getVectorNumElements()/2);
7123 SDValue V3 = Op.getOperand(2);
7124 SDValue V4 = Op.getOperand(3);
7125 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7126 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7128 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7131 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7132 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7133 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7134 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7135 Op.getNumOperands() == 4)));
7137 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7138 // from two other 128-bit ones.
7140 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7141 return LowerAVXCONCAT_VECTORS(Op, DAG);
7145 //===----------------------------------------------------------------------===//
7146 // Vector shuffle lowering
7148 // This is an experimental code path for lowering vector shuffles on x86. It is
7149 // designed to handle arbitrary vector shuffles and blends, gracefully
7150 // degrading performance as necessary. It works hard to recognize idiomatic
7151 // shuffles and lower them to optimal instruction patterns without leaving
7152 // a framework that allows reasonably efficient handling of all vector shuffle
7154 //===----------------------------------------------------------------------===//
7156 /// \brief Tiny helper function to identify a no-op mask.
7158 /// This is a somewhat boring predicate function. It checks whether the mask
7159 /// array input, which is assumed to be a single-input shuffle mask of the kind
7160 /// used by the X86 shuffle instructions (not a fully general
7161 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7162 /// in-place shuffle are 'no-op's.
7163 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7164 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7165 if (Mask[i] != -1 && Mask[i] != i)
7170 /// \brief Helper function to classify a mask as a single-input mask.
7172 /// This isn't a generic single-input test because in the vector shuffle
7173 /// lowering we canonicalize single inputs to be the first input operand. This
7174 /// means we can more quickly test for a single input by only checking whether
7175 /// an input from the second operand exists. We also assume that the size of
7176 /// mask corresponds to the size of the input vectors which isn't true in the
7177 /// fully general case.
7178 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7180 if (M >= (int)Mask.size())
7185 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7186 // 2013 will allow us to use it as a non-type template parameter.
7189 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7191 /// See its documentation for details.
7192 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7193 if (Mask.size() != Args.size())
7195 for (int i = 0, e = Mask.size(); i < e; ++i) {
7196 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7197 assert(*Args[i] < (int)Args.size() * 2 &&
7198 "Argument outside the range of possible shuffle inputs!");
7199 if (Mask[i] != -1 && Mask[i] != *Args[i])
7207 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7210 /// This is a fast way to test a shuffle mask against a fixed pattern:
7212 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7214 /// It returns true if the mask is exactly as wide as the argument list, and
7215 /// each element of the mask is either -1 (signifying undef) or the value given
7216 /// in the argument.
7217 static const VariadicFunction1<
7218 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7220 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7222 /// This helper function produces an 8-bit shuffle immediate corresponding to
7223 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7224 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7227 /// NB: We rely heavily on "undef" masks preserving the input lane.
7228 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7229 SelectionDAG &DAG) {
7230 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7231 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7232 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7233 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7234 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7237 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7238 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7239 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7240 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7241 return DAG.getConstant(Imm, MVT::i8);
7244 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7246 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7247 /// support for floating point shuffles but not integer shuffles. These
7248 /// instructions will incur a domain crossing penalty on some chips though so
7249 /// it is better to avoid lowering through this for integer vectors where
7251 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7252 const X86Subtarget *Subtarget,
7253 SelectionDAG &DAG) {
7255 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7256 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7257 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7258 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7259 ArrayRef<int> Mask = SVOp->getMask();
7260 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7262 if (isSingleInputShuffleMask(Mask)) {
7263 // Straight shuffle of a single input vector. Simulate this by using the
7264 // single input as both of the "inputs" to this instruction..
7265 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7266 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7267 DAG.getConstant(SHUFPDMask, MVT::i8));
7269 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7270 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7272 // Use dedicated unpack instructions for masks that match their pattern.
7273 if (isShuffleEquivalent(Mask, 0, 2))
7274 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7275 if (isShuffleEquivalent(Mask, 1, 3))
7276 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7278 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7279 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7280 DAG.getConstant(SHUFPDMask, MVT::i8));
7283 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7285 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7286 /// the integer unit to minimize domain crossing penalties. However, for blends
7287 /// it falls back to the floating point shuffle operation with appropriate bit
7289 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7290 const X86Subtarget *Subtarget,
7291 SelectionDAG &DAG) {
7293 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7294 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7295 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7297 ArrayRef<int> Mask = SVOp->getMask();
7298 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7300 if (isSingleInputShuffleMask(Mask)) {
7301 // Straight shuffle of a single input vector. For everything from SSE2
7302 // onward this has a single fast instruction with no scary immediates.
7303 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7304 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7305 int WidenedMask[4] = {
7306 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7307 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7309 ISD::BITCAST, DL, MVT::v2i64,
7310 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7311 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7314 // Use dedicated unpack instructions for masks that match their pattern.
7315 if (isShuffleEquivalent(Mask, 0, 2))
7316 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7317 if (isShuffleEquivalent(Mask, 1, 3))
7318 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7320 // We implement this with SHUFPD which is pretty lame because it will likely
7321 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7322 // However, all the alternatives are still more cycles and newer chips don't
7323 // have this problem. It would be really nice if x86 had better shuffles here.
7324 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7325 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7326 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7327 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7330 /// \brief Lower 4-lane 32-bit floating point shuffles.
7332 /// Uses instructions exclusively from the floating point unit to minimize
7333 /// domain crossing penalties, as these are sufficient to implement all v4f32
7335 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7336 const X86Subtarget *Subtarget,
7337 SelectionDAG &DAG) {
7339 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7340 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7341 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7343 ArrayRef<int> Mask = SVOp->getMask();
7344 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7346 SDValue LowV = V1, HighV = V2;
7347 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7350 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7352 if (NumV2Elements == 0)
7353 // Straight shuffle of a single input vector. We pass the input vector to
7354 // both operands to simulate this with a SHUFPS.
7355 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7356 getV4X86ShuffleImm8ForMask(Mask, DAG));
7358 // Use dedicated unpack instructions for masks that match their pattern.
7359 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7360 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7361 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7362 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7364 if (NumV2Elements == 1) {
7366 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7368 // Compute the index adjacent to V2Index and in the same half by toggling
7370 int V2AdjIndex = V2Index ^ 1;
7372 if (Mask[V2AdjIndex] == -1) {
7373 // Handles all the cases where we have a single V2 element and an undef.
7374 // This will only ever happen in the high lanes because we commute the
7375 // vector otherwise.
7377 std::swap(LowV, HighV);
7378 NewMask[V2Index] -= 4;
7380 // Handle the case where the V2 element ends up adjacent to a V1 element.
7381 // To make this work, blend them together as the first step.
7382 int V1Index = V2AdjIndex;
7383 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7384 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7385 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7387 // Now proceed to reconstruct the final blend as we have the necessary
7388 // high or low half formed.
7395 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7396 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7398 } else if (NumV2Elements == 2) {
7399 if (Mask[0] < 4 && Mask[1] < 4) {
7400 // Handle the easy case where we have V1 in the low lanes and V2 in the
7401 // high lanes. We never see this reversed because we sort the shuffle.
7405 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7406 // trying to place elements directly, just blend them and set up the final
7407 // shuffle to place them.
7409 // The first two blend mask elements are for V1, the second two are for
7411 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7412 Mask[2] < 4 ? Mask[2] : Mask[3],
7413 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7414 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7415 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7416 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7418 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7421 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7422 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7423 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7424 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7427 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7428 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7431 /// \brief Lower 4-lane i32 vector shuffles.
7433 /// We try to handle these with integer-domain shuffles where we can, but for
7434 /// blends we use the floating point domain blend instructions.
7435 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7436 const X86Subtarget *Subtarget,
7437 SelectionDAG &DAG) {
7439 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7440 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7441 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7443 ArrayRef<int> Mask = SVOp->getMask();
7444 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7446 if (isSingleInputShuffleMask(Mask))
7447 // Straight shuffle of a single input vector. For everything from SSE2
7448 // onward this has a single fast instruction with no scary immediates.
7449 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7450 getV4X86ShuffleImm8ForMask(Mask, DAG));
7452 // Use dedicated unpack instructions for masks that match their pattern.
7453 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7454 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7455 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7456 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7458 // We implement this with SHUFPS because it can blend from two vectors.
7459 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7460 // up the inputs, bypassing domain shift penalties that we would encur if we
7461 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7463 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7464 DAG.getVectorShuffle(
7466 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7467 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7470 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7471 /// shuffle lowering, and the most complex part.
7473 /// The lowering strategy is to try to form pairs of input lanes which are
7474 /// targeted at the same half of the final vector, and then use a dword shuffle
7475 /// to place them onto the right half, and finally unpack the paired lanes into
7476 /// their final position.
7478 /// The exact breakdown of how to form these dword pairs and align them on the
7479 /// correct sides is really tricky. See the comments within the function for
7480 /// more of the details.
7481 static SDValue lowerV8I16SingleInputVectorShuffle(
7482 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7483 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7484 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7485 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7486 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7488 SmallVector<int, 4> LoInputs;
7489 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7490 [](int M) { return M >= 0; });
7491 std::sort(LoInputs.begin(), LoInputs.end());
7492 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7493 SmallVector<int, 4> HiInputs;
7494 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7495 [](int M) { return M >= 0; });
7496 std::sort(HiInputs.begin(), HiInputs.end());
7497 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7499 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7500 int NumHToL = LoInputs.size() - NumLToL;
7502 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7503 int NumHToH = HiInputs.size() - NumLToH;
7504 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7505 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7506 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7507 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7509 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7510 // such inputs we can swap two of the dwords across the half mark and end up
7511 // with <=2 inputs to each half in each half. Once there, we can fall through
7512 // to the generic code below. For example:
7514 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7515 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7517 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7518 // and an existing 2-into-2 on the other half. In this case we may have to
7519 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7520 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7521 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7522 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7523 // half than the one we target for fixing) will be fixed when we re-enter this
7524 // path. We will also combine away any sequence of PSHUFD instructions that
7525 // result into a single instruction. Here is an example of the tricky case:
7527 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7528 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7530 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7532 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7533 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7535 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7536 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7538 // The result is fine to be handled by the generic logic.
7539 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7540 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7541 int AOffset, int BOffset) {
7542 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7543 "Must call this with A having 3 or 1 inputs from the A half.");
7544 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7545 "Must call this with B having 1 or 3 inputs from the B half.");
7546 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7547 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7549 // Compute the index of dword with only one word among the three inputs in
7550 // a half by taking the sum of the half with three inputs and subtracting
7551 // the sum of the actual three inputs. The difference is the remaining
7554 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7555 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7556 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7557 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7558 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7559 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7560 int TripleNonInputIdx =
7561 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7562 TripleDWord = TripleNonInputIdx / 2;
7564 // We use xor with one to compute the adjacent DWord to whichever one the
7566 OneInputDWord = (OneInput / 2) ^ 1;
7568 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7569 // and BToA inputs. If there is also such a problem with the BToB and AToB
7570 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7571 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7572 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7573 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7574 // Compute how many inputs will be flipped by swapping these DWords. We
7576 // to balance this to ensure we don't form a 3-1 shuffle in the other
7578 int NumFlippedAToBInputs =
7579 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7580 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7581 int NumFlippedBToBInputs =
7582 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7583 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7584 if ((NumFlippedAToBInputs == 1 &&
7585 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7586 (NumFlippedBToBInputs == 1 &&
7587 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7588 // We choose whether to fix the A half or B half based on whether that
7589 // half has zero flipped inputs. At zero, we may not be able to fix it
7590 // with that half. We also bias towards fixing the B half because that
7591 // will more commonly be the high half, and we have to bias one way.
7592 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7593 ArrayRef<int> Inputs) {
7594 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7595 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7596 PinnedIdx ^ 1) != Inputs.end();
7597 // Determine whether the free index is in the flipped dword or the
7598 // unflipped dword based on where the pinned index is. We use this bit
7599 // in an xor to conditionally select the adjacent dword.
7600 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7601 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7602 FixFreeIdx) != Inputs.end();
7603 if (IsFixIdxInput == IsFixFreeIdxInput)
7605 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7606 FixFreeIdx) != Inputs.end();
7607 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7608 "We need to be changing the number of flipped inputs!");
7609 int PSHUFHalfMask[] = {0, 1, 2, 3};
7610 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7611 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7613 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7616 if (M != -1 && M == FixIdx)
7618 else if (M != -1 && M == FixFreeIdx)
7621 if (NumFlippedBToBInputs != 0) {
7623 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7624 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7626 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7628 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7629 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7634 int PSHUFDMask[] = {0, 1, 2, 3};
7635 PSHUFDMask[ADWord] = BDWord;
7636 PSHUFDMask[BDWord] = ADWord;
7637 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7638 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7639 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7640 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7642 // Adjust the mask to match the new locations of A and B.
7644 if (M != -1 && M/2 == ADWord)
7645 M = 2 * BDWord + M % 2;
7646 else if (M != -1 && M/2 == BDWord)
7647 M = 2 * ADWord + M % 2;
7649 // Recurse back into this routine to re-compute state now that this isn't
7650 // a 3 and 1 problem.
7651 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7654 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7655 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7656 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7657 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7659 // At this point there are at most two inputs to the low and high halves from
7660 // each half. That means the inputs can always be grouped into dwords and
7661 // those dwords can then be moved to the correct half with a dword shuffle.
7662 // We use at most one low and one high word shuffle to collect these paired
7663 // inputs into dwords, and finally a dword shuffle to place them.
7664 int PSHUFLMask[4] = {-1, -1, -1, -1};
7665 int PSHUFHMask[4] = {-1, -1, -1, -1};
7666 int PSHUFDMask[4] = {-1, -1, -1, -1};
7668 // First fix the masks for all the inputs that are staying in their
7669 // original halves. This will then dictate the targets of the cross-half
7671 auto fixInPlaceInputs =
7672 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7673 MutableArrayRef<int> SourceHalfMask,
7674 MutableArrayRef<int> HalfMask, int HalfOffset) {
7675 if (InPlaceInputs.empty())
7677 if (InPlaceInputs.size() == 1) {
7678 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7679 InPlaceInputs[0] - HalfOffset;
7680 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7683 if (IncomingInputs.empty()) {
7684 // Just fix all of the in place inputs.
7685 for (int Input : InPlaceInputs) {
7686 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7687 PSHUFDMask[Input / 2] = Input / 2;
7692 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7693 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7694 InPlaceInputs[0] - HalfOffset;
7695 // Put the second input next to the first so that they are packed into
7696 // a dword. We find the adjacent index by toggling the low bit.
7697 int AdjIndex = InPlaceInputs[0] ^ 1;
7698 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7699 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7700 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7702 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7703 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7705 // Now gather the cross-half inputs and place them into a free dword of
7706 // their target half.
7707 // FIXME: This operation could almost certainly be simplified dramatically to
7708 // look more like the 3-1 fixing operation.
7709 auto moveInputsToRightHalf = [&PSHUFDMask](
7710 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7711 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7712 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7714 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7715 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7717 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7719 int LowWord = Word & ~1;
7720 int HighWord = Word | 1;
7721 return isWordClobbered(SourceHalfMask, LowWord) ||
7722 isWordClobbered(SourceHalfMask, HighWord);
7725 if (IncomingInputs.empty())
7728 if (ExistingInputs.empty()) {
7729 // Map any dwords with inputs from them into the right half.
7730 for (int Input : IncomingInputs) {
7731 // If the source half mask maps over the inputs, turn those into
7732 // swaps and use the swapped lane.
7733 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7734 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7735 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7736 Input - SourceOffset;
7737 // We have to swap the uses in our half mask in one sweep.
7738 for (int &M : HalfMask)
7739 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7741 else if (M == Input)
7742 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7744 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7745 Input - SourceOffset &&
7746 "Previous placement doesn't match!");
7748 // Note that this correctly re-maps both when we do a swap and when
7749 // we observe the other side of the swap above. We rely on that to
7750 // avoid swapping the members of the input list directly.
7751 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7754 // Map the input's dword into the correct half.
7755 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7756 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7758 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7760 "Previous placement doesn't match!");
7763 // And just directly shift any other-half mask elements to be same-half
7764 // as we will have mirrored the dword containing the element into the
7765 // same position within that half.
7766 for (int &M : HalfMask)
7767 if (M >= SourceOffset && M < SourceOffset + 4) {
7768 M = M - SourceOffset + DestOffset;
7769 assert(M >= 0 && "This should never wrap below zero!");
7774 // Ensure we have the input in a viable dword of its current half. This
7775 // is particularly tricky because the original position may be clobbered
7776 // by inputs being moved and *staying* in that half.
7777 if (IncomingInputs.size() == 1) {
7778 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7779 int InputFixed = std::find(std::begin(SourceHalfMask),
7780 std::end(SourceHalfMask), -1) -
7781 std::begin(SourceHalfMask) + SourceOffset;
7782 SourceHalfMask[InputFixed - SourceOffset] =
7783 IncomingInputs[0] - SourceOffset;
7784 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7786 IncomingInputs[0] = InputFixed;
7788 } else if (IncomingInputs.size() == 2) {
7789 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7790 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7791 // We have two non-adjacent or clobbered inputs we need to extract from
7792 // the source half. To do this, we need to map them into some adjacent
7793 // dword slot in the source mask.
7794 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7795 IncomingInputs[1] - SourceOffset};
7797 // If there is a free slot in the source half mask adjacent to one of
7798 // the inputs, place the other input in it. We use (Index XOR 1) to
7799 // compute an adjacent index.
7800 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7801 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7802 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7803 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7804 InputsFixed[1] = InputsFixed[0] ^ 1;
7805 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7806 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7807 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7808 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7809 InputsFixed[0] = InputsFixed[1] ^ 1;
7810 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7811 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7812 // The two inputs are in the same DWord but it is clobbered and the
7813 // adjacent DWord isn't used at all. Move both inputs to the free
7815 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7816 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7817 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7818 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7820 // The only way we hit this point is if there is no clobbering
7821 // (because there are no off-half inputs to this half) and there is no
7822 // free slot adjacent to one of the inputs. In this case, we have to
7823 // swap an input with a non-input.
7824 for (int i = 0; i < 4; ++i)
7825 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7826 "We can't handle any clobbers here!");
7827 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7828 "Cannot have adjacent inputs here!");
7830 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7831 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7833 // We also have to update the final source mask in this case because
7834 // it may need to undo the above swap.
7835 for (int &M : FinalSourceHalfMask)
7836 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7837 M = InputsFixed[1] + SourceOffset;
7838 else if (M == InputsFixed[1] + SourceOffset)
7839 M = (InputsFixed[0] ^ 1) + SourceOffset;
7841 InputsFixed[1] = InputsFixed[0] ^ 1;
7844 // Point everything at the fixed inputs.
7845 for (int &M : HalfMask)
7846 if (M == IncomingInputs[0])
7847 M = InputsFixed[0] + SourceOffset;
7848 else if (M == IncomingInputs[1])
7849 M = InputsFixed[1] + SourceOffset;
7851 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7852 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7855 llvm_unreachable("Unhandled input size!");
7858 // Now hoist the DWord down to the right half.
7859 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7860 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7861 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7862 for (int &M : HalfMask)
7863 for (int Input : IncomingInputs)
7865 M = FreeDWord * 2 + Input % 2;
7867 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7868 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7869 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7870 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7872 // Now enact all the shuffles we've computed to move the inputs into their
7874 if (!isNoopShuffleMask(PSHUFLMask))
7875 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7876 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7877 if (!isNoopShuffleMask(PSHUFHMask))
7878 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7879 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7880 if (!isNoopShuffleMask(PSHUFDMask))
7881 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7882 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7883 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7884 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7886 // At this point, each half should contain all its inputs, and we can then
7887 // just shuffle them into their final position.
7888 assert(std::count_if(LoMask.begin(), LoMask.end(),
7889 [](int M) { return M >= 4; }) == 0 &&
7890 "Failed to lift all the high half inputs to the low mask!");
7891 assert(std::count_if(HiMask.begin(), HiMask.end(),
7892 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7893 "Failed to lift all the low half inputs to the high mask!");
7895 // Do a half shuffle for the low mask.
7896 if (!isNoopShuffleMask(LoMask))
7897 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7898 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7900 // Do a half shuffle with the high mask after shifting its values down.
7901 for (int &M : HiMask)
7904 if (!isNoopShuffleMask(HiMask))
7905 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7906 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7911 /// \brief Detect whether the mask pattern should be lowered through
7914 /// This essentially tests whether viewing the mask as an interleaving of two
7915 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7916 /// lowering it through interleaving is a significantly better strategy.
7917 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7918 int NumEvenInputs[2] = {0, 0};
7919 int NumOddInputs[2] = {0, 0};
7920 int NumLoInputs[2] = {0, 0};
7921 int NumHiInputs[2] = {0, 0};
7922 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7926 int InputIdx = Mask[i] >= Size;
7929 ++NumLoInputs[InputIdx];
7931 ++NumHiInputs[InputIdx];
7934 ++NumEvenInputs[InputIdx];
7936 ++NumOddInputs[InputIdx];
7939 // The minimum number of cross-input results for both the interleaved and
7940 // split cases. If interleaving results in fewer cross-input results, return
7942 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7943 NumEvenInputs[0] + NumOddInputs[1]);
7944 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7945 NumLoInputs[0] + NumHiInputs[1]);
7946 return InterleavedCrosses < SplitCrosses;
7949 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7951 /// This strategy only works when the inputs from each vector fit into a single
7952 /// half of that vector, and generally there are not so many inputs as to leave
7953 /// the in-place shuffles required highly constrained (and thus expensive). It
7954 /// shifts all the inputs into a single side of both input vectors and then
7955 /// uses an unpack to interleave these inputs in a single vector. At that
7956 /// point, we will fall back on the generic single input shuffle lowering.
7957 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7959 MutableArrayRef<int> Mask,
7960 const X86Subtarget *Subtarget,
7961 SelectionDAG &DAG) {
7962 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7963 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7964 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7965 for (int i = 0; i < 8; ++i)
7966 if (Mask[i] >= 0 && Mask[i] < 4)
7967 LoV1Inputs.push_back(i);
7968 else if (Mask[i] >= 4 && Mask[i] < 8)
7969 HiV1Inputs.push_back(i);
7970 else if (Mask[i] >= 8 && Mask[i] < 12)
7971 LoV2Inputs.push_back(i);
7972 else if (Mask[i] >= 12)
7973 HiV2Inputs.push_back(i);
7975 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7976 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7979 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7980 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7981 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7983 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7984 HiV1Inputs.size() + HiV2Inputs.size();
7986 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7987 ArrayRef<int> HiInputs, bool MoveToLo,
7989 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7990 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7991 if (BadInputs.empty())
7994 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7995 int MoveOffset = MoveToLo ? 0 : 4;
7997 if (GoodInputs.empty()) {
7998 for (int BadInput : BadInputs) {
7999 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8000 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8003 if (GoodInputs.size() == 2) {
8004 // If the low inputs are spread across two dwords, pack them into
8006 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8007 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8008 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8009 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8011 // Otherwise pin the good inputs.
8012 for (int GoodInput : GoodInputs)
8013 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8016 if (BadInputs.size() == 2) {
8017 // If we have two bad inputs then there may be either one or two good
8018 // inputs fixed in place. Find a fixed input, and then find the *other*
8019 // two adjacent indices by using modular arithmetic.
8021 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8022 [](int M) { return M >= 0; }) -
8023 std::begin(MoveMask);
8025 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8026 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8027 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8028 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8029 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8030 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8031 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8033 assert(BadInputs.size() == 1 && "All sizes handled");
8034 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8035 std::end(MoveMask), -1) -
8036 std::begin(MoveMask);
8037 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8038 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8042 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8045 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8047 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8050 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8051 // cross-half traffic in the final shuffle.
8053 // Munge the mask to be a single-input mask after the unpack merges the
8057 M = 2 * (M % 4) + (M / 8);
8059 return DAG.getVectorShuffle(
8060 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8061 DL, MVT::v8i16, V1, V2),
8062 DAG.getUNDEF(MVT::v8i16), Mask);
8065 /// \brief Generic lowering of 8-lane i16 shuffles.
8067 /// This handles both single-input shuffles and combined shuffle/blends with
8068 /// two inputs. The single input shuffles are immediately delegated to
8069 /// a dedicated lowering routine.
8071 /// The blends are lowered in one of three fundamental ways. If there are few
8072 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8073 /// of the input is significantly cheaper when lowered as an interleaving of
8074 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8075 /// halves of the inputs separately (making them have relatively few inputs)
8076 /// and then concatenate them.
8077 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8078 const X86Subtarget *Subtarget,
8079 SelectionDAG &DAG) {
8081 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8082 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8083 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8085 ArrayRef<int> OrigMask = SVOp->getMask();
8086 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8087 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8088 MutableArrayRef<int> Mask(MaskStorage);
8090 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8092 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8093 auto isV2 = [](int M) { return M >= 8; };
8095 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8096 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8098 if (NumV2Inputs == 0)
8099 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8101 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8102 "to be V1-input shuffles.");
8104 if (NumV1Inputs + NumV2Inputs <= 4)
8105 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8107 // Check whether an interleaving lowering is likely to be more efficient.
8108 // This isn't perfect but it is a strong heuristic that tends to work well on
8109 // the kinds of shuffles that show up in practice.
8111 // FIXME: Handle 1x, 2x, and 4x interleaving.
8112 if (shouldLowerAsInterleaving(Mask)) {
8113 // FIXME: Figure out whether we should pack these into the low or high
8116 int EMask[8], OMask[8];
8117 for (int i = 0; i < 4; ++i) {
8118 EMask[i] = Mask[2*i];
8119 OMask[i] = Mask[2*i + 1];
8124 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8125 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8130 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8131 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8133 for (int i = 0; i < 4; ++i) {
8134 LoBlendMask[i] = Mask[i];
8135 HiBlendMask[i] = Mask[i + 4];
8138 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8139 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8140 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8141 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8143 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8144 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8147 /// \brief Check whether a compaction lowering can be done by dropping even
8148 /// elements and compute how many times even elements must be dropped.
8150 /// This handles shuffles which take every Nth element where N is a power of
8151 /// two. Example shuffle masks:
8153 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8154 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8155 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8156 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8157 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8158 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8160 /// Any of these lanes can of course be undef.
8162 /// This routine only supports N <= 3.
8163 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8166 /// \returns N above, or the number of times even elements must be dropped if
8167 /// there is such a number. Otherwise returns zero.
8168 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8169 // Figure out whether we're looping over two inputs or just one.
8170 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8172 // The modulus for the shuffle vector entries is based on whether this is
8173 // a single input or not.
8174 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8175 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8176 "We should only be called with masks with a power-of-2 size!");
8178 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8180 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8181 // and 2^3 simultaneously. This is because we may have ambiguity with
8182 // partially undef inputs.
8183 bool ViableForN[3] = {true, true, true};
8185 for (int i = 0, e = Mask.size(); i < e; ++i) {
8186 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8191 bool IsAnyViable = false;
8192 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8193 if (ViableForN[j]) {
8196 // The shuffle mask must be equal to (i * 2^N) % M.
8197 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8200 ViableForN[j] = false;
8202 // Early exit if we exhaust the possible powers of two.
8207 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8211 // Return 0 as there is no viable power of two.
8215 /// \brief Generic lowering of v16i8 shuffles.
8217 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8218 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8219 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8220 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8222 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8223 const X86Subtarget *Subtarget,
8224 SelectionDAG &DAG) {
8226 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8227 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8228 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8229 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8230 ArrayRef<int> OrigMask = SVOp->getMask();
8231 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8232 int MaskStorage[16] = {
8233 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8234 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8235 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8236 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8237 MutableArrayRef<int> Mask(MaskStorage);
8238 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8239 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8241 // For single-input shuffles, there are some nicer lowering tricks we can use.
8242 if (isSingleInputShuffleMask(Mask)) {
8243 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8244 // Notably, this handles splat and partial-splat shuffles more efficiently.
8245 // However, it only makes sense if the pre-duplication shuffle simplifies
8246 // things significantly. Currently, this means we need to be able to
8247 // express the pre-duplication shuffle as an i16 shuffle.
8249 // FIXME: We should check for other patterns which can be widened into an
8250 // i16 shuffle as well.
8251 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8252 for (int i = 0; i < 16; i += 2) {
8253 if (Mask[i] != Mask[i + 1])
8258 auto tryToWidenViaDuplication = [&]() -> SDValue {
8259 if (!canWidenViaDuplication(Mask))
8261 SmallVector<int, 4> LoInputs;
8262 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8263 [](int M) { return M >= 0 && M < 8; });
8264 std::sort(LoInputs.begin(), LoInputs.end());
8265 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8267 SmallVector<int, 4> HiInputs;
8268 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8269 [](int M) { return M >= 8; });
8270 std::sort(HiInputs.begin(), HiInputs.end());
8271 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8274 bool TargetLo = LoInputs.size() >= HiInputs.size();
8275 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8276 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8278 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8279 SmallDenseMap<int, int, 8> LaneMap;
8280 for (int I : InPlaceInputs) {
8281 PreDupI16Shuffle[I/2] = I/2;
8284 int j = TargetLo ? 0 : 4, je = j + 4;
8285 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8286 // Check if j is already a shuffle of this input. This happens when
8287 // there are two adjacent bytes after we move the low one.
8288 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8289 // If we haven't yet mapped the input, search for a slot into which
8291 while (j < je && PreDupI16Shuffle[j] != -1)
8295 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8298 // Map this input with the i16 shuffle.
8299 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8302 // Update the lane map based on the mapping we ended up with.
8303 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8306 ISD::BITCAST, DL, MVT::v16i8,
8307 DAG.getVectorShuffle(MVT::v8i16, DL,
8308 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8309 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8311 // Unpack the bytes to form the i16s that will be shuffled into place.
8312 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8313 MVT::v16i8, V1, V1);
8315 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8316 for (int i = 0; i < 16; i += 2) {
8318 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8319 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8322 ISD::BITCAST, DL, MVT::v16i8,
8323 DAG.getVectorShuffle(MVT::v8i16, DL,
8324 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8325 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8327 if (SDValue V = tryToWidenViaDuplication())
8331 // Check whether an interleaving lowering is likely to be more efficient.
8332 // This isn't perfect but it is a strong heuristic that tends to work well on
8333 // the kinds of shuffles that show up in practice.
8335 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8336 if (shouldLowerAsInterleaving(Mask)) {
8337 // FIXME: Figure out whether we should pack these into the low or high
8340 int EMask[16], OMask[16];
8341 for (int i = 0; i < 8; ++i) {
8342 EMask[i] = Mask[2*i];
8343 OMask[i] = Mask[2*i + 1];
8348 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8349 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8351 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8354 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8355 // with PSHUFB. It is important to do this before we attempt to generate any
8356 // blends but after all of the single-input lowerings. If the single input
8357 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8358 // want to preserve that and we can DAG combine any longer sequences into
8359 // a PSHUFB in the end. But once we start blending from multiple inputs,
8360 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8361 // and there are *very* few patterns that would actually be faster than the
8362 // PSHUFB approach because of its ability to zero lanes.
8364 // FIXME: The only exceptions to the above are blends which are exact
8365 // interleavings with direct instructions supporting them. We currently don't
8366 // handle those well here.
8367 if (Subtarget->hasSSSE3()) {
8370 for (int i = 0; i < 16; ++i)
8371 if (Mask[i] == -1) {
8372 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8374 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8376 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8378 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8379 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8380 if (isSingleInputShuffleMask(Mask))
8381 return V1; // Single inputs are easy.
8383 // Otherwise, blend the two.
8384 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8385 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8386 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8389 // Check whether a compaction lowering can be done. This handles shuffles
8390 // which take every Nth element for some even N. See the helper function for
8393 // We special case these as they can be particularly efficiently handled with
8394 // the PACKUSB instruction on x86 and they show up in common patterns of
8395 // rearranging bytes to truncate wide elements.
8396 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8397 // NumEvenDrops is the power of two stride of the elements. Another way of
8398 // thinking about it is that we need to drop the even elements this many
8399 // times to get the original input.
8400 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8402 // First we need to zero all the dropped bytes.
8403 assert(NumEvenDrops <= 3 &&
8404 "No support for dropping even elements more than 3 times.");
8405 // We use the mask type to pick which bytes are preserved based on how many
8406 // elements are dropped.
8407 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8408 SDValue ByteClearMask =
8409 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8410 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8411 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8413 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8415 // Now pack things back together.
8416 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8417 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8418 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8419 for (int i = 1; i < NumEvenDrops; ++i) {
8420 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8421 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8427 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8428 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8429 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8430 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8432 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8433 MutableArrayRef<int> V1HalfBlendMask,
8434 MutableArrayRef<int> V2HalfBlendMask) {
8435 for (int i = 0; i < 8; ++i)
8436 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8437 V1HalfBlendMask[i] = HalfMask[i];
8439 } else if (HalfMask[i] >= 16) {
8440 V2HalfBlendMask[i] = HalfMask[i] - 16;
8441 HalfMask[i] = i + 8;
8444 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8445 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8447 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8449 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8450 MutableArrayRef<int> HiBlendMask) {
8452 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8453 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8455 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8456 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8457 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8458 [](int M) { return M >= 0 && M % 2 == 1; })) {
8459 // Use a mask to drop the high bytes.
8460 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8461 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8462 DAG.getConstant(0x00FF, MVT::v8i16));
8464 // This will be a single vector shuffle instead of a blend so nuke V2.
8465 V2 = DAG.getUNDEF(MVT::v8i16);
8467 // Squash the masks to point directly into V1.
8468 for (int &M : LoBlendMask)
8471 for (int &M : HiBlendMask)
8475 // Otherwise just unpack the low half of V into V1 and the high half into
8476 // V2 so that we can blend them as i16s.
8477 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8478 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8479 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8480 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8483 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8484 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8485 return std::make_pair(BlendedLo, BlendedHi);
8487 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8488 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8489 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8491 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8492 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8494 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8497 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8499 /// This routine breaks down the specific type of 128-bit shuffle and
8500 /// dispatches to the lowering routines accordingly.
8501 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8502 MVT VT, const X86Subtarget *Subtarget,
8503 SelectionDAG &DAG) {
8504 switch (VT.SimpleTy) {
8506 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8508 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8510 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8512 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8514 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8516 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8519 llvm_unreachable("Unimplemented!");
8523 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
8524 int Size = Mask.size();
8525 for (int M : Mask.slice(0, Size / 2))
8526 if (M >= 0 && (M % Size) >= Size / 2)
8528 for (int M : Mask.slice(Size / 2, Size / 2))
8529 if (M >= 0 && (M % Size) < Size / 2)
8534 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8537 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8538 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8539 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8540 /// we encode the logic here for specific shuffle lowering routines to bail to
8541 /// when they exhaust the features avaible to more directly handle the shuffle.
8542 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8544 const X86Subtarget *Subtarget,
8545 SelectionDAG &DAG) {
8547 MVT VT = Op.getSimpleValueType();
8548 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8549 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8550 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8551 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8552 ArrayRef<int> Mask = SVOp->getMask();
8554 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8555 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8557 int NumElements = VT.getVectorNumElements();
8558 int SplitNumElements = NumElements / 2;
8559 MVT ScalarVT = VT.getScalarType();
8560 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8562 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8563 DAG.getIntPtrConstant(0));
8564 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8565 DAG.getIntPtrConstant(SplitNumElements));
8566 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8567 DAG.getIntPtrConstant(0));
8568 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8569 DAG.getIntPtrConstant(SplitNumElements));
8571 // Now create two 4-way blends of these half-width vectors.
8572 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8573 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8574 for (int i = 0; i < SplitNumElements; ++i) {
8575 int M = HalfMask[i];
8576 if (M >= NumElements) {
8577 V2BlendMask.push_back(M - NumElements);
8578 V1BlendMask.push_back(-1);
8579 BlendMask.push_back(SplitNumElements + i);
8580 } else if (M >= 0) {
8581 V2BlendMask.push_back(-1);
8582 V1BlendMask.push_back(M);
8583 BlendMask.push_back(i);
8585 V2BlendMask.push_back(-1);
8586 V1BlendMask.push_back(-1);
8587 BlendMask.push_back(-1);
8590 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8591 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8592 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8594 SDValue Lo = HalfBlend(LoMask);
8595 SDValue Hi = HalfBlend(HiMask);
8596 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8599 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
8601 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
8602 /// isn't available.
8603 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8604 const X86Subtarget *Subtarget,
8605 SelectionDAG &DAG) {
8607 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8608 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8610 ArrayRef<int> Mask = SVOp->getMask();
8611 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8613 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8614 // shuffles aren't a problem and FP and int have the same patterns.
8616 // FIXME: We can handle these more cleverly than splitting for v4f64.
8617 if (isHalfCrossingShuffleMask(Mask))
8618 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8620 if (isSingleInputShuffleMask(Mask)) {
8621 // Non-half-crossing single input shuffles can be lowerid with an
8622 // interleaved permutation.
8623 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
8624 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
8625 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
8626 DAG.getConstant(VPERMILPMask, MVT::i8));
8629 // X86 has dedicated unpack instructions that can handle specific blend
8630 // operations: UNPCKH and UNPCKL.
8631 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
8632 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
8633 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
8634 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
8635 // FIXME: It would be nice to find a way to get canonicalization to commute
8637 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
8638 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
8639 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
8640 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
8642 // Check if the blend happens to exactly fit that of SHUFPD.
8643 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
8644 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
8645 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
8646 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
8647 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
8648 DAG.getConstant(SHUFPDMask, MVT::i8));
8650 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
8651 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
8652 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
8653 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
8654 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
8655 DAG.getConstant(SHUFPDMask, MVT::i8));
8658 // Shuffle the input elements into the desired positions in V1 and V2 and
8659 // blend them together.
8660 int V1Mask[] = {-1, -1, -1, -1};
8661 int V2Mask[] = {-1, -1, -1, -1};
8662 for (int i = 0; i < 4; ++i)
8663 if (Mask[i] >= 0 && Mask[i] < 4)
8664 V1Mask[i] = Mask[i];
8665 else if (Mask[i] >= 4)
8666 V2Mask[i] = Mask[i] - 4;
8668 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
8669 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
8671 unsigned BlendMask = 0;
8672 for (int i = 0; i < 4; ++i)
8674 BlendMask |= 1 << i;
8676 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
8677 DAG.getConstant(BlendMask, MVT::i8));
8680 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
8682 /// Largely delegates to common code when we have AVX2 and to the floating-point
8683 /// code when we only have AVX.
8684 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8685 const X86Subtarget *Subtarget,
8686 SelectionDAG &DAG) {
8688 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
8689 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8690 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8692 ArrayRef<int> Mask = SVOp->getMask();
8693 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8695 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8696 // shuffles aren't a problem and FP and int have the same patterns.
8698 if (isHalfCrossingShuffleMask(Mask))
8699 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8701 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
8702 // delegate to floating point code.
8703 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
8704 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
8705 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
8706 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
8709 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8711 /// This routine either breaks down the specific type of a 256-bit x86 vector
8712 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8713 /// together based on the available instructions.
8714 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8715 MVT VT, const X86Subtarget *Subtarget,
8716 SelectionDAG &DAG) {
8717 switch (VT.SimpleTy) {
8719 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8721 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8726 // Fall back to the basic pattern of extracting the high half and forming
8728 // FIXME: Add targeted lowering for each type that can document rationale
8729 // for delegating to this when necessary.
8730 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8733 llvm_unreachable("Not a valid 256-bit x86 vector type!");
8737 /// \brief Tiny helper function to test whether a shuffle mask could be
8738 /// simplified by widening the elements being shuffled.
8739 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8740 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8741 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8747 /// \brief Top-level lowering for x86 vector shuffles.
8749 /// This handles decomposition, canonicalization, and lowering of all x86
8750 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8751 /// above in helper routines. The canonicalization attempts to widen shuffles
8752 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8753 /// s.t. only one of the two inputs needs to be tested, etc.
8754 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8755 SelectionDAG &DAG) {
8756 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8757 ArrayRef<int> Mask = SVOp->getMask();
8758 SDValue V1 = Op.getOperand(0);
8759 SDValue V2 = Op.getOperand(1);
8760 MVT VT = Op.getSimpleValueType();
8761 int NumElements = VT.getVectorNumElements();
8764 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8766 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8767 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8768 if (V1IsUndef && V2IsUndef)
8769 return DAG.getUNDEF(VT);
8771 // When we create a shuffle node we put the UNDEF node to second operand,
8772 // but in some cases the first operand may be transformed to UNDEF.
8773 // In this case we should just commute the node.
8775 return DAG.getCommutedVectorShuffle(*SVOp);
8777 // Check for non-undef masks pointing at an undef vector and make the masks
8778 // undef as well. This makes it easier to match the shuffle based solely on
8782 if (M >= NumElements) {
8783 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8784 for (int &M : NewMask)
8785 if (M >= NumElements)
8787 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8790 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8791 // lanes but wider integers. We cap this to not form integers larger than i64
8792 // but it might be interesting to form i128 integers to handle flipping the
8793 // low and high halves of AVX 256-bit vectors.
8794 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8795 canWidenShuffleElements(Mask)) {
8796 SmallVector<int, 8> NewMask;
8797 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8798 NewMask.push_back(Mask[i] / 2);
8800 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8801 VT.getVectorNumElements() / 2);
8802 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8803 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8804 return DAG.getNode(ISD::BITCAST, dl, VT,
8805 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8808 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8809 for (int M : SVOp->getMask())
8812 else if (M < NumElements)
8817 // Commute the shuffle as needed such that more elements come from V1 than
8818 // V2. This allows us to match the shuffle pattern strictly on how many
8819 // elements come from V1 without handling the symmetric cases.
8820 if (NumV2Elements > NumV1Elements)
8821 return DAG.getCommutedVectorShuffle(*SVOp);
8823 // When the number of V1 and V2 elements are the same, try to minimize the
8824 // number of uses of V2 in the low half of the vector.
8825 if (NumV1Elements == NumV2Elements) {
8826 int LowV1Elements = 0, LowV2Elements = 0;
8827 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8828 if (M >= NumElements)
8832 if (LowV2Elements > LowV1Elements)
8833 return DAG.getCommutedVectorShuffle(*SVOp);
8836 // For each vector width, delegate to a specialized lowering routine.
8837 if (VT.getSizeInBits() == 128)
8838 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8840 if (VT.getSizeInBits() == 256)
8841 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8843 llvm_unreachable("Unimplemented!");
8847 //===----------------------------------------------------------------------===//
8848 // Legacy vector shuffle lowering
8850 // This code is the legacy code handling vector shuffles until the above
8851 // replaces its functionality and performance.
8852 //===----------------------------------------------------------------------===//
8854 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8855 bool hasInt256, unsigned *MaskOut = nullptr) {
8856 MVT EltVT = VT.getVectorElementType();
8858 // There is no blend with immediate in AVX-512.
8859 if (VT.is512BitVector())
8862 if (!hasSSE41 || EltVT == MVT::i8)
8864 if (!hasInt256 && VT == MVT::v16i16)
8867 unsigned MaskValue = 0;
8868 unsigned NumElems = VT.getVectorNumElements();
8869 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8870 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8871 unsigned NumElemsInLane = NumElems / NumLanes;
8873 // Blend for v16i16 should be symetric for the both lanes.
8874 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8876 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8877 int EltIdx = MaskVals[i];
8879 if ((EltIdx < 0 || EltIdx == (int)i) &&
8880 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8883 if (((unsigned)EltIdx == (i + NumElems)) &&
8884 (SndLaneEltIdx < 0 ||
8885 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8886 MaskValue |= (1 << i);
8892 *MaskOut = MaskValue;
8896 // Try to lower a shuffle node into a simple blend instruction.
8897 // This function assumes isBlendMask returns true for this
8898 // SuffleVectorSDNode
8899 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8901 const X86Subtarget *Subtarget,
8902 SelectionDAG &DAG) {
8903 MVT VT = SVOp->getSimpleValueType(0);
8904 MVT EltVT = VT.getVectorElementType();
8905 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8906 Subtarget->hasInt256() && "Trying to lower a "
8907 "VECTOR_SHUFFLE to a Blend but "
8908 "with the wrong mask"));
8909 SDValue V1 = SVOp->getOperand(0);
8910 SDValue V2 = SVOp->getOperand(1);
8912 unsigned NumElems = VT.getVectorNumElements();
8914 // Convert i32 vectors to floating point if it is not AVX2.
8915 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8917 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8918 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8920 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8921 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8924 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8925 DAG.getConstant(MaskValue, MVT::i32));
8926 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8929 /// In vector type \p VT, return true if the element at index \p InputIdx
8930 /// falls on a different 128-bit lane than \p OutputIdx.
8931 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8932 unsigned OutputIdx) {
8933 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8934 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8937 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8938 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8939 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8940 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8942 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8943 SelectionDAG &DAG) {
8944 MVT VT = V1.getSimpleValueType();
8945 assert(VT.is128BitVector() || VT.is256BitVector());
8947 MVT EltVT = VT.getVectorElementType();
8948 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8949 unsigned NumElts = VT.getVectorNumElements();
8951 SmallVector<SDValue, 32> PshufbMask;
8952 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8953 int InputIdx = MaskVals[OutputIdx];
8954 unsigned InputByteIdx;
8956 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8957 InputByteIdx = 0x80;
8959 // Cross lane is not allowed.
8960 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8962 InputByteIdx = InputIdx * EltSizeInBytes;
8963 // Index is an byte offset within the 128-bit lane.
8964 InputByteIdx &= 0xf;
8967 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8968 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8969 if (InputByteIdx != 0x80)
8974 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8976 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8977 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8978 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8981 // v8i16 shuffles - Prefer shuffles in the following order:
8982 // 1. [all] pshuflw, pshufhw, optional move
8983 // 2. [ssse3] 1 x pshufb
8984 // 3. [ssse3] 2 x pshufb + 1 x por
8985 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8987 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8988 SelectionDAG &DAG) {
8989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8990 SDValue V1 = SVOp->getOperand(0);
8991 SDValue V2 = SVOp->getOperand(1);
8993 SmallVector<int, 8> MaskVals;
8995 // Determine if more than 1 of the words in each of the low and high quadwords
8996 // of the result come from the same quadword of one of the two inputs. Undef
8997 // mask values count as coming from any quadword, for better codegen.
8999 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9000 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9001 unsigned LoQuad[] = { 0, 0, 0, 0 };
9002 unsigned HiQuad[] = { 0, 0, 0, 0 };
9003 // Indices of quads used.
9004 std::bitset<4> InputQuads;
9005 for (unsigned i = 0; i < 8; ++i) {
9006 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9007 int EltIdx = SVOp->getMaskElt(i);
9008 MaskVals.push_back(EltIdx);
9017 InputQuads.set(EltIdx / 4);
9020 int BestLoQuad = -1;
9021 unsigned MaxQuad = 1;
9022 for (unsigned i = 0; i < 4; ++i) {
9023 if (LoQuad[i] > MaxQuad) {
9025 MaxQuad = LoQuad[i];
9029 int BestHiQuad = -1;
9031 for (unsigned i = 0; i < 4; ++i) {
9032 if (HiQuad[i] > MaxQuad) {
9034 MaxQuad = HiQuad[i];
9038 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9039 // of the two input vectors, shuffle them into one input vector so only a
9040 // single pshufb instruction is necessary. If there are more than 2 input
9041 // quads, disable the next transformation since it does not help SSSE3.
9042 bool V1Used = InputQuads[0] || InputQuads[1];
9043 bool V2Used = InputQuads[2] || InputQuads[3];
9044 if (Subtarget->hasSSSE3()) {
9045 if (InputQuads.count() == 2 && V1Used && V2Used) {
9046 BestLoQuad = InputQuads[0] ? 0 : 1;
9047 BestHiQuad = InputQuads[2] ? 2 : 3;
9049 if (InputQuads.count() > 2) {
9055 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9056 // the shuffle mask. If a quad is scored as -1, that means that it contains
9057 // words from all 4 input quadwords.
9059 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9061 BestLoQuad < 0 ? 0 : BestLoQuad,
9062 BestHiQuad < 0 ? 1 : BestHiQuad
9064 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9065 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9066 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9067 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9069 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9070 // source words for the shuffle, to aid later transformations.
9071 bool AllWordsInNewV = true;
9072 bool InOrder[2] = { true, true };
9073 for (unsigned i = 0; i != 8; ++i) {
9074 int idx = MaskVals[i];
9076 InOrder[i/4] = false;
9077 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9079 AllWordsInNewV = false;
9083 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9084 if (AllWordsInNewV) {
9085 for (int i = 0; i != 8; ++i) {
9086 int idx = MaskVals[i];
9089 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9090 if ((idx != i) && idx < 4)
9092 if ((idx != i) && idx > 3)
9101 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9102 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9103 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9104 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9105 unsigned TargetMask = 0;
9106 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9107 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9109 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9110 getShufflePSHUFLWImmediate(SVOp);
9111 V1 = NewV.getOperand(0);
9112 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9116 // Promote splats to a larger type which usually leads to more efficient code.
9117 // FIXME: Is this true if pshufb is available?
9118 if (SVOp->isSplat())
9119 return PromoteSplat(SVOp, DAG);
9121 // If we have SSSE3, and all words of the result are from 1 input vector,
9122 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9123 // is present, fall back to case 4.
9124 if (Subtarget->hasSSSE3()) {
9125 SmallVector<SDValue,16> pshufbMask;
9127 // If we have elements from both input vectors, set the high bit of the
9128 // shuffle mask element to zero out elements that come from V2 in the V1
9129 // mask, and elements that come from V1 in the V2 mask, so that the two
9130 // results can be OR'd together.
9131 bool TwoInputs = V1Used && V2Used;
9132 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9134 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9136 // Calculate the shuffle mask for the second input, shuffle it, and
9137 // OR it with the first shuffled input.
9138 CommuteVectorShuffleMask(MaskVals, 8);
9139 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9140 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9141 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9144 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9145 // and update MaskVals with new element order.
9146 std::bitset<8> InOrder;
9147 if (BestLoQuad >= 0) {
9148 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9149 for (int i = 0; i != 4; ++i) {
9150 int idx = MaskVals[i];
9153 } else if ((idx / 4) == BestLoQuad) {
9158 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9161 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9162 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9163 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9165 getShufflePSHUFLWImmediate(SVOp), DAG);
9169 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9170 // and update MaskVals with the new element order.
9171 if (BestHiQuad >= 0) {
9172 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9173 for (unsigned i = 4; i != 8; ++i) {
9174 int idx = MaskVals[i];
9177 } else if ((idx / 4) == BestHiQuad) {
9178 MaskV[i] = (idx & 3) + 4;
9182 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9185 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9186 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9187 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9189 getShufflePSHUFHWImmediate(SVOp), DAG);
9193 // In case BestHi & BestLo were both -1, which means each quadword has a word
9194 // from each of the four input quadwords, calculate the InOrder bitvector now
9195 // before falling through to the insert/extract cleanup.
9196 if (BestLoQuad == -1 && BestHiQuad == -1) {
9198 for (int i = 0; i != 8; ++i)
9199 if (MaskVals[i] < 0 || MaskVals[i] == i)
9203 // The other elements are put in the right place using pextrw and pinsrw.
9204 for (unsigned i = 0; i != 8; ++i) {
9207 int EltIdx = MaskVals[i];
9210 SDValue ExtOp = (EltIdx < 8) ?
9211 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9212 DAG.getIntPtrConstant(EltIdx)) :
9213 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9214 DAG.getIntPtrConstant(EltIdx - 8));
9215 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9216 DAG.getIntPtrConstant(i));
9221 /// \brief v16i16 shuffles
9223 /// FIXME: We only support generation of a single pshufb currently. We can
9224 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9225 /// well (e.g 2 x pshufb + 1 x por).
9227 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9228 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9229 SDValue V1 = SVOp->getOperand(0);
9230 SDValue V2 = SVOp->getOperand(1);
9233 if (V2.getOpcode() != ISD::UNDEF)
9236 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9237 return getPSHUFB(MaskVals, V1, dl, DAG);
9240 // v16i8 shuffles - Prefer shuffles in the following order:
9241 // 1. [ssse3] 1 x pshufb
9242 // 2. [ssse3] 2 x pshufb + 1 x por
9243 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9244 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9245 const X86Subtarget* Subtarget,
9246 SelectionDAG &DAG) {
9247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9248 SDValue V1 = SVOp->getOperand(0);
9249 SDValue V2 = SVOp->getOperand(1);
9251 ArrayRef<int> MaskVals = SVOp->getMask();
9253 // Promote splats to a larger type which usually leads to more efficient code.
9254 // FIXME: Is this true if pshufb is available?
9255 if (SVOp->isSplat())
9256 return PromoteSplat(SVOp, DAG);
9258 // If we have SSSE3, case 1 is generated when all result bytes come from
9259 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9260 // present, fall back to case 3.
9262 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9263 if (Subtarget->hasSSSE3()) {
9264 SmallVector<SDValue,16> pshufbMask;
9266 // If all result elements are from one input vector, then only translate
9267 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9269 // Otherwise, we have elements from both input vectors, and must zero out
9270 // elements that come from V2 in the first mask, and V1 in the second mask
9271 // so that we can OR them together.
9272 for (unsigned i = 0; i != 16; ++i) {
9273 int EltIdx = MaskVals[i];
9274 if (EltIdx < 0 || EltIdx >= 16)
9276 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9278 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9279 DAG.getNode(ISD::BUILD_VECTOR, dl,
9280 MVT::v16i8, pshufbMask));
9282 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9283 // the 2nd operand if it's undefined or zero.
9284 if (V2.getOpcode() == ISD::UNDEF ||
9285 ISD::isBuildVectorAllZeros(V2.getNode()))
9288 // Calculate the shuffle mask for the second input, shuffle it, and
9289 // OR it with the first shuffled input.
9291 for (unsigned i = 0; i != 16; ++i) {
9292 int EltIdx = MaskVals[i];
9293 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9294 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9296 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9297 DAG.getNode(ISD::BUILD_VECTOR, dl,
9298 MVT::v16i8, pshufbMask));
9299 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9302 // No SSSE3 - Calculate in place words and then fix all out of place words
9303 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9304 // the 16 different words that comprise the two doublequadword input vectors.
9305 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9306 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9308 for (int i = 0; i != 8; ++i) {
9309 int Elt0 = MaskVals[i*2];
9310 int Elt1 = MaskVals[i*2+1];
9312 // This word of the result is all undef, skip it.
9313 if (Elt0 < 0 && Elt1 < 0)
9316 // This word of the result is already in the correct place, skip it.
9317 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9320 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9321 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9324 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9325 // using a single extract together, load it and store it.
9326 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9327 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9328 DAG.getIntPtrConstant(Elt1 / 2));
9329 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9330 DAG.getIntPtrConstant(i));
9334 // If Elt1 is defined, extract it from the appropriate source. If the
9335 // source byte is not also odd, shift the extracted word left 8 bits
9336 // otherwise clear the bottom 8 bits if we need to do an or.
9338 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9339 DAG.getIntPtrConstant(Elt1 / 2));
9340 if ((Elt1 & 1) == 0)
9341 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9343 TLI.getShiftAmountTy(InsElt.getValueType())));
9345 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9346 DAG.getConstant(0xFF00, MVT::i16));
9348 // If Elt0 is defined, extract it from the appropriate source. If the
9349 // source byte is not also even, shift the extracted word right 8 bits. If
9350 // Elt1 was also defined, OR the extracted values together before
9351 // inserting them in the result.
9353 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9354 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9355 if ((Elt0 & 1) != 0)
9356 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9358 TLI.getShiftAmountTy(InsElt0.getValueType())));
9360 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9361 DAG.getConstant(0x00FF, MVT::i16));
9362 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9365 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9366 DAG.getIntPtrConstant(i));
9368 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9371 // v32i8 shuffles - Translate to VPSHUFB if possible.
9373 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9374 const X86Subtarget *Subtarget,
9375 SelectionDAG &DAG) {
9376 MVT VT = SVOp->getSimpleValueType(0);
9377 SDValue V1 = SVOp->getOperand(0);
9378 SDValue V2 = SVOp->getOperand(1);
9380 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9382 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9383 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9384 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9386 // VPSHUFB may be generated if
9387 // (1) one of input vector is undefined or zeroinitializer.
9388 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9389 // And (2) the mask indexes don't cross the 128-bit lane.
9390 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9391 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9394 if (V1IsAllZero && !V2IsAllZero) {
9395 CommuteVectorShuffleMask(MaskVals, 32);
9398 return getPSHUFB(MaskVals, V1, dl, DAG);
9401 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9402 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9403 /// done when every pair / quad of shuffle mask elements point to elements in
9404 /// the right sequence. e.g.
9405 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9407 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9408 SelectionDAG &DAG) {
9409 MVT VT = SVOp->getSimpleValueType(0);
9411 unsigned NumElems = VT.getVectorNumElements();
9414 switch (VT.SimpleTy) {
9415 default: llvm_unreachable("Unexpected!");
9418 return SDValue(SVOp, 0);
9419 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9420 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9421 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9422 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9423 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9424 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9427 SmallVector<int, 8> MaskVec;
9428 for (unsigned i = 0; i != NumElems; i += Scale) {
9430 for (unsigned j = 0; j != Scale; ++j) {
9431 int EltIdx = SVOp->getMaskElt(i+j);
9435 StartIdx = (EltIdx / Scale);
9436 if (EltIdx != (int)(StartIdx*Scale + j))
9439 MaskVec.push_back(StartIdx);
9442 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9443 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9444 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9447 /// getVZextMovL - Return a zero-extending vector move low node.
9449 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9450 SDValue SrcOp, SelectionDAG &DAG,
9451 const X86Subtarget *Subtarget, SDLoc dl) {
9452 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9453 LoadSDNode *LD = nullptr;
9454 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9455 LD = dyn_cast<LoadSDNode>(SrcOp);
9457 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9459 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9460 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9461 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9462 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9463 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9465 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9466 return DAG.getNode(ISD::BITCAST, dl, VT,
9467 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9468 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9476 return DAG.getNode(ISD::BITCAST, dl, VT,
9477 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9478 DAG.getNode(ISD::BITCAST, dl,
9482 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9483 /// which could not be matched by any known target speficic shuffle
9485 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9487 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9488 if (NewOp.getNode())
9491 MVT VT = SVOp->getSimpleValueType(0);
9493 unsigned NumElems = VT.getVectorNumElements();
9494 unsigned NumLaneElems = NumElems / 2;
9497 MVT EltVT = VT.getVectorElementType();
9498 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9501 SmallVector<int, 16> Mask;
9502 for (unsigned l = 0; l < 2; ++l) {
9503 // Build a shuffle mask for the output, discovering on the fly which
9504 // input vectors to use as shuffle operands (recorded in InputUsed).
9505 // If building a suitable shuffle vector proves too hard, then bail
9506 // out with UseBuildVector set.
9507 bool UseBuildVector = false;
9508 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9509 unsigned LaneStart = l * NumLaneElems;
9510 for (unsigned i = 0; i != NumLaneElems; ++i) {
9511 // The mask element. This indexes into the input.
9512 int Idx = SVOp->getMaskElt(i+LaneStart);
9514 // the mask element does not index into any input vector.
9519 // The input vector this mask element indexes into.
9520 int Input = Idx / NumLaneElems;
9522 // Turn the index into an offset from the start of the input vector.
9523 Idx -= Input * NumLaneElems;
9525 // Find or create a shuffle vector operand to hold this input.
9527 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9528 if (InputUsed[OpNo] == Input)
9529 // This input vector is already an operand.
9531 if (InputUsed[OpNo] < 0) {
9532 // Create a new operand for this input vector.
9533 InputUsed[OpNo] = Input;
9538 if (OpNo >= array_lengthof(InputUsed)) {
9539 // More than two input vectors used! Give up on trying to create a
9540 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9541 UseBuildVector = true;
9545 // Add the mask index for the new shuffle vector.
9546 Mask.push_back(Idx + OpNo * NumLaneElems);
9549 if (UseBuildVector) {
9550 SmallVector<SDValue, 16> SVOps;
9551 for (unsigned i = 0; i != NumLaneElems; ++i) {
9552 // The mask element. This indexes into the input.
9553 int Idx = SVOp->getMaskElt(i+LaneStart);
9555 SVOps.push_back(DAG.getUNDEF(EltVT));
9559 // The input vector this mask element indexes into.
9560 int Input = Idx / NumElems;
9562 // Turn the index into an offset from the start of the input vector.
9563 Idx -= Input * NumElems;
9565 // Extract the vector element by hand.
9566 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9567 SVOp->getOperand(Input),
9568 DAG.getIntPtrConstant(Idx)));
9571 // Construct the output using a BUILD_VECTOR.
9572 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9573 } else if (InputUsed[0] < 0) {
9574 // No input vectors were used! The result is undefined.
9575 Output[l] = DAG.getUNDEF(NVT);
9577 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9578 (InputUsed[0] % 2) * NumLaneElems,
9580 // If only one input was used, use an undefined vector for the other.
9581 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9582 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9583 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9584 // At least one input vector was used. Create a new shuffle vector.
9585 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9591 // Concatenate the result back
9592 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9595 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9596 /// 4 elements, and match them with several different shuffle types.
9598 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9599 SDValue V1 = SVOp->getOperand(0);
9600 SDValue V2 = SVOp->getOperand(1);
9602 MVT VT = SVOp->getSimpleValueType(0);
9604 assert(VT.is128BitVector() && "Unsupported vector size");
9606 std::pair<int, int> Locs[4];
9607 int Mask1[] = { -1, -1, -1, -1 };
9608 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9612 for (unsigned i = 0; i != 4; ++i) {
9613 int Idx = PermMask[i];
9615 Locs[i] = std::make_pair(-1, -1);
9617 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9619 Locs[i] = std::make_pair(0, NumLo);
9623 Locs[i] = std::make_pair(1, NumHi);
9625 Mask1[2+NumHi] = Idx;
9631 if (NumLo <= 2 && NumHi <= 2) {
9632 // If no more than two elements come from either vector. This can be
9633 // implemented with two shuffles. First shuffle gather the elements.
9634 // The second shuffle, which takes the first shuffle as both of its
9635 // vector operands, put the elements into the right order.
9636 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9638 int Mask2[] = { -1, -1, -1, -1 };
9640 for (unsigned i = 0; i != 4; ++i)
9641 if (Locs[i].first != -1) {
9642 unsigned Idx = (i < 2) ? 0 : 4;
9643 Idx += Locs[i].first * 2 + Locs[i].second;
9647 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9650 if (NumLo == 3 || NumHi == 3) {
9651 // Otherwise, we must have three elements from one vector, call it X, and
9652 // one element from the other, call it Y. First, use a shufps to build an
9653 // intermediate vector with the one element from Y and the element from X
9654 // that will be in the same half in the final destination (the indexes don't
9655 // matter). Then, use a shufps to build the final vector, taking the half
9656 // containing the element from Y from the intermediate, and the other half
9659 // Normalize it so the 3 elements come from V1.
9660 CommuteVectorShuffleMask(PermMask, 4);
9664 // Find the element from V2.
9666 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9667 int Val = PermMask[HiIndex];
9674 Mask1[0] = PermMask[HiIndex];
9676 Mask1[2] = PermMask[HiIndex^1];
9678 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9681 Mask1[0] = PermMask[0];
9682 Mask1[1] = PermMask[1];
9683 Mask1[2] = HiIndex & 1 ? 6 : 4;
9684 Mask1[3] = HiIndex & 1 ? 4 : 6;
9685 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9688 Mask1[0] = HiIndex & 1 ? 2 : 0;
9689 Mask1[1] = HiIndex & 1 ? 0 : 2;
9690 Mask1[2] = PermMask[2];
9691 Mask1[3] = PermMask[3];
9696 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9699 // Break it into (shuffle shuffle_hi, shuffle_lo).
9700 int LoMask[] = { -1, -1, -1, -1 };
9701 int HiMask[] = { -1, -1, -1, -1 };
9703 int *MaskPtr = LoMask;
9704 unsigned MaskIdx = 0;
9707 for (unsigned i = 0; i != 4; ++i) {
9714 int Idx = PermMask[i];
9716 Locs[i] = std::make_pair(-1, -1);
9717 } else if (Idx < 4) {
9718 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9719 MaskPtr[LoIdx] = Idx;
9722 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9723 MaskPtr[HiIdx] = Idx;
9728 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9729 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9730 int MaskOps[] = { -1, -1, -1, -1 };
9731 for (unsigned i = 0; i != 4; ++i)
9732 if (Locs[i].first != -1)
9733 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9734 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9737 static bool MayFoldVectorLoad(SDValue V) {
9738 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9739 V = V.getOperand(0);
9741 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9742 V = V.getOperand(0);
9743 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9744 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9745 // BUILD_VECTOR (load), undef
9746 V = V.getOperand(0);
9748 return MayFoldLoad(V);
9752 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9753 MVT VT = Op.getSimpleValueType();
9755 // Canonizalize to v2f64.
9756 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9757 return DAG.getNode(ISD::BITCAST, dl, VT,
9758 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9763 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9765 SDValue V1 = Op.getOperand(0);
9766 SDValue V2 = Op.getOperand(1);
9767 MVT VT = Op.getSimpleValueType();
9769 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9771 if (HasSSE2 && VT == MVT::v2f64)
9772 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9774 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9775 return DAG.getNode(ISD::BITCAST, dl, VT,
9776 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9777 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9778 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9782 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9783 SDValue V1 = Op.getOperand(0);
9784 SDValue V2 = Op.getOperand(1);
9785 MVT VT = Op.getSimpleValueType();
9787 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9788 "unsupported shuffle type");
9790 if (V2.getOpcode() == ISD::UNDEF)
9794 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9798 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9799 SDValue V1 = Op.getOperand(0);
9800 SDValue V2 = Op.getOperand(1);
9801 MVT VT = Op.getSimpleValueType();
9802 unsigned NumElems = VT.getVectorNumElements();
9804 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9805 // operand of these instructions is only memory, so check if there's a
9806 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9808 bool CanFoldLoad = false;
9810 // Trivial case, when V2 comes from a load.
9811 if (MayFoldVectorLoad(V2))
9814 // When V1 is a load, it can be folded later into a store in isel, example:
9815 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9817 // (MOVLPSmr addr:$src1, VR128:$src2)
9818 // So, recognize this potential and also use MOVLPS or MOVLPD
9819 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9824 if (HasSSE2 && NumElems == 2)
9825 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9828 // If we don't care about the second element, proceed to use movss.
9829 if (SVOp->getMaskElt(1) != -1)
9830 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9833 // movl and movlp will both match v2i64, but v2i64 is never matched by
9834 // movl earlier because we make it strict to avoid messing with the movlp load
9835 // folding logic (see the code above getMOVLP call). Match it here then,
9836 // this is horrible, but will stay like this until we move all shuffle
9837 // matching to x86 specific nodes. Note that for the 1st condition all
9838 // types are matched with movsd.
9840 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9841 // as to remove this logic from here, as much as possible
9842 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9843 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9844 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9847 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9849 // Invert the operand order and use SHUFPS to match it.
9850 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9851 getShuffleSHUFImmediate(SVOp), DAG);
9854 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9855 SelectionDAG &DAG) {
9857 MVT VT = Load->getSimpleValueType(0);
9858 MVT EVT = VT.getVectorElementType();
9859 SDValue Addr = Load->getOperand(1);
9860 SDValue NewAddr = DAG.getNode(
9861 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9862 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9865 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9866 DAG.getMachineFunction().getMachineMemOperand(
9867 Load->getMemOperand(), 0, EVT.getStoreSize()));
9871 // It is only safe to call this function if isINSERTPSMask is true for
9872 // this shufflevector mask.
9873 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9874 SelectionDAG &DAG) {
9875 // Generate an insertps instruction when inserting an f32 from memory onto a
9876 // v4f32 or when copying a member from one v4f32 to another.
9877 // We also use it for transferring i32 from one register to another,
9878 // since it simply copies the same bits.
9879 // If we're transferring an i32 from memory to a specific element in a
9880 // register, we output a generic DAG that will match the PINSRD
9882 MVT VT = SVOp->getSimpleValueType(0);
9883 MVT EVT = VT.getVectorElementType();
9884 SDValue V1 = SVOp->getOperand(0);
9885 SDValue V2 = SVOp->getOperand(1);
9886 auto Mask = SVOp->getMask();
9887 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9888 "unsupported vector type for insertps/pinsrd");
9890 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9891 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9892 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9900 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9903 // If we have 1 element from each vector, we have to check if we're
9904 // changing V1's element's place. If so, we're done. Otherwise, we
9905 // should assume we're changing V2's element's place and behave
9907 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9908 assert(DestIndex <= INT32_MAX && "truncated destination index");
9909 if (FromV1 == FromV2 &&
9910 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9914 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9917 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9918 "More than one element from V1 and from V2, or no elements from one "
9919 "of the vectors. This case should not have returned true from "
9924 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9927 // Get an index into the source vector in the range [0,4) (the mask is
9928 // in the range [0,8) because it can address V1 and V2)
9929 unsigned SrcIndex = Mask[DestIndex] % 4;
9930 if (MayFoldLoad(From)) {
9931 // Trivial case, when From comes from a load and is only used by the
9932 // shuffle. Make it use insertps from the vector that we need from that
9935 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9936 if (!NewLoad.getNode())
9939 if (EVT == MVT::f32) {
9940 // Create this as a scalar to vector to match the instruction pattern.
9941 SDValue LoadScalarToVector =
9942 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9943 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9944 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9946 } else { // EVT == MVT::i32
9947 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9948 // instruction, to match the PINSRD instruction, which loads an i32 to a
9949 // certain vector element.
9950 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9951 DAG.getConstant(DestIndex, MVT::i32));
9955 // Vector-element-to-vector
9956 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9957 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9960 // Reduce a vector shuffle to zext.
9961 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9962 SelectionDAG &DAG) {
9963 // PMOVZX is only available from SSE41.
9964 if (!Subtarget->hasSSE41())
9967 MVT VT = Op.getSimpleValueType();
9969 // Only AVX2 support 256-bit vector integer extending.
9970 if (!Subtarget->hasInt256() && VT.is256BitVector())
9973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9975 SDValue V1 = Op.getOperand(0);
9976 SDValue V2 = Op.getOperand(1);
9977 unsigned NumElems = VT.getVectorNumElements();
9979 // Extending is an unary operation and the element type of the source vector
9980 // won't be equal to or larger than i64.
9981 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9982 VT.getVectorElementType() == MVT::i64)
9985 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9986 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9987 while ((1U << Shift) < NumElems) {
9988 if (SVOp->getMaskElt(1U << Shift) == 1)
9991 // The maximal ratio is 8, i.e. from i8 to i64.
9996 // Check the shuffle mask.
9997 unsigned Mask = (1U << Shift) - 1;
9998 for (unsigned i = 0; i != NumElems; ++i) {
9999 int EltIdx = SVOp->getMaskElt(i);
10000 if ((i & Mask) != 0 && EltIdx != -1)
10002 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10006 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10007 MVT NeVT = MVT::getIntegerVT(NBits);
10008 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10010 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10013 // Simplify the operand as it's prepared to be fed into shuffle.
10014 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10015 if (V1.getOpcode() == ISD::BITCAST &&
10016 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10017 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10018 V1.getOperand(0).getOperand(0)
10019 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10020 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10021 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10022 ConstantSDNode *CIdx =
10023 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10024 // If it's foldable, i.e. normal load with single use, we will let code
10025 // selection to fold it. Otherwise, we will short the conversion sequence.
10026 if (CIdx && CIdx->getZExtValue() == 0 &&
10027 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10028 MVT FullVT = V.getSimpleValueType();
10029 MVT V1VT = V1.getSimpleValueType();
10030 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10031 // The "ext_vec_elt" node is wider than the result node.
10032 // In this case we should extract subvector from V.
10033 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10034 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10035 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10036 FullVT.getVectorNumElements()/Ratio);
10037 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10038 DAG.getIntPtrConstant(0));
10040 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10044 return DAG.getNode(ISD::BITCAST, DL, VT,
10045 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10048 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10049 SelectionDAG &DAG) {
10050 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10051 MVT VT = Op.getSimpleValueType();
10053 SDValue V1 = Op.getOperand(0);
10054 SDValue V2 = Op.getOperand(1);
10056 if (isZeroShuffle(SVOp))
10057 return getZeroVector(VT, Subtarget, DAG, dl);
10059 // Handle splat operations
10060 if (SVOp->isSplat()) {
10061 // Use vbroadcast whenever the splat comes from a foldable load
10062 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10063 if (Broadcast.getNode())
10067 // Check integer expanding shuffles.
10068 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10069 if (NewOp.getNode())
10072 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10074 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10075 VT == MVT::v32i8) {
10076 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10077 if (NewOp.getNode())
10078 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10079 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10080 // FIXME: Figure out a cleaner way to do this.
10081 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10082 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10083 if (NewOp.getNode()) {
10084 MVT NewVT = NewOp.getSimpleValueType();
10085 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10086 NewVT, true, false))
10087 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10090 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10091 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10092 if (NewOp.getNode()) {
10093 MVT NewVT = NewOp.getSimpleValueType();
10094 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10095 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10104 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10106 SDValue V1 = Op.getOperand(0);
10107 SDValue V2 = Op.getOperand(1);
10108 MVT VT = Op.getSimpleValueType();
10110 unsigned NumElems = VT.getVectorNumElements();
10111 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10112 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10113 bool V1IsSplat = false;
10114 bool V2IsSplat = false;
10115 bool HasSSE2 = Subtarget->hasSSE2();
10116 bool HasFp256 = Subtarget->hasFp256();
10117 bool HasInt256 = Subtarget->hasInt256();
10118 MachineFunction &MF = DAG.getMachineFunction();
10119 bool OptForSize = MF.getFunction()->getAttributes().
10120 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10122 // Check if we should use the experimental vector shuffle lowering. If so,
10123 // delegate completely to that code path.
10124 if (ExperimentalVectorShuffleLowering)
10125 return lowerVectorShuffle(Op, Subtarget, DAG);
10127 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10129 if (V1IsUndef && V2IsUndef)
10130 return DAG.getUNDEF(VT);
10132 // When we create a shuffle node we put the UNDEF node to second operand,
10133 // but in some cases the first operand may be transformed to UNDEF.
10134 // In this case we should just commute the node.
10136 return DAG.getCommutedVectorShuffle(*SVOp);
10138 // Vector shuffle lowering takes 3 steps:
10140 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10141 // narrowing and commutation of operands should be handled.
10142 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10144 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10145 // so the shuffle can be broken into other shuffles and the legalizer can
10146 // try the lowering again.
10148 // The general idea is that no vector_shuffle operation should be left to
10149 // be matched during isel, all of them must be converted to a target specific
10152 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10153 // narrowing and commutation of operands should be handled. The actual code
10154 // doesn't include all of those, work in progress...
10155 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10156 if (NewOp.getNode())
10159 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10161 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10162 // unpckh_undef). Only use pshufd if speed is more important than size.
10163 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10164 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10165 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10166 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10168 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10169 V2IsUndef && MayFoldVectorLoad(V1))
10170 return getMOVDDup(Op, dl, V1, DAG);
10172 if (isMOVHLPS_v_undef_Mask(M, VT))
10173 return getMOVHighToLow(Op, dl, DAG);
10175 // Use to match splats
10176 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10177 (VT == MVT::v2f64 || VT == MVT::v2i64))
10178 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10180 if (isPSHUFDMask(M, VT)) {
10181 // The actual implementation will match the mask in the if above and then
10182 // during isel it can match several different instructions, not only pshufd
10183 // as its name says, sad but true, emulate the behavior for now...
10184 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10185 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10187 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10189 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10190 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10192 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10193 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10196 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10200 if (isPALIGNRMask(M, VT, Subtarget))
10201 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10202 getShufflePALIGNRImmediate(SVOp),
10205 if (isVALIGNMask(M, VT, Subtarget))
10206 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10207 getShuffleVALIGNImmediate(SVOp),
10210 // Check if this can be converted into a logical shift.
10211 bool isLeft = false;
10212 unsigned ShAmt = 0;
10214 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10215 if (isShift && ShVal.hasOneUse()) {
10216 // If the shifted value has multiple uses, it may be cheaper to use
10217 // v_set0 + movlhps or movhlps, etc.
10218 MVT EltVT = VT.getVectorElementType();
10219 ShAmt *= EltVT.getSizeInBits();
10220 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10223 if (isMOVLMask(M, VT)) {
10224 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10225 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10226 if (!isMOVLPMask(M, VT)) {
10227 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10228 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10230 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10231 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10235 // FIXME: fold these into legal mask.
10236 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10237 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10239 if (isMOVHLPSMask(M, VT))
10240 return getMOVHighToLow(Op, dl, DAG);
10242 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10243 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10245 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10246 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10248 if (isMOVLPMask(M, VT))
10249 return getMOVLP(Op, dl, DAG, HasSSE2);
10251 if (ShouldXformToMOVHLPS(M, VT) ||
10252 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10253 return DAG.getCommutedVectorShuffle(*SVOp);
10256 // No better options. Use a vshldq / vsrldq.
10257 MVT EltVT = VT.getVectorElementType();
10258 ShAmt *= EltVT.getSizeInBits();
10259 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10262 bool Commuted = false;
10263 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10264 // 1,1,1,1 -> v8i16 though.
10265 BitVector UndefElements;
10266 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10267 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10269 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10270 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10273 // Canonicalize the splat or undef, if present, to be on the RHS.
10274 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10275 CommuteVectorShuffleMask(M, NumElems);
10277 std::swap(V1IsSplat, V2IsSplat);
10281 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10282 // Shuffling low element of v1 into undef, just return v1.
10285 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10286 // the instruction selector will not match, so get a canonical MOVL with
10287 // swapped operands to undo the commute.
10288 return getMOVL(DAG, dl, VT, V2, V1);
10291 if (isUNPCKLMask(M, VT, HasInt256))
10292 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10294 if (isUNPCKHMask(M, VT, HasInt256))
10295 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10298 // Normalize mask so all entries that point to V2 points to its first
10299 // element then try to match unpck{h|l} again. If match, return a
10300 // new vector_shuffle with the corrected mask.p
10301 SmallVector<int, 8> NewMask(M.begin(), M.end());
10302 NormalizeMask(NewMask, NumElems);
10303 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10304 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10305 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10306 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10310 // Commute is back and try unpck* again.
10311 // FIXME: this seems wrong.
10312 CommuteVectorShuffleMask(M, NumElems);
10314 std::swap(V1IsSplat, V2IsSplat);
10316 if (isUNPCKLMask(M, VT, HasInt256))
10317 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10319 if (isUNPCKHMask(M, VT, HasInt256))
10320 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10323 // Normalize the node to match x86 shuffle ops if needed
10324 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10325 return DAG.getCommutedVectorShuffle(*SVOp);
10327 // The checks below are all present in isShuffleMaskLegal, but they are
10328 // inlined here right now to enable us to directly emit target specific
10329 // nodes, and remove one by one until they don't return Op anymore.
10331 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10332 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10333 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10334 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10337 if (isPSHUFHWMask(M, VT, HasInt256))
10338 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10339 getShufflePSHUFHWImmediate(SVOp),
10342 if (isPSHUFLWMask(M, VT, HasInt256))
10343 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10344 getShufflePSHUFLWImmediate(SVOp),
10347 unsigned MaskValue;
10348 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10350 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10352 if (isSHUFPMask(M, VT))
10353 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10354 getShuffleSHUFImmediate(SVOp), DAG);
10356 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10357 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10358 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10359 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10361 //===--------------------------------------------------------------------===//
10362 // Generate target specific nodes for 128 or 256-bit shuffles only
10363 // supported in the AVX instruction set.
10366 // Handle VMOVDDUPY permutations
10367 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10368 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10370 // Handle VPERMILPS/D* permutations
10371 if (isVPERMILPMask(M, VT)) {
10372 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10373 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10374 getShuffleSHUFImmediate(SVOp), DAG);
10375 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10376 getShuffleSHUFImmediate(SVOp), DAG);
10380 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10381 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10382 Idx*(NumElems/2), DAG, dl);
10384 // Handle VPERM2F128/VPERM2I128 permutations
10385 if (isVPERM2X128Mask(M, VT, HasFp256))
10386 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10387 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10389 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10390 return getINSERTPS(SVOp, dl, DAG);
10393 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10394 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10396 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10397 VT.is512BitVector()) {
10398 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10399 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10400 SmallVector<SDValue, 16> permclMask;
10401 for (unsigned i = 0; i != NumElems; ++i) {
10402 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10405 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10407 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10408 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10409 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10410 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10411 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10414 //===--------------------------------------------------------------------===//
10415 // Since no target specific shuffle was selected for this generic one,
10416 // lower it into other known shuffles. FIXME: this isn't true yet, but
10417 // this is the plan.
10420 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10421 if (VT == MVT::v8i16) {
10422 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10423 if (NewOp.getNode())
10427 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10428 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10429 if (NewOp.getNode())
10433 if (VT == MVT::v16i8) {
10434 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10435 if (NewOp.getNode())
10439 if (VT == MVT::v32i8) {
10440 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10441 if (NewOp.getNode())
10445 // Handle all 128-bit wide vectors with 4 elements, and match them with
10446 // several different shuffle types.
10447 if (NumElems == 4 && VT.is128BitVector())
10448 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10450 // Handle general 256-bit shuffles
10451 if (VT.is256BitVector())
10452 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10457 // This function assumes its argument is a BUILD_VECTOR of constants or
10458 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10460 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10461 unsigned &MaskValue) {
10463 unsigned NumElems = BuildVector->getNumOperands();
10464 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10465 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10466 unsigned NumElemsInLane = NumElems / NumLanes;
10468 // Blend for v16i16 should be symetric for the both lanes.
10469 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10470 SDValue EltCond = BuildVector->getOperand(i);
10471 SDValue SndLaneEltCond =
10472 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10474 int Lane1Cond = -1, Lane2Cond = -1;
10475 if (isa<ConstantSDNode>(EltCond))
10476 Lane1Cond = !isZero(EltCond);
10477 if (isa<ConstantSDNode>(SndLaneEltCond))
10478 Lane2Cond = !isZero(SndLaneEltCond);
10480 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10481 // Lane1Cond != 0, means we want the first argument.
10482 // Lane1Cond == 0, means we want the second argument.
10483 // The encoding of this argument is 0 for the first argument, 1
10484 // for the second. Therefore, invert the condition.
10485 MaskValue |= !Lane1Cond << i;
10486 else if (Lane1Cond < 0)
10487 MaskValue |= !Lane2Cond << i;
10494 // Try to lower a vselect node into a simple blend instruction.
10495 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10496 SelectionDAG &DAG) {
10497 SDValue Cond = Op.getOperand(0);
10498 SDValue LHS = Op.getOperand(1);
10499 SDValue RHS = Op.getOperand(2);
10501 MVT VT = Op.getSimpleValueType();
10502 MVT EltVT = VT.getVectorElementType();
10503 unsigned NumElems = VT.getVectorNumElements();
10505 // There is no blend with immediate in AVX-512.
10506 if (VT.is512BitVector())
10509 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10511 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10514 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10517 // Check the mask for BLEND and build the value.
10518 unsigned MaskValue = 0;
10519 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10522 // Convert i32 vectors to floating point if it is not AVX2.
10523 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10525 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10526 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10528 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10529 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10532 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10533 DAG.getConstant(MaskValue, MVT::i32));
10534 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10537 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10538 // A vselect where all conditions and data are constants can be optimized into
10539 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10540 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10541 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10542 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10545 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10546 if (BlendOp.getNode())
10549 // Some types for vselect were previously set to Expand, not Legal or
10550 // Custom. Return an empty SDValue so we fall-through to Expand, after
10551 // the Custom lowering phase.
10552 MVT VT = Op.getSimpleValueType();
10553 switch (VT.SimpleTy) {
10558 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10563 // We couldn't create a "Blend with immediate" node.
10564 // This node should still be legal, but we'll have to emit a blendv*
10569 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10570 MVT VT = Op.getSimpleValueType();
10573 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10576 if (VT.getSizeInBits() == 8) {
10577 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10578 Op.getOperand(0), Op.getOperand(1));
10579 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10580 DAG.getValueType(VT));
10581 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10584 if (VT.getSizeInBits() == 16) {
10585 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10586 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10588 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10589 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10590 DAG.getNode(ISD::BITCAST, dl,
10593 Op.getOperand(1)));
10594 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10595 Op.getOperand(0), Op.getOperand(1));
10596 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10597 DAG.getValueType(VT));
10598 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10601 if (VT == MVT::f32) {
10602 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10603 // the result back to FR32 register. It's only worth matching if the
10604 // result has a single use which is a store or a bitcast to i32. And in
10605 // the case of a store, it's not worth it if the index is a constant 0,
10606 // because a MOVSSmr can be used instead, which is smaller and faster.
10607 if (!Op.hasOneUse())
10609 SDNode *User = *Op.getNode()->use_begin();
10610 if ((User->getOpcode() != ISD::STORE ||
10611 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10612 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10613 (User->getOpcode() != ISD::BITCAST ||
10614 User->getValueType(0) != MVT::i32))
10616 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10617 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10620 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10623 if (VT == MVT::i32 || VT == MVT::i64) {
10624 // ExtractPS/pextrq works with constant index.
10625 if (isa<ConstantSDNode>(Op.getOperand(1)))
10631 /// Extract one bit from mask vector, like v16i1 or v8i1.
10632 /// AVX-512 feature.
10634 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10635 SDValue Vec = Op.getOperand(0);
10637 MVT VecVT = Vec.getSimpleValueType();
10638 SDValue Idx = Op.getOperand(1);
10639 MVT EltVT = Op.getSimpleValueType();
10641 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10643 // variable index can't be handled in mask registers,
10644 // extend vector to VR512
10645 if (!isa<ConstantSDNode>(Idx)) {
10646 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10647 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10648 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10649 ExtVT.getVectorElementType(), Ext, Idx);
10650 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10653 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10654 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10655 unsigned MaxSift = rc->getSize()*8 - 1;
10656 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10657 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10658 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10659 DAG.getConstant(MaxSift, MVT::i8));
10660 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10661 DAG.getIntPtrConstant(0));
10665 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10666 SelectionDAG &DAG) const {
10668 SDValue Vec = Op.getOperand(0);
10669 MVT VecVT = Vec.getSimpleValueType();
10670 SDValue Idx = Op.getOperand(1);
10672 if (Op.getSimpleValueType() == MVT::i1)
10673 return ExtractBitFromMaskVector(Op, DAG);
10675 if (!isa<ConstantSDNode>(Idx)) {
10676 if (VecVT.is512BitVector() ||
10677 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10678 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10681 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10682 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10683 MaskEltVT.getSizeInBits());
10685 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10686 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10687 getZeroVector(MaskVT, Subtarget, DAG, dl),
10688 Idx, DAG.getConstant(0, getPointerTy()));
10689 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10690 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10691 Perm, DAG.getConstant(0, getPointerTy()));
10696 // If this is a 256-bit vector result, first extract the 128-bit vector and
10697 // then extract the element from the 128-bit vector.
10698 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10700 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10701 // Get the 128-bit vector.
10702 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10703 MVT EltVT = VecVT.getVectorElementType();
10705 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10707 //if (IdxVal >= NumElems/2)
10708 // IdxVal -= NumElems/2;
10709 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10710 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10711 DAG.getConstant(IdxVal, MVT::i32));
10714 assert(VecVT.is128BitVector() && "Unexpected vector length");
10716 if (Subtarget->hasSSE41()) {
10717 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10722 MVT VT = Op.getSimpleValueType();
10723 // TODO: handle v16i8.
10724 if (VT.getSizeInBits() == 16) {
10725 SDValue Vec = Op.getOperand(0);
10726 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10729 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10730 DAG.getNode(ISD::BITCAST, dl,
10732 Op.getOperand(1)));
10733 // Transform it so it match pextrw which produces a 32-bit result.
10734 MVT EltVT = MVT::i32;
10735 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10736 Op.getOperand(0), Op.getOperand(1));
10737 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10738 DAG.getValueType(VT));
10739 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10742 if (VT.getSizeInBits() == 32) {
10743 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10747 // SHUFPS the element to the lowest double word, then movss.
10748 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10749 MVT VVT = Op.getOperand(0).getSimpleValueType();
10750 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10751 DAG.getUNDEF(VVT), Mask);
10752 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10753 DAG.getIntPtrConstant(0));
10756 if (VT.getSizeInBits() == 64) {
10757 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10758 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10759 // to match extract_elt for f64.
10760 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10764 // UNPCKHPD the element to the lowest double word, then movsd.
10765 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10766 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10767 int Mask[2] = { 1, -1 };
10768 MVT VVT = Op.getOperand(0).getSimpleValueType();
10769 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10770 DAG.getUNDEF(VVT), Mask);
10771 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10772 DAG.getIntPtrConstant(0));
10778 /// Insert one bit to mask vector, like v16i1 or v8i1.
10779 /// AVX-512 feature.
10781 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10783 SDValue Vec = Op.getOperand(0);
10784 SDValue Elt = Op.getOperand(1);
10785 SDValue Idx = Op.getOperand(2);
10786 MVT VecVT = Vec.getSimpleValueType();
10788 if (!isa<ConstantSDNode>(Idx)) {
10789 // Non constant index. Extend source and destination,
10790 // insert element and then truncate the result.
10791 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10792 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10793 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10794 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10795 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10796 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10799 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10800 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10801 if (Vec.getOpcode() == ISD::UNDEF)
10802 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10803 DAG.getConstant(IdxVal, MVT::i8));
10804 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10805 unsigned MaxSift = rc->getSize()*8 - 1;
10806 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10807 DAG.getConstant(MaxSift, MVT::i8));
10808 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10809 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10810 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10813 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10814 SelectionDAG &DAG) const {
10815 MVT VT = Op.getSimpleValueType();
10816 MVT EltVT = VT.getVectorElementType();
10818 if (EltVT == MVT::i1)
10819 return InsertBitToMaskVector(Op, DAG);
10822 SDValue N0 = Op.getOperand(0);
10823 SDValue N1 = Op.getOperand(1);
10824 SDValue N2 = Op.getOperand(2);
10825 if (!isa<ConstantSDNode>(N2))
10827 auto *N2C = cast<ConstantSDNode>(N2);
10828 unsigned IdxVal = N2C->getZExtValue();
10830 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10831 // into that, and then insert the subvector back into the result.
10832 if (VT.is256BitVector() || VT.is512BitVector()) {
10833 // Get the desired 128-bit vector half.
10834 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10836 // Insert the element into the desired half.
10837 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10838 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10840 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10841 DAG.getConstant(IdxIn128, MVT::i32));
10843 // Insert the changed part back to the 256-bit vector
10844 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10846 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10848 if (Subtarget->hasSSE41()) {
10849 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10851 if (VT == MVT::v8i16) {
10852 Opc = X86ISD::PINSRW;
10854 assert(VT == MVT::v16i8);
10855 Opc = X86ISD::PINSRB;
10858 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10860 if (N1.getValueType() != MVT::i32)
10861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10862 if (N2.getValueType() != MVT::i32)
10863 N2 = DAG.getIntPtrConstant(IdxVal);
10864 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10867 if (EltVT == MVT::f32) {
10868 // Bits [7:6] of the constant are the source select. This will always be
10869 // zero here. The DAG Combiner may combine an extract_elt index into
10871 // bits. For example (insert (extract, 3), 2) could be matched by
10873 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10874 // Bits [5:4] of the constant are the destination select. This is the
10875 // value of the incoming immediate.
10876 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10877 // combine either bitwise AND or insert of float 0.0 to set these bits.
10878 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10879 // Create this as a scalar to vector..
10880 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10881 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10884 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10885 // PINSR* works with constant index.
10890 if (EltVT == MVT::i8)
10893 if (EltVT.getSizeInBits() == 16) {
10894 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10895 // as its second argument.
10896 if (N1.getValueType() != MVT::i32)
10897 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10898 if (N2.getValueType() != MVT::i32)
10899 N2 = DAG.getIntPtrConstant(IdxVal);
10900 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10905 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10907 MVT OpVT = Op.getSimpleValueType();
10909 // If this is a 256-bit vector result, first insert into a 128-bit
10910 // vector and then insert into the 256-bit vector.
10911 if (!OpVT.is128BitVector()) {
10912 // Insert into a 128-bit vector.
10913 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10914 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10915 OpVT.getVectorNumElements() / SizeFactor);
10917 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10919 // Insert the 128-bit vector.
10920 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10923 if (OpVT == MVT::v1i64 &&
10924 Op.getOperand(0).getValueType() == MVT::i64)
10925 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10927 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10928 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10929 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10930 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10933 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10934 // a simple subregister reference or explicit instructions to grab
10935 // upper bits of a vector.
10936 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10937 SelectionDAG &DAG) {
10939 SDValue In = Op.getOperand(0);
10940 SDValue Idx = Op.getOperand(1);
10941 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10942 MVT ResVT = Op.getSimpleValueType();
10943 MVT InVT = In.getSimpleValueType();
10945 if (Subtarget->hasFp256()) {
10946 if (ResVT.is128BitVector() &&
10947 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10948 isa<ConstantSDNode>(Idx)) {
10949 return Extract128BitVector(In, IdxVal, DAG, dl);
10951 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10952 isa<ConstantSDNode>(Idx)) {
10953 return Extract256BitVector(In, IdxVal, DAG, dl);
10959 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10960 // simple superregister reference or explicit instructions to insert
10961 // the upper bits of a vector.
10962 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10963 SelectionDAG &DAG) {
10964 if (Subtarget->hasFp256()) {
10965 SDLoc dl(Op.getNode());
10966 SDValue Vec = Op.getNode()->getOperand(0);
10967 SDValue SubVec = Op.getNode()->getOperand(1);
10968 SDValue Idx = Op.getNode()->getOperand(2);
10970 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10971 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10972 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10973 isa<ConstantSDNode>(Idx)) {
10974 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10975 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10978 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10979 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10980 isa<ConstantSDNode>(Idx)) {
10981 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10982 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10988 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10989 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10990 // one of the above mentioned nodes. It has to be wrapped because otherwise
10991 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10992 // be used to form addressing mode. These wrapped nodes will be selected
10995 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10996 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10998 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10999 // global base reg.
11000 unsigned char OpFlag = 0;
11001 unsigned WrapperKind = X86ISD::Wrapper;
11002 CodeModel::Model M = DAG.getTarget().getCodeModel();
11004 if (Subtarget->isPICStyleRIPRel() &&
11005 (M == CodeModel::Small || M == CodeModel::Kernel))
11006 WrapperKind = X86ISD::WrapperRIP;
11007 else if (Subtarget->isPICStyleGOT())
11008 OpFlag = X86II::MO_GOTOFF;
11009 else if (Subtarget->isPICStyleStubPIC())
11010 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11012 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11013 CP->getAlignment(),
11014 CP->getOffset(), OpFlag);
11016 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11017 // With PIC, the address is actually $g + Offset.
11019 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11020 DAG.getNode(X86ISD::GlobalBaseReg,
11021 SDLoc(), getPointerTy()),
11028 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11029 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11031 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11032 // global base reg.
11033 unsigned char OpFlag = 0;
11034 unsigned WrapperKind = X86ISD::Wrapper;
11035 CodeModel::Model M = DAG.getTarget().getCodeModel();
11037 if (Subtarget->isPICStyleRIPRel() &&
11038 (M == CodeModel::Small || M == CodeModel::Kernel))
11039 WrapperKind = X86ISD::WrapperRIP;
11040 else if (Subtarget->isPICStyleGOT())
11041 OpFlag = X86II::MO_GOTOFF;
11042 else if (Subtarget->isPICStyleStubPIC())
11043 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11045 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11048 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11050 // With PIC, the address is actually $g + Offset.
11052 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11053 DAG.getNode(X86ISD::GlobalBaseReg,
11054 SDLoc(), getPointerTy()),
11061 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11062 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11064 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11065 // global base reg.
11066 unsigned char OpFlag = 0;
11067 unsigned WrapperKind = X86ISD::Wrapper;
11068 CodeModel::Model M = DAG.getTarget().getCodeModel();
11070 if (Subtarget->isPICStyleRIPRel() &&
11071 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11072 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11073 OpFlag = X86II::MO_GOTPCREL;
11074 WrapperKind = X86ISD::WrapperRIP;
11075 } else if (Subtarget->isPICStyleGOT()) {
11076 OpFlag = X86II::MO_GOT;
11077 } else if (Subtarget->isPICStyleStubPIC()) {
11078 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11079 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11080 OpFlag = X86II::MO_DARWIN_NONLAZY;
11083 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11086 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11088 // With PIC, the address is actually $g + Offset.
11089 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11090 !Subtarget->is64Bit()) {
11091 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11092 DAG.getNode(X86ISD::GlobalBaseReg,
11093 SDLoc(), getPointerTy()),
11097 // For symbols that require a load from a stub to get the address, emit the
11099 if (isGlobalStubReference(OpFlag))
11100 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11101 MachinePointerInfo::getGOT(), false, false, false, 0);
11107 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11108 // Create the TargetBlockAddressAddress node.
11109 unsigned char OpFlags =
11110 Subtarget->ClassifyBlockAddressReference();
11111 CodeModel::Model M = DAG.getTarget().getCodeModel();
11112 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11113 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11115 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11118 if (Subtarget->isPICStyleRIPRel() &&
11119 (M == CodeModel::Small || M == CodeModel::Kernel))
11120 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11122 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11124 // With PIC, the address is actually $g + Offset.
11125 if (isGlobalRelativeToPICBase(OpFlags)) {
11126 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11127 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11135 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11136 int64_t Offset, SelectionDAG &DAG) const {
11137 // Create the TargetGlobalAddress node, folding in the constant
11138 // offset if it is legal.
11139 unsigned char OpFlags =
11140 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11141 CodeModel::Model M = DAG.getTarget().getCodeModel();
11143 if (OpFlags == X86II::MO_NO_FLAG &&
11144 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11145 // A direct static reference to a global.
11146 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11149 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11152 if (Subtarget->isPICStyleRIPRel() &&
11153 (M == CodeModel::Small || M == CodeModel::Kernel))
11154 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11156 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11158 // With PIC, the address is actually $g + Offset.
11159 if (isGlobalRelativeToPICBase(OpFlags)) {
11160 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11161 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11165 // For globals that require a load from a stub to get the address, emit the
11167 if (isGlobalStubReference(OpFlags))
11168 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11169 MachinePointerInfo::getGOT(), false, false, false, 0);
11171 // If there was a non-zero offset that we didn't fold, create an explicit
11172 // addition for it.
11174 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11175 DAG.getConstant(Offset, getPointerTy()));
11181 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11182 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11183 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11184 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11188 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11189 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11190 unsigned char OperandFlags, bool LocalDynamic = false) {
11191 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11192 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11194 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11195 GA->getValueType(0),
11199 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11203 SDValue Ops[] = { Chain, TGA, *InFlag };
11204 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11206 SDValue Ops[] = { Chain, TGA };
11207 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11210 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11211 MFI->setAdjustsStack(true);
11213 SDValue Flag = Chain.getValue(1);
11214 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11217 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11219 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11222 SDLoc dl(GA); // ? function entry point might be better
11223 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11224 DAG.getNode(X86ISD::GlobalBaseReg,
11225 SDLoc(), PtrVT), InFlag);
11226 InFlag = Chain.getValue(1);
11228 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11231 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11233 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11235 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11236 X86::RAX, X86II::MO_TLSGD);
11239 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11245 // Get the start address of the TLS block for this module.
11246 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11247 .getInfo<X86MachineFunctionInfo>();
11248 MFI->incNumLocalDynamicTLSAccesses();
11252 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11253 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11256 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11257 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11258 InFlag = Chain.getValue(1);
11259 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11260 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11263 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11267 unsigned char OperandFlags = X86II::MO_DTPOFF;
11268 unsigned WrapperKind = X86ISD::Wrapper;
11269 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11270 GA->getValueType(0),
11271 GA->getOffset(), OperandFlags);
11272 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11274 // Add x@dtpoff with the base.
11275 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11278 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11279 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11280 const EVT PtrVT, TLSModel::Model model,
11281 bool is64Bit, bool isPIC) {
11284 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11285 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11286 is64Bit ? 257 : 256));
11288 SDValue ThreadPointer =
11289 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11290 MachinePointerInfo(Ptr), false, false, false, 0);
11292 unsigned char OperandFlags = 0;
11293 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11295 unsigned WrapperKind = X86ISD::Wrapper;
11296 if (model == TLSModel::LocalExec) {
11297 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11298 } else if (model == TLSModel::InitialExec) {
11300 OperandFlags = X86II::MO_GOTTPOFF;
11301 WrapperKind = X86ISD::WrapperRIP;
11303 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11306 llvm_unreachable("Unexpected model");
11309 // emit "addl x@ntpoff,%eax" (local exec)
11310 // or "addl x@indntpoff,%eax" (initial exec)
11311 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11313 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11314 GA->getOffset(), OperandFlags);
11315 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11317 if (model == TLSModel::InitialExec) {
11318 if (isPIC && !is64Bit) {
11319 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11320 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11324 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11325 MachinePointerInfo::getGOT(), false, false, false, 0);
11328 // The address of the thread local variable is the add of the thread
11329 // pointer with the offset of the variable.
11330 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11334 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11336 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11337 const GlobalValue *GV = GA->getGlobal();
11339 if (Subtarget->isTargetELF()) {
11340 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11343 case TLSModel::GeneralDynamic:
11344 if (Subtarget->is64Bit())
11345 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11346 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11347 case TLSModel::LocalDynamic:
11348 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11349 Subtarget->is64Bit());
11350 case TLSModel::InitialExec:
11351 case TLSModel::LocalExec:
11352 return LowerToTLSExecModel(
11353 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11354 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11356 llvm_unreachable("Unknown TLS model.");
11359 if (Subtarget->isTargetDarwin()) {
11360 // Darwin only has one model of TLS. Lower to that.
11361 unsigned char OpFlag = 0;
11362 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11363 X86ISD::WrapperRIP : X86ISD::Wrapper;
11365 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11366 // global base reg.
11367 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11368 !Subtarget->is64Bit();
11370 OpFlag = X86II::MO_TLVP_PIC_BASE;
11372 OpFlag = X86II::MO_TLVP;
11374 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11375 GA->getValueType(0),
11376 GA->getOffset(), OpFlag);
11377 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11379 // With PIC32, the address is actually $g + Offset.
11381 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11382 DAG.getNode(X86ISD::GlobalBaseReg,
11383 SDLoc(), getPointerTy()),
11386 // Lowering the machine isd will make sure everything is in the right
11388 SDValue Chain = DAG.getEntryNode();
11389 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11390 SDValue Args[] = { Chain, Offset };
11391 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11393 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11394 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11395 MFI->setAdjustsStack(true);
11397 // And our return value (tls address) is in the standard call return value
11399 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11400 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11401 Chain.getValue(1));
11404 if (Subtarget->isTargetKnownWindowsMSVC() ||
11405 Subtarget->isTargetWindowsGNU()) {
11406 // Just use the implicit TLS architecture
11407 // Need to generate someting similar to:
11408 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11410 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11411 // mov rcx, qword [rdx+rcx*8]
11412 // mov eax, .tls$:tlsvar
11413 // [rax+rcx] contains the address
11414 // Windows 64bit: gs:0x58
11415 // Windows 32bit: fs:__tls_array
11418 SDValue Chain = DAG.getEntryNode();
11420 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11421 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11422 // use its literal value of 0x2C.
11423 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11424 ? Type::getInt8PtrTy(*DAG.getContext(),
11426 : Type::getInt32PtrTy(*DAG.getContext(),
11430 Subtarget->is64Bit()
11431 ? DAG.getIntPtrConstant(0x58)
11432 : (Subtarget->isTargetWindowsGNU()
11433 ? DAG.getIntPtrConstant(0x2C)
11434 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11436 SDValue ThreadPointer =
11437 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11438 MachinePointerInfo(Ptr), false, false, false, 0);
11440 // Load the _tls_index variable
11441 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11442 if (Subtarget->is64Bit())
11443 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11444 IDX, MachinePointerInfo(), MVT::i32,
11445 false, false, false, 0);
11447 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11448 false, false, false, 0);
11450 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11452 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11454 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11455 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11456 false, false, false, 0);
11458 // Get the offset of start of .tls section
11459 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11460 GA->getValueType(0),
11461 GA->getOffset(), X86II::MO_SECREL);
11462 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11464 // The address of the thread local variable is the add of the thread
11465 // pointer with the offset of the variable.
11466 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11469 llvm_unreachable("TLS not implemented for this target.");
11472 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11473 /// and take a 2 x i32 value to shift plus a shift amount.
11474 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11475 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11476 MVT VT = Op.getSimpleValueType();
11477 unsigned VTBits = VT.getSizeInBits();
11479 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11480 SDValue ShOpLo = Op.getOperand(0);
11481 SDValue ShOpHi = Op.getOperand(1);
11482 SDValue ShAmt = Op.getOperand(2);
11483 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11484 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11486 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11487 DAG.getConstant(VTBits - 1, MVT::i8));
11488 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11489 DAG.getConstant(VTBits - 1, MVT::i8))
11490 : DAG.getConstant(0, VT);
11492 SDValue Tmp2, Tmp3;
11493 if (Op.getOpcode() == ISD::SHL_PARTS) {
11494 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11495 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11497 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11498 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11501 // If the shift amount is larger or equal than the width of a part we can't
11502 // rely on the results of shld/shrd. Insert a test and select the appropriate
11503 // values for large shift amounts.
11504 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11505 DAG.getConstant(VTBits, MVT::i8));
11506 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11507 AndNode, DAG.getConstant(0, MVT::i8));
11510 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11511 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11512 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11514 if (Op.getOpcode() == ISD::SHL_PARTS) {
11515 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11516 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11518 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11519 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11522 SDValue Ops[2] = { Lo, Hi };
11523 return DAG.getMergeValues(Ops, dl);
11526 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11527 SelectionDAG &DAG) const {
11528 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11530 if (SrcVT.isVector())
11533 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11534 "Unknown SINT_TO_FP to lower!");
11536 // These are really Legal; return the operand so the caller accepts it as
11538 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11540 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11541 Subtarget->is64Bit()) {
11546 unsigned Size = SrcVT.getSizeInBits()/8;
11547 MachineFunction &MF = DAG.getMachineFunction();
11548 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11549 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11550 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11552 MachinePointerInfo::getFixedStack(SSFI),
11554 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11557 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11559 SelectionDAG &DAG) const {
11563 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11565 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11567 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11569 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11571 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11572 MachineMemOperand *MMO;
11574 int SSFI = FI->getIndex();
11576 DAG.getMachineFunction()
11577 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11578 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11580 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11581 StackSlot = StackSlot.getOperand(1);
11583 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11584 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11586 Tys, Ops, SrcVT, MMO);
11589 Chain = Result.getValue(1);
11590 SDValue InFlag = Result.getValue(2);
11592 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11593 // shouldn't be necessary except that RFP cannot be live across
11594 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11595 MachineFunction &MF = DAG.getMachineFunction();
11596 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11597 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11598 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11599 Tys = DAG.getVTList(MVT::Other);
11601 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11603 MachineMemOperand *MMO =
11604 DAG.getMachineFunction()
11605 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11606 MachineMemOperand::MOStore, SSFISize, SSFISize);
11608 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11609 Ops, Op.getValueType(), MMO);
11610 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11611 MachinePointerInfo::getFixedStack(SSFI),
11612 false, false, false, 0);
11618 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11619 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11620 SelectionDAG &DAG) const {
11621 // This algorithm is not obvious. Here it is what we're trying to output:
11624 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11625 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11627 haddpd %xmm0, %xmm0
11629 pshufd $0x4e, %xmm0, %xmm1
11635 LLVMContext *Context = DAG.getContext();
11637 // Build some magic constants.
11638 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11639 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11640 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11642 SmallVector<Constant*,2> CV1;
11644 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11645 APInt(64, 0x4330000000000000ULL))));
11647 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11648 APInt(64, 0x4530000000000000ULL))));
11649 Constant *C1 = ConstantVector::get(CV1);
11650 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11652 // Load the 64-bit value into an XMM register.
11653 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11655 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11656 MachinePointerInfo::getConstantPool(),
11657 false, false, false, 16);
11658 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11659 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11662 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11663 MachinePointerInfo::getConstantPool(),
11664 false, false, false, 16);
11665 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11666 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11669 if (Subtarget->hasSSE3()) {
11670 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11671 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11673 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11674 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11676 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11677 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11681 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11682 DAG.getIntPtrConstant(0));
11685 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11686 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11687 SelectionDAG &DAG) const {
11689 // FP constant to bias correct the final result.
11690 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11693 // Load the 32-bit value into an XMM register.
11694 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11697 // Zero out the upper parts of the register.
11698 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11700 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11701 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11702 DAG.getIntPtrConstant(0));
11704 // Or the load with the bias.
11705 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11706 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11707 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11708 MVT::v2f64, Load)),
11709 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11710 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11711 MVT::v2f64, Bias)));
11712 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11713 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11714 DAG.getIntPtrConstant(0));
11716 // Subtract the bias.
11717 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11719 // Handle final rounding.
11720 EVT DestVT = Op.getValueType();
11722 if (DestVT.bitsLT(MVT::f64))
11723 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11724 DAG.getIntPtrConstant(0));
11725 if (DestVT.bitsGT(MVT::f64))
11726 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11728 // Handle final rounding.
11732 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11733 SelectionDAG &DAG) const {
11734 SDValue N0 = Op.getOperand(0);
11735 MVT SVT = N0.getSimpleValueType();
11738 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11739 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11740 "Custom UINT_TO_FP is not supported!");
11742 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11743 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11744 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11747 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11748 SelectionDAG &DAG) const {
11749 SDValue N0 = Op.getOperand(0);
11752 if (Op.getValueType().isVector())
11753 return lowerUINT_TO_FP_vec(Op, DAG);
11755 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11756 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11757 // the optimization here.
11758 if (DAG.SignBitIsZero(N0))
11759 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11761 MVT SrcVT = N0.getSimpleValueType();
11762 MVT DstVT = Op.getSimpleValueType();
11763 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11764 return LowerUINT_TO_FP_i64(Op, DAG);
11765 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11766 return LowerUINT_TO_FP_i32(Op, DAG);
11767 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11770 // Make a 64-bit buffer, and use it to build an FILD.
11771 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11772 if (SrcVT == MVT::i32) {
11773 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11774 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11775 getPointerTy(), StackSlot, WordOff);
11776 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11777 StackSlot, MachinePointerInfo(),
11779 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11780 OffsetSlot, MachinePointerInfo(),
11782 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11786 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11787 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11788 StackSlot, MachinePointerInfo(),
11790 // For i64 source, we need to add the appropriate power of 2 if the input
11791 // was negative. This is the same as the optimization in
11792 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11793 // we must be careful to do the computation in x87 extended precision, not
11794 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11795 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11796 MachineMemOperand *MMO =
11797 DAG.getMachineFunction()
11798 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11799 MachineMemOperand::MOLoad, 8, 8);
11801 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11802 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11803 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11806 APInt FF(32, 0x5F800000ULL);
11808 // Check whether the sign bit is set.
11809 SDValue SignSet = DAG.getSetCC(dl,
11810 getSetCCResultType(*DAG.getContext(), MVT::i64),
11811 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11814 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11815 SDValue FudgePtr = DAG.getConstantPool(
11816 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11819 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11820 SDValue Zero = DAG.getIntPtrConstant(0);
11821 SDValue Four = DAG.getIntPtrConstant(4);
11822 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11824 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11826 // Load the value out, extending it from f32 to f80.
11827 // FIXME: Avoid the extend by constructing the right constant pool?
11828 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11829 FudgePtr, MachinePointerInfo::getConstantPool(),
11830 MVT::f32, false, false, false, 4);
11831 // Extend everything to 80 bits to force it to be done on x87.
11832 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11833 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11836 std::pair<SDValue,SDValue>
11837 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11838 bool IsSigned, bool IsReplace) const {
11841 EVT DstTy = Op.getValueType();
11843 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11844 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11848 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11849 DstTy.getSimpleVT() >= MVT::i16 &&
11850 "Unknown FP_TO_INT to lower!");
11852 // These are really Legal.
11853 if (DstTy == MVT::i32 &&
11854 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11855 return std::make_pair(SDValue(), SDValue());
11856 if (Subtarget->is64Bit() &&
11857 DstTy == MVT::i64 &&
11858 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11859 return std::make_pair(SDValue(), SDValue());
11861 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11862 // stack slot, or into the FTOL runtime function.
11863 MachineFunction &MF = DAG.getMachineFunction();
11864 unsigned MemSize = DstTy.getSizeInBits()/8;
11865 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11866 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11869 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11870 Opc = X86ISD::WIN_FTOL;
11872 switch (DstTy.getSimpleVT().SimpleTy) {
11873 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11874 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11875 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11876 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11879 SDValue Chain = DAG.getEntryNode();
11880 SDValue Value = Op.getOperand(0);
11881 EVT TheVT = Op.getOperand(0).getValueType();
11882 // FIXME This causes a redundant load/store if the SSE-class value is already
11883 // in memory, such as if it is on the callstack.
11884 if (isScalarFPTypeInSSEReg(TheVT)) {
11885 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11886 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11887 MachinePointerInfo::getFixedStack(SSFI),
11889 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11891 Chain, StackSlot, DAG.getValueType(TheVT)
11894 MachineMemOperand *MMO =
11895 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11896 MachineMemOperand::MOLoad, MemSize, MemSize);
11897 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11898 Chain = Value.getValue(1);
11899 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11900 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11903 MachineMemOperand *MMO =
11904 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11905 MachineMemOperand::MOStore, MemSize, MemSize);
11907 if (Opc != X86ISD::WIN_FTOL) {
11908 // Build the FP_TO_INT*_IN_MEM
11909 SDValue Ops[] = { Chain, Value, StackSlot };
11910 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11912 return std::make_pair(FIST, StackSlot);
11914 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11915 DAG.getVTList(MVT::Other, MVT::Glue),
11917 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11918 MVT::i32, ftol.getValue(1));
11919 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11920 MVT::i32, eax.getValue(2));
11921 SDValue Ops[] = { eax, edx };
11922 SDValue pair = IsReplace
11923 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11924 : DAG.getMergeValues(Ops, DL);
11925 return std::make_pair(pair, SDValue());
11929 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11930 const X86Subtarget *Subtarget) {
11931 MVT VT = Op->getSimpleValueType(0);
11932 SDValue In = Op->getOperand(0);
11933 MVT InVT = In.getSimpleValueType();
11936 // Optimize vectors in AVX mode:
11939 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11940 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11941 // Concat upper and lower parts.
11944 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11945 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11946 // Concat upper and lower parts.
11949 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11950 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11951 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11954 if (Subtarget->hasInt256())
11955 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11957 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11958 SDValue Undef = DAG.getUNDEF(InVT);
11959 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11960 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11961 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11963 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11964 VT.getVectorNumElements()/2);
11966 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11967 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11969 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11972 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11973 SelectionDAG &DAG) {
11974 MVT VT = Op->getSimpleValueType(0);
11975 SDValue In = Op->getOperand(0);
11976 MVT InVT = In.getSimpleValueType();
11978 unsigned int NumElts = VT.getVectorNumElements();
11979 if (NumElts != 8 && NumElts != 16)
11982 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11983 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11985 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11986 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11987 // Now we have only mask extension
11988 assert(InVT.getVectorElementType() == MVT::i1);
11989 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11990 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11991 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11992 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11993 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11994 MachinePointerInfo::getConstantPool(),
11995 false, false, false, Alignment);
11997 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11998 if (VT.is512BitVector())
12000 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12003 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12004 SelectionDAG &DAG) {
12005 if (Subtarget->hasFp256()) {
12006 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12014 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12015 SelectionDAG &DAG) {
12017 MVT VT = Op.getSimpleValueType();
12018 SDValue In = Op.getOperand(0);
12019 MVT SVT = In.getSimpleValueType();
12021 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12022 return LowerZERO_EXTEND_AVX512(Op, DAG);
12024 if (Subtarget->hasFp256()) {
12025 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12030 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12031 VT.getVectorNumElements() != SVT.getVectorNumElements());
12035 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12037 MVT VT = Op.getSimpleValueType();
12038 SDValue In = Op.getOperand(0);
12039 MVT InVT = In.getSimpleValueType();
12041 if (VT == MVT::i1) {
12042 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12043 "Invalid scalar TRUNCATE operation");
12044 if (InVT.getSizeInBits() >= 32)
12046 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12047 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12049 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12050 "Invalid TRUNCATE operation");
12052 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12053 if (VT.getVectorElementType().getSizeInBits() >=8)
12054 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12056 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12057 unsigned NumElts = InVT.getVectorNumElements();
12058 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12059 if (InVT.getSizeInBits() < 512) {
12060 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12061 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12065 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12066 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12067 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12068 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12069 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12070 MachinePointerInfo::getConstantPool(),
12071 false, false, false, Alignment);
12072 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12073 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12074 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12077 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12078 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12079 if (Subtarget->hasInt256()) {
12080 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12081 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12082 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12084 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12085 DAG.getIntPtrConstant(0));
12088 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12089 DAG.getIntPtrConstant(0));
12090 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12091 DAG.getIntPtrConstant(2));
12092 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12093 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12094 static const int ShufMask[] = {0, 2, 4, 6};
12095 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12098 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12099 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12100 if (Subtarget->hasInt256()) {
12101 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12103 SmallVector<SDValue,32> pshufbMask;
12104 for (unsigned i = 0; i < 2; ++i) {
12105 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12106 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12107 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12108 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12109 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12110 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12111 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12112 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12113 for (unsigned j = 0; j < 8; ++j)
12114 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12116 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12117 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12118 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12120 static const int ShufMask[] = {0, 2, -1, -1};
12121 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12123 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12124 DAG.getIntPtrConstant(0));
12125 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12128 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12129 DAG.getIntPtrConstant(0));
12131 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12132 DAG.getIntPtrConstant(4));
12134 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12135 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12137 // The PSHUFB mask:
12138 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12139 -1, -1, -1, -1, -1, -1, -1, -1};
12141 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12142 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12143 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12145 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12146 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12148 // The MOVLHPS Mask:
12149 static const int ShufMask2[] = {0, 1, 4, 5};
12150 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12151 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12154 // Handle truncation of V256 to V128 using shuffles.
12155 if (!VT.is128BitVector() || !InVT.is256BitVector())
12158 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12160 unsigned NumElems = VT.getVectorNumElements();
12161 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12163 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12164 // Prepare truncation shuffle mask
12165 for (unsigned i = 0; i != NumElems; ++i)
12166 MaskVec[i] = i * 2;
12167 SDValue V = DAG.getVectorShuffle(NVT, DL,
12168 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12169 DAG.getUNDEF(NVT), &MaskVec[0]);
12170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12171 DAG.getIntPtrConstant(0));
12174 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12175 SelectionDAG &DAG) const {
12176 assert(!Op.getSimpleValueType().isVector());
12178 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12179 /*IsSigned=*/ true, /*IsReplace=*/ false);
12180 SDValue FIST = Vals.first, StackSlot = Vals.second;
12181 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12182 if (!FIST.getNode()) return Op;
12184 if (StackSlot.getNode())
12185 // Load the result.
12186 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12187 FIST, StackSlot, MachinePointerInfo(),
12188 false, false, false, 0);
12190 // The node is the result.
12194 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12195 SelectionDAG &DAG) const {
12196 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12197 /*IsSigned=*/ false, /*IsReplace=*/ false);
12198 SDValue FIST = Vals.first, StackSlot = Vals.second;
12199 assert(FIST.getNode() && "Unexpected failure");
12201 if (StackSlot.getNode())
12202 // Load the result.
12203 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12204 FIST, StackSlot, MachinePointerInfo(),
12205 false, false, false, 0);
12207 // The node is the result.
12211 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12213 MVT VT = Op.getSimpleValueType();
12214 SDValue In = Op.getOperand(0);
12215 MVT SVT = In.getSimpleValueType();
12217 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12219 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12220 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12221 In, DAG.getUNDEF(SVT)));
12224 // The only differences between FABS and FNEG are the mask and the logic op.
12225 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12226 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12227 "Wrong opcode for lowering FABS or FNEG.");
12229 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12231 MVT VT = Op.getSimpleValueType();
12232 // Assume scalar op for initialization; update for vector if needed.
12233 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12234 // generate a 16-byte vector constant and logic op even for the scalar case.
12235 // Using a 16-byte mask allows folding the load of the mask with
12236 // the logic op, so it can save (~4 bytes) on code size.
12238 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12239 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12240 // decide if we should generate a 16-byte constant mask when we only need 4 or
12241 // 8 bytes for the scalar case.
12242 if (VT.isVector()) {
12243 EltVT = VT.getVectorElementType();
12244 NumElts = VT.getVectorNumElements();
12247 unsigned EltBits = EltVT.getSizeInBits();
12248 LLVMContext *Context = DAG.getContext();
12249 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12251 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12252 Constant *C = ConstantInt::get(*Context, MaskElt);
12253 C = ConstantVector::getSplat(NumElts, C);
12254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12255 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12256 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12257 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12258 MachinePointerInfo::getConstantPool(),
12259 false, false, false, Alignment);
12261 if (VT.isVector()) {
12262 // For a vector, cast operands to a vector type, perform the logic op,
12263 // and cast the result back to the original value type.
12264 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12265 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
12266 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12267 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
12268 return DAG.getNode(ISD::BITCAST, dl, VT,
12269 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
12271 // If not vector, then scalar.
12272 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
12273 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
12276 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12278 LLVMContext *Context = DAG.getContext();
12279 SDValue Op0 = Op.getOperand(0);
12280 SDValue Op1 = Op.getOperand(1);
12282 MVT VT = Op.getSimpleValueType();
12283 MVT SrcVT = Op1.getSimpleValueType();
12285 // If second operand is smaller, extend it first.
12286 if (SrcVT.bitsLT(VT)) {
12287 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12290 // And if it is bigger, shrink it first.
12291 if (SrcVT.bitsGT(VT)) {
12292 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12296 // At this point the operands and the result should have the same
12297 // type, and that won't be f80 since that is not custom lowered.
12299 // First get the sign bit of second operand.
12300 SmallVector<Constant*,4> CV;
12301 if (SrcVT == MVT::f64) {
12302 const fltSemantics &Sem = APFloat::IEEEdouble;
12303 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12304 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12306 const fltSemantics &Sem = APFloat::IEEEsingle;
12307 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12308 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12309 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12310 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12312 Constant *C = ConstantVector::get(CV);
12313 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12314 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12315 MachinePointerInfo::getConstantPool(),
12316 false, false, false, 16);
12317 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12319 // Shift sign bit right or left if the two operands have different types.
12320 if (SrcVT.bitsGT(VT)) {
12321 // Op0 is MVT::f32, Op1 is MVT::f64.
12322 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12323 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12324 DAG.getConstant(32, MVT::i32));
12325 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12326 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12327 DAG.getIntPtrConstant(0));
12330 // Clear first operand sign bit.
12332 if (VT == MVT::f64) {
12333 const fltSemantics &Sem = APFloat::IEEEdouble;
12334 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12335 APInt(64, ~(1ULL << 63)))));
12336 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12338 const fltSemantics &Sem = APFloat::IEEEsingle;
12339 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12340 APInt(32, ~(1U << 31)))));
12341 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12342 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12343 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12345 C = ConstantVector::get(CV);
12346 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12347 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12348 MachinePointerInfo::getConstantPool(),
12349 false, false, false, 16);
12350 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12352 // Or the value with the sign bit.
12353 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12356 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12357 SDValue N0 = Op.getOperand(0);
12359 MVT VT = Op.getSimpleValueType();
12361 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12362 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12363 DAG.getConstant(1, VT));
12364 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12367 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12369 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12370 SelectionDAG &DAG) {
12371 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12373 if (!Subtarget->hasSSE41())
12376 if (!Op->hasOneUse())
12379 SDNode *N = Op.getNode();
12382 SmallVector<SDValue, 8> Opnds;
12383 DenseMap<SDValue, unsigned> VecInMap;
12384 SmallVector<SDValue, 8> VecIns;
12385 EVT VT = MVT::Other;
12387 // Recognize a special case where a vector is casted into wide integer to
12389 Opnds.push_back(N->getOperand(0));
12390 Opnds.push_back(N->getOperand(1));
12392 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12393 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12394 // BFS traverse all OR'd operands.
12395 if (I->getOpcode() == ISD::OR) {
12396 Opnds.push_back(I->getOperand(0));
12397 Opnds.push_back(I->getOperand(1));
12398 // Re-evaluate the number of nodes to be traversed.
12399 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12403 // Quit if a non-EXTRACT_VECTOR_ELT
12404 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12407 // Quit if without a constant index.
12408 SDValue Idx = I->getOperand(1);
12409 if (!isa<ConstantSDNode>(Idx))
12412 SDValue ExtractedFromVec = I->getOperand(0);
12413 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12414 if (M == VecInMap.end()) {
12415 VT = ExtractedFromVec.getValueType();
12416 // Quit if not 128/256-bit vector.
12417 if (!VT.is128BitVector() && !VT.is256BitVector())
12419 // Quit if not the same type.
12420 if (VecInMap.begin() != VecInMap.end() &&
12421 VT != VecInMap.begin()->first.getValueType())
12423 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12424 VecIns.push_back(ExtractedFromVec);
12426 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12429 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12430 "Not extracted from 128-/256-bit vector.");
12432 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12434 for (DenseMap<SDValue, unsigned>::const_iterator
12435 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12436 // Quit if not all elements are used.
12437 if (I->second != FullMask)
12441 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12443 // Cast all vectors into TestVT for PTEST.
12444 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12445 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12447 // If more than one full vectors are evaluated, OR them first before PTEST.
12448 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12449 // Each iteration will OR 2 nodes and append the result until there is only
12450 // 1 node left, i.e. the final OR'd value of all vectors.
12451 SDValue LHS = VecIns[Slot];
12452 SDValue RHS = VecIns[Slot + 1];
12453 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12456 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12457 VecIns.back(), VecIns.back());
12460 /// \brief return true if \c Op has a use that doesn't just read flags.
12461 static bool hasNonFlagsUse(SDValue Op) {
12462 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12464 SDNode *User = *UI;
12465 unsigned UOpNo = UI.getOperandNo();
12466 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12467 // Look pass truncate.
12468 UOpNo = User->use_begin().getOperandNo();
12469 User = *User->use_begin();
12472 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12473 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12479 /// Emit nodes that will be selected as "test Op0,Op0", or something
12481 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12482 SelectionDAG &DAG) const {
12483 if (Op.getValueType() == MVT::i1)
12484 // KORTEST instruction should be selected
12485 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12486 DAG.getConstant(0, Op.getValueType()));
12488 // CF and OF aren't always set the way we want. Determine which
12489 // of these we need.
12490 bool NeedCF = false;
12491 bool NeedOF = false;
12494 case X86::COND_A: case X86::COND_AE:
12495 case X86::COND_B: case X86::COND_BE:
12498 case X86::COND_G: case X86::COND_GE:
12499 case X86::COND_L: case X86::COND_LE:
12500 case X86::COND_O: case X86::COND_NO: {
12501 // Check if we really need to set the
12502 // Overflow flag. If NoSignedWrap is present
12503 // that is not actually needed.
12504 switch (Op->getOpcode()) {
12509 const BinaryWithFlagsSDNode *BinNode =
12510 cast<BinaryWithFlagsSDNode>(Op.getNode());
12511 if (BinNode->hasNoSignedWrap())
12521 // See if we can use the EFLAGS value from the operand instead of
12522 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12523 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12524 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12525 // Emit a CMP with 0, which is the TEST pattern.
12526 //if (Op.getValueType() == MVT::i1)
12527 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12528 // DAG.getConstant(0, MVT::i1));
12529 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12530 DAG.getConstant(0, Op.getValueType()));
12532 unsigned Opcode = 0;
12533 unsigned NumOperands = 0;
12535 // Truncate operations may prevent the merge of the SETCC instruction
12536 // and the arithmetic instruction before it. Attempt to truncate the operands
12537 // of the arithmetic instruction and use a reduced bit-width instruction.
12538 bool NeedTruncation = false;
12539 SDValue ArithOp = Op;
12540 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12541 SDValue Arith = Op->getOperand(0);
12542 // Both the trunc and the arithmetic op need to have one user each.
12543 if (Arith->hasOneUse())
12544 switch (Arith.getOpcode()) {
12551 NeedTruncation = true;
12557 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12558 // which may be the result of a CAST. We use the variable 'Op', which is the
12559 // non-casted variable when we check for possible users.
12560 switch (ArithOp.getOpcode()) {
12562 // Due to an isel shortcoming, be conservative if this add is likely to be
12563 // selected as part of a load-modify-store instruction. When the root node
12564 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12565 // uses of other nodes in the match, such as the ADD in this case. This
12566 // leads to the ADD being left around and reselected, with the result being
12567 // two adds in the output. Alas, even if none our users are stores, that
12568 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12569 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12570 // climbing the DAG back to the root, and it doesn't seem to be worth the
12572 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12573 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12574 if (UI->getOpcode() != ISD::CopyToReg &&
12575 UI->getOpcode() != ISD::SETCC &&
12576 UI->getOpcode() != ISD::STORE)
12579 if (ConstantSDNode *C =
12580 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12581 // An add of one will be selected as an INC.
12582 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12583 Opcode = X86ISD::INC;
12588 // An add of negative one (subtract of one) will be selected as a DEC.
12589 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12590 Opcode = X86ISD::DEC;
12596 // Otherwise use a regular EFLAGS-setting add.
12597 Opcode = X86ISD::ADD;
12602 // If we have a constant logical shift that's only used in a comparison
12603 // against zero turn it into an equivalent AND. This allows turning it into
12604 // a TEST instruction later.
12605 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12606 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12607 EVT VT = Op.getValueType();
12608 unsigned BitWidth = VT.getSizeInBits();
12609 unsigned ShAmt = Op->getConstantOperandVal(1);
12610 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12612 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12613 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12614 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12615 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12617 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12618 DAG.getConstant(Mask, VT));
12619 DAG.ReplaceAllUsesWith(Op, New);
12625 // If the primary and result isn't used, don't bother using X86ISD::AND,
12626 // because a TEST instruction will be better.
12627 if (!hasNonFlagsUse(Op))
12633 // Due to the ISEL shortcoming noted above, be conservative if this op is
12634 // likely to be selected as part of a load-modify-store instruction.
12635 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12636 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12637 if (UI->getOpcode() == ISD::STORE)
12640 // Otherwise use a regular EFLAGS-setting instruction.
12641 switch (ArithOp.getOpcode()) {
12642 default: llvm_unreachable("unexpected operator!");
12643 case ISD::SUB: Opcode = X86ISD::SUB; break;
12644 case ISD::XOR: Opcode = X86ISD::XOR; break;
12645 case ISD::AND: Opcode = X86ISD::AND; break;
12647 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12648 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12649 if (EFLAGS.getNode())
12652 Opcode = X86ISD::OR;
12666 return SDValue(Op.getNode(), 1);
12672 // If we found that truncation is beneficial, perform the truncation and
12674 if (NeedTruncation) {
12675 EVT VT = Op.getValueType();
12676 SDValue WideVal = Op->getOperand(0);
12677 EVT WideVT = WideVal.getValueType();
12678 unsigned ConvertedOp = 0;
12679 // Use a target machine opcode to prevent further DAGCombine
12680 // optimizations that may separate the arithmetic operations
12681 // from the setcc node.
12682 switch (WideVal.getOpcode()) {
12684 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12685 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12686 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12687 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12688 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12692 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12693 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12694 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12695 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12696 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12702 // Emit a CMP with 0, which is the TEST pattern.
12703 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12704 DAG.getConstant(0, Op.getValueType()));
12706 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12707 SmallVector<SDValue, 4> Ops;
12708 for (unsigned i = 0; i != NumOperands; ++i)
12709 Ops.push_back(Op.getOperand(i));
12711 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12712 DAG.ReplaceAllUsesWith(Op, New);
12713 return SDValue(New.getNode(), 1);
12716 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12718 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12719 SDLoc dl, SelectionDAG &DAG) const {
12720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12721 if (C->getAPIntValue() == 0)
12722 return EmitTest(Op0, X86CC, dl, DAG);
12724 if (Op0.getValueType() == MVT::i1)
12725 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12728 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12729 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12730 // Do the comparison at i32 if it's smaller, besides the Atom case.
12731 // This avoids subregister aliasing issues. Keep the smaller reference
12732 // if we're optimizing for size, however, as that'll allow better folding
12733 // of memory operations.
12734 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12735 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12736 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12737 !Subtarget->isAtom()) {
12738 unsigned ExtendOp =
12739 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12740 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12741 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12743 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12744 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12745 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12747 return SDValue(Sub.getNode(), 1);
12749 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12752 /// Convert a comparison if required by the subtarget.
12753 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12754 SelectionDAG &DAG) const {
12755 // If the subtarget does not support the FUCOMI instruction, floating-point
12756 // comparisons have to be converted.
12757 if (Subtarget->hasCMov() ||
12758 Cmp.getOpcode() != X86ISD::CMP ||
12759 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12760 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12763 // The instruction selector will select an FUCOM instruction instead of
12764 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12765 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12766 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12768 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12769 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12770 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12771 DAG.getConstant(8, MVT::i8));
12772 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12773 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12776 static bool isAllOnes(SDValue V) {
12777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12778 return C && C->isAllOnesValue();
12781 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12782 /// if it's possible.
12783 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12784 SDLoc dl, SelectionDAG &DAG) const {
12785 SDValue Op0 = And.getOperand(0);
12786 SDValue Op1 = And.getOperand(1);
12787 if (Op0.getOpcode() == ISD::TRUNCATE)
12788 Op0 = Op0.getOperand(0);
12789 if (Op1.getOpcode() == ISD::TRUNCATE)
12790 Op1 = Op1.getOperand(0);
12793 if (Op1.getOpcode() == ISD::SHL)
12794 std::swap(Op0, Op1);
12795 if (Op0.getOpcode() == ISD::SHL) {
12796 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12797 if (And00C->getZExtValue() == 1) {
12798 // If we looked past a truncate, check that it's only truncating away
12800 unsigned BitWidth = Op0.getValueSizeInBits();
12801 unsigned AndBitWidth = And.getValueSizeInBits();
12802 if (BitWidth > AndBitWidth) {
12804 DAG.computeKnownBits(Op0, Zeros, Ones);
12805 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12809 RHS = Op0.getOperand(1);
12811 } else if (Op1.getOpcode() == ISD::Constant) {
12812 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12813 uint64_t AndRHSVal = AndRHS->getZExtValue();
12814 SDValue AndLHS = Op0;
12816 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12817 LHS = AndLHS.getOperand(0);
12818 RHS = AndLHS.getOperand(1);
12821 // Use BT if the immediate can't be encoded in a TEST instruction.
12822 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12824 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12828 if (LHS.getNode()) {
12829 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12830 // instruction. Since the shift amount is in-range-or-undefined, we know
12831 // that doing a bittest on the i32 value is ok. We extend to i32 because
12832 // the encoding for the i16 version is larger than the i32 version.
12833 // Also promote i16 to i32 for performance / code size reason.
12834 if (LHS.getValueType() == MVT::i8 ||
12835 LHS.getValueType() == MVT::i16)
12836 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12838 // If the operand types disagree, extend the shift amount to match. Since
12839 // BT ignores high bits (like shifts) we can use anyextend.
12840 if (LHS.getValueType() != RHS.getValueType())
12841 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12843 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12844 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12845 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12846 DAG.getConstant(Cond, MVT::i8), BT);
12852 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12854 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12859 // SSE Condition code mapping:
12868 switch (SetCCOpcode) {
12869 default: llvm_unreachable("Unexpected SETCC condition");
12871 case ISD::SETEQ: SSECC = 0; break;
12873 case ISD::SETGT: Swap = true; // Fallthrough
12875 case ISD::SETOLT: SSECC = 1; break;
12877 case ISD::SETGE: Swap = true; // Fallthrough
12879 case ISD::SETOLE: SSECC = 2; break;
12880 case ISD::SETUO: SSECC = 3; break;
12882 case ISD::SETNE: SSECC = 4; break;
12883 case ISD::SETULE: Swap = true; // Fallthrough
12884 case ISD::SETUGE: SSECC = 5; break;
12885 case ISD::SETULT: Swap = true; // Fallthrough
12886 case ISD::SETUGT: SSECC = 6; break;
12887 case ISD::SETO: SSECC = 7; break;
12889 case ISD::SETONE: SSECC = 8; break;
12892 std::swap(Op0, Op1);
12897 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12898 // ones, and then concatenate the result back.
12899 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12900 MVT VT = Op.getSimpleValueType();
12902 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12903 "Unsupported value type for operation");
12905 unsigned NumElems = VT.getVectorNumElements();
12907 SDValue CC = Op.getOperand(2);
12909 // Extract the LHS vectors
12910 SDValue LHS = Op.getOperand(0);
12911 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12912 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12914 // Extract the RHS vectors
12915 SDValue RHS = Op.getOperand(1);
12916 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12917 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12919 // Issue the operation on the smaller types and concatenate the result back
12920 MVT EltVT = VT.getVectorElementType();
12921 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12922 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12923 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12924 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12927 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12928 const X86Subtarget *Subtarget) {
12929 SDValue Op0 = Op.getOperand(0);
12930 SDValue Op1 = Op.getOperand(1);
12931 SDValue CC = Op.getOperand(2);
12932 MVT VT = Op.getSimpleValueType();
12935 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
12936 Op.getValueType().getScalarType() == MVT::i1 &&
12937 "Cannot set masked compare for this operation");
12939 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12941 bool Unsigned = false;
12944 switch (SetCCOpcode) {
12945 default: llvm_unreachable("Unexpected SETCC condition");
12946 case ISD::SETNE: SSECC = 4; break;
12947 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12948 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12949 case ISD::SETLT: Swap = true; //fall-through
12950 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12951 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12952 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12953 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12954 case ISD::SETULE: Unsigned = true; //fall-through
12955 case ISD::SETLE: SSECC = 2; break;
12959 std::swap(Op0, Op1);
12961 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12962 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12963 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12964 DAG.getConstant(SSECC, MVT::i8));
12967 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12968 /// operand \p Op1. If non-trivial (for example because it's not constant)
12969 /// return an empty value.
12970 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12972 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12976 MVT VT = Op1.getSimpleValueType();
12977 MVT EVT = VT.getVectorElementType();
12978 unsigned n = VT.getVectorNumElements();
12979 SmallVector<SDValue, 8> ULTOp1;
12981 for (unsigned i = 0; i < n; ++i) {
12982 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12983 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12986 // Avoid underflow.
12987 APInt Val = Elt->getAPIntValue();
12991 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12994 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12997 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12998 SelectionDAG &DAG) {
12999 SDValue Op0 = Op.getOperand(0);
13000 SDValue Op1 = Op.getOperand(1);
13001 SDValue CC = Op.getOperand(2);
13002 MVT VT = Op.getSimpleValueType();
13003 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13004 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13009 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13010 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13013 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13014 unsigned Opc = X86ISD::CMPP;
13015 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13016 assert(VT.getVectorNumElements() <= 16);
13017 Opc = X86ISD::CMPM;
13019 // In the two special cases we can't handle, emit two comparisons.
13022 unsigned CombineOpc;
13023 if (SetCCOpcode == ISD::SETUEQ) {
13024 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13026 assert(SetCCOpcode == ISD::SETONE);
13027 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13030 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13031 DAG.getConstant(CC0, MVT::i8));
13032 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13033 DAG.getConstant(CC1, MVT::i8));
13034 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13036 // Handle all other FP comparisons here.
13037 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13038 DAG.getConstant(SSECC, MVT::i8));
13041 // Break 256-bit integer vector compare into smaller ones.
13042 if (VT.is256BitVector() && !Subtarget->hasInt256())
13043 return Lower256IntVSETCC(Op, DAG);
13045 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13046 EVT OpVT = Op1.getValueType();
13047 if (Subtarget->hasAVX512()) {
13048 if (Op1.getValueType().is512BitVector() ||
13049 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13050 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13051 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13053 // In AVX-512 architecture setcc returns mask with i1 elements,
13054 // But there is no compare instruction for i8 and i16 elements in KNL.
13055 // We are not talking about 512-bit operands in this case, these
13056 // types are illegal.
13058 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13059 OpVT.getVectorElementType().getSizeInBits() >= 8))
13060 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13061 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13064 // We are handling one of the integer comparisons here. Since SSE only has
13065 // GT and EQ comparisons for integer, swapping operands and multiple
13066 // operations may be required for some comparisons.
13068 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13069 bool Subus = false;
13071 switch (SetCCOpcode) {
13072 default: llvm_unreachable("Unexpected SETCC condition");
13073 case ISD::SETNE: Invert = true;
13074 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13075 case ISD::SETLT: Swap = true;
13076 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13077 case ISD::SETGE: Swap = true;
13078 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13079 Invert = true; break;
13080 case ISD::SETULT: Swap = true;
13081 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13082 FlipSigns = true; break;
13083 case ISD::SETUGE: Swap = true;
13084 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13085 FlipSigns = true; Invert = true; break;
13088 // Special case: Use min/max operations for SETULE/SETUGE
13089 MVT VET = VT.getVectorElementType();
13091 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13092 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13095 switch (SetCCOpcode) {
13097 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13098 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13101 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13104 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13105 if (!MinMax && hasSubus) {
13106 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13108 // t = psubus Op0, Op1
13109 // pcmpeq t, <0..0>
13110 switch (SetCCOpcode) {
13112 case ISD::SETULT: {
13113 // If the comparison is against a constant we can turn this into a
13114 // setule. With psubus, setule does not require a swap. This is
13115 // beneficial because the constant in the register is no longer
13116 // destructed as the destination so it can be hoisted out of a loop.
13117 // Only do this pre-AVX since vpcmp* is no longer destructive.
13118 if (Subtarget->hasAVX())
13120 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13121 if (ULEOp1.getNode()) {
13123 Subus = true; Invert = false; Swap = false;
13127 // Psubus is better than flip-sign because it requires no inversion.
13128 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13129 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13133 Opc = X86ISD::SUBUS;
13139 std::swap(Op0, Op1);
13141 // Check that the operation in question is available (most are plain SSE2,
13142 // but PCMPGTQ and PCMPEQQ have different requirements).
13143 if (VT == MVT::v2i64) {
13144 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13145 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13147 // First cast everything to the right type.
13148 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13149 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13151 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13152 // bits of the inputs before performing those operations. The lower
13153 // compare is always unsigned.
13156 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13158 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13159 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13160 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13161 Sign, Zero, Sign, Zero);
13163 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13164 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13166 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13167 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13168 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13170 // Create masks for only the low parts/high parts of the 64 bit integers.
13171 static const int MaskHi[] = { 1, 1, 3, 3 };
13172 static const int MaskLo[] = { 0, 0, 2, 2 };
13173 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13174 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13175 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13177 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13178 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13181 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13183 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13186 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13187 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13188 // pcmpeqd + pshufd + pand.
13189 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13191 // First cast everything to the right type.
13192 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13193 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13196 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13198 // Make sure the lower and upper halves are both all-ones.
13199 static const int Mask[] = { 1, 0, 3, 2 };
13200 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13201 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13204 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13206 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13210 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13211 // bits of the inputs before performing those operations.
13213 EVT EltVT = VT.getVectorElementType();
13214 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13215 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13216 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13219 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13221 // If the logical-not of the result is required, perform that now.
13223 Result = DAG.getNOT(dl, Result, VT);
13226 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13229 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13230 getZeroVector(VT, Subtarget, DAG, dl));
13235 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13237 MVT VT = Op.getSimpleValueType();
13239 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13241 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13242 && "SetCC type must be 8-bit or 1-bit integer");
13243 SDValue Op0 = Op.getOperand(0);
13244 SDValue Op1 = Op.getOperand(1);
13246 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13248 // Optimize to BT if possible.
13249 // Lower (X & (1 << N)) == 0 to BT(X, N).
13250 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13251 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13252 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13253 Op1.getOpcode() == ISD::Constant &&
13254 cast<ConstantSDNode>(Op1)->isNullValue() &&
13255 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13256 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13257 if (NewSetCC.getNode())
13261 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13263 if (Op1.getOpcode() == ISD::Constant &&
13264 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13265 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13266 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13268 // If the input is a setcc, then reuse the input setcc or use a new one with
13269 // the inverted condition.
13270 if (Op0.getOpcode() == X86ISD::SETCC) {
13271 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13272 bool Invert = (CC == ISD::SETNE) ^
13273 cast<ConstantSDNode>(Op1)->isNullValue();
13277 CCode = X86::GetOppositeBranchCondition(CCode);
13278 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13279 DAG.getConstant(CCode, MVT::i8),
13280 Op0.getOperand(1));
13282 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13286 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13287 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13288 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13290 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13291 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13294 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13295 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13296 if (X86CC == X86::COND_INVALID)
13299 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13300 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13301 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13302 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13304 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13308 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13309 static bool isX86LogicalCmp(SDValue Op) {
13310 unsigned Opc = Op.getNode()->getOpcode();
13311 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13312 Opc == X86ISD::SAHF)
13314 if (Op.getResNo() == 1 &&
13315 (Opc == X86ISD::ADD ||
13316 Opc == X86ISD::SUB ||
13317 Opc == X86ISD::ADC ||
13318 Opc == X86ISD::SBB ||
13319 Opc == X86ISD::SMUL ||
13320 Opc == X86ISD::UMUL ||
13321 Opc == X86ISD::INC ||
13322 Opc == X86ISD::DEC ||
13323 Opc == X86ISD::OR ||
13324 Opc == X86ISD::XOR ||
13325 Opc == X86ISD::AND))
13328 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13334 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13335 if (V.getOpcode() != ISD::TRUNCATE)
13338 SDValue VOp0 = V.getOperand(0);
13339 unsigned InBits = VOp0.getValueSizeInBits();
13340 unsigned Bits = V.getValueSizeInBits();
13341 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13344 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13345 bool addTest = true;
13346 SDValue Cond = Op.getOperand(0);
13347 SDValue Op1 = Op.getOperand(1);
13348 SDValue Op2 = Op.getOperand(2);
13350 EVT VT = Op1.getValueType();
13353 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13354 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13355 // sequence later on.
13356 if (Cond.getOpcode() == ISD::SETCC &&
13357 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13358 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13359 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13360 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13361 int SSECC = translateX86FSETCC(
13362 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13365 if (Subtarget->hasAVX512()) {
13366 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13367 DAG.getConstant(SSECC, MVT::i8));
13368 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13370 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13371 DAG.getConstant(SSECC, MVT::i8));
13372 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13373 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13374 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13378 if (Cond.getOpcode() == ISD::SETCC) {
13379 SDValue NewCond = LowerSETCC(Cond, DAG);
13380 if (NewCond.getNode())
13384 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13385 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13386 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13387 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13388 if (Cond.getOpcode() == X86ISD::SETCC &&
13389 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13390 isZero(Cond.getOperand(1).getOperand(1))) {
13391 SDValue Cmp = Cond.getOperand(1);
13393 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13395 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13396 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13397 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13399 SDValue CmpOp0 = Cmp.getOperand(0);
13400 // Apply further optimizations for special cases
13401 // (select (x != 0), -1, 0) -> neg & sbb
13402 // (select (x == 0), 0, -1) -> neg & sbb
13403 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13404 if (YC->isNullValue() &&
13405 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13406 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13407 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13408 DAG.getConstant(0, CmpOp0.getValueType()),
13410 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13411 DAG.getConstant(X86::COND_B, MVT::i8),
13412 SDValue(Neg.getNode(), 1));
13416 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13417 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13418 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13420 SDValue Res = // Res = 0 or -1.
13421 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13422 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13424 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13425 Res = DAG.getNOT(DL, Res, Res.getValueType());
13427 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13428 if (!N2C || !N2C->isNullValue())
13429 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13434 // Look past (and (setcc_carry (cmp ...)), 1).
13435 if (Cond.getOpcode() == ISD::AND &&
13436 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13437 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13438 if (C && C->getAPIntValue() == 1)
13439 Cond = Cond.getOperand(0);
13442 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13443 // setting operand in place of the X86ISD::SETCC.
13444 unsigned CondOpcode = Cond.getOpcode();
13445 if (CondOpcode == X86ISD::SETCC ||
13446 CondOpcode == X86ISD::SETCC_CARRY) {
13447 CC = Cond.getOperand(0);
13449 SDValue Cmp = Cond.getOperand(1);
13450 unsigned Opc = Cmp.getOpcode();
13451 MVT VT = Op.getSimpleValueType();
13453 bool IllegalFPCMov = false;
13454 if (VT.isFloatingPoint() && !VT.isVector() &&
13455 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13456 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13458 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13459 Opc == X86ISD::BT) { // FIXME
13463 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13464 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13465 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13466 Cond.getOperand(0).getValueType() != MVT::i8)) {
13467 SDValue LHS = Cond.getOperand(0);
13468 SDValue RHS = Cond.getOperand(1);
13469 unsigned X86Opcode;
13472 switch (CondOpcode) {
13473 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13474 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13475 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13476 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13477 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13478 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13479 default: llvm_unreachable("unexpected overflowing operator");
13481 if (CondOpcode == ISD::UMULO)
13482 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13485 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13487 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13489 if (CondOpcode == ISD::UMULO)
13490 Cond = X86Op.getValue(2);
13492 Cond = X86Op.getValue(1);
13494 CC = DAG.getConstant(X86Cond, MVT::i8);
13499 // Look pass the truncate if the high bits are known zero.
13500 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13501 Cond = Cond.getOperand(0);
13503 // We know the result of AND is compared against zero. Try to match
13505 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13506 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13507 if (NewSetCC.getNode()) {
13508 CC = NewSetCC.getOperand(0);
13509 Cond = NewSetCC.getOperand(1);
13516 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13517 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13520 // a < b ? -1 : 0 -> RES = ~setcc_carry
13521 // a < b ? 0 : -1 -> RES = setcc_carry
13522 // a >= b ? -1 : 0 -> RES = setcc_carry
13523 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13524 if (Cond.getOpcode() == X86ISD::SUB) {
13525 Cond = ConvertCmpIfNecessary(Cond, DAG);
13526 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13528 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13529 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13530 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13531 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13532 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13533 return DAG.getNOT(DL, Res, Res.getValueType());
13538 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13539 // widen the cmov and push the truncate through. This avoids introducing a new
13540 // branch during isel and doesn't add any extensions.
13541 if (Op.getValueType() == MVT::i8 &&
13542 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13543 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13544 if (T1.getValueType() == T2.getValueType() &&
13545 // Blacklist CopyFromReg to avoid partial register stalls.
13546 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13547 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13548 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13549 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13553 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13554 // condition is true.
13555 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13556 SDValue Ops[] = { Op2, Op1, CC, Cond };
13557 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13560 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13561 MVT VT = Op->getSimpleValueType(0);
13562 SDValue In = Op->getOperand(0);
13563 MVT InVT = In.getSimpleValueType();
13566 unsigned int NumElts = VT.getVectorNumElements();
13567 if (NumElts != 8 && NumElts != 16)
13570 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13571 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13574 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13576 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13577 Constant *C = ConstantInt::get(*DAG.getContext(),
13578 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13580 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13581 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13582 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13583 MachinePointerInfo::getConstantPool(),
13584 false, false, false, Alignment);
13585 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13586 if (VT.is512BitVector())
13588 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13591 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13592 SelectionDAG &DAG) {
13593 MVT VT = Op->getSimpleValueType(0);
13594 SDValue In = Op->getOperand(0);
13595 MVT InVT = In.getSimpleValueType();
13598 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13599 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13601 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13602 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13603 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13606 if (Subtarget->hasInt256())
13607 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13609 // Optimize vectors in AVX mode
13610 // Sign extend v8i16 to v8i32 and
13613 // Divide input vector into two parts
13614 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13615 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13616 // concat the vectors to original VT
13618 unsigned NumElems = InVT.getVectorNumElements();
13619 SDValue Undef = DAG.getUNDEF(InVT);
13621 SmallVector<int,8> ShufMask1(NumElems, -1);
13622 for (unsigned i = 0; i != NumElems/2; ++i)
13625 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13627 SmallVector<int,8> ShufMask2(NumElems, -1);
13628 for (unsigned i = 0; i != NumElems/2; ++i)
13629 ShufMask2[i] = i + NumElems/2;
13631 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13633 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13634 VT.getVectorNumElements()/2);
13636 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13637 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13639 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13642 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13643 // may emit an illegal shuffle but the expansion is still better than scalar
13644 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13645 // we'll emit a shuffle and a arithmetic shift.
13646 // TODO: It is possible to support ZExt by zeroing the undef values during
13647 // the shuffle phase or after the shuffle.
13648 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13649 SelectionDAG &DAG) {
13650 MVT RegVT = Op.getSimpleValueType();
13651 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13652 assert(RegVT.isInteger() &&
13653 "We only custom lower integer vector sext loads.");
13655 // Nothing useful we can do without SSE2 shuffles.
13656 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13658 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13660 EVT MemVT = Ld->getMemoryVT();
13661 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13662 unsigned RegSz = RegVT.getSizeInBits();
13664 ISD::LoadExtType Ext = Ld->getExtensionType();
13666 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13667 && "Only anyext and sext are currently implemented.");
13668 assert(MemVT != RegVT && "Cannot extend to the same type");
13669 assert(MemVT.isVector() && "Must load a vector from memory");
13671 unsigned NumElems = RegVT.getVectorNumElements();
13672 unsigned MemSz = MemVT.getSizeInBits();
13673 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13675 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13676 // The only way in which we have a legal 256-bit vector result but not the
13677 // integer 256-bit operations needed to directly lower a sextload is if we
13678 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13679 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13680 // correctly legalized. We do this late to allow the canonical form of
13681 // sextload to persist throughout the rest of the DAG combiner -- it wants
13682 // to fold together any extensions it can, and so will fuse a sign_extend
13683 // of an sextload into a sextload targeting a wider value.
13685 if (MemSz == 128) {
13686 // Just switch this to a normal load.
13687 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13688 "it must be a legal 128-bit vector "
13690 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13691 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13692 Ld->isInvariant(), Ld->getAlignment());
13694 assert(MemSz < 128 &&
13695 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13696 // Do an sext load to a 128-bit vector type. We want to use the same
13697 // number of elements, but elements half as wide. This will end up being
13698 // recursively lowered by this routine, but will succeed as we definitely
13699 // have all the necessary features if we're using AVX1.
13701 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13702 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13704 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13705 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13706 Ld->isNonTemporal(), Ld->isInvariant(),
13707 Ld->getAlignment());
13710 // Replace chain users with the new chain.
13711 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13712 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13714 // Finally, do a normal sign-extend to the desired register.
13715 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13718 // All sizes must be a power of two.
13719 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13720 "Non-power-of-two elements are not custom lowered!");
13722 // Attempt to load the original value using scalar loads.
13723 // Find the largest scalar type that divides the total loaded size.
13724 MVT SclrLoadTy = MVT::i8;
13725 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13726 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13727 MVT Tp = (MVT::SimpleValueType)tp;
13728 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13733 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13734 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13736 SclrLoadTy = MVT::f64;
13738 // Calculate the number of scalar loads that we need to perform
13739 // in order to load our vector from memory.
13740 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13742 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13743 "Can only lower sext loads with a single scalar load!");
13745 unsigned loadRegZize = RegSz;
13746 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13749 // Represent our vector as a sequence of elements which are the
13750 // largest scalar that we can load.
13751 EVT LoadUnitVecVT = EVT::getVectorVT(
13752 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13754 // Represent the data using the same element type that is stored in
13755 // memory. In practice, we ''widen'' MemVT.
13757 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13758 loadRegZize / MemVT.getScalarType().getSizeInBits());
13760 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13761 "Invalid vector type");
13763 // We can't shuffle using an illegal type.
13764 assert(TLI.isTypeLegal(WideVecVT) &&
13765 "We only lower types that form legal widened vector types");
13767 SmallVector<SDValue, 8> Chains;
13768 SDValue Ptr = Ld->getBasePtr();
13769 SDValue Increment =
13770 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13771 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13773 for (unsigned i = 0; i < NumLoads; ++i) {
13774 // Perform a single load.
13775 SDValue ScalarLoad =
13776 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13777 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13778 Ld->getAlignment());
13779 Chains.push_back(ScalarLoad.getValue(1));
13780 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13781 // another round of DAGCombining.
13783 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13785 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13786 ScalarLoad, DAG.getIntPtrConstant(i));
13788 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13791 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13793 // Bitcast the loaded value to a vector of the original element type, in
13794 // the size of the target vector type.
13795 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13796 unsigned SizeRatio = RegSz / MemSz;
13798 if (Ext == ISD::SEXTLOAD) {
13799 // If we have SSE4.1, we can directly emit a VSEXT node.
13800 if (Subtarget->hasSSE41()) {
13801 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13802 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13806 // Otherwise we'll shuffle the small elements in the high bits of the
13807 // larger type and perform an arithmetic shift. If the shift is not legal
13808 // it's better to scalarize.
13809 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13810 "We can't implement a sext load without an arithmetic right shift!");
13812 // Redistribute the loaded elements into the different locations.
13813 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13814 for (unsigned i = 0; i != NumElems; ++i)
13815 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13817 SDValue Shuff = DAG.getVectorShuffle(
13818 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13820 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13822 // Build the arithmetic shift.
13823 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13824 MemVT.getVectorElementType().getSizeInBits();
13826 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13828 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13832 // Redistribute the loaded elements into the different locations.
13833 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13834 for (unsigned i = 0; i != NumElems; ++i)
13835 ShuffleVec[i * SizeRatio] = i;
13837 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13838 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13840 // Bitcast to the requested type.
13841 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13842 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13846 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13847 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13848 // from the AND / OR.
13849 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13850 Opc = Op.getOpcode();
13851 if (Opc != ISD::OR && Opc != ISD::AND)
13853 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13854 Op.getOperand(0).hasOneUse() &&
13855 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13856 Op.getOperand(1).hasOneUse());
13859 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13860 // 1 and that the SETCC node has a single use.
13861 static bool isXor1OfSetCC(SDValue Op) {
13862 if (Op.getOpcode() != ISD::XOR)
13864 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13865 if (N1C && N1C->getAPIntValue() == 1) {
13866 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13867 Op.getOperand(0).hasOneUse();
13872 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13873 bool addTest = true;
13874 SDValue Chain = Op.getOperand(0);
13875 SDValue Cond = Op.getOperand(1);
13876 SDValue Dest = Op.getOperand(2);
13879 bool Inverted = false;
13881 if (Cond.getOpcode() == ISD::SETCC) {
13882 // Check for setcc([su]{add,sub,mul}o == 0).
13883 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13884 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13885 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13886 Cond.getOperand(0).getResNo() == 1 &&
13887 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13888 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13889 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13890 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13891 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13892 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13894 Cond = Cond.getOperand(0);
13896 SDValue NewCond = LowerSETCC(Cond, DAG);
13897 if (NewCond.getNode())
13902 // FIXME: LowerXALUO doesn't handle these!!
13903 else if (Cond.getOpcode() == X86ISD::ADD ||
13904 Cond.getOpcode() == X86ISD::SUB ||
13905 Cond.getOpcode() == X86ISD::SMUL ||
13906 Cond.getOpcode() == X86ISD::UMUL)
13907 Cond = LowerXALUO(Cond, DAG);
13910 // Look pass (and (setcc_carry (cmp ...)), 1).
13911 if (Cond.getOpcode() == ISD::AND &&
13912 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13914 if (C && C->getAPIntValue() == 1)
13915 Cond = Cond.getOperand(0);
13918 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13919 // setting operand in place of the X86ISD::SETCC.
13920 unsigned CondOpcode = Cond.getOpcode();
13921 if (CondOpcode == X86ISD::SETCC ||
13922 CondOpcode == X86ISD::SETCC_CARRY) {
13923 CC = Cond.getOperand(0);
13925 SDValue Cmp = Cond.getOperand(1);
13926 unsigned Opc = Cmp.getOpcode();
13927 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13928 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13932 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13936 // These can only come from an arithmetic instruction with overflow,
13937 // e.g. SADDO, UADDO.
13938 Cond = Cond.getNode()->getOperand(1);
13944 CondOpcode = Cond.getOpcode();
13945 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13946 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13947 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13948 Cond.getOperand(0).getValueType() != MVT::i8)) {
13949 SDValue LHS = Cond.getOperand(0);
13950 SDValue RHS = Cond.getOperand(1);
13951 unsigned X86Opcode;
13954 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13955 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13957 switch (CondOpcode) {
13958 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13962 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13965 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13966 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13968 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13970 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13973 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13974 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13975 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13976 default: llvm_unreachable("unexpected overflowing operator");
13979 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13980 if (CondOpcode == ISD::UMULO)
13981 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13984 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13986 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13988 if (CondOpcode == ISD::UMULO)
13989 Cond = X86Op.getValue(2);
13991 Cond = X86Op.getValue(1);
13993 CC = DAG.getConstant(X86Cond, MVT::i8);
13997 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13998 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13999 if (CondOpc == ISD::OR) {
14000 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14001 // two branches instead of an explicit OR instruction with a
14003 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14004 isX86LogicalCmp(Cmp)) {
14005 CC = Cond.getOperand(0).getOperand(0);
14006 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14007 Chain, Dest, CC, Cmp);
14008 CC = Cond.getOperand(1).getOperand(0);
14012 } else { // ISD::AND
14013 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14014 // two branches instead of an explicit AND instruction with a
14015 // separate test. However, we only do this if this block doesn't
14016 // have a fall-through edge, because this requires an explicit
14017 // jmp when the condition is false.
14018 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14019 isX86LogicalCmp(Cmp) &&
14020 Op.getNode()->hasOneUse()) {
14021 X86::CondCode CCode =
14022 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14023 CCode = X86::GetOppositeBranchCondition(CCode);
14024 CC = DAG.getConstant(CCode, MVT::i8);
14025 SDNode *User = *Op.getNode()->use_begin();
14026 // Look for an unconditional branch following this conditional branch.
14027 // We need this because we need to reverse the successors in order
14028 // to implement FCMP_OEQ.
14029 if (User->getOpcode() == ISD::BR) {
14030 SDValue FalseBB = User->getOperand(1);
14032 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14033 assert(NewBR == User);
14037 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14038 Chain, Dest, CC, Cmp);
14039 X86::CondCode CCode =
14040 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14041 CCode = X86::GetOppositeBranchCondition(CCode);
14042 CC = DAG.getConstant(CCode, MVT::i8);
14048 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14049 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14050 // It should be transformed during dag combiner except when the condition
14051 // is set by a arithmetics with overflow node.
14052 X86::CondCode CCode =
14053 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14054 CCode = X86::GetOppositeBranchCondition(CCode);
14055 CC = DAG.getConstant(CCode, MVT::i8);
14056 Cond = Cond.getOperand(0).getOperand(1);
14058 } else if (Cond.getOpcode() == ISD::SETCC &&
14059 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14060 // For FCMP_OEQ, we can emit
14061 // two branches instead of an explicit AND instruction with a
14062 // separate test. However, we only do this if this block doesn't
14063 // have a fall-through edge, because this requires an explicit
14064 // jmp when the condition is false.
14065 if (Op.getNode()->hasOneUse()) {
14066 SDNode *User = *Op.getNode()->use_begin();
14067 // Look for an unconditional branch following this conditional branch.
14068 // We need this because we need to reverse the successors in order
14069 // to implement FCMP_OEQ.
14070 if (User->getOpcode() == ISD::BR) {
14071 SDValue FalseBB = User->getOperand(1);
14073 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14074 assert(NewBR == User);
14078 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14079 Cond.getOperand(0), Cond.getOperand(1));
14080 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14081 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14082 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14083 Chain, Dest, CC, Cmp);
14084 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14089 } else if (Cond.getOpcode() == ISD::SETCC &&
14090 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14091 // For FCMP_UNE, we can emit
14092 // two branches instead of an explicit AND instruction with a
14093 // separate test. However, we only do this if this block doesn't
14094 // have a fall-through edge, because this requires an explicit
14095 // jmp when the condition is false.
14096 if (Op.getNode()->hasOneUse()) {
14097 SDNode *User = *Op.getNode()->use_begin();
14098 // Look for an unconditional branch following this conditional branch.
14099 // We need this because we need to reverse the successors in order
14100 // to implement FCMP_UNE.
14101 if (User->getOpcode() == ISD::BR) {
14102 SDValue FalseBB = User->getOperand(1);
14104 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14105 assert(NewBR == User);
14108 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14109 Cond.getOperand(0), Cond.getOperand(1));
14110 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14111 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14112 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14113 Chain, Dest, CC, Cmp);
14114 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14124 // Look pass the truncate if the high bits are known zero.
14125 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14126 Cond = Cond.getOperand(0);
14128 // We know the result of AND is compared against zero. Try to match
14130 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14131 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14132 if (NewSetCC.getNode()) {
14133 CC = NewSetCC.getOperand(0);
14134 Cond = NewSetCC.getOperand(1);
14141 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14142 CC = DAG.getConstant(X86Cond, MVT::i8);
14143 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14145 Cond = ConvertCmpIfNecessary(Cond, DAG);
14146 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14147 Chain, Dest, CC, Cond);
14150 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14151 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14152 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14153 // that the guard pages used by the OS virtual memory manager are allocated in
14154 // correct sequence.
14156 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14157 SelectionDAG &DAG) const {
14158 MachineFunction &MF = DAG.getMachineFunction();
14159 bool SplitStack = MF.shouldSplitStack();
14160 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14166 SDNode* Node = Op.getNode();
14168 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14169 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14170 " not tell us which reg is the stack pointer!");
14171 EVT VT = Node->getValueType(0);
14172 SDValue Tmp1 = SDValue(Node, 0);
14173 SDValue Tmp2 = SDValue(Node, 1);
14174 SDValue Tmp3 = Node->getOperand(2);
14175 SDValue Chain = Tmp1.getOperand(0);
14177 // Chain the dynamic stack allocation so that it doesn't modify the stack
14178 // pointer when other instructions are using the stack.
14179 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14182 SDValue Size = Tmp2.getOperand(1);
14183 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14184 Chain = SP.getValue(1);
14185 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14186 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14187 unsigned StackAlign = TFI.getStackAlignment();
14188 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14189 if (Align > StackAlign)
14190 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14191 DAG.getConstant(-(uint64_t)Align, VT));
14192 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14194 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14195 DAG.getIntPtrConstant(0, true), SDValue(),
14198 SDValue Ops[2] = { Tmp1, Tmp2 };
14199 return DAG.getMergeValues(Ops, dl);
14203 SDValue Chain = Op.getOperand(0);
14204 SDValue Size = Op.getOperand(1);
14205 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14206 EVT VT = Op.getNode()->getValueType(0);
14208 bool Is64Bit = Subtarget->is64Bit();
14209 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14212 MachineRegisterInfo &MRI = MF.getRegInfo();
14215 // The 64 bit implementation of segmented stacks needs to clobber both r10
14216 // r11. This makes it impossible to use it along with nested parameters.
14217 const Function *F = MF.getFunction();
14219 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14221 if (I->hasNestAttr())
14222 report_fatal_error("Cannot use segmented stacks with functions that "
14223 "have nested arguments.");
14226 const TargetRegisterClass *AddrRegClass =
14227 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14228 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14229 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14230 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14231 DAG.getRegister(Vreg, SPTy));
14232 SDValue Ops1[2] = { Value, Chain };
14233 return DAG.getMergeValues(Ops1, dl);
14236 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14238 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14239 Flag = Chain.getValue(1);
14240 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14242 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14245 DAG.getSubtarget().getRegisterInfo());
14246 unsigned SPReg = RegInfo->getStackRegister();
14247 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14248 Chain = SP.getValue(1);
14251 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14252 DAG.getConstant(-(uint64_t)Align, VT));
14253 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14256 SDValue Ops1[2] = { SP, Chain };
14257 return DAG.getMergeValues(Ops1, dl);
14261 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14262 MachineFunction &MF = DAG.getMachineFunction();
14263 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14265 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14268 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14269 // vastart just stores the address of the VarArgsFrameIndex slot into the
14270 // memory location argument.
14271 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14273 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14274 MachinePointerInfo(SV), false, false, 0);
14278 // gp_offset (0 - 6 * 8)
14279 // fp_offset (48 - 48 + 8 * 16)
14280 // overflow_arg_area (point to parameters coming in memory).
14282 SmallVector<SDValue, 8> MemOps;
14283 SDValue FIN = Op.getOperand(1);
14285 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14286 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14288 FIN, MachinePointerInfo(SV), false, false, 0);
14289 MemOps.push_back(Store);
14292 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14293 FIN, DAG.getIntPtrConstant(4));
14294 Store = DAG.getStore(Op.getOperand(0), DL,
14295 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14297 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14298 MemOps.push_back(Store);
14300 // Store ptr to overflow_arg_area
14301 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14302 FIN, DAG.getIntPtrConstant(4));
14303 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14305 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14306 MachinePointerInfo(SV, 8),
14308 MemOps.push_back(Store);
14310 // Store ptr to reg_save_area.
14311 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14312 FIN, DAG.getIntPtrConstant(8));
14313 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14315 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14316 MachinePointerInfo(SV, 16), false, false, 0);
14317 MemOps.push_back(Store);
14318 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14321 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14322 assert(Subtarget->is64Bit() &&
14323 "LowerVAARG only handles 64-bit va_arg!");
14324 assert((Subtarget->isTargetLinux() ||
14325 Subtarget->isTargetDarwin()) &&
14326 "Unhandled target in LowerVAARG");
14327 assert(Op.getNode()->getNumOperands() == 4);
14328 SDValue Chain = Op.getOperand(0);
14329 SDValue SrcPtr = Op.getOperand(1);
14330 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14331 unsigned Align = Op.getConstantOperandVal(3);
14334 EVT ArgVT = Op.getNode()->getValueType(0);
14335 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14336 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14339 // Decide which area this value should be read from.
14340 // TODO: Implement the AMD64 ABI in its entirety. This simple
14341 // selection mechanism works only for the basic types.
14342 if (ArgVT == MVT::f80) {
14343 llvm_unreachable("va_arg for f80 not yet implemented");
14344 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14345 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14346 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14347 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14349 llvm_unreachable("Unhandled argument type in LowerVAARG");
14352 if (ArgMode == 2) {
14353 // Sanity Check: Make sure using fp_offset makes sense.
14354 assert(!DAG.getTarget().Options.UseSoftFloat &&
14355 !(DAG.getMachineFunction()
14356 .getFunction()->getAttributes()
14357 .hasAttribute(AttributeSet::FunctionIndex,
14358 Attribute::NoImplicitFloat)) &&
14359 Subtarget->hasSSE1());
14362 // Insert VAARG_64 node into the DAG
14363 // VAARG_64 returns two values: Variable Argument Address, Chain
14364 SmallVector<SDValue, 11> InstOps;
14365 InstOps.push_back(Chain);
14366 InstOps.push_back(SrcPtr);
14367 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14368 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14369 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14370 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14371 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14372 VTs, InstOps, MVT::i64,
14373 MachinePointerInfo(SV),
14375 /*Volatile=*/false,
14377 /*WriteMem=*/true);
14378 Chain = VAARG.getValue(1);
14380 // Load the next argument and return it
14381 return DAG.getLoad(ArgVT, dl,
14384 MachinePointerInfo(),
14385 false, false, false, 0);
14388 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14389 SelectionDAG &DAG) {
14390 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14391 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14392 SDValue Chain = Op.getOperand(0);
14393 SDValue DstPtr = Op.getOperand(1);
14394 SDValue SrcPtr = Op.getOperand(2);
14395 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14396 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14399 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14400 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14402 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14405 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14406 // amount is a constant. Takes immediate version of shift as input.
14407 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14408 SDValue SrcOp, uint64_t ShiftAmt,
14409 SelectionDAG &DAG) {
14410 MVT ElementType = VT.getVectorElementType();
14412 // Fold this packed shift into its first operand if ShiftAmt is 0.
14416 // Check for ShiftAmt >= element width
14417 if (ShiftAmt >= ElementType.getSizeInBits()) {
14418 if (Opc == X86ISD::VSRAI)
14419 ShiftAmt = ElementType.getSizeInBits() - 1;
14421 return DAG.getConstant(0, VT);
14424 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14425 && "Unknown target vector shift-by-constant node");
14427 // Fold this packed vector shift into a build vector if SrcOp is a
14428 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14429 if (VT == SrcOp.getSimpleValueType() &&
14430 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14431 SmallVector<SDValue, 8> Elts;
14432 unsigned NumElts = SrcOp->getNumOperands();
14433 ConstantSDNode *ND;
14436 default: llvm_unreachable(nullptr);
14437 case X86ISD::VSHLI:
14438 for (unsigned i=0; i!=NumElts; ++i) {
14439 SDValue CurrentOp = SrcOp->getOperand(i);
14440 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14441 Elts.push_back(CurrentOp);
14444 ND = cast<ConstantSDNode>(CurrentOp);
14445 const APInt &C = ND->getAPIntValue();
14446 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14449 case X86ISD::VSRLI:
14450 for (unsigned i=0; i!=NumElts; ++i) {
14451 SDValue CurrentOp = SrcOp->getOperand(i);
14452 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14453 Elts.push_back(CurrentOp);
14456 ND = cast<ConstantSDNode>(CurrentOp);
14457 const APInt &C = ND->getAPIntValue();
14458 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14461 case X86ISD::VSRAI:
14462 for (unsigned i=0; i!=NumElts; ++i) {
14463 SDValue CurrentOp = SrcOp->getOperand(i);
14464 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14465 Elts.push_back(CurrentOp);
14468 ND = cast<ConstantSDNode>(CurrentOp);
14469 const APInt &C = ND->getAPIntValue();
14470 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14475 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14478 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14481 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14482 // may or may not be a constant. Takes immediate version of shift as input.
14483 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14484 SDValue SrcOp, SDValue ShAmt,
14485 SelectionDAG &DAG) {
14486 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14488 // Catch shift-by-constant.
14489 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14490 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14491 CShAmt->getZExtValue(), DAG);
14493 // Change opcode to non-immediate version
14495 default: llvm_unreachable("Unknown target vector shift node");
14496 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14497 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14498 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14501 // Need to build a vector containing shift amount
14502 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14505 ShOps[1] = DAG.getConstant(0, MVT::i32);
14506 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14507 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14509 // The return type has to be a 128-bit type with the same element
14510 // type as the input type.
14511 MVT EltVT = VT.getVectorElementType();
14512 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14514 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14515 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14518 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14519 /// necessary casting for \p Mask when lowering masking intrinsics.
14520 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14521 SDValue PreservedSrc, SelectionDAG &DAG) {
14522 EVT VT = Op.getValueType();
14523 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14524 MVT::i1, VT.getVectorNumElements());
14527 assert(MaskVT.isSimple() && "invalid mask type");
14528 return DAG.getNode(ISD::VSELECT, dl, VT,
14529 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14533 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14535 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14536 case Intrinsic::x86_fma_vfmadd_ps:
14537 case Intrinsic::x86_fma_vfmadd_pd:
14538 case Intrinsic::x86_fma_vfmadd_ps_256:
14539 case Intrinsic::x86_fma_vfmadd_pd_256:
14540 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14541 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14542 return X86ISD::FMADD;
14543 case Intrinsic::x86_fma_vfmsub_ps:
14544 case Intrinsic::x86_fma_vfmsub_pd:
14545 case Intrinsic::x86_fma_vfmsub_ps_256:
14546 case Intrinsic::x86_fma_vfmsub_pd_256:
14547 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14548 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14549 return X86ISD::FMSUB;
14550 case Intrinsic::x86_fma_vfnmadd_ps:
14551 case Intrinsic::x86_fma_vfnmadd_pd:
14552 case Intrinsic::x86_fma_vfnmadd_ps_256:
14553 case Intrinsic::x86_fma_vfnmadd_pd_256:
14554 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14555 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14556 return X86ISD::FNMADD;
14557 case Intrinsic::x86_fma_vfnmsub_ps:
14558 case Intrinsic::x86_fma_vfnmsub_pd:
14559 case Intrinsic::x86_fma_vfnmsub_ps_256:
14560 case Intrinsic::x86_fma_vfnmsub_pd_256:
14561 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14562 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14563 return X86ISD::FNMSUB;
14564 case Intrinsic::x86_fma_vfmaddsub_ps:
14565 case Intrinsic::x86_fma_vfmaddsub_pd:
14566 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14567 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14568 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14569 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14570 return X86ISD::FMADDSUB;
14571 case Intrinsic::x86_fma_vfmsubadd_ps:
14572 case Intrinsic::x86_fma_vfmsubadd_pd:
14573 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14574 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14575 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14576 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14577 return X86ISD::FMSUBADD;
14581 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14583 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14585 const IntrinsicData* IntrData = GetIntrinsicWithoutChain(IntNo);
14587 switch(IntrData->Type) {
14588 case INTR_TYPE_1OP:
14589 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14590 case INTR_TYPE_2OP:
14591 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14593 case INTR_TYPE_3OP:
14594 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14595 Op.getOperand(2), Op.getOperand(3));
14596 case COMI: { // Comparison intrinsics
14597 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14598 SDValue LHS = Op.getOperand(1);
14599 SDValue RHS = Op.getOperand(2);
14600 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14601 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14602 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14603 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14604 DAG.getConstant(X86CC, MVT::i8), Cond);
14605 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14608 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14609 Op.getOperand(1), Op.getOperand(2), DAG);
14616 default: return SDValue(); // Don't custom lower most intrinsics.
14618 // Arithmetic intrinsics.
14619 case Intrinsic::x86_sse2_pmulu_dq:
14620 case Intrinsic::x86_avx2_pmulu_dq:
14621 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14622 Op.getOperand(1), Op.getOperand(2));
14624 case Intrinsic::x86_sse41_pmuldq:
14625 case Intrinsic::x86_avx2_pmul_dq:
14626 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14627 Op.getOperand(1), Op.getOperand(2));
14629 case Intrinsic::x86_sse2_pmulhu_w:
14630 case Intrinsic::x86_avx2_pmulhu_w:
14631 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14632 Op.getOperand(1), Op.getOperand(2));
14634 case Intrinsic::x86_sse2_pmulh_w:
14635 case Intrinsic::x86_avx2_pmulh_w:
14636 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14637 Op.getOperand(1), Op.getOperand(2));
14639 // SSE/SSE2/AVX floating point max/min intrinsics.
14640 case Intrinsic::x86_sse_max_ps:
14641 case Intrinsic::x86_sse2_max_pd:
14642 case Intrinsic::x86_avx_max_ps_256:
14643 case Intrinsic::x86_avx_max_pd_256:
14644 case Intrinsic::x86_sse_min_ps:
14645 case Intrinsic::x86_sse2_min_pd:
14646 case Intrinsic::x86_avx_min_ps_256:
14647 case Intrinsic::x86_avx_min_pd_256: {
14650 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14651 case Intrinsic::x86_sse_max_ps:
14652 case Intrinsic::x86_sse2_max_pd:
14653 case Intrinsic::x86_avx_max_ps_256:
14654 case Intrinsic::x86_avx_max_pd_256:
14655 Opcode = X86ISD::FMAX;
14657 case Intrinsic::x86_sse_min_ps:
14658 case Intrinsic::x86_sse2_min_pd:
14659 case Intrinsic::x86_avx_min_ps_256:
14660 case Intrinsic::x86_avx_min_pd_256:
14661 Opcode = X86ISD::FMIN;
14664 return DAG.getNode(Opcode, dl, Op.getValueType(),
14665 Op.getOperand(1), Op.getOperand(2));
14668 // AVX2 variable shift intrinsics
14669 case Intrinsic::x86_avx2_psllv_d:
14670 case Intrinsic::x86_avx2_psllv_q:
14671 case Intrinsic::x86_avx2_psllv_d_256:
14672 case Intrinsic::x86_avx2_psllv_q_256:
14673 case Intrinsic::x86_avx2_psrlv_d:
14674 case Intrinsic::x86_avx2_psrlv_q:
14675 case Intrinsic::x86_avx2_psrlv_d_256:
14676 case Intrinsic::x86_avx2_psrlv_q_256:
14677 case Intrinsic::x86_avx2_psrav_d:
14678 case Intrinsic::x86_avx2_psrav_d_256: {
14681 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14682 case Intrinsic::x86_avx2_psllv_d:
14683 case Intrinsic::x86_avx2_psllv_q:
14684 case Intrinsic::x86_avx2_psllv_d_256:
14685 case Intrinsic::x86_avx2_psllv_q_256:
14688 case Intrinsic::x86_avx2_psrlv_d:
14689 case Intrinsic::x86_avx2_psrlv_q:
14690 case Intrinsic::x86_avx2_psrlv_d_256:
14691 case Intrinsic::x86_avx2_psrlv_q_256:
14694 case Intrinsic::x86_avx2_psrav_d:
14695 case Intrinsic::x86_avx2_psrav_d_256:
14699 return DAG.getNode(Opcode, dl, Op.getValueType(),
14700 Op.getOperand(1), Op.getOperand(2));
14703 case Intrinsic::x86_sse2_packssdw_128:
14704 case Intrinsic::x86_sse2_packsswb_128:
14705 case Intrinsic::x86_avx2_packssdw:
14706 case Intrinsic::x86_avx2_packsswb:
14707 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14708 Op.getOperand(1), Op.getOperand(2));
14710 case Intrinsic::x86_sse2_packuswb_128:
14711 case Intrinsic::x86_sse41_packusdw:
14712 case Intrinsic::x86_avx2_packuswb:
14713 case Intrinsic::x86_avx2_packusdw:
14714 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14715 Op.getOperand(1), Op.getOperand(2));
14717 case Intrinsic::x86_ssse3_pshuf_b_128:
14718 case Intrinsic::x86_avx2_pshuf_b:
14719 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14720 Op.getOperand(1), Op.getOperand(2));
14722 case Intrinsic::x86_sse2_pshuf_d:
14723 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14724 Op.getOperand(1), Op.getOperand(2));
14726 case Intrinsic::x86_sse2_pshufl_w:
14727 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14728 Op.getOperand(1), Op.getOperand(2));
14730 case Intrinsic::x86_sse2_pshufh_w:
14731 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14732 Op.getOperand(1), Op.getOperand(2));
14734 case Intrinsic::x86_ssse3_psign_b_128:
14735 case Intrinsic::x86_ssse3_psign_w_128:
14736 case Intrinsic::x86_ssse3_psign_d_128:
14737 case Intrinsic::x86_avx2_psign_b:
14738 case Intrinsic::x86_avx2_psign_w:
14739 case Intrinsic::x86_avx2_psign_d:
14740 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14741 Op.getOperand(1), Op.getOperand(2));
14743 case Intrinsic::x86_avx2_permd:
14744 case Intrinsic::x86_avx2_permps:
14745 // Operands intentionally swapped. Mask is last operand to intrinsic,
14746 // but second operand for node/instruction.
14747 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14748 Op.getOperand(2), Op.getOperand(1));
14750 case Intrinsic::x86_avx512_mask_valign_q_512:
14751 case Intrinsic::x86_avx512_mask_valign_d_512:
14752 // Vector source operands are swapped.
14753 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14754 Op.getValueType(), Op.getOperand(2),
14757 Op.getOperand(5), Op.getOperand(4), DAG);
14759 // ptest and testp intrinsics. The intrinsic these come from are designed to
14760 // return an integer value, not just an instruction so lower it to the ptest
14761 // or testp pattern and a setcc for the result.
14762 case Intrinsic::x86_sse41_ptestz:
14763 case Intrinsic::x86_sse41_ptestc:
14764 case Intrinsic::x86_sse41_ptestnzc:
14765 case Intrinsic::x86_avx_ptestz_256:
14766 case Intrinsic::x86_avx_ptestc_256:
14767 case Intrinsic::x86_avx_ptestnzc_256:
14768 case Intrinsic::x86_avx_vtestz_ps:
14769 case Intrinsic::x86_avx_vtestc_ps:
14770 case Intrinsic::x86_avx_vtestnzc_ps:
14771 case Intrinsic::x86_avx_vtestz_pd:
14772 case Intrinsic::x86_avx_vtestc_pd:
14773 case Intrinsic::x86_avx_vtestnzc_pd:
14774 case Intrinsic::x86_avx_vtestz_ps_256:
14775 case Intrinsic::x86_avx_vtestc_ps_256:
14776 case Intrinsic::x86_avx_vtestnzc_ps_256:
14777 case Intrinsic::x86_avx_vtestz_pd_256:
14778 case Intrinsic::x86_avx_vtestc_pd_256:
14779 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14780 bool IsTestPacked = false;
14783 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14784 case Intrinsic::x86_avx_vtestz_ps:
14785 case Intrinsic::x86_avx_vtestz_pd:
14786 case Intrinsic::x86_avx_vtestz_ps_256:
14787 case Intrinsic::x86_avx_vtestz_pd_256:
14788 IsTestPacked = true; // Fallthrough
14789 case Intrinsic::x86_sse41_ptestz:
14790 case Intrinsic::x86_avx_ptestz_256:
14792 X86CC = X86::COND_E;
14794 case Intrinsic::x86_avx_vtestc_ps:
14795 case Intrinsic::x86_avx_vtestc_pd:
14796 case Intrinsic::x86_avx_vtestc_ps_256:
14797 case Intrinsic::x86_avx_vtestc_pd_256:
14798 IsTestPacked = true; // Fallthrough
14799 case Intrinsic::x86_sse41_ptestc:
14800 case Intrinsic::x86_avx_ptestc_256:
14802 X86CC = X86::COND_B;
14804 case Intrinsic::x86_avx_vtestnzc_ps:
14805 case Intrinsic::x86_avx_vtestnzc_pd:
14806 case Intrinsic::x86_avx_vtestnzc_ps_256:
14807 case Intrinsic::x86_avx_vtestnzc_pd_256:
14808 IsTestPacked = true; // Fallthrough
14809 case Intrinsic::x86_sse41_ptestnzc:
14810 case Intrinsic::x86_avx_ptestnzc_256:
14812 X86CC = X86::COND_A;
14816 SDValue LHS = Op.getOperand(1);
14817 SDValue RHS = Op.getOperand(2);
14818 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14819 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14820 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14822 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14824 case Intrinsic::x86_avx512_kortestz_w:
14825 case Intrinsic::x86_avx512_kortestc_w: {
14826 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14827 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14828 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14829 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14830 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14831 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14832 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14835 case Intrinsic::x86_sse42_pcmpistria128:
14836 case Intrinsic::x86_sse42_pcmpestria128:
14837 case Intrinsic::x86_sse42_pcmpistric128:
14838 case Intrinsic::x86_sse42_pcmpestric128:
14839 case Intrinsic::x86_sse42_pcmpistrio128:
14840 case Intrinsic::x86_sse42_pcmpestrio128:
14841 case Intrinsic::x86_sse42_pcmpistris128:
14842 case Intrinsic::x86_sse42_pcmpestris128:
14843 case Intrinsic::x86_sse42_pcmpistriz128:
14844 case Intrinsic::x86_sse42_pcmpestriz128: {
14848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14849 case Intrinsic::x86_sse42_pcmpistria128:
14850 Opcode = X86ISD::PCMPISTRI;
14851 X86CC = X86::COND_A;
14853 case Intrinsic::x86_sse42_pcmpestria128:
14854 Opcode = X86ISD::PCMPESTRI;
14855 X86CC = X86::COND_A;
14857 case Intrinsic::x86_sse42_pcmpistric128:
14858 Opcode = X86ISD::PCMPISTRI;
14859 X86CC = X86::COND_B;
14861 case Intrinsic::x86_sse42_pcmpestric128:
14862 Opcode = X86ISD::PCMPESTRI;
14863 X86CC = X86::COND_B;
14865 case Intrinsic::x86_sse42_pcmpistrio128:
14866 Opcode = X86ISD::PCMPISTRI;
14867 X86CC = X86::COND_O;
14869 case Intrinsic::x86_sse42_pcmpestrio128:
14870 Opcode = X86ISD::PCMPESTRI;
14871 X86CC = X86::COND_O;
14873 case Intrinsic::x86_sse42_pcmpistris128:
14874 Opcode = X86ISD::PCMPISTRI;
14875 X86CC = X86::COND_S;
14877 case Intrinsic::x86_sse42_pcmpestris128:
14878 Opcode = X86ISD::PCMPESTRI;
14879 X86CC = X86::COND_S;
14881 case Intrinsic::x86_sse42_pcmpistriz128:
14882 Opcode = X86ISD::PCMPISTRI;
14883 X86CC = X86::COND_E;
14885 case Intrinsic::x86_sse42_pcmpestriz128:
14886 Opcode = X86ISD::PCMPESTRI;
14887 X86CC = X86::COND_E;
14890 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14891 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14892 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14893 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14894 DAG.getConstant(X86CC, MVT::i8),
14895 SDValue(PCMP.getNode(), 1));
14896 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14899 case Intrinsic::x86_sse42_pcmpistri128:
14900 case Intrinsic::x86_sse42_pcmpestri128: {
14902 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14903 Opcode = X86ISD::PCMPISTRI;
14905 Opcode = X86ISD::PCMPESTRI;
14907 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14908 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14909 return DAG.getNode(Opcode, dl, VTs, NewOps);
14912 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14913 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14914 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14915 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14916 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14917 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14918 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14919 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14920 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14921 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14922 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14923 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
14924 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
14925 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
14926 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
14927 dl, Op.getValueType(),
14931 Op.getOperand(4), Op.getOperand(1), DAG);
14936 case Intrinsic::x86_fma_vfmadd_ps:
14937 case Intrinsic::x86_fma_vfmadd_pd:
14938 case Intrinsic::x86_fma_vfmsub_ps:
14939 case Intrinsic::x86_fma_vfmsub_pd:
14940 case Intrinsic::x86_fma_vfnmadd_ps:
14941 case Intrinsic::x86_fma_vfnmadd_pd:
14942 case Intrinsic::x86_fma_vfnmsub_ps:
14943 case Intrinsic::x86_fma_vfnmsub_pd:
14944 case Intrinsic::x86_fma_vfmaddsub_ps:
14945 case Intrinsic::x86_fma_vfmaddsub_pd:
14946 case Intrinsic::x86_fma_vfmsubadd_ps:
14947 case Intrinsic::x86_fma_vfmsubadd_pd:
14948 case Intrinsic::x86_fma_vfmadd_ps_256:
14949 case Intrinsic::x86_fma_vfmadd_pd_256:
14950 case Intrinsic::x86_fma_vfmsub_ps_256:
14951 case Intrinsic::x86_fma_vfmsub_pd_256:
14952 case Intrinsic::x86_fma_vfnmadd_ps_256:
14953 case Intrinsic::x86_fma_vfnmadd_pd_256:
14954 case Intrinsic::x86_fma_vfnmsub_ps_256:
14955 case Intrinsic::x86_fma_vfnmsub_pd_256:
14956 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14957 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14958 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14959 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14960 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
14961 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14965 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14966 SDValue Src, SDValue Mask, SDValue Base,
14967 SDValue Index, SDValue ScaleOp, SDValue Chain,
14968 const X86Subtarget * Subtarget) {
14970 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14971 assert(C && "Invalid scale type");
14972 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14973 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14974 Index.getSimpleValueType().getVectorNumElements());
14976 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14978 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14980 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14981 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14982 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14983 SDValue Segment = DAG.getRegister(0, MVT::i32);
14984 if (Src.getOpcode() == ISD::UNDEF)
14985 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14986 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14987 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14988 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14989 return DAG.getMergeValues(RetOps, dl);
14992 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14993 SDValue Src, SDValue Mask, SDValue Base,
14994 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14996 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14997 assert(C && "Invalid scale type");
14998 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14999 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15000 SDValue Segment = DAG.getRegister(0, MVT::i32);
15001 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15002 Index.getSimpleValueType().getVectorNumElements());
15004 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15006 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15008 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15009 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15010 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15011 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15012 return SDValue(Res, 1);
15015 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15016 SDValue Mask, SDValue Base, SDValue Index,
15017 SDValue ScaleOp, SDValue Chain) {
15019 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15020 assert(C && "Invalid scale type");
15021 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15022 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15023 SDValue Segment = DAG.getRegister(0, MVT::i32);
15025 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15027 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15029 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15031 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15032 //SDVTList VTs = DAG.getVTList(MVT::Other);
15033 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15034 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15035 return SDValue(Res, 0);
15038 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15039 // read performance monitor counters (x86_rdpmc).
15040 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15041 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15042 SmallVectorImpl<SDValue> &Results) {
15043 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15044 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15047 // The ECX register is used to select the index of the performance counter
15049 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15051 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15053 // Reads the content of a 64-bit performance counter and returns it in the
15054 // registers EDX:EAX.
15055 if (Subtarget->is64Bit()) {
15056 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15057 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15060 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15061 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15064 Chain = HI.getValue(1);
15066 if (Subtarget->is64Bit()) {
15067 // The EAX register is loaded with the low-order 32 bits. The EDX register
15068 // is loaded with the supported high-order bits of the counter.
15069 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15070 DAG.getConstant(32, MVT::i8));
15071 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15072 Results.push_back(Chain);
15076 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15077 SDValue Ops[] = { LO, HI };
15078 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15079 Results.push_back(Pair);
15080 Results.push_back(Chain);
15083 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15084 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15085 // also used to custom lower READCYCLECOUNTER nodes.
15086 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15087 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15088 SmallVectorImpl<SDValue> &Results) {
15089 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15090 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15093 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15094 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15095 // and the EAX register is loaded with the low-order 32 bits.
15096 if (Subtarget->is64Bit()) {
15097 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15098 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15101 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15102 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15105 SDValue Chain = HI.getValue(1);
15107 if (Opcode == X86ISD::RDTSCP_DAG) {
15108 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15110 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15111 // the ECX register. Add 'ecx' explicitly to the chain.
15112 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15114 // Explicitly store the content of ECX at the location passed in input
15115 // to the 'rdtscp' intrinsic.
15116 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15117 MachinePointerInfo(), false, false, 0);
15120 if (Subtarget->is64Bit()) {
15121 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15122 // the EAX register is loaded with the low-order 32 bits.
15123 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15124 DAG.getConstant(32, MVT::i8));
15125 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15126 Results.push_back(Chain);
15130 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15131 SDValue Ops[] = { LO, HI };
15132 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15133 Results.push_back(Pair);
15134 Results.push_back(Chain);
15137 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15138 SelectionDAG &DAG) {
15139 SmallVector<SDValue, 2> Results;
15141 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15143 return DAG.getMergeValues(Results, DL);
15147 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15148 SelectionDAG &DAG) {
15149 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15151 const IntrinsicData* IntrData = GetIntrinsicWithChain(IntNo);
15156 switch(IntrData->Type) {
15158 llvm_unreachable("Unknown Intrinsic Type");
15162 // Emit the node with the right value type.
15163 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15164 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15166 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15167 // Otherwise return the value from Rand, which is always 0, casted to i32.
15168 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15169 DAG.getConstant(1, Op->getValueType(1)),
15170 DAG.getConstant(X86::COND_B, MVT::i32),
15171 SDValue(Result.getNode(), 1) };
15172 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15173 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15176 // Return { result, isValid, chain }.
15177 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15178 SDValue(Result.getNode(), 2));
15181 //gather(v1, mask, index, base, scale);
15182 SDValue Chain = Op.getOperand(0);
15183 SDValue Src = Op.getOperand(2);
15184 SDValue Base = Op.getOperand(3);
15185 SDValue Index = Op.getOperand(4);
15186 SDValue Mask = Op.getOperand(5);
15187 SDValue Scale = Op.getOperand(6);
15188 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15192 //scatter(base, mask, index, v1, scale);
15193 SDValue Chain = Op.getOperand(0);
15194 SDValue Base = Op.getOperand(2);
15195 SDValue Mask = Op.getOperand(3);
15196 SDValue Index = Op.getOperand(4);
15197 SDValue Src = Op.getOperand(5);
15198 SDValue Scale = Op.getOperand(6);
15199 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15202 SDValue Hint = Op.getOperand(6);
15204 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15205 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15206 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15207 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15208 SDValue Chain = Op.getOperand(0);
15209 SDValue Mask = Op.getOperand(2);
15210 SDValue Index = Op.getOperand(3);
15211 SDValue Base = Op.getOperand(4);
15212 SDValue Scale = Op.getOperand(5);
15213 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15215 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15217 SmallVector<SDValue, 2> Results;
15218 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15219 return DAG.getMergeValues(Results, dl);
15221 // Read Performance Monitoring Counters.
15223 SmallVector<SDValue, 2> Results;
15224 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15225 return DAG.getMergeValues(Results, dl);
15227 // XTEST intrinsics.
15229 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15230 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15231 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15232 DAG.getConstant(X86::COND_NE, MVT::i8),
15234 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15235 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15236 Ret, SDValue(InTrans.getNode(), 1));
15240 SmallVector<SDValue, 2> Results;
15241 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15242 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15243 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15244 DAG.getConstant(-1, MVT::i8));
15245 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15246 Op.getOperand(4), GenCF.getValue(1));
15247 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15248 Op.getOperand(5), MachinePointerInfo(),
15250 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15251 DAG.getConstant(X86::COND_B, MVT::i8),
15253 Results.push_back(SetCC);
15254 Results.push_back(Store);
15255 return DAG.getMergeValues(Results, dl);
15260 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15261 SelectionDAG &DAG) const {
15262 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15263 MFI->setReturnAddressIsTaken(true);
15265 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15268 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15270 EVT PtrVT = getPointerTy();
15273 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15274 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15275 DAG.getSubtarget().getRegisterInfo());
15276 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15277 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15278 DAG.getNode(ISD::ADD, dl, PtrVT,
15279 FrameAddr, Offset),
15280 MachinePointerInfo(), false, false, false, 0);
15283 // Just load the return address.
15284 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15285 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15286 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15289 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15290 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15291 MFI->setFrameAddressIsTaken(true);
15293 EVT VT = Op.getValueType();
15294 SDLoc dl(Op); // FIXME probably not meaningful
15295 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15296 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15297 DAG.getSubtarget().getRegisterInfo());
15298 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15299 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15300 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15301 "Invalid Frame Register!");
15302 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15304 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15305 MachinePointerInfo(),
15306 false, false, false, 0);
15310 // FIXME? Maybe this could be a TableGen attribute on some registers and
15311 // this table could be generated automatically from RegInfo.
15312 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15314 unsigned Reg = StringSwitch<unsigned>(RegName)
15315 .Case("esp", X86::ESP)
15316 .Case("rsp", X86::RSP)
15320 report_fatal_error("Invalid register name global variable");
15323 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15324 SelectionDAG &DAG) const {
15325 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15326 DAG.getSubtarget().getRegisterInfo());
15327 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15330 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15331 SDValue Chain = Op.getOperand(0);
15332 SDValue Offset = Op.getOperand(1);
15333 SDValue Handler = Op.getOperand(2);
15336 EVT PtrVT = getPointerTy();
15337 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15338 DAG.getSubtarget().getRegisterInfo());
15339 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15340 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15341 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15342 "Invalid Frame Register!");
15343 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15344 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15346 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15347 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15348 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15349 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15351 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15353 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15354 DAG.getRegister(StoreAddrReg, PtrVT));
15357 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15358 SelectionDAG &DAG) const {
15360 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15361 DAG.getVTList(MVT::i32, MVT::Other),
15362 Op.getOperand(0), Op.getOperand(1));
15365 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15366 SelectionDAG &DAG) const {
15368 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15369 Op.getOperand(0), Op.getOperand(1));
15372 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15373 return Op.getOperand(0);
15376 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15377 SelectionDAG &DAG) const {
15378 SDValue Root = Op.getOperand(0);
15379 SDValue Trmp = Op.getOperand(1); // trampoline
15380 SDValue FPtr = Op.getOperand(2); // nested function
15381 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15384 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15385 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15387 if (Subtarget->is64Bit()) {
15388 SDValue OutChains[6];
15390 // Large code-model.
15391 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15392 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15394 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15395 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15397 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15399 // Load the pointer to the nested function into R11.
15400 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15401 SDValue Addr = Trmp;
15402 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15403 Addr, MachinePointerInfo(TrmpAddr),
15406 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15407 DAG.getConstant(2, MVT::i64));
15408 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15409 MachinePointerInfo(TrmpAddr, 2),
15412 // Load the 'nest' parameter value into R10.
15413 // R10 is specified in X86CallingConv.td
15414 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15415 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15416 DAG.getConstant(10, MVT::i64));
15417 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15418 Addr, MachinePointerInfo(TrmpAddr, 10),
15421 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15422 DAG.getConstant(12, MVT::i64));
15423 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15424 MachinePointerInfo(TrmpAddr, 12),
15427 // Jump to the nested function.
15428 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15429 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15430 DAG.getConstant(20, MVT::i64));
15431 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15432 Addr, MachinePointerInfo(TrmpAddr, 20),
15435 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15436 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15437 DAG.getConstant(22, MVT::i64));
15438 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15439 MachinePointerInfo(TrmpAddr, 22),
15442 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15444 const Function *Func =
15445 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15446 CallingConv::ID CC = Func->getCallingConv();
15451 llvm_unreachable("Unsupported calling convention");
15452 case CallingConv::C:
15453 case CallingConv::X86_StdCall: {
15454 // Pass 'nest' parameter in ECX.
15455 // Must be kept in sync with X86CallingConv.td
15456 NestReg = X86::ECX;
15458 // Check that ECX wasn't needed by an 'inreg' parameter.
15459 FunctionType *FTy = Func->getFunctionType();
15460 const AttributeSet &Attrs = Func->getAttributes();
15462 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15463 unsigned InRegCount = 0;
15466 for (FunctionType::param_iterator I = FTy->param_begin(),
15467 E = FTy->param_end(); I != E; ++I, ++Idx)
15468 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15469 // FIXME: should only count parameters that are lowered to integers.
15470 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15472 if (InRegCount > 2) {
15473 report_fatal_error("Nest register in use - reduce number of inreg"
15479 case CallingConv::X86_FastCall:
15480 case CallingConv::X86_ThisCall:
15481 case CallingConv::Fast:
15482 // Pass 'nest' parameter in EAX.
15483 // Must be kept in sync with X86CallingConv.td
15484 NestReg = X86::EAX;
15488 SDValue OutChains[4];
15489 SDValue Addr, Disp;
15491 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15492 DAG.getConstant(10, MVT::i32));
15493 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15495 // This is storing the opcode for MOV32ri.
15496 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15497 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15498 OutChains[0] = DAG.getStore(Root, dl,
15499 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15500 Trmp, MachinePointerInfo(TrmpAddr),
15503 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15504 DAG.getConstant(1, MVT::i32));
15505 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15506 MachinePointerInfo(TrmpAddr, 1),
15509 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15511 DAG.getConstant(5, MVT::i32));
15512 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15513 MachinePointerInfo(TrmpAddr, 5),
15516 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15517 DAG.getConstant(6, MVT::i32));
15518 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15519 MachinePointerInfo(TrmpAddr, 6),
15522 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15526 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15527 SelectionDAG &DAG) const {
15529 The rounding mode is in bits 11:10 of FPSR, and has the following
15531 00 Round to nearest
15536 FLT_ROUNDS, on the other hand, expects the following:
15543 To perform the conversion, we do:
15544 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15547 MachineFunction &MF = DAG.getMachineFunction();
15548 const TargetMachine &TM = MF.getTarget();
15549 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15550 unsigned StackAlignment = TFI.getStackAlignment();
15551 MVT VT = Op.getSimpleValueType();
15554 // Save FP Control Word to stack slot
15555 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15556 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15558 MachineMemOperand *MMO =
15559 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15560 MachineMemOperand::MOStore, 2, 2);
15562 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15563 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15564 DAG.getVTList(MVT::Other),
15565 Ops, MVT::i16, MMO);
15567 // Load FP Control Word from stack slot
15568 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15569 MachinePointerInfo(), false, false, false, 0);
15571 // Transform as necessary
15573 DAG.getNode(ISD::SRL, DL, MVT::i16,
15574 DAG.getNode(ISD::AND, DL, MVT::i16,
15575 CWD, DAG.getConstant(0x800, MVT::i16)),
15576 DAG.getConstant(11, MVT::i8));
15578 DAG.getNode(ISD::SRL, DL, MVT::i16,
15579 DAG.getNode(ISD::AND, DL, MVT::i16,
15580 CWD, DAG.getConstant(0x400, MVT::i16)),
15581 DAG.getConstant(9, MVT::i8));
15584 DAG.getNode(ISD::AND, DL, MVT::i16,
15585 DAG.getNode(ISD::ADD, DL, MVT::i16,
15586 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15587 DAG.getConstant(1, MVT::i16)),
15588 DAG.getConstant(3, MVT::i16));
15590 return DAG.getNode((VT.getSizeInBits() < 16 ?
15591 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15594 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15595 MVT VT = Op.getSimpleValueType();
15597 unsigned NumBits = VT.getSizeInBits();
15600 Op = Op.getOperand(0);
15601 if (VT == MVT::i8) {
15602 // Zero extend to i32 since there is not an i8 bsr.
15604 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15607 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15608 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15609 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15611 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15614 DAG.getConstant(NumBits+NumBits-1, OpVT),
15615 DAG.getConstant(X86::COND_E, MVT::i8),
15618 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15620 // Finally xor with NumBits-1.
15621 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15624 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15628 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15629 MVT VT = Op.getSimpleValueType();
15631 unsigned NumBits = VT.getSizeInBits();
15634 Op = Op.getOperand(0);
15635 if (VT == MVT::i8) {
15636 // Zero extend to i32 since there is not an i8 bsr.
15638 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15641 // Issue a bsr (scan bits in reverse).
15642 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15643 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15645 // And xor with NumBits-1.
15646 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15649 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15653 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15654 MVT VT = Op.getSimpleValueType();
15655 unsigned NumBits = VT.getSizeInBits();
15657 Op = Op.getOperand(0);
15659 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15660 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15661 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15663 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15666 DAG.getConstant(NumBits, VT),
15667 DAG.getConstant(X86::COND_E, MVT::i8),
15670 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15673 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15674 // ones, and then concatenate the result back.
15675 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15676 MVT VT = Op.getSimpleValueType();
15678 assert(VT.is256BitVector() && VT.isInteger() &&
15679 "Unsupported value type for operation");
15681 unsigned NumElems = VT.getVectorNumElements();
15684 // Extract the LHS vectors
15685 SDValue LHS = Op.getOperand(0);
15686 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15687 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15689 // Extract the RHS vectors
15690 SDValue RHS = Op.getOperand(1);
15691 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15692 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15694 MVT EltVT = VT.getVectorElementType();
15695 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15697 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15698 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15699 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15702 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15703 assert(Op.getSimpleValueType().is256BitVector() &&
15704 Op.getSimpleValueType().isInteger() &&
15705 "Only handle AVX 256-bit vector integer operation");
15706 return Lower256IntArith(Op, DAG);
15709 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15710 assert(Op.getSimpleValueType().is256BitVector() &&
15711 Op.getSimpleValueType().isInteger() &&
15712 "Only handle AVX 256-bit vector integer operation");
15713 return Lower256IntArith(Op, DAG);
15716 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15717 SelectionDAG &DAG) {
15719 MVT VT = Op.getSimpleValueType();
15721 // Decompose 256-bit ops into smaller 128-bit ops.
15722 if (VT.is256BitVector() && !Subtarget->hasInt256())
15723 return Lower256IntArith(Op, DAG);
15725 SDValue A = Op.getOperand(0);
15726 SDValue B = Op.getOperand(1);
15728 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15729 if (VT == MVT::v4i32) {
15730 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15731 "Should not custom lower when pmuldq is available!");
15733 // Extract the odd parts.
15734 static const int UnpackMask[] = { 1, -1, 3, -1 };
15735 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15736 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15738 // Multiply the even parts.
15739 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15740 // Now multiply odd parts.
15741 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15743 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15744 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15746 // Merge the two vectors back together with a shuffle. This expands into 2
15748 static const int ShufMask[] = { 0, 4, 2, 6 };
15749 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15752 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15753 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15755 // Ahi = psrlqi(a, 32);
15756 // Bhi = psrlqi(b, 32);
15758 // AloBlo = pmuludq(a, b);
15759 // AloBhi = pmuludq(a, Bhi);
15760 // AhiBlo = pmuludq(Ahi, b);
15762 // AloBhi = psllqi(AloBhi, 32);
15763 // AhiBlo = psllqi(AhiBlo, 32);
15764 // return AloBlo + AloBhi + AhiBlo;
15766 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15767 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15769 // Bit cast to 32-bit vectors for MULUDQ
15770 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15771 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15772 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15773 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15774 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15775 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15777 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15778 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15779 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15781 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15782 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15784 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15785 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15788 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15789 assert(Subtarget->isTargetWin64() && "Unexpected target");
15790 EVT VT = Op.getValueType();
15791 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15792 "Unexpected return type for lowering");
15796 switch (Op->getOpcode()) {
15797 default: llvm_unreachable("Unexpected request for libcall!");
15798 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15799 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15800 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15801 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15802 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15803 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15807 SDValue InChain = DAG.getEntryNode();
15809 TargetLowering::ArgListTy Args;
15810 TargetLowering::ArgListEntry Entry;
15811 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15812 EVT ArgVT = Op->getOperand(i).getValueType();
15813 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15814 "Unexpected argument type for lowering");
15815 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15816 Entry.Node = StackPtr;
15817 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15819 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15820 Entry.Ty = PointerType::get(ArgTy,0);
15821 Entry.isSExt = false;
15822 Entry.isZExt = false;
15823 Args.push_back(Entry);
15826 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15829 TargetLowering::CallLoweringInfo CLI(DAG);
15830 CLI.setDebugLoc(dl).setChain(InChain)
15831 .setCallee(getLibcallCallingConv(LC),
15832 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15833 Callee, std::move(Args), 0)
15834 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15836 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15837 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15840 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15841 SelectionDAG &DAG) {
15842 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15843 EVT VT = Op0.getValueType();
15846 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15847 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15849 // PMULxD operations multiply each even value (starting at 0) of LHS with
15850 // the related value of RHS and produce a widen result.
15851 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15852 // => <2 x i64> <ae|cg>
15854 // In other word, to have all the results, we need to perform two PMULxD:
15855 // 1. one with the even values.
15856 // 2. one with the odd values.
15857 // To achieve #2, with need to place the odd values at an even position.
15859 // Place the odd value at an even position (basically, shift all values 1
15860 // step to the left):
15861 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15862 // <a|b|c|d> => <b|undef|d|undef>
15863 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15864 // <e|f|g|h> => <f|undef|h|undef>
15865 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15867 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15869 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15870 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15872 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15873 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15874 // => <2 x i64> <ae|cg>
15875 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15876 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15877 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15878 // => <2 x i64> <bf|dh>
15879 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15880 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15882 // Shuffle it back into the right order.
15883 SDValue Highs, Lows;
15884 if (VT == MVT::v8i32) {
15885 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15886 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15887 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15888 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15890 const int HighMask[] = {1, 5, 3, 7};
15891 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15892 const int LowMask[] = {0, 4, 2, 6};
15893 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15896 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15897 // unsigned multiply.
15898 if (IsSigned && !Subtarget->hasSSE41()) {
15900 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15901 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15902 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15903 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15904 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15906 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15907 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15910 // The first result of MUL_LOHI is actually the low value, followed by the
15912 SDValue Ops[] = {Lows, Highs};
15913 return DAG.getMergeValues(Ops, dl);
15916 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15917 const X86Subtarget *Subtarget) {
15918 MVT VT = Op.getSimpleValueType();
15920 SDValue R = Op.getOperand(0);
15921 SDValue Amt = Op.getOperand(1);
15923 // Optimize shl/srl/sra with constant shift amount.
15924 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15925 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15926 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15928 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15929 (Subtarget->hasInt256() &&
15930 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15931 (Subtarget->hasAVX512() &&
15932 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15933 if (Op.getOpcode() == ISD::SHL)
15934 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15936 if (Op.getOpcode() == ISD::SRL)
15937 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15939 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15940 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15944 if (VT == MVT::v16i8) {
15945 if (Op.getOpcode() == ISD::SHL) {
15946 // Make a large shift.
15947 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15948 MVT::v8i16, R, ShiftAmt,
15950 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15951 // Zero out the rightmost bits.
15952 SmallVector<SDValue, 16> V(16,
15953 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15955 return DAG.getNode(ISD::AND, dl, VT, SHL,
15956 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15958 if (Op.getOpcode() == ISD::SRL) {
15959 // Make a large shift.
15960 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15961 MVT::v8i16, R, ShiftAmt,
15963 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15964 // Zero out the leftmost bits.
15965 SmallVector<SDValue, 16> V(16,
15966 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15968 return DAG.getNode(ISD::AND, dl, VT, SRL,
15969 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15971 if (Op.getOpcode() == ISD::SRA) {
15972 if (ShiftAmt == 7) {
15973 // R s>> 7 === R s< 0
15974 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15975 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15978 // R s>> a === ((R u>> a) ^ m) - m
15979 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15980 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15982 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15983 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15984 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15987 llvm_unreachable("Unknown shift opcode.");
15990 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15991 if (Op.getOpcode() == ISD::SHL) {
15992 // Make a large shift.
15993 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15994 MVT::v16i16, R, ShiftAmt,
15996 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15997 // Zero out the rightmost bits.
15998 SmallVector<SDValue, 32> V(32,
15999 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16001 return DAG.getNode(ISD::AND, dl, VT, SHL,
16002 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16004 if (Op.getOpcode() == ISD::SRL) {
16005 // Make a large shift.
16006 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16007 MVT::v16i16, R, ShiftAmt,
16009 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16010 // Zero out the leftmost bits.
16011 SmallVector<SDValue, 32> V(32,
16012 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16014 return DAG.getNode(ISD::AND, dl, VT, SRL,
16015 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16017 if (Op.getOpcode() == ISD::SRA) {
16018 if (ShiftAmt == 7) {
16019 // R s>> 7 === R s< 0
16020 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16021 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16024 // R s>> a === ((R u>> a) ^ m) - m
16025 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16026 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16028 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16029 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16030 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16033 llvm_unreachable("Unknown shift opcode.");
16038 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16039 if (!Subtarget->is64Bit() &&
16040 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16041 Amt.getOpcode() == ISD::BITCAST &&
16042 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16043 Amt = Amt.getOperand(0);
16044 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16045 VT.getVectorNumElements();
16046 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16047 uint64_t ShiftAmt = 0;
16048 for (unsigned i = 0; i != Ratio; ++i) {
16049 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16053 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16055 // Check remaining shift amounts.
16056 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16057 uint64_t ShAmt = 0;
16058 for (unsigned j = 0; j != Ratio; ++j) {
16059 ConstantSDNode *C =
16060 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16064 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16066 if (ShAmt != ShiftAmt)
16069 switch (Op.getOpcode()) {
16071 llvm_unreachable("Unknown shift opcode!");
16073 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16076 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16079 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16087 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16088 const X86Subtarget* Subtarget) {
16089 MVT VT = Op.getSimpleValueType();
16091 SDValue R = Op.getOperand(0);
16092 SDValue Amt = Op.getOperand(1);
16094 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16095 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16096 (Subtarget->hasInt256() &&
16097 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16098 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16099 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16101 EVT EltVT = VT.getVectorElementType();
16103 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16104 unsigned NumElts = VT.getVectorNumElements();
16106 for (i = 0; i != NumElts; ++i) {
16107 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16111 for (j = i; j != NumElts; ++j) {
16112 SDValue Arg = Amt.getOperand(j);
16113 if (Arg.getOpcode() == ISD::UNDEF) continue;
16114 if (Arg != Amt.getOperand(i))
16117 if (i != NumElts && j == NumElts)
16118 BaseShAmt = Amt.getOperand(i);
16120 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16121 Amt = Amt.getOperand(0);
16122 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16123 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16124 SDValue InVec = Amt.getOperand(0);
16125 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16126 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16128 for (; i != NumElts; ++i) {
16129 SDValue Arg = InVec.getOperand(i);
16130 if (Arg.getOpcode() == ISD::UNDEF) continue;
16134 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16135 if (ConstantSDNode *C =
16136 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16137 unsigned SplatIdx =
16138 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16139 if (C->getZExtValue() == SplatIdx)
16140 BaseShAmt = InVec.getOperand(1);
16143 if (!BaseShAmt.getNode())
16144 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16145 DAG.getIntPtrConstant(0));
16149 if (BaseShAmt.getNode()) {
16150 if (EltVT.bitsGT(MVT::i32))
16151 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16152 else if (EltVT.bitsLT(MVT::i32))
16153 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16155 switch (Op.getOpcode()) {
16157 llvm_unreachable("Unknown shift opcode!");
16159 switch (VT.SimpleTy) {
16160 default: return SDValue();
16169 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16172 switch (VT.SimpleTy) {
16173 default: return SDValue();
16180 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16183 switch (VT.SimpleTy) {
16184 default: return SDValue();
16193 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16199 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16200 if (!Subtarget->is64Bit() &&
16201 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16202 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16203 Amt.getOpcode() == ISD::BITCAST &&
16204 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16205 Amt = Amt.getOperand(0);
16206 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16207 VT.getVectorNumElements();
16208 std::vector<SDValue> Vals(Ratio);
16209 for (unsigned i = 0; i != Ratio; ++i)
16210 Vals[i] = Amt.getOperand(i);
16211 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16212 for (unsigned j = 0; j != Ratio; ++j)
16213 if (Vals[j] != Amt.getOperand(i + j))
16216 switch (Op.getOpcode()) {
16218 llvm_unreachable("Unknown shift opcode!");
16220 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16222 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16224 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16231 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16232 SelectionDAG &DAG) {
16233 MVT VT = Op.getSimpleValueType();
16235 SDValue R = Op.getOperand(0);
16236 SDValue Amt = Op.getOperand(1);
16239 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16240 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16242 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16246 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16250 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16252 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16253 if (Subtarget->hasInt256()) {
16254 if (Op.getOpcode() == ISD::SRL &&
16255 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16256 VT == MVT::v4i64 || VT == MVT::v8i32))
16258 if (Op.getOpcode() == ISD::SHL &&
16259 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16260 VT == MVT::v4i64 || VT == MVT::v8i32))
16262 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16266 // If possible, lower this packed shift into a vector multiply instead of
16267 // expanding it into a sequence of scalar shifts.
16268 // Do this only if the vector shift count is a constant build_vector.
16269 if (Op.getOpcode() == ISD::SHL &&
16270 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16271 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16272 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16273 SmallVector<SDValue, 8> Elts;
16274 EVT SVT = VT.getScalarType();
16275 unsigned SVTBits = SVT.getSizeInBits();
16276 const APInt &One = APInt(SVTBits, 1);
16277 unsigned NumElems = VT.getVectorNumElements();
16279 for (unsigned i=0; i !=NumElems; ++i) {
16280 SDValue Op = Amt->getOperand(i);
16281 if (Op->getOpcode() == ISD::UNDEF) {
16282 Elts.push_back(Op);
16286 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16287 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16288 uint64_t ShAmt = C.getZExtValue();
16289 if (ShAmt >= SVTBits) {
16290 Elts.push_back(DAG.getUNDEF(SVT));
16293 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16295 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16296 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16299 // Lower SHL with variable shift amount.
16300 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16301 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16303 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16304 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16305 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16306 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16309 // If possible, lower this shift as a sequence of two shifts by
16310 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16312 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16314 // Could be rewritten as:
16315 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16317 // The advantage is that the two shifts from the example would be
16318 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16319 // the vector shift into four scalar shifts plus four pairs of vector
16321 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16322 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16323 unsigned TargetOpcode = X86ISD::MOVSS;
16324 bool CanBeSimplified;
16325 // The splat value for the first packed shift (the 'X' from the example).
16326 SDValue Amt1 = Amt->getOperand(0);
16327 // The splat value for the second packed shift (the 'Y' from the example).
16328 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16329 Amt->getOperand(2);
16331 // See if it is possible to replace this node with a sequence of
16332 // two shifts followed by a MOVSS/MOVSD
16333 if (VT == MVT::v4i32) {
16334 // Check if it is legal to use a MOVSS.
16335 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16336 Amt2 == Amt->getOperand(3);
16337 if (!CanBeSimplified) {
16338 // Otherwise, check if we can still simplify this node using a MOVSD.
16339 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16340 Amt->getOperand(2) == Amt->getOperand(3);
16341 TargetOpcode = X86ISD::MOVSD;
16342 Amt2 = Amt->getOperand(2);
16345 // Do similar checks for the case where the machine value type
16347 CanBeSimplified = Amt1 == Amt->getOperand(1);
16348 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16349 CanBeSimplified = Amt2 == Amt->getOperand(i);
16351 if (!CanBeSimplified) {
16352 TargetOpcode = X86ISD::MOVSD;
16353 CanBeSimplified = true;
16354 Amt2 = Amt->getOperand(4);
16355 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16356 CanBeSimplified = Amt1 == Amt->getOperand(i);
16357 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16358 CanBeSimplified = Amt2 == Amt->getOperand(j);
16362 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16363 isa<ConstantSDNode>(Amt2)) {
16364 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16365 EVT CastVT = MVT::v4i32;
16367 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16368 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16370 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16371 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16372 if (TargetOpcode == X86ISD::MOVSD)
16373 CastVT = MVT::v2i64;
16374 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16375 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16376 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16378 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16382 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16383 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16386 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16387 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16389 // Turn 'a' into a mask suitable for VSELECT
16390 SDValue VSelM = DAG.getConstant(0x80, VT);
16391 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16392 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16394 SDValue CM1 = DAG.getConstant(0x0f, VT);
16395 SDValue CM2 = DAG.getConstant(0x3f, VT);
16397 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16398 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16399 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16400 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16401 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16404 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16405 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16406 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16408 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16409 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16410 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16411 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16412 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16415 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16416 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16417 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16419 // return VSELECT(r, r+r, a);
16420 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16421 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16425 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16426 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16427 // solution better.
16428 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16429 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16431 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16432 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16433 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16434 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16435 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16438 // Decompose 256-bit shifts into smaller 128-bit shifts.
16439 if (VT.is256BitVector()) {
16440 unsigned NumElems = VT.getVectorNumElements();
16441 MVT EltVT = VT.getVectorElementType();
16442 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16444 // Extract the two vectors
16445 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16446 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16448 // Recreate the shift amount vectors
16449 SDValue Amt1, Amt2;
16450 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16451 // Constant shift amount
16452 SmallVector<SDValue, 4> Amt1Csts;
16453 SmallVector<SDValue, 4> Amt2Csts;
16454 for (unsigned i = 0; i != NumElems/2; ++i)
16455 Amt1Csts.push_back(Amt->getOperand(i));
16456 for (unsigned i = NumElems/2; i != NumElems; ++i)
16457 Amt2Csts.push_back(Amt->getOperand(i));
16459 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16460 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16462 // Variable shift amount
16463 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16464 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16467 // Issue new vector shifts for the smaller types
16468 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16469 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16471 // Concatenate the result back
16472 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16478 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16479 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16480 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16481 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16482 // has only one use.
16483 SDNode *N = Op.getNode();
16484 SDValue LHS = N->getOperand(0);
16485 SDValue RHS = N->getOperand(1);
16486 unsigned BaseOp = 0;
16489 switch (Op.getOpcode()) {
16490 default: llvm_unreachable("Unknown ovf instruction!");
16492 // A subtract of one will be selected as a INC. Note that INC doesn't
16493 // set CF, so we can't do this for UADDO.
16494 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16496 BaseOp = X86ISD::INC;
16497 Cond = X86::COND_O;
16500 BaseOp = X86ISD::ADD;
16501 Cond = X86::COND_O;
16504 BaseOp = X86ISD::ADD;
16505 Cond = X86::COND_B;
16508 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16509 // set CF, so we can't do this for USUBO.
16510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16512 BaseOp = X86ISD::DEC;
16513 Cond = X86::COND_O;
16516 BaseOp = X86ISD::SUB;
16517 Cond = X86::COND_O;
16520 BaseOp = X86ISD::SUB;
16521 Cond = X86::COND_B;
16524 BaseOp = X86ISD::SMUL;
16525 Cond = X86::COND_O;
16527 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16528 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16530 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16533 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16534 DAG.getConstant(X86::COND_O, MVT::i32),
16535 SDValue(Sum.getNode(), 2));
16537 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16541 // Also sets EFLAGS.
16542 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16543 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16546 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16547 DAG.getConstant(Cond, MVT::i32),
16548 SDValue(Sum.getNode(), 1));
16550 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16553 // Sign extension of the low part of vector elements. This may be used either
16554 // when sign extend instructions are not available or if the vector element
16555 // sizes already match the sign-extended size. If the vector elements are in
16556 // their pre-extended size and sign extend instructions are available, that will
16557 // be handled by LowerSIGN_EXTEND.
16558 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16559 SelectionDAG &DAG) const {
16561 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16562 MVT VT = Op.getSimpleValueType();
16564 if (!Subtarget->hasSSE2() || !VT.isVector())
16567 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16568 ExtraVT.getScalarType().getSizeInBits();
16570 switch (VT.SimpleTy) {
16571 default: return SDValue();
16574 if (!Subtarget->hasFp256())
16576 if (!Subtarget->hasInt256()) {
16577 // needs to be split
16578 unsigned NumElems = VT.getVectorNumElements();
16580 // Extract the LHS vectors
16581 SDValue LHS = Op.getOperand(0);
16582 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16583 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16585 MVT EltVT = VT.getVectorElementType();
16586 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16588 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16589 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16590 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16592 SDValue Extra = DAG.getValueType(ExtraVT);
16594 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16595 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16597 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16602 SDValue Op0 = Op.getOperand(0);
16604 // This is a sign extension of some low part of vector elements without
16605 // changing the size of the vector elements themselves:
16606 // Shift-Left + Shift-Right-Algebraic.
16607 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
16609 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
16615 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16616 SelectionDAG &DAG) {
16618 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16619 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16620 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16621 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16623 // The only fence that needs an instruction is a sequentially-consistent
16624 // cross-thread fence.
16625 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16626 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16627 // no-sse2). There isn't any reason to disable it if the target processor
16629 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16630 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16632 SDValue Chain = Op.getOperand(0);
16633 SDValue Zero = DAG.getConstant(0, MVT::i32);
16635 DAG.getRegister(X86::ESP, MVT::i32), // Base
16636 DAG.getTargetConstant(1, MVT::i8), // Scale
16637 DAG.getRegister(0, MVT::i32), // Index
16638 DAG.getTargetConstant(0, MVT::i32), // Disp
16639 DAG.getRegister(0, MVT::i32), // Segment.
16643 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16644 return SDValue(Res, 0);
16647 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16648 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16651 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16652 SelectionDAG &DAG) {
16653 MVT T = Op.getSimpleValueType();
16657 switch(T.SimpleTy) {
16658 default: llvm_unreachable("Invalid value type!");
16659 case MVT::i8: Reg = X86::AL; size = 1; break;
16660 case MVT::i16: Reg = X86::AX; size = 2; break;
16661 case MVT::i32: Reg = X86::EAX; size = 4; break;
16663 assert(Subtarget->is64Bit() && "Node not type legal!");
16664 Reg = X86::RAX; size = 8;
16667 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16668 Op.getOperand(2), SDValue());
16669 SDValue Ops[] = { cpIn.getValue(0),
16672 DAG.getTargetConstant(size, MVT::i8),
16673 cpIn.getValue(1) };
16674 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16675 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16676 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16680 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16681 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16682 MVT::i32, cpOut.getValue(2));
16683 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16684 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16686 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16687 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16688 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16692 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16693 SelectionDAG &DAG) {
16694 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16695 MVT DstVT = Op.getSimpleValueType();
16697 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16698 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16699 if (DstVT != MVT::f64)
16700 // This conversion needs to be expanded.
16703 SDValue InVec = Op->getOperand(0);
16705 unsigned NumElts = SrcVT.getVectorNumElements();
16706 EVT SVT = SrcVT.getVectorElementType();
16708 // Widen the vector in input in the case of MVT::v2i32.
16709 // Example: from MVT::v2i32 to MVT::v4i32.
16710 SmallVector<SDValue, 16> Elts;
16711 for (unsigned i = 0, e = NumElts; i != e; ++i)
16712 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16713 DAG.getIntPtrConstant(i)));
16715 // Explicitly mark the extra elements as Undef.
16716 SDValue Undef = DAG.getUNDEF(SVT);
16717 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16718 Elts.push_back(Undef);
16720 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16721 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16722 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16723 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16724 DAG.getIntPtrConstant(0));
16727 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16728 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16729 assert((DstVT == MVT::i64 ||
16730 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16731 "Unexpected custom BITCAST");
16732 // i64 <=> MMX conversions are Legal.
16733 if (SrcVT==MVT::i64 && DstVT.isVector())
16735 if (DstVT==MVT::i64 && SrcVT.isVector())
16737 // MMX <=> MMX conversions are Legal.
16738 if (SrcVT.isVector() && DstVT.isVector())
16740 // All other conversions need to be expanded.
16744 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16745 SDNode *Node = Op.getNode();
16747 EVT T = Node->getValueType(0);
16748 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16749 DAG.getConstant(0, T), Node->getOperand(2));
16750 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16751 cast<AtomicSDNode>(Node)->getMemoryVT(),
16752 Node->getOperand(0),
16753 Node->getOperand(1), negOp,
16754 cast<AtomicSDNode>(Node)->getMemOperand(),
16755 cast<AtomicSDNode>(Node)->getOrdering(),
16756 cast<AtomicSDNode>(Node)->getSynchScope());
16759 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16760 SDNode *Node = Op.getNode();
16762 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16764 // Convert seq_cst store -> xchg
16765 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16766 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16767 // (The only way to get a 16-byte store is cmpxchg16b)
16768 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16769 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16770 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16771 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16772 cast<AtomicSDNode>(Node)->getMemoryVT(),
16773 Node->getOperand(0),
16774 Node->getOperand(1), Node->getOperand(2),
16775 cast<AtomicSDNode>(Node)->getMemOperand(),
16776 cast<AtomicSDNode>(Node)->getOrdering(),
16777 cast<AtomicSDNode>(Node)->getSynchScope());
16778 return Swap.getValue(1);
16780 // Other atomic stores have a simple pattern.
16784 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16785 EVT VT = Op.getNode()->getSimpleValueType(0);
16787 // Let legalize expand this if it isn't a legal type yet.
16788 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16791 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16794 bool ExtraOp = false;
16795 switch (Op.getOpcode()) {
16796 default: llvm_unreachable("Invalid code");
16797 case ISD::ADDC: Opc = X86ISD::ADD; break;
16798 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16799 case ISD::SUBC: Opc = X86ISD::SUB; break;
16800 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16804 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16806 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16807 Op.getOperand(1), Op.getOperand(2));
16810 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16811 SelectionDAG &DAG) {
16812 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16814 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16815 // which returns the values as { float, float } (in XMM0) or
16816 // { double, double } (which is returned in XMM0, XMM1).
16818 SDValue Arg = Op.getOperand(0);
16819 EVT ArgVT = Arg.getValueType();
16820 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16822 TargetLowering::ArgListTy Args;
16823 TargetLowering::ArgListEntry Entry;
16827 Entry.isSExt = false;
16828 Entry.isZExt = false;
16829 Args.push_back(Entry);
16831 bool isF64 = ArgVT == MVT::f64;
16832 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16833 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16834 // the results are returned via SRet in memory.
16835 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16837 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16839 Type *RetTy = isF64
16840 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16841 : (Type*)VectorType::get(ArgTy, 4);
16843 TargetLowering::CallLoweringInfo CLI(DAG);
16844 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16845 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16847 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16850 // Returned in xmm0 and xmm1.
16851 return CallResult.first;
16853 // Returned in bits 0:31 and 32:64 xmm0.
16854 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16855 CallResult.first, DAG.getIntPtrConstant(0));
16856 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16857 CallResult.first, DAG.getIntPtrConstant(1));
16858 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16859 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16862 /// LowerOperation - Provide custom lowering hooks for some operations.
16864 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16865 switch (Op.getOpcode()) {
16866 default: llvm_unreachable("Should not custom lower this!");
16867 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16868 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16869 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16870 return LowerCMP_SWAP(Op, Subtarget, DAG);
16871 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16872 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16873 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16874 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16875 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16876 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16877 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16878 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16879 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16880 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16881 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16882 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16883 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16884 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16885 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16886 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16887 case ISD::SHL_PARTS:
16888 case ISD::SRA_PARTS:
16889 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16890 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16891 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16892 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16893 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16894 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16895 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16896 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16897 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16898 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16899 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16901 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
16902 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16903 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16904 case ISD::SETCC: return LowerSETCC(Op, DAG);
16905 case ISD::SELECT: return LowerSELECT(Op, DAG);
16906 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16907 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16908 case ISD::VASTART: return LowerVASTART(Op, DAG);
16909 case ISD::VAARG: return LowerVAARG(Op, DAG);
16910 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16911 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16912 case ISD::INTRINSIC_VOID:
16913 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16914 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16915 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16916 case ISD::FRAME_TO_ARGS_OFFSET:
16917 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16918 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16919 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16920 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16921 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16922 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16923 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16924 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16925 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16926 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16927 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16928 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16929 case ISD::UMUL_LOHI:
16930 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16933 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16939 case ISD::UMULO: return LowerXALUO(Op, DAG);
16940 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16941 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16945 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16946 case ISD::ADD: return LowerADD(Op, DAG);
16947 case ISD::SUB: return LowerSUB(Op, DAG);
16948 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16952 static void ReplaceATOMIC_LOAD(SDNode *Node,
16953 SmallVectorImpl<SDValue> &Results,
16954 SelectionDAG &DAG) {
16956 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16958 // Convert wide load -> cmpxchg8b/cmpxchg16b
16959 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16960 // (The only way to get a 16-byte load is cmpxchg16b)
16961 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16962 SDValue Zero = DAG.getConstant(0, VT);
16963 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16965 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16966 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16967 cast<AtomicSDNode>(Node)->getMemOperand(),
16968 cast<AtomicSDNode>(Node)->getOrdering(),
16969 cast<AtomicSDNode>(Node)->getOrdering(),
16970 cast<AtomicSDNode>(Node)->getSynchScope());
16971 Results.push_back(Swap.getValue(0));
16972 Results.push_back(Swap.getValue(2));
16975 /// ReplaceNodeResults - Replace a node with an illegal result type
16976 /// with a new node built out of custom code.
16977 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16978 SmallVectorImpl<SDValue>&Results,
16979 SelectionDAG &DAG) const {
16981 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16982 switch (N->getOpcode()) {
16984 llvm_unreachable("Do not know how to custom type legalize this operation!");
16985 case ISD::SIGN_EXTEND_INREG:
16990 // We don't want to expand or promote these.
16997 case ISD::UDIVREM: {
16998 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16999 Results.push_back(V);
17002 case ISD::FP_TO_SINT:
17003 case ISD::FP_TO_UINT: {
17004 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17006 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17009 std::pair<SDValue,SDValue> Vals =
17010 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17011 SDValue FIST = Vals.first, StackSlot = Vals.second;
17012 if (FIST.getNode()) {
17013 EVT VT = N->getValueType(0);
17014 // Return a load from the stack slot.
17015 if (StackSlot.getNode())
17016 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17017 MachinePointerInfo(),
17018 false, false, false, 0));
17020 Results.push_back(FIST);
17024 case ISD::UINT_TO_FP: {
17025 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17026 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17027 N->getValueType(0) != MVT::v2f32)
17029 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17031 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17033 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17034 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17035 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17036 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17037 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17038 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17041 case ISD::FP_ROUND: {
17042 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17044 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17045 Results.push_back(V);
17048 case ISD::INTRINSIC_W_CHAIN: {
17049 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17051 default : llvm_unreachable("Do not know how to custom type "
17052 "legalize this intrinsic operation!");
17053 case Intrinsic::x86_rdtsc:
17054 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17056 case Intrinsic::x86_rdtscp:
17057 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17059 case Intrinsic::x86_rdpmc:
17060 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17063 case ISD::READCYCLECOUNTER: {
17064 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17067 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17068 EVT T = N->getValueType(0);
17069 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17070 bool Regs64bit = T == MVT::i128;
17071 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17072 SDValue cpInL, cpInH;
17073 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17074 DAG.getConstant(0, HalfT));
17075 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17076 DAG.getConstant(1, HalfT));
17077 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17078 Regs64bit ? X86::RAX : X86::EAX,
17080 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17081 Regs64bit ? X86::RDX : X86::EDX,
17082 cpInH, cpInL.getValue(1));
17083 SDValue swapInL, swapInH;
17084 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17085 DAG.getConstant(0, HalfT));
17086 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17087 DAG.getConstant(1, HalfT));
17088 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17089 Regs64bit ? X86::RBX : X86::EBX,
17090 swapInL, cpInH.getValue(1));
17091 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17092 Regs64bit ? X86::RCX : X86::ECX,
17093 swapInH, swapInL.getValue(1));
17094 SDValue Ops[] = { swapInH.getValue(0),
17096 swapInH.getValue(1) };
17097 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17098 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17099 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17100 X86ISD::LCMPXCHG8_DAG;
17101 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17102 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17103 Regs64bit ? X86::RAX : X86::EAX,
17104 HalfT, Result.getValue(1));
17105 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17106 Regs64bit ? X86::RDX : X86::EDX,
17107 HalfT, cpOutL.getValue(2));
17108 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17110 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17111 MVT::i32, cpOutH.getValue(2));
17113 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17114 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17115 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17117 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17118 Results.push_back(Success);
17119 Results.push_back(EFLAGS.getValue(1));
17122 case ISD::ATOMIC_SWAP:
17123 case ISD::ATOMIC_LOAD_ADD:
17124 case ISD::ATOMIC_LOAD_SUB:
17125 case ISD::ATOMIC_LOAD_AND:
17126 case ISD::ATOMIC_LOAD_OR:
17127 case ISD::ATOMIC_LOAD_XOR:
17128 case ISD::ATOMIC_LOAD_NAND:
17129 case ISD::ATOMIC_LOAD_MIN:
17130 case ISD::ATOMIC_LOAD_MAX:
17131 case ISD::ATOMIC_LOAD_UMIN:
17132 case ISD::ATOMIC_LOAD_UMAX:
17133 // Delegate to generic TypeLegalization. Situations we can really handle
17134 // should have already been dealt with by X86AtomicExpandPass.cpp.
17136 case ISD::ATOMIC_LOAD: {
17137 ReplaceATOMIC_LOAD(N, Results, DAG);
17140 case ISD::BITCAST: {
17141 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17142 EVT DstVT = N->getValueType(0);
17143 EVT SrcVT = N->getOperand(0)->getValueType(0);
17145 if (SrcVT != MVT::f64 ||
17146 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17149 unsigned NumElts = DstVT.getVectorNumElements();
17150 EVT SVT = DstVT.getVectorElementType();
17151 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17152 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17153 MVT::v2f64, N->getOperand(0));
17154 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17156 if (ExperimentalVectorWideningLegalization) {
17157 // If we are legalizing vectors by widening, we already have the desired
17158 // legal vector type, just return it.
17159 Results.push_back(ToVecInt);
17163 SmallVector<SDValue, 8> Elts;
17164 for (unsigned i = 0, e = NumElts; i != e; ++i)
17165 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17166 ToVecInt, DAG.getIntPtrConstant(i)));
17168 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17173 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17175 default: return nullptr;
17176 case X86ISD::BSF: return "X86ISD::BSF";
17177 case X86ISD::BSR: return "X86ISD::BSR";
17178 case X86ISD::SHLD: return "X86ISD::SHLD";
17179 case X86ISD::SHRD: return "X86ISD::SHRD";
17180 case X86ISD::FAND: return "X86ISD::FAND";
17181 case X86ISD::FANDN: return "X86ISD::FANDN";
17182 case X86ISD::FOR: return "X86ISD::FOR";
17183 case X86ISD::FXOR: return "X86ISD::FXOR";
17184 case X86ISD::FSRL: return "X86ISD::FSRL";
17185 case X86ISD::FILD: return "X86ISD::FILD";
17186 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17187 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17188 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17189 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17190 case X86ISD::FLD: return "X86ISD::FLD";
17191 case X86ISD::FST: return "X86ISD::FST";
17192 case X86ISD::CALL: return "X86ISD::CALL";
17193 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17194 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17195 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17196 case X86ISD::BT: return "X86ISD::BT";
17197 case X86ISD::CMP: return "X86ISD::CMP";
17198 case X86ISD::COMI: return "X86ISD::COMI";
17199 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17200 case X86ISD::CMPM: return "X86ISD::CMPM";
17201 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17202 case X86ISD::SETCC: return "X86ISD::SETCC";
17203 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17204 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17205 case X86ISD::CMOV: return "X86ISD::CMOV";
17206 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17207 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17208 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17209 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17210 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17211 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17212 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17213 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17214 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17215 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17216 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17217 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17218 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17219 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17220 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17221 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17222 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17223 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17224 case X86ISD::HADD: return "X86ISD::HADD";
17225 case X86ISD::HSUB: return "X86ISD::HSUB";
17226 case X86ISD::FHADD: return "X86ISD::FHADD";
17227 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17228 case X86ISD::UMAX: return "X86ISD::UMAX";
17229 case X86ISD::UMIN: return "X86ISD::UMIN";
17230 case X86ISD::SMAX: return "X86ISD::SMAX";
17231 case X86ISD::SMIN: return "X86ISD::SMIN";
17232 case X86ISD::FMAX: return "X86ISD::FMAX";
17233 case X86ISD::FMIN: return "X86ISD::FMIN";
17234 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17235 case X86ISD::FMINC: return "X86ISD::FMINC";
17236 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17237 case X86ISD::FRCP: return "X86ISD::FRCP";
17238 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17239 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17240 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17241 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17242 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17243 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17244 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17245 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17246 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17247 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17248 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17249 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17250 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17251 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17252 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17253 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17254 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17255 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17256 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17257 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17258 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17259 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17260 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17261 case X86ISD::VSHL: return "X86ISD::VSHL";
17262 case X86ISD::VSRL: return "X86ISD::VSRL";
17263 case X86ISD::VSRA: return "X86ISD::VSRA";
17264 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17265 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17266 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17267 case X86ISD::CMPP: return "X86ISD::CMPP";
17268 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17269 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17270 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17271 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17272 case X86ISD::ADD: return "X86ISD::ADD";
17273 case X86ISD::SUB: return "X86ISD::SUB";
17274 case X86ISD::ADC: return "X86ISD::ADC";
17275 case X86ISD::SBB: return "X86ISD::SBB";
17276 case X86ISD::SMUL: return "X86ISD::SMUL";
17277 case X86ISD::UMUL: return "X86ISD::UMUL";
17278 case X86ISD::INC: return "X86ISD::INC";
17279 case X86ISD::DEC: return "X86ISD::DEC";
17280 case X86ISD::OR: return "X86ISD::OR";
17281 case X86ISD::XOR: return "X86ISD::XOR";
17282 case X86ISD::AND: return "X86ISD::AND";
17283 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17284 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17285 case X86ISD::PTEST: return "X86ISD::PTEST";
17286 case X86ISD::TESTP: return "X86ISD::TESTP";
17287 case X86ISD::TESTM: return "X86ISD::TESTM";
17288 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17289 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17290 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17291 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17292 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17293 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17294 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17295 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17296 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17297 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17298 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17299 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17300 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17301 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17302 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17303 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17304 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17305 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17306 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17307 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17308 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17309 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17310 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17311 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17312 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17313 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17314 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17315 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17316 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17317 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17318 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17319 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17320 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17321 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17322 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17323 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17324 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17325 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17326 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17327 case X86ISD::SAHF: return "X86ISD::SAHF";
17328 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17329 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17330 case X86ISD::FMADD: return "X86ISD::FMADD";
17331 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17332 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17333 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17334 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17335 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17336 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17337 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17338 case X86ISD::XTEST: return "X86ISD::XTEST";
17342 // isLegalAddressingMode - Return true if the addressing mode represented
17343 // by AM is legal for this target, for a load/store of the specified type.
17344 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17346 // X86 supports extremely general addressing modes.
17347 CodeModel::Model M = getTargetMachine().getCodeModel();
17348 Reloc::Model R = getTargetMachine().getRelocationModel();
17350 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17351 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17356 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17358 // If a reference to this global requires an extra load, we can't fold it.
17359 if (isGlobalStubReference(GVFlags))
17362 // If BaseGV requires a register for the PIC base, we cannot also have a
17363 // BaseReg specified.
17364 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17367 // If lower 4G is not available, then we must use rip-relative addressing.
17368 if ((M != CodeModel::Small || R != Reloc::Static) &&
17369 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17373 switch (AM.Scale) {
17379 // These scales always work.
17384 // These scales are formed with basereg+scalereg. Only accept if there is
17389 default: // Other stuff never works.
17396 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17397 unsigned Bits = Ty->getScalarSizeInBits();
17399 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17400 // particularly cheaper than those without.
17404 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17405 // variable shifts just as cheap as scalar ones.
17406 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17409 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17410 // fully general vector.
17414 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17415 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17417 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17418 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17419 return NumBits1 > NumBits2;
17422 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17423 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17426 if (!isTypeLegal(EVT::getEVT(Ty1)))
17429 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17431 // Assuming the caller doesn't have a zeroext or signext return parameter,
17432 // truncation all the way down to i1 is valid.
17436 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17437 return isInt<32>(Imm);
17440 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17441 // Can also use sub to handle negated immediates.
17442 return isInt<32>(Imm);
17445 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17446 if (!VT1.isInteger() || !VT2.isInteger())
17448 unsigned NumBits1 = VT1.getSizeInBits();
17449 unsigned NumBits2 = VT2.getSizeInBits();
17450 return NumBits1 > NumBits2;
17453 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17454 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17455 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17458 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17459 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17460 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17463 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17464 EVT VT1 = Val.getValueType();
17465 if (isZExtFree(VT1, VT2))
17468 if (Val.getOpcode() != ISD::LOAD)
17471 if (!VT1.isSimple() || !VT1.isInteger() ||
17472 !VT2.isSimple() || !VT2.isInteger())
17475 switch (VT1.getSimpleVT().SimpleTy) {
17480 // X86 has 8, 16, and 32-bit zero-extending loads.
17488 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17489 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17492 VT = VT.getScalarType();
17494 if (!VT.isSimple())
17497 switch (VT.getSimpleVT().SimpleTy) {
17508 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17509 // i16 instructions are longer (0x66 prefix) and potentially slower.
17510 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17513 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17514 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17515 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17516 /// are assumed to be legal.
17518 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17520 if (!VT.isSimple())
17523 MVT SVT = VT.getSimpleVT();
17525 // Very little shuffling can be done for 64-bit vectors right now.
17526 if (VT.getSizeInBits() == 64)
17529 // If this is a single-input shuffle with no 128 bit lane crossings we can
17530 // lower it into pshufb.
17531 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17532 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17533 bool isLegal = true;
17534 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17535 if (M[I] >= (int)SVT.getVectorNumElements() ||
17536 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17545 // FIXME: blends, shifts.
17546 return (SVT.getVectorNumElements() == 2 ||
17547 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17548 isMOVLMask(M, SVT) ||
17549 isMOVHLPSMask(M, SVT) ||
17550 isSHUFPMask(M, SVT) ||
17551 isPSHUFDMask(M, SVT) ||
17552 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17553 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17554 isPALIGNRMask(M, SVT, Subtarget) ||
17555 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17556 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17557 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17558 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17559 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17563 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17565 if (!VT.isSimple())
17568 MVT SVT = VT.getSimpleVT();
17569 unsigned NumElts = SVT.getVectorNumElements();
17570 // FIXME: This collection of masks seems suspect.
17573 if (NumElts == 4 && SVT.is128BitVector()) {
17574 return (isMOVLMask(Mask, SVT) ||
17575 isCommutedMOVLMask(Mask, SVT, true) ||
17576 isSHUFPMask(Mask, SVT) ||
17577 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17582 //===----------------------------------------------------------------------===//
17583 // X86 Scheduler Hooks
17584 //===----------------------------------------------------------------------===//
17586 /// Utility function to emit xbegin specifying the start of an RTM region.
17587 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17588 const TargetInstrInfo *TII) {
17589 DebugLoc DL = MI->getDebugLoc();
17591 const BasicBlock *BB = MBB->getBasicBlock();
17592 MachineFunction::iterator I = MBB;
17595 // For the v = xbegin(), we generate
17606 MachineBasicBlock *thisMBB = MBB;
17607 MachineFunction *MF = MBB->getParent();
17608 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17609 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17610 MF->insert(I, mainMBB);
17611 MF->insert(I, sinkMBB);
17613 // Transfer the remainder of BB and its successor edges to sinkMBB.
17614 sinkMBB->splice(sinkMBB->begin(), MBB,
17615 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17616 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17620 // # fallthrough to mainMBB
17621 // # abortion to sinkMBB
17622 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17623 thisMBB->addSuccessor(mainMBB);
17624 thisMBB->addSuccessor(sinkMBB);
17628 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17629 mainMBB->addSuccessor(sinkMBB);
17632 // EAX is live into the sinkMBB
17633 sinkMBB->addLiveIn(X86::EAX);
17634 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17635 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17638 MI->eraseFromParent();
17642 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17643 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17644 // in the .td file.
17645 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17646 const TargetInstrInfo *TII) {
17648 switch (MI->getOpcode()) {
17649 default: llvm_unreachable("illegal opcode!");
17650 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17651 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17652 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17653 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17654 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17655 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17656 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17657 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17660 DebugLoc dl = MI->getDebugLoc();
17661 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17663 unsigned NumArgs = MI->getNumOperands();
17664 for (unsigned i = 1; i < NumArgs; ++i) {
17665 MachineOperand &Op = MI->getOperand(i);
17666 if (!(Op.isReg() && Op.isImplicit()))
17667 MIB.addOperand(Op);
17669 if (MI->hasOneMemOperand())
17670 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17672 BuildMI(*BB, MI, dl,
17673 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17674 .addReg(X86::XMM0);
17676 MI->eraseFromParent();
17680 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17681 // defs in an instruction pattern
17682 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17683 const TargetInstrInfo *TII) {
17685 switch (MI->getOpcode()) {
17686 default: llvm_unreachable("illegal opcode!");
17687 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17688 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17689 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17690 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17691 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17692 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17693 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17694 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17697 DebugLoc dl = MI->getDebugLoc();
17698 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17700 unsigned NumArgs = MI->getNumOperands(); // remove the results
17701 for (unsigned i = 1; i < NumArgs; ++i) {
17702 MachineOperand &Op = MI->getOperand(i);
17703 if (!(Op.isReg() && Op.isImplicit()))
17704 MIB.addOperand(Op);
17706 if (MI->hasOneMemOperand())
17707 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17709 BuildMI(*BB, MI, dl,
17710 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17713 MI->eraseFromParent();
17717 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17718 const TargetInstrInfo *TII,
17719 const X86Subtarget* Subtarget) {
17720 DebugLoc dl = MI->getDebugLoc();
17722 // Address into RAX/EAX, other two args into ECX, EDX.
17723 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17724 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17725 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17726 for (int i = 0; i < X86::AddrNumOperands; ++i)
17727 MIB.addOperand(MI->getOperand(i));
17729 unsigned ValOps = X86::AddrNumOperands;
17730 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17731 .addReg(MI->getOperand(ValOps).getReg());
17732 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17733 .addReg(MI->getOperand(ValOps+1).getReg());
17735 // The instruction doesn't actually take any operands though.
17736 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17738 MI->eraseFromParent(); // The pseudo is gone now.
17742 MachineBasicBlock *
17743 X86TargetLowering::EmitVAARG64WithCustomInserter(
17745 MachineBasicBlock *MBB) const {
17746 // Emit va_arg instruction on X86-64.
17748 // Operands to this pseudo-instruction:
17749 // 0 ) Output : destination address (reg)
17750 // 1-5) Input : va_list address (addr, i64mem)
17751 // 6 ) ArgSize : Size (in bytes) of vararg type
17752 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17753 // 8 ) Align : Alignment of type
17754 // 9 ) EFLAGS (implicit-def)
17756 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17757 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17759 unsigned DestReg = MI->getOperand(0).getReg();
17760 MachineOperand &Base = MI->getOperand(1);
17761 MachineOperand &Scale = MI->getOperand(2);
17762 MachineOperand &Index = MI->getOperand(3);
17763 MachineOperand &Disp = MI->getOperand(4);
17764 MachineOperand &Segment = MI->getOperand(5);
17765 unsigned ArgSize = MI->getOperand(6).getImm();
17766 unsigned ArgMode = MI->getOperand(7).getImm();
17767 unsigned Align = MI->getOperand(8).getImm();
17769 // Memory Reference
17770 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17771 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17772 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17774 // Machine Information
17775 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17776 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17777 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17778 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17779 DebugLoc DL = MI->getDebugLoc();
17781 // struct va_list {
17784 // i64 overflow_area (address)
17785 // i64 reg_save_area (address)
17787 // sizeof(va_list) = 24
17788 // alignment(va_list) = 8
17790 unsigned TotalNumIntRegs = 6;
17791 unsigned TotalNumXMMRegs = 8;
17792 bool UseGPOffset = (ArgMode == 1);
17793 bool UseFPOffset = (ArgMode == 2);
17794 unsigned MaxOffset = TotalNumIntRegs * 8 +
17795 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17797 /* Align ArgSize to a multiple of 8 */
17798 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17799 bool NeedsAlign = (Align > 8);
17801 MachineBasicBlock *thisMBB = MBB;
17802 MachineBasicBlock *overflowMBB;
17803 MachineBasicBlock *offsetMBB;
17804 MachineBasicBlock *endMBB;
17806 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17807 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17808 unsigned OffsetReg = 0;
17810 if (!UseGPOffset && !UseFPOffset) {
17811 // If we only pull from the overflow region, we don't create a branch.
17812 // We don't need to alter control flow.
17813 OffsetDestReg = 0; // unused
17814 OverflowDestReg = DestReg;
17816 offsetMBB = nullptr;
17817 overflowMBB = thisMBB;
17820 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17821 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17822 // If not, pull from overflow_area. (branch to overflowMBB)
17827 // offsetMBB overflowMBB
17832 // Registers for the PHI in endMBB
17833 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17834 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17836 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17837 MachineFunction *MF = MBB->getParent();
17838 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17839 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17840 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17842 MachineFunction::iterator MBBIter = MBB;
17845 // Insert the new basic blocks
17846 MF->insert(MBBIter, offsetMBB);
17847 MF->insert(MBBIter, overflowMBB);
17848 MF->insert(MBBIter, endMBB);
17850 // Transfer the remainder of MBB and its successor edges to endMBB.
17851 endMBB->splice(endMBB->begin(), thisMBB,
17852 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17853 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17855 // Make offsetMBB and overflowMBB successors of thisMBB
17856 thisMBB->addSuccessor(offsetMBB);
17857 thisMBB->addSuccessor(overflowMBB);
17859 // endMBB is a successor of both offsetMBB and overflowMBB
17860 offsetMBB->addSuccessor(endMBB);
17861 overflowMBB->addSuccessor(endMBB);
17863 // Load the offset value into a register
17864 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17865 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17869 .addDisp(Disp, UseFPOffset ? 4 : 0)
17870 .addOperand(Segment)
17871 .setMemRefs(MMOBegin, MMOEnd);
17873 // Check if there is enough room left to pull this argument.
17874 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17876 .addImm(MaxOffset + 8 - ArgSizeA8);
17878 // Branch to "overflowMBB" if offset >= max
17879 // Fall through to "offsetMBB" otherwise
17880 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17881 .addMBB(overflowMBB);
17884 // In offsetMBB, emit code to use the reg_save_area.
17886 assert(OffsetReg != 0);
17888 // Read the reg_save_area address.
17889 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17890 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17895 .addOperand(Segment)
17896 .setMemRefs(MMOBegin, MMOEnd);
17898 // Zero-extend the offset
17899 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17900 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17903 .addImm(X86::sub_32bit);
17905 // Add the offset to the reg_save_area to get the final address.
17906 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17907 .addReg(OffsetReg64)
17908 .addReg(RegSaveReg);
17910 // Compute the offset for the next argument
17911 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17912 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17914 .addImm(UseFPOffset ? 16 : 8);
17916 // Store it back into the va_list.
17917 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17921 .addDisp(Disp, UseFPOffset ? 4 : 0)
17922 .addOperand(Segment)
17923 .addReg(NextOffsetReg)
17924 .setMemRefs(MMOBegin, MMOEnd);
17927 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17932 // Emit code to use overflow area
17935 // Load the overflow_area address into a register.
17936 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17937 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17942 .addOperand(Segment)
17943 .setMemRefs(MMOBegin, MMOEnd);
17945 // If we need to align it, do so. Otherwise, just copy the address
17946 // to OverflowDestReg.
17948 // Align the overflow address
17949 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17950 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17952 // aligned_addr = (addr + (align-1)) & ~(align-1)
17953 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17954 .addReg(OverflowAddrReg)
17957 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17959 .addImm(~(uint64_t)(Align-1));
17961 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17962 .addReg(OverflowAddrReg);
17965 // Compute the next overflow address after this argument.
17966 // (the overflow address should be kept 8-byte aligned)
17967 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17968 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17969 .addReg(OverflowDestReg)
17970 .addImm(ArgSizeA8);
17972 // Store the new overflow address.
17973 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17978 .addOperand(Segment)
17979 .addReg(NextAddrReg)
17980 .setMemRefs(MMOBegin, MMOEnd);
17982 // If we branched, emit the PHI to the front of endMBB.
17984 BuildMI(*endMBB, endMBB->begin(), DL,
17985 TII->get(X86::PHI), DestReg)
17986 .addReg(OffsetDestReg).addMBB(offsetMBB)
17987 .addReg(OverflowDestReg).addMBB(overflowMBB);
17990 // Erase the pseudo instruction
17991 MI->eraseFromParent();
17996 MachineBasicBlock *
17997 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17999 MachineBasicBlock *MBB) const {
18000 // Emit code to save XMM registers to the stack. The ABI says that the
18001 // number of registers to save is given in %al, so it's theoretically
18002 // possible to do an indirect jump trick to avoid saving all of them,
18003 // however this code takes a simpler approach and just executes all
18004 // of the stores if %al is non-zero. It's less code, and it's probably
18005 // easier on the hardware branch predictor, and stores aren't all that
18006 // expensive anyway.
18008 // Create the new basic blocks. One block contains all the XMM stores,
18009 // and one block is the final destination regardless of whether any
18010 // stores were performed.
18011 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18012 MachineFunction *F = MBB->getParent();
18013 MachineFunction::iterator MBBIter = MBB;
18015 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18016 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18017 F->insert(MBBIter, XMMSaveMBB);
18018 F->insert(MBBIter, EndMBB);
18020 // Transfer the remainder of MBB and its successor edges to EndMBB.
18021 EndMBB->splice(EndMBB->begin(), MBB,
18022 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18023 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18025 // The original block will now fall through to the XMM save block.
18026 MBB->addSuccessor(XMMSaveMBB);
18027 // The XMMSaveMBB will fall through to the end block.
18028 XMMSaveMBB->addSuccessor(EndMBB);
18030 // Now add the instructions.
18031 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18032 DebugLoc DL = MI->getDebugLoc();
18034 unsigned CountReg = MI->getOperand(0).getReg();
18035 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18036 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18038 if (!Subtarget->isTargetWin64()) {
18039 // If %al is 0, branch around the XMM save block.
18040 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18041 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18042 MBB->addSuccessor(EndMBB);
18045 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18046 // that was just emitted, but clearly shouldn't be "saved".
18047 assert((MI->getNumOperands() <= 3 ||
18048 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18049 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18050 && "Expected last argument to be EFLAGS");
18051 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18052 // In the XMM save block, save all the XMM argument registers.
18053 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18054 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18055 MachineMemOperand *MMO =
18056 F->getMachineMemOperand(
18057 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18058 MachineMemOperand::MOStore,
18059 /*Size=*/16, /*Align=*/16);
18060 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18061 .addFrameIndex(RegSaveFrameIndex)
18062 .addImm(/*Scale=*/1)
18063 .addReg(/*IndexReg=*/0)
18064 .addImm(/*Disp=*/Offset)
18065 .addReg(/*Segment=*/0)
18066 .addReg(MI->getOperand(i).getReg())
18067 .addMemOperand(MMO);
18070 MI->eraseFromParent(); // The pseudo instruction is gone now.
18075 // The EFLAGS operand of SelectItr might be missing a kill marker
18076 // because there were multiple uses of EFLAGS, and ISel didn't know
18077 // which to mark. Figure out whether SelectItr should have had a
18078 // kill marker, and set it if it should. Returns the correct kill
18080 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18081 MachineBasicBlock* BB,
18082 const TargetRegisterInfo* TRI) {
18083 // Scan forward through BB for a use/def of EFLAGS.
18084 MachineBasicBlock::iterator miI(std::next(SelectItr));
18085 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18086 const MachineInstr& mi = *miI;
18087 if (mi.readsRegister(X86::EFLAGS))
18089 if (mi.definesRegister(X86::EFLAGS))
18090 break; // Should have kill-flag - update below.
18093 // If we hit the end of the block, check whether EFLAGS is live into a
18095 if (miI == BB->end()) {
18096 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18097 sEnd = BB->succ_end();
18098 sItr != sEnd; ++sItr) {
18099 MachineBasicBlock* succ = *sItr;
18100 if (succ->isLiveIn(X86::EFLAGS))
18105 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18106 // out. SelectMI should have a kill flag on EFLAGS.
18107 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18111 MachineBasicBlock *
18112 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18113 MachineBasicBlock *BB) const {
18114 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18115 DebugLoc DL = MI->getDebugLoc();
18117 // To "insert" a SELECT_CC instruction, we actually have to insert the
18118 // diamond control-flow pattern. The incoming instruction knows the
18119 // destination vreg to set, the condition code register to branch on, the
18120 // true/false values to select between, and a branch opcode to use.
18121 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18122 MachineFunction::iterator It = BB;
18128 // cmpTY ccX, r1, r2
18130 // fallthrough --> copy0MBB
18131 MachineBasicBlock *thisMBB = BB;
18132 MachineFunction *F = BB->getParent();
18133 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18134 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18135 F->insert(It, copy0MBB);
18136 F->insert(It, sinkMBB);
18138 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18139 // live into the sink and copy blocks.
18140 const TargetRegisterInfo *TRI =
18141 BB->getParent()->getSubtarget().getRegisterInfo();
18142 if (!MI->killsRegister(X86::EFLAGS) &&
18143 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18144 copy0MBB->addLiveIn(X86::EFLAGS);
18145 sinkMBB->addLiveIn(X86::EFLAGS);
18148 // Transfer the remainder of BB and its successor edges to sinkMBB.
18149 sinkMBB->splice(sinkMBB->begin(), BB,
18150 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18151 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18153 // Add the true and fallthrough blocks as its successors.
18154 BB->addSuccessor(copy0MBB);
18155 BB->addSuccessor(sinkMBB);
18157 // Create the conditional branch instruction.
18159 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18160 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18163 // %FalseValue = ...
18164 // # fallthrough to sinkMBB
18165 copy0MBB->addSuccessor(sinkMBB);
18168 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18170 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18171 TII->get(X86::PHI), MI->getOperand(0).getReg())
18172 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18173 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18175 MI->eraseFromParent(); // The pseudo instruction is gone now.
18179 MachineBasicBlock *
18180 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18181 bool Is64Bit) const {
18182 MachineFunction *MF = BB->getParent();
18183 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18184 DebugLoc DL = MI->getDebugLoc();
18185 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18187 assert(MF->shouldSplitStack());
18189 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18190 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18193 // ... [Till the alloca]
18194 // If stacklet is not large enough, jump to mallocMBB
18197 // Allocate by subtracting from RSP
18198 // Jump to continueMBB
18201 // Allocate by call to runtime
18205 // [rest of original BB]
18208 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18209 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18210 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18212 MachineRegisterInfo &MRI = MF->getRegInfo();
18213 const TargetRegisterClass *AddrRegClass =
18214 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18216 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18217 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18218 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18219 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18220 sizeVReg = MI->getOperand(1).getReg(),
18221 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18223 MachineFunction::iterator MBBIter = BB;
18226 MF->insert(MBBIter, bumpMBB);
18227 MF->insert(MBBIter, mallocMBB);
18228 MF->insert(MBBIter, continueMBB);
18230 continueMBB->splice(continueMBB->begin(), BB,
18231 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18232 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18234 // Add code to the main basic block to check if the stack limit has been hit,
18235 // and if so, jump to mallocMBB otherwise to bumpMBB.
18236 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18237 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18238 .addReg(tmpSPVReg).addReg(sizeVReg);
18239 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18240 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18241 .addReg(SPLimitVReg);
18242 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18244 // bumpMBB simply decreases the stack pointer, since we know the current
18245 // stacklet has enough space.
18246 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18247 .addReg(SPLimitVReg);
18248 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18249 .addReg(SPLimitVReg);
18250 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18252 // Calls into a routine in libgcc to allocate more space from the heap.
18253 const uint32_t *RegMask = MF->getTarget()
18254 .getSubtargetImpl()
18255 ->getRegisterInfo()
18256 ->getCallPreservedMask(CallingConv::C);
18258 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18260 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18261 .addExternalSymbol("__morestack_allocate_stack_space")
18262 .addRegMask(RegMask)
18263 .addReg(X86::RDI, RegState::Implicit)
18264 .addReg(X86::RAX, RegState::ImplicitDefine);
18266 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18268 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18269 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18270 .addExternalSymbol("__morestack_allocate_stack_space")
18271 .addRegMask(RegMask)
18272 .addReg(X86::EAX, RegState::ImplicitDefine);
18276 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18279 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18280 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18281 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18283 // Set up the CFG correctly.
18284 BB->addSuccessor(bumpMBB);
18285 BB->addSuccessor(mallocMBB);
18286 mallocMBB->addSuccessor(continueMBB);
18287 bumpMBB->addSuccessor(continueMBB);
18289 // Take care of the PHI nodes.
18290 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18291 MI->getOperand(0).getReg())
18292 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18293 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18295 // Delete the original pseudo instruction.
18296 MI->eraseFromParent();
18299 return continueMBB;
18302 MachineBasicBlock *
18303 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18304 MachineBasicBlock *BB) const {
18305 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18306 DebugLoc DL = MI->getDebugLoc();
18308 assert(!Subtarget->isTargetMacho());
18310 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18311 // non-trivial part is impdef of ESP.
18313 if (Subtarget->isTargetWin64()) {
18314 if (Subtarget->isTargetCygMing()) {
18315 // ___chkstk(Mingw64):
18316 // Clobbers R10, R11, RAX and EFLAGS.
18318 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18319 .addExternalSymbol("___chkstk")
18320 .addReg(X86::RAX, RegState::Implicit)
18321 .addReg(X86::RSP, RegState::Implicit)
18322 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18323 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18324 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18326 // __chkstk(MSVCRT): does not update stack pointer.
18327 // Clobbers R10, R11 and EFLAGS.
18328 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18329 .addExternalSymbol("__chkstk")
18330 .addReg(X86::RAX, RegState::Implicit)
18331 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18332 // RAX has the offset to be subtracted from RSP.
18333 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18338 const char *StackProbeSymbol =
18339 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18341 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18342 .addExternalSymbol(StackProbeSymbol)
18343 .addReg(X86::EAX, RegState::Implicit)
18344 .addReg(X86::ESP, RegState::Implicit)
18345 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18346 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18347 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18350 MI->eraseFromParent(); // The pseudo instruction is gone now.
18354 MachineBasicBlock *
18355 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18356 MachineBasicBlock *BB) const {
18357 // This is pretty easy. We're taking the value that we received from
18358 // our load from the relocation, sticking it in either RDI (x86-64)
18359 // or EAX and doing an indirect call. The return value will then
18360 // be in the normal return register.
18361 MachineFunction *F = BB->getParent();
18362 const X86InstrInfo *TII =
18363 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18364 DebugLoc DL = MI->getDebugLoc();
18366 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18367 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18369 // Get a register mask for the lowered call.
18370 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18371 // proper register mask.
18372 const uint32_t *RegMask = F->getTarget()
18373 .getSubtargetImpl()
18374 ->getRegisterInfo()
18375 ->getCallPreservedMask(CallingConv::C);
18376 if (Subtarget->is64Bit()) {
18377 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18378 TII->get(X86::MOV64rm), X86::RDI)
18380 .addImm(0).addReg(0)
18381 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18382 MI->getOperand(3).getTargetFlags())
18384 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18385 addDirectMem(MIB, X86::RDI);
18386 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18387 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18388 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18389 TII->get(X86::MOV32rm), X86::EAX)
18391 .addImm(0).addReg(0)
18392 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18393 MI->getOperand(3).getTargetFlags())
18395 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18396 addDirectMem(MIB, X86::EAX);
18397 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18399 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18400 TII->get(X86::MOV32rm), X86::EAX)
18401 .addReg(TII->getGlobalBaseReg(F))
18402 .addImm(0).addReg(0)
18403 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18404 MI->getOperand(3).getTargetFlags())
18406 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18407 addDirectMem(MIB, X86::EAX);
18408 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18411 MI->eraseFromParent(); // The pseudo instruction is gone now.
18415 MachineBasicBlock *
18416 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18417 MachineBasicBlock *MBB) const {
18418 DebugLoc DL = MI->getDebugLoc();
18419 MachineFunction *MF = MBB->getParent();
18420 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18421 MachineRegisterInfo &MRI = MF->getRegInfo();
18423 const BasicBlock *BB = MBB->getBasicBlock();
18424 MachineFunction::iterator I = MBB;
18427 // Memory Reference
18428 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18429 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18432 unsigned MemOpndSlot = 0;
18434 unsigned CurOp = 0;
18436 DstReg = MI->getOperand(CurOp++).getReg();
18437 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18438 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18439 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18440 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18442 MemOpndSlot = CurOp;
18444 MVT PVT = getPointerTy();
18445 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18446 "Invalid Pointer Size!");
18448 // For v = setjmp(buf), we generate
18451 // buf[LabelOffset] = restoreMBB
18452 // SjLjSetup restoreMBB
18458 // v = phi(main, restore)
18463 MachineBasicBlock *thisMBB = MBB;
18464 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18465 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18466 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18467 MF->insert(I, mainMBB);
18468 MF->insert(I, sinkMBB);
18469 MF->push_back(restoreMBB);
18471 MachineInstrBuilder MIB;
18473 // Transfer the remainder of BB and its successor edges to sinkMBB.
18474 sinkMBB->splice(sinkMBB->begin(), MBB,
18475 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18476 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18479 unsigned PtrStoreOpc = 0;
18480 unsigned LabelReg = 0;
18481 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18482 Reloc::Model RM = MF->getTarget().getRelocationModel();
18483 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18484 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18486 // Prepare IP either in reg or imm.
18487 if (!UseImmLabel) {
18488 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18489 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18490 LabelReg = MRI.createVirtualRegister(PtrRC);
18491 if (Subtarget->is64Bit()) {
18492 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18496 .addMBB(restoreMBB)
18499 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18500 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18501 .addReg(XII->getGlobalBaseReg(MF))
18504 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18508 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18510 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18511 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18512 if (i == X86::AddrDisp)
18513 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18515 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18518 MIB.addReg(LabelReg);
18520 MIB.addMBB(restoreMBB);
18521 MIB.setMemRefs(MMOBegin, MMOEnd);
18523 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18524 .addMBB(restoreMBB);
18526 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18527 MF->getSubtarget().getRegisterInfo());
18528 MIB.addRegMask(RegInfo->getNoPreservedMask());
18529 thisMBB->addSuccessor(mainMBB);
18530 thisMBB->addSuccessor(restoreMBB);
18534 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18535 mainMBB->addSuccessor(sinkMBB);
18538 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18539 TII->get(X86::PHI), DstReg)
18540 .addReg(mainDstReg).addMBB(mainMBB)
18541 .addReg(restoreDstReg).addMBB(restoreMBB);
18544 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18545 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18546 restoreMBB->addSuccessor(sinkMBB);
18548 MI->eraseFromParent();
18552 MachineBasicBlock *
18553 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18554 MachineBasicBlock *MBB) const {
18555 DebugLoc DL = MI->getDebugLoc();
18556 MachineFunction *MF = MBB->getParent();
18557 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18558 MachineRegisterInfo &MRI = MF->getRegInfo();
18560 // Memory Reference
18561 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18562 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18564 MVT PVT = getPointerTy();
18565 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18566 "Invalid Pointer Size!");
18568 const TargetRegisterClass *RC =
18569 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18570 unsigned Tmp = MRI.createVirtualRegister(RC);
18571 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18572 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18573 MF->getSubtarget().getRegisterInfo());
18574 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18575 unsigned SP = RegInfo->getStackRegister();
18577 MachineInstrBuilder MIB;
18579 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18580 const int64_t SPOffset = 2 * PVT.getStoreSize();
18582 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18583 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18586 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18587 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18588 MIB.addOperand(MI->getOperand(i));
18589 MIB.setMemRefs(MMOBegin, MMOEnd);
18591 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18592 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18593 if (i == X86::AddrDisp)
18594 MIB.addDisp(MI->getOperand(i), LabelOffset);
18596 MIB.addOperand(MI->getOperand(i));
18598 MIB.setMemRefs(MMOBegin, MMOEnd);
18600 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18601 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18602 if (i == X86::AddrDisp)
18603 MIB.addDisp(MI->getOperand(i), SPOffset);
18605 MIB.addOperand(MI->getOperand(i));
18607 MIB.setMemRefs(MMOBegin, MMOEnd);
18609 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18611 MI->eraseFromParent();
18615 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18616 // accumulator loops. Writing back to the accumulator allows the coalescer
18617 // to remove extra copies in the loop.
18618 MachineBasicBlock *
18619 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18620 MachineBasicBlock *MBB) const {
18621 MachineOperand &AddendOp = MI->getOperand(3);
18623 // Bail out early if the addend isn't a register - we can't switch these.
18624 if (!AddendOp.isReg())
18627 MachineFunction &MF = *MBB->getParent();
18628 MachineRegisterInfo &MRI = MF.getRegInfo();
18630 // Check whether the addend is defined by a PHI:
18631 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18632 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18633 if (!AddendDef.isPHI())
18636 // Look for the following pattern:
18638 // %addend = phi [%entry, 0], [%loop, %result]
18640 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18644 // %addend = phi [%entry, 0], [%loop, %result]
18646 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18648 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18649 assert(AddendDef.getOperand(i).isReg());
18650 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18651 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18652 if (&PHISrcInst == MI) {
18653 // Found a matching instruction.
18654 unsigned NewFMAOpc = 0;
18655 switch (MI->getOpcode()) {
18656 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18657 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18658 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18659 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18660 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18661 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18662 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18663 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18664 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18665 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18666 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18667 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18668 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18669 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18670 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18671 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18672 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18673 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18674 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18675 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18676 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18677 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18678 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18679 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18680 default: llvm_unreachable("Unrecognized FMA variant.");
18683 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18684 MachineInstrBuilder MIB =
18685 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18686 .addOperand(MI->getOperand(0))
18687 .addOperand(MI->getOperand(3))
18688 .addOperand(MI->getOperand(2))
18689 .addOperand(MI->getOperand(1));
18690 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18691 MI->eraseFromParent();
18698 MachineBasicBlock *
18699 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18700 MachineBasicBlock *BB) const {
18701 switch (MI->getOpcode()) {
18702 default: llvm_unreachable("Unexpected instr type to insert");
18703 case X86::TAILJMPd64:
18704 case X86::TAILJMPr64:
18705 case X86::TAILJMPm64:
18706 llvm_unreachable("TAILJMP64 would not be touched here.");
18707 case X86::TCRETURNdi64:
18708 case X86::TCRETURNri64:
18709 case X86::TCRETURNmi64:
18711 case X86::WIN_ALLOCA:
18712 return EmitLoweredWinAlloca(MI, BB);
18713 case X86::SEG_ALLOCA_32:
18714 return EmitLoweredSegAlloca(MI, BB, false);
18715 case X86::SEG_ALLOCA_64:
18716 return EmitLoweredSegAlloca(MI, BB, true);
18717 case X86::TLSCall_32:
18718 case X86::TLSCall_64:
18719 return EmitLoweredTLSCall(MI, BB);
18720 case X86::CMOV_GR8:
18721 case X86::CMOV_FR32:
18722 case X86::CMOV_FR64:
18723 case X86::CMOV_V4F32:
18724 case X86::CMOV_V2F64:
18725 case X86::CMOV_V2I64:
18726 case X86::CMOV_V8F32:
18727 case X86::CMOV_V4F64:
18728 case X86::CMOV_V4I64:
18729 case X86::CMOV_V16F32:
18730 case X86::CMOV_V8F64:
18731 case X86::CMOV_V8I64:
18732 case X86::CMOV_GR16:
18733 case X86::CMOV_GR32:
18734 case X86::CMOV_RFP32:
18735 case X86::CMOV_RFP64:
18736 case X86::CMOV_RFP80:
18737 return EmitLoweredSelect(MI, BB);
18739 case X86::FP32_TO_INT16_IN_MEM:
18740 case X86::FP32_TO_INT32_IN_MEM:
18741 case X86::FP32_TO_INT64_IN_MEM:
18742 case X86::FP64_TO_INT16_IN_MEM:
18743 case X86::FP64_TO_INT32_IN_MEM:
18744 case X86::FP64_TO_INT64_IN_MEM:
18745 case X86::FP80_TO_INT16_IN_MEM:
18746 case X86::FP80_TO_INT32_IN_MEM:
18747 case X86::FP80_TO_INT64_IN_MEM: {
18748 MachineFunction *F = BB->getParent();
18749 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18750 DebugLoc DL = MI->getDebugLoc();
18752 // Change the floating point control register to use "round towards zero"
18753 // mode when truncating to an integer value.
18754 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18755 addFrameReference(BuildMI(*BB, MI, DL,
18756 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18758 // Load the old value of the high byte of the control word...
18760 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18761 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18764 // Set the high part to be round to zero...
18765 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18768 // Reload the modified control word now...
18769 addFrameReference(BuildMI(*BB, MI, DL,
18770 TII->get(X86::FLDCW16m)), CWFrameIdx);
18772 // Restore the memory image of control word to original value
18773 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18776 // Get the X86 opcode to use.
18778 switch (MI->getOpcode()) {
18779 default: llvm_unreachable("illegal opcode!");
18780 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18781 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18782 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18783 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18784 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18785 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18786 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18787 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18788 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18792 MachineOperand &Op = MI->getOperand(0);
18794 AM.BaseType = X86AddressMode::RegBase;
18795 AM.Base.Reg = Op.getReg();
18797 AM.BaseType = X86AddressMode::FrameIndexBase;
18798 AM.Base.FrameIndex = Op.getIndex();
18800 Op = MI->getOperand(1);
18802 AM.Scale = Op.getImm();
18803 Op = MI->getOperand(2);
18805 AM.IndexReg = Op.getImm();
18806 Op = MI->getOperand(3);
18807 if (Op.isGlobal()) {
18808 AM.GV = Op.getGlobal();
18810 AM.Disp = Op.getImm();
18812 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18813 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18815 // Reload the original control word now.
18816 addFrameReference(BuildMI(*BB, MI, DL,
18817 TII->get(X86::FLDCW16m)), CWFrameIdx);
18819 MI->eraseFromParent(); // The pseudo instruction is gone now.
18822 // String/text processing lowering.
18823 case X86::PCMPISTRM128REG:
18824 case X86::VPCMPISTRM128REG:
18825 case X86::PCMPISTRM128MEM:
18826 case X86::VPCMPISTRM128MEM:
18827 case X86::PCMPESTRM128REG:
18828 case X86::VPCMPESTRM128REG:
18829 case X86::PCMPESTRM128MEM:
18830 case X86::VPCMPESTRM128MEM:
18831 assert(Subtarget->hasSSE42() &&
18832 "Target must have SSE4.2 or AVX features enabled");
18833 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18835 // String/text processing lowering.
18836 case X86::PCMPISTRIREG:
18837 case X86::VPCMPISTRIREG:
18838 case X86::PCMPISTRIMEM:
18839 case X86::VPCMPISTRIMEM:
18840 case X86::PCMPESTRIREG:
18841 case X86::VPCMPESTRIREG:
18842 case X86::PCMPESTRIMEM:
18843 case X86::VPCMPESTRIMEM:
18844 assert(Subtarget->hasSSE42() &&
18845 "Target must have SSE4.2 or AVX features enabled");
18846 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18848 // Thread synchronization.
18850 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
18855 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18857 case X86::VASTART_SAVE_XMM_REGS:
18858 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18860 case X86::VAARG_64:
18861 return EmitVAARG64WithCustomInserter(MI, BB);
18863 case X86::EH_SjLj_SetJmp32:
18864 case X86::EH_SjLj_SetJmp64:
18865 return emitEHSjLjSetJmp(MI, BB);
18867 case X86::EH_SjLj_LongJmp32:
18868 case X86::EH_SjLj_LongJmp64:
18869 return emitEHSjLjLongJmp(MI, BB);
18871 case TargetOpcode::STACKMAP:
18872 case TargetOpcode::PATCHPOINT:
18873 return emitPatchPoint(MI, BB);
18875 case X86::VFMADDPDr213r:
18876 case X86::VFMADDPSr213r:
18877 case X86::VFMADDSDr213r:
18878 case X86::VFMADDSSr213r:
18879 case X86::VFMSUBPDr213r:
18880 case X86::VFMSUBPSr213r:
18881 case X86::VFMSUBSDr213r:
18882 case X86::VFMSUBSSr213r:
18883 case X86::VFNMADDPDr213r:
18884 case X86::VFNMADDPSr213r:
18885 case X86::VFNMADDSDr213r:
18886 case X86::VFNMADDSSr213r:
18887 case X86::VFNMSUBPDr213r:
18888 case X86::VFNMSUBPSr213r:
18889 case X86::VFNMSUBSDr213r:
18890 case X86::VFNMSUBSSr213r:
18891 case X86::VFMADDPDr213rY:
18892 case X86::VFMADDPSr213rY:
18893 case X86::VFMSUBPDr213rY:
18894 case X86::VFMSUBPSr213rY:
18895 case X86::VFNMADDPDr213rY:
18896 case X86::VFNMADDPSr213rY:
18897 case X86::VFNMSUBPDr213rY:
18898 case X86::VFNMSUBPSr213rY:
18899 return emitFMA3Instr(MI, BB);
18903 //===----------------------------------------------------------------------===//
18904 // X86 Optimization Hooks
18905 //===----------------------------------------------------------------------===//
18907 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18910 const SelectionDAG &DAG,
18911 unsigned Depth) const {
18912 unsigned BitWidth = KnownZero.getBitWidth();
18913 unsigned Opc = Op.getOpcode();
18914 assert((Opc >= ISD::BUILTIN_OP_END ||
18915 Opc == ISD::INTRINSIC_WO_CHAIN ||
18916 Opc == ISD::INTRINSIC_W_CHAIN ||
18917 Opc == ISD::INTRINSIC_VOID) &&
18918 "Should use MaskedValueIsZero if you don't know whether Op"
18919 " is a target node!");
18921 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18935 // These nodes' second result is a boolean.
18936 if (Op.getResNo() == 0)
18939 case X86ISD::SETCC:
18940 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18942 case ISD::INTRINSIC_WO_CHAIN: {
18943 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18944 unsigned NumLoBits = 0;
18947 case Intrinsic::x86_sse_movmsk_ps:
18948 case Intrinsic::x86_avx_movmsk_ps_256:
18949 case Intrinsic::x86_sse2_movmsk_pd:
18950 case Intrinsic::x86_avx_movmsk_pd_256:
18951 case Intrinsic::x86_mmx_pmovmskb:
18952 case Intrinsic::x86_sse2_pmovmskb_128:
18953 case Intrinsic::x86_avx2_pmovmskb: {
18954 // High bits of movmskp{s|d}, pmovmskb are known zero.
18956 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18957 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18958 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18959 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18960 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18961 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18962 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18963 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18965 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18974 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18976 const SelectionDAG &,
18977 unsigned Depth) const {
18978 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18979 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18980 return Op.getValueType().getScalarType().getSizeInBits();
18986 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18987 /// node is a GlobalAddress + offset.
18988 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18989 const GlobalValue* &GA,
18990 int64_t &Offset) const {
18991 if (N->getOpcode() == X86ISD::Wrapper) {
18992 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18993 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18994 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18998 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19001 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19002 /// same as extracting the high 128-bit part of 256-bit vector and then
19003 /// inserting the result into the low part of a new 256-bit vector
19004 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19005 EVT VT = SVOp->getValueType(0);
19006 unsigned NumElems = VT.getVectorNumElements();
19008 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19009 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19010 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19011 SVOp->getMaskElt(j) >= 0)
19017 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19018 /// same as extracting the low 128-bit part of 256-bit vector and then
19019 /// inserting the result into the high part of a new 256-bit vector
19020 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19021 EVT VT = SVOp->getValueType(0);
19022 unsigned NumElems = VT.getVectorNumElements();
19024 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19025 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19026 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19027 SVOp->getMaskElt(j) >= 0)
19033 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19034 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19035 TargetLowering::DAGCombinerInfo &DCI,
19036 const X86Subtarget* Subtarget) {
19038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19039 SDValue V1 = SVOp->getOperand(0);
19040 SDValue V2 = SVOp->getOperand(1);
19041 EVT VT = SVOp->getValueType(0);
19042 unsigned NumElems = VT.getVectorNumElements();
19044 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19045 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19049 // V UNDEF BUILD_VECTOR UNDEF
19051 // CONCAT_VECTOR CONCAT_VECTOR
19054 // RESULT: V + zero extended
19056 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19057 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19058 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19061 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19064 // To match the shuffle mask, the first half of the mask should
19065 // be exactly the first vector, and all the rest a splat with the
19066 // first element of the second one.
19067 for (unsigned i = 0; i != NumElems/2; ++i)
19068 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19069 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19072 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19073 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19074 if (Ld->hasNUsesOfValue(1, 0)) {
19075 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19076 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19078 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19080 Ld->getPointerInfo(),
19081 Ld->getAlignment(),
19082 false/*isVolatile*/, true/*ReadMem*/,
19083 false/*WriteMem*/);
19085 // Make sure the newly-created LOAD is in the same position as Ld in
19086 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19087 // and update uses of Ld's output chain to use the TokenFactor.
19088 if (Ld->hasAnyUseOfValue(1)) {
19089 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19090 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19091 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19092 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19093 SDValue(ResNode.getNode(), 1));
19096 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19100 // Emit a zeroed vector and insert the desired subvector on its
19102 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19103 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19104 return DCI.CombineTo(N, InsV);
19107 //===--------------------------------------------------------------------===//
19108 // Combine some shuffles into subvector extracts and inserts:
19111 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19112 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19113 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19114 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19115 return DCI.CombineTo(N, InsV);
19118 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19119 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19120 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19121 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19122 return DCI.CombineTo(N, InsV);
19128 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19131 /// This is the leaf of the recursive combinine below. When we have found some
19132 /// chain of single-use x86 shuffle instructions and accumulated the combined
19133 /// shuffle mask represented by them, this will try to pattern match that mask
19134 /// into either a single instruction if there is a special purpose instruction
19135 /// for this operation, or into a PSHUFB instruction which is a fully general
19136 /// instruction but should only be used to replace chains over a certain depth.
19137 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19138 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19139 TargetLowering::DAGCombinerInfo &DCI,
19140 const X86Subtarget *Subtarget) {
19141 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19143 // Find the operand that enters the chain. Note that multiple uses are OK
19144 // here, we're not going to remove the operand we find.
19145 SDValue Input = Op.getOperand(0);
19146 while (Input.getOpcode() == ISD::BITCAST)
19147 Input = Input.getOperand(0);
19149 MVT VT = Input.getSimpleValueType();
19150 MVT RootVT = Root.getSimpleValueType();
19153 // Just remove no-op shuffle masks.
19154 if (Mask.size() == 1) {
19155 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19160 // Use the float domain if the operand type is a floating point type.
19161 bool FloatDomain = VT.isFloatingPoint();
19163 // If we don't have access to VEX encodings, the generic PSHUF instructions
19164 // are preferable to some of the specialized forms despite requiring one more
19165 // byte to encode because they can implicitly copy.
19167 // IF we *do* have VEX encodings, than we can use shorter, more specific
19168 // shuffle instructions freely as they can copy due to the extra register
19170 if (Subtarget->hasAVX()) {
19171 // We have both floating point and integer variants of shuffles that dup
19172 // either the low or high half of the vector.
19173 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19174 bool Lo = Mask.equals(0, 0);
19175 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19176 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19177 if (Depth == 1 && Root->getOpcode() == Shuffle)
19178 return false; // Nothing to do!
19179 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19180 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19181 DCI.AddToWorklist(Op.getNode());
19182 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19183 DCI.AddToWorklist(Op.getNode());
19184 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19189 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19191 // For the integer domain we have specialized instructions for duplicating
19192 // any element size from the low or high half.
19193 if (!FloatDomain &&
19194 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19195 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19196 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19197 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19198 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19200 bool Lo = Mask[0] == 0;
19201 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19202 if (Depth == 1 && Root->getOpcode() == Shuffle)
19203 return false; // Nothing to do!
19205 switch (Mask.size()) {
19206 case 4: ShuffleVT = MVT::v4i32; break;
19207 case 8: ShuffleVT = MVT::v8i16; break;
19208 case 16: ShuffleVT = MVT::v16i8; break;
19210 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19211 DCI.AddToWorklist(Op.getNode());
19212 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19213 DCI.AddToWorklist(Op.getNode());
19214 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19220 // Don't try to re-form single instruction chains under any circumstances now
19221 // that we've done encoding canonicalization for them.
19225 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19226 // can replace them with a single PSHUFB instruction profitably. Intel's
19227 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19228 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19229 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19230 SmallVector<SDValue, 16> PSHUFBMask;
19231 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19232 int Ratio = 16 / Mask.size();
19233 for (unsigned i = 0; i < 16; ++i) {
19234 int M = Mask[i / Ratio] != SM_SentinelZero
19235 ? Ratio * Mask[i / Ratio] + i % Ratio
19237 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19239 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19240 DCI.AddToWorklist(Op.getNode());
19241 SDValue PSHUFBMaskOp =
19242 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19243 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19244 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19245 DCI.AddToWorklist(Op.getNode());
19246 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19251 // Failed to find any combines.
19255 /// \brief Fully generic combining of x86 shuffle instructions.
19257 /// This should be the last combine run over the x86 shuffle instructions. Once
19258 /// they have been fully optimized, this will recursively consider all chains
19259 /// of single-use shuffle instructions, build a generic model of the cumulative
19260 /// shuffle operation, and check for simpler instructions which implement this
19261 /// operation. We use this primarily for two purposes:
19263 /// 1) Collapse generic shuffles to specialized single instructions when
19264 /// equivalent. In most cases, this is just an encoding size win, but
19265 /// sometimes we will collapse multiple generic shuffles into a single
19266 /// special-purpose shuffle.
19267 /// 2) Look for sequences of shuffle instructions with 3 or more total
19268 /// instructions, and replace them with the slightly more expensive SSSE3
19269 /// PSHUFB instruction if available. We do this as the last combining step
19270 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19271 /// a suitable short sequence of other instructions. The PHUFB will either
19272 /// use a register or have to read from memory and so is slightly (but only
19273 /// slightly) more expensive than the other shuffle instructions.
19275 /// Because this is inherently a quadratic operation (for each shuffle in
19276 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19277 /// This should never be an issue in practice as the shuffle lowering doesn't
19278 /// produce sequences of more than 8 instructions.
19280 /// FIXME: We will currently miss some cases where the redundant shuffling
19281 /// would simplify under the threshold for PSHUFB formation because of
19282 /// combine-ordering. To fix this, we should do the redundant instruction
19283 /// combining in this recursive walk.
19284 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19285 ArrayRef<int> RootMask,
19286 int Depth, bool HasPSHUFB,
19288 TargetLowering::DAGCombinerInfo &DCI,
19289 const X86Subtarget *Subtarget) {
19290 // Bound the depth of our recursive combine because this is ultimately
19291 // quadratic in nature.
19295 // Directly rip through bitcasts to find the underlying operand.
19296 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19297 Op = Op.getOperand(0);
19299 MVT VT = Op.getSimpleValueType();
19300 if (!VT.isVector())
19301 return false; // Bail if we hit a non-vector.
19302 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19303 // version should be added.
19304 if (VT.getSizeInBits() != 128)
19307 assert(Root.getSimpleValueType().isVector() &&
19308 "Shuffles operate on vector types!");
19309 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19310 "Can only combine shuffles of the same vector register size.");
19312 if (!isTargetShuffle(Op.getOpcode()))
19314 SmallVector<int, 16> OpMask;
19316 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19317 // We only can combine unary shuffles which we can decode the mask for.
19318 if (!HaveMask || !IsUnary)
19321 assert(VT.getVectorNumElements() == OpMask.size() &&
19322 "Different mask size from vector size!");
19323 assert(((RootMask.size() > OpMask.size() &&
19324 RootMask.size() % OpMask.size() == 0) ||
19325 (OpMask.size() > RootMask.size() &&
19326 OpMask.size() % RootMask.size() == 0) ||
19327 OpMask.size() == RootMask.size()) &&
19328 "The smaller number of elements must divide the larger.");
19329 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19330 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19331 assert(((RootRatio == 1 && OpRatio == 1) ||
19332 (RootRatio == 1) != (OpRatio == 1)) &&
19333 "Must not have a ratio for both incoming and op masks!");
19335 SmallVector<int, 16> Mask;
19336 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19338 // Merge this shuffle operation's mask into our accumulated mask. Note that
19339 // this shuffle's mask will be the first applied to the input, followed by the
19340 // root mask to get us all the way to the root value arrangement. The reason
19341 // for this order is that we are recursing up the operation chain.
19342 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19343 int RootIdx = i / RootRatio;
19344 if (RootMask[RootIdx] == SM_SentinelZero) {
19345 // This is a zero-ed lane, we're done.
19346 Mask.push_back(SM_SentinelZero);
19350 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19351 int OpIdx = RootMaskedIdx / OpRatio;
19352 if (OpMask[OpIdx] == SM_SentinelZero) {
19353 // The incoming lanes are zero, it doesn't matter which ones we are using.
19354 Mask.push_back(SM_SentinelZero);
19358 // Ok, we have non-zero lanes, map them through.
19359 Mask.push_back(OpMask[OpIdx] * OpRatio +
19360 RootMaskedIdx % OpRatio);
19363 // See if we can recurse into the operand to combine more things.
19364 switch (Op.getOpcode()) {
19365 case X86ISD::PSHUFB:
19367 case X86ISD::PSHUFD:
19368 case X86ISD::PSHUFHW:
19369 case X86ISD::PSHUFLW:
19370 if (Op.getOperand(0).hasOneUse() &&
19371 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19372 HasPSHUFB, DAG, DCI, Subtarget))
19376 case X86ISD::UNPCKL:
19377 case X86ISD::UNPCKH:
19378 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19379 // We can't check for single use, we have to check that this shuffle is the only user.
19380 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19381 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19382 HasPSHUFB, DAG, DCI, Subtarget))
19387 // Minor canonicalization of the accumulated shuffle mask to make it easier
19388 // to match below. All this does is detect masks with squential pairs of
19389 // elements, and shrink them to the half-width mask. It does this in a loop
19390 // so it will reduce the size of the mask to the minimal width mask which
19391 // performs an equivalent shuffle.
19392 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
19393 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
19394 Mask[i] = Mask[2 * i] / 2;
19395 Mask.resize(Mask.size() / 2);
19398 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19402 /// \brief Get the PSHUF-style mask from PSHUF node.
19404 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19405 /// PSHUF-style masks that can be reused with such instructions.
19406 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19407 SmallVector<int, 4> Mask;
19409 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19413 switch (N.getOpcode()) {
19414 case X86ISD::PSHUFD:
19416 case X86ISD::PSHUFLW:
19419 case X86ISD::PSHUFHW:
19420 Mask.erase(Mask.begin(), Mask.begin() + 4);
19421 for (int &M : Mask)
19425 llvm_unreachable("No valid shuffle instruction found!");
19429 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19431 /// We walk up the chain and look for a combinable shuffle, skipping over
19432 /// shuffles that we could hoist this shuffle's transformation past without
19433 /// altering anything.
19435 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19437 TargetLowering::DAGCombinerInfo &DCI) {
19438 assert(N.getOpcode() == X86ISD::PSHUFD &&
19439 "Called with something other than an x86 128-bit half shuffle!");
19442 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19443 // of the shuffles in the chain so that we can form a fresh chain to replace
19445 SmallVector<SDValue, 8> Chain;
19446 SDValue V = N.getOperand(0);
19447 for (; V.hasOneUse(); V = V.getOperand(0)) {
19448 switch (V.getOpcode()) {
19450 return SDValue(); // Nothing combined!
19453 // Skip bitcasts as we always know the type for the target specific
19457 case X86ISD::PSHUFD:
19458 // Found another dword shuffle.
19461 case X86ISD::PSHUFLW:
19462 // Check that the low words (being shuffled) are the identity in the
19463 // dword shuffle, and the high words are self-contained.
19464 if (Mask[0] != 0 || Mask[1] != 1 ||
19465 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19468 Chain.push_back(V);
19471 case X86ISD::PSHUFHW:
19472 // Check that the high words (being shuffled) are the identity in the
19473 // dword shuffle, and the low words are self-contained.
19474 if (Mask[2] != 2 || Mask[3] != 3 ||
19475 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19478 Chain.push_back(V);
19481 case X86ISD::UNPCKL:
19482 case X86ISD::UNPCKH:
19483 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19484 // shuffle into a preceding word shuffle.
19485 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19488 // Search for a half-shuffle which we can combine with.
19489 unsigned CombineOp =
19490 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19491 if (V.getOperand(0) != V.getOperand(1) ||
19492 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19494 Chain.push_back(V);
19495 V = V.getOperand(0);
19497 switch (V.getOpcode()) {
19499 return SDValue(); // Nothing to combine.
19501 case X86ISD::PSHUFLW:
19502 case X86ISD::PSHUFHW:
19503 if (V.getOpcode() == CombineOp)
19506 Chain.push_back(V);
19510 V = V.getOperand(0);
19514 } while (V.hasOneUse());
19517 // Break out of the loop if we break out of the switch.
19521 if (!V.hasOneUse())
19522 // We fell out of the loop without finding a viable combining instruction.
19525 // Merge this node's mask and our incoming mask.
19526 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19527 for (int &M : Mask)
19529 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19530 getV4X86ShuffleImm8ForMask(Mask, DAG));
19532 // Rebuild the chain around this new shuffle.
19533 while (!Chain.empty()) {
19534 SDValue W = Chain.pop_back_val();
19536 if (V.getValueType() != W.getOperand(0).getValueType())
19537 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19539 switch (W.getOpcode()) {
19541 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19543 case X86ISD::UNPCKL:
19544 case X86ISD::UNPCKH:
19545 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
19548 case X86ISD::PSHUFD:
19549 case X86ISD::PSHUFLW:
19550 case X86ISD::PSHUFHW:
19551 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
19555 if (V.getValueType() != N.getValueType())
19556 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
19558 // Return the new chain to replace N.
19562 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19564 /// We walk up the chain, skipping shuffles of the other half and looking
19565 /// through shuffles which switch halves trying to find a shuffle of the same
19566 /// pair of dwords.
19567 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19569 TargetLowering::DAGCombinerInfo &DCI) {
19571 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19572 "Called with something other than an x86 128-bit half shuffle!");
19574 unsigned CombineOpcode = N.getOpcode();
19576 // Walk up a single-use chain looking for a combinable shuffle.
19577 SDValue V = N.getOperand(0);
19578 for (; V.hasOneUse(); V = V.getOperand(0)) {
19579 switch (V.getOpcode()) {
19581 return false; // Nothing combined!
19584 // Skip bitcasts as we always know the type for the target specific
19588 case X86ISD::PSHUFLW:
19589 case X86ISD::PSHUFHW:
19590 if (V.getOpcode() == CombineOpcode)
19593 // Other-half shuffles are no-ops.
19596 // Break out of the loop if we break out of the switch.
19600 if (!V.hasOneUse())
19601 // We fell out of the loop without finding a viable combining instruction.
19604 // Combine away the bottom node as its shuffle will be accumulated into
19605 // a preceding shuffle.
19606 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19608 // Record the old value.
19611 // Merge this node's mask and our incoming mask (adjusted to account for all
19612 // the pshufd instructions encountered).
19613 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19614 for (int &M : Mask)
19616 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19617 getV4X86ShuffleImm8ForMask(Mask, DAG));
19619 // Check that the shuffles didn't cancel each other out. If not, we need to
19620 // combine to the new one.
19622 // Replace the combinable shuffle with the combined one, updating all users
19623 // so that we re-evaluate the chain here.
19624 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19629 /// \brief Try to combine x86 target specific shuffles.
19630 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19631 TargetLowering::DAGCombinerInfo &DCI,
19632 const X86Subtarget *Subtarget) {
19634 MVT VT = N.getSimpleValueType();
19635 SmallVector<int, 4> Mask;
19637 switch (N.getOpcode()) {
19638 case X86ISD::PSHUFD:
19639 case X86ISD::PSHUFLW:
19640 case X86ISD::PSHUFHW:
19641 Mask = getPSHUFShuffleMask(N);
19642 assert(Mask.size() == 4);
19648 // Nuke no-op shuffles that show up after combining.
19649 if (isNoopShuffleMask(Mask))
19650 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19652 // Look for simplifications involving one or two shuffle instructions.
19653 SDValue V = N.getOperand(0);
19654 switch (N.getOpcode()) {
19657 case X86ISD::PSHUFLW:
19658 case X86ISD::PSHUFHW:
19659 assert(VT == MVT::v8i16);
19662 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19663 return SDValue(); // We combined away this shuffle, so we're done.
19665 // See if this reduces to a PSHUFD which is no more expensive and can
19666 // combine with more operations.
19667 if (canWidenShuffleElements(Mask)) {
19668 int DMask[] = {-1, -1, -1, -1};
19669 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19670 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19671 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19672 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19673 DCI.AddToWorklist(V.getNode());
19674 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19675 getV4X86ShuffleImm8ForMask(DMask, DAG));
19676 DCI.AddToWorklist(V.getNode());
19677 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19680 // Look for shuffle patterns which can be implemented as a single unpack.
19681 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19682 // only works when we have a PSHUFD followed by two half-shuffles.
19683 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19684 (V.getOpcode() == X86ISD::PSHUFLW ||
19685 V.getOpcode() == X86ISD::PSHUFHW) &&
19686 V.getOpcode() != N.getOpcode() &&
19688 SDValue D = V.getOperand(0);
19689 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19690 D = D.getOperand(0);
19691 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19692 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19693 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19694 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19695 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19697 for (int i = 0; i < 4; ++i) {
19698 WordMask[i + NOffset] = Mask[i] + NOffset;
19699 WordMask[i + VOffset] = VMask[i] + VOffset;
19701 // Map the word mask through the DWord mask.
19703 for (int i = 0; i < 8; ++i)
19704 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19705 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19706 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19707 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19708 std::begin(UnpackLoMask)) ||
19709 std::equal(std::begin(MappedMask), std::end(MappedMask),
19710 std::begin(UnpackHiMask))) {
19711 // We can replace all three shuffles with an unpack.
19712 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19713 DCI.AddToWorklist(V.getNode());
19714 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19716 DL, MVT::v8i16, V, V);
19723 case X86ISD::PSHUFD:
19724 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19733 /// PerformShuffleCombine - Performs several different shuffle combines.
19734 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19735 TargetLowering::DAGCombinerInfo &DCI,
19736 const X86Subtarget *Subtarget) {
19738 SDValue N0 = N->getOperand(0);
19739 SDValue N1 = N->getOperand(1);
19740 EVT VT = N->getValueType(0);
19742 // Don't create instructions with illegal types after legalize types has run.
19743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19744 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19747 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19748 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19749 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19750 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19752 // During Type Legalization, when promoting illegal vector types,
19753 // the backend might introduce new shuffle dag nodes and bitcasts.
19755 // This code performs the following transformation:
19756 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19757 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19759 // We do this only if both the bitcast and the BINOP dag nodes have
19760 // one use. Also, perform this transformation only if the new binary
19761 // operation is legal. This is to avoid introducing dag nodes that
19762 // potentially need to be further expanded (or custom lowered) into a
19763 // less optimal sequence of dag nodes.
19764 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19765 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19766 N0.getOpcode() == ISD::BITCAST) {
19767 SDValue BC0 = N0.getOperand(0);
19768 EVT SVT = BC0.getValueType();
19769 unsigned Opcode = BC0.getOpcode();
19770 unsigned NumElts = VT.getVectorNumElements();
19772 if (BC0.hasOneUse() && SVT.isVector() &&
19773 SVT.getVectorNumElements() * 2 == NumElts &&
19774 TLI.isOperationLegal(Opcode, VT)) {
19775 bool CanFold = false;
19787 unsigned SVTNumElts = SVT.getVectorNumElements();
19788 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19789 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19790 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19791 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19792 CanFold = SVOp->getMaskElt(i) < 0;
19795 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19796 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19797 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19798 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19803 // Only handle 128 wide vector from here on.
19804 if (!VT.is128BitVector())
19807 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19808 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19809 // consecutive, non-overlapping, and in the right order.
19810 SmallVector<SDValue, 16> Elts;
19811 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19812 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19814 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19818 if (isTargetShuffle(N->getOpcode())) {
19820 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19821 if (Shuffle.getNode())
19824 // Try recursively combining arbitrary sequences of x86 shuffle
19825 // instructions into higher-order shuffles. We do this after combining
19826 // specific PSHUF instruction sequences into their minimal form so that we
19827 // can evaluate how many specialized shuffle instructions are involved in
19828 // a particular chain.
19829 SmallVector<int, 1> NonceMask; // Just a placeholder.
19830 NonceMask.push_back(0);
19831 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19832 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19834 return SDValue(); // This routine will use CombineTo to replace N.
19840 /// PerformTruncateCombine - Converts truncate operation to
19841 /// a sequence of vector shuffle operations.
19842 /// It is possible when we truncate 256-bit vector to 128-bit vector
19843 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19844 TargetLowering::DAGCombinerInfo &DCI,
19845 const X86Subtarget *Subtarget) {
19849 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19850 /// specific shuffle of a load can be folded into a single element load.
19851 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19852 /// shuffles have been customed lowered so we need to handle those here.
19853 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19854 TargetLowering::DAGCombinerInfo &DCI) {
19855 if (DCI.isBeforeLegalizeOps())
19858 SDValue InVec = N->getOperand(0);
19859 SDValue EltNo = N->getOperand(1);
19861 if (!isa<ConstantSDNode>(EltNo))
19864 EVT VT = InVec.getValueType();
19866 if (InVec.getOpcode() == ISD::BITCAST) {
19867 // Don't duplicate a load with other uses.
19868 if (!InVec.hasOneUse())
19870 EVT BCVT = InVec.getOperand(0).getValueType();
19871 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
19873 InVec = InVec.getOperand(0);
19876 if (!isTargetShuffle(InVec.getOpcode()))
19879 // Don't duplicate a load with other uses.
19880 if (!InVec.hasOneUse())
19883 SmallVector<int, 16> ShuffleMask;
19885 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
19889 // Select the input vector, guarding against out of range extract vector.
19890 unsigned NumElems = VT.getVectorNumElements();
19891 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19892 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19893 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19894 : InVec.getOperand(1);
19896 // If inputs to shuffle are the same for both ops, then allow 2 uses
19897 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19899 if (LdNode.getOpcode() == ISD::BITCAST) {
19900 // Don't duplicate a load with other uses.
19901 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19904 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19905 LdNode = LdNode.getOperand(0);
19908 if (!ISD::isNormalLoad(LdNode.getNode()))
19911 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19913 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19916 EVT EltVT = N->getValueType(0);
19917 // If there's a bitcast before the shuffle, check if the load type and
19918 // alignment is valid.
19919 unsigned Align = LN0->getAlignment();
19920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19921 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
19922 EltVT.getTypeForEVT(*DAG.getContext()));
19924 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
19927 // All checks match so transform back to vector_shuffle so that DAG combiner
19928 // can finish the job
19931 // Create shuffle node taking into account the case that its a unary shuffle
19932 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
19933 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
19934 InVec.getOperand(0), Shuffle,
19936 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
19937 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19941 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19942 /// generation and convert it from being a bunch of shuffles and extracts
19943 /// to a simple store and scalar loads to extract the elements.
19944 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19945 TargetLowering::DAGCombinerInfo &DCI) {
19946 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19947 if (NewOp.getNode())
19950 SDValue InputVector = N->getOperand(0);
19952 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19953 // from mmx to v2i32 has a single usage.
19954 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19955 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19956 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19957 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19958 N->getValueType(0),
19959 InputVector.getNode()->getOperand(0));
19961 // Only operate on vectors of 4 elements, where the alternative shuffling
19962 // gets to be more expensive.
19963 if (InputVector.getValueType() != MVT::v4i32)
19966 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19967 // single use which is a sign-extend or zero-extend, and all elements are
19969 SmallVector<SDNode *, 4> Uses;
19970 unsigned ExtractedElements = 0;
19971 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19972 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19973 if (UI.getUse().getResNo() != InputVector.getResNo())
19976 SDNode *Extract = *UI;
19977 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19980 if (Extract->getValueType(0) != MVT::i32)
19982 if (!Extract->hasOneUse())
19984 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19985 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19987 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19990 // Record which element was extracted.
19991 ExtractedElements |=
19992 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19994 Uses.push_back(Extract);
19997 // If not all the elements were used, this may not be worthwhile.
19998 if (ExtractedElements != 15)
20001 // Ok, we've now decided to do the transformation.
20002 SDLoc dl(InputVector);
20004 // Store the value to a temporary stack slot.
20005 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20006 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20007 MachinePointerInfo(), false, false, 0);
20009 // Replace each use (extract) with a load of the appropriate element.
20010 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20011 UE = Uses.end(); UI != UE; ++UI) {
20012 SDNode *Extract = *UI;
20014 // cOMpute the element's address.
20015 SDValue Idx = Extract->getOperand(1);
20017 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20018 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20020 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20022 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20023 StackPtr, OffsetVal);
20025 // Load the scalar.
20026 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20027 ScalarAddr, MachinePointerInfo(),
20028 false, false, false, 0);
20030 // Replace the exact with the load.
20031 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20034 // The replacement was made in place; don't return anything.
20038 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20039 static std::pair<unsigned, bool>
20040 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20041 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20042 if (!VT.isVector())
20043 return std::make_pair(0, false);
20045 bool NeedSplit = false;
20046 switch (VT.getSimpleVT().SimpleTy) {
20047 default: return std::make_pair(0, false);
20051 if (!Subtarget->hasAVX2())
20053 if (!Subtarget->hasAVX())
20054 return std::make_pair(0, false);
20059 if (!Subtarget->hasSSE2())
20060 return std::make_pair(0, false);
20063 // SSE2 has only a small subset of the operations.
20064 bool hasUnsigned = Subtarget->hasSSE41() ||
20065 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20066 bool hasSigned = Subtarget->hasSSE41() ||
20067 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20069 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20072 // Check for x CC y ? x : y.
20073 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20074 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20079 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20082 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20085 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20088 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20090 // Check for x CC y ? y : x -- a min/max with reversed arms.
20091 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20092 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20097 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20100 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20103 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20106 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20110 return std::make_pair(Opc, NeedSplit);
20114 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20115 const X86Subtarget *Subtarget) {
20117 SDValue Cond = N->getOperand(0);
20118 SDValue LHS = N->getOperand(1);
20119 SDValue RHS = N->getOperand(2);
20121 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20122 SDValue CondSrc = Cond->getOperand(0);
20123 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20124 Cond = CondSrc->getOperand(0);
20127 MVT VT = N->getSimpleValueType(0);
20128 MVT EltVT = VT.getVectorElementType();
20129 unsigned NumElems = VT.getVectorNumElements();
20130 // There is no blend with immediate in AVX-512.
20131 if (VT.is512BitVector())
20134 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20136 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20139 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20142 // A vselect where all conditions and data are constants can be optimized into
20143 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20144 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20145 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20148 unsigned MaskValue = 0;
20149 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20152 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20153 for (unsigned i = 0; i < NumElems; ++i) {
20154 // Be sure we emit undef where we can.
20155 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20156 ShuffleMask[i] = -1;
20158 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20161 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20164 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20166 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20167 TargetLowering::DAGCombinerInfo &DCI,
20168 const X86Subtarget *Subtarget) {
20170 SDValue Cond = N->getOperand(0);
20171 // Get the LHS/RHS of the select.
20172 SDValue LHS = N->getOperand(1);
20173 SDValue RHS = N->getOperand(2);
20174 EVT VT = LHS.getValueType();
20175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20177 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20178 // instructions match the semantics of the common C idiom x<y?x:y but not
20179 // x<=y?x:y, because of how they handle negative zero (which can be
20180 // ignored in unsafe-math mode).
20181 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20182 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20183 (Subtarget->hasSSE2() ||
20184 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20185 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20187 unsigned Opcode = 0;
20188 // Check for x CC y ? x : y.
20189 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20190 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20194 // Converting this to a min would handle NaNs incorrectly, and swapping
20195 // the operands would cause it to handle comparisons between positive
20196 // and negative zero incorrectly.
20197 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20198 if (!DAG.getTarget().Options.UnsafeFPMath &&
20199 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20201 std::swap(LHS, RHS);
20203 Opcode = X86ISD::FMIN;
20206 // Converting this to a min would handle comparisons between positive
20207 // and negative zero incorrectly.
20208 if (!DAG.getTarget().Options.UnsafeFPMath &&
20209 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20211 Opcode = X86ISD::FMIN;
20214 // Converting this to a min would handle both negative zeros and NaNs
20215 // incorrectly, but we can swap the operands to fix both.
20216 std::swap(LHS, RHS);
20220 Opcode = X86ISD::FMIN;
20224 // Converting this to a max would handle comparisons between positive
20225 // and negative zero incorrectly.
20226 if (!DAG.getTarget().Options.UnsafeFPMath &&
20227 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20229 Opcode = X86ISD::FMAX;
20232 // Converting this to a max would handle NaNs incorrectly, and swapping
20233 // the operands would cause it to handle comparisons between positive
20234 // and negative zero incorrectly.
20235 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20236 if (!DAG.getTarget().Options.UnsafeFPMath &&
20237 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20239 std::swap(LHS, RHS);
20241 Opcode = X86ISD::FMAX;
20244 // Converting this to a max would handle both negative zeros and NaNs
20245 // incorrectly, but we can swap the operands to fix both.
20246 std::swap(LHS, RHS);
20250 Opcode = X86ISD::FMAX;
20253 // Check for x CC y ? y : x -- a min/max with reversed arms.
20254 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20255 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20259 // Converting this to a min would handle comparisons between positive
20260 // and negative zero incorrectly, and swapping the operands would
20261 // cause it to handle NaNs incorrectly.
20262 if (!DAG.getTarget().Options.UnsafeFPMath &&
20263 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20264 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20266 std::swap(LHS, RHS);
20268 Opcode = X86ISD::FMIN;
20271 // Converting this to a min would handle NaNs incorrectly.
20272 if (!DAG.getTarget().Options.UnsafeFPMath &&
20273 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20275 Opcode = X86ISD::FMIN;
20278 // Converting this to a min would handle both negative zeros and NaNs
20279 // incorrectly, but we can swap the operands to fix both.
20280 std::swap(LHS, RHS);
20284 Opcode = X86ISD::FMIN;
20288 // Converting this to a max would handle NaNs incorrectly.
20289 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20291 Opcode = X86ISD::FMAX;
20294 // Converting this to a max would handle comparisons between positive
20295 // and negative zero incorrectly, and swapping the operands would
20296 // cause it to handle NaNs incorrectly.
20297 if (!DAG.getTarget().Options.UnsafeFPMath &&
20298 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20299 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20301 std::swap(LHS, RHS);
20303 Opcode = X86ISD::FMAX;
20306 // Converting this to a max would handle both negative zeros and NaNs
20307 // incorrectly, but we can swap the operands to fix both.
20308 std::swap(LHS, RHS);
20312 Opcode = X86ISD::FMAX;
20318 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20321 EVT CondVT = Cond.getValueType();
20322 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20323 CondVT.getVectorElementType() == MVT::i1) {
20324 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20325 // lowering on KNL. In this case we convert it to
20326 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20327 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20328 // Since SKX these selects have a proper lowering.
20329 EVT OpVT = LHS.getValueType();
20330 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20331 (OpVT.getVectorElementType() == MVT::i8 ||
20332 OpVT.getVectorElementType() == MVT::i16) &&
20333 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20334 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20335 DCI.AddToWorklist(Cond.getNode());
20336 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20339 // If this is a select between two integer constants, try to do some
20341 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20342 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20343 // Don't do this for crazy integer types.
20344 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20345 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20346 // so that TrueC (the true value) is larger than FalseC.
20347 bool NeedsCondInvert = false;
20349 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20350 // Efficiently invertible.
20351 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20352 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20353 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20354 NeedsCondInvert = true;
20355 std::swap(TrueC, FalseC);
20358 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20359 if (FalseC->getAPIntValue() == 0 &&
20360 TrueC->getAPIntValue().isPowerOf2()) {
20361 if (NeedsCondInvert) // Invert the condition if needed.
20362 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20363 DAG.getConstant(1, Cond.getValueType()));
20365 // Zero extend the condition if needed.
20366 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20368 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20369 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20370 DAG.getConstant(ShAmt, MVT::i8));
20373 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20374 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20375 if (NeedsCondInvert) // Invert the condition if needed.
20376 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20377 DAG.getConstant(1, Cond.getValueType()));
20379 // Zero extend the condition if needed.
20380 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20381 FalseC->getValueType(0), Cond);
20382 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20383 SDValue(FalseC, 0));
20386 // Optimize cases that will turn into an LEA instruction. This requires
20387 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20388 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20389 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20390 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20392 bool isFastMultiplier = false;
20394 switch ((unsigned char)Diff) {
20396 case 1: // result = add base, cond
20397 case 2: // result = lea base( , cond*2)
20398 case 3: // result = lea base(cond, cond*2)
20399 case 4: // result = lea base( , cond*4)
20400 case 5: // result = lea base(cond, cond*4)
20401 case 8: // result = lea base( , cond*8)
20402 case 9: // result = lea base(cond, cond*8)
20403 isFastMultiplier = true;
20408 if (isFastMultiplier) {
20409 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20410 if (NeedsCondInvert) // Invert the condition if needed.
20411 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20412 DAG.getConstant(1, Cond.getValueType()));
20414 // Zero extend the condition if needed.
20415 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20417 // Scale the condition by the difference.
20419 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20420 DAG.getConstant(Diff, Cond.getValueType()));
20422 // Add the base if non-zero.
20423 if (FalseC->getAPIntValue() != 0)
20424 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20425 SDValue(FalseC, 0));
20432 // Canonicalize max and min:
20433 // (x > y) ? x : y -> (x >= y) ? x : y
20434 // (x < y) ? x : y -> (x <= y) ? x : y
20435 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20436 // the need for an extra compare
20437 // against zero. e.g.
20438 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20440 // testl %edi, %edi
20442 // cmovgl %edi, %eax
20446 // cmovsl %eax, %edi
20447 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20448 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20449 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20450 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20455 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20456 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20457 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20458 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20463 // Early exit check
20464 if (!TLI.isTypeLegal(VT))
20467 // Match VSELECTs into subs with unsigned saturation.
20468 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20469 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20470 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20471 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20472 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20474 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20475 // left side invert the predicate to simplify logic below.
20477 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20479 CC = ISD::getSetCCInverse(CC, true);
20480 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20484 if (Other.getNode() && Other->getNumOperands() == 2 &&
20485 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20486 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20487 SDValue CondRHS = Cond->getOperand(1);
20489 // Look for a general sub with unsigned saturation first.
20490 // x >= y ? x-y : 0 --> subus x, y
20491 // x > y ? x-y : 0 --> subus x, y
20492 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20493 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20494 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20496 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20497 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20498 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20499 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20500 // If the RHS is a constant we have to reverse the const
20501 // canonicalization.
20502 // x > C-1 ? x+-C : 0 --> subus x, C
20503 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20504 CondRHSConst->getAPIntValue() ==
20505 (-OpRHSConst->getAPIntValue() - 1))
20506 return DAG.getNode(
20507 X86ISD::SUBUS, DL, VT, OpLHS,
20508 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20510 // Another special case: If C was a sign bit, the sub has been
20511 // canonicalized into a xor.
20512 // FIXME: Would it be better to use computeKnownBits to determine
20513 // whether it's safe to decanonicalize the xor?
20514 // x s< 0 ? x^C : 0 --> subus x, C
20515 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20516 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20517 OpRHSConst->getAPIntValue().isSignBit())
20518 // Note that we have to rebuild the RHS constant here to ensure we
20519 // don't rely on particular values of undef lanes.
20520 return DAG.getNode(
20521 X86ISD::SUBUS, DL, VT, OpLHS,
20522 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20527 // Try to match a min/max vector operation.
20528 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20529 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20530 unsigned Opc = ret.first;
20531 bool NeedSplit = ret.second;
20533 if (Opc && NeedSplit) {
20534 unsigned NumElems = VT.getVectorNumElements();
20535 // Extract the LHS vectors
20536 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20537 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20539 // Extract the RHS vectors
20540 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20541 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20543 // Create min/max for each subvector
20544 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20545 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20547 // Merge the result
20548 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20550 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20553 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20554 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20555 // Check if SETCC has already been promoted
20556 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20557 // Check that condition value type matches vselect operand type
20560 assert(Cond.getValueType().isVector() &&
20561 "vector select expects a vector selector!");
20563 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20564 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20566 if (!TValIsAllOnes && !FValIsAllZeros) {
20567 // Try invert the condition if true value is not all 1s and false value
20569 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20570 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20572 if (TValIsAllZeros || FValIsAllOnes) {
20573 SDValue CC = Cond.getOperand(2);
20574 ISD::CondCode NewCC =
20575 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20576 Cond.getOperand(0).getValueType().isInteger());
20577 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20578 std::swap(LHS, RHS);
20579 TValIsAllOnes = FValIsAllOnes;
20580 FValIsAllZeros = TValIsAllZeros;
20584 if (TValIsAllOnes || FValIsAllZeros) {
20587 if (TValIsAllOnes && FValIsAllZeros)
20589 else if (TValIsAllOnes)
20590 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20591 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20592 else if (FValIsAllZeros)
20593 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20594 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20596 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20600 // Try to fold this VSELECT into a MOVSS/MOVSD
20601 if (N->getOpcode() == ISD::VSELECT &&
20602 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20603 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20604 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20605 bool CanFold = false;
20606 unsigned NumElems = Cond.getNumOperands();
20610 if (isZero(Cond.getOperand(0))) {
20613 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20614 // fold (vselect <0,-1> -> (movsd A, B)
20615 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20616 CanFold = isAllOnes(Cond.getOperand(i));
20617 } else if (isAllOnes(Cond.getOperand(0))) {
20621 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20622 // fold (vselect <-1,0> -> (movsd B, A)
20623 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20624 CanFold = isZero(Cond.getOperand(i));
20628 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20629 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20630 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20633 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20634 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20635 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20636 // (v2i64 (bitcast B)))))
20638 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20639 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20640 // (v2f64 (bitcast B)))))
20642 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20643 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20644 // (v2i64 (bitcast A)))))
20646 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20647 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20648 // (v2f64 (bitcast A)))))
20650 CanFold = (isZero(Cond.getOperand(0)) &&
20651 isZero(Cond.getOperand(1)) &&
20652 isAllOnes(Cond.getOperand(2)) &&
20653 isAllOnes(Cond.getOperand(3)));
20655 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20656 isAllOnes(Cond.getOperand(1)) &&
20657 isZero(Cond.getOperand(2)) &&
20658 isZero(Cond.getOperand(3))) {
20660 std::swap(LHS, RHS);
20664 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20665 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20666 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20667 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20669 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20675 // If we know that this node is legal then we know that it is going to be
20676 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20677 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20678 // to simplify previous instructions.
20679 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20680 !DCI.isBeforeLegalize() &&
20681 // We explicitly check against v8i16 and v16i16 because, although
20682 // they're marked as Custom, they might only be legal when Cond is a
20683 // build_vector of constants. This will be taken care in a later
20685 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20686 VT != MVT::v8i16)) {
20687 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20689 // Don't optimize vector selects that map to mask-registers.
20693 // Check all uses of that condition operand to check whether it will be
20694 // consumed by non-BLEND instructions, which may depend on all bits are set
20696 for (SDNode::use_iterator I = Cond->use_begin(),
20697 E = Cond->use_end(); I != E; ++I)
20698 if (I->getOpcode() != ISD::VSELECT)
20699 // TODO: Add other opcodes eventually lowered into BLEND.
20702 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20703 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20705 APInt KnownZero, KnownOne;
20706 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20707 DCI.isBeforeLegalizeOps());
20708 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20709 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20710 DCI.CommitTargetLoweringOpt(TLO);
20713 // We should generate an X86ISD::BLENDI from a vselect if its argument
20714 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20715 // constants. This specific pattern gets generated when we split a
20716 // selector for a 512 bit vector in a machine without AVX512 (but with
20717 // 256-bit vectors), during legalization:
20719 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20721 // Iff we find this pattern and the build_vectors are built from
20722 // constants, we translate the vselect into a shuffle_vector that we
20723 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20724 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20725 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20726 if (Shuffle.getNode())
20733 // Check whether a boolean test is testing a boolean value generated by
20734 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20737 // Simplify the following patterns:
20738 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20739 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20740 // to (Op EFLAGS Cond)
20742 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20743 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20744 // to (Op EFLAGS !Cond)
20746 // where Op could be BRCOND or CMOV.
20748 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20749 // Quit if not CMP and SUB with its value result used.
20750 if (Cmp.getOpcode() != X86ISD::CMP &&
20751 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20754 // Quit if not used as a boolean value.
20755 if (CC != X86::COND_E && CC != X86::COND_NE)
20758 // Check CMP operands. One of them should be 0 or 1 and the other should be
20759 // an SetCC or extended from it.
20760 SDValue Op1 = Cmp.getOperand(0);
20761 SDValue Op2 = Cmp.getOperand(1);
20764 const ConstantSDNode* C = nullptr;
20765 bool needOppositeCond = (CC == X86::COND_E);
20766 bool checkAgainstTrue = false; // Is it a comparison against 1?
20768 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20770 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20772 else // Quit if all operands are not constants.
20775 if (C->getZExtValue() == 1) {
20776 needOppositeCond = !needOppositeCond;
20777 checkAgainstTrue = true;
20778 } else if (C->getZExtValue() != 0)
20779 // Quit if the constant is neither 0 or 1.
20782 bool truncatedToBoolWithAnd = false;
20783 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20784 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20785 SetCC.getOpcode() == ISD::TRUNCATE ||
20786 SetCC.getOpcode() == ISD::AND) {
20787 if (SetCC.getOpcode() == ISD::AND) {
20789 ConstantSDNode *CS;
20790 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20791 CS->getZExtValue() == 1)
20793 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20794 CS->getZExtValue() == 1)
20798 SetCC = SetCC.getOperand(OpIdx);
20799 truncatedToBoolWithAnd = true;
20801 SetCC = SetCC.getOperand(0);
20804 switch (SetCC.getOpcode()) {
20805 case X86ISD::SETCC_CARRY:
20806 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20807 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20808 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20809 // truncated to i1 using 'and'.
20810 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20812 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20813 "Invalid use of SETCC_CARRY!");
20815 case X86ISD::SETCC:
20816 // Set the condition code or opposite one if necessary.
20817 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20818 if (needOppositeCond)
20819 CC = X86::GetOppositeBranchCondition(CC);
20820 return SetCC.getOperand(1);
20821 case X86ISD::CMOV: {
20822 // Check whether false/true value has canonical one, i.e. 0 or 1.
20823 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20824 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20825 // Quit if true value is not a constant.
20828 // Quit if false value is not a constant.
20830 SDValue Op = SetCC.getOperand(0);
20831 // Skip 'zext' or 'trunc' node.
20832 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20833 Op.getOpcode() == ISD::TRUNCATE)
20834 Op = Op.getOperand(0);
20835 // A special case for rdrand/rdseed, where 0 is set if false cond is
20837 if ((Op.getOpcode() != X86ISD::RDRAND &&
20838 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20841 // Quit if false value is not the constant 0 or 1.
20842 bool FValIsFalse = true;
20843 if (FVal && FVal->getZExtValue() != 0) {
20844 if (FVal->getZExtValue() != 1)
20846 // If FVal is 1, opposite cond is needed.
20847 needOppositeCond = !needOppositeCond;
20848 FValIsFalse = false;
20850 // Quit if TVal is not the constant opposite of FVal.
20851 if (FValIsFalse && TVal->getZExtValue() != 1)
20853 if (!FValIsFalse && TVal->getZExtValue() != 0)
20855 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20856 if (needOppositeCond)
20857 CC = X86::GetOppositeBranchCondition(CC);
20858 return SetCC.getOperand(3);
20865 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20866 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20867 TargetLowering::DAGCombinerInfo &DCI,
20868 const X86Subtarget *Subtarget) {
20871 // If the flag operand isn't dead, don't touch this CMOV.
20872 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20875 SDValue FalseOp = N->getOperand(0);
20876 SDValue TrueOp = N->getOperand(1);
20877 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20878 SDValue Cond = N->getOperand(3);
20880 if (CC == X86::COND_E || CC == X86::COND_NE) {
20881 switch (Cond.getOpcode()) {
20885 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20886 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20887 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20893 Flags = checkBoolTestSetCCCombine(Cond, CC);
20894 if (Flags.getNode() &&
20895 // Extra check as FCMOV only supports a subset of X86 cond.
20896 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20897 SDValue Ops[] = { FalseOp, TrueOp,
20898 DAG.getConstant(CC, MVT::i8), Flags };
20899 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20902 // If this is a select between two integer constants, try to do some
20903 // optimizations. Note that the operands are ordered the opposite of SELECT
20905 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20906 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20907 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20908 // larger than FalseC (the false value).
20909 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20910 CC = X86::GetOppositeBranchCondition(CC);
20911 std::swap(TrueC, FalseC);
20912 std::swap(TrueOp, FalseOp);
20915 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20916 // This is efficient for any integer data type (including i8/i16) and
20918 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20919 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20920 DAG.getConstant(CC, MVT::i8), Cond);
20922 // Zero extend the condition if needed.
20923 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20925 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20926 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20927 DAG.getConstant(ShAmt, MVT::i8));
20928 if (N->getNumValues() == 2) // Dead flag value?
20929 return DCI.CombineTo(N, Cond, SDValue());
20933 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
20934 // for any integer data type, including i8/i16.
20935 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20936 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20937 DAG.getConstant(CC, MVT::i8), Cond);
20939 // Zero extend the condition if needed.
20940 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20941 FalseC->getValueType(0), Cond);
20942 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20943 SDValue(FalseC, 0));
20945 if (N->getNumValues() == 2) // Dead flag value?
20946 return DCI.CombineTo(N, Cond, SDValue());
20950 // Optimize cases that will turn into an LEA instruction. This requires
20951 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20952 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20953 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20954 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20956 bool isFastMultiplier = false;
20958 switch ((unsigned char)Diff) {
20960 case 1: // result = add base, cond
20961 case 2: // result = lea base( , cond*2)
20962 case 3: // result = lea base(cond, cond*2)
20963 case 4: // result = lea base( , cond*4)
20964 case 5: // result = lea base(cond, cond*4)
20965 case 8: // result = lea base( , cond*8)
20966 case 9: // result = lea base(cond, cond*8)
20967 isFastMultiplier = true;
20972 if (isFastMultiplier) {
20973 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20974 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20975 DAG.getConstant(CC, MVT::i8), Cond);
20976 // Zero extend the condition if needed.
20977 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20979 // Scale the condition by the difference.
20981 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20982 DAG.getConstant(Diff, Cond.getValueType()));
20984 // Add the base if non-zero.
20985 if (FalseC->getAPIntValue() != 0)
20986 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20987 SDValue(FalseC, 0));
20988 if (N->getNumValues() == 2) // Dead flag value?
20989 return DCI.CombineTo(N, Cond, SDValue());
20996 // Handle these cases:
20997 // (select (x != c), e, c) -> select (x != c), e, x),
20998 // (select (x == c), c, e) -> select (x == c), x, e)
20999 // where the c is an integer constant, and the "select" is the combination
21000 // of CMOV and CMP.
21002 // The rationale for this change is that the conditional-move from a constant
21003 // needs two instructions, however, conditional-move from a register needs
21004 // only one instruction.
21006 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21007 // some instruction-combining opportunities. This opt needs to be
21008 // postponed as late as possible.
21010 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21011 // the DCI.xxxx conditions are provided to postpone the optimization as
21012 // late as possible.
21014 ConstantSDNode *CmpAgainst = nullptr;
21015 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21016 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21017 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21019 if (CC == X86::COND_NE &&
21020 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21021 CC = X86::GetOppositeBranchCondition(CC);
21022 std::swap(TrueOp, FalseOp);
21025 if (CC == X86::COND_E &&
21026 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21027 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21028 DAG.getConstant(CC, MVT::i8), Cond };
21029 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21037 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21038 const X86Subtarget *Subtarget) {
21039 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21041 default: return SDValue();
21042 // SSE/AVX/AVX2 blend intrinsics.
21043 case Intrinsic::x86_avx2_pblendvb:
21044 case Intrinsic::x86_avx2_pblendw:
21045 case Intrinsic::x86_avx2_pblendd_128:
21046 case Intrinsic::x86_avx2_pblendd_256:
21047 // Don't try to simplify this intrinsic if we don't have AVX2.
21048 if (!Subtarget->hasAVX2())
21051 case Intrinsic::x86_avx_blend_pd_256:
21052 case Intrinsic::x86_avx_blend_ps_256:
21053 case Intrinsic::x86_avx_blendv_pd_256:
21054 case Intrinsic::x86_avx_blendv_ps_256:
21055 // Don't try to simplify this intrinsic if we don't have AVX.
21056 if (!Subtarget->hasAVX())
21059 case Intrinsic::x86_sse41_pblendw:
21060 case Intrinsic::x86_sse41_blendpd:
21061 case Intrinsic::x86_sse41_blendps:
21062 case Intrinsic::x86_sse41_blendvps:
21063 case Intrinsic::x86_sse41_blendvpd:
21064 case Intrinsic::x86_sse41_pblendvb: {
21065 SDValue Op0 = N->getOperand(1);
21066 SDValue Op1 = N->getOperand(2);
21067 SDValue Mask = N->getOperand(3);
21069 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21070 if (!Subtarget->hasSSE41())
21073 // fold (blend A, A, Mask) -> A
21076 // fold (blend A, B, allZeros) -> A
21077 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21079 // fold (blend A, B, allOnes) -> B
21080 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21083 // Simplify the case where the mask is a constant i32 value.
21084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21085 if (C->isNullValue())
21087 if (C->isAllOnesValue())
21094 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21095 case Intrinsic::x86_sse2_psrai_w:
21096 case Intrinsic::x86_sse2_psrai_d:
21097 case Intrinsic::x86_avx2_psrai_w:
21098 case Intrinsic::x86_avx2_psrai_d:
21099 case Intrinsic::x86_sse2_psra_w:
21100 case Intrinsic::x86_sse2_psra_d:
21101 case Intrinsic::x86_avx2_psra_w:
21102 case Intrinsic::x86_avx2_psra_d: {
21103 SDValue Op0 = N->getOperand(1);
21104 SDValue Op1 = N->getOperand(2);
21105 EVT VT = Op0.getValueType();
21106 assert(VT.isVector() && "Expected a vector type!");
21108 if (isa<BuildVectorSDNode>(Op1))
21109 Op1 = Op1.getOperand(0);
21111 if (!isa<ConstantSDNode>(Op1))
21114 EVT SVT = VT.getVectorElementType();
21115 unsigned SVTBits = SVT.getSizeInBits();
21117 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21118 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21119 uint64_t ShAmt = C.getZExtValue();
21121 // Don't try to convert this shift into a ISD::SRA if the shift
21122 // count is bigger than or equal to the element size.
21123 if (ShAmt >= SVTBits)
21126 // Trivial case: if the shift count is zero, then fold this
21127 // into the first operand.
21131 // Replace this packed shift intrinsic with a target independent
21133 SDValue Splat = DAG.getConstant(C, VT);
21134 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21139 /// PerformMulCombine - Optimize a single multiply with constant into two
21140 /// in order to implement it with two cheaper instructions, e.g.
21141 /// LEA + SHL, LEA + LEA.
21142 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21143 TargetLowering::DAGCombinerInfo &DCI) {
21144 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21147 EVT VT = N->getValueType(0);
21148 if (VT != MVT::i64)
21151 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21154 uint64_t MulAmt = C->getZExtValue();
21155 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21158 uint64_t MulAmt1 = 0;
21159 uint64_t MulAmt2 = 0;
21160 if ((MulAmt % 9) == 0) {
21162 MulAmt2 = MulAmt / 9;
21163 } else if ((MulAmt % 5) == 0) {
21165 MulAmt2 = MulAmt / 5;
21166 } else if ((MulAmt % 3) == 0) {
21168 MulAmt2 = MulAmt / 3;
21171 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21174 if (isPowerOf2_64(MulAmt2) &&
21175 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21176 // If second multiplifer is pow2, issue it first. We want the multiply by
21177 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21179 std::swap(MulAmt1, MulAmt2);
21182 if (isPowerOf2_64(MulAmt1))
21183 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21184 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21186 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21187 DAG.getConstant(MulAmt1, VT));
21189 if (isPowerOf2_64(MulAmt2))
21190 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21191 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21193 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21194 DAG.getConstant(MulAmt2, VT));
21196 // Do not add new nodes to DAG combiner worklist.
21197 DCI.CombineTo(N, NewMul, false);
21202 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21203 SDValue N0 = N->getOperand(0);
21204 SDValue N1 = N->getOperand(1);
21205 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21206 EVT VT = N0.getValueType();
21208 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21209 // since the result of setcc_c is all zero's or all ones.
21210 if (VT.isInteger() && !VT.isVector() &&
21211 N1C && N0.getOpcode() == ISD::AND &&
21212 N0.getOperand(1).getOpcode() == ISD::Constant) {
21213 SDValue N00 = N0.getOperand(0);
21214 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21215 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21216 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21217 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21218 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21219 APInt ShAmt = N1C->getAPIntValue();
21220 Mask = Mask.shl(ShAmt);
21222 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21223 N00, DAG.getConstant(Mask, VT));
21227 // Hardware support for vector shifts is sparse which makes us scalarize the
21228 // vector operations in many cases. Also, on sandybridge ADD is faster than
21230 // (shl V, 1) -> add V,V
21231 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21232 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21233 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21234 // We shift all of the values by one. In many cases we do not have
21235 // hardware support for this operation. This is better expressed as an ADD
21237 if (N1SplatC->getZExtValue() == 1)
21238 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21244 /// \brief Returns a vector of 0s if the node in input is a vector logical
21245 /// shift by a constant amount which is known to be bigger than or equal
21246 /// to the vector element size in bits.
21247 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21248 const X86Subtarget *Subtarget) {
21249 EVT VT = N->getValueType(0);
21251 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21252 (!Subtarget->hasInt256() ||
21253 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21256 SDValue Amt = N->getOperand(1);
21258 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21259 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21260 APInt ShiftAmt = AmtSplat->getAPIntValue();
21261 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21263 // SSE2/AVX2 logical shifts always return a vector of 0s
21264 // if the shift amount is bigger than or equal to
21265 // the element size. The constant shift amount will be
21266 // encoded as a 8-bit immediate.
21267 if (ShiftAmt.trunc(8).uge(MaxAmount))
21268 return getZeroVector(VT, Subtarget, DAG, DL);
21274 /// PerformShiftCombine - Combine shifts.
21275 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21276 TargetLowering::DAGCombinerInfo &DCI,
21277 const X86Subtarget *Subtarget) {
21278 if (N->getOpcode() == ISD::SHL) {
21279 SDValue V = PerformSHLCombine(N, DAG);
21280 if (V.getNode()) return V;
21283 if (N->getOpcode() != ISD::SRA) {
21284 // Try to fold this logical shift into a zero vector.
21285 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21286 if (V.getNode()) return V;
21292 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21293 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21294 // and friends. Likewise for OR -> CMPNEQSS.
21295 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21296 TargetLowering::DAGCombinerInfo &DCI,
21297 const X86Subtarget *Subtarget) {
21300 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21301 // we're requiring SSE2 for both.
21302 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21303 SDValue N0 = N->getOperand(0);
21304 SDValue N1 = N->getOperand(1);
21305 SDValue CMP0 = N0->getOperand(1);
21306 SDValue CMP1 = N1->getOperand(1);
21309 // The SETCCs should both refer to the same CMP.
21310 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21313 SDValue CMP00 = CMP0->getOperand(0);
21314 SDValue CMP01 = CMP0->getOperand(1);
21315 EVT VT = CMP00.getValueType();
21317 if (VT == MVT::f32 || VT == MVT::f64) {
21318 bool ExpectingFlags = false;
21319 // Check for any users that want flags:
21320 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21321 !ExpectingFlags && UI != UE; ++UI)
21322 switch (UI->getOpcode()) {
21327 ExpectingFlags = true;
21329 case ISD::CopyToReg:
21330 case ISD::SIGN_EXTEND:
21331 case ISD::ZERO_EXTEND:
21332 case ISD::ANY_EXTEND:
21336 if (!ExpectingFlags) {
21337 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21338 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21340 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21341 X86::CondCode tmp = cc0;
21346 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21347 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21348 // FIXME: need symbolic constants for these magic numbers.
21349 // See X86ATTInstPrinter.cpp:printSSECC().
21350 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21351 if (Subtarget->hasAVX512()) {
21352 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21353 CMP01, DAG.getConstant(x86cc, MVT::i8));
21354 if (N->getValueType(0) != MVT::i1)
21355 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21359 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21360 CMP00.getValueType(), CMP00, CMP01,
21361 DAG.getConstant(x86cc, MVT::i8));
21363 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21364 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21366 if (is64BitFP && !Subtarget->is64Bit()) {
21367 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21368 // 64-bit integer, since that's not a legal type. Since
21369 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21370 // bits, but can do this little dance to extract the lowest 32 bits
21371 // and work with those going forward.
21372 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21374 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21376 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21377 Vector32, DAG.getIntPtrConstant(0));
21381 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21382 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21383 DAG.getConstant(1, IntVT));
21384 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21385 return OneBitOfTruth;
21393 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21394 /// so it can be folded inside ANDNP.
21395 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21396 EVT VT = N->getValueType(0);
21398 // Match direct AllOnes for 128 and 256-bit vectors
21399 if (ISD::isBuildVectorAllOnes(N))
21402 // Look through a bit convert.
21403 if (N->getOpcode() == ISD::BITCAST)
21404 N = N->getOperand(0).getNode();
21406 // Sometimes the operand may come from a insert_subvector building a 256-bit
21408 if (VT.is256BitVector() &&
21409 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21410 SDValue V1 = N->getOperand(0);
21411 SDValue V2 = N->getOperand(1);
21413 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21414 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21415 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21416 ISD::isBuildVectorAllOnes(V2.getNode()))
21423 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21424 // register. In most cases we actually compare or select YMM-sized registers
21425 // and mixing the two types creates horrible code. This method optimizes
21426 // some of the transition sequences.
21427 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21428 TargetLowering::DAGCombinerInfo &DCI,
21429 const X86Subtarget *Subtarget) {
21430 EVT VT = N->getValueType(0);
21431 if (!VT.is256BitVector())
21434 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21435 N->getOpcode() == ISD::ZERO_EXTEND ||
21436 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21438 SDValue Narrow = N->getOperand(0);
21439 EVT NarrowVT = Narrow->getValueType(0);
21440 if (!NarrowVT.is128BitVector())
21443 if (Narrow->getOpcode() != ISD::XOR &&
21444 Narrow->getOpcode() != ISD::AND &&
21445 Narrow->getOpcode() != ISD::OR)
21448 SDValue N0 = Narrow->getOperand(0);
21449 SDValue N1 = Narrow->getOperand(1);
21452 // The Left side has to be a trunc.
21453 if (N0.getOpcode() != ISD::TRUNCATE)
21456 // The type of the truncated inputs.
21457 EVT WideVT = N0->getOperand(0)->getValueType(0);
21461 // The right side has to be a 'trunc' or a constant vector.
21462 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21463 ConstantSDNode *RHSConstSplat = nullptr;
21464 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21465 RHSConstSplat = RHSBV->getConstantSplatNode();
21466 if (!RHSTrunc && !RHSConstSplat)
21469 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21471 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21474 // Set N0 and N1 to hold the inputs to the new wide operation.
21475 N0 = N0->getOperand(0);
21476 if (RHSConstSplat) {
21477 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21478 SDValue(RHSConstSplat, 0));
21479 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21480 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21481 } else if (RHSTrunc) {
21482 N1 = N1->getOperand(0);
21485 // Generate the wide operation.
21486 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21487 unsigned Opcode = N->getOpcode();
21489 case ISD::ANY_EXTEND:
21491 case ISD::ZERO_EXTEND: {
21492 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21493 APInt Mask = APInt::getAllOnesValue(InBits);
21494 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21495 return DAG.getNode(ISD::AND, DL, VT,
21496 Op, DAG.getConstant(Mask, VT));
21498 case ISD::SIGN_EXTEND:
21499 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21500 Op, DAG.getValueType(NarrowVT));
21502 llvm_unreachable("Unexpected opcode");
21506 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21507 TargetLowering::DAGCombinerInfo &DCI,
21508 const X86Subtarget *Subtarget) {
21509 EVT VT = N->getValueType(0);
21510 if (DCI.isBeforeLegalizeOps())
21513 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21517 // Create BEXTR instructions
21518 // BEXTR is ((X >> imm) & (2**size-1))
21519 if (VT == MVT::i32 || VT == MVT::i64) {
21520 SDValue N0 = N->getOperand(0);
21521 SDValue N1 = N->getOperand(1);
21524 // Check for BEXTR.
21525 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21526 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21527 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21528 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21529 if (MaskNode && ShiftNode) {
21530 uint64_t Mask = MaskNode->getZExtValue();
21531 uint64_t Shift = ShiftNode->getZExtValue();
21532 if (isMask_64(Mask)) {
21533 uint64_t MaskSize = CountPopulation_64(Mask);
21534 if (Shift + MaskSize <= VT.getSizeInBits())
21535 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21536 DAG.getConstant(Shift | (MaskSize << 8), VT));
21544 // Want to form ANDNP nodes:
21545 // 1) In the hopes of then easily combining them with OR and AND nodes
21546 // to form PBLEND/PSIGN.
21547 // 2) To match ANDN packed intrinsics
21548 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21551 SDValue N0 = N->getOperand(0);
21552 SDValue N1 = N->getOperand(1);
21555 // Check LHS for vnot
21556 if (N0.getOpcode() == ISD::XOR &&
21557 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21558 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21559 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21561 // Check RHS for vnot
21562 if (N1.getOpcode() == ISD::XOR &&
21563 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21564 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21565 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21570 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21571 TargetLowering::DAGCombinerInfo &DCI,
21572 const X86Subtarget *Subtarget) {
21573 if (DCI.isBeforeLegalizeOps())
21576 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21580 SDValue N0 = N->getOperand(0);
21581 SDValue N1 = N->getOperand(1);
21582 EVT VT = N->getValueType(0);
21584 // look for psign/blend
21585 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21586 if (!Subtarget->hasSSSE3() ||
21587 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21590 // Canonicalize pandn to RHS
21591 if (N0.getOpcode() == X86ISD::ANDNP)
21593 // or (and (m, y), (pandn m, x))
21594 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21595 SDValue Mask = N1.getOperand(0);
21596 SDValue X = N1.getOperand(1);
21598 if (N0.getOperand(0) == Mask)
21599 Y = N0.getOperand(1);
21600 if (N0.getOperand(1) == Mask)
21601 Y = N0.getOperand(0);
21603 // Check to see if the mask appeared in both the AND and ANDNP and
21607 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21608 // Look through mask bitcast.
21609 if (Mask.getOpcode() == ISD::BITCAST)
21610 Mask = Mask.getOperand(0);
21611 if (X.getOpcode() == ISD::BITCAST)
21612 X = X.getOperand(0);
21613 if (Y.getOpcode() == ISD::BITCAST)
21614 Y = Y.getOperand(0);
21616 EVT MaskVT = Mask.getValueType();
21618 // Validate that the Mask operand is a vector sra node.
21619 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21620 // there is no psrai.b
21621 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21622 unsigned SraAmt = ~0;
21623 if (Mask.getOpcode() == ISD::SRA) {
21624 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21625 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21626 SraAmt = AmtConst->getZExtValue();
21627 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21628 SDValue SraC = Mask.getOperand(1);
21629 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21631 if ((SraAmt + 1) != EltBits)
21636 // Now we know we at least have a plendvb with the mask val. See if
21637 // we can form a psignb/w/d.
21638 // psign = x.type == y.type == mask.type && y = sub(0, x);
21639 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21640 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21641 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21642 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21643 "Unsupported VT for PSIGN");
21644 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21645 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21647 // PBLENDVB only available on SSE 4.1
21648 if (!Subtarget->hasSSE41())
21651 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21653 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21654 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21655 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21656 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21657 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21661 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21664 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21665 MachineFunction &MF = DAG.getMachineFunction();
21666 bool OptForSize = MF.getFunction()->getAttributes().
21667 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21669 // SHLD/SHRD instructions have lower register pressure, but on some
21670 // platforms they have higher latency than the equivalent
21671 // series of shifts/or that would otherwise be generated.
21672 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21673 // have higher latencies and we are not optimizing for size.
21674 if (!OptForSize && Subtarget->isSHLDSlow())
21677 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21679 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21681 if (!N0.hasOneUse() || !N1.hasOneUse())
21684 SDValue ShAmt0 = N0.getOperand(1);
21685 if (ShAmt0.getValueType() != MVT::i8)
21687 SDValue ShAmt1 = N1.getOperand(1);
21688 if (ShAmt1.getValueType() != MVT::i8)
21690 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21691 ShAmt0 = ShAmt0.getOperand(0);
21692 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21693 ShAmt1 = ShAmt1.getOperand(0);
21696 unsigned Opc = X86ISD::SHLD;
21697 SDValue Op0 = N0.getOperand(0);
21698 SDValue Op1 = N1.getOperand(0);
21699 if (ShAmt0.getOpcode() == ISD::SUB) {
21700 Opc = X86ISD::SHRD;
21701 std::swap(Op0, Op1);
21702 std::swap(ShAmt0, ShAmt1);
21705 unsigned Bits = VT.getSizeInBits();
21706 if (ShAmt1.getOpcode() == ISD::SUB) {
21707 SDValue Sum = ShAmt1.getOperand(0);
21708 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21709 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21710 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21711 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21712 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21713 return DAG.getNode(Opc, DL, VT,
21715 DAG.getNode(ISD::TRUNCATE, DL,
21718 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21719 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21721 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21722 return DAG.getNode(Opc, DL, VT,
21723 N0.getOperand(0), N1.getOperand(0),
21724 DAG.getNode(ISD::TRUNCATE, DL,
21731 // Generate NEG and CMOV for integer abs.
21732 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21733 EVT VT = N->getValueType(0);
21735 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21736 // 8-bit integer abs to NEG and CMOV.
21737 if (VT.isInteger() && VT.getSizeInBits() == 8)
21740 SDValue N0 = N->getOperand(0);
21741 SDValue N1 = N->getOperand(1);
21744 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21745 // and change it to SUB and CMOV.
21746 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21747 N0.getOpcode() == ISD::ADD &&
21748 N0.getOperand(1) == N1 &&
21749 N1.getOpcode() == ISD::SRA &&
21750 N1.getOperand(0) == N0.getOperand(0))
21751 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21752 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21753 // Generate SUB & CMOV.
21754 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21755 DAG.getConstant(0, VT), N0.getOperand(0));
21757 SDValue Ops[] = { N0.getOperand(0), Neg,
21758 DAG.getConstant(X86::COND_GE, MVT::i8),
21759 SDValue(Neg.getNode(), 1) };
21760 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21765 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21766 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21767 TargetLowering::DAGCombinerInfo &DCI,
21768 const X86Subtarget *Subtarget) {
21769 if (DCI.isBeforeLegalizeOps())
21772 if (Subtarget->hasCMov()) {
21773 SDValue RV = performIntegerAbsCombine(N, DAG);
21781 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21782 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21783 TargetLowering::DAGCombinerInfo &DCI,
21784 const X86Subtarget *Subtarget) {
21785 LoadSDNode *Ld = cast<LoadSDNode>(N);
21786 EVT RegVT = Ld->getValueType(0);
21787 EVT MemVT = Ld->getMemoryVT();
21789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21791 // On Sandybridge unaligned 256bit loads are inefficient.
21792 ISD::LoadExtType Ext = Ld->getExtensionType();
21793 unsigned Alignment = Ld->getAlignment();
21794 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21795 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21796 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21797 unsigned NumElems = RegVT.getVectorNumElements();
21801 SDValue Ptr = Ld->getBasePtr();
21802 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21804 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21806 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21807 Ld->getPointerInfo(), Ld->isVolatile(),
21808 Ld->isNonTemporal(), Ld->isInvariant(),
21810 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21811 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21812 Ld->getPointerInfo(), Ld->isVolatile(),
21813 Ld->isNonTemporal(), Ld->isInvariant(),
21814 std::min(16U, Alignment));
21815 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21817 Load2.getValue(1));
21819 SDValue NewVec = DAG.getUNDEF(RegVT);
21820 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21821 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21822 return DCI.CombineTo(N, NewVec, TF, true);
21828 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21829 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21830 const X86Subtarget *Subtarget) {
21831 StoreSDNode *St = cast<StoreSDNode>(N);
21832 EVT VT = St->getValue().getValueType();
21833 EVT StVT = St->getMemoryVT();
21835 SDValue StoredVal = St->getOperand(1);
21836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21838 // If we are saving a concatenation of two XMM registers, perform two stores.
21839 // On Sandy Bridge, 256-bit memory operations are executed by two
21840 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21841 // memory operation.
21842 unsigned Alignment = St->getAlignment();
21843 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21844 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21845 StVT == VT && !IsAligned) {
21846 unsigned NumElems = VT.getVectorNumElements();
21850 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21851 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21853 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21854 SDValue Ptr0 = St->getBasePtr();
21855 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21857 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21858 St->getPointerInfo(), St->isVolatile(),
21859 St->isNonTemporal(), Alignment);
21860 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21861 St->getPointerInfo(), St->isVolatile(),
21862 St->isNonTemporal(),
21863 std::min(16U, Alignment));
21864 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21867 // Optimize trunc store (of multiple scalars) to shuffle and store.
21868 // First, pack all of the elements in one place. Next, store to memory
21869 // in fewer chunks.
21870 if (St->isTruncatingStore() && VT.isVector()) {
21871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21872 unsigned NumElems = VT.getVectorNumElements();
21873 assert(StVT != VT && "Cannot truncate to the same type");
21874 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21875 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21877 // From, To sizes and ElemCount must be pow of two
21878 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21879 // We are going to use the original vector elt for storing.
21880 // Accumulated smaller vector elements must be a multiple of the store size.
21881 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21883 unsigned SizeRatio = FromSz / ToSz;
21885 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21887 // Create a type on which we perform the shuffle
21888 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21889 StVT.getScalarType(), NumElems*SizeRatio);
21891 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21893 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21894 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21895 for (unsigned i = 0; i != NumElems; ++i)
21896 ShuffleVec[i] = i * SizeRatio;
21898 // Can't shuffle using an illegal type.
21899 if (!TLI.isTypeLegal(WideVecVT))
21902 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21903 DAG.getUNDEF(WideVecVT),
21905 // At this point all of the data is stored at the bottom of the
21906 // register. We now need to save it to mem.
21908 // Find the largest store unit
21909 MVT StoreType = MVT::i8;
21910 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21911 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21912 MVT Tp = (MVT::SimpleValueType)tp;
21913 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21917 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21918 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21919 (64 <= NumElems * ToSz))
21920 StoreType = MVT::f64;
21922 // Bitcast the original vector into a vector of store-size units
21923 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21924 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21925 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21926 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21927 SmallVector<SDValue, 8> Chains;
21928 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21929 TLI.getPointerTy());
21930 SDValue Ptr = St->getBasePtr();
21932 // Perform one or more big stores into memory.
21933 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21934 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21935 StoreType, ShuffWide,
21936 DAG.getIntPtrConstant(i));
21937 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21938 St->getPointerInfo(), St->isVolatile(),
21939 St->isNonTemporal(), St->getAlignment());
21940 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21941 Chains.push_back(Ch);
21944 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21947 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21948 // the FP state in cases where an emms may be missing.
21949 // A preferable solution to the general problem is to figure out the right
21950 // places to insert EMMS. This qualifies as a quick hack.
21952 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21953 if (VT.getSizeInBits() != 64)
21956 const Function *F = DAG.getMachineFunction().getFunction();
21957 bool NoImplicitFloatOps = F->getAttributes().
21958 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21959 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21960 && Subtarget->hasSSE2();
21961 if ((VT.isVector() ||
21962 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21963 isa<LoadSDNode>(St->getValue()) &&
21964 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21965 St->getChain().hasOneUse() && !St->isVolatile()) {
21966 SDNode* LdVal = St->getValue().getNode();
21967 LoadSDNode *Ld = nullptr;
21968 int TokenFactorIndex = -1;
21969 SmallVector<SDValue, 8> Ops;
21970 SDNode* ChainVal = St->getChain().getNode();
21971 // Must be a store of a load. We currently handle two cases: the load
21972 // is a direct child, and it's under an intervening TokenFactor. It is
21973 // possible to dig deeper under nested TokenFactors.
21974 if (ChainVal == LdVal)
21975 Ld = cast<LoadSDNode>(St->getChain());
21976 else if (St->getValue().hasOneUse() &&
21977 ChainVal->getOpcode() == ISD::TokenFactor) {
21978 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21979 if (ChainVal->getOperand(i).getNode() == LdVal) {
21980 TokenFactorIndex = i;
21981 Ld = cast<LoadSDNode>(St->getValue());
21983 Ops.push_back(ChainVal->getOperand(i));
21987 if (!Ld || !ISD::isNormalLoad(Ld))
21990 // If this is not the MMX case, i.e. we are just turning i64 load/store
21991 // into f64 load/store, avoid the transformation if there are multiple
21992 // uses of the loaded value.
21993 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21998 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21999 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22001 if (Subtarget->is64Bit() || F64IsLegal) {
22002 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22003 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22004 Ld->getPointerInfo(), Ld->isVolatile(),
22005 Ld->isNonTemporal(), Ld->isInvariant(),
22006 Ld->getAlignment());
22007 SDValue NewChain = NewLd.getValue(1);
22008 if (TokenFactorIndex != -1) {
22009 Ops.push_back(NewChain);
22010 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22012 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22013 St->getPointerInfo(),
22014 St->isVolatile(), St->isNonTemporal(),
22015 St->getAlignment());
22018 // Otherwise, lower to two pairs of 32-bit loads / stores.
22019 SDValue LoAddr = Ld->getBasePtr();
22020 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22021 DAG.getConstant(4, MVT::i32));
22023 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22024 Ld->getPointerInfo(),
22025 Ld->isVolatile(), Ld->isNonTemporal(),
22026 Ld->isInvariant(), Ld->getAlignment());
22027 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22028 Ld->getPointerInfo().getWithOffset(4),
22029 Ld->isVolatile(), Ld->isNonTemporal(),
22031 MinAlign(Ld->getAlignment(), 4));
22033 SDValue NewChain = LoLd.getValue(1);
22034 if (TokenFactorIndex != -1) {
22035 Ops.push_back(LoLd);
22036 Ops.push_back(HiLd);
22037 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22040 LoAddr = St->getBasePtr();
22041 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22042 DAG.getConstant(4, MVT::i32));
22044 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22045 St->getPointerInfo(),
22046 St->isVolatile(), St->isNonTemporal(),
22047 St->getAlignment());
22048 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22049 St->getPointerInfo().getWithOffset(4),
22051 St->isNonTemporal(),
22052 MinAlign(St->getAlignment(), 4));
22053 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22058 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22059 /// and return the operands for the horizontal operation in LHS and RHS. A
22060 /// horizontal operation performs the binary operation on successive elements
22061 /// of its first operand, then on successive elements of its second operand,
22062 /// returning the resulting values in a vector. For example, if
22063 /// A = < float a0, float a1, float a2, float a3 >
22065 /// B = < float b0, float b1, float b2, float b3 >
22066 /// then the result of doing a horizontal operation on A and B is
22067 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22068 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22069 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22070 /// set to A, RHS to B, and the routine returns 'true'.
22071 /// Note that the binary operation should have the property that if one of the
22072 /// operands is UNDEF then the result is UNDEF.
22073 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22074 // Look for the following pattern: if
22075 // A = < float a0, float a1, float a2, float a3 >
22076 // B = < float b0, float b1, float b2, float b3 >
22078 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22079 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22080 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22081 // which is A horizontal-op B.
22083 // At least one of the operands should be a vector shuffle.
22084 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22085 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22088 MVT VT = LHS.getSimpleValueType();
22090 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22091 "Unsupported vector type for horizontal add/sub");
22093 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22094 // operate independently on 128-bit lanes.
22095 unsigned NumElts = VT.getVectorNumElements();
22096 unsigned NumLanes = VT.getSizeInBits()/128;
22097 unsigned NumLaneElts = NumElts / NumLanes;
22098 assert((NumLaneElts % 2 == 0) &&
22099 "Vector type should have an even number of elements in each lane");
22100 unsigned HalfLaneElts = NumLaneElts/2;
22102 // View LHS in the form
22103 // LHS = VECTOR_SHUFFLE A, B, LMask
22104 // If LHS is not a shuffle then pretend it is the shuffle
22105 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22106 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22109 SmallVector<int, 16> LMask(NumElts);
22110 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22111 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22112 A = LHS.getOperand(0);
22113 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22114 B = LHS.getOperand(1);
22115 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22116 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22118 if (LHS.getOpcode() != ISD::UNDEF)
22120 for (unsigned i = 0; i != NumElts; ++i)
22124 // Likewise, view RHS in the form
22125 // RHS = VECTOR_SHUFFLE C, D, RMask
22127 SmallVector<int, 16> RMask(NumElts);
22128 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22129 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22130 C = RHS.getOperand(0);
22131 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22132 D = RHS.getOperand(1);
22133 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22134 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22136 if (RHS.getOpcode() != ISD::UNDEF)
22138 for (unsigned i = 0; i != NumElts; ++i)
22142 // Check that the shuffles are both shuffling the same vectors.
22143 if (!(A == C && B == D) && !(A == D && B == C))
22146 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22147 if (!A.getNode() && !B.getNode())
22150 // If A and B occur in reverse order in RHS, then "swap" them (which means
22151 // rewriting the mask).
22153 CommuteVectorShuffleMask(RMask, NumElts);
22155 // At this point LHS and RHS are equivalent to
22156 // LHS = VECTOR_SHUFFLE A, B, LMask
22157 // RHS = VECTOR_SHUFFLE A, B, RMask
22158 // Check that the masks correspond to performing a horizontal operation.
22159 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22160 for (unsigned i = 0; i != NumLaneElts; ++i) {
22161 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22163 // Ignore any UNDEF components.
22164 if (LIdx < 0 || RIdx < 0 ||
22165 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22166 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22169 // Check that successive elements are being operated on. If not, this is
22170 // not a horizontal operation.
22171 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22172 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22173 if (!(LIdx == Index && RIdx == Index + 1) &&
22174 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22179 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22180 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22184 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22185 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22186 const X86Subtarget *Subtarget) {
22187 EVT VT = N->getValueType(0);
22188 SDValue LHS = N->getOperand(0);
22189 SDValue RHS = N->getOperand(1);
22191 // Try to synthesize horizontal adds from adds of shuffles.
22192 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22193 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22194 isHorizontalBinOp(LHS, RHS, true))
22195 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22199 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22200 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22201 const X86Subtarget *Subtarget) {
22202 EVT VT = N->getValueType(0);
22203 SDValue LHS = N->getOperand(0);
22204 SDValue RHS = N->getOperand(1);
22206 // Try to synthesize horizontal subs from subs of shuffles.
22207 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22208 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22209 isHorizontalBinOp(LHS, RHS, false))
22210 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22214 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22215 /// X86ISD::FXOR nodes.
22216 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22217 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22218 // F[X]OR(0.0, x) -> x
22219 // F[X]OR(x, 0.0) -> x
22220 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22221 if (C->getValueAPF().isPosZero())
22222 return N->getOperand(1);
22223 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22224 if (C->getValueAPF().isPosZero())
22225 return N->getOperand(0);
22229 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22230 /// X86ISD::FMAX nodes.
22231 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22232 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22234 // Only perform optimizations if UnsafeMath is used.
22235 if (!DAG.getTarget().Options.UnsafeFPMath)
22238 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22239 // into FMINC and FMAXC, which are Commutative operations.
22240 unsigned NewOp = 0;
22241 switch (N->getOpcode()) {
22242 default: llvm_unreachable("unknown opcode");
22243 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22244 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22247 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22248 N->getOperand(0), N->getOperand(1));
22251 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22252 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22253 // FAND(0.0, x) -> 0.0
22254 // FAND(x, 0.0) -> 0.0
22255 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22256 if (C->getValueAPF().isPosZero())
22257 return N->getOperand(0);
22258 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22259 if (C->getValueAPF().isPosZero())
22260 return N->getOperand(1);
22264 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22265 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22266 // FANDN(x, 0.0) -> 0.0
22267 // FANDN(0.0, x) -> x
22268 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22269 if (C->getValueAPF().isPosZero())
22270 return N->getOperand(1);
22271 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22272 if (C->getValueAPF().isPosZero())
22273 return N->getOperand(1);
22277 static SDValue PerformBTCombine(SDNode *N,
22279 TargetLowering::DAGCombinerInfo &DCI) {
22280 // BT ignores high bits in the bit index operand.
22281 SDValue Op1 = N->getOperand(1);
22282 if (Op1.hasOneUse()) {
22283 unsigned BitWidth = Op1.getValueSizeInBits();
22284 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22285 APInt KnownZero, KnownOne;
22286 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22287 !DCI.isBeforeLegalizeOps());
22288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22289 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22290 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22291 DCI.CommitTargetLoweringOpt(TLO);
22296 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22297 SDValue Op = N->getOperand(0);
22298 if (Op.getOpcode() == ISD::BITCAST)
22299 Op = Op.getOperand(0);
22300 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22301 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22302 VT.getVectorElementType().getSizeInBits() ==
22303 OpVT.getVectorElementType().getSizeInBits()) {
22304 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22309 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22310 const X86Subtarget *Subtarget) {
22311 EVT VT = N->getValueType(0);
22312 if (!VT.isVector())
22315 SDValue N0 = N->getOperand(0);
22316 SDValue N1 = N->getOperand(1);
22317 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22320 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22321 // both SSE and AVX2 since there is no sign-extended shift right
22322 // operation on a vector with 64-bit elements.
22323 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22324 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22325 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22326 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22327 SDValue N00 = N0.getOperand(0);
22329 // EXTLOAD has a better solution on AVX2,
22330 // it may be replaced with X86ISD::VSEXT node.
22331 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22332 if (!ISD::isNormalLoad(N00.getNode()))
22335 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22336 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22338 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22344 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22345 TargetLowering::DAGCombinerInfo &DCI,
22346 const X86Subtarget *Subtarget) {
22347 if (!DCI.isBeforeLegalizeOps())
22350 if (!Subtarget->hasFp256())
22353 EVT VT = N->getValueType(0);
22354 if (VT.isVector() && VT.getSizeInBits() == 256) {
22355 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22363 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22364 const X86Subtarget* Subtarget) {
22366 EVT VT = N->getValueType(0);
22368 // Let legalize expand this if it isn't a legal type yet.
22369 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22372 EVT ScalarVT = VT.getScalarType();
22373 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22374 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22377 SDValue A = N->getOperand(0);
22378 SDValue B = N->getOperand(1);
22379 SDValue C = N->getOperand(2);
22381 bool NegA = (A.getOpcode() == ISD::FNEG);
22382 bool NegB = (B.getOpcode() == ISD::FNEG);
22383 bool NegC = (C.getOpcode() == ISD::FNEG);
22385 // Negative multiplication when NegA xor NegB
22386 bool NegMul = (NegA != NegB);
22388 A = A.getOperand(0);
22390 B = B.getOperand(0);
22392 C = C.getOperand(0);
22396 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22398 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22400 return DAG.getNode(Opcode, dl, VT, A, B, C);
22403 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22404 TargetLowering::DAGCombinerInfo &DCI,
22405 const X86Subtarget *Subtarget) {
22406 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22407 // (and (i32 x86isd::setcc_carry), 1)
22408 // This eliminates the zext. This transformation is necessary because
22409 // ISD::SETCC is always legalized to i8.
22411 SDValue N0 = N->getOperand(0);
22412 EVT VT = N->getValueType(0);
22414 if (N0.getOpcode() == ISD::AND &&
22416 N0.getOperand(0).hasOneUse()) {
22417 SDValue N00 = N0.getOperand(0);
22418 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22420 if (!C || C->getZExtValue() != 1)
22422 return DAG.getNode(ISD::AND, dl, VT,
22423 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22424 N00.getOperand(0), N00.getOperand(1)),
22425 DAG.getConstant(1, VT));
22429 if (N0.getOpcode() == ISD::TRUNCATE &&
22431 N0.getOperand(0).hasOneUse()) {
22432 SDValue N00 = N0.getOperand(0);
22433 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22434 return DAG.getNode(ISD::AND, dl, VT,
22435 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22436 N00.getOperand(0), N00.getOperand(1)),
22437 DAG.getConstant(1, VT));
22440 if (VT.is256BitVector()) {
22441 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22449 // Optimize x == -y --> x+y == 0
22450 // x != -y --> x+y != 0
22451 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22452 const X86Subtarget* Subtarget) {
22453 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22454 SDValue LHS = N->getOperand(0);
22455 SDValue RHS = N->getOperand(1);
22456 EVT VT = N->getValueType(0);
22459 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22461 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22462 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22463 LHS.getValueType(), RHS, LHS.getOperand(1));
22464 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22465 addV, DAG.getConstant(0, addV.getValueType()), CC);
22467 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22468 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22469 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22470 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22471 RHS.getValueType(), LHS, RHS.getOperand(1));
22472 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22473 addV, DAG.getConstant(0, addV.getValueType()), CC);
22476 if (VT.getScalarType() == MVT::i1) {
22477 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22478 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22479 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22480 if (!IsSEXT0 && !IsVZero0)
22482 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22483 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22484 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22486 if (!IsSEXT1 && !IsVZero1)
22489 if (IsSEXT0 && IsVZero1) {
22490 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22491 if (CC == ISD::SETEQ)
22492 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22493 return LHS.getOperand(0);
22495 if (IsSEXT1 && IsVZero0) {
22496 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22497 if (CC == ISD::SETEQ)
22498 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22499 return RHS.getOperand(0);
22506 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22507 const X86Subtarget *Subtarget) {
22509 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22510 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22511 "X86insertps is only defined for v4x32");
22513 SDValue Ld = N->getOperand(1);
22514 if (MayFoldLoad(Ld)) {
22515 // Extract the countS bits from the immediate so we can get the proper
22516 // address when narrowing the vector load to a specific element.
22517 // When the second source op is a memory address, interps doesn't use
22518 // countS and just gets an f32 from that address.
22519 unsigned DestIndex =
22520 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22521 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22525 // Create this as a scalar to vector to match the instruction pattern.
22526 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22527 // countS bits are ignored when loading from memory on insertps, which
22528 // means we don't need to explicitly set them to 0.
22529 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22530 LoadScalarToVector, N->getOperand(2));
22533 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22534 // as "sbb reg,reg", since it can be extended without zext and produces
22535 // an all-ones bit which is more useful than 0/1 in some cases.
22536 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22539 return DAG.getNode(ISD::AND, DL, VT,
22540 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22541 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22542 DAG.getConstant(1, VT));
22543 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22544 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22545 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22546 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22549 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22550 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22551 TargetLowering::DAGCombinerInfo &DCI,
22552 const X86Subtarget *Subtarget) {
22554 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22555 SDValue EFLAGS = N->getOperand(1);
22557 if (CC == X86::COND_A) {
22558 // Try to convert COND_A into COND_B in an attempt to facilitate
22559 // materializing "setb reg".
22561 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22562 // cannot take an immediate as its first operand.
22564 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22565 EFLAGS.getValueType().isInteger() &&
22566 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22567 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22568 EFLAGS.getNode()->getVTList(),
22569 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22570 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22571 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22575 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22576 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22578 if (CC == X86::COND_B)
22579 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22583 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22584 if (Flags.getNode()) {
22585 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22586 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22592 // Optimize branch condition evaluation.
22594 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22595 TargetLowering::DAGCombinerInfo &DCI,
22596 const X86Subtarget *Subtarget) {
22598 SDValue Chain = N->getOperand(0);
22599 SDValue Dest = N->getOperand(1);
22600 SDValue EFLAGS = N->getOperand(3);
22601 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22605 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22606 if (Flags.getNode()) {
22607 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22608 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22615 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22616 SelectionDAG &DAG) {
22617 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22618 // optimize away operation when it's from a constant.
22620 // The general transformation is:
22621 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22622 // AND(VECTOR_CMP(x,y), constant2)
22623 // constant2 = UNARYOP(constant)
22625 // Early exit if this isn't a vector operation, the operand of the
22626 // unary operation isn't a bitwise AND, or if the sizes of the operations
22627 // aren't the same.
22628 EVT VT = N->getValueType(0);
22629 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22630 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22631 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22634 // Now check that the other operand of the AND is a constant. We could
22635 // make the transformation for non-constant splats as well, but it's unclear
22636 // that would be a benefit as it would not eliminate any operations, just
22637 // perform one more step in scalar code before moving to the vector unit.
22638 if (BuildVectorSDNode *BV =
22639 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22640 // Bail out if the vector isn't a constant.
22641 if (!BV->isConstant())
22644 // Everything checks out. Build up the new and improved node.
22646 EVT IntVT = BV->getValueType(0);
22647 // Create a new constant of the appropriate type for the transformed
22649 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22650 // The AND node needs bitcasts to/from an integer vector type around it.
22651 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22652 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22653 N->getOperand(0)->getOperand(0), MaskConst);
22654 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22661 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22662 const X86TargetLowering *XTLI) {
22663 // First try to optimize away the conversion entirely when it's
22664 // conditionally from a constant. Vectors only.
22665 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22666 if (Res != SDValue())
22669 // Now move on to more general possibilities.
22670 SDValue Op0 = N->getOperand(0);
22671 EVT InVT = Op0->getValueType(0);
22673 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22674 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22676 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22677 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22678 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22681 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22682 // a 32-bit target where SSE doesn't support i64->FP operations.
22683 if (Op0.getOpcode() == ISD::LOAD) {
22684 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22685 EVT VT = Ld->getValueType(0);
22686 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22687 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22688 !XTLI->getSubtarget()->is64Bit() &&
22690 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22691 Ld->getChain(), Op0, DAG);
22692 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22699 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22700 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22701 X86TargetLowering::DAGCombinerInfo &DCI) {
22702 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22703 // the result is either zero or one (depending on the input carry bit).
22704 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22705 if (X86::isZeroNode(N->getOperand(0)) &&
22706 X86::isZeroNode(N->getOperand(1)) &&
22707 // We don't have a good way to replace an EFLAGS use, so only do this when
22709 SDValue(N, 1).use_empty()) {
22711 EVT VT = N->getValueType(0);
22712 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22713 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22714 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22715 DAG.getConstant(X86::COND_B,MVT::i8),
22717 DAG.getConstant(1, VT));
22718 return DCI.CombineTo(N, Res1, CarryOut);
22724 // fold (add Y, (sete X, 0)) -> adc 0, Y
22725 // (add Y, (setne X, 0)) -> sbb -1, Y
22726 // (sub (sete X, 0), Y) -> sbb 0, Y
22727 // (sub (setne X, 0), Y) -> adc -1, Y
22728 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22731 // Look through ZExts.
22732 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22733 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22736 SDValue SetCC = Ext.getOperand(0);
22737 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22740 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22741 if (CC != X86::COND_E && CC != X86::COND_NE)
22744 SDValue Cmp = SetCC.getOperand(1);
22745 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22746 !X86::isZeroNode(Cmp.getOperand(1)) ||
22747 !Cmp.getOperand(0).getValueType().isInteger())
22750 SDValue CmpOp0 = Cmp.getOperand(0);
22751 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22752 DAG.getConstant(1, CmpOp0.getValueType()));
22754 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22755 if (CC == X86::COND_NE)
22756 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22757 DL, OtherVal.getValueType(), OtherVal,
22758 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22759 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22760 DL, OtherVal.getValueType(), OtherVal,
22761 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22764 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22765 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22766 const X86Subtarget *Subtarget) {
22767 EVT VT = N->getValueType(0);
22768 SDValue Op0 = N->getOperand(0);
22769 SDValue Op1 = N->getOperand(1);
22771 // Try to synthesize horizontal adds from adds of shuffles.
22772 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22773 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22774 isHorizontalBinOp(Op0, Op1, true))
22775 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22777 return OptimizeConditionalInDecrement(N, DAG);
22780 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22781 const X86Subtarget *Subtarget) {
22782 SDValue Op0 = N->getOperand(0);
22783 SDValue Op1 = N->getOperand(1);
22785 // X86 can't encode an immediate LHS of a sub. See if we can push the
22786 // negation into a preceding instruction.
22787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22788 // If the RHS of the sub is a XOR with one use and a constant, invert the
22789 // immediate. Then add one to the LHS of the sub so we can turn
22790 // X-Y -> X+~Y+1, saving one register.
22791 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22792 isa<ConstantSDNode>(Op1.getOperand(1))) {
22793 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22794 EVT VT = Op0.getValueType();
22795 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22797 DAG.getConstant(~XorC, VT));
22798 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22799 DAG.getConstant(C->getAPIntValue()+1, VT));
22803 // Try to synthesize horizontal adds from adds of shuffles.
22804 EVT VT = N->getValueType(0);
22805 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22806 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22807 isHorizontalBinOp(Op0, Op1, true))
22808 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22810 return OptimizeConditionalInDecrement(N, DAG);
22813 /// performVZEXTCombine - Performs build vector combines
22814 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22815 TargetLowering::DAGCombinerInfo &DCI,
22816 const X86Subtarget *Subtarget) {
22817 // (vzext (bitcast (vzext (x)) -> (vzext x)
22818 SDValue In = N->getOperand(0);
22819 while (In.getOpcode() == ISD::BITCAST)
22820 In = In.getOperand(0);
22822 if (In.getOpcode() != X86ISD::VZEXT)
22825 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22829 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22830 DAGCombinerInfo &DCI) const {
22831 SelectionDAG &DAG = DCI.DAG;
22832 switch (N->getOpcode()) {
22834 case ISD::EXTRACT_VECTOR_ELT:
22835 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22837 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22838 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22839 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22840 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22841 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22842 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22845 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22846 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22847 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22848 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22849 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22850 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22851 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22852 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22853 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22855 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22857 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22858 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22859 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22860 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22861 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22862 case ISD::ANY_EXTEND:
22863 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22864 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22865 case ISD::SIGN_EXTEND_INREG:
22866 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22867 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22868 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22869 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22870 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22871 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22872 case X86ISD::SHUFP: // Handle all target specific shuffles
22873 case X86ISD::PALIGNR:
22874 case X86ISD::UNPCKH:
22875 case X86ISD::UNPCKL:
22876 case X86ISD::MOVHLPS:
22877 case X86ISD::MOVLHPS:
22878 case X86ISD::PSHUFB:
22879 case X86ISD::PSHUFD:
22880 case X86ISD::PSHUFHW:
22881 case X86ISD::PSHUFLW:
22882 case X86ISD::MOVSS:
22883 case X86ISD::MOVSD:
22884 case X86ISD::VPERMILP:
22885 case X86ISD::VPERM2X128:
22886 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22887 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22888 case ISD::INTRINSIC_WO_CHAIN:
22889 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22890 case X86ISD::INSERTPS:
22891 return PerformINSERTPSCombine(N, DAG, Subtarget);
22892 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22898 /// isTypeDesirableForOp - Return true if the target has native support for
22899 /// the specified value type and it is 'desirable' to use the type for the
22900 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22901 /// instruction encodings are longer and some i16 instructions are slow.
22902 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22903 if (!isTypeLegal(VT))
22905 if (VT != MVT::i16)
22912 case ISD::SIGN_EXTEND:
22913 case ISD::ZERO_EXTEND:
22914 case ISD::ANY_EXTEND:
22927 /// IsDesirableToPromoteOp - This method query the target whether it is
22928 /// beneficial for dag combiner to promote the specified node. If true, it
22929 /// should return the desired promotion type by reference.
22930 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22931 EVT VT = Op.getValueType();
22932 if (VT != MVT::i16)
22935 bool Promote = false;
22936 bool Commute = false;
22937 switch (Op.getOpcode()) {
22940 LoadSDNode *LD = cast<LoadSDNode>(Op);
22941 // If the non-extending load has a single use and it's not live out, then it
22942 // might be folded.
22943 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22944 Op.hasOneUse()*/) {
22945 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22946 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22947 // The only case where we'd want to promote LOAD (rather then it being
22948 // promoted as an operand is when it's only use is liveout.
22949 if (UI->getOpcode() != ISD::CopyToReg)
22956 case ISD::SIGN_EXTEND:
22957 case ISD::ZERO_EXTEND:
22958 case ISD::ANY_EXTEND:
22963 SDValue N0 = Op.getOperand(0);
22964 // Look out for (store (shl (load), x)).
22965 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22978 SDValue N0 = Op.getOperand(0);
22979 SDValue N1 = Op.getOperand(1);
22980 if (!Commute && MayFoldLoad(N1))
22982 // Avoid disabling potential load folding opportunities.
22983 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22985 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22995 //===----------------------------------------------------------------------===//
22996 // X86 Inline Assembly Support
22997 //===----------------------------------------------------------------------===//
23000 // Helper to match a string separated by whitespace.
23001 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23002 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23004 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23005 StringRef piece(*args[i]);
23006 if (!s.startswith(piece)) // Check if the piece matches.
23009 s = s.substr(piece.size());
23010 StringRef::size_type pos = s.find_first_not_of(" \t");
23011 if (pos == 0) // We matched a prefix.
23019 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23022 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23024 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23025 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23026 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23027 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23029 if (AsmPieces.size() == 3)
23031 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23038 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23039 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23041 std::string AsmStr = IA->getAsmString();
23043 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23044 if (!Ty || Ty->getBitWidth() % 16 != 0)
23047 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23048 SmallVector<StringRef, 4> AsmPieces;
23049 SplitString(AsmStr, AsmPieces, ";\n");
23051 switch (AsmPieces.size()) {
23052 default: return false;
23054 // FIXME: this should verify that we are targeting a 486 or better. If not,
23055 // we will turn this bswap into something that will be lowered to logical
23056 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23057 // lower so don't worry about this.
23059 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23060 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23061 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23062 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23063 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23064 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23065 // No need to check constraints, nothing other than the equivalent of
23066 // "=r,0" would be valid here.
23067 return IntrinsicLowering::LowerToByteSwap(CI);
23070 // rorw $$8, ${0:w} --> llvm.bswap.i16
23071 if (CI->getType()->isIntegerTy(16) &&
23072 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23073 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23074 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23076 const std::string &ConstraintsStr = IA->getConstraintString();
23077 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23078 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23079 if (clobbersFlagRegisters(AsmPieces))
23080 return IntrinsicLowering::LowerToByteSwap(CI);
23084 if (CI->getType()->isIntegerTy(32) &&
23085 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23086 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23087 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23088 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23090 const std::string &ConstraintsStr = IA->getConstraintString();
23091 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23092 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23093 if (clobbersFlagRegisters(AsmPieces))
23094 return IntrinsicLowering::LowerToByteSwap(CI);
23097 if (CI->getType()->isIntegerTy(64)) {
23098 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23099 if (Constraints.size() >= 2 &&
23100 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23101 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23102 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23103 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23104 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23105 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23106 return IntrinsicLowering::LowerToByteSwap(CI);
23114 /// getConstraintType - Given a constraint letter, return the type of
23115 /// constraint it is for this target.
23116 X86TargetLowering::ConstraintType
23117 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23118 if (Constraint.size() == 1) {
23119 switch (Constraint[0]) {
23130 return C_RegisterClass;
23154 return TargetLowering::getConstraintType(Constraint);
23157 /// Examine constraint type and operand type and determine a weight value.
23158 /// This object must already have been set up with the operand type
23159 /// and the current alternative constraint selected.
23160 TargetLowering::ConstraintWeight
23161 X86TargetLowering::getSingleConstraintMatchWeight(
23162 AsmOperandInfo &info, const char *constraint) const {
23163 ConstraintWeight weight = CW_Invalid;
23164 Value *CallOperandVal = info.CallOperandVal;
23165 // If we don't have a value, we can't do a match,
23166 // but allow it at the lowest weight.
23167 if (!CallOperandVal)
23169 Type *type = CallOperandVal->getType();
23170 // Look at the constraint type.
23171 switch (*constraint) {
23173 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23184 if (CallOperandVal->getType()->isIntegerTy())
23185 weight = CW_SpecificReg;
23190 if (type->isFloatingPointTy())
23191 weight = CW_SpecificReg;
23194 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23195 weight = CW_SpecificReg;
23199 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23200 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23201 weight = CW_Register;
23204 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23205 if (C->getZExtValue() <= 31)
23206 weight = CW_Constant;
23210 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23211 if (C->getZExtValue() <= 63)
23212 weight = CW_Constant;
23216 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23217 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23218 weight = CW_Constant;
23222 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23223 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23224 weight = CW_Constant;
23228 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23229 if (C->getZExtValue() <= 3)
23230 weight = CW_Constant;
23234 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23235 if (C->getZExtValue() <= 0xff)
23236 weight = CW_Constant;
23241 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23242 weight = CW_Constant;
23246 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23247 if ((C->getSExtValue() >= -0x80000000LL) &&
23248 (C->getSExtValue() <= 0x7fffffffLL))
23249 weight = CW_Constant;
23253 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23254 if (C->getZExtValue() <= 0xffffffff)
23255 weight = CW_Constant;
23262 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23263 /// with another that has more specific requirements based on the type of the
23264 /// corresponding operand.
23265 const char *X86TargetLowering::
23266 LowerXConstraint(EVT ConstraintVT) const {
23267 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23268 // 'f' like normal targets.
23269 if (ConstraintVT.isFloatingPoint()) {
23270 if (Subtarget->hasSSE2())
23272 if (Subtarget->hasSSE1())
23276 return TargetLowering::LowerXConstraint(ConstraintVT);
23279 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23280 /// vector. If it is invalid, don't add anything to Ops.
23281 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23282 std::string &Constraint,
23283 std::vector<SDValue>&Ops,
23284 SelectionDAG &DAG) const {
23287 // Only support length 1 constraints for now.
23288 if (Constraint.length() > 1) return;
23290 char ConstraintLetter = Constraint[0];
23291 switch (ConstraintLetter) {
23294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23295 if (C->getZExtValue() <= 31) {
23296 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23303 if (C->getZExtValue() <= 63) {
23304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23311 if (isInt<8>(C->getSExtValue())) {
23312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23319 if (C->getZExtValue() <= 255) {
23320 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23326 // 32-bit signed value
23327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23328 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23329 C->getSExtValue())) {
23330 // Widen to 64 bits here to get it sign extended.
23331 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23334 // FIXME gcc accepts some relocatable values here too, but only in certain
23335 // memory models; it's complicated.
23340 // 32-bit unsigned value
23341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23342 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23343 C->getZExtValue())) {
23344 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23348 // FIXME gcc accepts some relocatable values here too, but only in certain
23349 // memory models; it's complicated.
23353 // Literal immediates are always ok.
23354 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23355 // Widen to 64 bits here to get it sign extended.
23356 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23360 // In any sort of PIC mode addresses need to be computed at runtime by
23361 // adding in a register or some sort of table lookup. These can't
23362 // be used as immediates.
23363 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23366 // If we are in non-pic codegen mode, we allow the address of a global (with
23367 // an optional displacement) to be used with 'i'.
23368 GlobalAddressSDNode *GA = nullptr;
23369 int64_t Offset = 0;
23371 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23373 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23374 Offset += GA->getOffset();
23376 } else if (Op.getOpcode() == ISD::ADD) {
23377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23378 Offset += C->getZExtValue();
23379 Op = Op.getOperand(0);
23382 } else if (Op.getOpcode() == ISD::SUB) {
23383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23384 Offset += -C->getZExtValue();
23385 Op = Op.getOperand(0);
23390 // Otherwise, this isn't something we can handle, reject it.
23394 const GlobalValue *GV = GA->getGlobal();
23395 // If we require an extra load to get this address, as in PIC mode, we
23396 // can't accept it.
23397 if (isGlobalStubReference(
23398 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23401 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23402 GA->getValueType(0), Offset);
23407 if (Result.getNode()) {
23408 Ops.push_back(Result);
23411 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23414 std::pair<unsigned, const TargetRegisterClass*>
23415 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23417 // First, see if this is a constraint that directly corresponds to an LLVM
23419 if (Constraint.size() == 1) {
23420 // GCC Constraint Letters
23421 switch (Constraint[0]) {
23423 // TODO: Slight differences here in allocation order and leaving
23424 // RIP in the class. Do they matter any more here than they do
23425 // in the normal allocation?
23426 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23427 if (Subtarget->is64Bit()) {
23428 if (VT == MVT::i32 || VT == MVT::f32)
23429 return std::make_pair(0U, &X86::GR32RegClass);
23430 if (VT == MVT::i16)
23431 return std::make_pair(0U, &X86::GR16RegClass);
23432 if (VT == MVT::i8 || VT == MVT::i1)
23433 return std::make_pair(0U, &X86::GR8RegClass);
23434 if (VT == MVT::i64 || VT == MVT::f64)
23435 return std::make_pair(0U, &X86::GR64RegClass);
23438 // 32-bit fallthrough
23439 case 'Q': // Q_REGS
23440 if (VT == MVT::i32 || VT == MVT::f32)
23441 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23442 if (VT == MVT::i16)
23443 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23444 if (VT == MVT::i8 || VT == MVT::i1)
23445 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23446 if (VT == MVT::i64)
23447 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23449 case 'r': // GENERAL_REGS
23450 case 'l': // INDEX_REGS
23451 if (VT == MVT::i8 || VT == MVT::i1)
23452 return std::make_pair(0U, &X86::GR8RegClass);
23453 if (VT == MVT::i16)
23454 return std::make_pair(0U, &X86::GR16RegClass);
23455 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23456 return std::make_pair(0U, &X86::GR32RegClass);
23457 return std::make_pair(0U, &X86::GR64RegClass);
23458 case 'R': // LEGACY_REGS
23459 if (VT == MVT::i8 || VT == MVT::i1)
23460 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23461 if (VT == MVT::i16)
23462 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23463 if (VT == MVT::i32 || !Subtarget->is64Bit())
23464 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23465 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23466 case 'f': // FP Stack registers.
23467 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23468 // value to the correct fpstack register class.
23469 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23470 return std::make_pair(0U, &X86::RFP32RegClass);
23471 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23472 return std::make_pair(0U, &X86::RFP64RegClass);
23473 return std::make_pair(0U, &X86::RFP80RegClass);
23474 case 'y': // MMX_REGS if MMX allowed.
23475 if (!Subtarget->hasMMX()) break;
23476 return std::make_pair(0U, &X86::VR64RegClass);
23477 case 'Y': // SSE_REGS if SSE2 allowed
23478 if (!Subtarget->hasSSE2()) break;
23480 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23481 if (!Subtarget->hasSSE1()) break;
23483 switch (VT.SimpleTy) {
23485 // Scalar SSE types.
23488 return std::make_pair(0U, &X86::FR32RegClass);
23491 return std::make_pair(0U, &X86::FR64RegClass);
23499 return std::make_pair(0U, &X86::VR128RegClass);
23507 return std::make_pair(0U, &X86::VR256RegClass);
23512 return std::make_pair(0U, &X86::VR512RegClass);
23518 // Use the default implementation in TargetLowering to convert the register
23519 // constraint into a member of a register class.
23520 std::pair<unsigned, const TargetRegisterClass*> Res;
23521 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23523 // Not found as a standard register?
23525 // Map st(0) -> st(7) -> ST0
23526 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23527 tolower(Constraint[1]) == 's' &&
23528 tolower(Constraint[2]) == 't' &&
23529 Constraint[3] == '(' &&
23530 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23531 Constraint[5] == ')' &&
23532 Constraint[6] == '}') {
23534 Res.first = X86::FP0+Constraint[4]-'0';
23535 Res.second = &X86::RFP80RegClass;
23539 // GCC allows "st(0)" to be called just plain "st".
23540 if (StringRef("{st}").equals_lower(Constraint)) {
23541 Res.first = X86::FP0;
23542 Res.second = &X86::RFP80RegClass;
23547 if (StringRef("{flags}").equals_lower(Constraint)) {
23548 Res.first = X86::EFLAGS;
23549 Res.second = &X86::CCRRegClass;
23553 // 'A' means EAX + EDX.
23554 if (Constraint == "A") {
23555 Res.first = X86::EAX;
23556 Res.second = &X86::GR32_ADRegClass;
23562 // Otherwise, check to see if this is a register class of the wrong value
23563 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23564 // turn into {ax},{dx}.
23565 if (Res.second->hasType(VT))
23566 return Res; // Correct type already, nothing to do.
23568 // All of the single-register GCC register classes map their values onto
23569 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23570 // really want an 8-bit or 32-bit register, map to the appropriate register
23571 // class and return the appropriate register.
23572 if (Res.second == &X86::GR16RegClass) {
23573 if (VT == MVT::i8 || VT == MVT::i1) {
23574 unsigned DestReg = 0;
23575 switch (Res.first) {
23577 case X86::AX: DestReg = X86::AL; break;
23578 case X86::DX: DestReg = X86::DL; break;
23579 case X86::CX: DestReg = X86::CL; break;
23580 case X86::BX: DestReg = X86::BL; break;
23583 Res.first = DestReg;
23584 Res.second = &X86::GR8RegClass;
23586 } else if (VT == MVT::i32 || VT == MVT::f32) {
23587 unsigned DestReg = 0;
23588 switch (Res.first) {
23590 case X86::AX: DestReg = X86::EAX; break;
23591 case X86::DX: DestReg = X86::EDX; break;
23592 case X86::CX: DestReg = X86::ECX; break;
23593 case X86::BX: DestReg = X86::EBX; break;
23594 case X86::SI: DestReg = X86::ESI; break;
23595 case X86::DI: DestReg = X86::EDI; break;
23596 case X86::BP: DestReg = X86::EBP; break;
23597 case X86::SP: DestReg = X86::ESP; break;
23600 Res.first = DestReg;
23601 Res.second = &X86::GR32RegClass;
23603 } else if (VT == MVT::i64 || VT == MVT::f64) {
23604 unsigned DestReg = 0;
23605 switch (Res.first) {
23607 case X86::AX: DestReg = X86::RAX; break;
23608 case X86::DX: DestReg = X86::RDX; break;
23609 case X86::CX: DestReg = X86::RCX; break;
23610 case X86::BX: DestReg = X86::RBX; break;
23611 case X86::SI: DestReg = X86::RSI; break;
23612 case X86::DI: DestReg = X86::RDI; break;
23613 case X86::BP: DestReg = X86::RBP; break;
23614 case X86::SP: DestReg = X86::RSP; break;
23617 Res.first = DestReg;
23618 Res.second = &X86::GR64RegClass;
23621 } else if (Res.second == &X86::FR32RegClass ||
23622 Res.second == &X86::FR64RegClass ||
23623 Res.second == &X86::VR128RegClass ||
23624 Res.second == &X86::VR256RegClass ||
23625 Res.second == &X86::FR32XRegClass ||
23626 Res.second == &X86::FR64XRegClass ||
23627 Res.second == &X86::VR128XRegClass ||
23628 Res.second == &X86::VR256XRegClass ||
23629 Res.second == &X86::VR512RegClass) {
23630 // Handle references to XMM physical registers that got mapped into the
23631 // wrong class. This can happen with constraints like {xmm0} where the
23632 // target independent register mapper will just pick the first match it can
23633 // find, ignoring the required type.
23635 if (VT == MVT::f32 || VT == MVT::i32)
23636 Res.second = &X86::FR32RegClass;
23637 else if (VT == MVT::f64 || VT == MVT::i64)
23638 Res.second = &X86::FR64RegClass;
23639 else if (X86::VR128RegClass.hasType(VT))
23640 Res.second = &X86::VR128RegClass;
23641 else if (X86::VR256RegClass.hasType(VT))
23642 Res.second = &X86::VR256RegClass;
23643 else if (X86::VR512RegClass.hasType(VT))
23644 Res.second = &X86::VR512RegClass;
23650 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23652 // Scaling factors are not free at all.
23653 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23654 // will take 2 allocations in the out of order engine instead of 1
23655 // for plain addressing mode, i.e. inst (reg1).
23657 // vaddps (%rsi,%drx), %ymm0, %ymm1
23658 // Requires two allocations (one for the load, one for the computation)
23660 // vaddps (%rsi), %ymm0, %ymm1
23661 // Requires just 1 allocation, i.e., freeing allocations for other operations
23662 // and having less micro operations to execute.
23664 // For some X86 architectures, this is even worse because for instance for
23665 // stores, the complex addressing mode forces the instruction to use the
23666 // "load" ports instead of the dedicated "store" port.
23667 // E.g., on Haswell:
23668 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23669 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23670 if (isLegalAddressingMode(AM, Ty))
23671 // Scale represents reg2 * scale, thus account for 1
23672 // as soon as we use a second register.
23673 return AM.Scale != 0;
23677 bool X86TargetLowering::isTargetFTOL() const {
23678 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();