1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 if (is64Bit) return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
73 return new X8632_ELFTargetObjectFile(TM);
74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
75 return new TargetLoweringObjectFileCOFF();
77 llvm_unreachable("unknown subtarget type");
80 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
81 : TargetLowering(TM, createTLOF(TM)) {
82 Subtarget = &TM.getSubtarget<X86Subtarget>();
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
87 RegInfo = TM.getRegisterInfo();
90 // Set up the TargetLowering object.
92 // X86 is weird, it always uses i8 for shift amounts and setcc results.
93 setShiftAmountType(MVT::i8);
94 setBooleanContents(ZeroOrOneBooleanContent);
95 setSchedulingPreference(Sched::RegPressure);
96 setStackPointerRegisterToSaveRestore(X86StackPtr);
98 if (Subtarget->isTargetDarwin()) {
99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
100 setUseUnderscoreSetJmp(false);
101 setUseUnderscoreLongJmp(false);
102 } else if (Subtarget->isTargetMingw()) {
103 // MS runtime is weird: it exports _setjmp, but longjmp!
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(false);
107 setUseUnderscoreSetJmp(true);
108 setUseUnderscoreLongJmp(true);
111 // Set up the register classes.
112 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 // We have an algorithm for SSE2->double, and we turn this into a
147 // 64-bit FILD followed by conditional FADD for other targets.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
149 // We have an algorithm for SSE2, and we turn this into a 64-bit
150 // FILD for other targets.
151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
160 // SSE has no i16 to fp conversion, only i32
161 if (X86ScalarSSEf32) {
162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
163 // f32 and f64 cases are Legal, f80 case is not
164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
175 // are Legal, f80 is custom lowered.
176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
184 if (X86ScalarSSEf32) {
185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
186 // f32 and f64 cases are Legal, f80 case is not
187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
193 // Handle FP_TO_UINT by promoting the destination to a larger signed
195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
199 if (Subtarget->is64Bit()) {
200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
202 } else if (!UseSoftFloat) {
203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
204 // Expand FP_TO_UINT into a select.
205 // FIXME: We would like to use a Custom expander here eventually to do
206 // the optimal thing for SSE vs. the default expansion in the legalizer.
207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
209 // With SSE3 we can use fisttpll to convert to a signed i64; without
210 // SSE, we're stuck with a fistpll.
211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
214 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
215 if (!X86ScalarSSEf64) {
216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
218 if (Subtarget->is64Bit()) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
221 if (Subtarget->hasMMX() && !DisableMMX)
222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
228 // Scalar integer divide and remainder are lowered to use operations that
229 // produce two results, to match the available instructions. This exposes
230 // the two-result form to trivial CSE, which is able to combine x/y and x%y
231 // into a single instruction.
233 // Scalar integer multiply-high is also lowered to use two-result
234 // operations, to match the available instructions. However, plain multiply
235 // (low) operations are left as Legal, as there are single-result
236 // instructions for this in x86. Using the two-result multiply instructions
237 // when both high and low results are needed must be arranged by dagcombine.
238 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::SREM , MVT::i8 , Expand);
243 setOperationAction(ISD::UREM , MVT::i8 , Expand);
244 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::SREM , MVT::i16 , Expand);
249 setOperationAction(ISD::UREM , MVT::i16 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::SREM , MVT::i32 , Expand);
255 setOperationAction(ISD::UREM , MVT::i32 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::SREM , MVT::i64 , Expand);
261 setOperationAction(ISD::UREM , MVT::i64 , Expand);
263 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
264 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
265 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
267 if (Subtarget->is64Bit())
268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
273 setOperationAction(ISD::FREM , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f64 , Expand);
275 setOperationAction(ISD::FREM , MVT::f80 , Expand);
276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
300 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
302 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
305 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
308 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
322 if (Subtarget->is64Bit())
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
343 if (Subtarget->hasSSE1())
344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
346 // We may not have a libcall for MEMBARRIER so we should lower this.
347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
349 // On X86 and X86-64, atomic operations are lowered to locked instructions.
350 // Locked instructions, in turn, have implicit fence semantics (all memory
351 // operations are flushed before issuing the locked instruction, and they
352 // are not buffered), so we can fold away the common pattern of
353 // fence-atomic-fence.
354 setShouldFoldAtomicFences(true);
356 // Expand certain atomics
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
367 if (!Subtarget->is64Bit()) {
368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
377 // FIXME - use subtarget debug flags
378 if (!Subtarget->isTargetDarwin() &&
379 !Subtarget->isTargetELF() &&
380 !Subtarget->isTargetCygMing()) {
381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
388 if (Subtarget->is64Bit()) {
389 setExceptionPointerRegister(X86::RAX);
390 setExceptionSelectorRegister(X86::RDX);
392 setExceptionPointerRegister(X86::EAX);
393 setExceptionSelectorRegister(X86::EDX);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
400 setOperationAction(ISD::TRAP, MVT::Other, Legal);
402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
403 setOperationAction(ISD::VASTART , MVT::Other, Custom);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::VAARG , MVT::Other, Custom);
407 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
409 setOperationAction(ISD::VAARG , MVT::Other, Expand);
410 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
417 if (Subtarget->isTargetCygMing())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
422 if (!UseSoftFloat && X86ScalarSSEf64) {
423 // f32 and f64 use SSE.
424 // Set up the FP register classes.
425 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
426 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
428 // Use ANDPD to simulate FABS.
429 setOperationAction(ISD::FABS , MVT::f64, Custom);
430 setOperationAction(ISD::FABS , MVT::f32, Custom);
432 // Use XORP to simulate FNEG.
433 setOperationAction(ISD::FNEG , MVT::f64, Custom);
434 setOperationAction(ISD::FNEG , MVT::f32, Custom);
436 // Use ANDPD and ORPD to simulate FCOPYSIGN.
437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
440 // We don't support sin/cos/fmod
441 setOperationAction(ISD::FSIN , MVT::f64, Expand);
442 setOperationAction(ISD::FCOS , MVT::f64, Expand);
443 setOperationAction(ISD::FSIN , MVT::f32, Expand);
444 setOperationAction(ISD::FCOS , MVT::f32, Expand);
446 // Expand FP immediates into loads from the stack, except for the special
448 addLegalFPImmediate(APFloat(+0.0)); // xorpd
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 } else if (!UseSoftFloat && X86ScalarSSEf32) {
451 // Use SSE for f32, x87 for f64.
452 // Set up the FP register classes.
453 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
456 // Use ANDPS to simulate FABS.
457 setOperationAction(ISD::FABS , MVT::f32, Custom);
459 // Use XORP to simulate FNEG.
460 setOperationAction(ISD::FNEG , MVT::f32, Custom);
462 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
464 // Use ANDPS and ORPS to simulate FCOPYSIGN.
465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
468 // We don't support sin/cos/fmod
469 setOperationAction(ISD::FSIN , MVT::f32, Expand);
470 setOperationAction(ISD::FCOS , MVT::f32, Expand);
472 // Special cases we handle for FP constants.
473 addLegalFPImmediate(APFloat(+0.0f)); // xorps
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
480 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
481 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
483 } else if (!UseSoftFloat) {
484 // f32 and f64 in x87.
485 // Set up the FP register classes.
486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
489 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
490 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
495 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
496 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
498 addLegalFPImmediate(APFloat(+0.0)); // FLD0
499 addLegalFPImmediate(APFloat(+1.0)); // FLD1
500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
508 // Long double always uses X87.
510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
511 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
515 APFloat TmpFlt(+0.0);
516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
518 addLegalFPImmediate(TmpFlt); // FLD0
520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
521 APFloat TmpFlt2(+1.0);
522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
524 addLegalFPImmediate(TmpFlt2); // FLD1
525 TmpFlt2.changeSign();
526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
530 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
531 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
535 // Always use a library call for pow.
536 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
540 setOperationAction(ISD::FLOG, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
546 // First set operation action for all vector types to either promote
547 // (for widening) or expand (for scalarization). Then we will selectively
548 // turn on ones that can be effectively codegen'd.
549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
606 setTruncStoreAction((MVT::SimpleValueType)VT,
607 (MVT::SimpleValueType)InnerVT, Expand);
608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
614 // with -msoft-float, disable use of MMX as well.
615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
622 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
623 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
624 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
625 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
627 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
628 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
629 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
630 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
633 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
635 setOperationAction(ISD::AND, MVT::v8i8, Promote);
636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
637 setOperationAction(ISD::AND, MVT::v4i16, Promote);
638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
639 setOperationAction(ISD::AND, MVT::v2i32, Promote);
640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
641 setOperationAction(ISD::AND, MVT::v1i64, Legal);
643 setOperationAction(ISD::OR, MVT::v8i8, Promote);
644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
645 setOperationAction(ISD::OR, MVT::v4i16, Promote);
646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
647 setOperationAction(ISD::OR, MVT::v2i32, Promote);
648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
649 setOperationAction(ISD::OR, MVT::v1i64, Legal);
651 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
653 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
655 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
657 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
699 if (!UseSoftFloat && Subtarget->hasSSE1()) {
700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
702 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
716 if (!UseSoftFloat && Subtarget->hasSSE2()) {
717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
720 // registers cannot be used even for integer operations.
721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
726 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
727 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
728 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
729 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
730 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
731 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
732 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
733 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
734 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
736 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
762 EVT VT = (MVT::SimpleValueType)i;
763 // Do not attempt to custom lower non-power-of-2 vectors
764 if (!isPowerOf2_32(VT.getVectorNumElements()))
766 // Do not attempt to custom lower non-128-bit vectors
767 if (!VT.is128BitVector())
769 setOperationAction(ISD::BUILD_VECTOR,
770 VT.getSimpleVT().SimpleTy, Custom);
771 setOperationAction(ISD::VECTOR_SHUFFLE,
772 VT.getSimpleVT().SimpleTy, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
774 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
784 if (Subtarget->is64Bit()) {
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
794 // Do not attempt to promote non-128-bit vectors
795 if (!VT.is128BitVector())
798 setOperationAction(ISD::AND, SVT, Promote);
799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
800 setOperationAction(ISD::OR, SVT, Promote);
801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
802 setOperationAction(ISD::XOR, SVT, Promote);
803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
804 setOperationAction(ISD::LOAD, SVT, Promote);
805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
806 setOperationAction(ISD::SELECT, SVT, Promote);
807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
810 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
812 // Custom lower v2i64 and v2f64 selects.
813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
820 if (!DisableMMX && Subtarget->hasMMX()) {
821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
826 if (Subtarget->hasSSE41()) {
827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
828 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
830 setOperationAction(ISD::FRINT, MVT::f32, Legal);
831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
833 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
835 setOperationAction(ISD::FRINT, MVT::f64, Legal);
836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
838 // FIXME: Do we need to handle scalar-to-vector here?
839 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
841 // i8 and i16 vectors are custom , because the source register and source
842 // source memory operand types are not the same width. f32 vectors are
843 // custom since the immediate controlling the insert encodes additional
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
855 if (Subtarget->is64Bit()) {
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
861 if (Subtarget->hasSSE42()) {
862 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
865 if (!UseSoftFloat && Subtarget->hasAVX()) {
866 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
867 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
868 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
869 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
871 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
872 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
873 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
874 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
875 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
876 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
877 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
878 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
880 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
881 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
882 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
883 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
884 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
885 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
887 // Operations to consider commented out -v16i16 v32i8
888 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
889 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
890 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
891 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
892 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
893 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
894 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
895 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
896 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
897 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
898 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
899 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
900 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
901 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
903 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
904 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
905 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
906 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
909 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
910 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
917 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
922 // Not sure we want to do this since there are no 256-bit integer
925 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
926 // This includes 256-bit vectors
927 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
928 EVT VT = (MVT::SimpleValueType)i;
930 // Do not attempt to custom lower non-power-of-2 vectors
931 if (!isPowerOf2_32(VT.getVectorNumElements()))
934 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
939 if (Subtarget->is64Bit()) {
940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
946 // Not sure we want to do this since there are no 256-bit integer
949 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
950 // Including 256-bit vectors
951 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
952 EVT VT = (MVT::SimpleValueType)i;
954 if (!VT.is256BitVector()) {
957 setOperationAction(ISD::AND, VT, Promote);
958 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
959 setOperationAction(ISD::OR, VT, Promote);
960 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
961 setOperationAction(ISD::XOR, VT, Promote);
962 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
963 setOperationAction(ISD::LOAD, VT, Promote);
964 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
965 setOperationAction(ISD::SELECT, VT, Promote);
966 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
969 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
973 // We want to custom lower some of our intrinsics.
974 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
976 // Add/Sub/Mul with overflow operations are custom lowered.
977 setOperationAction(ISD::SADDO, MVT::i32, Custom);
978 setOperationAction(ISD::UADDO, MVT::i32, Custom);
979 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
980 setOperationAction(ISD::USUBO, MVT::i32, Custom);
981 setOperationAction(ISD::SMULO, MVT::i32, Custom);
983 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
984 // handle type legalization for these operations here.
986 // FIXME: We really should do custom legalization for addition and
987 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
988 // than generic legalization for 64-bit multiplication-with-overflow, though.
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::SADDO, MVT::i64, Custom);
991 setOperationAction(ISD::UADDO, MVT::i64, Custom);
992 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
993 setOperationAction(ISD::USUBO, MVT::i64, Custom);
994 setOperationAction(ISD::SMULO, MVT::i64, Custom);
997 if (!Subtarget->is64Bit()) {
998 // These libcalls are not available in 32-bit.
999 setLibcallName(RTLIB::SHL_I128, 0);
1000 setLibcallName(RTLIB::SRL_I128, 0);
1001 setLibcallName(RTLIB::SRA_I128, 0);
1004 // We have target-specific dag combine patterns for the following nodes:
1005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1006 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1007 setTargetDAGCombine(ISD::BUILD_VECTOR);
1008 setTargetDAGCombine(ISD::SELECT);
1009 setTargetDAGCombine(ISD::SHL);
1010 setTargetDAGCombine(ISD::SRA);
1011 setTargetDAGCombine(ISD::SRL);
1012 setTargetDAGCombine(ISD::OR);
1013 setTargetDAGCombine(ISD::STORE);
1014 setTargetDAGCombine(ISD::ZERO_EXTEND);
1015 if (Subtarget->is64Bit())
1016 setTargetDAGCombine(ISD::MUL);
1018 computeRegisterProperties();
1020 // FIXME: These should be based on subtarget info. Plus, the values should
1021 // be smaller when we are in optimizing for size mode.
1022 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1023 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1024 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1025 setPrefLoopAlignment(16);
1026 benefitFromCodePlacementOpt = true;
1030 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1035 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1036 /// the desired ByVal argument alignment.
1037 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1040 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1041 if (VTy->getBitWidth() == 128)
1043 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1044 unsigned EltAlign = 0;
1045 getMaxByValAlign(ATy->getElementType(), EltAlign);
1046 if (EltAlign > MaxAlign)
1047 MaxAlign = EltAlign;
1048 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1049 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1050 unsigned EltAlign = 0;
1051 getMaxByValAlign(STy->getElementType(i), EltAlign);
1052 if (EltAlign > MaxAlign)
1053 MaxAlign = EltAlign;
1061 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1062 /// function arguments in the caller parameter area. For X86, aggregates
1063 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1064 /// are at 4-byte boundaries.
1065 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1066 if (Subtarget->is64Bit()) {
1067 // Max of 8 and alignment of type.
1068 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1075 if (Subtarget->hasSSE1())
1076 getMaxByValAlign(Ty, Align);
1080 /// getOptimalMemOpType - Returns the target specific optimal type for load
1081 /// and store operations as a result of memset, memcpy, and memmove
1082 /// lowering. If DstAlign is zero that means it's safe to destination
1083 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1084 /// means there isn't a need to check it against alignment requirement,
1085 /// probably because the source does not need to be loaded. If
1086 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1087 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1088 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1089 /// constant so it does not need to be loaded.
1090 /// It returns EVT::Other if the type should be determined using generic
1091 /// target-independent logic.
1093 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1094 unsigned DstAlign, unsigned SrcAlign,
1095 bool NonScalarIntSafe,
1097 MachineFunction &MF) const {
1098 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1099 // linux. This is because the stack realignment code can't handle certain
1100 // cases like PR2962. This should be removed when PR2962 is fixed.
1101 const Function *F = MF.getFunction();
1102 if (NonScalarIntSafe &&
1103 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1105 (Subtarget->isUnalignedMemAccessFast() ||
1106 ((DstAlign == 0 || DstAlign >= 16) &&
1107 (SrcAlign == 0 || SrcAlign >= 16))) &&
1108 Subtarget->getStackAlignment() >= 16) {
1109 if (Subtarget->hasSSE2())
1111 if (Subtarget->hasSSE1())
1113 } else if (!MemcpyStrSrc && Size >= 8 &&
1114 !Subtarget->is64Bit() &&
1115 Subtarget->getStackAlignment() >= 8 &&
1116 Subtarget->hasSSE2()) {
1117 // Do not use f64 to lower memcpy if source is string constant. It's
1118 // better to use i32 to avoid the loads.
1122 if (Subtarget->is64Bit() && Size >= 8)
1127 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1128 /// current function. The returned value is a member of the
1129 /// MachineJumpTableInfo::JTEntryKind enum.
1130 unsigned X86TargetLowering::getJumpTableEncoding() const {
1131 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1134 Subtarget->isPICStyleGOT())
1135 return MachineJumpTableInfo::EK_Custom32;
1137 // Otherwise, use the normal jump table encoding heuristics.
1138 return TargetLowering::getJumpTableEncoding();
1141 /// getPICBaseSymbol - Return the X86-32 PIC base.
1143 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1144 MCContext &Ctx) const {
1145 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1146 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1147 Twine(MF->getFunctionNumber())+"$pb");
1152 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1153 const MachineBasicBlock *MBB,
1154 unsigned uid,MCContext &Ctx) const{
1155 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1156 Subtarget->isPICStyleGOT());
1157 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1159 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1160 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1163 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1165 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1166 SelectionDAG &DAG) const {
1167 if (!Subtarget->is64Bit())
1168 // This doesn't have DebugLoc associated with it, but is not really the
1169 // same as a Register.
1170 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1174 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1175 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1177 const MCExpr *X86TargetLowering::
1178 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1179 MCContext &Ctx) const {
1180 // X86-64 uses RIP relative addressing based on the jump table label.
1181 if (Subtarget->isPICStyleRIPRel())
1182 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1184 // Otherwise, the reference is relative to the PIC base.
1185 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1188 /// getFunctionAlignment - Return the Log2 alignment of this function.
1189 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1190 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1193 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1194 unsigned &Offset) const {
1195 if (!Subtarget->isTargetLinux())
1198 if (Subtarget->is64Bit()) {
1199 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1201 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1214 //===----------------------------------------------------------------------===//
1215 // Return Value Calling Convention Implementation
1216 //===----------------------------------------------------------------------===//
1218 #include "X86GenCallingConv.inc"
1221 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1222 const SmallVectorImpl<ISD::OutputArg> &Outs,
1223 LLVMContext &Context) const {
1224 SmallVector<CCValAssign, 16> RVLocs;
1225 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1227 return CCInfo.CheckReturn(Outs, RetCC_X86);
1231 X86TargetLowering::LowerReturn(SDValue Chain,
1232 CallingConv::ID CallConv, bool isVarArg,
1233 const SmallVectorImpl<ISD::OutputArg> &Outs,
1234 const SmallVectorImpl<SDValue> &OutVals,
1235 DebugLoc dl, SelectionDAG &DAG) const {
1236 MachineFunction &MF = DAG.getMachineFunction();
1237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1239 SmallVector<CCValAssign, 16> RVLocs;
1240 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1241 RVLocs, *DAG.getContext());
1242 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1244 // Add the regs to the liveout set for the function.
1245 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1246 for (unsigned i = 0; i != RVLocs.size(); ++i)
1247 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1248 MRI.addLiveOut(RVLocs[i].getLocReg());
1252 SmallVector<SDValue, 6> RetOps;
1253 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1254 // Operand #1 = Bytes To Pop
1255 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1258 // Copy the result values into the output registers.
1259 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1260 CCValAssign &VA = RVLocs[i];
1261 assert(VA.isRegLoc() && "Can only return in registers!");
1262 SDValue ValToCopy = OutVals[i];
1264 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1265 // the RET instruction and handled by the FP Stackifier.
1266 if (VA.getLocReg() == X86::ST0 ||
1267 VA.getLocReg() == X86::ST1) {
1268 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1269 // change the value to the FP stack register class.
1270 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1271 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1272 RetOps.push_back(ValToCopy);
1273 // Don't emit a copytoreg.
1277 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1278 // which is returned in RAX / RDX.
1279 if (Subtarget->is64Bit()) {
1280 EVT ValVT = ValToCopy.getValueType();
1281 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1282 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1283 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1284 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1289 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1290 Flag = Chain.getValue(1);
1293 // The x86-64 ABI for returning structs by value requires that we copy
1294 // the sret argument into %rax for the return. We saved the argument into
1295 // a virtual register in the entry block, so now we copy the value out
1297 if (Subtarget->is64Bit() &&
1298 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1301 unsigned Reg = FuncInfo->getSRetReturnReg();
1303 "SRetReturnReg should have been set in LowerFormalArguments().");
1304 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1306 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1307 Flag = Chain.getValue(1);
1309 // RAX now acts like a return value.
1310 MRI.addLiveOut(X86::RAX);
1313 RetOps[0] = Chain; // Update chain.
1315 // Add the flag if we have it.
1317 RetOps.push_back(Flag);
1319 return DAG.getNode(X86ISD::RET_FLAG, dl,
1320 MVT::Other, &RetOps[0], RetOps.size());
1323 /// LowerCallResult - Lower the result values of a call into the
1324 /// appropriate copies out of appropriate physical registers.
1327 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1328 CallingConv::ID CallConv, bool isVarArg,
1329 const SmallVectorImpl<ISD::InputArg> &Ins,
1330 DebugLoc dl, SelectionDAG &DAG,
1331 SmallVectorImpl<SDValue> &InVals) const {
1333 // Assign locations to each value returned by this call.
1334 SmallVector<CCValAssign, 16> RVLocs;
1335 bool Is64Bit = Subtarget->is64Bit();
1336 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1337 RVLocs, *DAG.getContext());
1338 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1340 // Copy all of the result registers out of their specified physreg.
1341 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1342 CCValAssign &VA = RVLocs[i];
1343 EVT CopyVT = VA.getValVT();
1345 // If this is x86-64, and we disabled SSE, we can't return FP values
1346 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1347 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1348 report_fatal_error("SSE register return with SSE disabled");
1353 // If this is a call to a function that returns an fp value on the floating
1354 // point stack, we must guarantee the the value is popped from the stack, so
1355 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1356 // if the return value is not used. We use the FpGET_ST0 instructions
1358 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1359 // If we prefer to use the value in xmm registers, copy it out as f80 and
1360 // use a truncate to move it from fp stack reg to xmm reg.
1361 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1362 bool isST0 = VA.getLocReg() == X86::ST0;
1364 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1365 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1366 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1367 SDValue Ops[] = { Chain, InFlag };
1368 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1370 Val = Chain.getValue(0);
1372 // Round the f80 to the right size, which also moves it to the appropriate
1374 if (CopyVT != VA.getValVT())
1375 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1376 // This truncation won't change the value.
1377 DAG.getIntPtrConstant(1));
1378 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1379 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1380 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1381 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1382 MVT::v2i64, InFlag).getValue(1);
1383 Val = Chain.getValue(0);
1384 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1385 Val, DAG.getConstant(0, MVT::i64));
1387 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1388 MVT::i64, InFlag).getValue(1);
1389 Val = Chain.getValue(0);
1391 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1393 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1394 CopyVT, InFlag).getValue(1);
1395 Val = Chain.getValue(0);
1397 InFlag = Chain.getValue(2);
1398 InVals.push_back(Val);
1405 //===----------------------------------------------------------------------===//
1406 // C & StdCall & Fast Calling Convention implementation
1407 //===----------------------------------------------------------------------===//
1408 // StdCall calling convention seems to be standard for many Windows' API
1409 // routines and around. It differs from C calling convention just a little:
1410 // callee should clean up the stack, not caller. Symbols should be also
1411 // decorated in some fancy way :) It doesn't support any vector arguments.
1412 // For info on fast calling convention see Fast Calling Convention (tail call)
1413 // implementation LowerX86_32FastCCCallTo.
1415 /// CallIsStructReturn - Determines whether a call uses struct return
1417 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1421 return Outs[0].Flags.isSRet();
1424 /// ArgsAreStructReturn - Determines whether a function uses struct
1425 /// return semantics.
1427 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1431 return Ins[0].Flags.isSRet();
1434 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1435 /// given CallingConvention value.
1436 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1437 if (Subtarget->is64Bit()) {
1438 if (CC == CallingConv::GHC)
1439 return CC_X86_64_GHC;
1440 else if (Subtarget->isTargetWin64())
1441 return CC_X86_Win64_C;
1446 if (CC == CallingConv::X86_FastCall)
1447 return CC_X86_32_FastCall;
1448 else if (CC == CallingConv::X86_ThisCall)
1449 return CC_X86_32_ThisCall;
1450 else if (CC == CallingConv::Fast)
1451 return CC_X86_32_FastCC;
1452 else if (CC == CallingConv::GHC)
1453 return CC_X86_32_GHC;
1458 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1459 /// by "Src" to address "Dst" with size and alignment information specified by
1460 /// the specific parameter attribute. The copy will be passed as a byval
1461 /// function parameter.
1463 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1464 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1466 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1467 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1468 /*isVolatile*/false, /*AlwaysInline=*/true,
1472 /// IsTailCallConvention - Return true if the calling convention is one that
1473 /// supports tail call optimization.
1474 static bool IsTailCallConvention(CallingConv::ID CC) {
1475 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1478 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1479 /// a tailcall target by changing its ABI.
1480 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1481 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1485 X86TargetLowering::LowerMemArgument(SDValue Chain,
1486 CallingConv::ID CallConv,
1487 const SmallVectorImpl<ISD::InputArg> &Ins,
1488 DebugLoc dl, SelectionDAG &DAG,
1489 const CCValAssign &VA,
1490 MachineFrameInfo *MFI,
1492 // Create the nodes corresponding to a load from this parameter slot.
1493 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1494 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1495 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1498 // If value is passed by pointer we have address passed instead of the value
1500 if (VA.getLocInfo() == CCValAssign::Indirect)
1501 ValVT = VA.getLocVT();
1503 ValVT = VA.getValVT();
1505 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1506 // changed with more analysis.
1507 // In case of tail call optimization mark all arguments mutable. Since they
1508 // could be overwritten by lowering of arguments in case of a tail call.
1509 if (Flags.isByVal()) {
1510 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1511 VA.getLocMemOffset(), isImmutable);
1512 return DAG.getFrameIndex(FI, getPointerTy());
1514 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1515 VA.getLocMemOffset(), isImmutable);
1516 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1517 return DAG.getLoad(ValVT, dl, Chain, FIN,
1518 PseudoSourceValue::getFixedStack(FI), 0,
1524 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1525 CallingConv::ID CallConv,
1527 const SmallVectorImpl<ISD::InputArg> &Ins,
1530 SmallVectorImpl<SDValue> &InVals)
1532 MachineFunction &MF = DAG.getMachineFunction();
1533 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1535 const Function* Fn = MF.getFunction();
1536 if (Fn->hasExternalLinkage() &&
1537 Subtarget->isTargetCygMing() &&
1538 Fn->getName() == "main")
1539 FuncInfo->setForceFramePointer(true);
1541 MachineFrameInfo *MFI = MF.getFrameInfo();
1542 bool Is64Bit = Subtarget->is64Bit();
1543 bool IsWin64 = Subtarget->isTargetWin64();
1545 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1546 "Var args not supported with calling convention fastcc or ghc");
1548 // Assign locations to all of the incoming arguments.
1549 SmallVector<CCValAssign, 16> ArgLocs;
1550 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1551 ArgLocs, *DAG.getContext());
1552 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1554 unsigned LastVal = ~0U;
1556 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1557 CCValAssign &VA = ArgLocs[i];
1558 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1560 assert(VA.getValNo() != LastVal &&
1561 "Don't support value assigned to multiple locs yet");
1562 LastVal = VA.getValNo();
1564 if (VA.isRegLoc()) {
1565 EVT RegVT = VA.getLocVT();
1566 TargetRegisterClass *RC = NULL;
1567 if (RegVT == MVT::i32)
1568 RC = X86::GR32RegisterClass;
1569 else if (Is64Bit && RegVT == MVT::i64)
1570 RC = X86::GR64RegisterClass;
1571 else if (RegVT == MVT::f32)
1572 RC = X86::FR32RegisterClass;
1573 else if (RegVT == MVT::f64)
1574 RC = X86::FR64RegisterClass;
1575 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1576 RC = X86::VR128RegisterClass;
1577 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1578 RC = X86::VR64RegisterClass;
1580 llvm_unreachable("Unknown argument type!");
1582 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1583 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1585 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1586 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1588 if (VA.getLocInfo() == CCValAssign::SExt)
1589 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1590 DAG.getValueType(VA.getValVT()));
1591 else if (VA.getLocInfo() == CCValAssign::ZExt)
1592 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1593 DAG.getValueType(VA.getValVT()));
1594 else if (VA.getLocInfo() == CCValAssign::BCvt)
1595 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1597 if (VA.isExtInLoc()) {
1598 // Handle MMX values passed in XMM regs.
1599 if (RegVT.isVector()) {
1600 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1601 ArgValue, DAG.getConstant(0, MVT::i64));
1602 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1604 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1607 assert(VA.isMemLoc());
1608 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1611 // If value is passed via pointer - do a load.
1612 if (VA.getLocInfo() == CCValAssign::Indirect)
1613 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1616 InVals.push_back(ArgValue);
1619 // The x86-64 ABI for returning structs by value requires that we copy
1620 // the sret argument into %rax for the return. Save the argument into
1621 // a virtual register so that we can access it from the return points.
1622 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1623 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1624 unsigned Reg = FuncInfo->getSRetReturnReg();
1626 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1627 FuncInfo->setSRetReturnReg(Reg);
1629 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1630 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1633 unsigned StackSize = CCInfo.getNextStackOffset();
1634 // Align stack specially for tail calls.
1635 if (FuncIsMadeTailCallSafe(CallConv))
1636 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1638 // If the function takes variable number of arguments, make a frame index for
1639 // the start of the first vararg value... for expansion of llvm.va_start.
1641 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1642 CallConv != CallingConv::X86_ThisCall)) {
1643 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1646 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1648 // FIXME: We should really autogenerate these arrays
1649 static const unsigned GPR64ArgRegsWin64[] = {
1650 X86::RCX, X86::RDX, X86::R8, X86::R9
1652 static const unsigned XMMArgRegsWin64[] = {
1653 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1655 static const unsigned GPR64ArgRegs64Bit[] = {
1656 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1658 static const unsigned XMMArgRegs64Bit[] = {
1659 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1660 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1662 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1665 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1666 GPR64ArgRegs = GPR64ArgRegsWin64;
1667 XMMArgRegs = XMMArgRegsWin64;
1669 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1670 GPR64ArgRegs = GPR64ArgRegs64Bit;
1671 XMMArgRegs = XMMArgRegs64Bit;
1673 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1675 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1678 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1679 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1680 "SSE register cannot be used when SSE is disabled!");
1681 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1682 "SSE register cannot be used when SSE is disabled!");
1683 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1684 // Kernel mode asks for SSE to be disabled, so don't push them
1686 TotalNumXMMRegs = 0;
1688 // For X86-64, if there are vararg parameters that are passed via
1689 // registers, then we must store them to their spots on the stack so they
1690 // may be loaded by deferencing the result of va_next.
1691 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1692 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1693 FuncInfo->setRegSaveFrameIndex(
1694 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1697 // Store the integer parameter registers.
1698 SmallVector<SDValue, 8> MemOps;
1699 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1701 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1702 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1703 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1704 DAG.getIntPtrConstant(Offset));
1705 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1706 X86::GR64RegisterClass);
1707 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1709 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1710 PseudoSourceValue::getFixedStack(
1711 FuncInfo->getRegSaveFrameIndex()),
1712 Offset, false, false, 0);
1713 MemOps.push_back(Store);
1717 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1718 // Now store the XMM (fp + vector) parameter registers.
1719 SmallVector<SDValue, 11> SaveXMMOps;
1720 SaveXMMOps.push_back(Chain);
1722 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1723 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1724 SaveXMMOps.push_back(ALVal);
1726 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1727 FuncInfo->getRegSaveFrameIndex()));
1728 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1729 FuncInfo->getVarArgsFPOffset()));
1731 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1732 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1733 X86::VR128RegisterClass);
1734 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1735 SaveXMMOps.push_back(Val);
1737 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1739 &SaveXMMOps[0], SaveXMMOps.size()));
1742 if (!MemOps.empty())
1743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1744 &MemOps[0], MemOps.size());
1748 // Some CCs need callee pop.
1749 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1750 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1752 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1753 // If this is an sret function, the return should pop the hidden pointer.
1754 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1755 FuncInfo->setBytesToPopOnReturn(4);
1759 // RegSaveFrameIndex is X86-64 only.
1760 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1761 if (CallConv == CallingConv::X86_FastCall ||
1762 CallConv == CallingConv::X86_ThisCall)
1763 // fastcc functions can't have varargs.
1764 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1771 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1772 SDValue StackPtr, SDValue Arg,
1773 DebugLoc dl, SelectionDAG &DAG,
1774 const CCValAssign &VA,
1775 ISD::ArgFlagsTy Flags) const {
1776 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1777 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1778 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1779 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1780 if (Flags.isByVal()) {
1781 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1783 return DAG.getStore(Chain, dl, Arg, PtrOff,
1784 PseudoSourceValue::getStack(), LocMemOffset,
1788 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1789 /// optimization is performed and it is required.
1791 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1792 SDValue &OutRetAddr, SDValue Chain,
1793 bool IsTailCall, bool Is64Bit,
1794 int FPDiff, DebugLoc dl) const {
1795 // Adjust the Return address stack slot.
1796 EVT VT = getPointerTy();
1797 OutRetAddr = getReturnAddressFrameIndex(DAG);
1799 // Load the "old" Return address.
1800 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1801 return SDValue(OutRetAddr.getNode(), 1);
1804 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1805 /// optimization is performed and it is required (FPDiff!=0).
1807 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1808 SDValue Chain, SDValue RetAddrFrIdx,
1809 bool Is64Bit, int FPDiff, DebugLoc dl) {
1810 // Store the return address to the appropriate stack slot.
1811 if (!FPDiff) return Chain;
1812 // Calculate the new stack slot for the return address.
1813 int SlotSize = Is64Bit ? 8 : 4;
1814 int NewReturnAddrFI =
1815 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1816 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1817 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1818 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1819 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1825 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1826 CallingConv::ID CallConv, bool isVarArg,
1828 const SmallVectorImpl<ISD::OutputArg> &Outs,
1829 const SmallVectorImpl<SDValue> &OutVals,
1830 const SmallVectorImpl<ISD::InputArg> &Ins,
1831 DebugLoc dl, SelectionDAG &DAG,
1832 SmallVectorImpl<SDValue> &InVals) const {
1833 MachineFunction &MF = DAG.getMachineFunction();
1834 bool Is64Bit = Subtarget->is64Bit();
1835 bool IsStructRet = CallIsStructReturn(Outs);
1836 bool IsSibcall = false;
1839 // Check if it's really possible to do a tail call.
1840 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1841 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1842 Outs, OutVals, Ins, DAG);
1844 // Sibcalls are automatically detected tailcalls which do not require
1846 if (!GuaranteedTailCallOpt && isTailCall)
1853 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1854 "Var args not supported with calling convention fastcc or ghc");
1856 // Analyze operands of the call, assigning locations to each operand.
1857 SmallVector<CCValAssign, 16> ArgLocs;
1858 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1859 ArgLocs, *DAG.getContext());
1860 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1862 // Get a count of how many bytes are to be pushed on the stack.
1863 unsigned NumBytes = CCInfo.getNextStackOffset();
1865 // This is a sibcall. The memory operands are available in caller's
1866 // own caller's stack.
1868 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1869 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1872 if (isTailCall && !IsSibcall) {
1873 // Lower arguments at fp - stackoffset + fpdiff.
1874 unsigned NumBytesCallerPushed =
1875 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1876 FPDiff = NumBytesCallerPushed - NumBytes;
1878 // Set the delta of movement of the returnaddr stackslot.
1879 // But only set if delta is greater than previous delta.
1880 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1881 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1885 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1887 SDValue RetAddrFrIdx;
1888 // Load return adress for tail calls.
1889 if (isTailCall && FPDiff)
1890 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1891 Is64Bit, FPDiff, dl);
1893 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1894 SmallVector<SDValue, 8> MemOpChains;
1897 // Walk the register/memloc assignments, inserting copies/loads. In the case
1898 // of tail call optimization arguments are handle later.
1899 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1900 CCValAssign &VA = ArgLocs[i];
1901 EVT RegVT = VA.getLocVT();
1902 SDValue Arg = OutVals[i];
1903 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1904 bool isByVal = Flags.isByVal();
1906 // Promote the value if needed.
1907 switch (VA.getLocInfo()) {
1908 default: llvm_unreachable("Unknown loc info!");
1909 case CCValAssign::Full: break;
1910 case CCValAssign::SExt:
1911 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1913 case CCValAssign::ZExt:
1914 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1916 case CCValAssign::AExt:
1917 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1918 // Special case: passing MMX values in XMM registers.
1919 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1920 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1921 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1923 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1925 case CCValAssign::BCvt:
1926 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1928 case CCValAssign::Indirect: {
1929 // Store the argument.
1930 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1931 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1932 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1933 PseudoSourceValue::getFixedStack(FI), 0,
1940 if (VA.isRegLoc()) {
1941 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1943 assert(VA.isMemLoc());
1944 if (StackPtr.getNode() == 0)
1945 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1946 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1947 dl, DAG, VA, Flags));
1951 if (!MemOpChains.empty())
1952 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1953 &MemOpChains[0], MemOpChains.size());
1955 // Build a sequence of copy-to-reg nodes chained together with token chain
1956 // and flag operands which copy the outgoing args into registers.
1958 // Tail call byval lowering might overwrite argument registers so in case of
1959 // tail call optimization the copies to registers are lowered later.
1961 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1962 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1963 RegsToPass[i].second, InFlag);
1964 InFlag = Chain.getValue(1);
1967 if (Subtarget->isPICStyleGOT()) {
1968 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1971 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1972 DAG.getNode(X86ISD::GlobalBaseReg,
1973 DebugLoc(), getPointerTy()),
1975 InFlag = Chain.getValue(1);
1977 // If we are tail calling and generating PIC/GOT style code load the
1978 // address of the callee into ECX. The value in ecx is used as target of
1979 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1980 // for tail calls on PIC/GOT architectures. Normally we would just put the
1981 // address of GOT into ebx and then call target@PLT. But for tail calls
1982 // ebx would be restored (since ebx is callee saved) before jumping to the
1985 // Note: The actual moving to ECX is done further down.
1986 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1987 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1988 !G->getGlobal()->hasProtectedVisibility())
1989 Callee = LowerGlobalAddress(Callee, DAG);
1990 else if (isa<ExternalSymbolSDNode>(Callee))
1991 Callee = LowerExternalSymbol(Callee, DAG);
1995 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
1996 // From AMD64 ABI document:
1997 // For calls that may call functions that use varargs or stdargs
1998 // (prototype-less calls or calls to functions containing ellipsis (...) in
1999 // the declaration) %al is used as hidden argument to specify the number
2000 // of SSE registers used. The contents of %al do not need to match exactly
2001 // the number of registers, but must be an ubound on the number of SSE
2002 // registers used and is in the range 0 - 8 inclusive.
2004 // Count the number of XMM registers allocated.
2005 static const unsigned XMMArgRegs[] = {
2006 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2007 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2009 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2010 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2011 && "SSE registers cannot be used when SSE is disabled");
2013 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2014 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2015 InFlag = Chain.getValue(1);
2019 // For tail calls lower the arguments to the 'real' stack slot.
2021 // Force all the incoming stack arguments to be loaded from the stack
2022 // before any new outgoing arguments are stored to the stack, because the
2023 // outgoing stack slots may alias the incoming argument stack slots, and
2024 // the alias isn't otherwise explicit. This is slightly more conservative
2025 // than necessary, because it means that each store effectively depends
2026 // on every argument instead of just those arguments it would clobber.
2027 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2029 SmallVector<SDValue, 8> MemOpChains2;
2032 // Do not flag preceeding copytoreg stuff together with the following stuff.
2034 if (GuaranteedTailCallOpt) {
2035 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2036 CCValAssign &VA = ArgLocs[i];
2039 assert(VA.isMemLoc());
2040 SDValue Arg = OutVals[i];
2041 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2042 // Create frame index.
2043 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2044 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2045 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2046 FIN = DAG.getFrameIndex(FI, getPointerTy());
2048 if (Flags.isByVal()) {
2049 // Copy relative to framepointer.
2050 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2051 if (StackPtr.getNode() == 0)
2052 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2054 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2056 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2060 // Store relative to framepointer.
2061 MemOpChains2.push_back(
2062 DAG.getStore(ArgChain, dl, Arg, FIN,
2063 PseudoSourceValue::getFixedStack(FI), 0,
2069 if (!MemOpChains2.empty())
2070 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2071 &MemOpChains2[0], MemOpChains2.size());
2073 // Copy arguments to their registers.
2074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2076 RegsToPass[i].second, InFlag);
2077 InFlag = Chain.getValue(1);
2081 // Store the return address to the appropriate stack slot.
2082 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2086 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2087 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2088 // In the 64-bit large code model, we have to make all calls
2089 // through a register, since the call instruction's 32-bit
2090 // pc-relative offset may not be large enough to hold the whole
2092 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2093 // If the callee is a GlobalAddress node (quite common, every direct call
2094 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2097 // We should use extra load for direct calls to dllimported functions in
2099 const GlobalValue *GV = G->getGlobal();
2100 if (!GV->hasDLLImportLinkage()) {
2101 unsigned char OpFlags = 0;
2103 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2104 // external symbols most go through the PLT in PIC mode. If the symbol
2105 // has hidden or protected visibility, or if it is static or local, then
2106 // we don't need to use the PLT - we can directly call it.
2107 if (Subtarget->isTargetELF() &&
2108 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2109 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2110 OpFlags = X86II::MO_PLT;
2111 } else if (Subtarget->isPICStyleStubAny() &&
2112 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2113 Subtarget->getDarwinVers() < 9) {
2114 // PC-relative references to external symbols should go through $stub,
2115 // unless we're building with the leopard linker or later, which
2116 // automatically synthesizes these stubs.
2117 OpFlags = X86II::MO_DARWIN_STUB;
2120 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2121 G->getOffset(), OpFlags);
2123 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2124 unsigned char OpFlags = 0;
2126 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2127 // symbols should go through the PLT.
2128 if (Subtarget->isTargetELF() &&
2129 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2130 OpFlags = X86II::MO_PLT;
2131 } else if (Subtarget->isPICStyleStubAny() &&
2132 Subtarget->getDarwinVers() < 9) {
2133 // PC-relative references to external symbols should go through $stub,
2134 // unless we're building with the leopard linker or later, which
2135 // automatically synthesizes these stubs.
2136 OpFlags = X86II::MO_DARWIN_STUB;
2139 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2143 // Returns a chain & a flag for retval copy to use.
2144 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2145 SmallVector<SDValue, 8> Ops;
2147 if (!IsSibcall && isTailCall) {
2148 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2149 DAG.getIntPtrConstant(0, true), InFlag);
2150 InFlag = Chain.getValue(1);
2153 Ops.push_back(Chain);
2154 Ops.push_back(Callee);
2157 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2159 // Add argument registers to the end of the list so that they are known live
2161 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2162 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2163 RegsToPass[i].second.getValueType()));
2165 // Add an implicit use GOT pointer in EBX.
2166 if (!isTailCall && Subtarget->isPICStyleGOT())
2167 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2169 // Add an implicit use of AL for x86 vararg functions.
2170 if (Is64Bit && isVarArg)
2171 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2173 if (InFlag.getNode())
2174 Ops.push_back(InFlag);
2178 //// If this is the first return lowered for this function, add the regs
2179 //// to the liveout set for the function.
2180 // This isn't right, although it's probably harmless on x86; liveouts
2181 // should be computed from returns not tail calls. Consider a void
2182 // function making a tail call to a function returning int.
2183 return DAG.getNode(X86ISD::TC_RETURN, dl,
2184 NodeTys, &Ops[0], Ops.size());
2187 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2188 InFlag = Chain.getValue(1);
2190 // Create the CALLSEQ_END node.
2191 unsigned NumBytesForCalleeToPush;
2192 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2193 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2194 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2195 // If this is a call to a struct-return function, the callee
2196 // pops the hidden struct pointer, so we have to push it back.
2197 // This is common for Darwin/X86, Linux & Mingw32 targets.
2198 NumBytesForCalleeToPush = 4;
2200 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2202 // Returns a flag for retval copy to use.
2204 Chain = DAG.getCALLSEQ_END(Chain,
2205 DAG.getIntPtrConstant(NumBytes, true),
2206 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2209 InFlag = Chain.getValue(1);
2212 // Handle result values, copying them out of physregs into vregs that we
2214 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2215 Ins, dl, DAG, InVals);
2219 //===----------------------------------------------------------------------===//
2220 // Fast Calling Convention (tail call) implementation
2221 //===----------------------------------------------------------------------===//
2223 // Like std call, callee cleans arguments, convention except that ECX is
2224 // reserved for storing the tail called function address. Only 2 registers are
2225 // free for argument passing (inreg). Tail call optimization is performed
2227 // * tailcallopt is enabled
2228 // * caller/callee are fastcc
2229 // On X86_64 architecture with GOT-style position independent code only local
2230 // (within module) calls are supported at the moment.
2231 // To keep the stack aligned according to platform abi the function
2232 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2233 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2234 // If a tail called function callee has more arguments than the caller the
2235 // caller needs to make sure that there is room to move the RETADDR to. This is
2236 // achieved by reserving an area the size of the argument delta right after the
2237 // original REtADDR, but before the saved framepointer or the spilled registers
2238 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2250 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2251 /// for a 16 byte align requirement.
2253 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2254 SelectionDAG& DAG) const {
2255 MachineFunction &MF = DAG.getMachineFunction();
2256 const TargetMachine &TM = MF.getTarget();
2257 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2258 unsigned StackAlignment = TFI.getStackAlignment();
2259 uint64_t AlignMask = StackAlignment - 1;
2260 int64_t Offset = StackSize;
2261 uint64_t SlotSize = TD->getPointerSize();
2262 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2263 // Number smaller than 12 so just add the difference.
2264 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2266 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2267 Offset = ((~AlignMask) & Offset) + StackAlignment +
2268 (StackAlignment-SlotSize);
2273 /// MatchingStackOffset - Return true if the given stack call argument is
2274 /// already available in the same position (relatively) of the caller's
2275 /// incoming argument stack.
2277 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2278 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2279 const X86InstrInfo *TII) {
2280 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2282 if (Arg.getOpcode() == ISD::CopyFromReg) {
2283 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2284 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2286 MachineInstr *Def = MRI->getVRegDef(VR);
2289 if (!Flags.isByVal()) {
2290 if (!TII->isLoadFromStackSlot(Def, FI))
2293 unsigned Opcode = Def->getOpcode();
2294 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2295 Def->getOperand(1).isFI()) {
2296 FI = Def->getOperand(1).getIndex();
2297 Bytes = Flags.getByValSize();
2301 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2302 if (Flags.isByVal())
2303 // ByVal argument is passed in as a pointer but it's now being
2304 // dereferenced. e.g.
2305 // define @foo(%struct.X* %A) {
2306 // tail call @bar(%struct.X* byval %A)
2309 SDValue Ptr = Ld->getBasePtr();
2310 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2313 FI = FINode->getIndex();
2317 assert(FI != INT_MAX);
2318 if (!MFI->isFixedObjectIndex(FI))
2320 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2323 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2324 /// for tail call optimization. Targets which want to do tail call
2325 /// optimization should implement this function.
2327 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2328 CallingConv::ID CalleeCC,
2330 bool isCalleeStructRet,
2331 bool isCallerStructRet,
2332 const SmallVectorImpl<ISD::OutputArg> &Outs,
2333 const SmallVectorImpl<SDValue> &OutVals,
2334 const SmallVectorImpl<ISD::InputArg> &Ins,
2335 SelectionDAG& DAG) const {
2336 if (!IsTailCallConvention(CalleeCC) &&
2337 CalleeCC != CallingConv::C)
2340 // If -tailcallopt is specified, make fastcc functions tail-callable.
2341 const MachineFunction &MF = DAG.getMachineFunction();
2342 const Function *CallerF = DAG.getMachineFunction().getFunction();
2343 CallingConv::ID CallerCC = CallerF->getCallingConv();
2344 bool CCMatch = CallerCC == CalleeCC;
2346 if (GuaranteedTailCallOpt) {
2347 if (IsTailCallConvention(CalleeCC) && CCMatch)
2352 // Look for obvious safe cases to perform tail call optimization that do not
2353 // require ABI changes. This is what gcc calls sibcall.
2355 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2356 // emit a special epilogue.
2357 if (RegInfo->needsStackRealignment(MF))
2360 // Do not sibcall optimize vararg calls unless the call site is not passing
2362 if (isVarArg && !Outs.empty())
2365 // Also avoid sibcall optimization if either caller or callee uses struct
2366 // return semantics.
2367 if (isCalleeStructRet || isCallerStructRet)
2370 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2371 // Therefore if it's not used by the call it is not safe to optimize this into
2373 bool Unused = false;
2374 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2381 SmallVector<CCValAssign, 16> RVLocs;
2382 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2383 RVLocs, *DAG.getContext());
2384 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2385 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2386 CCValAssign &VA = RVLocs[i];
2387 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2392 // If the calling conventions do not match, then we'd better make sure the
2393 // results are returned in the same way as what the caller expects.
2395 SmallVector<CCValAssign, 16> RVLocs1;
2396 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2397 RVLocs1, *DAG.getContext());
2398 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2400 SmallVector<CCValAssign, 16> RVLocs2;
2401 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2402 RVLocs2, *DAG.getContext());
2403 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2405 if (RVLocs1.size() != RVLocs2.size())
2407 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2408 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2410 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2412 if (RVLocs1[i].isRegLoc()) {
2413 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2416 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2422 // If the callee takes no arguments then go on to check the results of the
2424 if (!Outs.empty()) {
2425 // Check if stack adjustment is needed. For now, do not do this if any
2426 // argument is passed on the stack.
2427 SmallVector<CCValAssign, 16> ArgLocs;
2428 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2429 ArgLocs, *DAG.getContext());
2430 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2431 if (CCInfo.getNextStackOffset()) {
2432 MachineFunction &MF = DAG.getMachineFunction();
2433 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2435 if (Subtarget->isTargetWin64())
2436 // Win64 ABI has additional complications.
2439 // Check if the arguments are already laid out in the right way as
2440 // the caller's fixed stack objects.
2441 MachineFrameInfo *MFI = MF.getFrameInfo();
2442 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2443 const X86InstrInfo *TII =
2444 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2445 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2446 CCValAssign &VA = ArgLocs[i];
2447 SDValue Arg = OutVals[i];
2448 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2449 if (VA.getLocInfo() == CCValAssign::Indirect)
2451 if (!VA.isRegLoc()) {
2452 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2459 // If the tailcall address may be in a register, then make sure it's
2460 // possible to register allocate for it. In 32-bit, the call address can
2461 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2462 // callee-saved registers are restored. These happen to be the same
2463 // registers used to pass 'inreg' arguments so watch out for those.
2464 if (!Subtarget->is64Bit() &&
2465 !isa<GlobalAddressSDNode>(Callee) &&
2466 !isa<ExternalSymbolSDNode>(Callee)) {
2467 unsigned NumInRegs = 0;
2468 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2469 CCValAssign &VA = ArgLocs[i];
2472 unsigned Reg = VA.getLocReg();
2475 case X86::EAX: case X86::EDX: case X86::ECX:
2476 if (++NumInRegs == 3)
2488 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2489 return X86::createFastISel(funcInfo);
2493 //===----------------------------------------------------------------------===//
2494 // Other Lowering Hooks
2495 //===----------------------------------------------------------------------===//
2498 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2499 MachineFunction &MF = DAG.getMachineFunction();
2500 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2501 int ReturnAddrIndex = FuncInfo->getRAIndex();
2503 if (ReturnAddrIndex == 0) {
2504 // Set up a frame object for the return address.
2505 uint64_t SlotSize = TD->getPointerSize();
2506 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2508 FuncInfo->setRAIndex(ReturnAddrIndex);
2511 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2515 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2516 bool hasSymbolicDisplacement) {
2517 // Offset should fit into 32 bit immediate field.
2518 if (!isInt<32>(Offset))
2521 // If we don't have a symbolic displacement - we don't have any extra
2523 if (!hasSymbolicDisplacement)
2526 // FIXME: Some tweaks might be needed for medium code model.
2527 if (M != CodeModel::Small && M != CodeModel::Kernel)
2530 // For small code model we assume that latest object is 16MB before end of 31
2531 // bits boundary. We may also accept pretty large negative constants knowing
2532 // that all objects are in the positive half of address space.
2533 if (M == CodeModel::Small && Offset < 16*1024*1024)
2536 // For kernel code model we know that all object resist in the negative half
2537 // of 32bits address space. We may not accept negative offsets, since they may
2538 // be just off and we may accept pretty large positive ones.
2539 if (M == CodeModel::Kernel && Offset > 0)
2545 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2546 /// specific condition code, returning the condition code and the LHS/RHS of the
2547 /// comparison to make.
2548 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2549 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2551 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2552 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2553 // X > -1 -> X == 0, jump !sign.
2554 RHS = DAG.getConstant(0, RHS.getValueType());
2555 return X86::COND_NS;
2556 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2557 // X < 0 -> X == 0, jump on sign.
2559 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2561 RHS = DAG.getConstant(0, RHS.getValueType());
2562 return X86::COND_LE;
2566 switch (SetCCOpcode) {
2567 default: llvm_unreachable("Invalid integer condition!");
2568 case ISD::SETEQ: return X86::COND_E;
2569 case ISD::SETGT: return X86::COND_G;
2570 case ISD::SETGE: return X86::COND_GE;
2571 case ISD::SETLT: return X86::COND_L;
2572 case ISD::SETLE: return X86::COND_LE;
2573 case ISD::SETNE: return X86::COND_NE;
2574 case ISD::SETULT: return X86::COND_B;
2575 case ISD::SETUGT: return X86::COND_A;
2576 case ISD::SETULE: return X86::COND_BE;
2577 case ISD::SETUGE: return X86::COND_AE;
2581 // First determine if it is required or is profitable to flip the operands.
2583 // If LHS is a foldable load, but RHS is not, flip the condition.
2584 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2585 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2586 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2587 std::swap(LHS, RHS);
2590 switch (SetCCOpcode) {
2596 std::swap(LHS, RHS);
2600 // On a floating point condition, the flags are set as follows:
2602 // 0 | 0 | 0 | X > Y
2603 // 0 | 0 | 1 | X < Y
2604 // 1 | 0 | 0 | X == Y
2605 // 1 | 1 | 1 | unordered
2606 switch (SetCCOpcode) {
2607 default: llvm_unreachable("Condcode should be pre-legalized away");
2609 case ISD::SETEQ: return X86::COND_E;
2610 case ISD::SETOLT: // flipped
2612 case ISD::SETGT: return X86::COND_A;
2613 case ISD::SETOLE: // flipped
2615 case ISD::SETGE: return X86::COND_AE;
2616 case ISD::SETUGT: // flipped
2618 case ISD::SETLT: return X86::COND_B;
2619 case ISD::SETUGE: // flipped
2621 case ISD::SETLE: return X86::COND_BE;
2623 case ISD::SETNE: return X86::COND_NE;
2624 case ISD::SETUO: return X86::COND_P;
2625 case ISD::SETO: return X86::COND_NP;
2627 case ISD::SETUNE: return X86::COND_INVALID;
2631 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2632 /// code. Current x86 isa includes the following FP cmov instructions:
2633 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2634 static bool hasFPCMov(unsigned X86CC) {
2650 /// isFPImmLegal - Returns true if the target can instruction select the
2651 /// specified FP immediate natively. If false, the legalizer will
2652 /// materialize the FP immediate as a load from a constant pool.
2653 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2654 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2655 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2661 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2662 /// the specified range (L, H].
2663 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2664 return (Val < 0) || (Val >= Low && Val < Hi);
2667 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2668 /// specified value.
2669 static bool isUndefOrEqual(int Val, int CmpVal) {
2670 if (Val < 0 || Val == CmpVal)
2675 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2676 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2677 /// the second operand.
2678 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2679 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2680 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2681 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2682 return (Mask[0] < 2 && Mask[1] < 2);
2686 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2687 SmallVector<int, 8> M;
2689 return ::isPSHUFDMask(M, N->getValueType(0));
2692 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2693 /// is suitable for input to PSHUFHW.
2694 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2695 if (VT != MVT::v8i16)
2698 // Lower quadword copied in order or undef.
2699 for (int i = 0; i != 4; ++i)
2700 if (Mask[i] >= 0 && Mask[i] != i)
2703 // Upper quadword shuffled.
2704 for (int i = 4; i != 8; ++i)
2705 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2711 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2712 SmallVector<int, 8> M;
2714 return ::isPSHUFHWMask(M, N->getValueType(0));
2717 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2718 /// is suitable for input to PSHUFLW.
2719 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2720 if (VT != MVT::v8i16)
2723 // Upper quadword copied in order.
2724 for (int i = 4; i != 8; ++i)
2725 if (Mask[i] >= 0 && Mask[i] != i)
2728 // Lower quadword shuffled.
2729 for (int i = 0; i != 4; ++i)
2736 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2737 SmallVector<int, 8> M;
2739 return ::isPSHUFLWMask(M, N->getValueType(0));
2742 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2743 /// is suitable for input to PALIGNR.
2744 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2746 int i, e = VT.getVectorNumElements();
2748 // Do not handle v2i64 / v2f64 shuffles with palignr.
2749 if (e < 4 || !hasSSSE3)
2752 for (i = 0; i != e; ++i)
2756 // All undef, not a palignr.
2760 // Determine if it's ok to perform a palignr with only the LHS, since we
2761 // don't have access to the actual shuffle elements to see if RHS is undef.
2762 bool Unary = Mask[i] < (int)e;
2763 bool NeedsUnary = false;
2765 int s = Mask[i] - i;
2767 // Check the rest of the elements to see if they are consecutive.
2768 for (++i; i != e; ++i) {
2773 Unary = Unary && (m < (int)e);
2774 NeedsUnary = NeedsUnary || (m < s);
2776 if (NeedsUnary && !Unary)
2778 if (Unary && m != ((s+i) & (e-1)))
2780 if (!Unary && m != (s+i))
2786 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2787 SmallVector<int, 8> M;
2789 return ::isPALIGNRMask(M, N->getValueType(0), true);
2792 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2793 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2794 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2795 int NumElems = VT.getVectorNumElements();
2796 if (NumElems != 2 && NumElems != 4)
2799 int Half = NumElems / 2;
2800 for (int i = 0; i < Half; ++i)
2801 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2803 for (int i = Half; i < NumElems; ++i)
2804 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2810 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2811 SmallVector<int, 8> M;
2813 return ::isSHUFPMask(M, N->getValueType(0));
2816 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2817 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2818 /// half elements to come from vector 1 (which would equal the dest.) and
2819 /// the upper half to come from vector 2.
2820 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2821 int NumElems = VT.getVectorNumElements();
2823 if (NumElems != 2 && NumElems != 4)
2826 int Half = NumElems / 2;
2827 for (int i = 0; i < Half; ++i)
2828 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2830 for (int i = Half; i < NumElems; ++i)
2831 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2836 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2837 SmallVector<int, 8> M;
2839 return isCommutedSHUFPMask(M, N->getValueType(0));
2842 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2843 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2844 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2845 if (N->getValueType(0).getVectorNumElements() != 4)
2848 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2849 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2850 isUndefOrEqual(N->getMaskElt(1), 7) &&
2851 isUndefOrEqual(N->getMaskElt(2), 2) &&
2852 isUndefOrEqual(N->getMaskElt(3), 3);
2855 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2856 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2858 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2859 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2864 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2865 isUndefOrEqual(N->getMaskElt(1), 3) &&
2866 isUndefOrEqual(N->getMaskElt(2), 2) &&
2867 isUndefOrEqual(N->getMaskElt(3), 3);
2870 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2871 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2872 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2873 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2875 if (NumElems != 2 && NumElems != 4)
2878 for (unsigned i = 0; i < NumElems/2; ++i)
2879 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2882 for (unsigned i = NumElems/2; i < NumElems; ++i)
2883 if (!isUndefOrEqual(N->getMaskElt(i), i))
2889 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2890 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2891 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2892 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2894 if (NumElems != 2 && NumElems != 4)
2897 for (unsigned i = 0; i < NumElems/2; ++i)
2898 if (!isUndefOrEqual(N->getMaskElt(i), i))
2901 for (unsigned i = 0; i < NumElems/2; ++i)
2902 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2908 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2909 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2910 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2911 bool V2IsSplat = false) {
2912 int NumElts = VT.getVectorNumElements();
2913 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2916 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2918 int BitI1 = Mask[i+1];
2919 if (!isUndefOrEqual(BitI, j))
2922 if (!isUndefOrEqual(BitI1, NumElts))
2925 if (!isUndefOrEqual(BitI1, j + NumElts))
2932 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2933 SmallVector<int, 8> M;
2935 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2938 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2939 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2940 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2941 bool V2IsSplat = false) {
2942 int NumElts = VT.getVectorNumElements();
2943 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2946 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2948 int BitI1 = Mask[i+1];
2949 if (!isUndefOrEqual(BitI, j + NumElts/2))
2952 if (isUndefOrEqual(BitI1, NumElts))
2955 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2962 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2963 SmallVector<int, 8> M;
2965 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2968 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2969 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2971 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2972 int NumElems = VT.getVectorNumElements();
2973 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2976 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2978 int BitI1 = Mask[i+1];
2979 if (!isUndefOrEqual(BitI, j))
2981 if (!isUndefOrEqual(BitI1, j))
2987 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2988 SmallVector<int, 8> M;
2990 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2993 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2994 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2996 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2997 int NumElems = VT.getVectorNumElements();
2998 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3001 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3003 int BitI1 = Mask[i+1];
3004 if (!isUndefOrEqual(BitI, j))
3006 if (!isUndefOrEqual(BitI1, j))
3012 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3013 SmallVector<int, 8> M;
3015 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3018 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3019 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3020 /// MOVSD, and MOVD, i.e. setting the lowest element.
3021 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3022 if (VT.getVectorElementType().getSizeInBits() < 32)
3025 int NumElts = VT.getVectorNumElements();
3027 if (!isUndefOrEqual(Mask[0], NumElts))
3030 for (int i = 1; i < NumElts; ++i)
3031 if (!isUndefOrEqual(Mask[i], i))
3037 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3038 SmallVector<int, 8> M;
3040 return ::isMOVLMask(M, N->getValueType(0));
3043 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3044 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3045 /// element of vector 2 and the other elements to come from vector 1 in order.
3046 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3047 bool V2IsSplat = false, bool V2IsUndef = false) {
3048 int NumOps = VT.getVectorNumElements();
3049 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3052 if (!isUndefOrEqual(Mask[0], 0))
3055 for (int i = 1; i < NumOps; ++i)
3056 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3057 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3058 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3064 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3065 bool V2IsUndef = false) {
3066 SmallVector<int, 8> M;
3068 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3071 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3072 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3073 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3074 if (N->getValueType(0).getVectorNumElements() != 4)
3077 // Expect 1, 1, 3, 3
3078 for (unsigned i = 0; i < 2; ++i) {
3079 int Elt = N->getMaskElt(i);
3080 if (Elt >= 0 && Elt != 1)
3085 for (unsigned i = 2; i < 4; ++i) {
3086 int Elt = N->getMaskElt(i);
3087 if (Elt >= 0 && Elt != 3)
3092 // Don't use movshdup if it can be done with a shufps.
3093 // FIXME: verify that matching u, u, 3, 3 is what we want.
3097 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3098 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3099 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3100 if (N->getValueType(0).getVectorNumElements() != 4)
3103 // Expect 0, 0, 2, 2
3104 for (unsigned i = 0; i < 2; ++i)
3105 if (N->getMaskElt(i) > 0)
3109 for (unsigned i = 2; i < 4; ++i) {
3110 int Elt = N->getMaskElt(i);
3111 if (Elt >= 0 && Elt != 2)
3116 // Don't use movsldup if it can be done with a shufps.
3120 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3121 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3122 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3123 int e = N->getValueType(0).getVectorNumElements() / 2;
3125 for (int i = 0; i < e; ++i)
3126 if (!isUndefOrEqual(N->getMaskElt(i), i))
3128 for (int i = 0; i < e; ++i)
3129 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3134 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3135 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3136 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3138 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3140 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3142 for (int i = 0; i < NumOperands; ++i) {
3143 int Val = SVOp->getMaskElt(NumOperands-i-1);
3144 if (Val < 0) Val = 0;
3145 if (Val >= NumOperands) Val -= NumOperands;
3147 if (i != NumOperands - 1)
3153 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3154 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3155 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3158 // 8 nodes, but we only care about the last 4.
3159 for (unsigned i = 7; i >= 4; --i) {
3160 int Val = SVOp->getMaskElt(i);
3169 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3170 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3171 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3174 // 8 nodes, but we only care about the first 4.
3175 for (int i = 3; i >= 0; --i) {
3176 int Val = SVOp->getMaskElt(i);
3185 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3186 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3187 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3188 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3189 EVT VVT = N->getValueType(0);
3190 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3194 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3195 Val = SVOp->getMaskElt(i);
3199 return (Val - i) * EltSize;
3202 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3204 bool X86::isZeroNode(SDValue Elt) {
3205 return ((isa<ConstantSDNode>(Elt) &&
3206 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3207 (isa<ConstantFPSDNode>(Elt) &&
3208 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3211 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3212 /// their permute mask.
3213 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3214 SelectionDAG &DAG) {
3215 EVT VT = SVOp->getValueType(0);
3216 unsigned NumElems = VT.getVectorNumElements();
3217 SmallVector<int, 8> MaskVec;
3219 for (unsigned i = 0; i != NumElems; ++i) {
3220 int idx = SVOp->getMaskElt(i);
3222 MaskVec.push_back(idx);
3223 else if (idx < (int)NumElems)
3224 MaskVec.push_back(idx + NumElems);
3226 MaskVec.push_back(idx - NumElems);
3228 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3229 SVOp->getOperand(0), &MaskVec[0]);
3232 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3233 /// the two vector operands have swapped position.
3234 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3235 unsigned NumElems = VT.getVectorNumElements();
3236 for (unsigned i = 0; i != NumElems; ++i) {
3240 else if (idx < (int)NumElems)
3241 Mask[i] = idx + NumElems;
3243 Mask[i] = idx - NumElems;
3247 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3248 /// match movhlps. The lower half elements should come from upper half of
3249 /// V1 (and in order), and the upper half elements should come from the upper
3250 /// half of V2 (and in order).
3251 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3252 if (Op->getValueType(0).getVectorNumElements() != 4)
3254 for (unsigned i = 0, e = 2; i != e; ++i)
3255 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3257 for (unsigned i = 2; i != 4; ++i)
3258 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3263 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3264 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3266 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3267 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3269 N = N->getOperand(0).getNode();
3270 if (!ISD::isNON_EXTLoad(N))
3273 *LD = cast<LoadSDNode>(N);
3277 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3278 /// match movlp{s|d}. The lower half elements should come from lower half of
3279 /// V1 (and in order), and the upper half elements should come from the upper
3280 /// half of V2 (and in order). And since V1 will become the source of the
3281 /// MOVLP, it must be either a vector load or a scalar load to vector.
3282 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3283 ShuffleVectorSDNode *Op) {
3284 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3286 // Is V2 is a vector load, don't do this transformation. We will try to use
3287 // load folding shufps op.
3288 if (ISD::isNON_EXTLoad(V2))
3291 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3293 if (NumElems != 2 && NumElems != 4)
3295 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3296 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3298 for (unsigned i = NumElems/2; i != NumElems; ++i)
3299 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3304 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3306 static bool isSplatVector(SDNode *N) {
3307 if (N->getOpcode() != ISD::BUILD_VECTOR)
3310 SDValue SplatValue = N->getOperand(0);
3311 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3312 if (N->getOperand(i) != SplatValue)
3317 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3318 /// to an zero vector.
3319 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3320 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3321 SDValue V1 = N->getOperand(0);
3322 SDValue V2 = N->getOperand(1);
3323 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3324 for (unsigned i = 0; i != NumElems; ++i) {
3325 int Idx = N->getMaskElt(i);
3326 if (Idx >= (int)NumElems) {
3327 unsigned Opc = V2.getOpcode();
3328 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3330 if (Opc != ISD::BUILD_VECTOR ||
3331 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3333 } else if (Idx >= 0) {
3334 unsigned Opc = V1.getOpcode();
3335 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3337 if (Opc != ISD::BUILD_VECTOR ||
3338 !X86::isZeroNode(V1.getOperand(Idx)))
3345 /// getZeroVector - Returns a vector of specified type with all zero elements.
3347 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3349 assert(VT.isVector() && "Expected a vector type");
3351 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3352 // type. This ensures they get CSE'd.
3354 if (VT.getSizeInBits() == 64) { // MMX
3355 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3356 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3357 } else if (HasSSE2) { // SSE2
3358 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3359 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3361 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3362 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3364 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3367 /// getOnesVector - Returns a vector of specified type with all bits set.
3369 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3370 assert(VT.isVector() && "Expected a vector type");
3372 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3373 // type. This ensures they get CSE'd.
3374 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3376 if (VT.getSizeInBits() == 64) // MMX
3377 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3379 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3380 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3384 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3385 /// that point to V2 points to its first element.
3386 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3387 EVT VT = SVOp->getValueType(0);
3388 unsigned NumElems = VT.getVectorNumElements();
3390 bool Changed = false;
3391 SmallVector<int, 8> MaskVec;
3392 SVOp->getMask(MaskVec);
3394 for (unsigned i = 0; i != NumElems; ++i) {
3395 if (MaskVec[i] > (int)NumElems) {
3396 MaskVec[i] = NumElems;
3401 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3402 SVOp->getOperand(1), &MaskVec[0]);
3403 return SDValue(SVOp, 0);
3406 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3407 /// operation of specified width.
3408 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3410 unsigned NumElems = VT.getVectorNumElements();
3411 SmallVector<int, 8> Mask;
3412 Mask.push_back(NumElems);
3413 for (unsigned i = 1; i != NumElems; ++i)
3415 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3418 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3419 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3421 unsigned NumElems = VT.getVectorNumElements();
3422 SmallVector<int, 8> Mask;
3423 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3425 Mask.push_back(i + NumElems);
3427 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3430 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3431 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3433 unsigned NumElems = VT.getVectorNumElements();
3434 unsigned Half = NumElems/2;
3435 SmallVector<int, 8> Mask;
3436 for (unsigned i = 0; i != Half; ++i) {
3437 Mask.push_back(i + Half);
3438 Mask.push_back(i + NumElems + Half);
3440 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3443 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3444 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3446 if (SV->getValueType(0).getVectorNumElements() <= 4)
3447 return SDValue(SV, 0);
3449 EVT PVT = MVT::v4f32;
3450 EVT VT = SV->getValueType(0);
3451 DebugLoc dl = SV->getDebugLoc();
3452 SDValue V1 = SV->getOperand(0);
3453 int NumElems = VT.getVectorNumElements();
3454 int EltNo = SV->getSplatIndex();
3456 // unpack elements to the correct location
3457 while (NumElems > 4) {
3458 if (EltNo < NumElems/2) {
3459 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3461 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3462 EltNo -= NumElems/2;
3467 // Perform the splat.
3468 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3469 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3470 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3471 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3474 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3475 /// vector of zero or undef vector. This produces a shuffle where the low
3476 /// element of V2 is swizzled into the zero/undef vector, landing at element
3477 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3478 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3479 bool isZero, bool HasSSE2,
3480 SelectionDAG &DAG) {
3481 EVT VT = V2.getValueType();
3483 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3484 unsigned NumElems = VT.getVectorNumElements();
3485 SmallVector<int, 16> MaskVec;
3486 for (unsigned i = 0; i != NumElems; ++i)
3487 // If this is the insertion idx, put the low elt of V2 here.
3488 MaskVec.push_back(i == Idx ? NumElems : i);
3489 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3492 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3493 /// a shuffle that is zero.
3495 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3496 bool Low, SelectionDAG &DAG) {
3497 unsigned NumZeros = 0;
3498 for (int i = 0; i < NumElems; ++i) {
3499 unsigned Index = Low ? i : NumElems-i-1;
3500 int Idx = SVOp->getMaskElt(Index);
3505 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3506 if (Elt.getNode() && X86::isZeroNode(Elt))
3514 /// isVectorShift - Returns true if the shuffle can be implemented as a
3515 /// logical left or right shift of a vector.
3516 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3517 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3518 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3519 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3522 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3525 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3529 bool SeenV1 = false;
3530 bool SeenV2 = false;
3531 for (unsigned i = NumZeros; i < NumElems; ++i) {
3532 unsigned Val = isLeft ? (i - NumZeros) : i;
3533 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3536 unsigned Idx = (unsigned) Idx_;
3546 if (SeenV1 && SeenV2)
3549 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3555 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3557 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3558 unsigned NumNonZero, unsigned NumZero,
3560 const TargetLowering &TLI) {
3564 DebugLoc dl = Op.getDebugLoc();
3567 for (unsigned i = 0; i < 16; ++i) {
3568 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3569 if (ThisIsNonZero && First) {
3571 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3573 V = DAG.getUNDEF(MVT::v8i16);
3578 SDValue ThisElt(0, 0), LastElt(0, 0);
3579 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3580 if (LastIsNonZero) {
3581 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3582 MVT::i16, Op.getOperand(i-1));
3584 if (ThisIsNonZero) {
3585 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3586 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3587 ThisElt, DAG.getConstant(8, MVT::i8));
3589 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3593 if (ThisElt.getNode())
3594 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3595 DAG.getIntPtrConstant(i/2));
3599 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3602 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3604 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3605 unsigned NumNonZero, unsigned NumZero,
3607 const TargetLowering &TLI) {
3611 DebugLoc dl = Op.getDebugLoc();
3614 for (unsigned i = 0; i < 8; ++i) {
3615 bool isNonZero = (NonZeros & (1 << i)) != 0;
3619 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3621 V = DAG.getUNDEF(MVT::v8i16);
3624 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3625 MVT::v8i16, V, Op.getOperand(i),
3626 DAG.getIntPtrConstant(i));
3633 /// getVShift - Return a vector logical shift node.
3635 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3636 unsigned NumBits, SelectionDAG &DAG,
3637 const TargetLowering &TLI, DebugLoc dl) {
3638 bool isMMX = VT.getSizeInBits() == 64;
3639 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3640 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3641 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3642 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3643 DAG.getNode(Opc, dl, ShVT, SrcOp,
3644 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3648 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3649 SelectionDAG &DAG) const {
3651 // Check if the scalar load can be widened into a vector load. And if
3652 // the address is "base + cst" see if the cst can be "absorbed" into
3653 // the shuffle mask.
3654 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3655 SDValue Ptr = LD->getBasePtr();
3656 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3658 EVT PVT = LD->getValueType(0);
3659 if (PVT != MVT::i32 && PVT != MVT::f32)
3664 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3665 FI = FINode->getIndex();
3667 } else if (Ptr.getOpcode() == ISD::ADD &&
3668 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3669 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3670 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3671 Offset = Ptr.getConstantOperandVal(1);
3672 Ptr = Ptr.getOperand(0);
3677 SDValue Chain = LD->getChain();
3678 // Make sure the stack object alignment is at least 16.
3679 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3680 if (DAG.InferPtrAlignment(Ptr) < 16) {
3681 if (MFI->isFixedObjectIndex(FI)) {
3682 // Can't change the alignment. FIXME: It's possible to compute
3683 // the exact stack offset and reference FI + adjust offset instead.
3684 // If someone *really* cares about this. That's the way to implement it.
3687 MFI->setObjectAlignment(FI, 16);
3691 // (Offset % 16) must be multiple of 4. Then address is then
3692 // Ptr + (Offset & ~15).
3695 if ((Offset % 16) & 3)
3697 int64_t StartOffset = Offset & ~15;
3699 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3700 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3702 int EltNo = (Offset - StartOffset) >> 2;
3703 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3704 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3705 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3707 // Canonicalize it to a v4i32 shuffle.
3708 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3709 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3710 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3711 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3717 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3718 /// vector of type 'VT', see if the elements can be replaced by a single large
3719 /// load which has the same value as a build_vector whose operands are 'elts'.
3721 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3723 /// FIXME: we'd also like to handle the case where the last elements are zero
3724 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3725 /// There's even a handy isZeroNode for that purpose.
3726 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3727 DebugLoc &dl, SelectionDAG &DAG) {
3728 EVT EltVT = VT.getVectorElementType();
3729 unsigned NumElems = Elts.size();
3731 LoadSDNode *LDBase = NULL;
3732 unsigned LastLoadedElt = -1U;
3734 // For each element in the initializer, see if we've found a load or an undef.
3735 // If we don't find an initial load element, or later load elements are
3736 // non-consecutive, bail out.
3737 for (unsigned i = 0; i < NumElems; ++i) {
3738 SDValue Elt = Elts[i];
3740 if (!Elt.getNode() ||
3741 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3744 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3746 LDBase = cast<LoadSDNode>(Elt.getNode());
3750 if (Elt.getOpcode() == ISD::UNDEF)
3753 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3754 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3759 // If we have found an entire vector of loads and undefs, then return a large
3760 // load of the entire vector width starting at the base pointer. If we found
3761 // consecutive loads for the low half, generate a vzext_load node.
3762 if (LastLoadedElt == NumElems - 1) {
3763 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3764 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3765 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3766 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3767 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3768 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3769 LDBase->isVolatile(), LDBase->isNonTemporal(),
3770 LDBase->getAlignment());
3771 } else if (NumElems == 4 && LastLoadedElt == 1) {
3772 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3773 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3774 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3775 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3781 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3782 DebugLoc dl = Op.getDebugLoc();
3783 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3784 if (ISD::isBuildVectorAllZeros(Op.getNode())
3785 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3786 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3787 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3788 // eliminated on x86-32 hosts.
3789 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3792 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3793 return getOnesVector(Op.getValueType(), DAG, dl);
3794 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3797 EVT VT = Op.getValueType();
3798 EVT ExtVT = VT.getVectorElementType();
3799 unsigned EVTBits = ExtVT.getSizeInBits();
3801 unsigned NumElems = Op.getNumOperands();
3802 unsigned NumZero = 0;
3803 unsigned NumNonZero = 0;
3804 unsigned NonZeros = 0;
3805 bool IsAllConstants = true;
3806 SmallSet<SDValue, 8> Values;
3807 for (unsigned i = 0; i < NumElems; ++i) {
3808 SDValue Elt = Op.getOperand(i);
3809 if (Elt.getOpcode() == ISD::UNDEF)
3812 if (Elt.getOpcode() != ISD::Constant &&
3813 Elt.getOpcode() != ISD::ConstantFP)
3814 IsAllConstants = false;
3815 if (X86::isZeroNode(Elt))
3818 NonZeros |= (1 << i);
3823 if (NumNonZero == 0) {
3824 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3825 return DAG.getUNDEF(VT);
3828 // Special case for single non-zero, non-undef, element.
3829 if (NumNonZero == 1) {
3830 unsigned Idx = CountTrailingZeros_32(NonZeros);
3831 SDValue Item = Op.getOperand(Idx);
3833 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3834 // the value are obviously zero, truncate the value to i32 and do the
3835 // insertion that way. Only do this if the value is non-constant or if the
3836 // value is a constant being inserted into element 0. It is cheaper to do
3837 // a constant pool load than it is to do a movd + shuffle.
3838 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3839 (!IsAllConstants || Idx == 0)) {
3840 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3841 // Handle MMX and SSE both.
3842 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3843 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3845 // Truncate the value (which may itself be a constant) to i32, and
3846 // convert it to a vector with movd (S2V+shuffle to zero extend).
3847 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3848 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3849 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3850 Subtarget->hasSSE2(), DAG);
3852 // Now we have our 32-bit value zero extended in the low element of
3853 // a vector. If Idx != 0, swizzle it into place.
3855 SmallVector<int, 4> Mask;
3856 Mask.push_back(Idx);
3857 for (unsigned i = 1; i != VecElts; ++i)
3859 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3860 DAG.getUNDEF(Item.getValueType()),
3863 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3867 // If we have a constant or non-constant insertion into the low element of
3868 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3869 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3870 // depending on what the source datatype is.
3873 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3874 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3875 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3876 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3877 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3878 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3880 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3881 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3882 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3883 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3884 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3885 Subtarget->hasSSE2(), DAG);
3886 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3890 // Is it a vector logical left shift?
3891 if (NumElems == 2 && Idx == 1 &&
3892 X86::isZeroNode(Op.getOperand(0)) &&
3893 !X86::isZeroNode(Op.getOperand(1))) {
3894 unsigned NumBits = VT.getSizeInBits();
3895 return getVShift(true, VT,
3896 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3897 VT, Op.getOperand(1)),
3898 NumBits/2, DAG, *this, dl);
3901 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3904 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3905 // is a non-constant being inserted into an element other than the low one,
3906 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3907 // movd/movss) to move this into the low element, then shuffle it into
3909 if (EVTBits == 32) {
3910 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3912 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3913 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3914 Subtarget->hasSSE2(), DAG);
3915 SmallVector<int, 8> MaskVec;
3916 for (unsigned i = 0; i < NumElems; i++)
3917 MaskVec.push_back(i == Idx ? 0 : 1);
3918 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3922 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3923 if (Values.size() == 1) {
3924 if (EVTBits == 32) {
3925 // Instead of a shuffle like this:
3926 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3927 // Check if it's possible to issue this instead.
3928 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3929 unsigned Idx = CountTrailingZeros_32(NonZeros);
3930 SDValue Item = Op.getOperand(Idx);
3931 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3932 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3937 // A vector full of immediates; various special cases are already
3938 // handled, so this is best done with a single constant-pool load.
3942 // Let legalizer expand 2-wide build_vectors.
3943 if (EVTBits == 64) {
3944 if (NumNonZero == 1) {
3945 // One half is zero or undef.
3946 unsigned Idx = CountTrailingZeros_32(NonZeros);
3947 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3948 Op.getOperand(Idx));
3949 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3950 Subtarget->hasSSE2(), DAG);
3955 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3956 if (EVTBits == 8 && NumElems == 16) {
3957 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3959 if (V.getNode()) return V;
3962 if (EVTBits == 16 && NumElems == 8) {
3963 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3965 if (V.getNode()) return V;
3968 // If element VT is == 32 bits, turn it into a number of shuffles.
3969 SmallVector<SDValue, 8> V;
3971 if (NumElems == 4 && NumZero > 0) {
3972 for (unsigned i = 0; i < 4; ++i) {
3973 bool isZero = !(NonZeros & (1 << i));
3975 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3977 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3980 for (unsigned i = 0; i < 2; ++i) {
3981 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3984 V[i] = V[i*2]; // Must be a zero vector.
3987 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3990 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3993 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3998 SmallVector<int, 8> MaskVec;
3999 bool Reverse = (NonZeros & 0x3) == 2;
4000 for (unsigned i = 0; i < 2; ++i)
4001 MaskVec.push_back(Reverse ? 1-i : i);
4002 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4003 for (unsigned i = 0; i < 2; ++i)
4004 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4005 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4008 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4009 // Check for a build vector of consecutive loads.
4010 for (unsigned i = 0; i < NumElems; ++i)
4011 V[i] = Op.getOperand(i);
4013 // Check for elements which are consecutive loads.
4014 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4018 // For SSE 4.1, use inserts into undef.
4019 if (getSubtarget()->hasSSE41()) {
4020 V[0] = DAG.getUNDEF(VT);
4021 for (unsigned i = 0; i < NumElems; ++i)
4022 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4023 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4024 Op.getOperand(i), DAG.getIntPtrConstant(i));
4028 // Otherwise, expand into a number of unpckl*
4030 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4031 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4032 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4033 for (unsigned i = 0; i < NumElems; ++i)
4034 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4036 while (NumElems != 0) {
4037 for (unsigned i = 0; i < NumElems; ++i)
4038 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4047 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4048 // We support concatenate two MMX registers and place them in a MMX
4049 // register. This is better than doing a stack convert.
4050 DebugLoc dl = Op.getDebugLoc();
4051 EVT ResVT = Op.getValueType();
4052 assert(Op.getNumOperands() == 2);
4053 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4054 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4056 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4057 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4058 InVec = Op.getOperand(1);
4059 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4060 unsigned NumElts = ResVT.getVectorNumElements();
4061 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4062 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4063 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4065 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4066 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4067 Mask[0] = 0; Mask[1] = 2;
4068 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4070 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4073 // v8i16 shuffles - Prefer shuffles in the following order:
4074 // 1. [all] pshuflw, pshufhw, optional move
4075 // 2. [ssse3] 1 x pshufb
4076 // 3. [ssse3] 2 x pshufb + 1 x por
4077 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4079 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4081 const X86TargetLowering &TLI) {
4082 SDValue V1 = SVOp->getOperand(0);
4083 SDValue V2 = SVOp->getOperand(1);
4084 DebugLoc dl = SVOp->getDebugLoc();
4085 SmallVector<int, 8> MaskVals;
4087 // Determine if more than 1 of the words in each of the low and high quadwords
4088 // of the result come from the same quadword of one of the two inputs. Undef
4089 // mask values count as coming from any quadword, for better codegen.
4090 SmallVector<unsigned, 4> LoQuad(4);
4091 SmallVector<unsigned, 4> HiQuad(4);
4092 BitVector InputQuads(4);
4093 for (unsigned i = 0; i < 8; ++i) {
4094 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4095 int EltIdx = SVOp->getMaskElt(i);
4096 MaskVals.push_back(EltIdx);
4105 InputQuads.set(EltIdx / 4);
4108 int BestLoQuad = -1;
4109 unsigned MaxQuad = 1;
4110 for (unsigned i = 0; i < 4; ++i) {
4111 if (LoQuad[i] > MaxQuad) {
4113 MaxQuad = LoQuad[i];
4117 int BestHiQuad = -1;
4119 for (unsigned i = 0; i < 4; ++i) {
4120 if (HiQuad[i] > MaxQuad) {
4122 MaxQuad = HiQuad[i];
4126 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4127 // of the two input vectors, shuffle them into one input vector so only a
4128 // single pshufb instruction is necessary. If There are more than 2 input
4129 // quads, disable the next transformation since it does not help SSSE3.
4130 bool V1Used = InputQuads[0] || InputQuads[1];
4131 bool V2Used = InputQuads[2] || InputQuads[3];
4132 if (TLI.getSubtarget()->hasSSSE3()) {
4133 if (InputQuads.count() == 2 && V1Used && V2Used) {
4134 BestLoQuad = InputQuads.find_first();
4135 BestHiQuad = InputQuads.find_next(BestLoQuad);
4137 if (InputQuads.count() > 2) {
4143 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4144 // the shuffle mask. If a quad is scored as -1, that means that it contains
4145 // words from all 4 input quadwords.
4147 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4148 SmallVector<int, 8> MaskV;
4149 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4150 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4151 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4152 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4153 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4154 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4156 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4157 // source words for the shuffle, to aid later transformations.
4158 bool AllWordsInNewV = true;
4159 bool InOrder[2] = { true, true };
4160 for (unsigned i = 0; i != 8; ++i) {
4161 int idx = MaskVals[i];
4163 InOrder[i/4] = false;
4164 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4166 AllWordsInNewV = false;
4170 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4171 if (AllWordsInNewV) {
4172 for (int i = 0; i != 8; ++i) {
4173 int idx = MaskVals[i];
4176 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4177 if ((idx != i) && idx < 4)
4179 if ((idx != i) && idx > 3)
4188 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4189 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4190 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4191 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4192 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4196 // If we have SSSE3, and all words of the result are from 1 input vector,
4197 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4198 // is present, fall back to case 4.
4199 if (TLI.getSubtarget()->hasSSSE3()) {
4200 SmallVector<SDValue,16> pshufbMask;
4202 // If we have elements from both input vectors, set the high bit of the
4203 // shuffle mask element to zero out elements that come from V2 in the V1
4204 // mask, and elements that come from V1 in the V2 mask, so that the two
4205 // results can be OR'd together.
4206 bool TwoInputs = V1Used && V2Used;
4207 for (unsigned i = 0; i != 8; ++i) {
4208 int EltIdx = MaskVals[i] * 2;
4209 if (TwoInputs && (EltIdx >= 16)) {
4210 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4211 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4214 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4215 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4217 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4218 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4219 DAG.getNode(ISD::BUILD_VECTOR, dl,
4220 MVT::v16i8, &pshufbMask[0], 16));
4222 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4224 // Calculate the shuffle mask for the second input, shuffle it, and
4225 // OR it with the first shuffled input.
4227 for (unsigned i = 0; i != 8; ++i) {
4228 int EltIdx = MaskVals[i] * 2;
4230 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4231 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4234 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4235 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4237 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4238 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4239 DAG.getNode(ISD::BUILD_VECTOR, dl,
4240 MVT::v16i8, &pshufbMask[0], 16));
4241 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4242 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4245 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4246 // and update MaskVals with new element order.
4247 BitVector InOrder(8);
4248 if (BestLoQuad >= 0) {
4249 SmallVector<int, 8> MaskV;
4250 for (int i = 0; i != 4; ++i) {
4251 int idx = MaskVals[i];
4253 MaskV.push_back(-1);
4255 } else if ((idx / 4) == BestLoQuad) {
4256 MaskV.push_back(idx & 3);
4259 MaskV.push_back(-1);
4262 for (unsigned i = 4; i != 8; ++i)
4264 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4268 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4269 // and update MaskVals with the new element order.
4270 if (BestHiQuad >= 0) {
4271 SmallVector<int, 8> MaskV;
4272 for (unsigned i = 0; i != 4; ++i)
4274 for (unsigned i = 4; i != 8; ++i) {
4275 int idx = MaskVals[i];
4277 MaskV.push_back(-1);
4279 } else if ((idx / 4) == BestHiQuad) {
4280 MaskV.push_back((idx & 3) + 4);
4283 MaskV.push_back(-1);
4286 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4290 // In case BestHi & BestLo were both -1, which means each quadword has a word
4291 // from each of the four input quadwords, calculate the InOrder bitvector now
4292 // before falling through to the insert/extract cleanup.
4293 if (BestLoQuad == -1 && BestHiQuad == -1) {
4295 for (int i = 0; i != 8; ++i)
4296 if (MaskVals[i] < 0 || MaskVals[i] == i)
4300 // The other elements are put in the right place using pextrw and pinsrw.
4301 for (unsigned i = 0; i != 8; ++i) {
4304 int EltIdx = MaskVals[i];
4307 SDValue ExtOp = (EltIdx < 8)
4308 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4309 DAG.getIntPtrConstant(EltIdx))
4310 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4311 DAG.getIntPtrConstant(EltIdx - 8));
4312 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4313 DAG.getIntPtrConstant(i));
4318 // v16i8 shuffles - Prefer shuffles in the following order:
4319 // 1. [ssse3] 1 x pshufb
4320 // 2. [ssse3] 2 x pshufb + 1 x por
4321 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4323 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4325 const X86TargetLowering &TLI) {
4326 SDValue V1 = SVOp->getOperand(0);
4327 SDValue V2 = SVOp->getOperand(1);
4328 DebugLoc dl = SVOp->getDebugLoc();
4329 SmallVector<int, 16> MaskVals;
4330 SVOp->getMask(MaskVals);
4332 // If we have SSSE3, case 1 is generated when all result bytes come from
4333 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4334 // present, fall back to case 3.
4335 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4338 for (unsigned i = 0; i < 16; ++i) {
4339 int EltIdx = MaskVals[i];
4348 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4349 if (TLI.getSubtarget()->hasSSSE3()) {
4350 SmallVector<SDValue,16> pshufbMask;
4352 // If all result elements are from one input vector, then only translate
4353 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4355 // Otherwise, we have elements from both input vectors, and must zero out
4356 // elements that come from V2 in the first mask, and V1 in the second mask
4357 // so that we can OR them together.
4358 bool TwoInputs = !(V1Only || V2Only);
4359 for (unsigned i = 0; i != 16; ++i) {
4360 int EltIdx = MaskVals[i];
4361 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4362 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4365 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4367 // If all the elements are from V2, assign it to V1 and return after
4368 // building the first pshufb.
4371 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4372 DAG.getNode(ISD::BUILD_VECTOR, dl,
4373 MVT::v16i8, &pshufbMask[0], 16));
4377 // Calculate the shuffle mask for the second input, shuffle it, and
4378 // OR it with the first shuffled input.
4380 for (unsigned i = 0; i != 16; ++i) {
4381 int EltIdx = MaskVals[i];
4383 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4386 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4388 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4389 DAG.getNode(ISD::BUILD_VECTOR, dl,
4390 MVT::v16i8, &pshufbMask[0], 16));
4391 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4394 // No SSSE3 - Calculate in place words and then fix all out of place words
4395 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4396 // the 16 different words that comprise the two doublequadword input vectors.
4397 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4398 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4399 SDValue NewV = V2Only ? V2 : V1;
4400 for (int i = 0; i != 8; ++i) {
4401 int Elt0 = MaskVals[i*2];
4402 int Elt1 = MaskVals[i*2+1];
4404 // This word of the result is all undef, skip it.
4405 if (Elt0 < 0 && Elt1 < 0)
4408 // This word of the result is already in the correct place, skip it.
4409 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4411 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4414 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4415 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4418 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4419 // using a single extract together, load it and store it.
4420 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4421 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4422 DAG.getIntPtrConstant(Elt1 / 2));
4423 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4424 DAG.getIntPtrConstant(i));
4428 // If Elt1 is defined, extract it from the appropriate source. If the
4429 // source byte is not also odd, shift the extracted word left 8 bits
4430 // otherwise clear the bottom 8 bits if we need to do an or.
4432 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4433 DAG.getIntPtrConstant(Elt1 / 2));
4434 if ((Elt1 & 1) == 0)
4435 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4436 DAG.getConstant(8, TLI.getShiftAmountTy()));
4438 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4439 DAG.getConstant(0xFF00, MVT::i16));
4441 // If Elt0 is defined, extract it from the appropriate source. If the
4442 // source byte is not also even, shift the extracted word right 8 bits. If
4443 // Elt1 was also defined, OR the extracted values together before
4444 // inserting them in the result.
4446 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4447 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4448 if ((Elt0 & 1) != 0)
4449 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4450 DAG.getConstant(8, TLI.getShiftAmountTy()));
4452 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4453 DAG.getConstant(0x00FF, MVT::i16));
4454 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4457 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4458 DAG.getIntPtrConstant(i));
4460 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4463 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4464 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4465 /// done when every pair / quad of shuffle mask elements point to elements in
4466 /// the right sequence. e.g.
4467 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4469 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4471 const TargetLowering &TLI, DebugLoc dl) {
4472 EVT VT = SVOp->getValueType(0);
4473 SDValue V1 = SVOp->getOperand(0);
4474 SDValue V2 = SVOp->getOperand(1);
4475 unsigned NumElems = VT.getVectorNumElements();
4476 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4477 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4479 switch (VT.getSimpleVT().SimpleTy) {
4480 default: assert(false && "Unexpected!");
4481 case MVT::v4f32: NewVT = MVT::v2f64; break;
4482 case MVT::v4i32: NewVT = MVT::v2i64; break;
4483 case MVT::v8i16: NewVT = MVT::v4i32; break;
4484 case MVT::v16i8: NewVT = MVT::v4i32; break;
4487 if (NewWidth == 2) {
4493 int Scale = NumElems / NewWidth;
4494 SmallVector<int, 8> MaskVec;
4495 for (unsigned i = 0; i < NumElems; i += Scale) {
4497 for (int j = 0; j < Scale; ++j) {
4498 int EltIdx = SVOp->getMaskElt(i+j);
4502 StartIdx = EltIdx - (EltIdx % Scale);
4503 if (EltIdx != StartIdx + j)
4507 MaskVec.push_back(-1);
4509 MaskVec.push_back(StartIdx / Scale);
4512 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4513 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4514 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4517 /// getVZextMovL - Return a zero-extending vector move low node.
4519 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4520 SDValue SrcOp, SelectionDAG &DAG,
4521 const X86Subtarget *Subtarget, DebugLoc dl) {
4522 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4523 LoadSDNode *LD = NULL;
4524 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4525 LD = dyn_cast<LoadSDNode>(SrcOp);
4527 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4529 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4530 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4531 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4532 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4533 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4535 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4536 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4537 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4538 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4546 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4547 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4548 DAG.getNode(ISD::BIT_CONVERT, dl,
4552 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4555 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4556 SDValue V1 = SVOp->getOperand(0);
4557 SDValue V2 = SVOp->getOperand(1);
4558 DebugLoc dl = SVOp->getDebugLoc();
4559 EVT VT = SVOp->getValueType(0);
4561 SmallVector<std::pair<int, int>, 8> Locs;
4563 SmallVector<int, 8> Mask1(4U, -1);
4564 SmallVector<int, 8> PermMask;
4565 SVOp->getMask(PermMask);
4569 for (unsigned i = 0; i != 4; ++i) {
4570 int Idx = PermMask[i];
4572 Locs[i] = std::make_pair(-1, -1);
4574 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4576 Locs[i] = std::make_pair(0, NumLo);
4580 Locs[i] = std::make_pair(1, NumHi);
4582 Mask1[2+NumHi] = Idx;
4588 if (NumLo <= 2 && NumHi <= 2) {
4589 // If no more than two elements come from either vector. This can be
4590 // implemented with two shuffles. First shuffle gather the elements.
4591 // The second shuffle, which takes the first shuffle as both of its
4592 // vector operands, put the elements into the right order.
4593 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4595 SmallVector<int, 8> Mask2(4U, -1);
4597 for (unsigned i = 0; i != 4; ++i) {
4598 if (Locs[i].first == -1)
4601 unsigned Idx = (i < 2) ? 0 : 4;
4602 Idx += Locs[i].first * 2 + Locs[i].second;
4607 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4608 } else if (NumLo == 3 || NumHi == 3) {
4609 // Otherwise, we must have three elements from one vector, call it X, and
4610 // one element from the other, call it Y. First, use a shufps to build an
4611 // intermediate vector with the one element from Y and the element from X
4612 // that will be in the same half in the final destination (the indexes don't
4613 // matter). Then, use a shufps to build the final vector, taking the half
4614 // containing the element from Y from the intermediate, and the other half
4617 // Normalize it so the 3 elements come from V1.
4618 CommuteVectorShuffleMask(PermMask, VT);
4622 // Find the element from V2.
4624 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4625 int Val = PermMask[HiIndex];
4632 Mask1[0] = PermMask[HiIndex];
4634 Mask1[2] = PermMask[HiIndex^1];
4636 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4639 Mask1[0] = PermMask[0];
4640 Mask1[1] = PermMask[1];
4641 Mask1[2] = HiIndex & 1 ? 6 : 4;
4642 Mask1[3] = HiIndex & 1 ? 4 : 6;
4643 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4645 Mask1[0] = HiIndex & 1 ? 2 : 0;
4646 Mask1[1] = HiIndex & 1 ? 0 : 2;
4647 Mask1[2] = PermMask[2];
4648 Mask1[3] = PermMask[3];
4653 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4657 // Break it into (shuffle shuffle_hi, shuffle_lo).
4659 SmallVector<int,8> LoMask(4U, -1);
4660 SmallVector<int,8> HiMask(4U, -1);
4662 SmallVector<int,8> *MaskPtr = &LoMask;
4663 unsigned MaskIdx = 0;
4666 for (unsigned i = 0; i != 4; ++i) {
4673 int Idx = PermMask[i];
4675 Locs[i] = std::make_pair(-1, -1);
4676 } else if (Idx < 4) {
4677 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4678 (*MaskPtr)[LoIdx] = Idx;
4681 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4682 (*MaskPtr)[HiIdx] = Idx;
4687 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4688 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4689 SmallVector<int, 8> MaskOps;
4690 for (unsigned i = 0; i != 4; ++i) {
4691 if (Locs[i].first == -1) {
4692 MaskOps.push_back(-1);
4694 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4695 MaskOps.push_back(Idx);
4698 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4702 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4704 SDValue V1 = Op.getOperand(0);
4705 SDValue V2 = Op.getOperand(1);
4706 EVT VT = Op.getValueType();
4707 DebugLoc dl = Op.getDebugLoc();
4708 unsigned NumElems = VT.getVectorNumElements();
4709 bool isMMX = VT.getSizeInBits() == 64;
4710 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4711 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4712 bool V1IsSplat = false;
4713 bool V2IsSplat = false;
4715 if (isZeroShuffle(SVOp))
4716 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4718 // Promote splats to v4f32.
4719 if (SVOp->isSplat()) {
4720 if (isMMX || NumElems < 4)
4722 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4725 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4727 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4728 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4729 if (NewOp.getNode())
4730 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4731 LowerVECTOR_SHUFFLE(NewOp, DAG));
4732 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4733 // FIXME: Figure out a cleaner way to do this.
4734 // Try to make use of movq to zero out the top part.
4735 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4736 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4737 if (NewOp.getNode()) {
4738 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4739 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4740 DAG, Subtarget, dl);
4742 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4743 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4744 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4745 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4746 DAG, Subtarget, dl);
4750 if (X86::isPSHUFDMask(SVOp))
4753 // Check if this can be converted into a logical shift.
4754 bool isLeft = false;
4757 bool isShift = getSubtarget()->hasSSE2() &&
4758 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4759 if (isShift && ShVal.hasOneUse()) {
4760 // If the shifted value has multiple uses, it may be cheaper to use
4761 // v_set0 + movlhps or movhlps, etc.
4762 EVT EltVT = VT.getVectorElementType();
4763 ShAmt *= EltVT.getSizeInBits();
4764 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4767 if (X86::isMOVLMask(SVOp)) {
4770 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4771 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4776 // FIXME: fold these into legal mask.
4777 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4778 X86::isMOVSLDUPMask(SVOp) ||
4779 X86::isMOVHLPSMask(SVOp) ||
4780 X86::isMOVLHPSMask(SVOp) ||
4781 X86::isMOVLPMask(SVOp)))
4784 if (ShouldXformToMOVHLPS(SVOp) ||
4785 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4786 return CommuteVectorShuffle(SVOp, DAG);
4789 // No better options. Use a vshl / vsrl.
4790 EVT EltVT = VT.getVectorElementType();
4791 ShAmt *= EltVT.getSizeInBits();
4792 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4795 bool Commuted = false;
4796 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4797 // 1,1,1,1 -> v8i16 though.
4798 V1IsSplat = isSplatVector(V1.getNode());
4799 V2IsSplat = isSplatVector(V2.getNode());
4801 // Canonicalize the splat or undef, if present, to be on the RHS.
4802 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4803 Op = CommuteVectorShuffle(SVOp, DAG);
4804 SVOp = cast<ShuffleVectorSDNode>(Op);
4805 V1 = SVOp->getOperand(0);
4806 V2 = SVOp->getOperand(1);
4807 std::swap(V1IsSplat, V2IsSplat);
4808 std::swap(V1IsUndef, V2IsUndef);
4812 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4813 // Shuffling low element of v1 into undef, just return v1.
4816 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4817 // the instruction selector will not match, so get a canonical MOVL with
4818 // swapped operands to undo the commute.
4819 return getMOVL(DAG, dl, VT, V2, V1);
4822 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4823 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4824 X86::isUNPCKLMask(SVOp) ||
4825 X86::isUNPCKHMask(SVOp))
4829 // Normalize mask so all entries that point to V2 points to its first
4830 // element then try to match unpck{h|l} again. If match, return a
4831 // new vector_shuffle with the corrected mask.
4832 SDValue NewMask = NormalizeMask(SVOp, DAG);
4833 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4834 if (NSVOp != SVOp) {
4835 if (X86::isUNPCKLMask(NSVOp, true)) {
4837 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4844 // Commute is back and try unpck* again.
4845 // FIXME: this seems wrong.
4846 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4847 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4848 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4849 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4850 X86::isUNPCKLMask(NewSVOp) ||
4851 X86::isUNPCKHMask(NewSVOp))
4855 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4857 // Normalize the node to match x86 shuffle ops if needed
4858 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4859 return CommuteVectorShuffle(SVOp, DAG);
4861 // Check for legal shuffle and return?
4862 SmallVector<int, 16> PermMask;
4863 SVOp->getMask(PermMask);
4864 if (isShuffleMaskLegal(PermMask, VT))
4867 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4868 if (VT == MVT::v8i16) {
4869 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4870 if (NewOp.getNode())
4874 if (VT == MVT::v16i8) {
4875 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4876 if (NewOp.getNode())
4880 // Handle all 4 wide cases with a number of shuffles except for MMX.
4881 if (NumElems == 4 && !isMMX)
4882 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4888 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4889 SelectionDAG &DAG) const {
4890 EVT VT = Op.getValueType();
4891 DebugLoc dl = Op.getDebugLoc();
4892 if (VT.getSizeInBits() == 8) {
4893 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4894 Op.getOperand(0), Op.getOperand(1));
4895 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4896 DAG.getValueType(VT));
4897 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4898 } else if (VT.getSizeInBits() == 16) {
4899 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4900 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4902 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4903 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4904 DAG.getNode(ISD::BIT_CONVERT, dl,
4908 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4909 Op.getOperand(0), Op.getOperand(1));
4910 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4911 DAG.getValueType(VT));
4912 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4913 } else if (VT == MVT::f32) {
4914 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4915 // the result back to FR32 register. It's only worth matching if the
4916 // result has a single use which is a store or a bitcast to i32. And in
4917 // the case of a store, it's not worth it if the index is a constant 0,
4918 // because a MOVSSmr can be used instead, which is smaller and faster.
4919 if (!Op.hasOneUse())
4921 SDNode *User = *Op.getNode()->use_begin();
4922 if ((User->getOpcode() != ISD::STORE ||
4923 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4924 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4925 (User->getOpcode() != ISD::BIT_CONVERT ||
4926 User->getValueType(0) != MVT::i32))
4928 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4929 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4932 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4933 } else if (VT == MVT::i32) {
4934 // ExtractPS works with constant index.
4935 if (isa<ConstantSDNode>(Op.getOperand(1)))
4943 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4944 SelectionDAG &DAG) const {
4945 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4948 if (Subtarget->hasSSE41()) {
4949 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4954 EVT VT = Op.getValueType();
4955 DebugLoc dl = Op.getDebugLoc();
4956 // TODO: handle v16i8.
4957 if (VT.getSizeInBits() == 16) {
4958 SDValue Vec = Op.getOperand(0);
4959 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4961 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4962 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4963 DAG.getNode(ISD::BIT_CONVERT, dl,
4966 // Transform it so it match pextrw which produces a 32-bit result.
4967 EVT EltVT = MVT::i32;
4968 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4969 Op.getOperand(0), Op.getOperand(1));
4970 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4971 DAG.getValueType(VT));
4972 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4973 } else if (VT.getSizeInBits() == 32) {
4974 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4978 // SHUFPS the element to the lowest double word, then movss.
4979 int Mask[4] = { Idx, -1, -1, -1 };
4980 EVT VVT = Op.getOperand(0).getValueType();
4981 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4982 DAG.getUNDEF(VVT), Mask);
4983 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4984 DAG.getIntPtrConstant(0));
4985 } else if (VT.getSizeInBits() == 64) {
4986 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4987 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4988 // to match extract_elt for f64.
4989 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4993 // UNPCKHPD the element to the lowest double word, then movsd.
4994 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4995 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4996 int Mask[2] = { 1, -1 };
4997 EVT VVT = Op.getOperand(0).getValueType();
4998 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4999 DAG.getUNDEF(VVT), Mask);
5000 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5001 DAG.getIntPtrConstant(0));
5008 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5009 SelectionDAG &DAG) const {
5010 EVT VT = Op.getValueType();
5011 EVT EltVT = VT.getVectorElementType();
5012 DebugLoc dl = Op.getDebugLoc();
5014 SDValue N0 = Op.getOperand(0);
5015 SDValue N1 = Op.getOperand(1);
5016 SDValue N2 = Op.getOperand(2);
5018 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5019 isa<ConstantSDNode>(N2)) {
5021 if (VT == MVT::v8i16)
5022 Opc = X86ISD::PINSRW;
5023 else if (VT == MVT::v4i16)
5024 Opc = X86ISD::MMX_PINSRW;
5025 else if (VT == MVT::v16i8)
5026 Opc = X86ISD::PINSRB;
5028 Opc = X86ISD::PINSRB;
5030 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5032 if (N1.getValueType() != MVT::i32)
5033 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5034 if (N2.getValueType() != MVT::i32)
5035 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5036 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5037 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5038 // Bits [7:6] of the constant are the source select. This will always be
5039 // zero here. The DAG Combiner may combine an extract_elt index into these
5040 // bits. For example (insert (extract, 3), 2) could be matched by putting
5041 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5042 // Bits [5:4] of the constant are the destination select. This is the
5043 // value of the incoming immediate.
5044 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5045 // combine either bitwise AND or insert of float 0.0 to set these bits.
5046 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5047 // Create this as a scalar to vector..
5048 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5049 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5050 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5051 // PINSR* works with constant index.
5058 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5059 EVT VT = Op.getValueType();
5060 EVT EltVT = VT.getVectorElementType();
5062 if (Subtarget->hasSSE41())
5063 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5065 if (EltVT == MVT::i8)
5068 DebugLoc dl = Op.getDebugLoc();
5069 SDValue N0 = Op.getOperand(0);
5070 SDValue N1 = Op.getOperand(1);
5071 SDValue N2 = Op.getOperand(2);
5073 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5074 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5075 // as its second argument.
5076 if (N1.getValueType() != MVT::i32)
5077 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5078 if (N2.getValueType() != MVT::i32)
5079 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5080 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5081 dl, VT, N0, N1, N2);
5087 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5088 DebugLoc dl = Op.getDebugLoc();
5090 if (Op.getValueType() == MVT::v1i64 &&
5091 Op.getOperand(0).getValueType() == MVT::i64)
5092 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5094 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5095 EVT VT = MVT::v2i32;
5096 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5103 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5104 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5107 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5108 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5109 // one of the above mentioned nodes. It has to be wrapped because otherwise
5110 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5111 // be used to form addressing mode. These wrapped nodes will be selected
5114 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5115 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5117 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5119 unsigned char OpFlag = 0;
5120 unsigned WrapperKind = X86ISD::Wrapper;
5121 CodeModel::Model M = getTargetMachine().getCodeModel();
5123 if (Subtarget->isPICStyleRIPRel() &&
5124 (M == CodeModel::Small || M == CodeModel::Kernel))
5125 WrapperKind = X86ISD::WrapperRIP;
5126 else if (Subtarget->isPICStyleGOT())
5127 OpFlag = X86II::MO_GOTOFF;
5128 else if (Subtarget->isPICStyleStubPIC())
5129 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5131 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5133 CP->getOffset(), OpFlag);
5134 DebugLoc DL = CP->getDebugLoc();
5135 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5136 // With PIC, the address is actually $g + Offset.
5138 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5139 DAG.getNode(X86ISD::GlobalBaseReg,
5140 DebugLoc(), getPointerTy()),
5147 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5148 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5150 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5152 unsigned char OpFlag = 0;
5153 unsigned WrapperKind = X86ISD::Wrapper;
5154 CodeModel::Model M = getTargetMachine().getCodeModel();
5156 if (Subtarget->isPICStyleRIPRel() &&
5157 (M == CodeModel::Small || M == CodeModel::Kernel))
5158 WrapperKind = X86ISD::WrapperRIP;
5159 else if (Subtarget->isPICStyleGOT())
5160 OpFlag = X86II::MO_GOTOFF;
5161 else if (Subtarget->isPICStyleStubPIC())
5162 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5164 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5166 DebugLoc DL = JT->getDebugLoc();
5167 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5169 // With PIC, the address is actually $g + Offset.
5171 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5172 DAG.getNode(X86ISD::GlobalBaseReg,
5173 DebugLoc(), getPointerTy()),
5181 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5182 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5184 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5186 unsigned char OpFlag = 0;
5187 unsigned WrapperKind = X86ISD::Wrapper;
5188 CodeModel::Model M = getTargetMachine().getCodeModel();
5190 if (Subtarget->isPICStyleRIPRel() &&
5191 (M == CodeModel::Small || M == CodeModel::Kernel))
5192 WrapperKind = X86ISD::WrapperRIP;
5193 else if (Subtarget->isPICStyleGOT())
5194 OpFlag = X86II::MO_GOTOFF;
5195 else if (Subtarget->isPICStyleStubPIC())
5196 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5198 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5200 DebugLoc DL = Op.getDebugLoc();
5201 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5204 // With PIC, the address is actually $g + Offset.
5205 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5206 !Subtarget->is64Bit()) {
5207 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5208 DAG.getNode(X86ISD::GlobalBaseReg,
5209 DebugLoc(), getPointerTy()),
5217 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5218 // Create the TargetBlockAddressAddress node.
5219 unsigned char OpFlags =
5220 Subtarget->ClassifyBlockAddressReference();
5221 CodeModel::Model M = getTargetMachine().getCodeModel();
5222 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5223 DebugLoc dl = Op.getDebugLoc();
5224 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5225 /*isTarget=*/true, OpFlags);
5227 if (Subtarget->isPICStyleRIPRel() &&
5228 (M == CodeModel::Small || M == CodeModel::Kernel))
5229 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5231 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5233 // With PIC, the address is actually $g + Offset.
5234 if (isGlobalRelativeToPICBase(OpFlags)) {
5235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5236 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5244 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5246 SelectionDAG &DAG) const {
5247 // Create the TargetGlobalAddress node, folding in the constant
5248 // offset if it is legal.
5249 unsigned char OpFlags =
5250 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5251 CodeModel::Model M = getTargetMachine().getCodeModel();
5253 if (OpFlags == X86II::MO_NO_FLAG &&
5254 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5255 // A direct static reference to a global.
5256 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5259 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5262 if (Subtarget->isPICStyleRIPRel() &&
5263 (M == CodeModel::Small || M == CodeModel::Kernel))
5264 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5266 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5268 // With PIC, the address is actually $g + Offset.
5269 if (isGlobalRelativeToPICBase(OpFlags)) {
5270 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5271 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5275 // For globals that require a load from a stub to get the address, emit the
5277 if (isGlobalStubReference(OpFlags))
5278 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5279 PseudoSourceValue::getGOT(), 0, false, false, 0);
5281 // If there was a non-zero offset that we didn't fold, create an explicit
5284 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5285 DAG.getConstant(Offset, getPointerTy()));
5291 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5292 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5293 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5294 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5298 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5299 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5300 unsigned char OperandFlags) {
5301 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5302 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5303 DebugLoc dl = GA->getDebugLoc();
5304 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5305 GA->getValueType(0),
5309 SDValue Ops[] = { Chain, TGA, *InFlag };
5310 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5312 SDValue Ops[] = { Chain, TGA };
5313 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5316 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5317 MFI->setAdjustsStack(true);
5319 SDValue Flag = Chain.getValue(1);
5320 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5323 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5325 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5328 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5329 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5330 DAG.getNode(X86ISD::GlobalBaseReg,
5331 DebugLoc(), PtrVT), InFlag);
5332 InFlag = Chain.getValue(1);
5334 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5337 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5339 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5341 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5342 X86::RAX, X86II::MO_TLSGD);
5345 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5346 // "local exec" model.
5347 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5348 const EVT PtrVT, TLSModel::Model model,
5350 DebugLoc dl = GA->getDebugLoc();
5351 // Get the Thread Pointer
5352 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5354 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5357 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5358 NULL, 0, false, false, 0);
5360 unsigned char OperandFlags = 0;
5361 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5363 unsigned WrapperKind = X86ISD::Wrapper;
5364 if (model == TLSModel::LocalExec) {
5365 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5366 } else if (is64Bit) {
5367 assert(model == TLSModel::InitialExec);
5368 OperandFlags = X86II::MO_GOTTPOFF;
5369 WrapperKind = X86ISD::WrapperRIP;
5371 assert(model == TLSModel::InitialExec);
5372 OperandFlags = X86II::MO_INDNTPOFF;
5375 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5377 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5378 GA->getValueType(0),
5379 GA->getOffset(), OperandFlags);
5380 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5382 if (model == TLSModel::InitialExec)
5383 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5384 PseudoSourceValue::getGOT(), 0, false, false, 0);
5386 // The address of the thread local variable is the add of the thread
5387 // pointer with the offset of the variable.
5388 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5392 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5394 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5395 const GlobalValue *GV = GA->getGlobal();
5397 if (Subtarget->isTargetELF()) {
5398 // TODO: implement the "local dynamic" model
5399 // TODO: implement the "initial exec"model for pic executables
5401 // If GV is an alias then use the aliasee for determining
5402 // thread-localness.
5403 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5404 GV = GA->resolveAliasedGlobal(false);
5406 TLSModel::Model model
5407 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5410 case TLSModel::GeneralDynamic:
5411 case TLSModel::LocalDynamic: // not implemented
5412 if (Subtarget->is64Bit())
5413 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5414 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5416 case TLSModel::InitialExec:
5417 case TLSModel::LocalExec:
5418 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5419 Subtarget->is64Bit());
5421 } else if (Subtarget->isTargetDarwin()) {
5422 // Darwin only has one model of TLS. Lower to that.
5423 unsigned char OpFlag = 0;
5424 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5425 X86ISD::WrapperRIP : X86ISD::Wrapper;
5427 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5429 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5430 !Subtarget->is64Bit();
5432 OpFlag = X86II::MO_TLVP_PIC_BASE;
5434 OpFlag = X86II::MO_TLVP;
5435 DebugLoc DL = Op.getDebugLoc();
5436 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
5438 GA->getOffset(), OpFlag);
5439 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5441 // With PIC32, the address is actually $g + Offset.
5443 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5444 DAG.getNode(X86ISD::GlobalBaseReg,
5445 DebugLoc(), getPointerTy()),
5448 // Lowering the machine isd will make sure everything is in the right
5450 SDValue Args[] = { Offset };
5451 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5453 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5454 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5455 MFI->setAdjustsStack(true);
5457 // And our return value (tls address) is in the standard call return value
5459 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5460 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5464 "TLS not implemented for this target.");
5466 llvm_unreachable("Unreachable");
5471 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5472 /// take a 2 x i32 value to shift plus a shift amount.
5473 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5474 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5475 EVT VT = Op.getValueType();
5476 unsigned VTBits = VT.getSizeInBits();
5477 DebugLoc dl = Op.getDebugLoc();
5478 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5479 SDValue ShOpLo = Op.getOperand(0);
5480 SDValue ShOpHi = Op.getOperand(1);
5481 SDValue ShAmt = Op.getOperand(2);
5482 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5483 DAG.getConstant(VTBits - 1, MVT::i8))
5484 : DAG.getConstant(0, VT);
5487 if (Op.getOpcode() == ISD::SHL_PARTS) {
5488 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5489 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5491 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5492 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5495 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5496 DAG.getConstant(VTBits, MVT::i8));
5497 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5498 AndNode, DAG.getConstant(0, MVT::i8));
5501 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5502 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5503 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5505 if (Op.getOpcode() == ISD::SHL_PARTS) {
5506 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5507 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5509 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5510 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5513 SDValue Ops[2] = { Lo, Hi };
5514 return DAG.getMergeValues(Ops, 2, dl);
5517 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5518 SelectionDAG &DAG) const {
5519 EVT SrcVT = Op.getOperand(0).getValueType();
5521 if (SrcVT.isVector()) {
5522 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5528 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5529 "Unknown SINT_TO_FP to lower!");
5531 // These are really Legal; return the operand so the caller accepts it as
5533 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5535 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5536 Subtarget->is64Bit()) {
5540 DebugLoc dl = Op.getDebugLoc();
5541 unsigned Size = SrcVT.getSizeInBits()/8;
5542 MachineFunction &MF = DAG.getMachineFunction();
5543 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5544 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5545 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5547 PseudoSourceValue::getFixedStack(SSFI), 0,
5549 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5552 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5554 SelectionDAG &DAG) const {
5556 DebugLoc dl = Op.getDebugLoc();
5558 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5560 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5562 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5563 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5564 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5565 Tys, Ops, array_lengthof(Ops));
5568 Chain = Result.getValue(1);
5569 SDValue InFlag = Result.getValue(2);
5571 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5572 // shouldn't be necessary except that RFP cannot be live across
5573 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5574 MachineFunction &MF = DAG.getMachineFunction();
5575 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5576 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5577 Tys = DAG.getVTList(MVT::Other);
5579 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5581 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5582 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5583 PseudoSourceValue::getFixedStack(SSFI), 0,
5590 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5591 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5592 SelectionDAG &DAG) const {
5593 // This algorithm is not obvious. Here it is in C code, more or less:
5595 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5596 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5597 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5599 // Copy ints to xmm registers.
5600 __m128i xh = _mm_cvtsi32_si128( hi );
5601 __m128i xl = _mm_cvtsi32_si128( lo );
5603 // Combine into low half of a single xmm register.
5604 __m128i x = _mm_unpacklo_epi32( xh, xl );
5608 // Merge in appropriate exponents to give the integer bits the right
5610 x = _mm_unpacklo_epi32( x, exp );
5612 // Subtract away the biases to deal with the IEEE-754 double precision
5614 d = _mm_sub_pd( (__m128d) x, bias );
5616 // All conversions up to here are exact. The correctly rounded result is
5617 // calculated using the current rounding mode using the following
5619 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5620 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5621 // store doesn't really need to be here (except
5622 // maybe to zero the other double)
5627 DebugLoc dl = Op.getDebugLoc();
5628 LLVMContext *Context = DAG.getContext();
5630 // Build some magic constants.
5631 std::vector<Constant*> CV0;
5632 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5633 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5634 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5635 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5636 Constant *C0 = ConstantVector::get(CV0);
5637 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5639 std::vector<Constant*> CV1;
5641 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5643 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5644 Constant *C1 = ConstantVector::get(CV1);
5645 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5647 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5648 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5650 DAG.getIntPtrConstant(1)));
5651 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5652 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5654 DAG.getIntPtrConstant(0)));
5655 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5656 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5657 PseudoSourceValue::getConstantPool(), 0,
5659 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5660 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5661 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5662 PseudoSourceValue::getConstantPool(), 0,
5664 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5666 // Add the halves; easiest way is to swap them into another reg first.
5667 int ShufMask[2] = { 1, -1 };
5668 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5669 DAG.getUNDEF(MVT::v2f64), ShufMask);
5670 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5671 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5672 DAG.getIntPtrConstant(0));
5675 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5676 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5677 SelectionDAG &DAG) const {
5678 DebugLoc dl = Op.getDebugLoc();
5679 // FP constant to bias correct the final result.
5680 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5683 // Load the 32-bit value into an XMM register.
5684 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5685 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5687 DAG.getIntPtrConstant(0)));
5689 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5690 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5691 DAG.getIntPtrConstant(0));
5693 // Or the load with the bias.
5694 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5695 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5696 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5698 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5699 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5700 MVT::v2f64, Bias)));
5701 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5702 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5703 DAG.getIntPtrConstant(0));
5705 // Subtract the bias.
5706 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5708 // Handle final rounding.
5709 EVT DestVT = Op.getValueType();
5711 if (DestVT.bitsLT(MVT::f64)) {
5712 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5713 DAG.getIntPtrConstant(0));
5714 } else if (DestVT.bitsGT(MVT::f64)) {
5715 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5718 // Handle final rounding.
5722 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5723 SelectionDAG &DAG) const {
5724 SDValue N0 = Op.getOperand(0);
5725 DebugLoc dl = Op.getDebugLoc();
5727 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5728 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5729 // the optimization here.
5730 if (DAG.SignBitIsZero(N0))
5731 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5733 EVT SrcVT = N0.getValueType();
5734 EVT DstVT = Op.getValueType();
5735 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5736 return LowerUINT_TO_FP_i64(Op, DAG);
5737 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5738 return LowerUINT_TO_FP_i32(Op, DAG);
5740 // Make a 64-bit buffer, and use it to build an FILD.
5741 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5742 if (SrcVT == MVT::i32) {
5743 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5744 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5745 getPointerTy(), StackSlot, WordOff);
5746 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5747 StackSlot, NULL, 0, false, false, 0);
5748 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5749 OffsetSlot, NULL, 0, false, false, 0);
5750 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5754 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5755 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5756 StackSlot, NULL, 0, false, false, 0);
5757 // For i64 source, we need to add the appropriate power of 2 if the input
5758 // was negative. This is the same as the optimization in
5759 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5760 // we must be careful to do the computation in x87 extended precision, not
5761 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5762 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5763 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5764 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5766 APInt FF(32, 0x5F800000ULL);
5768 // Check whether the sign bit is set.
5769 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5770 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5773 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5774 SDValue FudgePtr = DAG.getConstantPool(
5775 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5778 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5779 SDValue Zero = DAG.getIntPtrConstant(0);
5780 SDValue Four = DAG.getIntPtrConstant(4);
5781 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5783 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5785 // Load the value out, extending it from f32 to f80.
5786 // FIXME: Avoid the extend by constructing the right constant pool?
5787 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
5788 FudgePtr, PseudoSourceValue::getConstantPool(),
5789 0, MVT::f32, false, false, 4);
5790 // Extend everything to 80 bits to force it to be done on x87.
5791 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5792 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5795 std::pair<SDValue,SDValue> X86TargetLowering::
5796 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5797 DebugLoc dl = Op.getDebugLoc();
5799 EVT DstTy = Op.getValueType();
5802 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5806 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5807 DstTy.getSimpleVT() >= MVT::i16 &&
5808 "Unknown FP_TO_SINT to lower!");
5810 // These are really Legal.
5811 if (DstTy == MVT::i32 &&
5812 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5813 return std::make_pair(SDValue(), SDValue());
5814 if (Subtarget->is64Bit() &&
5815 DstTy == MVT::i64 &&
5816 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5817 return std::make_pair(SDValue(), SDValue());
5819 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5821 MachineFunction &MF = DAG.getMachineFunction();
5822 unsigned MemSize = DstTy.getSizeInBits()/8;
5823 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5824 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5827 switch (DstTy.getSimpleVT().SimpleTy) {
5828 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5829 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5830 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5831 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5834 SDValue Chain = DAG.getEntryNode();
5835 SDValue Value = Op.getOperand(0);
5836 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5837 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5838 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5839 PseudoSourceValue::getFixedStack(SSFI), 0,
5841 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5843 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5845 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5846 Chain = Value.getValue(1);
5847 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5848 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5851 // Build the FP_TO_INT*_IN_MEM
5852 SDValue Ops[] = { Chain, Value, StackSlot };
5853 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5855 return std::make_pair(FIST, StackSlot);
5858 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5859 SelectionDAG &DAG) const {
5860 if (Op.getValueType().isVector()) {
5861 if (Op.getValueType() == MVT::v2i32 &&
5862 Op.getOperand(0).getValueType() == MVT::v2f64) {
5868 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5869 SDValue FIST = Vals.first, StackSlot = Vals.second;
5870 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5871 if (FIST.getNode() == 0) return Op;
5874 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5875 FIST, StackSlot, NULL, 0, false, false, 0);
5878 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5879 SelectionDAG &DAG) const {
5880 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5881 SDValue FIST = Vals.first, StackSlot = Vals.second;
5882 assert(FIST.getNode() && "Unexpected failure");
5885 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5886 FIST, StackSlot, NULL, 0, false, false, 0);
5889 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5890 SelectionDAG &DAG) const {
5891 LLVMContext *Context = DAG.getContext();
5892 DebugLoc dl = Op.getDebugLoc();
5893 EVT VT = Op.getValueType();
5896 EltVT = VT.getVectorElementType();
5897 std::vector<Constant*> CV;
5898 if (EltVT == MVT::f64) {
5899 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5903 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5909 Constant *C = ConstantVector::get(CV);
5910 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5911 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5912 PseudoSourceValue::getConstantPool(), 0,
5914 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5917 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5918 LLVMContext *Context = DAG.getContext();
5919 DebugLoc dl = Op.getDebugLoc();
5920 EVT VT = Op.getValueType();
5923 EltVT = VT.getVectorElementType();
5924 std::vector<Constant*> CV;
5925 if (EltVT == MVT::f64) {
5926 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5930 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5936 Constant *C = ConstantVector::get(CV);
5937 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5938 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5939 PseudoSourceValue::getConstantPool(), 0,
5941 if (VT.isVector()) {
5942 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5943 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5944 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5946 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5948 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5952 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5953 LLVMContext *Context = DAG.getContext();
5954 SDValue Op0 = Op.getOperand(0);
5955 SDValue Op1 = Op.getOperand(1);
5956 DebugLoc dl = Op.getDebugLoc();
5957 EVT VT = Op.getValueType();
5958 EVT SrcVT = Op1.getValueType();
5960 // If second operand is smaller, extend it first.
5961 if (SrcVT.bitsLT(VT)) {
5962 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5965 // And if it is bigger, shrink it first.
5966 if (SrcVT.bitsGT(VT)) {
5967 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5971 // At this point the operands and the result should have the same
5972 // type, and that won't be f80 since that is not custom lowered.
5974 // First get the sign bit of second operand.
5975 std::vector<Constant*> CV;
5976 if (SrcVT == MVT::f64) {
5977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5978 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5980 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5981 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5982 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5983 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5985 Constant *C = ConstantVector::get(CV);
5986 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5987 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5988 PseudoSourceValue::getConstantPool(), 0,
5990 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5992 // Shift sign bit right or left if the two operands have different types.
5993 if (SrcVT.bitsGT(VT)) {
5994 // Op0 is MVT::f32, Op1 is MVT::f64.
5995 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5996 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5997 DAG.getConstant(32, MVT::i32));
5998 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5999 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6000 DAG.getIntPtrConstant(0));
6003 // Clear first operand sign bit.
6005 if (VT == MVT::f64) {
6006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6011 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6012 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6014 C = ConstantVector::get(CV);
6015 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6016 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6017 PseudoSourceValue::getConstantPool(), 0,
6019 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6021 // Or the value with the sign bit.
6022 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6025 /// Emit nodes that will be selected as "test Op0,Op0", or something
6027 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6028 SelectionDAG &DAG) const {
6029 DebugLoc dl = Op.getDebugLoc();
6031 // CF and OF aren't always set the way we want. Determine which
6032 // of these we need.
6033 bool NeedCF = false;
6034 bool NeedOF = false;
6037 case X86::COND_A: case X86::COND_AE:
6038 case X86::COND_B: case X86::COND_BE:
6041 case X86::COND_G: case X86::COND_GE:
6042 case X86::COND_L: case X86::COND_LE:
6043 case X86::COND_O: case X86::COND_NO:
6048 // See if we can use the EFLAGS value from the operand instead of
6049 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6050 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6051 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6052 // Emit a CMP with 0, which is the TEST pattern.
6053 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6054 DAG.getConstant(0, Op.getValueType()));
6056 unsigned Opcode = 0;
6057 unsigned NumOperands = 0;
6058 switch (Op.getNode()->getOpcode()) {
6060 // Due to an isel shortcoming, be conservative if this add is likely to be
6061 // selected as part of a load-modify-store instruction. When the root node
6062 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6063 // uses of other nodes in the match, such as the ADD in this case. This
6064 // leads to the ADD being left around and reselected, with the result being
6065 // two adds in the output. Alas, even if none our users are stores, that
6066 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6067 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6068 // climbing the DAG back to the root, and it doesn't seem to be worth the
6070 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6071 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6072 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6075 if (ConstantSDNode *C =
6076 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6077 // An add of one will be selected as an INC.
6078 if (C->getAPIntValue() == 1) {
6079 Opcode = X86ISD::INC;
6084 // An add of negative one (subtract of one) will be selected as a DEC.
6085 if (C->getAPIntValue().isAllOnesValue()) {
6086 Opcode = X86ISD::DEC;
6092 // Otherwise use a regular EFLAGS-setting add.
6093 Opcode = X86ISD::ADD;
6097 // If the primary and result isn't used, don't bother using X86ISD::AND,
6098 // because a TEST instruction will be better.
6099 bool NonFlagUse = false;
6100 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6101 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6103 unsigned UOpNo = UI.getOperandNo();
6104 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6105 // Look pass truncate.
6106 UOpNo = User->use_begin().getOperandNo();
6107 User = *User->use_begin();
6110 if (User->getOpcode() != ISD::BRCOND &&
6111 User->getOpcode() != ISD::SETCC &&
6112 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6125 // Due to the ISEL shortcoming noted above, be conservative if this op is
6126 // likely to be selected as part of a load-modify-store instruction.
6127 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6128 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6129 if (UI->getOpcode() == ISD::STORE)
6132 // Otherwise use a regular EFLAGS-setting instruction.
6133 switch (Op.getNode()->getOpcode()) {
6134 default: llvm_unreachable("unexpected operator!");
6135 case ISD::SUB: Opcode = X86ISD::SUB; break;
6136 case ISD::OR: Opcode = X86ISD::OR; break;
6137 case ISD::XOR: Opcode = X86ISD::XOR; break;
6138 case ISD::AND: Opcode = X86ISD::AND; break;
6150 return SDValue(Op.getNode(), 1);
6157 // Emit a CMP with 0, which is the TEST pattern.
6158 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6159 DAG.getConstant(0, Op.getValueType()));
6161 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6162 SmallVector<SDValue, 4> Ops;
6163 for (unsigned i = 0; i != NumOperands; ++i)
6164 Ops.push_back(Op.getOperand(i));
6166 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6167 DAG.ReplaceAllUsesWith(Op, New);
6168 return SDValue(New.getNode(), 1);
6171 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6173 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6174 SelectionDAG &DAG) const {
6175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6176 if (C->getAPIntValue() == 0)
6177 return EmitTest(Op0, X86CC, DAG);
6179 DebugLoc dl = Op0.getDebugLoc();
6180 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6183 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6184 /// if it's possible.
6185 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6186 DebugLoc dl, SelectionDAG &DAG) const {
6187 SDValue Op0 = And.getOperand(0);
6188 SDValue Op1 = And.getOperand(1);
6189 if (Op0.getOpcode() == ISD::TRUNCATE)
6190 Op0 = Op0.getOperand(0);
6191 if (Op1.getOpcode() == ISD::TRUNCATE)
6192 Op1 = Op1.getOperand(0);
6195 if (Op1.getOpcode() == ISD::SHL)
6196 std::swap(Op0, Op1);
6197 if (Op0.getOpcode() == ISD::SHL) {
6198 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6199 if (And00C->getZExtValue() == 1) {
6200 // If we looked past a truncate, check that it's only truncating away
6202 unsigned BitWidth = Op0.getValueSizeInBits();
6203 unsigned AndBitWidth = And.getValueSizeInBits();
6204 if (BitWidth > AndBitWidth) {
6205 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6206 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6207 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6211 RHS = Op0.getOperand(1);
6213 } else if (Op1.getOpcode() == ISD::Constant) {
6214 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6215 SDValue AndLHS = Op0;
6216 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6217 LHS = AndLHS.getOperand(0);
6218 RHS = AndLHS.getOperand(1);
6222 if (LHS.getNode()) {
6223 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6224 // instruction. Since the shift amount is in-range-or-undefined, we know
6225 // that doing a bittest on the i32 value is ok. We extend to i32 because
6226 // the encoding for the i16 version is larger than the i32 version.
6227 // Also promote i16 to i32 for performance / code size reason.
6228 if (LHS.getValueType() == MVT::i8 ||
6229 LHS.getValueType() == MVT::i16)
6230 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6232 // If the operand types disagree, extend the shift amount to match. Since
6233 // BT ignores high bits (like shifts) we can use anyextend.
6234 if (LHS.getValueType() != RHS.getValueType())
6235 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6237 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6238 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6239 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6240 DAG.getConstant(Cond, MVT::i8), BT);
6246 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6247 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6248 SDValue Op0 = Op.getOperand(0);
6249 SDValue Op1 = Op.getOperand(1);
6250 DebugLoc dl = Op.getDebugLoc();
6251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6253 // Optimize to BT if possible.
6254 // Lower (X & (1 << N)) == 0 to BT(X, N).
6255 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6256 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6257 if (Op0.getOpcode() == ISD::AND &&
6259 Op1.getOpcode() == ISD::Constant &&
6260 cast<ConstantSDNode>(Op1)->isNullValue() &&
6261 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6262 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6263 if (NewSetCC.getNode())
6267 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6268 if (Op0.getOpcode() == X86ISD::SETCC &&
6269 Op1.getOpcode() == ISD::Constant &&
6270 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6271 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6272 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6273 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6274 bool Invert = (CC == ISD::SETNE) ^
6275 cast<ConstantSDNode>(Op1)->isNullValue();
6277 CCode = X86::GetOppositeBranchCondition(CCode);
6278 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6279 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6282 bool isFP = Op1.getValueType().isFloatingPoint();
6283 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6284 if (X86CC == X86::COND_INVALID)
6287 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6289 // Use sbb x, x to materialize carry bit into a GPR.
6290 if (X86CC == X86::COND_B)
6291 return DAG.getNode(ISD::AND, dl, MVT::i8,
6292 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6293 DAG.getConstant(X86CC, MVT::i8), Cond),
6294 DAG.getConstant(1, MVT::i8));
6296 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6297 DAG.getConstant(X86CC, MVT::i8), Cond);
6300 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6302 SDValue Op0 = Op.getOperand(0);
6303 SDValue Op1 = Op.getOperand(1);
6304 SDValue CC = Op.getOperand(2);
6305 EVT VT = Op.getValueType();
6306 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6307 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6308 DebugLoc dl = Op.getDebugLoc();
6312 EVT VT0 = Op0.getValueType();
6313 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6314 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6317 switch (SetCCOpcode) {
6320 case ISD::SETEQ: SSECC = 0; break;
6322 case ISD::SETGT: Swap = true; // Fallthrough
6324 case ISD::SETOLT: SSECC = 1; break;
6326 case ISD::SETGE: Swap = true; // Fallthrough
6328 case ISD::SETOLE: SSECC = 2; break;
6329 case ISD::SETUO: SSECC = 3; break;
6331 case ISD::SETNE: SSECC = 4; break;
6332 case ISD::SETULE: Swap = true;
6333 case ISD::SETUGE: SSECC = 5; break;
6334 case ISD::SETULT: Swap = true;
6335 case ISD::SETUGT: SSECC = 6; break;
6336 case ISD::SETO: SSECC = 7; break;
6339 std::swap(Op0, Op1);
6341 // In the two special cases we can't handle, emit two comparisons.
6343 if (SetCCOpcode == ISD::SETUEQ) {
6345 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6346 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6347 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6349 else if (SetCCOpcode == ISD::SETONE) {
6351 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6352 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6353 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6355 llvm_unreachable("Illegal FP comparison");
6357 // Handle all other FP comparisons here.
6358 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6361 // We are handling one of the integer comparisons here. Since SSE only has
6362 // GT and EQ comparisons for integer, swapping operands and multiple
6363 // operations may be required for some comparisons.
6364 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6365 bool Swap = false, Invert = false, FlipSigns = false;
6367 switch (VT.getSimpleVT().SimpleTy) {
6370 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6372 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6374 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6375 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6378 switch (SetCCOpcode) {
6380 case ISD::SETNE: Invert = true;
6381 case ISD::SETEQ: Opc = EQOpc; break;
6382 case ISD::SETLT: Swap = true;
6383 case ISD::SETGT: Opc = GTOpc; break;
6384 case ISD::SETGE: Swap = true;
6385 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6386 case ISD::SETULT: Swap = true;
6387 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6388 case ISD::SETUGE: Swap = true;
6389 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6392 std::swap(Op0, Op1);
6394 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6395 // bits of the inputs before performing those operations.
6397 EVT EltVT = VT.getVectorElementType();
6398 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6400 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6401 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6403 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6404 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6407 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6409 // If the logical-not of the result is required, perform that now.
6411 Result = DAG.getNOT(dl, Result, VT);
6416 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6417 static bool isX86LogicalCmp(SDValue Op) {
6418 unsigned Opc = Op.getNode()->getOpcode();
6419 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6421 if (Op.getResNo() == 1 &&
6422 (Opc == X86ISD::ADD ||
6423 Opc == X86ISD::SUB ||
6424 Opc == X86ISD::SMUL ||
6425 Opc == X86ISD::UMUL ||
6426 Opc == X86ISD::INC ||
6427 Opc == X86ISD::DEC ||
6428 Opc == X86ISD::OR ||
6429 Opc == X86ISD::XOR ||
6430 Opc == X86ISD::AND))
6436 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6437 bool addTest = true;
6438 SDValue Cond = Op.getOperand(0);
6439 DebugLoc dl = Op.getDebugLoc();
6442 if (Cond.getOpcode() == ISD::SETCC) {
6443 SDValue NewCond = LowerSETCC(Cond, DAG);
6444 if (NewCond.getNode())
6448 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6449 SDValue Op1 = Op.getOperand(1);
6450 SDValue Op2 = Op.getOperand(2);
6451 if (Cond.getOpcode() == X86ISD::SETCC &&
6452 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6453 SDValue Cmp = Cond.getOperand(1);
6454 if (Cmp.getOpcode() == X86ISD::CMP) {
6455 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6456 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6457 ConstantSDNode *RHSC =
6458 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6459 if (N1C && N1C->isAllOnesValue() &&
6460 N2C && N2C->isNullValue() &&
6461 RHSC && RHSC->isNullValue()) {
6462 SDValue CmpOp0 = Cmp.getOperand(0);
6463 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6464 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6465 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6466 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6471 // Look pass (and (setcc_carry (cmp ...)), 1).
6472 if (Cond.getOpcode() == ISD::AND &&
6473 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6474 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6475 if (C && C->getAPIntValue() == 1)
6476 Cond = Cond.getOperand(0);
6479 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6480 // setting operand in place of the X86ISD::SETCC.
6481 if (Cond.getOpcode() == X86ISD::SETCC ||
6482 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6483 CC = Cond.getOperand(0);
6485 SDValue Cmp = Cond.getOperand(1);
6486 unsigned Opc = Cmp.getOpcode();
6487 EVT VT = Op.getValueType();
6489 bool IllegalFPCMov = false;
6490 if (VT.isFloatingPoint() && !VT.isVector() &&
6491 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6492 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6494 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6495 Opc == X86ISD::BT) { // FIXME
6502 // Look pass the truncate.
6503 if (Cond.getOpcode() == ISD::TRUNCATE)
6504 Cond = Cond.getOperand(0);
6506 // We know the result of AND is compared against zero. Try to match
6508 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6509 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6510 if (NewSetCC.getNode()) {
6511 CC = NewSetCC.getOperand(0);
6512 Cond = NewSetCC.getOperand(1);
6519 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6520 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6523 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6524 // condition is true.
6525 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6526 SDValue Ops[] = { Op2, Op1, CC, Cond };
6527 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6530 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6531 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6532 // from the AND / OR.
6533 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6534 Opc = Op.getOpcode();
6535 if (Opc != ISD::OR && Opc != ISD::AND)
6537 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6538 Op.getOperand(0).hasOneUse() &&
6539 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6540 Op.getOperand(1).hasOneUse());
6543 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6544 // 1 and that the SETCC node has a single use.
6545 static bool isXor1OfSetCC(SDValue Op) {
6546 if (Op.getOpcode() != ISD::XOR)
6548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6549 if (N1C && N1C->getAPIntValue() == 1) {
6550 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6551 Op.getOperand(0).hasOneUse();
6556 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6557 bool addTest = true;
6558 SDValue Chain = Op.getOperand(0);
6559 SDValue Cond = Op.getOperand(1);
6560 SDValue Dest = Op.getOperand(2);
6561 DebugLoc dl = Op.getDebugLoc();
6564 if (Cond.getOpcode() == ISD::SETCC) {
6565 SDValue NewCond = LowerSETCC(Cond, DAG);
6566 if (NewCond.getNode())
6570 // FIXME: LowerXALUO doesn't handle these!!
6571 else if (Cond.getOpcode() == X86ISD::ADD ||
6572 Cond.getOpcode() == X86ISD::SUB ||
6573 Cond.getOpcode() == X86ISD::SMUL ||
6574 Cond.getOpcode() == X86ISD::UMUL)
6575 Cond = LowerXALUO(Cond, DAG);
6578 // Look pass (and (setcc_carry (cmp ...)), 1).
6579 if (Cond.getOpcode() == ISD::AND &&
6580 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6581 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6582 if (C && C->getAPIntValue() == 1)
6583 Cond = Cond.getOperand(0);
6586 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6587 // setting operand in place of the X86ISD::SETCC.
6588 if (Cond.getOpcode() == X86ISD::SETCC ||
6589 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6590 CC = Cond.getOperand(0);
6592 SDValue Cmp = Cond.getOperand(1);
6593 unsigned Opc = Cmp.getOpcode();
6594 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6595 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6599 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6603 // These can only come from an arithmetic instruction with overflow,
6604 // e.g. SADDO, UADDO.
6605 Cond = Cond.getNode()->getOperand(1);
6612 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6613 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6614 if (CondOpc == ISD::OR) {
6615 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6616 // two branches instead of an explicit OR instruction with a
6618 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6619 isX86LogicalCmp(Cmp)) {
6620 CC = Cond.getOperand(0).getOperand(0);
6621 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6622 Chain, Dest, CC, Cmp);
6623 CC = Cond.getOperand(1).getOperand(0);
6627 } else { // ISD::AND
6628 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6629 // two branches instead of an explicit AND instruction with a
6630 // separate test. However, we only do this if this block doesn't
6631 // have a fall-through edge, because this requires an explicit
6632 // jmp when the condition is false.
6633 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6634 isX86LogicalCmp(Cmp) &&
6635 Op.getNode()->hasOneUse()) {
6636 X86::CondCode CCode =
6637 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6638 CCode = X86::GetOppositeBranchCondition(CCode);
6639 CC = DAG.getConstant(CCode, MVT::i8);
6640 SDNode *User = *Op.getNode()->use_begin();
6641 // Look for an unconditional branch following this conditional branch.
6642 // We need this because we need to reverse the successors in order
6643 // to implement FCMP_OEQ.
6644 if (User->getOpcode() == ISD::BR) {
6645 SDValue FalseBB = User->getOperand(1);
6647 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6648 assert(NewBR == User);
6652 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6653 Chain, Dest, CC, Cmp);
6654 X86::CondCode CCode =
6655 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6656 CCode = X86::GetOppositeBranchCondition(CCode);
6657 CC = DAG.getConstant(CCode, MVT::i8);
6663 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6664 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6665 // It should be transformed during dag combiner except when the condition
6666 // is set by a arithmetics with overflow node.
6667 X86::CondCode CCode =
6668 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6669 CCode = X86::GetOppositeBranchCondition(CCode);
6670 CC = DAG.getConstant(CCode, MVT::i8);
6671 Cond = Cond.getOperand(0).getOperand(1);
6677 // Look pass the truncate.
6678 if (Cond.getOpcode() == ISD::TRUNCATE)
6679 Cond = Cond.getOperand(0);
6681 // We know the result of AND is compared against zero. Try to match
6683 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6684 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6685 if (NewSetCC.getNode()) {
6686 CC = NewSetCC.getOperand(0);
6687 Cond = NewSetCC.getOperand(1);
6694 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6695 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6697 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6698 Chain, Dest, CC, Cond);
6702 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6703 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6704 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6705 // that the guard pages used by the OS virtual memory manager are allocated in
6706 // correct sequence.
6708 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6709 SelectionDAG &DAG) const {
6710 assert(Subtarget->isTargetCygMing() &&
6711 "This should be used only on Cygwin/Mingw targets");
6712 DebugLoc dl = Op.getDebugLoc();
6715 SDValue Chain = Op.getOperand(0);
6716 SDValue Size = Op.getOperand(1);
6717 // FIXME: Ensure alignment here
6721 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6723 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6724 Flag = Chain.getValue(1);
6726 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6728 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6729 Flag = Chain.getValue(1);
6731 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6733 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6734 return DAG.getMergeValues(Ops1, 2, dl);
6737 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6738 MachineFunction &MF = DAG.getMachineFunction();
6739 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6741 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6742 DebugLoc dl = Op.getDebugLoc();
6744 if (!Subtarget->is64Bit()) {
6745 // vastart just stores the address of the VarArgsFrameIndex slot into the
6746 // memory location argument.
6747 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6749 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6754 // gp_offset (0 - 6 * 8)
6755 // fp_offset (48 - 48 + 8 * 16)
6756 // overflow_arg_area (point to parameters coming in memory).
6758 SmallVector<SDValue, 8> MemOps;
6759 SDValue FIN = Op.getOperand(1);
6761 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6762 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6764 FIN, SV, 0, false, false, 0);
6765 MemOps.push_back(Store);
6768 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6769 FIN, DAG.getIntPtrConstant(4));
6770 Store = DAG.getStore(Op.getOperand(0), dl,
6771 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6773 FIN, SV, 4, false, false, 0);
6774 MemOps.push_back(Store);
6776 // Store ptr to overflow_arg_area
6777 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6778 FIN, DAG.getIntPtrConstant(4));
6779 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6781 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
6783 MemOps.push_back(Store);
6785 // Store ptr to reg_save_area.
6786 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6787 FIN, DAG.getIntPtrConstant(8));
6788 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6790 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
6792 MemOps.push_back(Store);
6793 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6794 &MemOps[0], MemOps.size());
6797 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6798 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6799 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6801 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6805 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6806 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6807 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6808 SDValue Chain = Op.getOperand(0);
6809 SDValue DstPtr = Op.getOperand(1);
6810 SDValue SrcPtr = Op.getOperand(2);
6811 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6812 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6813 DebugLoc dl = Op.getDebugLoc();
6815 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6816 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6817 false, DstSV, 0, SrcSV, 0);
6821 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6822 DebugLoc dl = Op.getDebugLoc();
6823 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6825 default: return SDValue(); // Don't custom lower most intrinsics.
6826 // Comparison intrinsics.
6827 case Intrinsic::x86_sse_comieq_ss:
6828 case Intrinsic::x86_sse_comilt_ss:
6829 case Intrinsic::x86_sse_comile_ss:
6830 case Intrinsic::x86_sse_comigt_ss:
6831 case Intrinsic::x86_sse_comige_ss:
6832 case Intrinsic::x86_sse_comineq_ss:
6833 case Intrinsic::x86_sse_ucomieq_ss:
6834 case Intrinsic::x86_sse_ucomilt_ss:
6835 case Intrinsic::x86_sse_ucomile_ss:
6836 case Intrinsic::x86_sse_ucomigt_ss:
6837 case Intrinsic::x86_sse_ucomige_ss:
6838 case Intrinsic::x86_sse_ucomineq_ss:
6839 case Intrinsic::x86_sse2_comieq_sd:
6840 case Intrinsic::x86_sse2_comilt_sd:
6841 case Intrinsic::x86_sse2_comile_sd:
6842 case Intrinsic::x86_sse2_comigt_sd:
6843 case Intrinsic::x86_sse2_comige_sd:
6844 case Intrinsic::x86_sse2_comineq_sd:
6845 case Intrinsic::x86_sse2_ucomieq_sd:
6846 case Intrinsic::x86_sse2_ucomilt_sd:
6847 case Intrinsic::x86_sse2_ucomile_sd:
6848 case Intrinsic::x86_sse2_ucomigt_sd:
6849 case Intrinsic::x86_sse2_ucomige_sd:
6850 case Intrinsic::x86_sse2_ucomineq_sd: {
6852 ISD::CondCode CC = ISD::SETCC_INVALID;
6855 case Intrinsic::x86_sse_comieq_ss:
6856 case Intrinsic::x86_sse2_comieq_sd:
6860 case Intrinsic::x86_sse_comilt_ss:
6861 case Intrinsic::x86_sse2_comilt_sd:
6865 case Intrinsic::x86_sse_comile_ss:
6866 case Intrinsic::x86_sse2_comile_sd:
6870 case Intrinsic::x86_sse_comigt_ss:
6871 case Intrinsic::x86_sse2_comigt_sd:
6875 case Intrinsic::x86_sse_comige_ss:
6876 case Intrinsic::x86_sse2_comige_sd:
6880 case Intrinsic::x86_sse_comineq_ss:
6881 case Intrinsic::x86_sse2_comineq_sd:
6885 case Intrinsic::x86_sse_ucomieq_ss:
6886 case Intrinsic::x86_sse2_ucomieq_sd:
6887 Opc = X86ISD::UCOMI;
6890 case Intrinsic::x86_sse_ucomilt_ss:
6891 case Intrinsic::x86_sse2_ucomilt_sd:
6892 Opc = X86ISD::UCOMI;
6895 case Intrinsic::x86_sse_ucomile_ss:
6896 case Intrinsic::x86_sse2_ucomile_sd:
6897 Opc = X86ISD::UCOMI;
6900 case Intrinsic::x86_sse_ucomigt_ss:
6901 case Intrinsic::x86_sse2_ucomigt_sd:
6902 Opc = X86ISD::UCOMI;
6905 case Intrinsic::x86_sse_ucomige_ss:
6906 case Intrinsic::x86_sse2_ucomige_sd:
6907 Opc = X86ISD::UCOMI;
6910 case Intrinsic::x86_sse_ucomineq_ss:
6911 case Intrinsic::x86_sse2_ucomineq_sd:
6912 Opc = X86ISD::UCOMI;
6917 SDValue LHS = Op.getOperand(1);
6918 SDValue RHS = Op.getOperand(2);
6919 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6920 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6921 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6922 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6923 DAG.getConstant(X86CC, MVT::i8), Cond);
6924 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6926 // ptest intrinsics. The intrinsic these come from are designed to return
6927 // an integer value, not just an instruction so lower it to the ptest
6928 // pattern and a setcc for the result.
6929 case Intrinsic::x86_sse41_ptestz:
6930 case Intrinsic::x86_sse41_ptestc:
6931 case Intrinsic::x86_sse41_ptestnzc:{
6934 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6935 case Intrinsic::x86_sse41_ptestz:
6937 X86CC = X86::COND_E;
6939 case Intrinsic::x86_sse41_ptestc:
6941 X86CC = X86::COND_B;
6943 case Intrinsic::x86_sse41_ptestnzc:
6945 X86CC = X86::COND_A;
6949 SDValue LHS = Op.getOperand(1);
6950 SDValue RHS = Op.getOperand(2);
6951 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6952 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6953 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6954 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6957 // Fix vector shift instructions where the last operand is a non-immediate
6959 case Intrinsic::x86_sse2_pslli_w:
6960 case Intrinsic::x86_sse2_pslli_d:
6961 case Intrinsic::x86_sse2_pslli_q:
6962 case Intrinsic::x86_sse2_psrli_w:
6963 case Intrinsic::x86_sse2_psrli_d:
6964 case Intrinsic::x86_sse2_psrli_q:
6965 case Intrinsic::x86_sse2_psrai_w:
6966 case Intrinsic::x86_sse2_psrai_d:
6967 case Intrinsic::x86_mmx_pslli_w:
6968 case Intrinsic::x86_mmx_pslli_d:
6969 case Intrinsic::x86_mmx_pslli_q:
6970 case Intrinsic::x86_mmx_psrli_w:
6971 case Intrinsic::x86_mmx_psrli_d:
6972 case Intrinsic::x86_mmx_psrli_q:
6973 case Intrinsic::x86_mmx_psrai_w:
6974 case Intrinsic::x86_mmx_psrai_d: {
6975 SDValue ShAmt = Op.getOperand(2);
6976 if (isa<ConstantSDNode>(ShAmt))
6979 unsigned NewIntNo = 0;
6980 EVT ShAmtVT = MVT::v4i32;
6982 case Intrinsic::x86_sse2_pslli_w:
6983 NewIntNo = Intrinsic::x86_sse2_psll_w;
6985 case Intrinsic::x86_sse2_pslli_d:
6986 NewIntNo = Intrinsic::x86_sse2_psll_d;
6988 case Intrinsic::x86_sse2_pslli_q:
6989 NewIntNo = Intrinsic::x86_sse2_psll_q;
6991 case Intrinsic::x86_sse2_psrli_w:
6992 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6994 case Intrinsic::x86_sse2_psrli_d:
6995 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6997 case Intrinsic::x86_sse2_psrli_q:
6998 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7000 case Intrinsic::x86_sse2_psrai_w:
7001 NewIntNo = Intrinsic::x86_sse2_psra_w;
7003 case Intrinsic::x86_sse2_psrai_d:
7004 NewIntNo = Intrinsic::x86_sse2_psra_d;
7007 ShAmtVT = MVT::v2i32;
7009 case Intrinsic::x86_mmx_pslli_w:
7010 NewIntNo = Intrinsic::x86_mmx_psll_w;
7012 case Intrinsic::x86_mmx_pslli_d:
7013 NewIntNo = Intrinsic::x86_mmx_psll_d;
7015 case Intrinsic::x86_mmx_pslli_q:
7016 NewIntNo = Intrinsic::x86_mmx_psll_q;
7018 case Intrinsic::x86_mmx_psrli_w:
7019 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7021 case Intrinsic::x86_mmx_psrli_d:
7022 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7024 case Intrinsic::x86_mmx_psrli_q:
7025 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7027 case Intrinsic::x86_mmx_psrai_w:
7028 NewIntNo = Intrinsic::x86_mmx_psra_w;
7030 case Intrinsic::x86_mmx_psrai_d:
7031 NewIntNo = Intrinsic::x86_mmx_psra_d;
7033 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7039 // The vector shift intrinsics with scalars uses 32b shift amounts but
7040 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7044 ShOps[1] = DAG.getConstant(0, MVT::i32);
7045 if (ShAmtVT == MVT::v4i32) {
7046 ShOps[2] = DAG.getUNDEF(MVT::i32);
7047 ShOps[3] = DAG.getUNDEF(MVT::i32);
7048 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7050 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7053 EVT VT = Op.getValueType();
7054 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7055 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7056 DAG.getConstant(NewIntNo, MVT::i32),
7057 Op.getOperand(1), ShAmt);
7062 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7063 SelectionDAG &DAG) const {
7064 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7065 MFI->setReturnAddressIsTaken(true);
7067 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7068 DebugLoc dl = Op.getDebugLoc();
7071 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7073 DAG.getConstant(TD->getPointerSize(),
7074 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7075 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7076 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7078 NULL, 0, false, false, 0);
7081 // Just load the return address.
7082 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7083 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7084 RetAddrFI, NULL, 0, false, false, 0);
7087 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7089 MFI->setFrameAddressIsTaken(true);
7091 EVT VT = Op.getValueType();
7092 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7093 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7094 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7095 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7097 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7102 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7103 SelectionDAG &DAG) const {
7104 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7107 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7108 MachineFunction &MF = DAG.getMachineFunction();
7109 SDValue Chain = Op.getOperand(0);
7110 SDValue Offset = Op.getOperand(1);
7111 SDValue Handler = Op.getOperand(2);
7112 DebugLoc dl = Op.getDebugLoc();
7114 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7116 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7118 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7119 DAG.getIntPtrConstant(-TD->getPointerSize()));
7120 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7121 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7122 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7123 MF.getRegInfo().addLiveOut(StoreAddrReg);
7125 return DAG.getNode(X86ISD::EH_RETURN, dl,
7127 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7130 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7131 SelectionDAG &DAG) const {
7132 SDValue Root = Op.getOperand(0);
7133 SDValue Trmp = Op.getOperand(1); // trampoline
7134 SDValue FPtr = Op.getOperand(2); // nested function
7135 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7136 DebugLoc dl = Op.getDebugLoc();
7138 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7140 if (Subtarget->is64Bit()) {
7141 SDValue OutChains[6];
7143 // Large code-model.
7144 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7145 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7147 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7148 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7150 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7152 // Load the pointer to the nested function into R11.
7153 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7154 SDValue Addr = Trmp;
7155 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7156 Addr, TrmpAddr, 0, false, false, 0);
7158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7159 DAG.getConstant(2, MVT::i64));
7160 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7163 // Load the 'nest' parameter value into R10.
7164 // R10 is specified in X86CallingConv.td
7165 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7166 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7167 DAG.getConstant(10, MVT::i64));
7168 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7169 Addr, TrmpAddr, 10, false, false, 0);
7171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7172 DAG.getConstant(12, MVT::i64));
7173 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7176 // Jump to the nested function.
7177 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7178 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7179 DAG.getConstant(20, MVT::i64));
7180 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7181 Addr, TrmpAddr, 20, false, false, 0);
7183 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7185 DAG.getConstant(22, MVT::i64));
7186 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7187 TrmpAddr, 22, false, false, 0);
7190 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7191 return DAG.getMergeValues(Ops, 2, dl);
7193 const Function *Func =
7194 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7195 CallingConv::ID CC = Func->getCallingConv();
7200 llvm_unreachable("Unsupported calling convention");
7201 case CallingConv::C:
7202 case CallingConv::X86_StdCall: {
7203 // Pass 'nest' parameter in ECX.
7204 // Must be kept in sync with X86CallingConv.td
7207 // Check that ECX wasn't needed by an 'inreg' parameter.
7208 const FunctionType *FTy = Func->getFunctionType();
7209 const AttrListPtr &Attrs = Func->getAttributes();
7211 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7212 unsigned InRegCount = 0;
7215 for (FunctionType::param_iterator I = FTy->param_begin(),
7216 E = FTy->param_end(); I != E; ++I, ++Idx)
7217 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7218 // FIXME: should only count parameters that are lowered to integers.
7219 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7221 if (InRegCount > 2) {
7222 report_fatal_error("Nest register in use - reduce number of inreg"
7228 case CallingConv::X86_FastCall:
7229 case CallingConv::X86_ThisCall:
7230 case CallingConv::Fast:
7231 // Pass 'nest' parameter in EAX.
7232 // Must be kept in sync with X86CallingConv.td
7237 SDValue OutChains[4];
7240 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7241 DAG.getConstant(10, MVT::i32));
7242 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7244 // This is storing the opcode for MOV32ri.
7245 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7246 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7247 OutChains[0] = DAG.getStore(Root, dl,
7248 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7249 Trmp, TrmpAddr, 0, false, false, 0);
7251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7252 DAG.getConstant(1, MVT::i32));
7253 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7256 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7257 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7258 DAG.getConstant(5, MVT::i32));
7259 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7260 TrmpAddr, 5, false, false, 1);
7262 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7263 DAG.getConstant(6, MVT::i32));
7264 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7268 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7269 return DAG.getMergeValues(Ops, 2, dl);
7273 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7274 SelectionDAG &DAG) const {
7276 The rounding mode is in bits 11:10 of FPSR, and has the following
7283 FLT_ROUNDS, on the other hand, expects the following:
7290 To perform the conversion, we do:
7291 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7294 MachineFunction &MF = DAG.getMachineFunction();
7295 const TargetMachine &TM = MF.getTarget();
7296 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7297 unsigned StackAlignment = TFI.getStackAlignment();
7298 EVT VT = Op.getValueType();
7299 DebugLoc dl = Op.getDebugLoc();
7301 // Save FP Control Word to stack slot
7302 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7303 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7305 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7306 DAG.getEntryNode(), StackSlot);
7308 // Load FP Control Word from stack slot
7309 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7312 // Transform as necessary
7314 DAG.getNode(ISD::SRL, dl, MVT::i16,
7315 DAG.getNode(ISD::AND, dl, MVT::i16,
7316 CWD, DAG.getConstant(0x800, MVT::i16)),
7317 DAG.getConstant(11, MVT::i8));
7319 DAG.getNode(ISD::SRL, dl, MVT::i16,
7320 DAG.getNode(ISD::AND, dl, MVT::i16,
7321 CWD, DAG.getConstant(0x400, MVT::i16)),
7322 DAG.getConstant(9, MVT::i8));
7325 DAG.getNode(ISD::AND, dl, MVT::i16,
7326 DAG.getNode(ISD::ADD, dl, MVT::i16,
7327 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7328 DAG.getConstant(1, MVT::i16)),
7329 DAG.getConstant(3, MVT::i16));
7332 return DAG.getNode((VT.getSizeInBits() < 16 ?
7333 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7336 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7337 EVT VT = Op.getValueType();
7339 unsigned NumBits = VT.getSizeInBits();
7340 DebugLoc dl = Op.getDebugLoc();
7342 Op = Op.getOperand(0);
7343 if (VT == MVT::i8) {
7344 // Zero extend to i32 since there is not an i8 bsr.
7346 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7349 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7350 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7351 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7353 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7356 DAG.getConstant(NumBits+NumBits-1, OpVT),
7357 DAG.getConstant(X86::COND_E, MVT::i8),
7360 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7362 // Finally xor with NumBits-1.
7363 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7366 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7370 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7371 EVT VT = Op.getValueType();
7373 unsigned NumBits = VT.getSizeInBits();
7374 DebugLoc dl = Op.getDebugLoc();
7376 Op = Op.getOperand(0);
7377 if (VT == MVT::i8) {
7379 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7382 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7383 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7384 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7386 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7389 DAG.getConstant(NumBits, OpVT),
7390 DAG.getConstant(X86::COND_E, MVT::i8),
7393 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7396 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7400 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7401 EVT VT = Op.getValueType();
7402 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7403 DebugLoc dl = Op.getDebugLoc();
7405 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7406 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7407 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7408 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7409 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7411 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7412 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7413 // return AloBlo + AloBhi + AhiBlo;
7415 SDValue A = Op.getOperand(0);
7416 SDValue B = Op.getOperand(1);
7418 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7419 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7420 A, DAG.getConstant(32, MVT::i32));
7421 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7422 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7423 B, DAG.getConstant(32, MVT::i32));
7424 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7425 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7427 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7428 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7430 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7431 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7433 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7434 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7435 AloBhi, DAG.getConstant(32, MVT::i32));
7436 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7437 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7438 AhiBlo, DAG.getConstant(32, MVT::i32));
7439 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7440 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7445 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7446 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7447 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7448 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7449 // has only one use.
7450 SDNode *N = Op.getNode();
7451 SDValue LHS = N->getOperand(0);
7452 SDValue RHS = N->getOperand(1);
7453 unsigned BaseOp = 0;
7455 DebugLoc dl = Op.getDebugLoc();
7457 switch (Op.getOpcode()) {
7458 default: llvm_unreachable("Unknown ovf instruction!");
7460 // A subtract of one will be selected as a INC. Note that INC doesn't
7461 // set CF, so we can't do this for UADDO.
7462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7463 if (C->getAPIntValue() == 1) {
7464 BaseOp = X86ISD::INC;
7468 BaseOp = X86ISD::ADD;
7472 BaseOp = X86ISD::ADD;
7476 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7477 // set CF, so we can't do this for USUBO.
7478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7479 if (C->getAPIntValue() == 1) {
7480 BaseOp = X86ISD::DEC;
7484 BaseOp = X86ISD::SUB;
7488 BaseOp = X86ISD::SUB;
7492 BaseOp = X86ISD::SMUL;
7496 BaseOp = X86ISD::UMUL;
7501 // Also sets EFLAGS.
7502 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7503 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7506 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7507 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7509 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7513 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
7514 DebugLoc dl = Op.getDebugLoc();
7516 if (!Subtarget->hasSSE2())
7517 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
7518 DAG.getConstant(0, MVT::i32));
7520 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
7522 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
7524 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7525 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
7526 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
7527 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
7529 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
7530 if (!Op1 && !Op2 && !Op3 && Op4)
7531 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
7533 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
7534 if (Op1 && !Op2 && !Op3 && !Op4)
7535 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
7537 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
7539 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
7543 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7544 EVT T = Op.getValueType();
7545 DebugLoc dl = Op.getDebugLoc();
7548 switch(T.getSimpleVT().SimpleTy) {
7550 assert(false && "Invalid value type!");
7551 case MVT::i8: Reg = X86::AL; size = 1; break;
7552 case MVT::i16: Reg = X86::AX; size = 2; break;
7553 case MVT::i32: Reg = X86::EAX; size = 4; break;
7555 assert(Subtarget->is64Bit() && "Node not type legal!");
7556 Reg = X86::RAX; size = 8;
7559 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7560 Op.getOperand(2), SDValue());
7561 SDValue Ops[] = { cpIn.getValue(0),
7564 DAG.getTargetConstant(size, MVT::i8),
7566 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7567 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7569 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7573 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7574 SelectionDAG &DAG) const {
7575 assert(Subtarget->is64Bit() && "Result not type legalized?");
7576 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7577 SDValue TheChain = Op.getOperand(0);
7578 DebugLoc dl = Op.getDebugLoc();
7579 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7580 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7581 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7583 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7584 DAG.getConstant(32, MVT::i8));
7586 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7589 return DAG.getMergeValues(Ops, 2, dl);
7592 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7593 SelectionDAG &DAG) const {
7594 EVT SrcVT = Op.getOperand(0).getValueType();
7595 EVT DstVT = Op.getValueType();
7596 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7597 Subtarget->hasMMX() && !DisableMMX) &&
7598 "Unexpected custom BIT_CONVERT");
7599 assert((DstVT == MVT::i64 ||
7600 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7601 "Unexpected custom BIT_CONVERT");
7602 // i64 <=> MMX conversions are Legal.
7603 if (SrcVT==MVT::i64 && DstVT.isVector())
7605 if (DstVT==MVT::i64 && SrcVT.isVector())
7607 // MMX <=> MMX conversions are Legal.
7608 if (SrcVT.isVector() && DstVT.isVector())
7610 // All other conversions need to be expanded.
7613 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7614 SDNode *Node = Op.getNode();
7615 DebugLoc dl = Node->getDebugLoc();
7616 EVT T = Node->getValueType(0);
7617 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7618 DAG.getConstant(0, T), Node->getOperand(2));
7619 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7620 cast<AtomicSDNode>(Node)->getMemoryVT(),
7621 Node->getOperand(0),
7622 Node->getOperand(1), negOp,
7623 cast<AtomicSDNode>(Node)->getSrcValue(),
7624 cast<AtomicSDNode>(Node)->getAlignment());
7627 /// LowerOperation - Provide custom lowering hooks for some operations.
7629 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7630 switch (Op.getOpcode()) {
7631 default: llvm_unreachable("Should not custom lower this!");
7632 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
7633 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7634 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7635 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7636 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7637 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7638 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7639 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7640 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7641 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7642 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7643 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7644 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7645 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7646 case ISD::SHL_PARTS:
7647 case ISD::SRA_PARTS:
7648 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7649 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7650 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7651 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7652 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7653 case ISD::FABS: return LowerFABS(Op, DAG);
7654 case ISD::FNEG: return LowerFNEG(Op, DAG);
7655 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7656 case ISD::SETCC: return LowerSETCC(Op, DAG);
7657 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7658 case ISD::SELECT: return LowerSELECT(Op, DAG);
7659 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7660 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7661 case ISD::VASTART: return LowerVASTART(Op, DAG);
7662 case ISD::VAARG: return LowerVAARG(Op, DAG);
7663 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7664 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7665 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7666 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7667 case ISD::FRAME_TO_ARGS_OFFSET:
7668 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7669 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7670 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7671 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7672 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7673 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7674 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7675 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7681 case ISD::UMULO: return LowerXALUO(Op, DAG);
7682 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7683 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7687 void X86TargetLowering::
7688 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7689 SelectionDAG &DAG, unsigned NewOp) const {
7690 EVT T = Node->getValueType(0);
7691 DebugLoc dl = Node->getDebugLoc();
7692 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7694 SDValue Chain = Node->getOperand(0);
7695 SDValue In1 = Node->getOperand(1);
7696 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7697 Node->getOperand(2), DAG.getIntPtrConstant(0));
7698 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7699 Node->getOperand(2), DAG.getIntPtrConstant(1));
7700 SDValue Ops[] = { Chain, In1, In2L, In2H };
7701 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7703 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7704 cast<MemSDNode>(Node)->getMemOperand());
7705 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7706 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7707 Results.push_back(Result.getValue(2));
7710 /// ReplaceNodeResults - Replace a node with an illegal result type
7711 /// with a new node built out of custom code.
7712 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7713 SmallVectorImpl<SDValue>&Results,
7714 SelectionDAG &DAG) const {
7715 DebugLoc dl = N->getDebugLoc();
7716 switch (N->getOpcode()) {
7718 assert(false && "Do not know how to custom type legalize this operation!");
7720 case ISD::FP_TO_SINT: {
7721 std::pair<SDValue,SDValue> Vals =
7722 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7723 SDValue FIST = Vals.first, StackSlot = Vals.second;
7724 if (FIST.getNode() != 0) {
7725 EVT VT = N->getValueType(0);
7726 // Return a load from the stack slot.
7727 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7732 case ISD::READCYCLECOUNTER: {
7733 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7734 SDValue TheChain = N->getOperand(0);
7735 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7736 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7738 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7740 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7741 SDValue Ops[] = { eax, edx };
7742 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7743 Results.push_back(edx.getValue(1));
7746 case ISD::ATOMIC_CMP_SWAP: {
7747 EVT T = N->getValueType(0);
7748 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7749 SDValue cpInL, cpInH;
7750 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7751 DAG.getConstant(0, MVT::i32));
7752 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7753 DAG.getConstant(1, MVT::i32));
7754 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7755 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7757 SDValue swapInL, swapInH;
7758 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7759 DAG.getConstant(0, MVT::i32));
7760 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7761 DAG.getConstant(1, MVT::i32));
7762 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7764 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7765 swapInL.getValue(1));
7766 SDValue Ops[] = { swapInH.getValue(0),
7768 swapInH.getValue(1) };
7769 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7770 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7771 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7772 MVT::i32, Result.getValue(1));
7773 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7774 MVT::i32, cpOutL.getValue(2));
7775 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7776 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7777 Results.push_back(cpOutH.getValue(1));
7780 case ISD::ATOMIC_LOAD_ADD:
7781 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7783 case ISD::ATOMIC_LOAD_AND:
7784 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7786 case ISD::ATOMIC_LOAD_NAND:
7787 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7789 case ISD::ATOMIC_LOAD_OR:
7790 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7792 case ISD::ATOMIC_LOAD_SUB:
7793 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7795 case ISD::ATOMIC_LOAD_XOR:
7796 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7798 case ISD::ATOMIC_SWAP:
7799 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7804 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7806 default: return NULL;
7807 case X86ISD::BSF: return "X86ISD::BSF";
7808 case X86ISD::BSR: return "X86ISD::BSR";
7809 case X86ISD::SHLD: return "X86ISD::SHLD";
7810 case X86ISD::SHRD: return "X86ISD::SHRD";
7811 case X86ISD::FAND: return "X86ISD::FAND";
7812 case X86ISD::FOR: return "X86ISD::FOR";
7813 case X86ISD::FXOR: return "X86ISD::FXOR";
7814 case X86ISD::FSRL: return "X86ISD::FSRL";
7815 case X86ISD::FILD: return "X86ISD::FILD";
7816 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7817 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7818 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7819 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7820 case X86ISD::FLD: return "X86ISD::FLD";
7821 case X86ISD::FST: return "X86ISD::FST";
7822 case X86ISD::CALL: return "X86ISD::CALL";
7823 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7824 case X86ISD::BT: return "X86ISD::BT";
7825 case X86ISD::CMP: return "X86ISD::CMP";
7826 case X86ISD::COMI: return "X86ISD::COMI";
7827 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7828 case X86ISD::SETCC: return "X86ISD::SETCC";
7829 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7830 case X86ISD::CMOV: return "X86ISD::CMOV";
7831 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7832 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7833 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7834 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7835 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7836 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7837 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7838 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7839 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7840 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7841 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7842 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7843 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7844 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7845 case X86ISD::FMAX: return "X86ISD::FMAX";
7846 case X86ISD::FMIN: return "X86ISD::FMIN";
7847 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7848 case X86ISD::FRCP: return "X86ISD::FRCP";
7849 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7850 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7851 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7852 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7853 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7854 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7855 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7856 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7857 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7858 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7859 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7860 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7861 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7862 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7863 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7864 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7865 case X86ISD::VSHL: return "X86ISD::VSHL";
7866 case X86ISD::VSRL: return "X86ISD::VSRL";
7867 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7868 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7869 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7870 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7871 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7872 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7873 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7874 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7875 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7876 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7877 case X86ISD::ADD: return "X86ISD::ADD";
7878 case X86ISD::SUB: return "X86ISD::SUB";
7879 case X86ISD::SMUL: return "X86ISD::SMUL";
7880 case X86ISD::UMUL: return "X86ISD::UMUL";
7881 case X86ISD::INC: return "X86ISD::INC";
7882 case X86ISD::DEC: return "X86ISD::DEC";
7883 case X86ISD::OR: return "X86ISD::OR";
7884 case X86ISD::XOR: return "X86ISD::XOR";
7885 case X86ISD::AND: return "X86ISD::AND";
7886 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7887 case X86ISD::PTEST: return "X86ISD::PTEST";
7888 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7889 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7893 // isLegalAddressingMode - Return true if the addressing mode represented
7894 // by AM is legal for this target, for a load/store of the specified type.
7895 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7896 const Type *Ty) const {
7897 // X86 supports extremely general addressing modes.
7898 CodeModel::Model M = getTargetMachine().getCodeModel();
7900 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7901 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7906 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7908 // If a reference to this global requires an extra load, we can't fold it.
7909 if (isGlobalStubReference(GVFlags))
7912 // If BaseGV requires a register for the PIC base, we cannot also have a
7913 // BaseReg specified.
7914 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7917 // If lower 4G is not available, then we must use rip-relative addressing.
7918 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7928 // These scales always work.
7933 // These scales are formed with basereg+scalereg. Only accept if there is
7938 default: // Other stuff never works.
7946 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7947 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7949 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7950 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7951 if (NumBits1 <= NumBits2)
7956 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7957 if (!VT1.isInteger() || !VT2.isInteger())
7959 unsigned NumBits1 = VT1.getSizeInBits();
7960 unsigned NumBits2 = VT2.getSizeInBits();
7961 if (NumBits1 <= NumBits2)
7966 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7967 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7968 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7971 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7972 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7973 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7976 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7977 // i16 instructions are longer (0x66 prefix) and potentially slower.
7978 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7981 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7982 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7983 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7984 /// are assumed to be legal.
7986 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7988 // Very little shuffling can be done for 64-bit vectors right now.
7989 if (VT.getSizeInBits() == 64)
7990 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
7992 // FIXME: pshufb, blends, shifts.
7993 return (VT.getVectorNumElements() == 2 ||
7994 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7995 isMOVLMask(M, VT) ||
7996 isSHUFPMask(M, VT) ||
7997 isPSHUFDMask(M, VT) ||
7998 isPSHUFHWMask(M, VT) ||
7999 isPSHUFLWMask(M, VT) ||
8000 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8001 isUNPCKLMask(M, VT) ||
8002 isUNPCKHMask(M, VT) ||
8003 isUNPCKL_v_undef_Mask(M, VT) ||
8004 isUNPCKH_v_undef_Mask(M, VT));
8008 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8010 unsigned NumElts = VT.getVectorNumElements();
8011 // FIXME: This collection of masks seems suspect.
8014 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8015 return (isMOVLMask(Mask, VT) ||
8016 isCommutedMOVLMask(Mask, VT, true) ||
8017 isSHUFPMask(Mask, VT) ||
8018 isCommutedSHUFPMask(Mask, VT));
8023 //===----------------------------------------------------------------------===//
8024 // X86 Scheduler Hooks
8025 //===----------------------------------------------------------------------===//
8027 // private utility function
8029 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8030 MachineBasicBlock *MBB,
8037 TargetRegisterClass *RC,
8038 bool invSrc) const {
8039 // For the atomic bitwise operator, we generate
8042 // ld t1 = [bitinstr.addr]
8043 // op t2 = t1, [bitinstr.val]
8045 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8047 // fallthrough -->nextMBB
8048 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8049 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8050 MachineFunction::iterator MBBIter = MBB;
8053 /// First build the CFG
8054 MachineFunction *F = MBB->getParent();
8055 MachineBasicBlock *thisMBB = MBB;
8056 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8057 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8058 F->insert(MBBIter, newMBB);
8059 F->insert(MBBIter, nextMBB);
8061 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8062 nextMBB->splice(nextMBB->begin(), thisMBB,
8063 llvm::next(MachineBasicBlock::iterator(bInstr)),
8065 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8067 // Update thisMBB to fall through to newMBB
8068 thisMBB->addSuccessor(newMBB);
8070 // newMBB jumps to itself and fall through to nextMBB
8071 newMBB->addSuccessor(nextMBB);
8072 newMBB->addSuccessor(newMBB);
8074 // Insert instructions into newMBB based on incoming instruction
8075 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8076 "unexpected number of operands");
8077 DebugLoc dl = bInstr->getDebugLoc();
8078 MachineOperand& destOper = bInstr->getOperand(0);
8079 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8080 int numArgs = bInstr->getNumOperands() - 1;
8081 for (int i=0; i < numArgs; ++i)
8082 argOpers[i] = &bInstr->getOperand(i+1);
8084 // x86 address has 4 operands: base, index, scale, and displacement
8085 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8086 int valArgIndx = lastAddrIndx + 1;
8088 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8089 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8090 for (int i=0; i <= lastAddrIndx; ++i)
8091 (*MIB).addOperand(*argOpers[i]);
8093 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8095 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8100 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8101 assert((argOpers[valArgIndx]->isReg() ||
8102 argOpers[valArgIndx]->isImm()) &&
8104 if (argOpers[valArgIndx]->isReg())
8105 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8107 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8109 (*MIB).addOperand(*argOpers[valArgIndx]);
8111 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
8114 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8115 for (int i=0; i <= lastAddrIndx; ++i)
8116 (*MIB).addOperand(*argOpers[i]);
8118 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8119 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8120 bInstr->memoperands_end());
8122 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8126 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8128 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8132 // private utility function: 64 bit atomics on 32 bit host.
8134 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8135 MachineBasicBlock *MBB,
8140 bool invSrc) const {
8141 // For the atomic bitwise operator, we generate
8142 // thisMBB (instructions are in pairs, except cmpxchg8b)
8143 // ld t1,t2 = [bitinstr.addr]
8145 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8146 // op t5, t6 <- out1, out2, [bitinstr.val]
8147 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8148 // mov ECX, EBX <- t5, t6
8149 // mov EAX, EDX <- t1, t2
8150 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8151 // mov t3, t4 <- EAX, EDX
8153 // result in out1, out2
8154 // fallthrough -->nextMBB
8156 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8157 const unsigned LoadOpc = X86::MOV32rm;
8158 const unsigned NotOpc = X86::NOT32r;
8159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8160 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8161 MachineFunction::iterator MBBIter = MBB;
8164 /// First build the CFG
8165 MachineFunction *F = MBB->getParent();
8166 MachineBasicBlock *thisMBB = MBB;
8167 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8168 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8169 F->insert(MBBIter, newMBB);
8170 F->insert(MBBIter, nextMBB);
8172 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8173 nextMBB->splice(nextMBB->begin(), thisMBB,
8174 llvm::next(MachineBasicBlock::iterator(bInstr)),
8176 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8178 // Update thisMBB to fall through to newMBB
8179 thisMBB->addSuccessor(newMBB);
8181 // newMBB jumps to itself and fall through to nextMBB
8182 newMBB->addSuccessor(nextMBB);
8183 newMBB->addSuccessor(newMBB);
8185 DebugLoc dl = bInstr->getDebugLoc();
8186 // Insert instructions into newMBB based on incoming instruction
8187 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8188 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
8189 "unexpected number of operands");
8190 MachineOperand& dest1Oper = bInstr->getOperand(0);
8191 MachineOperand& dest2Oper = bInstr->getOperand(1);
8192 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8193 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
8194 argOpers[i] = &bInstr->getOperand(i+2);
8196 // We use some of the operands multiple times, so conservatively just
8197 // clear any kill flags that might be present.
8198 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8199 argOpers[i]->setIsKill(false);
8202 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8203 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8205 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8206 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8207 for (int i=0; i <= lastAddrIndx; ++i)
8208 (*MIB).addOperand(*argOpers[i]);
8209 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8210 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8211 // add 4 to displacement.
8212 for (int i=0; i <= lastAddrIndx-2; ++i)
8213 (*MIB).addOperand(*argOpers[i]);
8214 MachineOperand newOp3 = *(argOpers[3]);
8216 newOp3.setImm(newOp3.getImm()+4);
8218 newOp3.setOffset(newOp3.getOffset()+4);
8219 (*MIB).addOperand(newOp3);
8220 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8222 // t3/4 are defined later, at the bottom of the loop
8223 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8224 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8225 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8226 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8227 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8228 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8230 // The subsequent operations should be using the destination registers of
8231 //the PHI instructions.
8233 t1 = F->getRegInfo().createVirtualRegister(RC);
8234 t2 = F->getRegInfo().createVirtualRegister(RC);
8235 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8236 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8238 t1 = dest1Oper.getReg();
8239 t2 = dest2Oper.getReg();
8242 int valArgIndx = lastAddrIndx + 1;
8243 assert((argOpers[valArgIndx]->isReg() ||
8244 argOpers[valArgIndx]->isImm()) &&
8246 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8247 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8248 if (argOpers[valArgIndx]->isReg())
8249 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8251 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8252 if (regOpcL != X86::MOV32rr)
8254 (*MIB).addOperand(*argOpers[valArgIndx]);
8255 assert(argOpers[valArgIndx + 1]->isReg() ==
8256 argOpers[valArgIndx]->isReg());
8257 assert(argOpers[valArgIndx + 1]->isImm() ==
8258 argOpers[valArgIndx]->isImm());
8259 if (argOpers[valArgIndx + 1]->isReg())
8260 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8262 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8263 if (regOpcH != X86::MOV32rr)
8265 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8267 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8269 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
8272 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
8274 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
8277 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8278 for (int i=0; i <= lastAddrIndx; ++i)
8279 (*MIB).addOperand(*argOpers[i]);
8281 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8282 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8283 bInstr->memoperands_end());
8285 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
8286 MIB.addReg(X86::EAX);
8287 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
8288 MIB.addReg(X86::EDX);
8291 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8293 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8297 // private utility function
8299 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8300 MachineBasicBlock *MBB,
8301 unsigned cmovOpc) const {
8302 // For the atomic min/max operator, we generate
8305 // ld t1 = [min/max.addr]
8306 // mov t2 = [min/max.val]
8308 // cmov[cond] t2 = t1
8310 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8312 // fallthrough -->nextMBB
8314 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8315 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8316 MachineFunction::iterator MBBIter = MBB;
8319 /// First build the CFG
8320 MachineFunction *F = MBB->getParent();
8321 MachineBasicBlock *thisMBB = MBB;
8322 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8323 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8324 F->insert(MBBIter, newMBB);
8325 F->insert(MBBIter, nextMBB);
8327 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8328 nextMBB->splice(nextMBB->begin(), thisMBB,
8329 llvm::next(MachineBasicBlock::iterator(mInstr)),
8331 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8333 // Update thisMBB to fall through to newMBB
8334 thisMBB->addSuccessor(newMBB);
8336 // newMBB jumps to newMBB and fall through to nextMBB
8337 newMBB->addSuccessor(nextMBB);
8338 newMBB->addSuccessor(newMBB);
8340 DebugLoc dl = mInstr->getDebugLoc();
8341 // Insert instructions into newMBB based on incoming instruction
8342 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8343 "unexpected number of operands");
8344 MachineOperand& destOper = mInstr->getOperand(0);
8345 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8346 int numArgs = mInstr->getNumOperands() - 1;
8347 for (int i=0; i < numArgs; ++i)
8348 argOpers[i] = &mInstr->getOperand(i+1);
8350 // x86 address has 4 operands: base, index, scale, and displacement
8351 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8352 int valArgIndx = lastAddrIndx + 1;
8354 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8355 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8356 for (int i=0; i <= lastAddrIndx; ++i)
8357 (*MIB).addOperand(*argOpers[i]);
8359 // We only support register and immediate values
8360 assert((argOpers[valArgIndx]->isReg() ||
8361 argOpers[valArgIndx]->isImm()) &&
8364 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8365 if (argOpers[valArgIndx]->isReg())
8366 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
8368 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8369 (*MIB).addOperand(*argOpers[valArgIndx]);
8371 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8374 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8379 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8380 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8384 // Cmp and exchange if none has modified the memory location
8385 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8386 for (int i=0; i <= lastAddrIndx; ++i)
8387 (*MIB).addOperand(*argOpers[i]);
8389 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8390 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8391 mInstr->memoperands_end());
8393 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8394 MIB.addReg(X86::EAX);
8397 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8399 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
8403 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8404 // all of this code can be replaced with that in the .td file.
8406 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8407 unsigned numArgs, bool memArg) const {
8409 DebugLoc dl = MI->getDebugLoc();
8410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8414 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8416 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8418 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8420 for (unsigned i = 0; i < numArgs; ++i) {
8421 MachineOperand &Op = MI->getOperand(i+1);
8423 if (!(Op.isReg() && Op.isImplicit()))
8427 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8430 MI->eraseFromParent();
8436 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8438 MachineBasicBlock *MBB) const {
8439 // Emit code to save XMM registers to the stack. The ABI says that the
8440 // number of registers to save is given in %al, so it's theoretically
8441 // possible to do an indirect jump trick to avoid saving all of them,
8442 // however this code takes a simpler approach and just executes all
8443 // of the stores if %al is non-zero. It's less code, and it's probably
8444 // easier on the hardware branch predictor, and stores aren't all that
8445 // expensive anyway.
8447 // Create the new basic blocks. One block contains all the XMM stores,
8448 // and one block is the final destination regardless of whether any
8449 // stores were performed.
8450 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8451 MachineFunction *F = MBB->getParent();
8452 MachineFunction::iterator MBBIter = MBB;
8454 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8455 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8456 F->insert(MBBIter, XMMSaveMBB);
8457 F->insert(MBBIter, EndMBB);
8459 // Transfer the remainder of MBB and its successor edges to EndMBB.
8460 EndMBB->splice(EndMBB->begin(), MBB,
8461 llvm::next(MachineBasicBlock::iterator(MI)),
8463 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
8465 // The original block will now fall through to the XMM save block.
8466 MBB->addSuccessor(XMMSaveMBB);
8467 // The XMMSaveMBB will fall through to the end block.
8468 XMMSaveMBB->addSuccessor(EndMBB);
8470 // Now add the instructions.
8471 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8472 DebugLoc DL = MI->getDebugLoc();
8474 unsigned CountReg = MI->getOperand(0).getReg();
8475 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8476 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8478 if (!Subtarget->isTargetWin64()) {
8479 // If %al is 0, branch around the XMM save block.
8480 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8481 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8482 MBB->addSuccessor(EndMBB);
8485 // In the XMM save block, save all the XMM argument registers.
8486 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8487 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8488 MachineMemOperand *MMO =
8489 F->getMachineMemOperand(
8490 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8491 MachineMemOperand::MOStore, Offset,
8492 /*Size=*/16, /*Align=*/16);
8493 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8494 .addFrameIndex(RegSaveFrameIndex)
8495 .addImm(/*Scale=*/1)
8496 .addReg(/*IndexReg=*/0)
8497 .addImm(/*Disp=*/Offset)
8498 .addReg(/*Segment=*/0)
8499 .addReg(MI->getOperand(i).getReg())
8500 .addMemOperand(MMO);
8503 MI->eraseFromParent(); // The pseudo instruction is gone now.
8509 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8510 MachineBasicBlock *BB) const {
8511 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8512 DebugLoc DL = MI->getDebugLoc();
8514 // To "insert" a SELECT_CC instruction, we actually have to insert the
8515 // diamond control-flow pattern. The incoming instruction knows the
8516 // destination vreg to set, the condition code register to branch on, the
8517 // true/false values to select between, and a branch opcode to use.
8518 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8519 MachineFunction::iterator It = BB;
8525 // cmpTY ccX, r1, r2
8527 // fallthrough --> copy0MBB
8528 MachineBasicBlock *thisMBB = BB;
8529 MachineFunction *F = BB->getParent();
8530 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8531 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8532 F->insert(It, copy0MBB);
8533 F->insert(It, sinkMBB);
8535 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8536 // live into the sink and copy blocks.
8537 const MachineFunction *MF = BB->getParent();
8538 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8539 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8541 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
8542 const MachineOperand &MO = MI->getOperand(I);
8543 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
8544 unsigned Reg = MO.getReg();
8545 if (Reg != X86::EFLAGS) continue;
8546 copy0MBB->addLiveIn(Reg);
8547 sinkMBB->addLiveIn(Reg);
8550 // Transfer the remainder of BB and its successor edges to sinkMBB.
8551 sinkMBB->splice(sinkMBB->begin(), BB,
8552 llvm::next(MachineBasicBlock::iterator(MI)),
8554 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8556 // Add the true and fallthrough blocks as its successors.
8557 BB->addSuccessor(copy0MBB);
8558 BB->addSuccessor(sinkMBB);
8560 // Create the conditional branch instruction.
8562 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8563 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8566 // %FalseValue = ...
8567 // # fallthrough to sinkMBB
8568 copy0MBB->addSuccessor(sinkMBB);
8571 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8573 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8574 TII->get(X86::PHI), MI->getOperand(0).getReg())
8575 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8576 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8578 MI->eraseFromParent(); // The pseudo instruction is gone now.
8583 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8584 MachineBasicBlock *BB) const {
8585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8586 DebugLoc DL = MI->getDebugLoc();
8588 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8589 // non-trivial part is impdef of ESP.
8590 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8593 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
8594 .addExternalSymbol("_alloca")
8595 .addReg(X86::EAX, RegState::Implicit)
8596 .addReg(X86::ESP, RegState::Implicit)
8597 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8598 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8600 MI->eraseFromParent(); // The pseudo instruction is gone now.
8605 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8606 MachineBasicBlock *BB) const {
8607 // This is pretty easy. We're taking the value that we received from
8608 // our load from the relocation, sticking it in either RDI (x86-64)
8609 // or EAX and doing an indirect call. The return value will then
8610 // be in the normal return register.
8611 const X86InstrInfo *TII
8612 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8613 DebugLoc DL = MI->getDebugLoc();
8614 MachineFunction *F = BB->getParent();
8616 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8618 if (Subtarget->is64Bit()) {
8619 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8620 TII->get(X86::MOV64rm), X86::RDI)
8622 .addImm(0).addReg(0)
8623 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8624 MI->getOperand(3).getTargetFlags())
8626 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
8627 addDirectMem(MIB, X86::RDI);
8628 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8629 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8630 TII->get(X86::MOV32rm), X86::EAX)
8632 .addImm(0).addReg(0)
8633 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8634 MI->getOperand(3).getTargetFlags())
8636 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8637 addDirectMem(MIB, X86::EAX);
8639 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8640 TII->get(X86::MOV32rm), X86::EAX)
8641 .addReg(TII->getGlobalBaseReg(F))
8642 .addImm(0).addReg(0)
8643 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8644 MI->getOperand(3).getTargetFlags())
8646 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8647 addDirectMem(MIB, X86::EAX);
8650 MI->eraseFromParent(); // The pseudo instruction is gone now.
8655 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8656 MachineBasicBlock *BB) const {
8657 switch (MI->getOpcode()) {
8658 default: assert(false && "Unexpected instr type to insert");
8659 case X86::MINGW_ALLOCA:
8660 return EmitLoweredMingwAlloca(MI, BB);
8661 case X86::TLSCall_32:
8662 case X86::TLSCall_64:
8663 return EmitLoweredTLSCall(MI, BB);
8665 case X86::CMOV_V1I64:
8666 case X86::CMOV_FR32:
8667 case X86::CMOV_FR64:
8668 case X86::CMOV_V4F32:
8669 case X86::CMOV_V2F64:
8670 case X86::CMOV_V2I64:
8671 case X86::CMOV_GR16:
8672 case X86::CMOV_GR32:
8673 case X86::CMOV_RFP32:
8674 case X86::CMOV_RFP64:
8675 case X86::CMOV_RFP80:
8676 return EmitLoweredSelect(MI, BB);
8678 case X86::FP32_TO_INT16_IN_MEM:
8679 case X86::FP32_TO_INT32_IN_MEM:
8680 case X86::FP32_TO_INT64_IN_MEM:
8681 case X86::FP64_TO_INT16_IN_MEM:
8682 case X86::FP64_TO_INT32_IN_MEM:
8683 case X86::FP64_TO_INT64_IN_MEM:
8684 case X86::FP80_TO_INT16_IN_MEM:
8685 case X86::FP80_TO_INT32_IN_MEM:
8686 case X86::FP80_TO_INT64_IN_MEM: {
8687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8688 DebugLoc DL = MI->getDebugLoc();
8690 // Change the floating point control register to use "round towards zero"
8691 // mode when truncating to an integer value.
8692 MachineFunction *F = BB->getParent();
8693 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8694 addFrameReference(BuildMI(*BB, MI, DL,
8695 TII->get(X86::FNSTCW16m)), CWFrameIdx);
8697 // Load the old value of the high byte of the control word...
8699 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8700 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
8703 // Set the high part to be round to zero...
8704 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8707 // Reload the modified control word now...
8708 addFrameReference(BuildMI(*BB, MI, DL,
8709 TII->get(X86::FLDCW16m)), CWFrameIdx);
8711 // Restore the memory image of control word to original value
8712 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8715 // Get the X86 opcode to use.
8717 switch (MI->getOpcode()) {
8718 default: llvm_unreachable("illegal opcode!");
8719 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8720 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8721 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8722 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8723 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8724 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8725 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8726 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8727 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8731 MachineOperand &Op = MI->getOperand(0);
8733 AM.BaseType = X86AddressMode::RegBase;
8734 AM.Base.Reg = Op.getReg();
8736 AM.BaseType = X86AddressMode::FrameIndexBase;
8737 AM.Base.FrameIndex = Op.getIndex();
8739 Op = MI->getOperand(1);
8741 AM.Scale = Op.getImm();
8742 Op = MI->getOperand(2);
8744 AM.IndexReg = Op.getImm();
8745 Op = MI->getOperand(3);
8746 if (Op.isGlobal()) {
8747 AM.GV = Op.getGlobal();
8749 AM.Disp = Op.getImm();
8751 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
8752 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
8754 // Reload the original control word now.
8755 addFrameReference(BuildMI(*BB, MI, DL,
8756 TII->get(X86::FLDCW16m)), CWFrameIdx);
8758 MI->eraseFromParent(); // The pseudo instruction is gone now.
8761 // String/text processing lowering.
8762 case X86::PCMPISTRM128REG:
8763 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8764 case X86::PCMPISTRM128MEM:
8765 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8766 case X86::PCMPESTRM128REG:
8767 return EmitPCMP(MI, BB, 5, false /* in mem */);
8768 case X86::PCMPESTRM128MEM:
8769 return EmitPCMP(MI, BB, 5, true /* in mem */);
8772 case X86::ATOMAND32:
8773 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8774 X86::AND32ri, X86::MOV32rm,
8776 X86::NOT32r, X86::EAX,
8777 X86::GR32RegisterClass);
8779 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8780 X86::OR32ri, X86::MOV32rm,
8782 X86::NOT32r, X86::EAX,
8783 X86::GR32RegisterClass);
8784 case X86::ATOMXOR32:
8785 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8786 X86::XOR32ri, X86::MOV32rm,
8788 X86::NOT32r, X86::EAX,
8789 X86::GR32RegisterClass);
8790 case X86::ATOMNAND32:
8791 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8792 X86::AND32ri, X86::MOV32rm,
8794 X86::NOT32r, X86::EAX,
8795 X86::GR32RegisterClass, true);
8796 case X86::ATOMMIN32:
8797 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8798 case X86::ATOMMAX32:
8799 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8800 case X86::ATOMUMIN32:
8801 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8802 case X86::ATOMUMAX32:
8803 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8805 case X86::ATOMAND16:
8806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8807 X86::AND16ri, X86::MOV16rm,
8809 X86::NOT16r, X86::AX,
8810 X86::GR16RegisterClass);
8812 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8813 X86::OR16ri, X86::MOV16rm,
8815 X86::NOT16r, X86::AX,
8816 X86::GR16RegisterClass);
8817 case X86::ATOMXOR16:
8818 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8819 X86::XOR16ri, X86::MOV16rm,
8821 X86::NOT16r, X86::AX,
8822 X86::GR16RegisterClass);
8823 case X86::ATOMNAND16:
8824 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8825 X86::AND16ri, X86::MOV16rm,
8827 X86::NOT16r, X86::AX,
8828 X86::GR16RegisterClass, true);
8829 case X86::ATOMMIN16:
8830 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8831 case X86::ATOMMAX16:
8832 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8833 case X86::ATOMUMIN16:
8834 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8835 case X86::ATOMUMAX16:
8836 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8839 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8840 X86::AND8ri, X86::MOV8rm,
8842 X86::NOT8r, X86::AL,
8843 X86::GR8RegisterClass);
8845 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8846 X86::OR8ri, X86::MOV8rm,
8848 X86::NOT8r, X86::AL,
8849 X86::GR8RegisterClass);
8851 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8852 X86::XOR8ri, X86::MOV8rm,
8854 X86::NOT8r, X86::AL,
8855 X86::GR8RegisterClass);
8856 case X86::ATOMNAND8:
8857 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8858 X86::AND8ri, X86::MOV8rm,
8860 X86::NOT8r, X86::AL,
8861 X86::GR8RegisterClass, true);
8862 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8863 // This group is for 64-bit host.
8864 case X86::ATOMAND64:
8865 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8866 X86::AND64ri32, X86::MOV64rm,
8868 X86::NOT64r, X86::RAX,
8869 X86::GR64RegisterClass);
8871 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8872 X86::OR64ri32, X86::MOV64rm,
8874 X86::NOT64r, X86::RAX,
8875 X86::GR64RegisterClass);
8876 case X86::ATOMXOR64:
8877 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8878 X86::XOR64ri32, X86::MOV64rm,
8880 X86::NOT64r, X86::RAX,
8881 X86::GR64RegisterClass);
8882 case X86::ATOMNAND64:
8883 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8884 X86::AND64ri32, X86::MOV64rm,
8886 X86::NOT64r, X86::RAX,
8887 X86::GR64RegisterClass, true);
8888 case X86::ATOMMIN64:
8889 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8890 case X86::ATOMMAX64:
8891 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8892 case X86::ATOMUMIN64:
8893 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8894 case X86::ATOMUMAX64:
8895 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8897 // This group does 64-bit operations on a 32-bit host.
8898 case X86::ATOMAND6432:
8899 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8900 X86::AND32rr, X86::AND32rr,
8901 X86::AND32ri, X86::AND32ri,
8903 case X86::ATOMOR6432:
8904 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8905 X86::OR32rr, X86::OR32rr,
8906 X86::OR32ri, X86::OR32ri,
8908 case X86::ATOMXOR6432:
8909 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8910 X86::XOR32rr, X86::XOR32rr,
8911 X86::XOR32ri, X86::XOR32ri,
8913 case X86::ATOMNAND6432:
8914 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8915 X86::AND32rr, X86::AND32rr,
8916 X86::AND32ri, X86::AND32ri,
8918 case X86::ATOMADD6432:
8919 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8920 X86::ADD32rr, X86::ADC32rr,
8921 X86::ADD32ri, X86::ADC32ri,
8923 case X86::ATOMSUB6432:
8924 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8925 X86::SUB32rr, X86::SBB32rr,
8926 X86::SUB32ri, X86::SBB32ri,
8928 case X86::ATOMSWAP6432:
8929 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8930 X86::MOV32rr, X86::MOV32rr,
8931 X86::MOV32ri, X86::MOV32ri,
8933 case X86::VASTART_SAVE_XMM_REGS:
8934 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8938 //===----------------------------------------------------------------------===//
8939 // X86 Optimization Hooks
8940 //===----------------------------------------------------------------------===//
8942 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8946 const SelectionDAG &DAG,
8947 unsigned Depth) const {
8948 unsigned Opc = Op.getOpcode();
8949 assert((Opc >= ISD::BUILTIN_OP_END ||
8950 Opc == ISD::INTRINSIC_WO_CHAIN ||
8951 Opc == ISD::INTRINSIC_W_CHAIN ||
8952 Opc == ISD::INTRINSIC_VOID) &&
8953 "Should use MaskedValueIsZero if you don't know whether Op"
8954 " is a target node!");
8956 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8968 // These nodes' second result is a boolean.
8969 if (Op.getResNo() == 0)
8973 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8974 Mask.getBitWidth() - 1);
8979 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8980 /// node is a GlobalAddress + offset.
8981 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8982 const GlobalValue* &GA,
8983 int64_t &Offset) const {
8984 if (N->getOpcode() == X86ISD::Wrapper) {
8985 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8986 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8987 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8991 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8994 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8995 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8996 /// if the load addresses are consecutive, non-overlapping, and in the right
8998 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8999 const TargetLowering &TLI) {
9000 DebugLoc dl = N->getDebugLoc();
9001 EVT VT = N->getValueType(0);
9002 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9004 if (VT.getSizeInBits() != 128)
9007 SmallVector<SDValue, 16> Elts;
9008 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
9009 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
9011 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
9014 /// PerformShuffleCombine - Detect vector gather/scatter index generation
9015 /// and convert it from being a bunch of shuffles and extracts to a simple
9016 /// store and scalar loads to extract the elements.
9017 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
9018 const TargetLowering &TLI) {
9019 SDValue InputVector = N->getOperand(0);
9021 // Only operate on vectors of 4 elements, where the alternative shuffling
9022 // gets to be more expensive.
9023 if (InputVector.getValueType() != MVT::v4i32)
9026 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
9027 // single use which is a sign-extend or zero-extend, and all elements are
9029 SmallVector<SDNode *, 4> Uses;
9030 unsigned ExtractedElements = 0;
9031 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
9032 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
9033 if (UI.getUse().getResNo() != InputVector.getResNo())
9036 SDNode *Extract = *UI;
9037 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9040 if (Extract->getValueType(0) != MVT::i32)
9042 if (!Extract->hasOneUse())
9044 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9045 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9047 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9050 // Record which element was extracted.
9051 ExtractedElements |=
9052 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9054 Uses.push_back(Extract);
9057 // If not all the elements were used, this may not be worthwhile.
9058 if (ExtractedElements != 15)
9061 // Ok, we've now decided to do the transformation.
9062 DebugLoc dl = InputVector.getDebugLoc();
9064 // Store the value to a temporary stack slot.
9065 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9066 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
9067 0, false, false, 0);
9069 // Replace each use (extract) with a load of the appropriate element.
9070 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9071 UE = Uses.end(); UI != UE; ++UI) {
9072 SDNode *Extract = *UI;
9074 // Compute the element's address.
9075 SDValue Idx = Extract->getOperand(1);
9077 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9078 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9079 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9081 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
9082 OffsetVal, StackPtr);
9085 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
9086 ScalarAddr, NULL, 0, false, false, 0);
9088 // Replace the exact with the load.
9089 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9092 // The replacement was made in place; don't return anything.
9096 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9097 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9098 const X86Subtarget *Subtarget) {
9099 DebugLoc DL = N->getDebugLoc();
9100 SDValue Cond = N->getOperand(0);
9101 // Get the LHS/RHS of the select.
9102 SDValue LHS = N->getOperand(1);
9103 SDValue RHS = N->getOperand(2);
9105 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9106 // instructions match the semantics of the common C idiom x<y?x:y but not
9107 // x<=y?x:y, because of how they handle negative zero (which can be
9108 // ignored in unsafe-math mode).
9109 if (Subtarget->hasSSE2() &&
9110 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9111 Cond.getOpcode() == ISD::SETCC) {
9112 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9114 unsigned Opcode = 0;
9115 // Check for x CC y ? x : y.
9116 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9117 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9121 // Converting this to a min would handle NaNs incorrectly, and swapping
9122 // the operands would cause it to handle comparisons between positive
9123 // and negative zero incorrectly.
9124 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9125 if (!UnsafeFPMath &&
9126 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9128 std::swap(LHS, RHS);
9130 Opcode = X86ISD::FMIN;
9133 // Converting this to a min would handle comparisons between positive
9134 // and negative zero incorrectly.
9135 if (!UnsafeFPMath &&
9136 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9138 Opcode = X86ISD::FMIN;
9141 // Converting this to a min would handle both negative zeros and NaNs
9142 // incorrectly, but we can swap the operands to fix both.
9143 std::swap(LHS, RHS);
9147 Opcode = X86ISD::FMIN;
9151 // Converting this to a max would handle comparisons between positive
9152 // and negative zero incorrectly.
9153 if (!UnsafeFPMath &&
9154 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9156 Opcode = X86ISD::FMAX;
9159 // Converting this to a max would handle NaNs incorrectly, and swapping
9160 // the operands would cause it to handle comparisons between positive
9161 // and negative zero incorrectly.
9162 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9163 if (!UnsafeFPMath &&
9164 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9166 std::swap(LHS, RHS);
9168 Opcode = X86ISD::FMAX;
9171 // Converting this to a max would handle both negative zeros and NaNs
9172 // incorrectly, but we can swap the operands to fix both.
9173 std::swap(LHS, RHS);
9177 Opcode = X86ISD::FMAX;
9180 // Check for x CC y ? y : x -- a min/max with reversed arms.
9181 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9182 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9186 // Converting this to a min would handle comparisons between positive
9187 // and negative zero incorrectly, and swapping the operands would
9188 // cause it to handle NaNs incorrectly.
9189 if (!UnsafeFPMath &&
9190 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9191 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9193 std::swap(LHS, RHS);
9195 Opcode = X86ISD::FMIN;
9198 // Converting this to a min would handle NaNs incorrectly.
9199 if (!UnsafeFPMath &&
9200 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9202 Opcode = X86ISD::FMIN;
9205 // Converting this to a min would handle both negative zeros and NaNs
9206 // incorrectly, but we can swap the operands to fix both.
9207 std::swap(LHS, RHS);
9211 Opcode = X86ISD::FMIN;
9215 // Converting this to a max would handle NaNs incorrectly.
9216 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9218 Opcode = X86ISD::FMAX;
9221 // Converting this to a max would handle comparisons between positive
9222 // and negative zero incorrectly, and swapping the operands would
9223 // cause it to handle NaNs incorrectly.
9224 if (!UnsafeFPMath &&
9225 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9226 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9228 std::swap(LHS, RHS);
9230 Opcode = X86ISD::FMAX;
9233 // Converting this to a max would handle both negative zeros and NaNs
9234 // incorrectly, but we can swap the operands to fix both.
9235 std::swap(LHS, RHS);
9239 Opcode = X86ISD::FMAX;
9245 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9248 // If this is a select between two integer constants, try to do some
9250 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9251 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9252 // Don't do this for crazy integer types.
9253 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9254 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9255 // so that TrueC (the true value) is larger than FalseC.
9256 bool NeedsCondInvert = false;
9258 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9259 // Efficiently invertible.
9260 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9261 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9262 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9263 NeedsCondInvert = true;
9264 std::swap(TrueC, FalseC);
9267 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9268 if (FalseC->getAPIntValue() == 0 &&
9269 TrueC->getAPIntValue().isPowerOf2()) {
9270 if (NeedsCondInvert) // Invert the condition if needed.
9271 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9272 DAG.getConstant(1, Cond.getValueType()));
9274 // Zero extend the condition if needed.
9275 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9277 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9278 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9279 DAG.getConstant(ShAmt, MVT::i8));
9282 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9283 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9284 if (NeedsCondInvert) // Invert the condition if needed.
9285 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9286 DAG.getConstant(1, Cond.getValueType()));
9288 // Zero extend the condition if needed.
9289 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9290 FalseC->getValueType(0), Cond);
9291 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9292 SDValue(FalseC, 0));
9295 // Optimize cases that will turn into an LEA instruction. This requires
9296 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9297 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9298 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9299 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9301 bool isFastMultiplier = false;
9303 switch ((unsigned char)Diff) {
9305 case 1: // result = add base, cond
9306 case 2: // result = lea base( , cond*2)
9307 case 3: // result = lea base(cond, cond*2)
9308 case 4: // result = lea base( , cond*4)
9309 case 5: // result = lea base(cond, cond*4)
9310 case 8: // result = lea base( , cond*8)
9311 case 9: // result = lea base(cond, cond*8)
9312 isFastMultiplier = true;
9317 if (isFastMultiplier) {
9318 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9319 if (NeedsCondInvert) // Invert the condition if needed.
9320 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9321 DAG.getConstant(1, Cond.getValueType()));
9323 // Zero extend the condition if needed.
9324 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9326 // Scale the condition by the difference.
9328 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9329 DAG.getConstant(Diff, Cond.getValueType()));
9331 // Add the base if non-zero.
9332 if (FalseC->getAPIntValue() != 0)
9333 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9334 SDValue(FalseC, 0));
9344 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9345 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9346 TargetLowering::DAGCombinerInfo &DCI) {
9347 DebugLoc DL = N->getDebugLoc();
9349 // If the flag operand isn't dead, don't touch this CMOV.
9350 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9353 // If this is a select between two integer constants, try to do some
9354 // optimizations. Note that the operands are ordered the opposite of SELECT
9356 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9357 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9358 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9359 // larger than FalseC (the false value).
9360 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9362 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9363 CC = X86::GetOppositeBranchCondition(CC);
9364 std::swap(TrueC, FalseC);
9367 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9368 // This is efficient for any integer data type (including i8/i16) and
9370 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9371 SDValue Cond = N->getOperand(3);
9372 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9373 DAG.getConstant(CC, MVT::i8), Cond);
9375 // Zero extend the condition if needed.
9376 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9378 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9379 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9380 DAG.getConstant(ShAmt, MVT::i8));
9381 if (N->getNumValues() == 2) // Dead flag value?
9382 return DCI.CombineTo(N, Cond, SDValue());
9386 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9387 // for any integer data type, including i8/i16.
9388 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9389 SDValue Cond = N->getOperand(3);
9390 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9391 DAG.getConstant(CC, MVT::i8), Cond);
9393 // Zero extend the condition if needed.
9394 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9395 FalseC->getValueType(0), Cond);
9396 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9397 SDValue(FalseC, 0));
9399 if (N->getNumValues() == 2) // Dead flag value?
9400 return DCI.CombineTo(N, Cond, SDValue());
9404 // Optimize cases that will turn into an LEA instruction. This requires
9405 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9406 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9407 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9408 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9410 bool isFastMultiplier = false;
9412 switch ((unsigned char)Diff) {
9414 case 1: // result = add base, cond
9415 case 2: // result = lea base( , cond*2)
9416 case 3: // result = lea base(cond, cond*2)
9417 case 4: // result = lea base( , cond*4)
9418 case 5: // result = lea base(cond, cond*4)
9419 case 8: // result = lea base( , cond*8)
9420 case 9: // result = lea base(cond, cond*8)
9421 isFastMultiplier = true;
9426 if (isFastMultiplier) {
9427 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9428 SDValue Cond = N->getOperand(3);
9429 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9430 DAG.getConstant(CC, MVT::i8), Cond);
9431 // Zero extend the condition if needed.
9432 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9434 // Scale the condition by the difference.
9436 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9437 DAG.getConstant(Diff, Cond.getValueType()));
9439 // Add the base if non-zero.
9440 if (FalseC->getAPIntValue() != 0)
9441 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9442 SDValue(FalseC, 0));
9443 if (N->getNumValues() == 2) // Dead flag value?
9444 return DCI.CombineTo(N, Cond, SDValue());
9454 /// PerformMulCombine - Optimize a single multiply with constant into two
9455 /// in order to implement it with two cheaper instructions, e.g.
9456 /// LEA + SHL, LEA + LEA.
9457 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9458 TargetLowering::DAGCombinerInfo &DCI) {
9459 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9462 EVT VT = N->getValueType(0);
9466 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9469 uint64_t MulAmt = C->getZExtValue();
9470 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9473 uint64_t MulAmt1 = 0;
9474 uint64_t MulAmt2 = 0;
9475 if ((MulAmt % 9) == 0) {
9477 MulAmt2 = MulAmt / 9;
9478 } else if ((MulAmt % 5) == 0) {
9480 MulAmt2 = MulAmt / 5;
9481 } else if ((MulAmt % 3) == 0) {
9483 MulAmt2 = MulAmt / 3;
9486 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9487 DebugLoc DL = N->getDebugLoc();
9489 if (isPowerOf2_64(MulAmt2) &&
9490 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9491 // If second multiplifer is pow2, issue it first. We want the multiply by
9492 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9494 std::swap(MulAmt1, MulAmt2);
9497 if (isPowerOf2_64(MulAmt1))
9498 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9499 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9501 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9502 DAG.getConstant(MulAmt1, VT));
9504 if (isPowerOf2_64(MulAmt2))
9505 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9506 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9508 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9509 DAG.getConstant(MulAmt2, VT));
9511 // Do not add new nodes to DAG combiner worklist.
9512 DCI.CombineTo(N, NewMul, false);
9517 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9518 SDValue N0 = N->getOperand(0);
9519 SDValue N1 = N->getOperand(1);
9520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9521 EVT VT = N0.getValueType();
9523 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9524 // since the result of setcc_c is all zero's or all ones.
9525 if (N1C && N0.getOpcode() == ISD::AND &&
9526 N0.getOperand(1).getOpcode() == ISD::Constant) {
9527 SDValue N00 = N0.getOperand(0);
9528 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9529 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9530 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9531 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9532 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9533 APInt ShAmt = N1C->getAPIntValue();
9534 Mask = Mask.shl(ShAmt);
9536 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9537 N00, DAG.getConstant(Mask, VT));
9544 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9546 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9547 const X86Subtarget *Subtarget) {
9548 EVT VT = N->getValueType(0);
9549 if (!VT.isVector() && VT.isInteger() &&
9550 N->getOpcode() == ISD::SHL)
9551 return PerformSHLCombine(N, DAG);
9553 // On X86 with SSE2 support, we can transform this to a vector shift if
9554 // all elements are shifted by the same amount. We can't do this in legalize
9555 // because the a constant vector is typically transformed to a constant pool
9556 // so we have no knowledge of the shift amount.
9557 if (!Subtarget->hasSSE2())
9560 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9563 SDValue ShAmtOp = N->getOperand(1);
9564 EVT EltVT = VT.getVectorElementType();
9565 DebugLoc DL = N->getDebugLoc();
9566 SDValue BaseShAmt = SDValue();
9567 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9568 unsigned NumElts = VT.getVectorNumElements();
9570 for (; i != NumElts; ++i) {
9571 SDValue Arg = ShAmtOp.getOperand(i);
9572 if (Arg.getOpcode() == ISD::UNDEF) continue;
9576 for (; i != NumElts; ++i) {
9577 SDValue Arg = ShAmtOp.getOperand(i);
9578 if (Arg.getOpcode() == ISD::UNDEF) continue;
9579 if (Arg != BaseShAmt) {
9583 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9584 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9585 SDValue InVec = ShAmtOp.getOperand(0);
9586 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9587 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9589 for (; i != NumElts; ++i) {
9590 SDValue Arg = InVec.getOperand(i);
9591 if (Arg.getOpcode() == ISD::UNDEF) continue;
9595 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9597 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9598 if (C->getZExtValue() == SplatIdx)
9599 BaseShAmt = InVec.getOperand(1);
9602 if (BaseShAmt.getNode() == 0)
9603 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9604 DAG.getIntPtrConstant(0));
9608 // The shift amount is an i32.
9609 if (EltVT.bitsGT(MVT::i32))
9610 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9611 else if (EltVT.bitsLT(MVT::i32))
9612 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9614 // The shift amount is identical so we can do a vector shift.
9615 SDValue ValOp = N->getOperand(0);
9616 switch (N->getOpcode()) {
9618 llvm_unreachable("Unknown shift opcode!");
9621 if (VT == MVT::v2i64)
9622 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9623 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9625 if (VT == MVT::v4i32)
9626 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9627 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9629 if (VT == MVT::v8i16)
9630 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9631 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9635 if (VT == MVT::v4i32)
9636 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9637 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9639 if (VT == MVT::v8i16)
9640 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9641 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9645 if (VT == MVT::v2i64)
9646 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9647 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9649 if (VT == MVT::v4i32)
9650 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9651 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9653 if (VT == MVT::v8i16)
9654 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9655 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9662 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9663 TargetLowering::DAGCombinerInfo &DCI,
9664 const X86Subtarget *Subtarget) {
9665 if (DCI.isBeforeLegalizeOps())
9668 EVT VT = N->getValueType(0);
9669 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9672 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9673 SDValue N0 = N->getOperand(0);
9674 SDValue N1 = N->getOperand(1);
9675 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9677 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9679 if (!N0.hasOneUse() || !N1.hasOneUse())
9682 SDValue ShAmt0 = N0.getOperand(1);
9683 if (ShAmt0.getValueType() != MVT::i8)
9685 SDValue ShAmt1 = N1.getOperand(1);
9686 if (ShAmt1.getValueType() != MVT::i8)
9688 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9689 ShAmt0 = ShAmt0.getOperand(0);
9690 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9691 ShAmt1 = ShAmt1.getOperand(0);
9693 DebugLoc DL = N->getDebugLoc();
9694 unsigned Opc = X86ISD::SHLD;
9695 SDValue Op0 = N0.getOperand(0);
9696 SDValue Op1 = N1.getOperand(0);
9697 if (ShAmt0.getOpcode() == ISD::SUB) {
9699 std::swap(Op0, Op1);
9700 std::swap(ShAmt0, ShAmt1);
9703 unsigned Bits = VT.getSizeInBits();
9704 if (ShAmt1.getOpcode() == ISD::SUB) {
9705 SDValue Sum = ShAmt1.getOperand(0);
9706 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9707 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9708 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9709 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9710 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9711 return DAG.getNode(Opc, DL, VT,
9713 DAG.getNode(ISD::TRUNCATE, DL,
9716 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9717 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9719 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9720 return DAG.getNode(Opc, DL, VT,
9721 N0.getOperand(0), N1.getOperand(0),
9722 DAG.getNode(ISD::TRUNCATE, DL,
9729 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9730 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9731 const X86Subtarget *Subtarget) {
9732 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9733 // the FP state in cases where an emms may be missing.
9734 // A preferable solution to the general problem is to figure out the right
9735 // places to insert EMMS. This qualifies as a quick hack.
9737 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9738 StoreSDNode *St = cast<StoreSDNode>(N);
9739 EVT VT = St->getValue().getValueType();
9740 if (VT.getSizeInBits() != 64)
9743 const Function *F = DAG.getMachineFunction().getFunction();
9744 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9745 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9746 && Subtarget->hasSSE2();
9747 if ((VT.isVector() ||
9748 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9749 isa<LoadSDNode>(St->getValue()) &&
9750 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9751 St->getChain().hasOneUse() && !St->isVolatile()) {
9752 SDNode* LdVal = St->getValue().getNode();
9754 int TokenFactorIndex = -1;
9755 SmallVector<SDValue, 8> Ops;
9756 SDNode* ChainVal = St->getChain().getNode();
9757 // Must be a store of a load. We currently handle two cases: the load
9758 // is a direct child, and it's under an intervening TokenFactor. It is
9759 // possible to dig deeper under nested TokenFactors.
9760 if (ChainVal == LdVal)
9761 Ld = cast<LoadSDNode>(St->getChain());
9762 else if (St->getValue().hasOneUse() &&
9763 ChainVal->getOpcode() == ISD::TokenFactor) {
9764 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9765 if (ChainVal->getOperand(i).getNode() == LdVal) {
9766 TokenFactorIndex = i;
9767 Ld = cast<LoadSDNode>(St->getValue());
9769 Ops.push_back(ChainVal->getOperand(i));
9773 if (!Ld || !ISD::isNormalLoad(Ld))
9776 // If this is not the MMX case, i.e. we are just turning i64 load/store
9777 // into f64 load/store, avoid the transformation if there are multiple
9778 // uses of the loaded value.
9779 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9782 DebugLoc LdDL = Ld->getDebugLoc();
9783 DebugLoc StDL = N->getDebugLoc();
9784 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9785 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9787 if (Subtarget->is64Bit() || F64IsLegal) {
9788 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9789 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9790 Ld->getBasePtr(), Ld->getSrcValue(),
9791 Ld->getSrcValueOffset(), Ld->isVolatile(),
9792 Ld->isNonTemporal(), Ld->getAlignment());
9793 SDValue NewChain = NewLd.getValue(1);
9794 if (TokenFactorIndex != -1) {
9795 Ops.push_back(NewChain);
9796 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9799 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9800 St->getSrcValue(), St->getSrcValueOffset(),
9801 St->isVolatile(), St->isNonTemporal(),
9802 St->getAlignment());
9805 // Otherwise, lower to two pairs of 32-bit loads / stores.
9806 SDValue LoAddr = Ld->getBasePtr();
9807 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9808 DAG.getConstant(4, MVT::i32));
9810 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9811 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9812 Ld->isVolatile(), Ld->isNonTemporal(),
9813 Ld->getAlignment());
9814 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9815 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9816 Ld->isVolatile(), Ld->isNonTemporal(),
9817 MinAlign(Ld->getAlignment(), 4));
9819 SDValue NewChain = LoLd.getValue(1);
9820 if (TokenFactorIndex != -1) {
9821 Ops.push_back(LoLd);
9822 Ops.push_back(HiLd);
9823 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9827 LoAddr = St->getBasePtr();
9828 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9829 DAG.getConstant(4, MVT::i32));
9831 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9832 St->getSrcValue(), St->getSrcValueOffset(),
9833 St->isVolatile(), St->isNonTemporal(),
9834 St->getAlignment());
9835 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9837 St->getSrcValueOffset() + 4,
9839 St->isNonTemporal(),
9840 MinAlign(St->getAlignment(), 4));
9841 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9846 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9847 /// X86ISD::FXOR nodes.
9848 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9849 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9850 // F[X]OR(0.0, x) -> x
9851 // F[X]OR(x, 0.0) -> x
9852 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9853 if (C->getValueAPF().isPosZero())
9854 return N->getOperand(1);
9855 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9856 if (C->getValueAPF().isPosZero())
9857 return N->getOperand(0);
9861 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9862 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9863 // FAND(0.0, x) -> 0.0
9864 // FAND(x, 0.0) -> 0.0
9865 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9866 if (C->getValueAPF().isPosZero())
9867 return N->getOperand(0);
9868 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9869 if (C->getValueAPF().isPosZero())
9870 return N->getOperand(1);
9874 static SDValue PerformBTCombine(SDNode *N,
9876 TargetLowering::DAGCombinerInfo &DCI) {
9877 // BT ignores high bits in the bit index operand.
9878 SDValue Op1 = N->getOperand(1);
9879 if (Op1.hasOneUse()) {
9880 unsigned BitWidth = Op1.getValueSizeInBits();
9881 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9882 APInt KnownZero, KnownOne;
9883 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9884 !DCI.isBeforeLegalizeOps());
9885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9886 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9887 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9888 DCI.CommitTargetLoweringOpt(TLO);
9893 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9894 SDValue Op = N->getOperand(0);
9895 if (Op.getOpcode() == ISD::BIT_CONVERT)
9896 Op = Op.getOperand(0);
9897 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9898 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9899 VT.getVectorElementType().getSizeInBits() ==
9900 OpVT.getVectorElementType().getSizeInBits()) {
9901 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9906 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9907 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9908 // (and (i32 x86isd::setcc_carry), 1)
9909 // This eliminates the zext. This transformation is necessary because
9910 // ISD::SETCC is always legalized to i8.
9911 DebugLoc dl = N->getDebugLoc();
9912 SDValue N0 = N->getOperand(0);
9913 EVT VT = N->getValueType(0);
9914 if (N0.getOpcode() == ISD::AND &&
9916 N0.getOperand(0).hasOneUse()) {
9917 SDValue N00 = N0.getOperand(0);
9918 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9920 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9921 if (!C || C->getZExtValue() != 1)
9923 return DAG.getNode(ISD::AND, dl, VT,
9924 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9925 N00.getOperand(0), N00.getOperand(1)),
9926 DAG.getConstant(1, VT));
9932 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9933 DAGCombinerInfo &DCI) const {
9934 SelectionDAG &DAG = DCI.DAG;
9935 switch (N->getOpcode()) {
9937 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9938 case ISD::EXTRACT_VECTOR_ELT:
9939 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9940 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9941 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9942 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9945 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9946 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9947 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9949 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9950 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9951 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9952 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9953 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9959 /// isTypeDesirableForOp - Return true if the target has native support for
9960 /// the specified value type and it is 'desirable' to use the type for the
9961 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9962 /// instruction encodings are longer and some i16 instructions are slow.
9963 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9964 if (!isTypeLegal(VT))
9973 case ISD::SIGN_EXTEND:
9974 case ISD::ZERO_EXTEND:
9975 case ISD::ANY_EXTEND:
9988 static bool MayFoldLoad(SDValue Op) {
9989 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
9992 static bool MayFoldIntoStore(SDValue Op) {
9993 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
9996 /// IsDesirableToPromoteOp - This method query the target whether it is
9997 /// beneficial for dag combiner to promote the specified node. If true, it
9998 /// should return the desired promotion type by reference.
9999 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
10000 EVT VT = Op.getValueType();
10001 if (VT != MVT::i16)
10004 bool Promote = false;
10005 bool Commute = false;
10006 switch (Op.getOpcode()) {
10009 LoadSDNode *LD = cast<LoadSDNode>(Op);
10010 // If the non-extending load has a single use and it's not live out, then it
10011 // might be folded.
10012 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
10013 Op.hasOneUse()*/) {
10014 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10015 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
10016 // The only case where we'd want to promote LOAD (rather then it being
10017 // promoted as an operand is when it's only use is liveout.
10018 if (UI->getOpcode() != ISD::CopyToReg)
10025 case ISD::SIGN_EXTEND:
10026 case ISD::ZERO_EXTEND:
10027 case ISD::ANY_EXTEND:
10032 SDValue N0 = Op.getOperand(0);
10033 // Look out for (store (shl (load), x)).
10034 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10047 SDValue N0 = Op.getOperand(0);
10048 SDValue N1 = Op.getOperand(1);
10049 if (!Commute && MayFoldLoad(N1))
10051 // Avoid disabling potential load folding opportunities.
10052 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10054 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10064 //===----------------------------------------------------------------------===//
10065 // X86 Inline Assembly Support
10066 //===----------------------------------------------------------------------===//
10068 static bool LowerToBSwap(CallInst *CI) {
10069 // FIXME: this should verify that we are targetting a 486 or better. If not,
10070 // we will turn this bswap into something that will be lowered to logical ops
10071 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10072 // so don't worry about this.
10074 // Verify this is a simple bswap.
10075 if (CI->getNumArgOperands() != 1 ||
10076 CI->getType() != CI->getArgOperand(0)->getType() ||
10077 !CI->getType()->isIntegerTy())
10080 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10081 if (!Ty || Ty->getBitWidth() % 16 != 0)
10084 // Okay, we can do this xform, do so now.
10085 const Type *Tys[] = { Ty };
10086 Module *M = CI->getParent()->getParent()->getParent();
10087 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10089 Value *Op = CI->getArgOperand(0);
10090 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10092 CI->replaceAllUsesWith(Op);
10093 CI->eraseFromParent();
10097 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10098 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10099 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10101 std::string AsmStr = IA->getAsmString();
10103 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10104 SmallVector<StringRef, 4> AsmPieces;
10105 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10107 switch (AsmPieces.size()) {
10108 default: return false;
10110 AsmStr = AsmPieces[0];
10112 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10115 if (AsmPieces.size() == 2 &&
10116 (AsmPieces[0] == "bswap" ||
10117 AsmPieces[0] == "bswapq" ||
10118 AsmPieces[0] == "bswapl") &&
10119 (AsmPieces[1] == "$0" ||
10120 AsmPieces[1] == "${0:q}")) {
10121 // No need to check constraints, nothing other than the equivalent of
10122 // "=r,0" would be valid here.
10123 return LowerToBSwap(CI);
10125 // rorw $$8, ${0:w} --> llvm.bswap.i16
10126 if (CI->getType()->isIntegerTy(16) &&
10127 AsmPieces.size() == 3 &&
10128 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10129 AsmPieces[1] == "$$8," &&
10130 AsmPieces[2] == "${0:w}" &&
10131 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10133 const std::string &Constraints = IA->getConstraintString();
10134 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10135 std::sort(AsmPieces.begin(), AsmPieces.end());
10136 if (AsmPieces.size() == 4 &&
10137 AsmPieces[0] == "~{cc}" &&
10138 AsmPieces[1] == "~{dirflag}" &&
10139 AsmPieces[2] == "~{flags}" &&
10140 AsmPieces[3] == "~{fpsr}") {
10141 return LowerToBSwap(CI);
10146 if (CI->getType()->isIntegerTy(64) &&
10147 Constraints.size() >= 2 &&
10148 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10149 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10150 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10151 SmallVector<StringRef, 4> Words;
10152 SplitString(AsmPieces[0], Words, " \t");
10153 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10155 SplitString(AsmPieces[1], Words, " \t");
10156 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10158 SplitString(AsmPieces[2], Words, " \t,");
10159 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10160 Words[2] == "%edx") {
10161 return LowerToBSwap(CI);
10173 /// getConstraintType - Given a constraint letter, return the type of
10174 /// constraint it is for this target.
10175 X86TargetLowering::ConstraintType
10176 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10177 if (Constraint.size() == 1) {
10178 switch (Constraint[0]) {
10190 return C_RegisterClass;
10198 return TargetLowering::getConstraintType(Constraint);
10201 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10202 /// with another that has more specific requirements based on the type of the
10203 /// corresponding operand.
10204 const char *X86TargetLowering::
10205 LowerXConstraint(EVT ConstraintVT) const {
10206 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10207 // 'f' like normal targets.
10208 if (ConstraintVT.isFloatingPoint()) {
10209 if (Subtarget->hasSSE2())
10211 if (Subtarget->hasSSE1())
10215 return TargetLowering::LowerXConstraint(ConstraintVT);
10218 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10219 /// vector. If it is invalid, don't add anything to Ops.
10220 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10222 std::vector<SDValue>&Ops,
10223 SelectionDAG &DAG) const {
10224 SDValue Result(0, 0);
10226 switch (Constraint) {
10229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10230 if (C->getZExtValue() <= 31) {
10231 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10238 if (C->getZExtValue() <= 63) {
10239 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10246 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10247 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10254 if (C->getZExtValue() <= 255) {
10255 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10261 // 32-bit signed value
10262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10263 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10264 C->getSExtValue())) {
10265 // Widen to 64 bits here to get it sign extended.
10266 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10269 // FIXME gcc accepts some relocatable values here too, but only in certain
10270 // memory models; it's complicated.
10275 // 32-bit unsigned value
10276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10277 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10278 C->getZExtValue())) {
10279 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10283 // FIXME gcc accepts some relocatable values here too, but only in certain
10284 // memory models; it's complicated.
10288 // Literal immediates are always ok.
10289 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10290 // Widen to 64 bits here to get it sign extended.
10291 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10295 // In any sort of PIC mode addresses need to be computed at runtime by
10296 // adding in a register or some sort of table lookup. These can't
10297 // be used as immediates.
10298 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
10301 // If we are in non-pic codegen mode, we allow the address of a global (with
10302 // an optional displacement) to be used with 'i'.
10303 GlobalAddressSDNode *GA = 0;
10304 int64_t Offset = 0;
10306 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10308 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10309 Offset += GA->getOffset();
10311 } else if (Op.getOpcode() == ISD::ADD) {
10312 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10313 Offset += C->getZExtValue();
10314 Op = Op.getOperand(0);
10317 } else if (Op.getOpcode() == ISD::SUB) {
10318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10319 Offset += -C->getZExtValue();
10320 Op = Op.getOperand(0);
10325 // Otherwise, this isn't something we can handle, reject it.
10329 const GlobalValue *GV = GA->getGlobal();
10330 // If we require an extra load to get this address, as in PIC mode, we
10331 // can't accept it.
10332 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10333 getTargetMachine())))
10336 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
10337 GA->getValueType(0), Offset);
10342 if (Result.getNode()) {
10343 Ops.push_back(Result);
10346 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10349 std::vector<unsigned> X86TargetLowering::
10350 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10352 if (Constraint.size() == 1) {
10353 // FIXME: not handling fp-stack yet!
10354 switch (Constraint[0]) { // GCC X86 Constraint Letters
10355 default: break; // Unknown constraint letter
10356 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10357 if (Subtarget->is64Bit()) {
10358 if (VT == MVT::i32)
10359 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10360 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10361 X86::R10D,X86::R11D,X86::R12D,
10362 X86::R13D,X86::R14D,X86::R15D,
10363 X86::EBP, X86::ESP, 0);
10364 else if (VT == MVT::i16)
10365 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10366 X86::SI, X86::DI, X86::R8W,X86::R9W,
10367 X86::R10W,X86::R11W,X86::R12W,
10368 X86::R13W,X86::R14W,X86::R15W,
10369 X86::BP, X86::SP, 0);
10370 else if (VT == MVT::i8)
10371 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10372 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10373 X86::R10B,X86::R11B,X86::R12B,
10374 X86::R13B,X86::R14B,X86::R15B,
10375 X86::BPL, X86::SPL, 0);
10377 else if (VT == MVT::i64)
10378 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10379 X86::RSI, X86::RDI, X86::R8, X86::R9,
10380 X86::R10, X86::R11, X86::R12,
10381 X86::R13, X86::R14, X86::R15,
10382 X86::RBP, X86::RSP, 0);
10386 // 32-bit fallthrough
10387 case 'Q': // Q_REGS
10388 if (VT == MVT::i32)
10389 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10390 else if (VT == MVT::i16)
10391 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10392 else if (VT == MVT::i8)
10393 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10394 else if (VT == MVT::i64)
10395 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10400 return std::vector<unsigned>();
10403 std::pair<unsigned, const TargetRegisterClass*>
10404 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10406 // First, see if this is a constraint that directly corresponds to an LLVM
10408 if (Constraint.size() == 1) {
10409 // GCC Constraint Letters
10410 switch (Constraint[0]) {
10412 case 'r': // GENERAL_REGS
10413 case 'l': // INDEX_REGS
10415 return std::make_pair(0U, X86::GR8RegisterClass);
10416 if (VT == MVT::i16)
10417 return std::make_pair(0U, X86::GR16RegisterClass);
10418 if (VT == MVT::i32 || !Subtarget->is64Bit())
10419 return std::make_pair(0U, X86::GR32RegisterClass);
10420 return std::make_pair(0U, X86::GR64RegisterClass);
10421 case 'R': // LEGACY_REGS
10423 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10424 if (VT == MVT::i16)
10425 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10426 if (VT == MVT::i32 || !Subtarget->is64Bit())
10427 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10428 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10429 case 'f': // FP Stack registers.
10430 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10431 // value to the correct fpstack register class.
10432 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10433 return std::make_pair(0U, X86::RFP32RegisterClass);
10434 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10435 return std::make_pair(0U, X86::RFP64RegisterClass);
10436 return std::make_pair(0U, X86::RFP80RegisterClass);
10437 case 'y': // MMX_REGS if MMX allowed.
10438 if (!Subtarget->hasMMX()) break;
10439 return std::make_pair(0U, X86::VR64RegisterClass);
10440 case 'Y': // SSE_REGS if SSE2 allowed
10441 if (!Subtarget->hasSSE2()) break;
10443 case 'x': // SSE_REGS if SSE1 allowed
10444 if (!Subtarget->hasSSE1()) break;
10446 switch (VT.getSimpleVT().SimpleTy) {
10448 // Scalar SSE types.
10451 return std::make_pair(0U, X86::FR32RegisterClass);
10454 return std::make_pair(0U, X86::FR64RegisterClass);
10462 return std::make_pair(0U, X86::VR128RegisterClass);
10468 // Use the default implementation in TargetLowering to convert the register
10469 // constraint into a member of a register class.
10470 std::pair<unsigned, const TargetRegisterClass*> Res;
10471 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10473 // Not found as a standard register?
10474 if (Res.second == 0) {
10475 // Map st(0) -> st(7) -> ST0
10476 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10477 tolower(Constraint[1]) == 's' &&
10478 tolower(Constraint[2]) == 't' &&
10479 Constraint[3] == '(' &&
10480 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10481 Constraint[5] == ')' &&
10482 Constraint[6] == '}') {
10484 Res.first = X86::ST0+Constraint[4]-'0';
10485 Res.second = X86::RFP80RegisterClass;
10489 // GCC allows "st(0)" to be called just plain "st".
10490 if (StringRef("{st}").equals_lower(Constraint)) {
10491 Res.first = X86::ST0;
10492 Res.second = X86::RFP80RegisterClass;
10497 if (StringRef("{flags}").equals_lower(Constraint)) {
10498 Res.first = X86::EFLAGS;
10499 Res.second = X86::CCRRegisterClass;
10503 // 'A' means EAX + EDX.
10504 if (Constraint == "A") {
10505 Res.first = X86::EAX;
10506 Res.second = X86::GR32_ADRegisterClass;
10512 // Otherwise, check to see if this is a register class of the wrong value
10513 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10514 // turn into {ax},{dx}.
10515 if (Res.second->hasType(VT))
10516 return Res; // Correct type already, nothing to do.
10518 // All of the single-register GCC register classes map their values onto
10519 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10520 // really want an 8-bit or 32-bit register, map to the appropriate register
10521 // class and return the appropriate register.
10522 if (Res.second == X86::GR16RegisterClass) {
10523 if (VT == MVT::i8) {
10524 unsigned DestReg = 0;
10525 switch (Res.first) {
10527 case X86::AX: DestReg = X86::AL; break;
10528 case X86::DX: DestReg = X86::DL; break;
10529 case X86::CX: DestReg = X86::CL; break;
10530 case X86::BX: DestReg = X86::BL; break;
10533 Res.first = DestReg;
10534 Res.second = X86::GR8RegisterClass;
10536 } else if (VT == MVT::i32) {
10537 unsigned DestReg = 0;
10538 switch (Res.first) {
10540 case X86::AX: DestReg = X86::EAX; break;
10541 case X86::DX: DestReg = X86::EDX; break;
10542 case X86::CX: DestReg = X86::ECX; break;
10543 case X86::BX: DestReg = X86::EBX; break;
10544 case X86::SI: DestReg = X86::ESI; break;
10545 case X86::DI: DestReg = X86::EDI; break;
10546 case X86::BP: DestReg = X86::EBP; break;
10547 case X86::SP: DestReg = X86::ESP; break;
10550 Res.first = DestReg;
10551 Res.second = X86::GR32RegisterClass;
10553 } else if (VT == MVT::i64) {
10554 unsigned DestReg = 0;
10555 switch (Res.first) {
10557 case X86::AX: DestReg = X86::RAX; break;
10558 case X86::DX: DestReg = X86::RDX; break;
10559 case X86::CX: DestReg = X86::RCX; break;
10560 case X86::BX: DestReg = X86::RBX; break;
10561 case X86::SI: DestReg = X86::RSI; break;
10562 case X86::DI: DestReg = X86::RDI; break;
10563 case X86::BP: DestReg = X86::RBP; break;
10564 case X86::SP: DestReg = X86::RSP; break;
10567 Res.first = DestReg;
10568 Res.second = X86::GR64RegisterClass;
10571 } else if (Res.second == X86::FR32RegisterClass ||
10572 Res.second == X86::FR64RegisterClass ||
10573 Res.second == X86::VR128RegisterClass) {
10574 // Handle references to XMM physical registers that got mapped into the
10575 // wrong class. This can happen with constraints like {xmm0} where the
10576 // target independent register mapper will just pick the first match it can
10577 // find, ignoring the required type.
10578 if (VT == MVT::f32)
10579 Res.second = X86::FR32RegisterClass;
10580 else if (VT == MVT::f64)
10581 Res.second = X86::FR64RegisterClass;
10582 else if (X86::VR128RegisterClass->hasType(VT))
10583 Res.second = X86::VR128RegisterClass;