1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1737 return VT.changeVectorElementTypeToInteger();
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1810 if (Subtarget->hasInt256())
1812 if (Subtarget->hasFp256())
1815 if (Subtarget->hasSSE2())
1817 if (Subtarget->hasSSE1())
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1827 if (Subtarget->is64Bit() && Size >= 8)
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1906 switch (VT.SimpleTy) {
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1913 RRC = &X86::VR64RegClass;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1920 RRC = &X86::VR128RegClass;
1923 return std::make_pair(RRC, Cost);
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2098 if (!N->hasNUsesOfValue(1, 0))
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2210 enum StructReturnType {
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3948 for (i = 0; i != NumLaneElts; ++i) {
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4013 return isAlignrMask(Mask, VT, false);
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4023 return isAlignrMask(Mask, VT, true);
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4037 Mask[i] = idx - NumElems;
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4094 if ((signed)(Idx - l) != MaskVal[i])
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4108 unsigned NumElems = VT.getVectorNumElements();
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4127 unsigned NumElems = VT.getVectorNumElements();
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4201 else if (Mask[i] == i + 4)
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4214 // Some special combinations that can be optimized.
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4239 if (!MatchEvenMask && !MatchOddMask)
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4287 if (!isUndefOrEqual(BitI1, NumElts))
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4325 if (isUndefOrEqual(BitI1, NumElts))
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4371 if (!isUndefOrEqual(BitI1, j))
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4406 if (!isUndefOrEqual(BitI1, j))
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4442 if (!VT.is128BitVector())
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4489 return MatchA && MatchB;
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4513 return (FstHalf | (SndHalf << 4));
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4528 Imm8 |= Mask[i] << (i*2);
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4602 if (!isUndefOrEqual(Mask[0], 0))
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4669 unsigned NumElts = VT.getVectorNumElements();
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4707 // The index should be aligned on a vecWidth-bit boundary.
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4725 // The index should be aligned on a vecWidth-bit boundary.
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4937 bool X86::isZeroNode(SDValue Elt) {
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4952 if (VT.getVectorNumElements() != 4)
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4973 *LD = cast<LoadSDNode>(N);
4977 // Test whether the given value is a vector value which will be legalized
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4987 case ISD::ConstantFP:
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5158 Mask.push_back(i + NumElems);
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5258 return getLegalSplat(DAG, V1, EltNo);
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFB: {
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5375 DecodePSHUFBMask(RawMask, Mask);
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5398 DecodePSHUFBMask(C, Mask);
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6016 MVT VT = Op.getSimpleValueType();
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6025 switch (Op.getOpcode()) {
6027 // Unknown pattern found.
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6158 // Unsupported broadcast.
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6206 unsigned NumElems = Op.getNumOperands();
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6224 InsertIndices.push_back(i);
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6249 if (ExtractedFromVec == VecIn1)
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6255 if (!VecIn1.getNode())
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6310 if (In != Op.getOperand(0))
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6434 ExpectedVExtractIdx += 2;
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6587 if (InVec1 != Op1.getOperand(0))
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6653 if (!Subtarget->hasAVX())
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6709 // Convert this build_vector into a pair of horizontal binop followed by
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6737 // Convert this build_vector into two horizontal add/sub followed by
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6803 NonZeros |= (1 << i);
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6990 if (V.getNode()) return V;
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7016 V[i] = V[i*2]; // Must be a zero vector.
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7079 V[i] = DAG.getUNDEF(VT);
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7172 /// \brief Helper function to classify a mask as a single-input mask.
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7182 if (M >= (int)Mask.size())
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7294 /// \brief Try to emit a blend instruction for a shuffle.
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7316 switch (VT.SimpleTy) {
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7415 llvm_unreachable("Not a supported integer vector type!");
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7490 // The identity rotation isn't interesting, stop.
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7569 // If this is an index into a build_vector node, dig out the input value and
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7649 // Otherwise emit a sequence of unpacks.
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7685 auto Lower = [&](int Scale) -> SDValue {
7688 for (int i = 0; i < NumElements; ++i) {
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7696 // We no lorger are in the anyext case.
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7737 // No viable ext lowering found.
7741 /// \brief Try to lower insertion of a single element into a zero vector.
7743 /// This is a common pattern that we have especially efficient patterns to lower
7744 /// across all subtarget feature sets.
7745 static SDValue lowerVectorShuffleAsElementInsertion(
7746 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7747 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7748 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7750 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7751 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7753 if (Mask.size() == 2) {
7754 if (!Zeroable[V2Index ^ 1]) {
7755 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7756 // with 2 to flip from {2,3} to {0,1} and vice versa.
7757 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7758 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7759 if (Zeroable[V2Index])
7760 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7767 if (i != V2Index && !Zeroable[i])
7768 return SDValue(); // Not inserting into a zero vector.
7771 // Step over any bitcasts on either input so we can scan the actual
7772 // BUILD_VECTOR nodes.
7773 while (V1.getOpcode() == ISD::BITCAST)
7774 V1 = V1.getOperand(0);
7775 while (V2.getOpcode() == ISD::BITCAST)
7776 V2 = V2.getOperand(0);
7778 // Check for a single input from a SCALAR_TO_VECTOR node.
7779 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7780 // all the smarts here sunk into that routine. However, the current
7781 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7782 // vector shuffle lowering is dead.
7783 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7784 Mask[V2Index] == (int)Mask.size()) ||
7785 V2.getOpcode() == ISD::BUILD_VECTOR))
7788 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7790 // First, we need to zext the scalar if it is smaller than an i32.
7792 MVT EltVT = VT.getVectorElementType();
7793 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7794 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7795 // Zero-extend directly to i32.
7797 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7800 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7801 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7803 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7806 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7807 // the desired position. Otherwise it is more efficient to do a vector
7808 // shift left. We know that we can do a vector shift left because all
7809 // the inputs are zero.
7810 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7811 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7812 V2Shuffle[V2Index] = 0;
7813 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7815 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7817 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7819 V2Index * EltVT.getSizeInBits(),
7820 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7821 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7827 /// \brief Try to lower broadcast of a single element.
7829 /// For convenience, this code also bundles all of the subtarget feature set
7830 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7831 /// a convenient way to factor it out.
7832 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7834 const X86Subtarget *Subtarget,
7835 SelectionDAG &DAG) {
7836 if (!Subtarget->hasAVX())
7838 if (VT.isInteger() && !Subtarget->hasAVX2())
7841 // Check that the mask is a broadcast.
7842 int BroadcastIdx = -1;
7844 if (M >= 0 && BroadcastIdx == -1)
7846 else if (M >= 0 && M != BroadcastIdx)
7849 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7850 "a sorted mask where the broadcast "
7853 // Check if this is a broadcast of a scalar. We special case lowering for
7854 // scalars so that we can more effectively fold with loads.
7855 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7856 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7857 V = V.getOperand(BroadcastIdx);
7859 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7861 if (!Subtarget->hasAVX2() && !ISD::isNON_EXTLoad(V.getNode()))
7863 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7864 // We can't broadcast from a vector register w/o AVX2, and we can only
7865 // broadcast from the zero-element of a vector register.
7869 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7872 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7874 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7875 /// support for floating point shuffles but not integer shuffles. These
7876 /// instructions will incur a domain crossing penalty on some chips though so
7877 /// it is better to avoid lowering through this for integer vectors where
7879 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7880 const X86Subtarget *Subtarget,
7881 SelectionDAG &DAG) {
7883 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7884 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7885 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7887 ArrayRef<int> Mask = SVOp->getMask();
7888 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7890 if (isSingleInputShuffleMask(Mask)) {
7891 // Straight shuffle of a single input vector. Simulate this by using the
7892 // single input as both of the "inputs" to this instruction..
7893 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7895 if (Subtarget->hasAVX()) {
7896 // If we have AVX, we can use VPERMILPS which will allow folding a load
7897 // into the shuffle.
7898 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7899 DAG.getConstant(SHUFPDMask, MVT::i8));
7902 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7903 DAG.getConstant(SHUFPDMask, MVT::i8));
7905 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7906 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7908 // Use dedicated unpack instructions for masks that match their pattern.
7909 if (isShuffleEquivalent(Mask, 0, 2))
7910 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7911 if (isShuffleEquivalent(Mask, 1, 3))
7912 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7914 // If we have a single input, insert that into V1 if we can do so cheaply.
7915 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7916 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7917 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7920 if (Subtarget->hasSSE41())
7921 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7925 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7926 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7927 DAG.getConstant(SHUFPDMask, MVT::i8));
7930 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7932 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7933 /// the integer unit to minimize domain crossing penalties. However, for blends
7934 /// it falls back to the floating point shuffle operation with appropriate bit
7936 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7937 const X86Subtarget *Subtarget,
7938 SelectionDAG &DAG) {
7940 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7941 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7942 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7943 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7944 ArrayRef<int> Mask = SVOp->getMask();
7945 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7947 if (isSingleInputShuffleMask(Mask)) {
7948 // Check for being able to broadcast a single element.
7949 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
7950 Mask, Subtarget, DAG))
7953 // Straight shuffle of a single input vector. For everything from SSE2
7954 // onward this has a single fast instruction with no scary immediates.
7955 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7956 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7957 int WidenedMask[4] = {
7958 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7959 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7961 ISD::BITCAST, DL, MVT::v2i64,
7962 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7963 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7966 // Use dedicated unpack instructions for masks that match their pattern.
7967 if (isShuffleEquivalent(Mask, 0, 2))
7968 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7969 if (isShuffleEquivalent(Mask, 1, 3))
7970 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7972 // If we have a single input from V2 insert that into V1 if we can do so
7974 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7975 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7976 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7979 if (Subtarget->hasSSE41())
7980 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7984 // Try to use rotation instructions if available.
7985 if (Subtarget->hasSSSE3())
7986 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7987 DL, MVT::v2i64, V1, V2, Mask, DAG))
7990 // We implement this with SHUFPD which is pretty lame because it will likely
7991 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7992 // However, all the alternatives are still more cycles and newer chips don't
7993 // have this problem. It would be really nice if x86 had better shuffles here.
7994 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7995 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7996 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7997 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8000 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8002 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8003 /// It makes no assumptions about whether this is the *best* lowering, it simply
8005 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8006 ArrayRef<int> Mask, SDValue V1,
8007 SDValue V2, SelectionDAG &DAG) {
8008 SDValue LowV = V1, HighV = V2;
8009 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8012 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8014 if (NumV2Elements == 1) {
8016 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8019 // Compute the index adjacent to V2Index and in the same half by toggling
8021 int V2AdjIndex = V2Index ^ 1;
8023 if (Mask[V2AdjIndex] == -1) {
8024 // Handles all the cases where we have a single V2 element and an undef.
8025 // This will only ever happen in the high lanes because we commute the
8026 // vector otherwise.
8028 std::swap(LowV, HighV);
8029 NewMask[V2Index] -= 4;
8031 // Handle the case where the V2 element ends up adjacent to a V1 element.
8032 // To make this work, blend them together as the first step.
8033 int V1Index = V2AdjIndex;
8034 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8035 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8036 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8038 // Now proceed to reconstruct the final blend as we have the necessary
8039 // high or low half formed.
8046 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8047 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8049 } else if (NumV2Elements == 2) {
8050 if (Mask[0] < 4 && Mask[1] < 4) {
8051 // Handle the easy case where we have V1 in the low lanes and V2 in the
8055 } else if (Mask[2] < 4 && Mask[3] < 4) {
8056 // We also handle the reversed case because this utility may get called
8057 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8058 // arrange things in the right direction.
8064 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8065 // trying to place elements directly, just blend them and set up the final
8066 // shuffle to place them.
8068 // The first two blend mask elements are for V1, the second two are for
8070 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8071 Mask[2] < 4 ? Mask[2] : Mask[3],
8072 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8073 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8074 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8075 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8077 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8080 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8081 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8082 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8083 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8086 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8087 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8090 /// \brief Lower 4-lane 32-bit floating point shuffles.
8092 /// Uses instructions exclusively from the floating point unit to minimize
8093 /// domain crossing penalties, as these are sufficient to implement all v4f32
8095 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8096 const X86Subtarget *Subtarget,
8097 SelectionDAG &DAG) {
8099 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8100 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8101 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8102 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8103 ArrayRef<int> Mask = SVOp->getMask();
8104 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8107 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8109 if (NumV2Elements == 0) {
8110 // Check for being able to broadcast a single element.
8111 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8112 Mask, Subtarget, DAG))
8115 if (Subtarget->hasAVX()) {
8116 // If we have AVX, we can use VPERMILPS which will allow folding a load
8117 // into the shuffle.
8118 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8119 getV4X86ShuffleImm8ForMask(Mask, DAG));
8122 // Otherwise, use a straight shuffle of a single input vector. We pass the
8123 // input vector to both operands to simulate this with a SHUFPS.
8124 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8125 getV4X86ShuffleImm8ForMask(Mask, DAG));
8128 // Use dedicated unpack instructions for masks that match their pattern.
8129 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8130 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8131 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8132 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8134 // There are special ways we can lower some single-element blends. However, we
8135 // have custom ways we can lower more complex single-element blends below that
8136 // we defer to if both this and BLENDPS fail to match, so restrict this to
8137 // when the V2 input is targeting element 0 of the mask -- that is the fast
8139 if (NumV2Elements == 1 && Mask[0] >= 4)
8140 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8141 Mask, Subtarget, DAG))
8144 if (Subtarget->hasSSE41())
8145 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8149 // Check for whether we can use INSERTPS to perform the blend. We only use
8150 // INSERTPS when the V1 elements are already in the correct locations
8151 // because otherwise we can just always use two SHUFPS instructions which
8152 // are much smaller to encode than a SHUFPS and an INSERTPS.
8153 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8155 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8158 // When using INSERTPS we can zero any lane of the destination. Collect
8159 // the zero inputs into a mask and drop them from the lanes of V1 which
8160 // actually need to be present as inputs to the INSERTPS.
8161 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8163 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8164 bool InsertNeedsShuffle = false;
8166 for (int i = 0; i < 4; ++i)
8170 } else if (Mask[i] != i) {
8171 InsertNeedsShuffle = true;
8176 // We don't want to use INSERTPS or other insertion techniques if it will
8177 // require shuffling anyways.
8178 if (!InsertNeedsShuffle) {
8179 // If all of V1 is zeroable, replace it with undef.
8180 if ((ZMask | 1 << V2Index) == 0xF)
8181 V1 = DAG.getUNDEF(MVT::v4f32);
8183 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8184 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8186 // Insert the V2 element into the desired position.
8187 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8188 DAG.getConstant(InsertPSMask, MVT::i8));
8192 // Otherwise fall back to a SHUFPS lowering strategy.
8193 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8196 /// \brief Lower 4-lane i32 vector shuffles.
8198 /// We try to handle these with integer-domain shuffles where we can, but for
8199 /// blends we use the floating point domain blend instructions.
8200 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8201 const X86Subtarget *Subtarget,
8202 SelectionDAG &DAG) {
8204 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8205 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8206 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8208 ArrayRef<int> Mask = SVOp->getMask();
8209 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8211 // Whenever we can lower this as a zext, that instruction is strictly faster
8212 // than any alternative. It also allows us to fold memory operansd into the
8213 // shuffle in many cases.
8214 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8215 Mask, Subtarget, DAG))
8219 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8221 if (NumV2Elements == 0) {
8222 // Check for being able to broadcast a single element.
8223 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8224 Mask, Subtarget, DAG))
8227 // Straight shuffle of a single input vector. For everything from SSE2
8228 // onward this has a single fast instruction with no scary immediates.
8229 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8230 // but we aren't actually going to use the UNPCK instruction because doing
8231 // so prevents folding a load into this instruction or making a copy.
8232 const int UnpackLoMask[] = {0, 0, 1, 1};
8233 const int UnpackHiMask[] = {2, 2, 3, 3};
8234 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8235 Mask = UnpackLoMask;
8236 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8237 Mask = UnpackHiMask;
8239 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8240 getV4X86ShuffleImm8ForMask(Mask, DAG));
8243 // Use dedicated unpack instructions for masks that match their pattern.
8244 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8246 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8247 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8249 // There are special ways we can lower some single-element blends.
8250 if (NumV2Elements == 1)
8251 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8252 Mask, Subtarget, DAG))
8255 if (Subtarget->hasSSE41())
8256 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8260 // Try to use rotation instructions if available.
8261 if (Subtarget->hasSSSE3())
8262 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8263 DL, MVT::v4i32, V1, V2, Mask, DAG))
8266 // We implement this with SHUFPS because it can blend from two vectors.
8267 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8268 // up the inputs, bypassing domain shift penalties that we would encur if we
8269 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8271 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8272 DAG.getVectorShuffle(
8274 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8275 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8278 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8279 /// shuffle lowering, and the most complex part.
8281 /// The lowering strategy is to try to form pairs of input lanes which are
8282 /// targeted at the same half of the final vector, and then use a dword shuffle
8283 /// to place them onto the right half, and finally unpack the paired lanes into
8284 /// their final position.
8286 /// The exact breakdown of how to form these dword pairs and align them on the
8287 /// correct sides is really tricky. See the comments within the function for
8288 /// more of the details.
8289 static SDValue lowerV8I16SingleInputVectorShuffle(
8290 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8291 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8292 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8293 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8294 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8296 SmallVector<int, 4> LoInputs;
8297 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8298 [](int M) { return M >= 0; });
8299 std::sort(LoInputs.begin(), LoInputs.end());
8300 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8301 SmallVector<int, 4> HiInputs;
8302 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8303 [](int M) { return M >= 0; });
8304 std::sort(HiInputs.begin(), HiInputs.end());
8305 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8307 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8308 int NumHToL = LoInputs.size() - NumLToL;
8310 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8311 int NumHToH = HiInputs.size() - NumLToH;
8312 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8313 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8314 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8315 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8317 // Check for being able to broadcast a single element.
8318 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8319 Mask, Subtarget, DAG))
8322 // Use dedicated unpack instructions for masks that match their pattern.
8323 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8324 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8325 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8326 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8328 // Try to use rotation instructions if available.
8329 if (Subtarget->hasSSSE3())
8330 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8331 DL, MVT::v8i16, V, V, Mask, DAG))
8334 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8335 // such inputs we can swap two of the dwords across the half mark and end up
8336 // with <=2 inputs to each half in each half. Once there, we can fall through
8337 // to the generic code below. For example:
8339 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8340 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8342 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8343 // and an existing 2-into-2 on the other half. In this case we may have to
8344 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8345 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8346 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8347 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8348 // half than the one we target for fixing) will be fixed when we re-enter this
8349 // path. We will also combine away any sequence of PSHUFD instructions that
8350 // result into a single instruction. Here is an example of the tricky case:
8352 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8353 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8355 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8357 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8358 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8360 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8361 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8363 // The result is fine to be handled by the generic logic.
8364 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8365 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8366 int AOffset, int BOffset) {
8367 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8368 "Must call this with A having 3 or 1 inputs from the A half.");
8369 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8370 "Must call this with B having 1 or 3 inputs from the B half.");
8371 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8372 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8374 // Compute the index of dword with only one word among the three inputs in
8375 // a half by taking the sum of the half with three inputs and subtracting
8376 // the sum of the actual three inputs. The difference is the remaining
8379 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8380 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8381 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8382 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8383 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8384 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8385 int TripleNonInputIdx =
8386 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8387 TripleDWord = TripleNonInputIdx / 2;
8389 // We use xor with one to compute the adjacent DWord to whichever one the
8391 OneInputDWord = (OneInput / 2) ^ 1;
8393 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8394 // and BToA inputs. If there is also such a problem with the BToB and AToB
8395 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8396 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8397 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8398 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8399 // Compute how many inputs will be flipped by swapping these DWords. We
8401 // to balance this to ensure we don't form a 3-1 shuffle in the other
8403 int NumFlippedAToBInputs =
8404 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8405 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8406 int NumFlippedBToBInputs =
8407 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8408 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8409 if ((NumFlippedAToBInputs == 1 &&
8410 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8411 (NumFlippedBToBInputs == 1 &&
8412 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8413 // We choose whether to fix the A half or B half based on whether that
8414 // half has zero flipped inputs. At zero, we may not be able to fix it
8415 // with that half. We also bias towards fixing the B half because that
8416 // will more commonly be the high half, and we have to bias one way.
8417 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8418 ArrayRef<int> Inputs) {
8419 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8420 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8421 PinnedIdx ^ 1) != Inputs.end();
8422 // Determine whether the free index is in the flipped dword or the
8423 // unflipped dword based on where the pinned index is. We use this bit
8424 // in an xor to conditionally select the adjacent dword.
8425 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8426 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8427 FixFreeIdx) != Inputs.end();
8428 if (IsFixIdxInput == IsFixFreeIdxInput)
8430 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8431 FixFreeIdx) != Inputs.end();
8432 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8433 "We need to be changing the number of flipped inputs!");
8434 int PSHUFHalfMask[] = {0, 1, 2, 3};
8435 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8436 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8438 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8441 if (M != -1 && M == FixIdx)
8443 else if (M != -1 && M == FixFreeIdx)
8446 if (NumFlippedBToBInputs != 0) {
8448 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8449 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8451 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8453 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8454 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8459 int PSHUFDMask[] = {0, 1, 2, 3};
8460 PSHUFDMask[ADWord] = BDWord;
8461 PSHUFDMask[BDWord] = ADWord;
8462 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8463 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8464 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8465 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8467 // Adjust the mask to match the new locations of A and B.
8469 if (M != -1 && M/2 == ADWord)
8470 M = 2 * BDWord + M % 2;
8471 else if (M != -1 && M/2 == BDWord)
8472 M = 2 * ADWord + M % 2;
8474 // Recurse back into this routine to re-compute state now that this isn't
8475 // a 3 and 1 problem.
8476 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8479 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8480 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8481 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8482 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8484 // At this point there are at most two inputs to the low and high halves from
8485 // each half. That means the inputs can always be grouped into dwords and
8486 // those dwords can then be moved to the correct half with a dword shuffle.
8487 // We use at most one low and one high word shuffle to collect these paired
8488 // inputs into dwords, and finally a dword shuffle to place them.
8489 int PSHUFLMask[4] = {-1, -1, -1, -1};
8490 int PSHUFHMask[4] = {-1, -1, -1, -1};
8491 int PSHUFDMask[4] = {-1, -1, -1, -1};
8493 // First fix the masks for all the inputs that are staying in their
8494 // original halves. This will then dictate the targets of the cross-half
8496 auto fixInPlaceInputs =
8497 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8498 MutableArrayRef<int> SourceHalfMask,
8499 MutableArrayRef<int> HalfMask, int HalfOffset) {
8500 if (InPlaceInputs.empty())
8502 if (InPlaceInputs.size() == 1) {
8503 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8504 InPlaceInputs[0] - HalfOffset;
8505 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8508 if (IncomingInputs.empty()) {
8509 // Just fix all of the in place inputs.
8510 for (int Input : InPlaceInputs) {
8511 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8512 PSHUFDMask[Input / 2] = Input / 2;
8517 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8518 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8519 InPlaceInputs[0] - HalfOffset;
8520 // Put the second input next to the first so that they are packed into
8521 // a dword. We find the adjacent index by toggling the low bit.
8522 int AdjIndex = InPlaceInputs[0] ^ 1;
8523 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8524 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8525 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8527 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8528 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8530 // Now gather the cross-half inputs and place them into a free dword of
8531 // their target half.
8532 // FIXME: This operation could almost certainly be simplified dramatically to
8533 // look more like the 3-1 fixing operation.
8534 auto moveInputsToRightHalf = [&PSHUFDMask](
8535 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8536 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8537 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8539 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8540 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8542 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8544 int LowWord = Word & ~1;
8545 int HighWord = Word | 1;
8546 return isWordClobbered(SourceHalfMask, LowWord) ||
8547 isWordClobbered(SourceHalfMask, HighWord);
8550 if (IncomingInputs.empty())
8553 if (ExistingInputs.empty()) {
8554 // Map any dwords with inputs from them into the right half.
8555 for (int Input : IncomingInputs) {
8556 // If the source half mask maps over the inputs, turn those into
8557 // swaps and use the swapped lane.
8558 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8559 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8560 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8561 Input - SourceOffset;
8562 // We have to swap the uses in our half mask in one sweep.
8563 for (int &M : HalfMask)
8564 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8566 else if (M == Input)
8567 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8569 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8570 Input - SourceOffset &&
8571 "Previous placement doesn't match!");
8573 // Note that this correctly re-maps both when we do a swap and when
8574 // we observe the other side of the swap above. We rely on that to
8575 // avoid swapping the members of the input list directly.
8576 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8579 // Map the input's dword into the correct half.
8580 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8581 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8583 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8585 "Previous placement doesn't match!");
8588 // And just directly shift any other-half mask elements to be same-half
8589 // as we will have mirrored the dword containing the element into the
8590 // same position within that half.
8591 for (int &M : HalfMask)
8592 if (M >= SourceOffset && M < SourceOffset + 4) {
8593 M = M - SourceOffset + DestOffset;
8594 assert(M >= 0 && "This should never wrap below zero!");
8599 // Ensure we have the input in a viable dword of its current half. This
8600 // is particularly tricky because the original position may be clobbered
8601 // by inputs being moved and *staying* in that half.
8602 if (IncomingInputs.size() == 1) {
8603 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8604 int InputFixed = std::find(std::begin(SourceHalfMask),
8605 std::end(SourceHalfMask), -1) -
8606 std::begin(SourceHalfMask) + SourceOffset;
8607 SourceHalfMask[InputFixed - SourceOffset] =
8608 IncomingInputs[0] - SourceOffset;
8609 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8611 IncomingInputs[0] = InputFixed;
8613 } else if (IncomingInputs.size() == 2) {
8614 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8615 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8616 // We have two non-adjacent or clobbered inputs we need to extract from
8617 // the source half. To do this, we need to map them into some adjacent
8618 // dword slot in the source mask.
8619 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8620 IncomingInputs[1] - SourceOffset};
8622 // If there is a free slot in the source half mask adjacent to one of
8623 // the inputs, place the other input in it. We use (Index XOR 1) to
8624 // compute an adjacent index.
8625 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8626 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8627 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8628 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8629 InputsFixed[1] = InputsFixed[0] ^ 1;
8630 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8631 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8632 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8633 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8634 InputsFixed[0] = InputsFixed[1] ^ 1;
8635 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8636 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8637 // The two inputs are in the same DWord but it is clobbered and the
8638 // adjacent DWord isn't used at all. Move both inputs to the free
8640 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8641 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8642 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8643 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8645 // The only way we hit this point is if there is no clobbering
8646 // (because there are no off-half inputs to this half) and there is no
8647 // free slot adjacent to one of the inputs. In this case, we have to
8648 // swap an input with a non-input.
8649 for (int i = 0; i < 4; ++i)
8650 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8651 "We can't handle any clobbers here!");
8652 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8653 "Cannot have adjacent inputs here!");
8655 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8656 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8658 // We also have to update the final source mask in this case because
8659 // it may need to undo the above swap.
8660 for (int &M : FinalSourceHalfMask)
8661 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8662 M = InputsFixed[1] + SourceOffset;
8663 else if (M == InputsFixed[1] + SourceOffset)
8664 M = (InputsFixed[0] ^ 1) + SourceOffset;
8666 InputsFixed[1] = InputsFixed[0] ^ 1;
8669 // Point everything at the fixed inputs.
8670 for (int &M : HalfMask)
8671 if (M == IncomingInputs[0])
8672 M = InputsFixed[0] + SourceOffset;
8673 else if (M == IncomingInputs[1])
8674 M = InputsFixed[1] + SourceOffset;
8676 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8677 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8680 llvm_unreachable("Unhandled input size!");
8683 // Now hoist the DWord down to the right half.
8684 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8685 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8686 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8687 for (int &M : HalfMask)
8688 for (int Input : IncomingInputs)
8690 M = FreeDWord * 2 + Input % 2;
8692 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8693 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8694 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8695 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8697 // Now enact all the shuffles we've computed to move the inputs into their
8699 if (!isNoopShuffleMask(PSHUFLMask))
8700 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8701 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8702 if (!isNoopShuffleMask(PSHUFHMask))
8703 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8704 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8705 if (!isNoopShuffleMask(PSHUFDMask))
8706 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8707 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8708 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8709 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8711 // At this point, each half should contain all its inputs, and we can then
8712 // just shuffle them into their final position.
8713 assert(std::count_if(LoMask.begin(), LoMask.end(),
8714 [](int M) { return M >= 4; }) == 0 &&
8715 "Failed to lift all the high half inputs to the low mask!");
8716 assert(std::count_if(HiMask.begin(), HiMask.end(),
8717 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8718 "Failed to lift all the low half inputs to the high mask!");
8720 // Do a half shuffle for the low mask.
8721 if (!isNoopShuffleMask(LoMask))
8722 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8723 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8725 // Do a half shuffle with the high mask after shifting its values down.
8726 for (int &M : HiMask)
8729 if (!isNoopShuffleMask(HiMask))
8730 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8731 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8736 /// \brief Detect whether the mask pattern should be lowered through
8739 /// This essentially tests whether viewing the mask as an interleaving of two
8740 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8741 /// lowering it through interleaving is a significantly better strategy.
8742 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8743 int NumEvenInputs[2] = {0, 0};
8744 int NumOddInputs[2] = {0, 0};
8745 int NumLoInputs[2] = {0, 0};
8746 int NumHiInputs[2] = {0, 0};
8747 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8751 int InputIdx = Mask[i] >= Size;
8754 ++NumLoInputs[InputIdx];
8756 ++NumHiInputs[InputIdx];
8759 ++NumEvenInputs[InputIdx];
8761 ++NumOddInputs[InputIdx];
8764 // The minimum number of cross-input results for both the interleaved and
8765 // split cases. If interleaving results in fewer cross-input results, return
8767 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8768 NumEvenInputs[0] + NumOddInputs[1]);
8769 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8770 NumLoInputs[0] + NumHiInputs[1]);
8771 return InterleavedCrosses < SplitCrosses;
8774 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8776 /// This strategy only works when the inputs from each vector fit into a single
8777 /// half of that vector, and generally there are not so many inputs as to leave
8778 /// the in-place shuffles required highly constrained (and thus expensive). It
8779 /// shifts all the inputs into a single side of both input vectors and then
8780 /// uses an unpack to interleave these inputs in a single vector. At that
8781 /// point, we will fall back on the generic single input shuffle lowering.
8782 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8784 MutableArrayRef<int> Mask,
8785 const X86Subtarget *Subtarget,
8786 SelectionDAG &DAG) {
8787 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8788 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8789 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8790 for (int i = 0; i < 8; ++i)
8791 if (Mask[i] >= 0 && Mask[i] < 4)
8792 LoV1Inputs.push_back(i);
8793 else if (Mask[i] >= 4 && Mask[i] < 8)
8794 HiV1Inputs.push_back(i);
8795 else if (Mask[i] >= 8 && Mask[i] < 12)
8796 LoV2Inputs.push_back(i);
8797 else if (Mask[i] >= 12)
8798 HiV2Inputs.push_back(i);
8800 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8801 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8804 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8805 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8806 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8808 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8809 HiV1Inputs.size() + HiV2Inputs.size();
8811 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8812 ArrayRef<int> HiInputs, bool MoveToLo,
8814 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8815 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8816 if (BadInputs.empty())
8819 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8820 int MoveOffset = MoveToLo ? 0 : 4;
8822 if (GoodInputs.empty()) {
8823 for (int BadInput : BadInputs) {
8824 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8825 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8828 if (GoodInputs.size() == 2) {
8829 // If the low inputs are spread across two dwords, pack them into
8831 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8832 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8833 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8834 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8836 // Otherwise pin the good inputs.
8837 for (int GoodInput : GoodInputs)
8838 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8841 if (BadInputs.size() == 2) {
8842 // If we have two bad inputs then there may be either one or two good
8843 // inputs fixed in place. Find a fixed input, and then find the *other*
8844 // two adjacent indices by using modular arithmetic.
8846 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8847 [](int M) { return M >= 0; }) -
8848 std::begin(MoveMask);
8850 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8851 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8852 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8853 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8854 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8855 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8856 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8858 assert(BadInputs.size() == 1 && "All sizes handled");
8859 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8860 std::end(MoveMask), -1) -
8861 std::begin(MoveMask);
8862 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8863 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8867 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8870 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8872 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8875 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8876 // cross-half traffic in the final shuffle.
8878 // Munge the mask to be a single-input mask after the unpack merges the
8882 M = 2 * (M % 4) + (M / 8);
8884 return DAG.getVectorShuffle(
8885 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8886 DL, MVT::v8i16, V1, V2),
8887 DAG.getUNDEF(MVT::v8i16), Mask);
8890 /// \brief Generic lowering of 8-lane i16 shuffles.
8892 /// This handles both single-input shuffles and combined shuffle/blends with
8893 /// two inputs. The single input shuffles are immediately delegated to
8894 /// a dedicated lowering routine.
8896 /// The blends are lowered in one of three fundamental ways. If there are few
8897 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8898 /// of the input is significantly cheaper when lowered as an interleaving of
8899 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8900 /// halves of the inputs separately (making them have relatively few inputs)
8901 /// and then concatenate them.
8902 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8903 const X86Subtarget *Subtarget,
8904 SelectionDAG &DAG) {
8906 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8907 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8908 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8909 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8910 ArrayRef<int> OrigMask = SVOp->getMask();
8911 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8912 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8913 MutableArrayRef<int> Mask(MaskStorage);
8915 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8917 // Whenever we can lower this as a zext, that instruction is strictly faster
8918 // than any alternative.
8919 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8920 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8923 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8924 auto isV2 = [](int M) { return M >= 8; };
8926 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8927 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8929 if (NumV2Inputs == 0)
8930 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8932 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8933 "to be V1-input shuffles.");
8935 // There are special ways we can lower some single-element blends.
8936 if (NumV2Inputs == 1)
8937 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8938 Mask, Subtarget, DAG))
8941 if (Subtarget->hasSSE41())
8942 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8946 // Try to use rotation instructions if available.
8947 if (Subtarget->hasSSSE3())
8948 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8951 if (NumV1Inputs + NumV2Inputs <= 4)
8952 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8954 // Check whether an interleaving lowering is likely to be more efficient.
8955 // This isn't perfect but it is a strong heuristic that tends to work well on
8956 // the kinds of shuffles that show up in practice.
8958 // FIXME: Handle 1x, 2x, and 4x interleaving.
8959 if (shouldLowerAsInterleaving(Mask)) {
8960 // FIXME: Figure out whether we should pack these into the low or high
8963 int EMask[8], OMask[8];
8964 for (int i = 0; i < 4; ++i) {
8965 EMask[i] = Mask[2*i];
8966 OMask[i] = Mask[2*i + 1];
8971 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8972 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8974 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8977 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8978 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8980 for (int i = 0; i < 4; ++i) {
8981 LoBlendMask[i] = Mask[i];
8982 HiBlendMask[i] = Mask[i + 4];
8985 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8986 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8987 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8988 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8990 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8991 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8994 /// \brief Check whether a compaction lowering can be done by dropping even
8995 /// elements and compute how many times even elements must be dropped.
8997 /// This handles shuffles which take every Nth element where N is a power of
8998 /// two. Example shuffle masks:
9000 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9001 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9002 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9003 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9004 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9005 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9007 /// Any of these lanes can of course be undef.
9009 /// This routine only supports N <= 3.
9010 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9013 /// \returns N above, or the number of times even elements must be dropped if
9014 /// there is such a number. Otherwise returns zero.
9015 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9016 // Figure out whether we're looping over two inputs or just one.
9017 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9019 // The modulus for the shuffle vector entries is based on whether this is
9020 // a single input or not.
9021 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9022 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9023 "We should only be called with masks with a power-of-2 size!");
9025 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9027 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9028 // and 2^3 simultaneously. This is because we may have ambiguity with
9029 // partially undef inputs.
9030 bool ViableForN[3] = {true, true, true};
9032 for (int i = 0, e = Mask.size(); i < e; ++i) {
9033 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9038 bool IsAnyViable = false;
9039 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9040 if (ViableForN[j]) {
9043 // The shuffle mask must be equal to (i * 2^N) % M.
9044 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9047 ViableForN[j] = false;
9049 // Early exit if we exhaust the possible powers of two.
9054 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9058 // Return 0 as there is no viable power of two.
9062 /// \brief Generic lowering of v16i8 shuffles.
9064 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9065 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9066 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9067 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9069 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9070 const X86Subtarget *Subtarget,
9071 SelectionDAG &DAG) {
9073 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9074 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9075 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9076 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9077 ArrayRef<int> OrigMask = SVOp->getMask();
9078 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9080 // Try to use rotation instructions if available.
9081 if (Subtarget->hasSSSE3())
9082 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9086 // Try to use a zext lowering.
9087 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9088 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9091 int MaskStorage[16] = {
9092 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9093 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9094 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9095 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9096 MutableArrayRef<int> Mask(MaskStorage);
9097 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9098 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9101 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9103 // For single-input shuffles, there are some nicer lowering tricks we can use.
9104 if (NumV2Elements == 0) {
9105 // Check for being able to broadcast a single element.
9106 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9107 Mask, Subtarget, DAG))
9110 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9111 // Notably, this handles splat and partial-splat shuffles more efficiently.
9112 // However, it only makes sense if the pre-duplication shuffle simplifies
9113 // things significantly. Currently, this means we need to be able to
9114 // express the pre-duplication shuffle as an i16 shuffle.
9116 // FIXME: We should check for other patterns which can be widened into an
9117 // i16 shuffle as well.
9118 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9119 for (int i = 0; i < 16; i += 2)
9120 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9125 auto tryToWidenViaDuplication = [&]() -> SDValue {
9126 if (!canWidenViaDuplication(Mask))
9128 SmallVector<int, 4> LoInputs;
9129 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9130 [](int M) { return M >= 0 && M < 8; });
9131 std::sort(LoInputs.begin(), LoInputs.end());
9132 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9134 SmallVector<int, 4> HiInputs;
9135 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9136 [](int M) { return M >= 8; });
9137 std::sort(HiInputs.begin(), HiInputs.end());
9138 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9141 bool TargetLo = LoInputs.size() >= HiInputs.size();
9142 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9143 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9145 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9146 SmallDenseMap<int, int, 8> LaneMap;
9147 for (int I : InPlaceInputs) {
9148 PreDupI16Shuffle[I/2] = I/2;
9151 int j = TargetLo ? 0 : 4, je = j + 4;
9152 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9153 // Check if j is already a shuffle of this input. This happens when
9154 // there are two adjacent bytes after we move the low one.
9155 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9156 // If we haven't yet mapped the input, search for a slot into which
9158 while (j < je && PreDupI16Shuffle[j] != -1)
9162 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9165 // Map this input with the i16 shuffle.
9166 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9169 // Update the lane map based on the mapping we ended up with.
9170 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9173 ISD::BITCAST, DL, MVT::v16i8,
9174 DAG.getVectorShuffle(MVT::v8i16, DL,
9175 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9176 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9178 // Unpack the bytes to form the i16s that will be shuffled into place.
9179 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9180 MVT::v16i8, V1, V1);
9182 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9183 for (int i = 0; i < 16; ++i)
9184 if (Mask[i] != -1) {
9185 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9186 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9187 if (PostDupI16Shuffle[i / 2] == -1)
9188 PostDupI16Shuffle[i / 2] = MappedMask;
9190 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9191 "Conflicting entrties in the original shuffle!");
9194 ISD::BITCAST, DL, MVT::v16i8,
9195 DAG.getVectorShuffle(MVT::v8i16, DL,
9196 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9197 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9199 if (SDValue V = tryToWidenViaDuplication())
9203 // Check whether an interleaving lowering is likely to be more efficient.
9204 // This isn't perfect but it is a strong heuristic that tends to work well on
9205 // the kinds of shuffles that show up in practice.
9207 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9208 if (shouldLowerAsInterleaving(Mask)) {
9209 // FIXME: Figure out whether we should pack these into the low or high
9212 int EMask[16], OMask[16];
9213 for (int i = 0; i < 8; ++i) {
9214 EMask[i] = Mask[2*i];
9215 OMask[i] = Mask[2*i + 1];
9220 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9221 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9223 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9226 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9227 // with PSHUFB. It is important to do this before we attempt to generate any
9228 // blends but after all of the single-input lowerings. If the single input
9229 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9230 // want to preserve that and we can DAG combine any longer sequences into
9231 // a PSHUFB in the end. But once we start blending from multiple inputs,
9232 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9233 // and there are *very* few patterns that would actually be faster than the
9234 // PSHUFB approach because of its ability to zero lanes.
9236 // FIXME: The only exceptions to the above are blends which are exact
9237 // interleavings with direct instructions supporting them. We currently don't
9238 // handle those well here.
9239 if (Subtarget->hasSSSE3()) {
9242 for (int i = 0; i < 16; ++i)
9243 if (Mask[i] == -1) {
9244 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9246 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9248 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9250 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9251 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9252 if (isSingleInputShuffleMask(Mask))
9253 return V1; // Single inputs are easy.
9255 // Otherwise, blend the two.
9256 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9257 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9258 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9261 // There are special ways we can lower some single-element blends.
9262 if (NumV2Elements == 1)
9263 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9264 Mask, Subtarget, DAG))
9267 // Check whether a compaction lowering can be done. This handles shuffles
9268 // which take every Nth element for some even N. See the helper function for
9271 // We special case these as they can be particularly efficiently handled with
9272 // the PACKUSB instruction on x86 and they show up in common patterns of
9273 // rearranging bytes to truncate wide elements.
9274 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9275 // NumEvenDrops is the power of two stride of the elements. Another way of
9276 // thinking about it is that we need to drop the even elements this many
9277 // times to get the original input.
9278 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9280 // First we need to zero all the dropped bytes.
9281 assert(NumEvenDrops <= 3 &&
9282 "No support for dropping even elements more than 3 times.");
9283 // We use the mask type to pick which bytes are preserved based on how many
9284 // elements are dropped.
9285 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9286 SDValue ByteClearMask =
9287 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9288 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9289 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9291 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9293 // Now pack things back together.
9294 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9295 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9296 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9297 for (int i = 1; i < NumEvenDrops; ++i) {
9298 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9299 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9305 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9306 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9307 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9308 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9310 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9311 MutableArrayRef<int> V1HalfBlendMask,
9312 MutableArrayRef<int> V2HalfBlendMask) {
9313 for (int i = 0; i < 8; ++i)
9314 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9315 V1HalfBlendMask[i] = HalfMask[i];
9317 } else if (HalfMask[i] >= 16) {
9318 V2HalfBlendMask[i] = HalfMask[i] - 16;
9319 HalfMask[i] = i + 8;
9322 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9323 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9325 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9327 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9328 MutableArrayRef<int> HiBlendMask) {
9330 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9331 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9333 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9334 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9335 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9336 [](int M) { return M >= 0 && M % 2 == 1; })) {
9337 // Use a mask to drop the high bytes.
9338 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9339 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9340 DAG.getConstant(0x00FF, MVT::v8i16));
9342 // This will be a single vector shuffle instead of a blend so nuke V2.
9343 V2 = DAG.getUNDEF(MVT::v8i16);
9345 // Squash the masks to point directly into V1.
9346 for (int &M : LoBlendMask)
9349 for (int &M : HiBlendMask)
9353 // Otherwise just unpack the low half of V into V1 and the high half into
9354 // V2 so that we can blend them as i16s.
9355 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9356 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9357 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9358 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9361 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9362 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9363 return std::make_pair(BlendedLo, BlendedHi);
9365 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9366 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9367 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9369 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9370 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9372 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9375 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9377 /// This routine breaks down the specific type of 128-bit shuffle and
9378 /// dispatches to the lowering routines accordingly.
9379 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9380 MVT VT, const X86Subtarget *Subtarget,
9381 SelectionDAG &DAG) {
9382 switch (VT.SimpleTy) {
9384 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9386 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9388 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9390 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9392 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9394 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9397 llvm_unreachable("Unimplemented!");
9401 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9403 /// This routine just extracts two subvectors, shuffles them independently, and
9404 /// then concatenates them back together. This should work effectively with all
9405 /// AVX vector shuffle types.
9406 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9407 SDValue V2, ArrayRef<int> Mask,
9408 SelectionDAG &DAG) {
9409 assert(VT.getSizeInBits() >= 256 &&
9410 "Only for 256-bit or wider vector shuffles!");
9411 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9412 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9414 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9415 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9417 int NumElements = VT.getVectorNumElements();
9418 int SplitNumElements = NumElements / 2;
9419 MVT ScalarVT = VT.getScalarType();
9420 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9422 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9423 DAG.getIntPtrConstant(0));
9424 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9425 DAG.getIntPtrConstant(SplitNumElements));
9426 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9427 DAG.getIntPtrConstant(0));
9428 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9429 DAG.getIntPtrConstant(SplitNumElements));
9431 // Now create two 4-way blends of these half-width vectors.
9432 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9433 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9434 for (int i = 0; i < SplitNumElements; ++i) {
9435 int M = HalfMask[i];
9436 if (M >= NumElements) {
9437 V2BlendMask.push_back(M - NumElements);
9438 V1BlendMask.push_back(-1);
9439 BlendMask.push_back(SplitNumElements + i);
9440 } else if (M >= 0) {
9441 V2BlendMask.push_back(-1);
9442 V1BlendMask.push_back(M);
9443 BlendMask.push_back(i);
9445 V2BlendMask.push_back(-1);
9446 V1BlendMask.push_back(-1);
9447 BlendMask.push_back(-1);
9451 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9453 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9454 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9456 SDValue Lo = HalfBlend(LoMask);
9457 SDValue Hi = HalfBlend(HiMask);
9458 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9461 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9462 /// a permutation and blend of those lanes.
9464 /// This essentially blends the out-of-lane inputs to each lane into the lane
9465 /// from a permuted copy of the vector. This lowering strategy results in four
9466 /// instructions in the worst case for a single-input cross lane shuffle which
9467 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9468 /// of. Special cases for each particular shuffle pattern should be handled
9469 /// prior to trying this lowering.
9470 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9471 SDValue V1, SDValue V2,
9473 SelectionDAG &DAG) {
9474 // FIXME: This should probably be generalized for 512-bit vectors as well.
9475 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9476 int LaneSize = Mask.size() / 2;
9478 // If there are only inputs from one 128-bit lane, splitting will in fact be
9479 // less expensive. The flags track wether the given lane contains an element
9480 // that crosses to another lane.
9481 bool LaneCrossing[2] = {false, false};
9482 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9483 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9484 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9485 if (!LaneCrossing[0] || !LaneCrossing[1])
9486 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9488 if (isSingleInputShuffleMask(Mask)) {
9489 SmallVector<int, 32> FlippedBlendMask;
9490 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9491 FlippedBlendMask.push_back(
9492 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9494 : Mask[i] % LaneSize +
9495 (i / LaneSize) * LaneSize + Size));
9497 // Flip the vector, and blend the results which should now be in-lane. The
9498 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9499 // 5 for the high source. The value 3 selects the high half of source 2 and
9500 // the value 2 selects the low half of source 2. We only use source 2 to
9501 // allow folding it into a memory operand.
9502 unsigned PERMMask = 3 | 2 << 4;
9503 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9504 V1, DAG.getConstant(PERMMask, MVT::i8));
9505 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9508 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9509 // will be handled by the above logic and a blend of the results, much like
9510 // other patterns in AVX.
9511 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9514 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9516 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9517 /// isn't available.
9518 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9519 const X86Subtarget *Subtarget,
9520 SelectionDAG &DAG) {
9522 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9523 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9524 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9525 ArrayRef<int> Mask = SVOp->getMask();
9526 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9528 if (isSingleInputShuffleMask(Mask)) {
9529 // Check for being able to broadcast a single element.
9530 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9531 Mask, Subtarget, DAG))
9534 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9535 // Non-half-crossing single input shuffles can be lowerid with an
9536 // interleaved permutation.
9537 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9538 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9539 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9540 DAG.getConstant(VPERMILPMask, MVT::i8));
9543 // With AVX2 we have direct support for this permutation.
9544 if (Subtarget->hasAVX2())
9545 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9546 getV4X86ShuffleImm8ForMask(Mask, DAG));
9548 // Otherwise, fall back.
9549 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9553 // X86 has dedicated unpack instructions that can handle specific blend
9554 // operations: UNPCKH and UNPCKL.
9555 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9556 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9557 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9558 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9560 // If we have a single input to the zero element, insert that into V1 if we
9561 // can do so cheaply.
9563 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9564 if (NumV2Elements == 1 && Mask[0] >= 4)
9565 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9566 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9569 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9573 // Check if the blend happens to exactly fit that of SHUFPD.
9574 if ((Mask[0] == -1 || Mask[0] < 2) &&
9575 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9576 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9577 (Mask[3] == -1 || Mask[3] >= 6)) {
9578 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9579 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9580 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9581 DAG.getConstant(SHUFPDMask, MVT::i8));
9583 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9584 (Mask[1] == -1 || Mask[1] < 2) &&
9585 (Mask[2] == -1 || Mask[2] >= 6) &&
9586 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9587 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9588 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9589 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9590 DAG.getConstant(SHUFPDMask, MVT::i8));
9593 // Otherwise fall back on generic blend lowering.
9594 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9598 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9600 /// This routine is only called when we have AVX2 and thus a reasonable
9601 /// instruction set for v4i64 shuffling..
9602 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9603 const X86Subtarget *Subtarget,
9604 SelectionDAG &DAG) {
9606 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9607 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9608 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9609 ArrayRef<int> Mask = SVOp->getMask();
9610 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9611 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9613 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9617 // Check for being able to broadcast a single element.
9618 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9619 Mask, Subtarget, DAG))
9622 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9623 // use lower latency instructions that will operate on both 128-bit lanes.
9624 SmallVector<int, 2> RepeatedMask;
9625 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9626 if (isSingleInputShuffleMask(Mask)) {
9627 int PSHUFDMask[] = {-1, -1, -1, -1};
9628 for (int i = 0; i < 2; ++i)
9629 if (RepeatedMask[i] >= 0) {
9630 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9631 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9634 ISD::BITCAST, DL, MVT::v4i64,
9635 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9636 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9637 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9640 // Use dedicated unpack instructions for masks that match their pattern.
9641 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9642 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9643 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9644 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9647 // AVX2 provides a direct instruction for permuting a single input across
9649 if (isSingleInputShuffleMask(Mask))
9650 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9651 getV4X86ShuffleImm8ForMask(Mask, DAG));
9653 // Otherwise fall back on generic blend lowering.
9654 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9658 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9660 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9661 /// isn't available.
9662 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9663 const X86Subtarget *Subtarget,
9664 SelectionDAG &DAG) {
9666 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9667 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9668 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9669 ArrayRef<int> Mask = SVOp->getMask();
9670 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9672 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9676 // Check for being able to broadcast a single element.
9677 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9678 Mask, Subtarget, DAG))
9681 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9682 // options to efficiently lower the shuffle.
9683 SmallVector<int, 4> RepeatedMask;
9684 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9685 assert(RepeatedMask.size() == 4 &&
9686 "Repeated masks must be half the mask width!");
9687 if (isSingleInputShuffleMask(Mask))
9688 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9689 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9691 // Use dedicated unpack instructions for masks that match their pattern.
9692 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9693 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9694 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9695 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9697 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9698 // have already handled any direct blends. We also need to squash the
9699 // repeated mask into a simulated v4f32 mask.
9700 for (int i = 0; i < 4; ++i)
9701 if (RepeatedMask[i] >= 8)
9702 RepeatedMask[i] -= 4;
9703 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9706 // If we have a single input shuffle with different shuffle patterns in the
9707 // two 128-bit lanes use the variable mask to VPERMILPS.
9708 if (isSingleInputShuffleMask(Mask)) {
9709 SDValue VPermMask[8];
9710 for (int i = 0; i < 8; ++i)
9711 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9712 : DAG.getConstant(Mask[i], MVT::i32);
9713 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9715 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9716 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9718 if (Subtarget->hasAVX2())
9719 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9720 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9721 DAG.getNode(ISD::BUILD_VECTOR, DL,
9722 MVT::v8i32, VPermMask)),
9725 // Otherwise, fall back.
9726 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9730 // Otherwise fall back on generic blend lowering.
9731 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9735 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9737 /// This routine is only called when we have AVX2 and thus a reasonable
9738 /// instruction set for v8i32 shuffling..
9739 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9740 const X86Subtarget *Subtarget,
9741 SelectionDAG &DAG) {
9743 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9744 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9745 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9746 ArrayRef<int> Mask = SVOp->getMask();
9747 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9748 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9750 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9754 // Check for being able to broadcast a single element.
9755 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9756 Mask, Subtarget, DAG))
9759 // If the shuffle mask is repeated in each 128-bit lane we can use more
9760 // efficient instructions that mirror the shuffles across the two 128-bit
9762 SmallVector<int, 4> RepeatedMask;
9763 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9764 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9765 if (isSingleInputShuffleMask(Mask))
9766 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9767 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9769 // Use dedicated unpack instructions for masks that match their pattern.
9770 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9771 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9772 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9773 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9776 // If the shuffle patterns aren't repeated but it is a single input, directly
9777 // generate a cross-lane VPERMD instruction.
9778 if (isSingleInputShuffleMask(Mask)) {
9779 SDValue VPermMask[8];
9780 for (int i = 0; i < 8; ++i)
9781 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9782 : DAG.getConstant(Mask[i], MVT::i32);
9784 X86ISD::VPERMV, DL, MVT::v8i32,
9785 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9788 // Otherwise fall back on generic blend lowering.
9789 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9793 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9795 /// This routine is only called when we have AVX2 and thus a reasonable
9796 /// instruction set for v16i16 shuffling..
9797 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9798 const X86Subtarget *Subtarget,
9799 SelectionDAG &DAG) {
9801 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9802 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9803 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9804 ArrayRef<int> Mask = SVOp->getMask();
9805 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9806 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9808 // Check for being able to broadcast a single element.
9809 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9810 Mask, Subtarget, DAG))
9813 // There are no generalized cross-lane shuffle operations available on i16
9815 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9816 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9819 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9823 // Use dedicated unpack instructions for masks that match their pattern.
9824 if (isShuffleEquivalent(Mask,
9825 // First 128-bit lane:
9826 0, 16, 1, 17, 2, 18, 3, 19,
9827 // Second 128-bit lane:
9828 8, 24, 9, 25, 10, 26, 11, 27))
9829 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9830 if (isShuffleEquivalent(Mask,
9831 // First 128-bit lane:
9832 4, 20, 5, 21, 6, 22, 7, 23,
9833 // Second 128-bit lane:
9834 12, 28, 13, 29, 14, 30, 15, 31))
9835 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9837 if (isSingleInputShuffleMask(Mask)) {
9838 SDValue PSHUFBMask[32];
9839 for (int i = 0; i < 16; ++i) {
9840 if (Mask[i] == -1) {
9841 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9845 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9846 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9847 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9848 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9851 ISD::BITCAST, DL, MVT::v16i16,
9853 X86ISD::PSHUFB, DL, MVT::v32i8,
9854 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9855 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9858 // Otherwise fall back on generic blend lowering.
9859 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9863 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9865 /// This routine is only called when we have AVX2 and thus a reasonable
9866 /// instruction set for v32i8 shuffling..
9867 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9868 const X86Subtarget *Subtarget,
9869 SelectionDAG &DAG) {
9871 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9872 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9874 ArrayRef<int> Mask = SVOp->getMask();
9875 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9876 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9878 // Check for being able to broadcast a single element.
9879 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
9880 Mask, Subtarget, DAG))
9883 // There are no generalized cross-lane shuffle operations available on i8
9885 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9886 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9889 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9893 // Use dedicated unpack instructions for masks that match their pattern.
9894 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9896 if (isShuffleEquivalent(
9898 // First 128-bit lane:
9899 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9900 // Second 128-bit lane:
9901 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9902 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9903 if (isShuffleEquivalent(
9905 // First 128-bit lane:
9906 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9907 // Second 128-bit lane:
9908 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9909 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9911 if (isSingleInputShuffleMask(Mask)) {
9912 SDValue PSHUFBMask[32];
9913 for (int i = 0; i < 32; ++i)
9916 ? DAG.getUNDEF(MVT::i8)
9917 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9920 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9921 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9924 // Otherwise fall back on generic blend lowering.
9925 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9929 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9931 /// This routine either breaks down the specific type of a 256-bit x86 vector
9932 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9933 /// together based on the available instructions.
9934 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9935 MVT VT, const X86Subtarget *Subtarget,
9936 SelectionDAG &DAG) {
9938 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9939 ArrayRef<int> Mask = SVOp->getMask();
9941 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9942 // check for those subtargets here and avoid much of the subtarget querying in
9943 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9944 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9945 // floating point types there eventually, just immediately cast everything to
9946 // a float and operate entirely in that domain.
9947 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9948 int ElementBits = VT.getScalarSizeInBits();
9949 if (ElementBits < 32)
9950 // No floating point type available, decompose into 128-bit vectors.
9951 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9953 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9954 VT.getVectorNumElements());
9955 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9956 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9957 return DAG.getNode(ISD::BITCAST, DL, VT,
9958 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9961 switch (VT.SimpleTy) {
9963 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9965 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9967 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9969 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9971 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9973 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9976 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9980 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9981 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9982 const X86Subtarget *Subtarget,
9983 SelectionDAG &DAG) {
9985 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9986 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9988 ArrayRef<int> Mask = SVOp->getMask();
9989 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9991 // FIXME: Implement direct support for this type!
9992 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9995 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9996 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9997 const X86Subtarget *Subtarget,
9998 SelectionDAG &DAG) {
10000 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10001 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10002 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10003 ArrayRef<int> Mask = SVOp->getMask();
10004 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10006 // FIXME: Implement direct support for this type!
10007 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10010 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10011 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10012 const X86Subtarget *Subtarget,
10013 SelectionDAG &DAG) {
10015 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10016 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10018 ArrayRef<int> Mask = SVOp->getMask();
10019 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10020 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10022 // FIXME: Implement direct support for this type!
10023 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10026 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10027 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10028 const X86Subtarget *Subtarget,
10029 SelectionDAG &DAG) {
10031 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10032 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10033 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10034 ArrayRef<int> Mask = SVOp->getMask();
10035 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10036 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10038 // FIXME: Implement direct support for this type!
10039 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10042 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10043 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10044 const X86Subtarget *Subtarget,
10045 SelectionDAG &DAG) {
10047 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10048 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10049 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10050 ArrayRef<int> Mask = SVOp->getMask();
10051 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10052 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10054 // FIXME: Implement direct support for this type!
10055 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10058 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10059 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10060 const X86Subtarget *Subtarget,
10061 SelectionDAG &DAG) {
10063 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10064 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10065 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10066 ArrayRef<int> Mask = SVOp->getMask();
10067 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10068 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10070 // FIXME: Implement direct support for this type!
10071 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10074 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10076 /// This routine either breaks down the specific type of a 512-bit x86 vector
10077 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10078 /// together based on the available instructions.
10079 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10080 MVT VT, const X86Subtarget *Subtarget,
10081 SelectionDAG &DAG) {
10083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10084 ArrayRef<int> Mask = SVOp->getMask();
10085 assert(Subtarget->hasAVX512() &&
10086 "Cannot lower 512-bit vectors w/ basic ISA!");
10088 // Dispatch to each element type for lowering. If we don't have supprot for
10089 // specific element type shuffles at 512 bits, immediately split them and
10090 // lower them. Each lowering routine of a given type is allowed to assume that
10091 // the requisite ISA extensions for that element type are available.
10092 switch (VT.SimpleTy) {
10094 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10096 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10098 if (Subtarget->hasDQI())
10099 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10102 if (Subtarget->hasDQI())
10103 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10106 if (Subtarget->hasBWI())
10107 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10110 if (Subtarget->hasBWI())
10111 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10115 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10118 // Otherwise fall back on splitting.
10119 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10122 /// \brief Helper function to test whether a shuffle mask could be
10123 /// simplified by widening the elements being shuffled.
10125 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10126 /// leaves it in an unspecified state.
10128 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10129 /// shuffle masks. The latter have the special property of a '-2' representing
10130 /// a zero-ed lane of a vector.
10131 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10132 SmallVectorImpl<int> &WidenedMask) {
10133 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10134 // If both elements are undef, its trivial.
10135 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10136 WidenedMask.push_back(SM_SentinelUndef);
10140 // Check for an undef mask and a mask value properly aligned to fit with
10141 // a pair of values. If we find such a case, use the non-undef mask's value.
10142 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10143 WidenedMask.push_back(Mask[i + 1] / 2);
10146 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10147 WidenedMask.push_back(Mask[i] / 2);
10151 // When zeroing, we need to spread the zeroing across both lanes to widen.
10152 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10153 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10154 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10155 WidenedMask.push_back(SM_SentinelZero);
10161 // Finally check if the two mask values are adjacent and aligned with
10163 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10164 WidenedMask.push_back(Mask[i] / 2);
10168 // Otherwise we can't safely widen the elements used in this shuffle.
10171 assert(WidenedMask.size() == Mask.size() / 2 &&
10172 "Incorrect size of mask after widening the elements!");
10177 /// \brief Top-level lowering for x86 vector shuffles.
10179 /// This handles decomposition, canonicalization, and lowering of all x86
10180 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10181 /// above in helper routines. The canonicalization attempts to widen shuffles
10182 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10183 /// s.t. only one of the two inputs needs to be tested, etc.
10184 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10185 SelectionDAG &DAG) {
10186 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10187 ArrayRef<int> Mask = SVOp->getMask();
10188 SDValue V1 = Op.getOperand(0);
10189 SDValue V2 = Op.getOperand(1);
10190 MVT VT = Op.getSimpleValueType();
10191 int NumElements = VT.getVectorNumElements();
10194 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10196 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10197 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10198 if (V1IsUndef && V2IsUndef)
10199 return DAG.getUNDEF(VT);
10201 // When we create a shuffle node we put the UNDEF node to second operand,
10202 // but in some cases the first operand may be transformed to UNDEF.
10203 // In this case we should just commute the node.
10205 return DAG.getCommutedVectorShuffle(*SVOp);
10207 // Check for non-undef masks pointing at an undef vector and make the masks
10208 // undef as well. This makes it easier to match the shuffle based solely on
10212 if (M >= NumElements) {
10213 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10214 for (int &M : NewMask)
10215 if (M >= NumElements)
10217 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10220 // For integer vector shuffles, try to collapse them into a shuffle of fewer
10221 // lanes but wider integers. We cap this to not form integers larger than i64
10222 // but it might be interesting to form i128 integers to handle flipping the
10223 // low and high halves of AVX 256-bit vectors.
10224 SmallVector<int, 16> WidenedMask;
10225 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
10226 canWidenShuffleElements(Mask, WidenedMask)) {
10228 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
10229 VT.getVectorNumElements() / 2);
10230 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10231 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10232 return DAG.getNode(ISD::BITCAST, dl, VT,
10233 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10236 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10237 for (int M : SVOp->getMask())
10239 ++NumUndefElements;
10240 else if (M < NumElements)
10245 // Commute the shuffle as needed such that more elements come from V1 than
10246 // V2. This allows us to match the shuffle pattern strictly on how many
10247 // elements come from V1 without handling the symmetric cases.
10248 if (NumV2Elements > NumV1Elements)
10249 return DAG.getCommutedVectorShuffle(*SVOp);
10251 // When the number of V1 and V2 elements are the same, try to minimize the
10252 // number of uses of V2 in the low half of the vector. When that is tied,
10253 // ensure that the sum of indices for V1 is equal to or lower than the sum
10255 if (NumV1Elements == NumV2Elements) {
10256 int LowV1Elements = 0, LowV2Elements = 0;
10257 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10258 if (M >= NumElements)
10262 if (LowV2Elements > LowV1Elements) {
10263 return DAG.getCommutedVectorShuffle(*SVOp);
10264 } else if (LowV2Elements == LowV1Elements) {
10265 int SumV1Indices = 0, SumV2Indices = 0;
10266 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10267 if (SVOp->getMask()[i] >= NumElements)
10269 else if (SVOp->getMask()[i] >= 0)
10271 if (SumV2Indices < SumV1Indices)
10272 return DAG.getCommutedVectorShuffle(*SVOp);
10276 // For each vector width, delegate to a specialized lowering routine.
10277 if (VT.getSizeInBits() == 128)
10278 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10280 if (VT.getSizeInBits() == 256)
10281 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10283 // Force AVX-512 vectors to be scalarized for now.
10284 // FIXME: Implement AVX-512 support!
10285 if (VT.getSizeInBits() == 512)
10286 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10288 llvm_unreachable("Unimplemented!");
10292 //===----------------------------------------------------------------------===//
10293 // Legacy vector shuffle lowering
10295 // This code is the legacy code handling vector shuffles until the above
10296 // replaces its functionality and performance.
10297 //===----------------------------------------------------------------------===//
10299 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10300 bool hasInt256, unsigned *MaskOut = nullptr) {
10301 MVT EltVT = VT.getVectorElementType();
10303 // There is no blend with immediate in AVX-512.
10304 if (VT.is512BitVector())
10307 if (!hasSSE41 || EltVT == MVT::i8)
10309 if (!hasInt256 && VT == MVT::v16i16)
10312 unsigned MaskValue = 0;
10313 unsigned NumElems = VT.getVectorNumElements();
10314 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10315 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10316 unsigned NumElemsInLane = NumElems / NumLanes;
10318 // Blend for v16i16 should be symetric for the both lanes.
10319 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10321 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10322 int EltIdx = MaskVals[i];
10324 if ((EltIdx < 0 || EltIdx == (int)i) &&
10325 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10328 if (((unsigned)EltIdx == (i + NumElems)) &&
10329 (SndLaneEltIdx < 0 ||
10330 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10331 MaskValue |= (1 << i);
10337 *MaskOut = MaskValue;
10341 // Try to lower a shuffle node into a simple blend instruction.
10342 // This function assumes isBlendMask returns true for this
10343 // SuffleVectorSDNode
10344 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10345 unsigned MaskValue,
10346 const X86Subtarget *Subtarget,
10347 SelectionDAG &DAG) {
10348 MVT VT = SVOp->getSimpleValueType(0);
10349 MVT EltVT = VT.getVectorElementType();
10350 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10351 Subtarget->hasInt256() && "Trying to lower a "
10352 "VECTOR_SHUFFLE to a Blend but "
10353 "with the wrong mask"));
10354 SDValue V1 = SVOp->getOperand(0);
10355 SDValue V2 = SVOp->getOperand(1);
10357 unsigned NumElems = VT.getVectorNumElements();
10359 // Convert i32 vectors to floating point if it is not AVX2.
10360 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10362 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10363 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10365 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10366 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10369 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10370 DAG.getConstant(MaskValue, MVT::i32));
10371 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10374 /// In vector type \p VT, return true if the element at index \p InputIdx
10375 /// falls on a different 128-bit lane than \p OutputIdx.
10376 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10377 unsigned OutputIdx) {
10378 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10379 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10382 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10383 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10384 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10385 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10387 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10388 SelectionDAG &DAG) {
10389 MVT VT = V1.getSimpleValueType();
10390 assert(VT.is128BitVector() || VT.is256BitVector());
10392 MVT EltVT = VT.getVectorElementType();
10393 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10394 unsigned NumElts = VT.getVectorNumElements();
10396 SmallVector<SDValue, 32> PshufbMask;
10397 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10398 int InputIdx = MaskVals[OutputIdx];
10399 unsigned InputByteIdx;
10401 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10402 InputByteIdx = 0x80;
10404 // Cross lane is not allowed.
10405 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10407 InputByteIdx = InputIdx * EltSizeInBytes;
10408 // Index is an byte offset within the 128-bit lane.
10409 InputByteIdx &= 0xf;
10412 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10413 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10414 if (InputByteIdx != 0x80)
10419 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10421 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10422 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10423 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10426 // v8i16 shuffles - Prefer shuffles in the following order:
10427 // 1. [all] pshuflw, pshufhw, optional move
10428 // 2. [ssse3] 1 x pshufb
10429 // 3. [ssse3] 2 x pshufb + 1 x por
10430 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10432 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10433 SelectionDAG &DAG) {
10434 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10435 SDValue V1 = SVOp->getOperand(0);
10436 SDValue V2 = SVOp->getOperand(1);
10438 SmallVector<int, 8> MaskVals;
10440 // Determine if more than 1 of the words in each of the low and high quadwords
10441 // of the result come from the same quadword of one of the two inputs. Undef
10442 // mask values count as coming from any quadword, for better codegen.
10444 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10445 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10446 unsigned LoQuad[] = { 0, 0, 0, 0 };
10447 unsigned HiQuad[] = { 0, 0, 0, 0 };
10448 // Indices of quads used.
10449 std::bitset<4> InputQuads;
10450 for (unsigned i = 0; i < 8; ++i) {
10451 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10452 int EltIdx = SVOp->getMaskElt(i);
10453 MaskVals.push_back(EltIdx);
10461 ++Quad[EltIdx / 4];
10462 InputQuads.set(EltIdx / 4);
10465 int BestLoQuad = -1;
10466 unsigned MaxQuad = 1;
10467 for (unsigned i = 0; i < 4; ++i) {
10468 if (LoQuad[i] > MaxQuad) {
10470 MaxQuad = LoQuad[i];
10474 int BestHiQuad = -1;
10476 for (unsigned i = 0; i < 4; ++i) {
10477 if (HiQuad[i] > MaxQuad) {
10479 MaxQuad = HiQuad[i];
10483 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10484 // of the two input vectors, shuffle them into one input vector so only a
10485 // single pshufb instruction is necessary. If there are more than 2 input
10486 // quads, disable the next transformation since it does not help SSSE3.
10487 bool V1Used = InputQuads[0] || InputQuads[1];
10488 bool V2Used = InputQuads[2] || InputQuads[3];
10489 if (Subtarget->hasSSSE3()) {
10490 if (InputQuads.count() == 2 && V1Used && V2Used) {
10491 BestLoQuad = InputQuads[0] ? 0 : 1;
10492 BestHiQuad = InputQuads[2] ? 2 : 3;
10494 if (InputQuads.count() > 2) {
10500 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10501 // the shuffle mask. If a quad is scored as -1, that means that it contains
10502 // words from all 4 input quadwords.
10504 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10506 BestLoQuad < 0 ? 0 : BestLoQuad,
10507 BestHiQuad < 0 ? 1 : BestHiQuad
10509 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10510 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10511 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10512 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10514 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10515 // source words for the shuffle, to aid later transformations.
10516 bool AllWordsInNewV = true;
10517 bool InOrder[2] = { true, true };
10518 for (unsigned i = 0; i != 8; ++i) {
10519 int idx = MaskVals[i];
10521 InOrder[i/4] = false;
10522 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10524 AllWordsInNewV = false;
10528 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10529 if (AllWordsInNewV) {
10530 for (int i = 0; i != 8; ++i) {
10531 int idx = MaskVals[i];
10534 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10535 if ((idx != i) && idx < 4)
10537 if ((idx != i) && idx > 3)
10546 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10547 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10548 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10549 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10550 unsigned TargetMask = 0;
10551 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10552 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10554 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10555 getShufflePSHUFLWImmediate(SVOp);
10556 V1 = NewV.getOperand(0);
10557 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10561 // Promote splats to a larger type which usually leads to more efficient code.
10562 // FIXME: Is this true if pshufb is available?
10563 if (SVOp->isSplat())
10564 return PromoteSplat(SVOp, DAG);
10566 // If we have SSSE3, and all words of the result are from 1 input vector,
10567 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10568 // is present, fall back to case 4.
10569 if (Subtarget->hasSSSE3()) {
10570 SmallVector<SDValue,16> pshufbMask;
10572 // If we have elements from both input vectors, set the high bit of the
10573 // shuffle mask element to zero out elements that come from V2 in the V1
10574 // mask, and elements that come from V1 in the V2 mask, so that the two
10575 // results can be OR'd together.
10576 bool TwoInputs = V1Used && V2Used;
10577 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10579 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10581 // Calculate the shuffle mask for the second input, shuffle it, and
10582 // OR it with the first shuffled input.
10583 CommuteVectorShuffleMask(MaskVals, 8);
10584 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10585 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10586 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10589 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10590 // and update MaskVals with new element order.
10591 std::bitset<8> InOrder;
10592 if (BestLoQuad >= 0) {
10593 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10594 for (int i = 0; i != 4; ++i) {
10595 int idx = MaskVals[i];
10598 } else if ((idx / 4) == BestLoQuad) {
10599 MaskV[i] = idx & 3;
10603 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10606 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10607 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10608 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10609 NewV.getOperand(0),
10610 getShufflePSHUFLWImmediate(SVOp), DAG);
10614 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10615 // and update MaskVals with the new element order.
10616 if (BestHiQuad >= 0) {
10617 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10618 for (unsigned i = 4; i != 8; ++i) {
10619 int idx = MaskVals[i];
10622 } else if ((idx / 4) == BestHiQuad) {
10623 MaskV[i] = (idx & 3) + 4;
10627 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10630 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10631 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10632 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10633 NewV.getOperand(0),
10634 getShufflePSHUFHWImmediate(SVOp), DAG);
10638 // In case BestHi & BestLo were both -1, which means each quadword has a word
10639 // from each of the four input quadwords, calculate the InOrder bitvector now
10640 // before falling through to the insert/extract cleanup.
10641 if (BestLoQuad == -1 && BestHiQuad == -1) {
10643 for (int i = 0; i != 8; ++i)
10644 if (MaskVals[i] < 0 || MaskVals[i] == i)
10648 // The other elements are put in the right place using pextrw and pinsrw.
10649 for (unsigned i = 0; i != 8; ++i) {
10652 int EltIdx = MaskVals[i];
10655 SDValue ExtOp = (EltIdx < 8) ?
10656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10657 DAG.getIntPtrConstant(EltIdx)) :
10658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10659 DAG.getIntPtrConstant(EltIdx - 8));
10660 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10661 DAG.getIntPtrConstant(i));
10666 /// \brief v16i16 shuffles
10668 /// FIXME: We only support generation of a single pshufb currently. We can
10669 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10670 /// well (e.g 2 x pshufb + 1 x por).
10672 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10673 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10674 SDValue V1 = SVOp->getOperand(0);
10675 SDValue V2 = SVOp->getOperand(1);
10678 if (V2.getOpcode() != ISD::UNDEF)
10681 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10682 return getPSHUFB(MaskVals, V1, dl, DAG);
10685 // v16i8 shuffles - Prefer shuffles in the following order:
10686 // 1. [ssse3] 1 x pshufb
10687 // 2. [ssse3] 2 x pshufb + 1 x por
10688 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10689 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10690 const X86Subtarget* Subtarget,
10691 SelectionDAG &DAG) {
10692 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10693 SDValue V1 = SVOp->getOperand(0);
10694 SDValue V2 = SVOp->getOperand(1);
10696 ArrayRef<int> MaskVals = SVOp->getMask();
10698 // Promote splats to a larger type which usually leads to more efficient code.
10699 // FIXME: Is this true if pshufb is available?
10700 if (SVOp->isSplat())
10701 return PromoteSplat(SVOp, DAG);
10703 // If we have SSSE3, case 1 is generated when all result bytes come from
10704 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10705 // present, fall back to case 3.
10707 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10708 if (Subtarget->hasSSSE3()) {
10709 SmallVector<SDValue,16> pshufbMask;
10711 // If all result elements are from one input vector, then only translate
10712 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10714 // Otherwise, we have elements from both input vectors, and must zero out
10715 // elements that come from V2 in the first mask, and V1 in the second mask
10716 // so that we can OR them together.
10717 for (unsigned i = 0; i != 16; ++i) {
10718 int EltIdx = MaskVals[i];
10719 if (EltIdx < 0 || EltIdx >= 16)
10721 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10723 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10724 DAG.getNode(ISD::BUILD_VECTOR, dl,
10725 MVT::v16i8, pshufbMask));
10727 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10728 // the 2nd operand if it's undefined or zero.
10729 if (V2.getOpcode() == ISD::UNDEF ||
10730 ISD::isBuildVectorAllZeros(V2.getNode()))
10733 // Calculate the shuffle mask for the second input, shuffle it, and
10734 // OR it with the first shuffled input.
10735 pshufbMask.clear();
10736 for (unsigned i = 0; i != 16; ++i) {
10737 int EltIdx = MaskVals[i];
10738 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10739 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10741 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10742 DAG.getNode(ISD::BUILD_VECTOR, dl,
10743 MVT::v16i8, pshufbMask));
10744 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10747 // No SSSE3 - Calculate in place words and then fix all out of place words
10748 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10749 // the 16 different words that comprise the two doublequadword input vectors.
10750 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10751 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10753 for (int i = 0; i != 8; ++i) {
10754 int Elt0 = MaskVals[i*2];
10755 int Elt1 = MaskVals[i*2+1];
10757 // This word of the result is all undef, skip it.
10758 if (Elt0 < 0 && Elt1 < 0)
10761 // This word of the result is already in the correct place, skip it.
10762 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10765 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10766 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10769 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10770 // using a single extract together, load it and store it.
10771 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10772 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10773 DAG.getIntPtrConstant(Elt1 / 2));
10774 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10775 DAG.getIntPtrConstant(i));
10779 // If Elt1 is defined, extract it from the appropriate source. If the
10780 // source byte is not also odd, shift the extracted word left 8 bits
10781 // otherwise clear the bottom 8 bits if we need to do an or.
10783 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10784 DAG.getIntPtrConstant(Elt1 / 2));
10785 if ((Elt1 & 1) == 0)
10786 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10788 TLI.getShiftAmountTy(InsElt.getValueType())));
10789 else if (Elt0 >= 0)
10790 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10791 DAG.getConstant(0xFF00, MVT::i16));
10793 // If Elt0 is defined, extract it from the appropriate source. If the
10794 // source byte is not also even, shift the extracted word right 8 bits. If
10795 // Elt1 was also defined, OR the extracted values together before
10796 // inserting them in the result.
10798 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10799 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10800 if ((Elt0 & 1) != 0)
10801 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10803 TLI.getShiftAmountTy(InsElt0.getValueType())));
10804 else if (Elt1 >= 0)
10805 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10806 DAG.getConstant(0x00FF, MVT::i16));
10807 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10810 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10811 DAG.getIntPtrConstant(i));
10813 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10816 // v32i8 shuffles - Translate to VPSHUFB if possible.
10818 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10819 const X86Subtarget *Subtarget,
10820 SelectionDAG &DAG) {
10821 MVT VT = SVOp->getSimpleValueType(0);
10822 SDValue V1 = SVOp->getOperand(0);
10823 SDValue V2 = SVOp->getOperand(1);
10825 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10827 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10828 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10829 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10831 // VPSHUFB may be generated if
10832 // (1) one of input vector is undefined or zeroinitializer.
10833 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10834 // And (2) the mask indexes don't cross the 128-bit lane.
10835 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10836 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10839 if (V1IsAllZero && !V2IsAllZero) {
10840 CommuteVectorShuffleMask(MaskVals, 32);
10843 return getPSHUFB(MaskVals, V1, dl, DAG);
10846 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10847 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10848 /// done when every pair / quad of shuffle mask elements point to elements in
10849 /// the right sequence. e.g.
10850 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10852 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10853 SelectionDAG &DAG) {
10854 MVT VT = SVOp->getSimpleValueType(0);
10856 unsigned NumElems = VT.getVectorNumElements();
10859 switch (VT.SimpleTy) {
10860 default: llvm_unreachable("Unexpected!");
10863 return SDValue(SVOp, 0);
10864 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10865 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10866 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10867 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10868 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10869 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10872 SmallVector<int, 8> MaskVec;
10873 for (unsigned i = 0; i != NumElems; i += Scale) {
10875 for (unsigned j = 0; j != Scale; ++j) {
10876 int EltIdx = SVOp->getMaskElt(i+j);
10880 StartIdx = (EltIdx / Scale);
10881 if (EltIdx != (int)(StartIdx*Scale + j))
10884 MaskVec.push_back(StartIdx);
10887 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10888 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10889 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10892 /// getVZextMovL - Return a zero-extending vector move low node.
10894 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10895 SDValue SrcOp, SelectionDAG &DAG,
10896 const X86Subtarget *Subtarget, SDLoc dl) {
10897 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10898 LoadSDNode *LD = nullptr;
10899 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10900 LD = dyn_cast<LoadSDNode>(SrcOp);
10902 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10904 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10905 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10906 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10907 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10908 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10910 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10911 return DAG.getNode(ISD::BITCAST, dl, VT,
10912 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10913 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10915 SrcOp.getOperand(0)
10921 return DAG.getNode(ISD::BITCAST, dl, VT,
10922 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10923 DAG.getNode(ISD::BITCAST, dl,
10927 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10928 /// which could not be matched by any known target speficic shuffle
10930 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10932 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10933 if (NewOp.getNode())
10936 MVT VT = SVOp->getSimpleValueType(0);
10938 unsigned NumElems = VT.getVectorNumElements();
10939 unsigned NumLaneElems = NumElems / 2;
10942 MVT EltVT = VT.getVectorElementType();
10943 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10946 SmallVector<int, 16> Mask;
10947 for (unsigned l = 0; l < 2; ++l) {
10948 // Build a shuffle mask for the output, discovering on the fly which
10949 // input vectors to use as shuffle operands (recorded in InputUsed).
10950 // If building a suitable shuffle vector proves too hard, then bail
10951 // out with UseBuildVector set.
10952 bool UseBuildVector = false;
10953 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10954 unsigned LaneStart = l * NumLaneElems;
10955 for (unsigned i = 0; i != NumLaneElems; ++i) {
10956 // The mask element. This indexes into the input.
10957 int Idx = SVOp->getMaskElt(i+LaneStart);
10959 // the mask element does not index into any input vector.
10960 Mask.push_back(-1);
10964 // The input vector this mask element indexes into.
10965 int Input = Idx / NumLaneElems;
10967 // Turn the index into an offset from the start of the input vector.
10968 Idx -= Input * NumLaneElems;
10970 // Find or create a shuffle vector operand to hold this input.
10972 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10973 if (InputUsed[OpNo] == Input)
10974 // This input vector is already an operand.
10976 if (InputUsed[OpNo] < 0) {
10977 // Create a new operand for this input vector.
10978 InputUsed[OpNo] = Input;
10983 if (OpNo >= array_lengthof(InputUsed)) {
10984 // More than two input vectors used! Give up on trying to create a
10985 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10986 UseBuildVector = true;
10990 // Add the mask index for the new shuffle vector.
10991 Mask.push_back(Idx + OpNo * NumLaneElems);
10994 if (UseBuildVector) {
10995 SmallVector<SDValue, 16> SVOps;
10996 for (unsigned i = 0; i != NumLaneElems; ++i) {
10997 // The mask element. This indexes into the input.
10998 int Idx = SVOp->getMaskElt(i+LaneStart);
11000 SVOps.push_back(DAG.getUNDEF(EltVT));
11004 // The input vector this mask element indexes into.
11005 int Input = Idx / NumElems;
11007 // Turn the index into an offset from the start of the input vector.
11008 Idx -= Input * NumElems;
11010 // Extract the vector element by hand.
11011 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11012 SVOp->getOperand(Input),
11013 DAG.getIntPtrConstant(Idx)));
11016 // Construct the output using a BUILD_VECTOR.
11017 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11018 } else if (InputUsed[0] < 0) {
11019 // No input vectors were used! The result is undefined.
11020 Output[l] = DAG.getUNDEF(NVT);
11022 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11023 (InputUsed[0] % 2) * NumLaneElems,
11025 // If only one input was used, use an undefined vector for the other.
11026 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11027 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11028 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11029 // At least one input vector was used. Create a new shuffle vector.
11030 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11036 // Concatenate the result back
11037 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11040 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11041 /// 4 elements, and match them with several different shuffle types.
11043 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11044 SDValue V1 = SVOp->getOperand(0);
11045 SDValue V2 = SVOp->getOperand(1);
11047 MVT VT = SVOp->getSimpleValueType(0);
11049 assert(VT.is128BitVector() && "Unsupported vector size");
11051 std::pair<int, int> Locs[4];
11052 int Mask1[] = { -1, -1, -1, -1 };
11053 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11055 unsigned NumHi = 0;
11056 unsigned NumLo = 0;
11057 for (unsigned i = 0; i != 4; ++i) {
11058 int Idx = PermMask[i];
11060 Locs[i] = std::make_pair(-1, -1);
11062 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11064 Locs[i] = std::make_pair(0, NumLo);
11065 Mask1[NumLo] = Idx;
11068 Locs[i] = std::make_pair(1, NumHi);
11070 Mask1[2+NumHi] = Idx;
11076 if (NumLo <= 2 && NumHi <= 2) {
11077 // If no more than two elements come from either vector. This can be
11078 // implemented with two shuffles. First shuffle gather the elements.
11079 // The second shuffle, which takes the first shuffle as both of its
11080 // vector operands, put the elements into the right order.
11081 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11083 int Mask2[] = { -1, -1, -1, -1 };
11085 for (unsigned i = 0; i != 4; ++i)
11086 if (Locs[i].first != -1) {
11087 unsigned Idx = (i < 2) ? 0 : 4;
11088 Idx += Locs[i].first * 2 + Locs[i].second;
11092 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11095 if (NumLo == 3 || NumHi == 3) {
11096 // Otherwise, we must have three elements from one vector, call it X, and
11097 // one element from the other, call it Y. First, use a shufps to build an
11098 // intermediate vector with the one element from Y and the element from X
11099 // that will be in the same half in the final destination (the indexes don't
11100 // matter). Then, use a shufps to build the final vector, taking the half
11101 // containing the element from Y from the intermediate, and the other half
11104 // Normalize it so the 3 elements come from V1.
11105 CommuteVectorShuffleMask(PermMask, 4);
11109 // Find the element from V2.
11111 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11112 int Val = PermMask[HiIndex];
11119 Mask1[0] = PermMask[HiIndex];
11121 Mask1[2] = PermMask[HiIndex^1];
11123 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11125 if (HiIndex >= 2) {
11126 Mask1[0] = PermMask[0];
11127 Mask1[1] = PermMask[1];
11128 Mask1[2] = HiIndex & 1 ? 6 : 4;
11129 Mask1[3] = HiIndex & 1 ? 4 : 6;
11130 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11133 Mask1[0] = HiIndex & 1 ? 2 : 0;
11134 Mask1[1] = HiIndex & 1 ? 0 : 2;
11135 Mask1[2] = PermMask[2];
11136 Mask1[3] = PermMask[3];
11141 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11144 // Break it into (shuffle shuffle_hi, shuffle_lo).
11145 int LoMask[] = { -1, -1, -1, -1 };
11146 int HiMask[] = { -1, -1, -1, -1 };
11148 int *MaskPtr = LoMask;
11149 unsigned MaskIdx = 0;
11150 unsigned LoIdx = 0;
11151 unsigned HiIdx = 2;
11152 for (unsigned i = 0; i != 4; ++i) {
11159 int Idx = PermMask[i];
11161 Locs[i] = std::make_pair(-1, -1);
11162 } else if (Idx < 4) {
11163 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11164 MaskPtr[LoIdx] = Idx;
11167 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11168 MaskPtr[HiIdx] = Idx;
11173 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11174 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11175 int MaskOps[] = { -1, -1, -1, -1 };
11176 for (unsigned i = 0; i != 4; ++i)
11177 if (Locs[i].first != -1)
11178 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11179 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11182 static bool MayFoldVectorLoad(SDValue V) {
11183 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11184 V = V.getOperand(0);
11186 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11187 V = V.getOperand(0);
11188 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11189 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11190 // BUILD_VECTOR (load), undef
11191 V = V.getOperand(0);
11193 return MayFoldLoad(V);
11197 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11198 MVT VT = Op.getSimpleValueType();
11200 // Canonizalize to v2f64.
11201 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11202 return DAG.getNode(ISD::BITCAST, dl, VT,
11203 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11208 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11210 SDValue V1 = Op.getOperand(0);
11211 SDValue V2 = Op.getOperand(1);
11212 MVT VT = Op.getSimpleValueType();
11214 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11216 if (HasSSE2 && VT == MVT::v2f64)
11217 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11219 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11220 return DAG.getNode(ISD::BITCAST, dl, VT,
11221 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11222 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11223 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11227 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11228 SDValue V1 = Op.getOperand(0);
11229 SDValue V2 = Op.getOperand(1);
11230 MVT VT = Op.getSimpleValueType();
11232 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11233 "unsupported shuffle type");
11235 if (V2.getOpcode() == ISD::UNDEF)
11239 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11243 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11244 SDValue V1 = Op.getOperand(0);
11245 SDValue V2 = Op.getOperand(1);
11246 MVT VT = Op.getSimpleValueType();
11247 unsigned NumElems = VT.getVectorNumElements();
11249 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11250 // operand of these instructions is only memory, so check if there's a
11251 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11253 bool CanFoldLoad = false;
11255 // Trivial case, when V2 comes from a load.
11256 if (MayFoldVectorLoad(V2))
11257 CanFoldLoad = true;
11259 // When V1 is a load, it can be folded later into a store in isel, example:
11260 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11262 // (MOVLPSmr addr:$src1, VR128:$src2)
11263 // So, recognize this potential and also use MOVLPS or MOVLPD
11264 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11265 CanFoldLoad = true;
11267 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11269 if (HasSSE2 && NumElems == 2)
11270 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11273 // If we don't care about the second element, proceed to use movss.
11274 if (SVOp->getMaskElt(1) != -1)
11275 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11278 // movl and movlp will both match v2i64, but v2i64 is never matched by
11279 // movl earlier because we make it strict to avoid messing with the movlp load
11280 // folding logic (see the code above getMOVLP call). Match it here then,
11281 // this is horrible, but will stay like this until we move all shuffle
11282 // matching to x86 specific nodes. Note that for the 1st condition all
11283 // types are matched with movsd.
11285 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11286 // as to remove this logic from here, as much as possible
11287 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11288 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11289 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11292 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11294 // Invert the operand order and use SHUFPS to match it.
11295 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11296 getShuffleSHUFImmediate(SVOp), DAG);
11299 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11300 SelectionDAG &DAG) {
11302 MVT VT = Load->getSimpleValueType(0);
11303 MVT EVT = VT.getVectorElementType();
11304 SDValue Addr = Load->getOperand(1);
11305 SDValue NewAddr = DAG.getNode(
11306 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11307 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11310 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11311 DAG.getMachineFunction().getMachineMemOperand(
11312 Load->getMemOperand(), 0, EVT.getStoreSize()));
11316 // It is only safe to call this function if isINSERTPSMask is true for
11317 // this shufflevector mask.
11318 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11319 SelectionDAG &DAG) {
11320 // Generate an insertps instruction when inserting an f32 from memory onto a
11321 // v4f32 or when copying a member from one v4f32 to another.
11322 // We also use it for transferring i32 from one register to another,
11323 // since it simply copies the same bits.
11324 // If we're transferring an i32 from memory to a specific element in a
11325 // register, we output a generic DAG that will match the PINSRD
11327 MVT VT = SVOp->getSimpleValueType(0);
11328 MVT EVT = VT.getVectorElementType();
11329 SDValue V1 = SVOp->getOperand(0);
11330 SDValue V2 = SVOp->getOperand(1);
11331 auto Mask = SVOp->getMask();
11332 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11333 "unsupported vector type for insertps/pinsrd");
11335 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11336 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11337 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11341 unsigned DestIndex;
11345 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11348 // If we have 1 element from each vector, we have to check if we're
11349 // changing V1's element's place. If so, we're done. Otherwise, we
11350 // should assume we're changing V2's element's place and behave
11352 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11353 assert(DestIndex <= INT32_MAX && "truncated destination index");
11354 if (FromV1 == FromV2 &&
11355 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11359 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11362 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11363 "More than one element from V1 and from V2, or no elements from one "
11364 "of the vectors. This case should not have returned true from "
11369 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11372 // Get an index into the source vector in the range [0,4) (the mask is
11373 // in the range [0,8) because it can address V1 and V2)
11374 unsigned SrcIndex = Mask[DestIndex] % 4;
11375 if (MayFoldLoad(From)) {
11376 // Trivial case, when From comes from a load and is only used by the
11377 // shuffle. Make it use insertps from the vector that we need from that
11380 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11381 if (!NewLoad.getNode())
11384 if (EVT == MVT::f32) {
11385 // Create this as a scalar to vector to match the instruction pattern.
11386 SDValue LoadScalarToVector =
11387 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11388 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11389 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11391 } else { // EVT == MVT::i32
11392 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11393 // instruction, to match the PINSRD instruction, which loads an i32 to a
11394 // certain vector element.
11395 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11396 DAG.getConstant(DestIndex, MVT::i32));
11400 // Vector-element-to-vector
11401 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11402 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11405 // Reduce a vector shuffle to zext.
11406 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11407 SelectionDAG &DAG) {
11408 // PMOVZX is only available from SSE41.
11409 if (!Subtarget->hasSSE41())
11412 MVT VT = Op.getSimpleValueType();
11414 // Only AVX2 support 256-bit vector integer extending.
11415 if (!Subtarget->hasInt256() && VT.is256BitVector())
11418 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11420 SDValue V1 = Op.getOperand(0);
11421 SDValue V2 = Op.getOperand(1);
11422 unsigned NumElems = VT.getVectorNumElements();
11424 // Extending is an unary operation and the element type of the source vector
11425 // won't be equal to or larger than i64.
11426 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11427 VT.getVectorElementType() == MVT::i64)
11430 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11431 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11432 while ((1U << Shift) < NumElems) {
11433 if (SVOp->getMaskElt(1U << Shift) == 1)
11436 // The maximal ratio is 8, i.e. from i8 to i64.
11441 // Check the shuffle mask.
11442 unsigned Mask = (1U << Shift) - 1;
11443 for (unsigned i = 0; i != NumElems; ++i) {
11444 int EltIdx = SVOp->getMaskElt(i);
11445 if ((i & Mask) != 0 && EltIdx != -1)
11447 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11451 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11452 MVT NeVT = MVT::getIntegerVT(NBits);
11453 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11455 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11458 // Simplify the operand as it's prepared to be fed into shuffle.
11459 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11460 if (V1.getOpcode() == ISD::BITCAST &&
11461 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11462 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11463 V1.getOperand(0).getOperand(0)
11464 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11465 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11466 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11467 ConstantSDNode *CIdx =
11468 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11469 // If it's foldable, i.e. normal load with single use, we will let code
11470 // selection to fold it. Otherwise, we will short the conversion sequence.
11471 if (CIdx && CIdx->getZExtValue() == 0 &&
11472 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11473 MVT FullVT = V.getSimpleValueType();
11474 MVT V1VT = V1.getSimpleValueType();
11475 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11476 // The "ext_vec_elt" node is wider than the result node.
11477 // In this case we should extract subvector from V.
11478 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11479 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11480 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11481 FullVT.getVectorNumElements()/Ratio);
11482 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11483 DAG.getIntPtrConstant(0));
11485 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11489 return DAG.getNode(ISD::BITCAST, DL, VT,
11490 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11493 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11494 SelectionDAG &DAG) {
11495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11496 MVT VT = Op.getSimpleValueType();
11498 SDValue V1 = Op.getOperand(0);
11499 SDValue V2 = Op.getOperand(1);
11501 if (isZeroShuffle(SVOp))
11502 return getZeroVector(VT, Subtarget, DAG, dl);
11504 // Handle splat operations
11505 if (SVOp->isSplat()) {
11506 // Use vbroadcast whenever the splat comes from a foldable load
11507 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11508 if (Broadcast.getNode())
11512 // Check integer expanding shuffles.
11513 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11514 if (NewOp.getNode())
11517 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11519 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11520 VT == MVT::v32i8) {
11521 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11522 if (NewOp.getNode())
11523 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11524 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11525 // FIXME: Figure out a cleaner way to do this.
11526 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11527 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11528 if (NewOp.getNode()) {
11529 MVT NewVT = NewOp.getSimpleValueType();
11530 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11531 NewVT, true, false))
11532 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11535 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11536 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11537 if (NewOp.getNode()) {
11538 MVT NewVT = NewOp.getSimpleValueType();
11539 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11540 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11549 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11551 SDValue V1 = Op.getOperand(0);
11552 SDValue V2 = Op.getOperand(1);
11553 MVT VT = Op.getSimpleValueType();
11555 unsigned NumElems = VT.getVectorNumElements();
11556 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11557 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11558 bool V1IsSplat = false;
11559 bool V2IsSplat = false;
11560 bool HasSSE2 = Subtarget->hasSSE2();
11561 bool HasFp256 = Subtarget->hasFp256();
11562 bool HasInt256 = Subtarget->hasInt256();
11563 MachineFunction &MF = DAG.getMachineFunction();
11564 bool OptForSize = MF.getFunction()->getAttributes().
11565 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11567 // Check if we should use the experimental vector shuffle lowering. If so,
11568 // delegate completely to that code path.
11569 if (ExperimentalVectorShuffleLowering)
11570 return lowerVectorShuffle(Op, Subtarget, DAG);
11572 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11574 if (V1IsUndef && V2IsUndef)
11575 return DAG.getUNDEF(VT);
11577 // When we create a shuffle node we put the UNDEF node to second operand,
11578 // but in some cases the first operand may be transformed to UNDEF.
11579 // In this case we should just commute the node.
11581 return DAG.getCommutedVectorShuffle(*SVOp);
11583 // Vector shuffle lowering takes 3 steps:
11585 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11586 // narrowing and commutation of operands should be handled.
11587 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11589 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11590 // so the shuffle can be broken into other shuffles and the legalizer can
11591 // try the lowering again.
11593 // The general idea is that no vector_shuffle operation should be left to
11594 // be matched during isel, all of them must be converted to a target specific
11597 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11598 // narrowing and commutation of operands should be handled. The actual code
11599 // doesn't include all of those, work in progress...
11600 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11601 if (NewOp.getNode())
11604 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11606 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11607 // unpckh_undef). Only use pshufd if speed is more important than size.
11608 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11609 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11610 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11611 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11613 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11614 V2IsUndef && MayFoldVectorLoad(V1))
11615 return getMOVDDup(Op, dl, V1, DAG);
11617 if (isMOVHLPS_v_undef_Mask(M, VT))
11618 return getMOVHighToLow(Op, dl, DAG);
11620 // Use to match splats
11621 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11622 (VT == MVT::v2f64 || VT == MVT::v2i64))
11623 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11625 if (isPSHUFDMask(M, VT)) {
11626 // The actual implementation will match the mask in the if above and then
11627 // during isel it can match several different instructions, not only pshufd
11628 // as its name says, sad but true, emulate the behavior for now...
11629 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11630 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11632 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11634 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11635 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11637 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11638 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11641 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11645 if (isPALIGNRMask(M, VT, Subtarget))
11646 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11647 getShufflePALIGNRImmediate(SVOp),
11650 if (isVALIGNMask(M, VT, Subtarget))
11651 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11652 getShuffleVALIGNImmediate(SVOp),
11655 // Check if this can be converted into a logical shift.
11656 bool isLeft = false;
11657 unsigned ShAmt = 0;
11659 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11660 if (isShift && ShVal.hasOneUse()) {
11661 // If the shifted value has multiple uses, it may be cheaper to use
11662 // v_set0 + movlhps or movhlps, etc.
11663 MVT EltVT = VT.getVectorElementType();
11664 ShAmt *= EltVT.getSizeInBits();
11665 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11668 if (isMOVLMask(M, VT)) {
11669 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11670 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11671 if (!isMOVLPMask(M, VT)) {
11672 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11673 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11675 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11676 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11680 // FIXME: fold these into legal mask.
11681 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11682 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11684 if (isMOVHLPSMask(M, VT))
11685 return getMOVHighToLow(Op, dl, DAG);
11687 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11688 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11690 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11691 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11693 if (isMOVLPMask(M, VT))
11694 return getMOVLP(Op, dl, DAG, HasSSE2);
11696 if (ShouldXformToMOVHLPS(M, VT) ||
11697 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11698 return DAG.getCommutedVectorShuffle(*SVOp);
11701 // No better options. Use a vshldq / vsrldq.
11702 MVT EltVT = VT.getVectorElementType();
11703 ShAmt *= EltVT.getSizeInBits();
11704 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11707 bool Commuted = false;
11708 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11709 // 1,1,1,1 -> v8i16 though.
11710 BitVector UndefElements;
11711 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11712 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11714 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11715 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11718 // Canonicalize the splat or undef, if present, to be on the RHS.
11719 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11720 CommuteVectorShuffleMask(M, NumElems);
11722 std::swap(V1IsSplat, V2IsSplat);
11726 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11727 // Shuffling low element of v1 into undef, just return v1.
11730 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11731 // the instruction selector will not match, so get a canonical MOVL with
11732 // swapped operands to undo the commute.
11733 return getMOVL(DAG, dl, VT, V2, V1);
11736 if (isUNPCKLMask(M, VT, HasInt256))
11737 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11739 if (isUNPCKHMask(M, VT, HasInt256))
11740 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11743 // Normalize mask so all entries that point to V2 points to its first
11744 // element then try to match unpck{h|l} again. If match, return a
11745 // new vector_shuffle with the corrected mask.p
11746 SmallVector<int, 8> NewMask(M.begin(), M.end());
11747 NormalizeMask(NewMask, NumElems);
11748 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11749 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11750 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11751 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11755 // Commute is back and try unpck* again.
11756 // FIXME: this seems wrong.
11757 CommuteVectorShuffleMask(M, NumElems);
11759 std::swap(V1IsSplat, V2IsSplat);
11761 if (isUNPCKLMask(M, VT, HasInt256))
11762 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11764 if (isUNPCKHMask(M, VT, HasInt256))
11765 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11768 // Normalize the node to match x86 shuffle ops if needed
11769 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11770 return DAG.getCommutedVectorShuffle(*SVOp);
11772 // The checks below are all present in isShuffleMaskLegal, but they are
11773 // inlined here right now to enable us to directly emit target specific
11774 // nodes, and remove one by one until they don't return Op anymore.
11776 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11777 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11778 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11779 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11782 if (isPSHUFHWMask(M, VT, HasInt256))
11783 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11784 getShufflePSHUFHWImmediate(SVOp),
11787 if (isPSHUFLWMask(M, VT, HasInt256))
11788 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11789 getShufflePSHUFLWImmediate(SVOp),
11792 unsigned MaskValue;
11793 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11795 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11797 if (isSHUFPMask(M, VT))
11798 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11799 getShuffleSHUFImmediate(SVOp), DAG);
11801 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11802 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11803 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11804 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11806 //===--------------------------------------------------------------------===//
11807 // Generate target specific nodes for 128 or 256-bit shuffles only
11808 // supported in the AVX instruction set.
11811 // Handle VMOVDDUPY permutations
11812 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11813 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11815 // Handle VPERMILPS/D* permutations
11816 if (isVPERMILPMask(M, VT)) {
11817 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11818 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11819 getShuffleSHUFImmediate(SVOp), DAG);
11820 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11821 getShuffleSHUFImmediate(SVOp), DAG);
11825 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11826 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11827 Idx*(NumElems/2), DAG, dl);
11829 // Handle VPERM2F128/VPERM2I128 permutations
11830 if (isVPERM2X128Mask(M, VT, HasFp256))
11831 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11832 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11834 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11835 return getINSERTPS(SVOp, dl, DAG);
11838 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11839 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11841 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11842 VT.is512BitVector()) {
11843 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11844 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11845 SmallVector<SDValue, 16> permclMask;
11846 for (unsigned i = 0; i != NumElems; ++i) {
11847 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11850 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11852 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11853 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11854 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11855 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11856 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11859 //===--------------------------------------------------------------------===//
11860 // Since no target specific shuffle was selected for this generic one,
11861 // lower it into other known shuffles. FIXME: this isn't true yet, but
11862 // this is the plan.
11865 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11866 if (VT == MVT::v8i16) {
11867 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11868 if (NewOp.getNode())
11872 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11873 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11874 if (NewOp.getNode())
11878 if (VT == MVT::v16i8) {
11879 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11880 if (NewOp.getNode())
11884 if (VT == MVT::v32i8) {
11885 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11886 if (NewOp.getNode())
11890 // Handle all 128-bit wide vectors with 4 elements, and match them with
11891 // several different shuffle types.
11892 if (NumElems == 4 && VT.is128BitVector())
11893 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11895 // Handle general 256-bit shuffles
11896 if (VT.is256BitVector())
11897 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11902 // This function assumes its argument is a BUILD_VECTOR of constants or
11903 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11905 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11906 unsigned &MaskValue) {
11908 unsigned NumElems = BuildVector->getNumOperands();
11909 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11910 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11911 unsigned NumElemsInLane = NumElems / NumLanes;
11913 // Blend for v16i16 should be symetric for the both lanes.
11914 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11915 SDValue EltCond = BuildVector->getOperand(i);
11916 SDValue SndLaneEltCond =
11917 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11919 int Lane1Cond = -1, Lane2Cond = -1;
11920 if (isa<ConstantSDNode>(EltCond))
11921 Lane1Cond = !isZero(EltCond);
11922 if (isa<ConstantSDNode>(SndLaneEltCond))
11923 Lane2Cond = !isZero(SndLaneEltCond);
11925 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11926 // Lane1Cond != 0, means we want the first argument.
11927 // Lane1Cond == 0, means we want the second argument.
11928 // The encoding of this argument is 0 for the first argument, 1
11929 // for the second. Therefore, invert the condition.
11930 MaskValue |= !Lane1Cond << i;
11931 else if (Lane1Cond < 0)
11932 MaskValue |= !Lane2Cond << i;
11939 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11941 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11942 SelectionDAG &DAG) {
11943 SDValue Cond = Op.getOperand(0);
11944 SDValue LHS = Op.getOperand(1);
11945 SDValue RHS = Op.getOperand(2);
11947 MVT VT = Op.getSimpleValueType();
11948 MVT EltVT = VT.getVectorElementType();
11949 unsigned NumElems = VT.getVectorNumElements();
11951 // There is no blend with immediate in AVX-512.
11952 if (VT.is512BitVector())
11955 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11957 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11960 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11963 // Check the mask for BLEND and build the value.
11964 unsigned MaskValue = 0;
11965 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11968 // Convert i32 vectors to floating point if it is not AVX2.
11969 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11971 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11972 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11974 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11975 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11978 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11979 DAG.getConstant(MaskValue, MVT::i32));
11980 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11983 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11984 // A vselect where all conditions and data are constants can be optimized into
11985 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11986 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11987 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11988 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11991 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
11992 if (BlendOp.getNode())
11995 // Some types for vselect were previously set to Expand, not Legal or
11996 // Custom. Return an empty SDValue so we fall-through to Expand, after
11997 // the Custom lowering phase.
11998 MVT VT = Op.getSimpleValueType();
11999 switch (VT.SimpleTy) {
12004 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12009 // We couldn't create a "Blend with immediate" node.
12010 // This node should still be legal, but we'll have to emit a blendv*
12015 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12016 MVT VT = Op.getSimpleValueType();
12019 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12022 if (VT.getSizeInBits() == 8) {
12023 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12024 Op.getOperand(0), Op.getOperand(1));
12025 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12026 DAG.getValueType(VT));
12027 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12030 if (VT.getSizeInBits() == 16) {
12031 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12032 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12034 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12035 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12036 DAG.getNode(ISD::BITCAST, dl,
12039 Op.getOperand(1)));
12040 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12041 Op.getOperand(0), Op.getOperand(1));
12042 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12043 DAG.getValueType(VT));
12044 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12047 if (VT == MVT::f32) {
12048 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12049 // the result back to FR32 register. It's only worth matching if the
12050 // result has a single use which is a store or a bitcast to i32. And in
12051 // the case of a store, it's not worth it if the index is a constant 0,
12052 // because a MOVSSmr can be used instead, which is smaller and faster.
12053 if (!Op.hasOneUse())
12055 SDNode *User = *Op.getNode()->use_begin();
12056 if ((User->getOpcode() != ISD::STORE ||
12057 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12058 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12059 (User->getOpcode() != ISD::BITCAST ||
12060 User->getValueType(0) != MVT::i32))
12062 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12063 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12066 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12069 if (VT == MVT::i32 || VT == MVT::i64) {
12070 // ExtractPS/pextrq works with constant index.
12071 if (isa<ConstantSDNode>(Op.getOperand(1)))
12077 /// Extract one bit from mask vector, like v16i1 or v8i1.
12078 /// AVX-512 feature.
12080 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12081 SDValue Vec = Op.getOperand(0);
12083 MVT VecVT = Vec.getSimpleValueType();
12084 SDValue Idx = Op.getOperand(1);
12085 MVT EltVT = Op.getSimpleValueType();
12087 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12089 // variable index can't be handled in mask registers,
12090 // extend vector to VR512
12091 if (!isa<ConstantSDNode>(Idx)) {
12092 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12093 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12094 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12095 ExtVT.getVectorElementType(), Ext, Idx);
12096 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12099 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12100 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12101 unsigned MaxSift = rc->getSize()*8 - 1;
12102 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12103 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12104 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12105 DAG.getConstant(MaxSift, MVT::i8));
12106 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12107 DAG.getIntPtrConstant(0));
12111 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12112 SelectionDAG &DAG) const {
12114 SDValue Vec = Op.getOperand(0);
12115 MVT VecVT = Vec.getSimpleValueType();
12116 SDValue Idx = Op.getOperand(1);
12118 if (Op.getSimpleValueType() == MVT::i1)
12119 return ExtractBitFromMaskVector(Op, DAG);
12121 if (!isa<ConstantSDNode>(Idx)) {
12122 if (VecVT.is512BitVector() ||
12123 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12124 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12127 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12128 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12129 MaskEltVT.getSizeInBits());
12131 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12132 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12133 getZeroVector(MaskVT, Subtarget, DAG, dl),
12134 Idx, DAG.getConstant(0, getPointerTy()));
12135 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12136 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12137 Perm, DAG.getConstant(0, getPointerTy()));
12142 // If this is a 256-bit vector result, first extract the 128-bit vector and
12143 // then extract the element from the 128-bit vector.
12144 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12146 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12147 // Get the 128-bit vector.
12148 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12149 MVT EltVT = VecVT.getVectorElementType();
12151 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12153 //if (IdxVal >= NumElems/2)
12154 // IdxVal -= NumElems/2;
12155 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12157 DAG.getConstant(IdxVal, MVT::i32));
12160 assert(VecVT.is128BitVector() && "Unexpected vector length");
12162 if (Subtarget->hasSSE41()) {
12163 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12168 MVT VT = Op.getSimpleValueType();
12169 // TODO: handle v16i8.
12170 if (VT.getSizeInBits() == 16) {
12171 SDValue Vec = Op.getOperand(0);
12172 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12174 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12175 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12176 DAG.getNode(ISD::BITCAST, dl,
12178 Op.getOperand(1)));
12179 // Transform it so it match pextrw which produces a 32-bit result.
12180 MVT EltVT = MVT::i32;
12181 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12182 Op.getOperand(0), Op.getOperand(1));
12183 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12184 DAG.getValueType(VT));
12185 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12188 if (VT.getSizeInBits() == 32) {
12189 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12193 // SHUFPS the element to the lowest double word, then movss.
12194 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12195 MVT VVT = Op.getOperand(0).getSimpleValueType();
12196 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12197 DAG.getUNDEF(VVT), Mask);
12198 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12199 DAG.getIntPtrConstant(0));
12202 if (VT.getSizeInBits() == 64) {
12203 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12204 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12205 // to match extract_elt for f64.
12206 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12210 // UNPCKHPD the element to the lowest double word, then movsd.
12211 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12212 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12213 int Mask[2] = { 1, -1 };
12214 MVT VVT = Op.getOperand(0).getSimpleValueType();
12215 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12216 DAG.getUNDEF(VVT), Mask);
12217 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12218 DAG.getIntPtrConstant(0));
12224 /// Insert one bit to mask vector, like v16i1 or v8i1.
12225 /// AVX-512 feature.
12227 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12229 SDValue Vec = Op.getOperand(0);
12230 SDValue Elt = Op.getOperand(1);
12231 SDValue Idx = Op.getOperand(2);
12232 MVT VecVT = Vec.getSimpleValueType();
12234 if (!isa<ConstantSDNode>(Idx)) {
12235 // Non constant index. Extend source and destination,
12236 // insert element and then truncate the result.
12237 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12238 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12239 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12240 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12241 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12242 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12245 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12246 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12247 if (Vec.getOpcode() == ISD::UNDEF)
12248 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12249 DAG.getConstant(IdxVal, MVT::i8));
12250 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12251 unsigned MaxSift = rc->getSize()*8 - 1;
12252 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12253 DAG.getConstant(MaxSift, MVT::i8));
12254 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12255 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12256 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12259 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12260 SelectionDAG &DAG) const {
12261 MVT VT = Op.getSimpleValueType();
12262 MVT EltVT = VT.getVectorElementType();
12264 if (EltVT == MVT::i1)
12265 return InsertBitToMaskVector(Op, DAG);
12268 SDValue N0 = Op.getOperand(0);
12269 SDValue N1 = Op.getOperand(1);
12270 SDValue N2 = Op.getOperand(2);
12271 if (!isa<ConstantSDNode>(N2))
12273 auto *N2C = cast<ConstantSDNode>(N2);
12274 unsigned IdxVal = N2C->getZExtValue();
12276 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12277 // into that, and then insert the subvector back into the result.
12278 if (VT.is256BitVector() || VT.is512BitVector()) {
12279 // Get the desired 128-bit vector half.
12280 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12282 // Insert the element into the desired half.
12283 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12284 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12286 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12287 DAG.getConstant(IdxIn128, MVT::i32));
12289 // Insert the changed part back to the 256-bit vector
12290 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12292 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12294 if (Subtarget->hasSSE41()) {
12295 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12297 if (VT == MVT::v8i16) {
12298 Opc = X86ISD::PINSRW;
12300 assert(VT == MVT::v16i8);
12301 Opc = X86ISD::PINSRB;
12304 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12306 if (N1.getValueType() != MVT::i32)
12307 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12308 if (N2.getValueType() != MVT::i32)
12309 N2 = DAG.getIntPtrConstant(IdxVal);
12310 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12313 if (EltVT == MVT::f32) {
12314 // Bits [7:6] of the constant are the source select. This will always be
12315 // zero here. The DAG Combiner may combine an extract_elt index into
12317 // bits. For example (insert (extract, 3), 2) could be matched by
12319 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12320 // Bits [5:4] of the constant are the destination select. This is the
12321 // value of the incoming immediate.
12322 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12323 // combine either bitwise AND or insert of float 0.0 to set these bits.
12324 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12325 // Create this as a scalar to vector..
12326 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12327 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12330 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12331 // PINSR* works with constant index.
12336 if (EltVT == MVT::i8)
12339 if (EltVT.getSizeInBits() == 16) {
12340 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12341 // as its second argument.
12342 if (N1.getValueType() != MVT::i32)
12343 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12344 if (N2.getValueType() != MVT::i32)
12345 N2 = DAG.getIntPtrConstant(IdxVal);
12346 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12351 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12353 MVT OpVT = Op.getSimpleValueType();
12355 // If this is a 256-bit vector result, first insert into a 128-bit
12356 // vector and then insert into the 256-bit vector.
12357 if (!OpVT.is128BitVector()) {
12358 // Insert into a 128-bit vector.
12359 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12360 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12361 OpVT.getVectorNumElements() / SizeFactor);
12363 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12365 // Insert the 128-bit vector.
12366 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12369 if (OpVT == MVT::v1i64 &&
12370 Op.getOperand(0).getValueType() == MVT::i64)
12371 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12373 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12374 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12375 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12376 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12379 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12380 // a simple subregister reference or explicit instructions to grab
12381 // upper bits of a vector.
12382 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12383 SelectionDAG &DAG) {
12385 SDValue In = Op.getOperand(0);
12386 SDValue Idx = Op.getOperand(1);
12387 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12388 MVT ResVT = Op.getSimpleValueType();
12389 MVT InVT = In.getSimpleValueType();
12391 if (Subtarget->hasFp256()) {
12392 if (ResVT.is128BitVector() &&
12393 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12394 isa<ConstantSDNode>(Idx)) {
12395 return Extract128BitVector(In, IdxVal, DAG, dl);
12397 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12398 isa<ConstantSDNode>(Idx)) {
12399 return Extract256BitVector(In, IdxVal, DAG, dl);
12405 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12406 // simple superregister reference or explicit instructions to insert
12407 // the upper bits of a vector.
12408 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12409 SelectionDAG &DAG) {
12410 if (Subtarget->hasFp256()) {
12411 SDLoc dl(Op.getNode());
12412 SDValue Vec = Op.getNode()->getOperand(0);
12413 SDValue SubVec = Op.getNode()->getOperand(1);
12414 SDValue Idx = Op.getNode()->getOperand(2);
12416 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12417 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12418 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12419 isa<ConstantSDNode>(Idx)) {
12420 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12421 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12424 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12425 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12426 isa<ConstantSDNode>(Idx)) {
12427 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12428 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12434 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12435 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12436 // one of the above mentioned nodes. It has to be wrapped because otherwise
12437 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12438 // be used to form addressing mode. These wrapped nodes will be selected
12441 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12442 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12444 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12445 // global base reg.
12446 unsigned char OpFlag = 0;
12447 unsigned WrapperKind = X86ISD::Wrapper;
12448 CodeModel::Model M = DAG.getTarget().getCodeModel();
12450 if (Subtarget->isPICStyleRIPRel() &&
12451 (M == CodeModel::Small || M == CodeModel::Kernel))
12452 WrapperKind = X86ISD::WrapperRIP;
12453 else if (Subtarget->isPICStyleGOT())
12454 OpFlag = X86II::MO_GOTOFF;
12455 else if (Subtarget->isPICStyleStubPIC())
12456 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12458 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12459 CP->getAlignment(),
12460 CP->getOffset(), OpFlag);
12462 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12463 // With PIC, the address is actually $g + Offset.
12465 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12466 DAG.getNode(X86ISD::GlobalBaseReg,
12467 SDLoc(), getPointerTy()),
12474 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12475 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12477 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12478 // global base reg.
12479 unsigned char OpFlag = 0;
12480 unsigned WrapperKind = X86ISD::Wrapper;
12481 CodeModel::Model M = DAG.getTarget().getCodeModel();
12483 if (Subtarget->isPICStyleRIPRel() &&
12484 (M == CodeModel::Small || M == CodeModel::Kernel))
12485 WrapperKind = X86ISD::WrapperRIP;
12486 else if (Subtarget->isPICStyleGOT())
12487 OpFlag = X86II::MO_GOTOFF;
12488 else if (Subtarget->isPICStyleStubPIC())
12489 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12491 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12494 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12496 // With PIC, the address is actually $g + Offset.
12498 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12499 DAG.getNode(X86ISD::GlobalBaseReg,
12500 SDLoc(), getPointerTy()),
12507 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12508 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12510 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12511 // global base reg.
12512 unsigned char OpFlag = 0;
12513 unsigned WrapperKind = X86ISD::Wrapper;
12514 CodeModel::Model M = DAG.getTarget().getCodeModel();
12516 if (Subtarget->isPICStyleRIPRel() &&
12517 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12518 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12519 OpFlag = X86II::MO_GOTPCREL;
12520 WrapperKind = X86ISD::WrapperRIP;
12521 } else if (Subtarget->isPICStyleGOT()) {
12522 OpFlag = X86II::MO_GOT;
12523 } else if (Subtarget->isPICStyleStubPIC()) {
12524 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12525 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12526 OpFlag = X86II::MO_DARWIN_NONLAZY;
12529 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12532 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12534 // With PIC, the address is actually $g + Offset.
12535 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12536 !Subtarget->is64Bit()) {
12537 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12538 DAG.getNode(X86ISD::GlobalBaseReg,
12539 SDLoc(), getPointerTy()),
12543 // For symbols that require a load from a stub to get the address, emit the
12545 if (isGlobalStubReference(OpFlag))
12546 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12547 MachinePointerInfo::getGOT(), false, false, false, 0);
12553 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12554 // Create the TargetBlockAddressAddress node.
12555 unsigned char OpFlags =
12556 Subtarget->ClassifyBlockAddressReference();
12557 CodeModel::Model M = DAG.getTarget().getCodeModel();
12558 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12559 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12561 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12564 if (Subtarget->isPICStyleRIPRel() &&
12565 (M == CodeModel::Small || M == CodeModel::Kernel))
12566 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12568 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12570 // With PIC, the address is actually $g + Offset.
12571 if (isGlobalRelativeToPICBase(OpFlags)) {
12572 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12573 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12581 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12582 int64_t Offset, SelectionDAG &DAG) const {
12583 // Create the TargetGlobalAddress node, folding in the constant
12584 // offset if it is legal.
12585 unsigned char OpFlags =
12586 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12587 CodeModel::Model M = DAG.getTarget().getCodeModel();
12589 if (OpFlags == X86II::MO_NO_FLAG &&
12590 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12591 // A direct static reference to a global.
12592 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12595 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12598 if (Subtarget->isPICStyleRIPRel() &&
12599 (M == CodeModel::Small || M == CodeModel::Kernel))
12600 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12602 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12604 // With PIC, the address is actually $g + Offset.
12605 if (isGlobalRelativeToPICBase(OpFlags)) {
12606 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12607 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12611 // For globals that require a load from a stub to get the address, emit the
12613 if (isGlobalStubReference(OpFlags))
12614 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12615 MachinePointerInfo::getGOT(), false, false, false, 0);
12617 // If there was a non-zero offset that we didn't fold, create an explicit
12618 // addition for it.
12620 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12621 DAG.getConstant(Offset, getPointerTy()));
12627 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12628 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12629 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12630 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12634 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12635 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12636 unsigned char OperandFlags, bool LocalDynamic = false) {
12637 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12640 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12641 GA->getValueType(0),
12645 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12649 SDValue Ops[] = { Chain, TGA, *InFlag };
12650 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12652 SDValue Ops[] = { Chain, TGA };
12653 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12656 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12657 MFI->setAdjustsStack(true);
12659 SDValue Flag = Chain.getValue(1);
12660 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12663 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12665 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12668 SDLoc dl(GA); // ? function entry point might be better
12669 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12670 DAG.getNode(X86ISD::GlobalBaseReg,
12671 SDLoc(), PtrVT), InFlag);
12672 InFlag = Chain.getValue(1);
12674 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12677 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12679 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12681 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12682 X86::RAX, X86II::MO_TLSGD);
12685 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12691 // Get the start address of the TLS block for this module.
12692 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12693 .getInfo<X86MachineFunctionInfo>();
12694 MFI->incNumLocalDynamicTLSAccesses();
12698 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12699 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12702 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12703 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12704 InFlag = Chain.getValue(1);
12705 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12706 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12709 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12713 unsigned char OperandFlags = X86II::MO_DTPOFF;
12714 unsigned WrapperKind = X86ISD::Wrapper;
12715 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12716 GA->getValueType(0),
12717 GA->getOffset(), OperandFlags);
12718 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12720 // Add x@dtpoff with the base.
12721 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12724 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12725 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12726 const EVT PtrVT, TLSModel::Model model,
12727 bool is64Bit, bool isPIC) {
12730 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12731 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12732 is64Bit ? 257 : 256));
12734 SDValue ThreadPointer =
12735 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12736 MachinePointerInfo(Ptr), false, false, false, 0);
12738 unsigned char OperandFlags = 0;
12739 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12741 unsigned WrapperKind = X86ISD::Wrapper;
12742 if (model == TLSModel::LocalExec) {
12743 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12744 } else if (model == TLSModel::InitialExec) {
12746 OperandFlags = X86II::MO_GOTTPOFF;
12747 WrapperKind = X86ISD::WrapperRIP;
12749 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12752 llvm_unreachable("Unexpected model");
12755 // emit "addl x@ntpoff,%eax" (local exec)
12756 // or "addl x@indntpoff,%eax" (initial exec)
12757 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12759 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12760 GA->getOffset(), OperandFlags);
12761 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12763 if (model == TLSModel::InitialExec) {
12764 if (isPIC && !is64Bit) {
12765 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12766 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12770 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12771 MachinePointerInfo::getGOT(), false, false, false, 0);
12774 // The address of the thread local variable is the add of the thread
12775 // pointer with the offset of the variable.
12776 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12780 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12782 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12783 const GlobalValue *GV = GA->getGlobal();
12785 if (Subtarget->isTargetELF()) {
12786 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12789 case TLSModel::GeneralDynamic:
12790 if (Subtarget->is64Bit())
12791 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12792 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12793 case TLSModel::LocalDynamic:
12794 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12795 Subtarget->is64Bit());
12796 case TLSModel::InitialExec:
12797 case TLSModel::LocalExec:
12798 return LowerToTLSExecModel(
12799 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12800 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12802 llvm_unreachable("Unknown TLS model.");
12805 if (Subtarget->isTargetDarwin()) {
12806 // Darwin only has one model of TLS. Lower to that.
12807 unsigned char OpFlag = 0;
12808 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12809 X86ISD::WrapperRIP : X86ISD::Wrapper;
12811 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12812 // global base reg.
12813 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12814 !Subtarget->is64Bit();
12816 OpFlag = X86II::MO_TLVP_PIC_BASE;
12818 OpFlag = X86II::MO_TLVP;
12820 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12821 GA->getValueType(0),
12822 GA->getOffset(), OpFlag);
12823 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12825 // With PIC32, the address is actually $g + Offset.
12827 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12828 DAG.getNode(X86ISD::GlobalBaseReg,
12829 SDLoc(), getPointerTy()),
12832 // Lowering the machine isd will make sure everything is in the right
12834 SDValue Chain = DAG.getEntryNode();
12835 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12836 SDValue Args[] = { Chain, Offset };
12837 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12839 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12840 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12841 MFI->setAdjustsStack(true);
12843 // And our return value (tls address) is in the standard call return value
12845 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12846 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12847 Chain.getValue(1));
12850 if (Subtarget->isTargetKnownWindowsMSVC() ||
12851 Subtarget->isTargetWindowsGNU()) {
12852 // Just use the implicit TLS architecture
12853 // Need to generate someting similar to:
12854 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12856 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12857 // mov rcx, qword [rdx+rcx*8]
12858 // mov eax, .tls$:tlsvar
12859 // [rax+rcx] contains the address
12860 // Windows 64bit: gs:0x58
12861 // Windows 32bit: fs:__tls_array
12864 SDValue Chain = DAG.getEntryNode();
12866 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12867 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12868 // use its literal value of 0x2C.
12869 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12870 ? Type::getInt8PtrTy(*DAG.getContext(),
12872 : Type::getInt32PtrTy(*DAG.getContext(),
12876 Subtarget->is64Bit()
12877 ? DAG.getIntPtrConstant(0x58)
12878 : (Subtarget->isTargetWindowsGNU()
12879 ? DAG.getIntPtrConstant(0x2C)
12880 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12882 SDValue ThreadPointer =
12883 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12884 MachinePointerInfo(Ptr), false, false, false, 0);
12886 // Load the _tls_index variable
12887 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12888 if (Subtarget->is64Bit())
12889 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12890 IDX, MachinePointerInfo(), MVT::i32,
12891 false, false, false, 0);
12893 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12894 false, false, false, 0);
12896 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12898 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12900 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12901 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12902 false, false, false, 0);
12904 // Get the offset of start of .tls section
12905 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12906 GA->getValueType(0),
12907 GA->getOffset(), X86II::MO_SECREL);
12908 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12910 // The address of the thread local variable is the add of the thread
12911 // pointer with the offset of the variable.
12912 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12915 llvm_unreachable("TLS not implemented for this target.");
12918 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12919 /// and take a 2 x i32 value to shift plus a shift amount.
12920 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12921 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12922 MVT VT = Op.getSimpleValueType();
12923 unsigned VTBits = VT.getSizeInBits();
12925 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12926 SDValue ShOpLo = Op.getOperand(0);
12927 SDValue ShOpHi = Op.getOperand(1);
12928 SDValue ShAmt = Op.getOperand(2);
12929 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12930 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12932 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12933 DAG.getConstant(VTBits - 1, MVT::i8));
12934 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12935 DAG.getConstant(VTBits - 1, MVT::i8))
12936 : DAG.getConstant(0, VT);
12938 SDValue Tmp2, Tmp3;
12939 if (Op.getOpcode() == ISD::SHL_PARTS) {
12940 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12941 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12943 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12944 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12947 // If the shift amount is larger or equal than the width of a part we can't
12948 // rely on the results of shld/shrd. Insert a test and select the appropriate
12949 // values for large shift amounts.
12950 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12951 DAG.getConstant(VTBits, MVT::i8));
12952 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12953 AndNode, DAG.getConstant(0, MVT::i8));
12956 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12957 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12958 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12960 if (Op.getOpcode() == ISD::SHL_PARTS) {
12961 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12962 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12964 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12965 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12968 SDValue Ops[2] = { Lo, Hi };
12969 return DAG.getMergeValues(Ops, dl);
12972 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12973 SelectionDAG &DAG) const {
12974 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12976 if (SrcVT.isVector())
12979 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12980 "Unknown SINT_TO_FP to lower!");
12982 // These are really Legal; return the operand so the caller accepts it as
12984 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12986 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12987 Subtarget->is64Bit()) {
12992 unsigned Size = SrcVT.getSizeInBits()/8;
12993 MachineFunction &MF = DAG.getMachineFunction();
12994 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12995 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12996 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12998 MachinePointerInfo::getFixedStack(SSFI),
13000 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13003 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13005 SelectionDAG &DAG) const {
13009 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13011 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13013 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13015 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13017 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13018 MachineMemOperand *MMO;
13020 int SSFI = FI->getIndex();
13022 DAG.getMachineFunction()
13023 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13024 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13026 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13027 StackSlot = StackSlot.getOperand(1);
13029 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13030 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13032 Tys, Ops, SrcVT, MMO);
13035 Chain = Result.getValue(1);
13036 SDValue InFlag = Result.getValue(2);
13038 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13039 // shouldn't be necessary except that RFP cannot be live across
13040 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13041 MachineFunction &MF = DAG.getMachineFunction();
13042 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13043 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13044 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13045 Tys = DAG.getVTList(MVT::Other);
13047 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13049 MachineMemOperand *MMO =
13050 DAG.getMachineFunction()
13051 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13052 MachineMemOperand::MOStore, SSFISize, SSFISize);
13054 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13055 Ops, Op.getValueType(), MMO);
13056 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13057 MachinePointerInfo::getFixedStack(SSFI),
13058 false, false, false, 0);
13064 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13065 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13066 SelectionDAG &DAG) const {
13067 // This algorithm is not obvious. Here it is what we're trying to output:
13070 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13071 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13073 haddpd %xmm0, %xmm0
13075 pshufd $0x4e, %xmm0, %xmm1
13081 LLVMContext *Context = DAG.getContext();
13083 // Build some magic constants.
13084 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13085 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13086 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13088 SmallVector<Constant*,2> CV1;
13090 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13091 APInt(64, 0x4330000000000000ULL))));
13093 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13094 APInt(64, 0x4530000000000000ULL))));
13095 Constant *C1 = ConstantVector::get(CV1);
13096 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13098 // Load the 64-bit value into an XMM register.
13099 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13101 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13102 MachinePointerInfo::getConstantPool(),
13103 false, false, false, 16);
13104 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13105 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13108 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13109 MachinePointerInfo::getConstantPool(),
13110 false, false, false, 16);
13111 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13112 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13115 if (Subtarget->hasSSE3()) {
13116 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13117 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13119 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13120 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13122 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13123 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13127 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13128 DAG.getIntPtrConstant(0));
13131 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13132 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13133 SelectionDAG &DAG) const {
13135 // FP constant to bias correct the final result.
13136 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13139 // Load the 32-bit value into an XMM register.
13140 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13143 // Zero out the upper parts of the register.
13144 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13146 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13147 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13148 DAG.getIntPtrConstant(0));
13150 // Or the load with the bias.
13151 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13152 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13153 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13154 MVT::v2f64, Load)),
13155 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13156 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13157 MVT::v2f64, Bias)));
13158 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13159 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13160 DAG.getIntPtrConstant(0));
13162 // Subtract the bias.
13163 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13165 // Handle final rounding.
13166 EVT DestVT = Op.getValueType();
13168 if (DestVT.bitsLT(MVT::f64))
13169 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13170 DAG.getIntPtrConstant(0));
13171 if (DestVT.bitsGT(MVT::f64))
13172 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13174 // Handle final rounding.
13178 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13179 SelectionDAG &DAG) const {
13180 SDValue N0 = Op.getOperand(0);
13181 MVT SVT = N0.getSimpleValueType();
13184 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13185 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13186 "Custom UINT_TO_FP is not supported!");
13188 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13189 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13190 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13193 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13194 SelectionDAG &DAG) const {
13195 SDValue N0 = Op.getOperand(0);
13198 if (Op.getValueType().isVector())
13199 return lowerUINT_TO_FP_vec(Op, DAG);
13201 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13202 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13203 // the optimization here.
13204 if (DAG.SignBitIsZero(N0))
13205 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13207 MVT SrcVT = N0.getSimpleValueType();
13208 MVT DstVT = Op.getSimpleValueType();
13209 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13210 return LowerUINT_TO_FP_i64(Op, DAG);
13211 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13212 return LowerUINT_TO_FP_i32(Op, DAG);
13213 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13216 // Make a 64-bit buffer, and use it to build an FILD.
13217 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13218 if (SrcVT == MVT::i32) {
13219 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13220 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13221 getPointerTy(), StackSlot, WordOff);
13222 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13223 StackSlot, MachinePointerInfo(),
13225 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13226 OffsetSlot, MachinePointerInfo(),
13228 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13232 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13233 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13234 StackSlot, MachinePointerInfo(),
13236 // For i64 source, we need to add the appropriate power of 2 if the input
13237 // was negative. This is the same as the optimization in
13238 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13239 // we must be careful to do the computation in x87 extended precision, not
13240 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13241 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13242 MachineMemOperand *MMO =
13243 DAG.getMachineFunction()
13244 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13245 MachineMemOperand::MOLoad, 8, 8);
13247 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13248 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13249 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13252 APInt FF(32, 0x5F800000ULL);
13254 // Check whether the sign bit is set.
13255 SDValue SignSet = DAG.getSetCC(dl,
13256 getSetCCResultType(*DAG.getContext(), MVT::i64),
13257 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13260 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13261 SDValue FudgePtr = DAG.getConstantPool(
13262 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13265 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13266 SDValue Zero = DAG.getIntPtrConstant(0);
13267 SDValue Four = DAG.getIntPtrConstant(4);
13268 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13270 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13272 // Load the value out, extending it from f32 to f80.
13273 // FIXME: Avoid the extend by constructing the right constant pool?
13274 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13275 FudgePtr, MachinePointerInfo::getConstantPool(),
13276 MVT::f32, false, false, false, 4);
13277 // Extend everything to 80 bits to force it to be done on x87.
13278 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13279 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13282 std::pair<SDValue,SDValue>
13283 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13284 bool IsSigned, bool IsReplace) const {
13287 EVT DstTy = Op.getValueType();
13289 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13290 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13294 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13295 DstTy.getSimpleVT() >= MVT::i16 &&
13296 "Unknown FP_TO_INT to lower!");
13298 // These are really Legal.
13299 if (DstTy == MVT::i32 &&
13300 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13301 return std::make_pair(SDValue(), SDValue());
13302 if (Subtarget->is64Bit() &&
13303 DstTy == MVT::i64 &&
13304 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13305 return std::make_pair(SDValue(), SDValue());
13307 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13308 // stack slot, or into the FTOL runtime function.
13309 MachineFunction &MF = DAG.getMachineFunction();
13310 unsigned MemSize = DstTy.getSizeInBits()/8;
13311 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13312 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13315 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13316 Opc = X86ISD::WIN_FTOL;
13318 switch (DstTy.getSimpleVT().SimpleTy) {
13319 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13320 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13321 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13322 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13325 SDValue Chain = DAG.getEntryNode();
13326 SDValue Value = Op.getOperand(0);
13327 EVT TheVT = Op.getOperand(0).getValueType();
13328 // FIXME This causes a redundant load/store if the SSE-class value is already
13329 // in memory, such as if it is on the callstack.
13330 if (isScalarFPTypeInSSEReg(TheVT)) {
13331 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13332 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13333 MachinePointerInfo::getFixedStack(SSFI),
13335 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13337 Chain, StackSlot, DAG.getValueType(TheVT)
13340 MachineMemOperand *MMO =
13341 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13342 MachineMemOperand::MOLoad, MemSize, MemSize);
13343 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13344 Chain = Value.getValue(1);
13345 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13346 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13349 MachineMemOperand *MMO =
13350 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13351 MachineMemOperand::MOStore, MemSize, MemSize);
13353 if (Opc != X86ISD::WIN_FTOL) {
13354 // Build the FP_TO_INT*_IN_MEM
13355 SDValue Ops[] = { Chain, Value, StackSlot };
13356 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13358 return std::make_pair(FIST, StackSlot);
13360 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13361 DAG.getVTList(MVT::Other, MVT::Glue),
13363 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13364 MVT::i32, ftol.getValue(1));
13365 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13366 MVT::i32, eax.getValue(2));
13367 SDValue Ops[] = { eax, edx };
13368 SDValue pair = IsReplace
13369 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13370 : DAG.getMergeValues(Ops, DL);
13371 return std::make_pair(pair, SDValue());
13375 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13376 const X86Subtarget *Subtarget) {
13377 MVT VT = Op->getSimpleValueType(0);
13378 SDValue In = Op->getOperand(0);
13379 MVT InVT = In.getSimpleValueType();
13382 // Optimize vectors in AVX mode:
13385 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13386 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13387 // Concat upper and lower parts.
13390 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13391 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13392 // Concat upper and lower parts.
13395 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13396 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13397 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13400 if (Subtarget->hasInt256())
13401 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13403 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13404 SDValue Undef = DAG.getUNDEF(InVT);
13405 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13406 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13407 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13409 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13410 VT.getVectorNumElements()/2);
13412 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13413 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13415 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13418 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13419 SelectionDAG &DAG) {
13420 MVT VT = Op->getSimpleValueType(0);
13421 SDValue In = Op->getOperand(0);
13422 MVT InVT = In.getSimpleValueType();
13424 unsigned int NumElts = VT.getVectorNumElements();
13425 if (NumElts != 8 && NumElts != 16)
13428 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13429 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13431 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13433 // Now we have only mask extension
13434 assert(InVT.getVectorElementType() == MVT::i1);
13435 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13436 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13437 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13438 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13439 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13440 MachinePointerInfo::getConstantPool(),
13441 false, false, false, Alignment);
13443 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13444 if (VT.is512BitVector())
13446 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13449 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13450 SelectionDAG &DAG) {
13451 if (Subtarget->hasFp256()) {
13452 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13460 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13461 SelectionDAG &DAG) {
13463 MVT VT = Op.getSimpleValueType();
13464 SDValue In = Op.getOperand(0);
13465 MVT SVT = In.getSimpleValueType();
13467 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13468 return LowerZERO_EXTEND_AVX512(Op, DAG);
13470 if (Subtarget->hasFp256()) {
13471 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13476 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13477 VT.getVectorNumElements() != SVT.getVectorNumElements());
13481 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13483 MVT VT = Op.getSimpleValueType();
13484 SDValue In = Op.getOperand(0);
13485 MVT InVT = In.getSimpleValueType();
13487 if (VT == MVT::i1) {
13488 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13489 "Invalid scalar TRUNCATE operation");
13490 if (InVT.getSizeInBits() >= 32)
13492 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13493 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13495 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13496 "Invalid TRUNCATE operation");
13498 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13499 if (VT.getVectorElementType().getSizeInBits() >=8)
13500 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13502 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13503 unsigned NumElts = InVT.getVectorNumElements();
13504 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13505 if (InVT.getSizeInBits() < 512) {
13506 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13507 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13511 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13512 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13513 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13514 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13515 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13516 MachinePointerInfo::getConstantPool(),
13517 false, false, false, Alignment);
13518 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13519 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13520 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13523 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13524 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13525 if (Subtarget->hasInt256()) {
13526 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13527 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13528 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13530 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13531 DAG.getIntPtrConstant(0));
13534 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13535 DAG.getIntPtrConstant(0));
13536 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13537 DAG.getIntPtrConstant(2));
13538 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13539 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13540 static const int ShufMask[] = {0, 2, 4, 6};
13541 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13544 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13545 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13546 if (Subtarget->hasInt256()) {
13547 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13549 SmallVector<SDValue,32> pshufbMask;
13550 for (unsigned i = 0; i < 2; ++i) {
13551 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13552 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13553 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13554 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13555 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13556 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13557 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13558 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13559 for (unsigned j = 0; j < 8; ++j)
13560 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13562 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13563 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13564 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13566 static const int ShufMask[] = {0, 2, -1, -1};
13567 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13569 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13570 DAG.getIntPtrConstant(0));
13571 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13574 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13575 DAG.getIntPtrConstant(0));
13577 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13578 DAG.getIntPtrConstant(4));
13580 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13581 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13583 // The PSHUFB mask:
13584 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13585 -1, -1, -1, -1, -1, -1, -1, -1};
13587 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13588 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13589 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13591 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13592 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13594 // The MOVLHPS Mask:
13595 static const int ShufMask2[] = {0, 1, 4, 5};
13596 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13597 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13600 // Handle truncation of V256 to V128 using shuffles.
13601 if (!VT.is128BitVector() || !InVT.is256BitVector())
13604 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13606 unsigned NumElems = VT.getVectorNumElements();
13607 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13609 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13610 // Prepare truncation shuffle mask
13611 for (unsigned i = 0; i != NumElems; ++i)
13612 MaskVec[i] = i * 2;
13613 SDValue V = DAG.getVectorShuffle(NVT, DL,
13614 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13615 DAG.getUNDEF(NVT), &MaskVec[0]);
13616 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13617 DAG.getIntPtrConstant(0));
13620 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13621 SelectionDAG &DAG) const {
13622 assert(!Op.getSimpleValueType().isVector());
13624 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13625 /*IsSigned=*/ true, /*IsReplace=*/ false);
13626 SDValue FIST = Vals.first, StackSlot = Vals.second;
13627 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13628 if (!FIST.getNode()) return Op;
13630 if (StackSlot.getNode())
13631 // Load the result.
13632 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13633 FIST, StackSlot, MachinePointerInfo(),
13634 false, false, false, 0);
13636 // The node is the result.
13640 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13641 SelectionDAG &DAG) const {
13642 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13643 /*IsSigned=*/ false, /*IsReplace=*/ false);
13644 SDValue FIST = Vals.first, StackSlot = Vals.second;
13645 assert(FIST.getNode() && "Unexpected failure");
13647 if (StackSlot.getNode())
13648 // Load the result.
13649 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13650 FIST, StackSlot, MachinePointerInfo(),
13651 false, false, false, 0);
13653 // The node is the result.
13657 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13659 MVT VT = Op.getSimpleValueType();
13660 SDValue In = Op.getOperand(0);
13661 MVT SVT = In.getSimpleValueType();
13663 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13665 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13666 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13667 In, DAG.getUNDEF(SVT)));
13670 // The only differences between FABS and FNEG are the mask and the logic op.
13671 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13672 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13673 "Wrong opcode for lowering FABS or FNEG.");
13675 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13677 MVT VT = Op.getSimpleValueType();
13678 // Assume scalar op for initialization; update for vector if needed.
13679 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13680 // generate a 16-byte vector constant and logic op even for the scalar case.
13681 // Using a 16-byte mask allows folding the load of the mask with
13682 // the logic op, so it can save (~4 bytes) on code size.
13684 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13685 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13686 // decide if we should generate a 16-byte constant mask when we only need 4 or
13687 // 8 bytes for the scalar case.
13688 if (VT.isVector()) {
13689 EltVT = VT.getVectorElementType();
13690 NumElts = VT.getVectorNumElements();
13693 unsigned EltBits = EltVT.getSizeInBits();
13694 LLVMContext *Context = DAG.getContext();
13695 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13697 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13698 Constant *C = ConstantInt::get(*Context, MaskElt);
13699 C = ConstantVector::getSplat(NumElts, C);
13700 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13701 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13702 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13703 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13704 MachinePointerInfo::getConstantPool(),
13705 false, false, false, Alignment);
13707 if (VT.isVector()) {
13708 // For a vector, cast operands to a vector type, perform the logic op,
13709 // and cast the result back to the original value type.
13710 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13711 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13712 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13713 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13714 return DAG.getNode(ISD::BITCAST, dl, VT,
13715 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13717 // If not vector, then scalar.
13718 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13719 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13722 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13723 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13724 LLVMContext *Context = DAG.getContext();
13725 SDValue Op0 = Op.getOperand(0);
13726 SDValue Op1 = Op.getOperand(1);
13728 MVT VT = Op.getSimpleValueType();
13729 MVT SrcVT = Op1.getSimpleValueType();
13731 // If second operand is smaller, extend it first.
13732 if (SrcVT.bitsLT(VT)) {
13733 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13736 // And if it is bigger, shrink it first.
13737 if (SrcVT.bitsGT(VT)) {
13738 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13742 // At this point the operands and the result should have the same
13743 // type, and that won't be f80 since that is not custom lowered.
13745 // First get the sign bit of second operand.
13746 SmallVector<Constant*,4> CV;
13747 if (SrcVT == MVT::f64) {
13748 const fltSemantics &Sem = APFloat::IEEEdouble;
13749 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13750 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13752 const fltSemantics &Sem = APFloat::IEEEsingle;
13753 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13754 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13755 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13756 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13758 Constant *C = ConstantVector::get(CV);
13759 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13760 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13761 MachinePointerInfo::getConstantPool(),
13762 false, false, false, 16);
13763 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13765 // Shift sign bit right or left if the two operands have different types.
13766 if (SrcVT.bitsGT(VT)) {
13767 // Op0 is MVT::f32, Op1 is MVT::f64.
13768 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13769 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13770 DAG.getConstant(32, MVT::i32));
13771 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13772 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13773 DAG.getIntPtrConstant(0));
13776 // Clear first operand sign bit.
13778 if (VT == MVT::f64) {
13779 const fltSemantics &Sem = APFloat::IEEEdouble;
13780 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13781 APInt(64, ~(1ULL << 63)))));
13782 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13784 const fltSemantics &Sem = APFloat::IEEEsingle;
13785 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13786 APInt(32, ~(1U << 31)))));
13787 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13788 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13789 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13791 C = ConstantVector::get(CV);
13792 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13793 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13794 MachinePointerInfo::getConstantPool(),
13795 false, false, false, 16);
13796 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13798 // Or the value with the sign bit.
13799 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13802 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13803 SDValue N0 = Op.getOperand(0);
13805 MVT VT = Op.getSimpleValueType();
13807 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13808 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13809 DAG.getConstant(1, VT));
13810 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13813 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13815 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13816 SelectionDAG &DAG) {
13817 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13819 if (!Subtarget->hasSSE41())
13822 if (!Op->hasOneUse())
13825 SDNode *N = Op.getNode();
13828 SmallVector<SDValue, 8> Opnds;
13829 DenseMap<SDValue, unsigned> VecInMap;
13830 SmallVector<SDValue, 8> VecIns;
13831 EVT VT = MVT::Other;
13833 // Recognize a special case where a vector is casted into wide integer to
13835 Opnds.push_back(N->getOperand(0));
13836 Opnds.push_back(N->getOperand(1));
13838 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13839 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13840 // BFS traverse all OR'd operands.
13841 if (I->getOpcode() == ISD::OR) {
13842 Opnds.push_back(I->getOperand(0));
13843 Opnds.push_back(I->getOperand(1));
13844 // Re-evaluate the number of nodes to be traversed.
13845 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13849 // Quit if a non-EXTRACT_VECTOR_ELT
13850 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13853 // Quit if without a constant index.
13854 SDValue Idx = I->getOperand(1);
13855 if (!isa<ConstantSDNode>(Idx))
13858 SDValue ExtractedFromVec = I->getOperand(0);
13859 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13860 if (M == VecInMap.end()) {
13861 VT = ExtractedFromVec.getValueType();
13862 // Quit if not 128/256-bit vector.
13863 if (!VT.is128BitVector() && !VT.is256BitVector())
13865 // Quit if not the same type.
13866 if (VecInMap.begin() != VecInMap.end() &&
13867 VT != VecInMap.begin()->first.getValueType())
13869 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13870 VecIns.push_back(ExtractedFromVec);
13872 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13875 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13876 "Not extracted from 128-/256-bit vector.");
13878 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13880 for (DenseMap<SDValue, unsigned>::const_iterator
13881 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13882 // Quit if not all elements are used.
13883 if (I->second != FullMask)
13887 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13889 // Cast all vectors into TestVT for PTEST.
13890 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13891 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13893 // If more than one full vectors are evaluated, OR them first before PTEST.
13894 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13895 // Each iteration will OR 2 nodes and append the result until there is only
13896 // 1 node left, i.e. the final OR'd value of all vectors.
13897 SDValue LHS = VecIns[Slot];
13898 SDValue RHS = VecIns[Slot + 1];
13899 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13902 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13903 VecIns.back(), VecIns.back());
13906 /// \brief return true if \c Op has a use that doesn't just read flags.
13907 static bool hasNonFlagsUse(SDValue Op) {
13908 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13910 SDNode *User = *UI;
13911 unsigned UOpNo = UI.getOperandNo();
13912 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13913 // Look pass truncate.
13914 UOpNo = User->use_begin().getOperandNo();
13915 User = *User->use_begin();
13918 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13919 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13925 /// Emit nodes that will be selected as "test Op0,Op0", or something
13927 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13928 SelectionDAG &DAG) const {
13929 if (Op.getValueType() == MVT::i1)
13930 // KORTEST instruction should be selected
13931 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13932 DAG.getConstant(0, Op.getValueType()));
13934 // CF and OF aren't always set the way we want. Determine which
13935 // of these we need.
13936 bool NeedCF = false;
13937 bool NeedOF = false;
13940 case X86::COND_A: case X86::COND_AE:
13941 case X86::COND_B: case X86::COND_BE:
13944 case X86::COND_G: case X86::COND_GE:
13945 case X86::COND_L: case X86::COND_LE:
13946 case X86::COND_O: case X86::COND_NO: {
13947 // Check if we really need to set the
13948 // Overflow flag. If NoSignedWrap is present
13949 // that is not actually needed.
13950 switch (Op->getOpcode()) {
13955 const BinaryWithFlagsSDNode *BinNode =
13956 cast<BinaryWithFlagsSDNode>(Op.getNode());
13957 if (BinNode->hasNoSignedWrap())
13967 // See if we can use the EFLAGS value from the operand instead of
13968 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13969 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13970 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13971 // Emit a CMP with 0, which is the TEST pattern.
13972 //if (Op.getValueType() == MVT::i1)
13973 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13974 // DAG.getConstant(0, MVT::i1));
13975 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13976 DAG.getConstant(0, Op.getValueType()));
13978 unsigned Opcode = 0;
13979 unsigned NumOperands = 0;
13981 // Truncate operations may prevent the merge of the SETCC instruction
13982 // and the arithmetic instruction before it. Attempt to truncate the operands
13983 // of the arithmetic instruction and use a reduced bit-width instruction.
13984 bool NeedTruncation = false;
13985 SDValue ArithOp = Op;
13986 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13987 SDValue Arith = Op->getOperand(0);
13988 // Both the trunc and the arithmetic op need to have one user each.
13989 if (Arith->hasOneUse())
13990 switch (Arith.getOpcode()) {
13997 NeedTruncation = true;
14003 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14004 // which may be the result of a CAST. We use the variable 'Op', which is the
14005 // non-casted variable when we check for possible users.
14006 switch (ArithOp.getOpcode()) {
14008 // Due to an isel shortcoming, be conservative if this add is likely to be
14009 // selected as part of a load-modify-store instruction. When the root node
14010 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14011 // uses of other nodes in the match, such as the ADD in this case. This
14012 // leads to the ADD being left around and reselected, with the result being
14013 // two adds in the output. Alas, even if none our users are stores, that
14014 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14015 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14016 // climbing the DAG back to the root, and it doesn't seem to be worth the
14018 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14019 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14020 if (UI->getOpcode() != ISD::CopyToReg &&
14021 UI->getOpcode() != ISD::SETCC &&
14022 UI->getOpcode() != ISD::STORE)
14025 if (ConstantSDNode *C =
14026 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14027 // An add of one will be selected as an INC.
14028 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14029 Opcode = X86ISD::INC;
14034 // An add of negative one (subtract of one) will be selected as a DEC.
14035 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14036 Opcode = X86ISD::DEC;
14042 // Otherwise use a regular EFLAGS-setting add.
14043 Opcode = X86ISD::ADD;
14048 // If we have a constant logical shift that's only used in a comparison
14049 // against zero turn it into an equivalent AND. This allows turning it into
14050 // a TEST instruction later.
14051 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14052 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14053 EVT VT = Op.getValueType();
14054 unsigned BitWidth = VT.getSizeInBits();
14055 unsigned ShAmt = Op->getConstantOperandVal(1);
14056 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14058 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14059 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14060 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14061 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14063 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14064 DAG.getConstant(Mask, VT));
14065 DAG.ReplaceAllUsesWith(Op, New);
14071 // If the primary and result isn't used, don't bother using X86ISD::AND,
14072 // because a TEST instruction will be better.
14073 if (!hasNonFlagsUse(Op))
14079 // Due to the ISEL shortcoming noted above, be conservative if this op is
14080 // likely to be selected as part of a load-modify-store instruction.
14081 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14082 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14083 if (UI->getOpcode() == ISD::STORE)
14086 // Otherwise use a regular EFLAGS-setting instruction.
14087 switch (ArithOp.getOpcode()) {
14088 default: llvm_unreachable("unexpected operator!");
14089 case ISD::SUB: Opcode = X86ISD::SUB; break;
14090 case ISD::XOR: Opcode = X86ISD::XOR; break;
14091 case ISD::AND: Opcode = X86ISD::AND; break;
14093 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14094 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14095 if (EFLAGS.getNode())
14098 Opcode = X86ISD::OR;
14112 return SDValue(Op.getNode(), 1);
14118 // If we found that truncation is beneficial, perform the truncation and
14120 if (NeedTruncation) {
14121 EVT VT = Op.getValueType();
14122 SDValue WideVal = Op->getOperand(0);
14123 EVT WideVT = WideVal.getValueType();
14124 unsigned ConvertedOp = 0;
14125 // Use a target machine opcode to prevent further DAGCombine
14126 // optimizations that may separate the arithmetic operations
14127 // from the setcc node.
14128 switch (WideVal.getOpcode()) {
14130 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14131 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14132 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14133 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14134 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14139 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14140 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14141 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14142 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14148 // Emit a CMP with 0, which is the TEST pattern.
14149 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14150 DAG.getConstant(0, Op.getValueType()));
14152 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14153 SmallVector<SDValue, 4> Ops;
14154 for (unsigned i = 0; i != NumOperands; ++i)
14155 Ops.push_back(Op.getOperand(i));
14157 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14158 DAG.ReplaceAllUsesWith(Op, New);
14159 return SDValue(New.getNode(), 1);
14162 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14164 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14165 SDLoc dl, SelectionDAG &DAG) const {
14166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14167 if (C->getAPIntValue() == 0)
14168 return EmitTest(Op0, X86CC, dl, DAG);
14170 if (Op0.getValueType() == MVT::i1)
14171 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14174 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14175 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14176 // Do the comparison at i32 if it's smaller, besides the Atom case.
14177 // This avoids subregister aliasing issues. Keep the smaller reference
14178 // if we're optimizing for size, however, as that'll allow better folding
14179 // of memory operations.
14180 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14181 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14182 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14183 !Subtarget->isAtom()) {
14184 unsigned ExtendOp =
14185 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14186 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14187 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14189 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14190 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14191 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14193 return SDValue(Sub.getNode(), 1);
14195 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14198 /// Convert a comparison if required by the subtarget.
14199 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14200 SelectionDAG &DAG) const {
14201 // If the subtarget does not support the FUCOMI instruction, floating-point
14202 // comparisons have to be converted.
14203 if (Subtarget->hasCMov() ||
14204 Cmp.getOpcode() != X86ISD::CMP ||
14205 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14206 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14209 // The instruction selector will select an FUCOM instruction instead of
14210 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14211 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14212 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14214 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14215 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14216 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14217 DAG.getConstant(8, MVT::i8));
14218 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14219 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14222 static bool isAllOnes(SDValue V) {
14223 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14224 return C && C->isAllOnesValue();
14227 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14228 /// if it's possible.
14229 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14230 SDLoc dl, SelectionDAG &DAG) const {
14231 SDValue Op0 = And.getOperand(0);
14232 SDValue Op1 = And.getOperand(1);
14233 if (Op0.getOpcode() == ISD::TRUNCATE)
14234 Op0 = Op0.getOperand(0);
14235 if (Op1.getOpcode() == ISD::TRUNCATE)
14236 Op1 = Op1.getOperand(0);
14239 if (Op1.getOpcode() == ISD::SHL)
14240 std::swap(Op0, Op1);
14241 if (Op0.getOpcode() == ISD::SHL) {
14242 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14243 if (And00C->getZExtValue() == 1) {
14244 // If we looked past a truncate, check that it's only truncating away
14246 unsigned BitWidth = Op0.getValueSizeInBits();
14247 unsigned AndBitWidth = And.getValueSizeInBits();
14248 if (BitWidth > AndBitWidth) {
14250 DAG.computeKnownBits(Op0, Zeros, Ones);
14251 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14255 RHS = Op0.getOperand(1);
14257 } else if (Op1.getOpcode() == ISD::Constant) {
14258 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14259 uint64_t AndRHSVal = AndRHS->getZExtValue();
14260 SDValue AndLHS = Op0;
14262 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14263 LHS = AndLHS.getOperand(0);
14264 RHS = AndLHS.getOperand(1);
14267 // Use BT if the immediate can't be encoded in a TEST instruction.
14268 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14270 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14274 if (LHS.getNode()) {
14275 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14276 // instruction. Since the shift amount is in-range-or-undefined, we know
14277 // that doing a bittest on the i32 value is ok. We extend to i32 because
14278 // the encoding for the i16 version is larger than the i32 version.
14279 // Also promote i16 to i32 for performance / code size reason.
14280 if (LHS.getValueType() == MVT::i8 ||
14281 LHS.getValueType() == MVT::i16)
14282 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14284 // If the operand types disagree, extend the shift amount to match. Since
14285 // BT ignores high bits (like shifts) we can use anyextend.
14286 if (LHS.getValueType() != RHS.getValueType())
14287 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14289 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14290 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14291 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14292 DAG.getConstant(Cond, MVT::i8), BT);
14298 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14300 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14305 // SSE Condition code mapping:
14314 switch (SetCCOpcode) {
14315 default: llvm_unreachable("Unexpected SETCC condition");
14317 case ISD::SETEQ: SSECC = 0; break;
14319 case ISD::SETGT: Swap = true; // Fallthrough
14321 case ISD::SETOLT: SSECC = 1; break;
14323 case ISD::SETGE: Swap = true; // Fallthrough
14325 case ISD::SETOLE: SSECC = 2; break;
14326 case ISD::SETUO: SSECC = 3; break;
14328 case ISD::SETNE: SSECC = 4; break;
14329 case ISD::SETULE: Swap = true; // Fallthrough
14330 case ISD::SETUGE: SSECC = 5; break;
14331 case ISD::SETULT: Swap = true; // Fallthrough
14332 case ISD::SETUGT: SSECC = 6; break;
14333 case ISD::SETO: SSECC = 7; break;
14335 case ISD::SETONE: SSECC = 8; break;
14338 std::swap(Op0, Op1);
14343 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14344 // ones, and then concatenate the result back.
14345 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14346 MVT VT = Op.getSimpleValueType();
14348 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14349 "Unsupported value type for operation");
14351 unsigned NumElems = VT.getVectorNumElements();
14353 SDValue CC = Op.getOperand(2);
14355 // Extract the LHS vectors
14356 SDValue LHS = Op.getOperand(0);
14357 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14358 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14360 // Extract the RHS vectors
14361 SDValue RHS = Op.getOperand(1);
14362 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14363 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14365 // Issue the operation on the smaller types and concatenate the result back
14366 MVT EltVT = VT.getVectorElementType();
14367 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14368 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14369 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14370 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14373 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14374 const X86Subtarget *Subtarget) {
14375 SDValue Op0 = Op.getOperand(0);
14376 SDValue Op1 = Op.getOperand(1);
14377 SDValue CC = Op.getOperand(2);
14378 MVT VT = Op.getSimpleValueType();
14381 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14382 Op.getValueType().getScalarType() == MVT::i1 &&
14383 "Cannot set masked compare for this operation");
14385 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14387 bool Unsigned = false;
14390 switch (SetCCOpcode) {
14391 default: llvm_unreachable("Unexpected SETCC condition");
14392 case ISD::SETNE: SSECC = 4; break;
14393 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14394 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14395 case ISD::SETLT: Swap = true; //fall-through
14396 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14397 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14398 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14399 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14400 case ISD::SETULE: Unsigned = true; //fall-through
14401 case ISD::SETLE: SSECC = 2; break;
14405 std::swap(Op0, Op1);
14407 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14408 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14409 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14410 DAG.getConstant(SSECC, MVT::i8));
14413 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14414 /// operand \p Op1. If non-trivial (for example because it's not constant)
14415 /// return an empty value.
14416 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14418 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14422 MVT VT = Op1.getSimpleValueType();
14423 MVT EVT = VT.getVectorElementType();
14424 unsigned n = VT.getVectorNumElements();
14425 SmallVector<SDValue, 8> ULTOp1;
14427 for (unsigned i = 0; i < n; ++i) {
14428 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14429 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14432 // Avoid underflow.
14433 APInt Val = Elt->getAPIntValue();
14437 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14440 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14443 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14444 SelectionDAG &DAG) {
14445 SDValue Op0 = Op.getOperand(0);
14446 SDValue Op1 = Op.getOperand(1);
14447 SDValue CC = Op.getOperand(2);
14448 MVT VT = Op.getSimpleValueType();
14449 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14450 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14455 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14456 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14459 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14460 unsigned Opc = X86ISD::CMPP;
14461 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14462 assert(VT.getVectorNumElements() <= 16);
14463 Opc = X86ISD::CMPM;
14465 // In the two special cases we can't handle, emit two comparisons.
14468 unsigned CombineOpc;
14469 if (SetCCOpcode == ISD::SETUEQ) {
14470 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14472 assert(SetCCOpcode == ISD::SETONE);
14473 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14476 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14477 DAG.getConstant(CC0, MVT::i8));
14478 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14479 DAG.getConstant(CC1, MVT::i8));
14480 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14482 // Handle all other FP comparisons here.
14483 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14484 DAG.getConstant(SSECC, MVT::i8));
14487 // Break 256-bit integer vector compare into smaller ones.
14488 if (VT.is256BitVector() && !Subtarget->hasInt256())
14489 return Lower256IntVSETCC(Op, DAG);
14491 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14492 EVT OpVT = Op1.getValueType();
14493 if (Subtarget->hasAVX512()) {
14494 if (Op1.getValueType().is512BitVector() ||
14495 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14496 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14497 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14499 // In AVX-512 architecture setcc returns mask with i1 elements,
14500 // But there is no compare instruction for i8 and i16 elements in KNL.
14501 // We are not talking about 512-bit operands in this case, these
14502 // types are illegal.
14504 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14505 OpVT.getVectorElementType().getSizeInBits() >= 8))
14506 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14507 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14510 // We are handling one of the integer comparisons here. Since SSE only has
14511 // GT and EQ comparisons for integer, swapping operands and multiple
14512 // operations may be required for some comparisons.
14514 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14515 bool Subus = false;
14517 switch (SetCCOpcode) {
14518 default: llvm_unreachable("Unexpected SETCC condition");
14519 case ISD::SETNE: Invert = true;
14520 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14521 case ISD::SETLT: Swap = true;
14522 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14523 case ISD::SETGE: Swap = true;
14524 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14525 Invert = true; break;
14526 case ISD::SETULT: Swap = true;
14527 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14528 FlipSigns = true; break;
14529 case ISD::SETUGE: Swap = true;
14530 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14531 FlipSigns = true; Invert = true; break;
14534 // Special case: Use min/max operations for SETULE/SETUGE
14535 MVT VET = VT.getVectorElementType();
14537 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14538 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14541 switch (SetCCOpcode) {
14543 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14544 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14547 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14550 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14551 if (!MinMax && hasSubus) {
14552 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14554 // t = psubus Op0, Op1
14555 // pcmpeq t, <0..0>
14556 switch (SetCCOpcode) {
14558 case ISD::SETULT: {
14559 // If the comparison is against a constant we can turn this into a
14560 // setule. With psubus, setule does not require a swap. This is
14561 // beneficial because the constant in the register is no longer
14562 // destructed as the destination so it can be hoisted out of a loop.
14563 // Only do this pre-AVX since vpcmp* is no longer destructive.
14564 if (Subtarget->hasAVX())
14566 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14567 if (ULEOp1.getNode()) {
14569 Subus = true; Invert = false; Swap = false;
14573 // Psubus is better than flip-sign because it requires no inversion.
14574 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14575 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14579 Opc = X86ISD::SUBUS;
14585 std::swap(Op0, Op1);
14587 // Check that the operation in question is available (most are plain SSE2,
14588 // but PCMPGTQ and PCMPEQQ have different requirements).
14589 if (VT == MVT::v2i64) {
14590 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14591 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14593 // First cast everything to the right type.
14594 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14595 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14597 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14598 // bits of the inputs before performing those operations. The lower
14599 // compare is always unsigned.
14602 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14604 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14605 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14606 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14607 Sign, Zero, Sign, Zero);
14609 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14610 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14612 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14613 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14614 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14616 // Create masks for only the low parts/high parts of the 64 bit integers.
14617 static const int MaskHi[] = { 1, 1, 3, 3 };
14618 static const int MaskLo[] = { 0, 0, 2, 2 };
14619 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14620 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14621 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14623 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14624 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14627 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14629 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14632 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14633 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14634 // pcmpeqd + pshufd + pand.
14635 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14637 // First cast everything to the right type.
14638 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14639 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14642 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14644 // Make sure the lower and upper halves are both all-ones.
14645 static const int Mask[] = { 1, 0, 3, 2 };
14646 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14647 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14650 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14652 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14656 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14657 // bits of the inputs before performing those operations.
14659 EVT EltVT = VT.getVectorElementType();
14660 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14661 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14662 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14665 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14667 // If the logical-not of the result is required, perform that now.
14669 Result = DAG.getNOT(dl, Result, VT);
14672 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14675 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14676 getZeroVector(VT, Subtarget, DAG, dl));
14681 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14683 MVT VT = Op.getSimpleValueType();
14685 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14687 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14688 && "SetCC type must be 8-bit or 1-bit integer");
14689 SDValue Op0 = Op.getOperand(0);
14690 SDValue Op1 = Op.getOperand(1);
14692 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14694 // Optimize to BT if possible.
14695 // Lower (X & (1 << N)) == 0 to BT(X, N).
14696 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14697 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14698 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14699 Op1.getOpcode() == ISD::Constant &&
14700 cast<ConstantSDNode>(Op1)->isNullValue() &&
14701 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14702 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14703 if (NewSetCC.getNode())
14707 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14709 if (Op1.getOpcode() == ISD::Constant &&
14710 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14711 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14712 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14714 // If the input is a setcc, then reuse the input setcc or use a new one with
14715 // the inverted condition.
14716 if (Op0.getOpcode() == X86ISD::SETCC) {
14717 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14718 bool Invert = (CC == ISD::SETNE) ^
14719 cast<ConstantSDNode>(Op1)->isNullValue();
14723 CCode = X86::GetOppositeBranchCondition(CCode);
14724 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14725 DAG.getConstant(CCode, MVT::i8),
14726 Op0.getOperand(1));
14728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14732 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14733 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14734 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14736 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14737 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14740 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14741 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14742 if (X86CC == X86::COND_INVALID)
14745 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14746 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14747 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14748 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14750 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14754 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14755 static bool isX86LogicalCmp(SDValue Op) {
14756 unsigned Opc = Op.getNode()->getOpcode();
14757 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14758 Opc == X86ISD::SAHF)
14760 if (Op.getResNo() == 1 &&
14761 (Opc == X86ISD::ADD ||
14762 Opc == X86ISD::SUB ||
14763 Opc == X86ISD::ADC ||
14764 Opc == X86ISD::SBB ||
14765 Opc == X86ISD::SMUL ||
14766 Opc == X86ISD::UMUL ||
14767 Opc == X86ISD::INC ||
14768 Opc == X86ISD::DEC ||
14769 Opc == X86ISD::OR ||
14770 Opc == X86ISD::XOR ||
14771 Opc == X86ISD::AND))
14774 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14780 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14781 if (V.getOpcode() != ISD::TRUNCATE)
14784 SDValue VOp0 = V.getOperand(0);
14785 unsigned InBits = VOp0.getValueSizeInBits();
14786 unsigned Bits = V.getValueSizeInBits();
14787 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14790 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14791 bool addTest = true;
14792 SDValue Cond = Op.getOperand(0);
14793 SDValue Op1 = Op.getOperand(1);
14794 SDValue Op2 = Op.getOperand(2);
14796 EVT VT = Op1.getValueType();
14799 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14800 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14801 // sequence later on.
14802 if (Cond.getOpcode() == ISD::SETCC &&
14803 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14804 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14805 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14806 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14807 int SSECC = translateX86FSETCC(
14808 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14811 if (Subtarget->hasAVX512()) {
14812 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14813 DAG.getConstant(SSECC, MVT::i8));
14814 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14816 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14817 DAG.getConstant(SSECC, MVT::i8));
14818 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14819 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14820 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14824 if (Cond.getOpcode() == ISD::SETCC) {
14825 SDValue NewCond = LowerSETCC(Cond, DAG);
14826 if (NewCond.getNode())
14830 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14831 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14832 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14833 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14834 if (Cond.getOpcode() == X86ISD::SETCC &&
14835 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14836 isZero(Cond.getOperand(1).getOperand(1))) {
14837 SDValue Cmp = Cond.getOperand(1);
14839 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14841 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14842 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14843 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14845 SDValue CmpOp0 = Cmp.getOperand(0);
14846 // Apply further optimizations for special cases
14847 // (select (x != 0), -1, 0) -> neg & sbb
14848 // (select (x == 0), 0, -1) -> neg & sbb
14849 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14850 if (YC->isNullValue() &&
14851 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14852 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14853 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14854 DAG.getConstant(0, CmpOp0.getValueType()),
14856 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14857 DAG.getConstant(X86::COND_B, MVT::i8),
14858 SDValue(Neg.getNode(), 1));
14862 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14863 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14864 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14866 SDValue Res = // Res = 0 or -1.
14867 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14868 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14870 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14871 Res = DAG.getNOT(DL, Res, Res.getValueType());
14873 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14874 if (!N2C || !N2C->isNullValue())
14875 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14880 // Look past (and (setcc_carry (cmp ...)), 1).
14881 if (Cond.getOpcode() == ISD::AND &&
14882 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14883 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14884 if (C && C->getAPIntValue() == 1)
14885 Cond = Cond.getOperand(0);
14888 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14889 // setting operand in place of the X86ISD::SETCC.
14890 unsigned CondOpcode = Cond.getOpcode();
14891 if (CondOpcode == X86ISD::SETCC ||
14892 CondOpcode == X86ISD::SETCC_CARRY) {
14893 CC = Cond.getOperand(0);
14895 SDValue Cmp = Cond.getOperand(1);
14896 unsigned Opc = Cmp.getOpcode();
14897 MVT VT = Op.getSimpleValueType();
14899 bool IllegalFPCMov = false;
14900 if (VT.isFloatingPoint() && !VT.isVector() &&
14901 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14902 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14904 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14905 Opc == X86ISD::BT) { // FIXME
14909 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14910 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14911 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14912 Cond.getOperand(0).getValueType() != MVT::i8)) {
14913 SDValue LHS = Cond.getOperand(0);
14914 SDValue RHS = Cond.getOperand(1);
14915 unsigned X86Opcode;
14918 switch (CondOpcode) {
14919 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14920 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14921 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14922 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14923 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14924 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14925 default: llvm_unreachable("unexpected overflowing operator");
14927 if (CondOpcode == ISD::UMULO)
14928 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14931 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14933 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14935 if (CondOpcode == ISD::UMULO)
14936 Cond = X86Op.getValue(2);
14938 Cond = X86Op.getValue(1);
14940 CC = DAG.getConstant(X86Cond, MVT::i8);
14945 // Look pass the truncate if the high bits are known zero.
14946 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14947 Cond = Cond.getOperand(0);
14949 // We know the result of AND is compared against zero. Try to match
14951 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14952 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14953 if (NewSetCC.getNode()) {
14954 CC = NewSetCC.getOperand(0);
14955 Cond = NewSetCC.getOperand(1);
14962 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14963 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14966 // a < b ? -1 : 0 -> RES = ~setcc_carry
14967 // a < b ? 0 : -1 -> RES = setcc_carry
14968 // a >= b ? -1 : 0 -> RES = setcc_carry
14969 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14970 if (Cond.getOpcode() == X86ISD::SUB) {
14971 Cond = ConvertCmpIfNecessary(Cond, DAG);
14972 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14974 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14975 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14976 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14977 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14978 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14979 return DAG.getNOT(DL, Res, Res.getValueType());
14984 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14985 // widen the cmov and push the truncate through. This avoids introducing a new
14986 // branch during isel and doesn't add any extensions.
14987 if (Op.getValueType() == MVT::i8 &&
14988 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14989 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14990 if (T1.getValueType() == T2.getValueType() &&
14991 // Blacklist CopyFromReg to avoid partial register stalls.
14992 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14993 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14994 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14995 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14999 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15000 // condition is true.
15001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15002 SDValue Ops[] = { Op2, Op1, CC, Cond };
15003 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15006 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
15007 MVT VT = Op->getSimpleValueType(0);
15008 SDValue In = Op->getOperand(0);
15009 MVT InVT = In.getSimpleValueType();
15012 unsigned int NumElts = VT.getVectorNumElements();
15013 if (NumElts != 8 && NumElts != 16)
15016 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15017 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15020 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15022 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15023 Constant *C = ConstantInt::get(*DAG.getContext(),
15024 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15026 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15027 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15028 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15029 MachinePointerInfo::getConstantPool(),
15030 false, false, false, Alignment);
15031 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15032 if (VT.is512BitVector())
15034 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15037 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15038 SelectionDAG &DAG) {
15039 MVT VT = Op->getSimpleValueType(0);
15040 SDValue In = Op->getOperand(0);
15041 MVT InVT = In.getSimpleValueType();
15044 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15045 return LowerSIGN_EXTEND_AVX512(Op, DAG);
15047 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15048 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15049 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15052 if (Subtarget->hasInt256())
15053 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15055 // Optimize vectors in AVX mode
15056 // Sign extend v8i16 to v8i32 and
15059 // Divide input vector into two parts
15060 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15061 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15062 // concat the vectors to original VT
15064 unsigned NumElems = InVT.getVectorNumElements();
15065 SDValue Undef = DAG.getUNDEF(InVT);
15067 SmallVector<int,8> ShufMask1(NumElems, -1);
15068 for (unsigned i = 0; i != NumElems/2; ++i)
15071 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15073 SmallVector<int,8> ShufMask2(NumElems, -1);
15074 for (unsigned i = 0; i != NumElems/2; ++i)
15075 ShufMask2[i] = i + NumElems/2;
15077 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15079 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15080 VT.getVectorNumElements()/2);
15082 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15083 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15085 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15088 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15089 // may emit an illegal shuffle but the expansion is still better than scalar
15090 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15091 // we'll emit a shuffle and a arithmetic shift.
15092 // TODO: It is possible to support ZExt by zeroing the undef values during
15093 // the shuffle phase or after the shuffle.
15094 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15095 SelectionDAG &DAG) {
15096 MVT RegVT = Op.getSimpleValueType();
15097 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15098 assert(RegVT.isInteger() &&
15099 "We only custom lower integer vector sext loads.");
15101 // Nothing useful we can do without SSE2 shuffles.
15102 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15104 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15106 EVT MemVT = Ld->getMemoryVT();
15107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15108 unsigned RegSz = RegVT.getSizeInBits();
15110 ISD::LoadExtType Ext = Ld->getExtensionType();
15112 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15113 && "Only anyext and sext are currently implemented.");
15114 assert(MemVT != RegVT && "Cannot extend to the same type");
15115 assert(MemVT.isVector() && "Must load a vector from memory");
15117 unsigned NumElems = RegVT.getVectorNumElements();
15118 unsigned MemSz = MemVT.getSizeInBits();
15119 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15121 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15122 // The only way in which we have a legal 256-bit vector result but not the
15123 // integer 256-bit operations needed to directly lower a sextload is if we
15124 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15125 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15126 // correctly legalized. We do this late to allow the canonical form of
15127 // sextload to persist throughout the rest of the DAG combiner -- it wants
15128 // to fold together any extensions it can, and so will fuse a sign_extend
15129 // of an sextload into a sextload targeting a wider value.
15131 if (MemSz == 128) {
15132 // Just switch this to a normal load.
15133 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15134 "it must be a legal 128-bit vector "
15136 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15137 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15138 Ld->isInvariant(), Ld->getAlignment());
15140 assert(MemSz < 128 &&
15141 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15142 // Do an sext load to a 128-bit vector type. We want to use the same
15143 // number of elements, but elements half as wide. This will end up being
15144 // recursively lowered by this routine, but will succeed as we definitely
15145 // have all the necessary features if we're using AVX1.
15147 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15148 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15150 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15151 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15152 Ld->isNonTemporal(), Ld->isInvariant(),
15153 Ld->getAlignment());
15156 // Replace chain users with the new chain.
15157 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15158 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15160 // Finally, do a normal sign-extend to the desired register.
15161 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15164 // All sizes must be a power of two.
15165 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15166 "Non-power-of-two elements are not custom lowered!");
15168 // Attempt to load the original value using scalar loads.
15169 // Find the largest scalar type that divides the total loaded size.
15170 MVT SclrLoadTy = MVT::i8;
15171 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15172 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15173 MVT Tp = (MVT::SimpleValueType)tp;
15174 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15179 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15180 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15182 SclrLoadTy = MVT::f64;
15184 // Calculate the number of scalar loads that we need to perform
15185 // in order to load our vector from memory.
15186 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15188 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15189 "Can only lower sext loads with a single scalar load!");
15191 unsigned loadRegZize = RegSz;
15192 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15195 // Represent our vector as a sequence of elements which are the
15196 // largest scalar that we can load.
15197 EVT LoadUnitVecVT = EVT::getVectorVT(
15198 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15200 // Represent the data using the same element type that is stored in
15201 // memory. In practice, we ''widen'' MemVT.
15203 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15204 loadRegZize / MemVT.getScalarType().getSizeInBits());
15206 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15207 "Invalid vector type");
15209 // We can't shuffle using an illegal type.
15210 assert(TLI.isTypeLegal(WideVecVT) &&
15211 "We only lower types that form legal widened vector types");
15213 SmallVector<SDValue, 8> Chains;
15214 SDValue Ptr = Ld->getBasePtr();
15215 SDValue Increment =
15216 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15217 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15219 for (unsigned i = 0; i < NumLoads; ++i) {
15220 // Perform a single load.
15221 SDValue ScalarLoad =
15222 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15223 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15224 Ld->getAlignment());
15225 Chains.push_back(ScalarLoad.getValue(1));
15226 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15227 // another round of DAGCombining.
15229 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15231 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15232 ScalarLoad, DAG.getIntPtrConstant(i));
15234 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15237 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15239 // Bitcast the loaded value to a vector of the original element type, in
15240 // the size of the target vector type.
15241 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15242 unsigned SizeRatio = RegSz / MemSz;
15244 if (Ext == ISD::SEXTLOAD) {
15245 // If we have SSE4.1, we can directly emit a VSEXT node.
15246 if (Subtarget->hasSSE41()) {
15247 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15248 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15252 // Otherwise we'll shuffle the small elements in the high bits of the
15253 // larger type and perform an arithmetic shift. If the shift is not legal
15254 // it's better to scalarize.
15255 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15256 "We can't implement a sext load without an arithmetic right shift!");
15258 // Redistribute the loaded elements into the different locations.
15259 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15260 for (unsigned i = 0; i != NumElems; ++i)
15261 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15263 SDValue Shuff = DAG.getVectorShuffle(
15264 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15266 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15268 // Build the arithmetic shift.
15269 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15270 MemVT.getVectorElementType().getSizeInBits();
15272 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15274 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15278 // Redistribute the loaded elements into the different locations.
15279 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15280 for (unsigned i = 0; i != NumElems; ++i)
15281 ShuffleVec[i * SizeRatio] = i;
15283 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15284 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15286 // Bitcast to the requested type.
15287 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15288 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15292 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15293 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15294 // from the AND / OR.
15295 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15296 Opc = Op.getOpcode();
15297 if (Opc != ISD::OR && Opc != ISD::AND)
15299 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15300 Op.getOperand(0).hasOneUse() &&
15301 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15302 Op.getOperand(1).hasOneUse());
15305 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15306 // 1 and that the SETCC node has a single use.
15307 static bool isXor1OfSetCC(SDValue Op) {
15308 if (Op.getOpcode() != ISD::XOR)
15310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15311 if (N1C && N1C->getAPIntValue() == 1) {
15312 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15313 Op.getOperand(0).hasOneUse();
15318 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15319 bool addTest = true;
15320 SDValue Chain = Op.getOperand(0);
15321 SDValue Cond = Op.getOperand(1);
15322 SDValue Dest = Op.getOperand(2);
15325 bool Inverted = false;
15327 if (Cond.getOpcode() == ISD::SETCC) {
15328 // Check for setcc([su]{add,sub,mul}o == 0).
15329 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15330 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15331 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15332 Cond.getOperand(0).getResNo() == 1 &&
15333 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15334 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15335 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15336 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15337 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15338 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15340 Cond = Cond.getOperand(0);
15342 SDValue NewCond = LowerSETCC(Cond, DAG);
15343 if (NewCond.getNode())
15348 // FIXME: LowerXALUO doesn't handle these!!
15349 else if (Cond.getOpcode() == X86ISD::ADD ||
15350 Cond.getOpcode() == X86ISD::SUB ||
15351 Cond.getOpcode() == X86ISD::SMUL ||
15352 Cond.getOpcode() == X86ISD::UMUL)
15353 Cond = LowerXALUO(Cond, DAG);
15356 // Look pass (and (setcc_carry (cmp ...)), 1).
15357 if (Cond.getOpcode() == ISD::AND &&
15358 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15360 if (C && C->getAPIntValue() == 1)
15361 Cond = Cond.getOperand(0);
15364 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15365 // setting operand in place of the X86ISD::SETCC.
15366 unsigned CondOpcode = Cond.getOpcode();
15367 if (CondOpcode == X86ISD::SETCC ||
15368 CondOpcode == X86ISD::SETCC_CARRY) {
15369 CC = Cond.getOperand(0);
15371 SDValue Cmp = Cond.getOperand(1);
15372 unsigned Opc = Cmp.getOpcode();
15373 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15374 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15378 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15382 // These can only come from an arithmetic instruction with overflow,
15383 // e.g. SADDO, UADDO.
15384 Cond = Cond.getNode()->getOperand(1);
15390 CondOpcode = Cond.getOpcode();
15391 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15392 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15393 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15394 Cond.getOperand(0).getValueType() != MVT::i8)) {
15395 SDValue LHS = Cond.getOperand(0);
15396 SDValue RHS = Cond.getOperand(1);
15397 unsigned X86Opcode;
15400 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15401 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15403 switch (CondOpcode) {
15404 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15408 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15411 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15412 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15414 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15416 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15419 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15420 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15421 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15422 default: llvm_unreachable("unexpected overflowing operator");
15425 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15426 if (CondOpcode == ISD::UMULO)
15427 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15430 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15432 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15434 if (CondOpcode == ISD::UMULO)
15435 Cond = X86Op.getValue(2);
15437 Cond = X86Op.getValue(1);
15439 CC = DAG.getConstant(X86Cond, MVT::i8);
15443 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15444 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15445 if (CondOpc == ISD::OR) {
15446 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15447 // two branches instead of an explicit OR instruction with a
15449 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15450 isX86LogicalCmp(Cmp)) {
15451 CC = Cond.getOperand(0).getOperand(0);
15452 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15453 Chain, Dest, CC, Cmp);
15454 CC = Cond.getOperand(1).getOperand(0);
15458 } else { // ISD::AND
15459 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15460 // two branches instead of an explicit AND instruction with a
15461 // separate test. However, we only do this if this block doesn't
15462 // have a fall-through edge, because this requires an explicit
15463 // jmp when the condition is false.
15464 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15465 isX86LogicalCmp(Cmp) &&
15466 Op.getNode()->hasOneUse()) {
15467 X86::CondCode CCode =
15468 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15469 CCode = X86::GetOppositeBranchCondition(CCode);
15470 CC = DAG.getConstant(CCode, MVT::i8);
15471 SDNode *User = *Op.getNode()->use_begin();
15472 // Look for an unconditional branch following this conditional branch.
15473 // We need this because we need to reverse the successors in order
15474 // to implement FCMP_OEQ.
15475 if (User->getOpcode() == ISD::BR) {
15476 SDValue FalseBB = User->getOperand(1);
15478 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15479 assert(NewBR == User);
15483 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15484 Chain, Dest, CC, Cmp);
15485 X86::CondCode CCode =
15486 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15487 CCode = X86::GetOppositeBranchCondition(CCode);
15488 CC = DAG.getConstant(CCode, MVT::i8);
15494 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15495 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15496 // It should be transformed during dag combiner except when the condition
15497 // is set by a arithmetics with overflow node.
15498 X86::CondCode CCode =
15499 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15500 CCode = X86::GetOppositeBranchCondition(CCode);
15501 CC = DAG.getConstant(CCode, MVT::i8);
15502 Cond = Cond.getOperand(0).getOperand(1);
15504 } else if (Cond.getOpcode() == ISD::SETCC &&
15505 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15506 // For FCMP_OEQ, we can emit
15507 // two branches instead of an explicit AND instruction with a
15508 // separate test. However, we only do this if this block doesn't
15509 // have a fall-through edge, because this requires an explicit
15510 // jmp when the condition is false.
15511 if (Op.getNode()->hasOneUse()) {
15512 SDNode *User = *Op.getNode()->use_begin();
15513 // Look for an unconditional branch following this conditional branch.
15514 // We need this because we need to reverse the successors in order
15515 // to implement FCMP_OEQ.
15516 if (User->getOpcode() == ISD::BR) {
15517 SDValue FalseBB = User->getOperand(1);
15519 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15520 assert(NewBR == User);
15524 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15525 Cond.getOperand(0), Cond.getOperand(1));
15526 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15527 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15528 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15529 Chain, Dest, CC, Cmp);
15530 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15535 } else if (Cond.getOpcode() == ISD::SETCC &&
15536 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15537 // For FCMP_UNE, we can emit
15538 // two branches instead of an explicit AND instruction with a
15539 // separate test. However, we only do this if this block doesn't
15540 // have a fall-through edge, because this requires an explicit
15541 // jmp when the condition is false.
15542 if (Op.getNode()->hasOneUse()) {
15543 SDNode *User = *Op.getNode()->use_begin();
15544 // Look for an unconditional branch following this conditional branch.
15545 // We need this because we need to reverse the successors in order
15546 // to implement FCMP_UNE.
15547 if (User->getOpcode() == ISD::BR) {
15548 SDValue FalseBB = User->getOperand(1);
15550 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15551 assert(NewBR == User);
15554 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15555 Cond.getOperand(0), Cond.getOperand(1));
15556 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15557 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15558 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15559 Chain, Dest, CC, Cmp);
15560 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15570 // Look pass the truncate if the high bits are known zero.
15571 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15572 Cond = Cond.getOperand(0);
15574 // We know the result of AND is compared against zero. Try to match
15576 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15577 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15578 if (NewSetCC.getNode()) {
15579 CC = NewSetCC.getOperand(0);
15580 Cond = NewSetCC.getOperand(1);
15587 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15588 CC = DAG.getConstant(X86Cond, MVT::i8);
15589 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15591 Cond = ConvertCmpIfNecessary(Cond, DAG);
15592 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15593 Chain, Dest, CC, Cond);
15596 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15597 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15598 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15599 // that the guard pages used by the OS virtual memory manager are allocated in
15600 // correct sequence.
15602 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15603 SelectionDAG &DAG) const {
15604 MachineFunction &MF = DAG.getMachineFunction();
15605 bool SplitStack = MF.shouldSplitStack();
15606 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15612 SDNode* Node = Op.getNode();
15614 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15615 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15616 " not tell us which reg is the stack pointer!");
15617 EVT VT = Node->getValueType(0);
15618 SDValue Tmp1 = SDValue(Node, 0);
15619 SDValue Tmp2 = SDValue(Node, 1);
15620 SDValue Tmp3 = Node->getOperand(2);
15621 SDValue Chain = Tmp1.getOperand(0);
15623 // Chain the dynamic stack allocation so that it doesn't modify the stack
15624 // pointer when other instructions are using the stack.
15625 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15628 SDValue Size = Tmp2.getOperand(1);
15629 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15630 Chain = SP.getValue(1);
15631 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15632 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15633 unsigned StackAlign = TFI.getStackAlignment();
15634 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15635 if (Align > StackAlign)
15636 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15637 DAG.getConstant(-(uint64_t)Align, VT));
15638 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15640 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15641 DAG.getIntPtrConstant(0, true), SDValue(),
15644 SDValue Ops[2] = { Tmp1, Tmp2 };
15645 return DAG.getMergeValues(Ops, dl);
15649 SDValue Chain = Op.getOperand(0);
15650 SDValue Size = Op.getOperand(1);
15651 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15652 EVT VT = Op.getNode()->getValueType(0);
15654 bool Is64Bit = Subtarget->is64Bit();
15655 EVT SPTy = getPointerTy();
15658 MachineRegisterInfo &MRI = MF.getRegInfo();
15661 // The 64 bit implementation of segmented stacks needs to clobber both r10
15662 // r11. This makes it impossible to use it along with nested parameters.
15663 const Function *F = MF.getFunction();
15665 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15667 if (I->hasNestAttr())
15668 report_fatal_error("Cannot use segmented stacks with functions that "
15669 "have nested arguments.");
15672 const TargetRegisterClass *AddrRegClass =
15673 getRegClassFor(getPointerTy());
15674 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15675 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15676 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15677 DAG.getRegister(Vreg, SPTy));
15678 SDValue Ops1[2] = { Value, Chain };
15679 return DAG.getMergeValues(Ops1, dl);
15682 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15684 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15685 Flag = Chain.getValue(1);
15686 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15688 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15690 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15691 DAG.getSubtarget().getRegisterInfo());
15692 unsigned SPReg = RegInfo->getStackRegister();
15693 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15694 Chain = SP.getValue(1);
15697 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15698 DAG.getConstant(-(uint64_t)Align, VT));
15699 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15702 SDValue Ops1[2] = { SP, Chain };
15703 return DAG.getMergeValues(Ops1, dl);
15707 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15708 MachineFunction &MF = DAG.getMachineFunction();
15709 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15711 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15714 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15715 // vastart just stores the address of the VarArgsFrameIndex slot into the
15716 // memory location argument.
15717 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15719 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15720 MachinePointerInfo(SV), false, false, 0);
15724 // gp_offset (0 - 6 * 8)
15725 // fp_offset (48 - 48 + 8 * 16)
15726 // overflow_arg_area (point to parameters coming in memory).
15728 SmallVector<SDValue, 8> MemOps;
15729 SDValue FIN = Op.getOperand(1);
15731 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15732 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15734 FIN, MachinePointerInfo(SV), false, false, 0);
15735 MemOps.push_back(Store);
15738 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15739 FIN, DAG.getIntPtrConstant(4));
15740 Store = DAG.getStore(Op.getOperand(0), DL,
15741 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15743 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15744 MemOps.push_back(Store);
15746 // Store ptr to overflow_arg_area
15747 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15748 FIN, DAG.getIntPtrConstant(4));
15749 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15751 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15752 MachinePointerInfo(SV, 8),
15754 MemOps.push_back(Store);
15756 // Store ptr to reg_save_area.
15757 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15758 FIN, DAG.getIntPtrConstant(8));
15759 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15761 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15762 MachinePointerInfo(SV, 16), false, false, 0);
15763 MemOps.push_back(Store);
15764 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15767 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15768 assert(Subtarget->is64Bit() &&
15769 "LowerVAARG only handles 64-bit va_arg!");
15770 assert((Subtarget->isTargetLinux() ||
15771 Subtarget->isTargetDarwin()) &&
15772 "Unhandled target in LowerVAARG");
15773 assert(Op.getNode()->getNumOperands() == 4);
15774 SDValue Chain = Op.getOperand(0);
15775 SDValue SrcPtr = Op.getOperand(1);
15776 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15777 unsigned Align = Op.getConstantOperandVal(3);
15780 EVT ArgVT = Op.getNode()->getValueType(0);
15781 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15782 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15785 // Decide which area this value should be read from.
15786 // TODO: Implement the AMD64 ABI in its entirety. This simple
15787 // selection mechanism works only for the basic types.
15788 if (ArgVT == MVT::f80) {
15789 llvm_unreachable("va_arg for f80 not yet implemented");
15790 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15791 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15792 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15793 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15795 llvm_unreachable("Unhandled argument type in LowerVAARG");
15798 if (ArgMode == 2) {
15799 // Sanity Check: Make sure using fp_offset makes sense.
15800 assert(!DAG.getTarget().Options.UseSoftFloat &&
15801 !(DAG.getMachineFunction()
15802 .getFunction()->getAttributes()
15803 .hasAttribute(AttributeSet::FunctionIndex,
15804 Attribute::NoImplicitFloat)) &&
15805 Subtarget->hasSSE1());
15808 // Insert VAARG_64 node into the DAG
15809 // VAARG_64 returns two values: Variable Argument Address, Chain
15810 SmallVector<SDValue, 11> InstOps;
15811 InstOps.push_back(Chain);
15812 InstOps.push_back(SrcPtr);
15813 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15814 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15815 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15816 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15817 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15818 VTs, InstOps, MVT::i64,
15819 MachinePointerInfo(SV),
15821 /*Volatile=*/false,
15823 /*WriteMem=*/true);
15824 Chain = VAARG.getValue(1);
15826 // Load the next argument and return it
15827 return DAG.getLoad(ArgVT, dl,
15830 MachinePointerInfo(),
15831 false, false, false, 0);
15834 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15835 SelectionDAG &DAG) {
15836 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15837 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15838 SDValue Chain = Op.getOperand(0);
15839 SDValue DstPtr = Op.getOperand(1);
15840 SDValue SrcPtr = Op.getOperand(2);
15841 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15842 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15845 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15846 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15848 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15851 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15852 // amount is a constant. Takes immediate version of shift as input.
15853 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15854 SDValue SrcOp, uint64_t ShiftAmt,
15855 SelectionDAG &DAG) {
15856 MVT ElementType = VT.getVectorElementType();
15858 // Fold this packed shift into its first operand if ShiftAmt is 0.
15862 // Check for ShiftAmt >= element width
15863 if (ShiftAmt >= ElementType.getSizeInBits()) {
15864 if (Opc == X86ISD::VSRAI)
15865 ShiftAmt = ElementType.getSizeInBits() - 1;
15867 return DAG.getConstant(0, VT);
15870 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15871 && "Unknown target vector shift-by-constant node");
15873 // Fold this packed vector shift into a build vector if SrcOp is a
15874 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15875 if (VT == SrcOp.getSimpleValueType() &&
15876 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15877 SmallVector<SDValue, 8> Elts;
15878 unsigned NumElts = SrcOp->getNumOperands();
15879 ConstantSDNode *ND;
15882 default: llvm_unreachable(nullptr);
15883 case X86ISD::VSHLI:
15884 for (unsigned i=0; i!=NumElts; ++i) {
15885 SDValue CurrentOp = SrcOp->getOperand(i);
15886 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15887 Elts.push_back(CurrentOp);
15890 ND = cast<ConstantSDNode>(CurrentOp);
15891 const APInt &C = ND->getAPIntValue();
15892 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15895 case X86ISD::VSRLI:
15896 for (unsigned i=0; i!=NumElts; ++i) {
15897 SDValue CurrentOp = SrcOp->getOperand(i);
15898 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15899 Elts.push_back(CurrentOp);
15902 ND = cast<ConstantSDNode>(CurrentOp);
15903 const APInt &C = ND->getAPIntValue();
15904 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15907 case X86ISD::VSRAI:
15908 for (unsigned i=0; i!=NumElts; ++i) {
15909 SDValue CurrentOp = SrcOp->getOperand(i);
15910 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15911 Elts.push_back(CurrentOp);
15914 ND = cast<ConstantSDNode>(CurrentOp);
15915 const APInt &C = ND->getAPIntValue();
15916 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15921 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15924 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15927 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15928 // may or may not be a constant. Takes immediate version of shift as input.
15929 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15930 SDValue SrcOp, SDValue ShAmt,
15931 SelectionDAG &DAG) {
15932 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15934 // Catch shift-by-constant.
15935 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15936 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15937 CShAmt->getZExtValue(), DAG);
15939 // Change opcode to non-immediate version
15941 default: llvm_unreachable("Unknown target vector shift node");
15942 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15943 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15944 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15947 // Need to build a vector containing shift amount
15948 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15951 ShOps[1] = DAG.getConstant(0, MVT::i32);
15952 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15953 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15955 // The return type has to be a 128-bit type with the same element
15956 // type as the input type.
15957 MVT EltVT = VT.getVectorElementType();
15958 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15960 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15961 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15964 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15965 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15966 /// necessary casting for \p Mask when lowering masking intrinsics.
15967 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15968 SDValue PreservedSrc, SelectionDAG &DAG) {
15969 EVT VT = Op.getValueType();
15970 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15971 MVT::i1, VT.getVectorNumElements());
15972 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15973 Mask.getValueType().getSizeInBits());
15976 assert(MaskVT.isSimple() && "invalid mask type");
15978 if (isAllOnes(Mask))
15981 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15982 // are extracted by EXTRACT_SUBVECTOR.
15983 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15984 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15985 DAG.getIntPtrConstant(0));
15987 switch (Op.getOpcode()) {
15989 case X86ISD::PCMPEQM:
15990 case X86ISD::PCMPGTM:
15992 case X86ISD::CMPMU:
15993 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15996 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15999 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16001 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16002 case Intrinsic::x86_fma_vfmadd_ps:
16003 case Intrinsic::x86_fma_vfmadd_pd:
16004 case Intrinsic::x86_fma_vfmadd_ps_256:
16005 case Intrinsic::x86_fma_vfmadd_pd_256:
16006 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16007 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16008 return X86ISD::FMADD;
16009 case Intrinsic::x86_fma_vfmsub_ps:
16010 case Intrinsic::x86_fma_vfmsub_pd:
16011 case Intrinsic::x86_fma_vfmsub_ps_256:
16012 case Intrinsic::x86_fma_vfmsub_pd_256:
16013 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16014 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16015 return X86ISD::FMSUB;
16016 case Intrinsic::x86_fma_vfnmadd_ps:
16017 case Intrinsic::x86_fma_vfnmadd_pd:
16018 case Intrinsic::x86_fma_vfnmadd_ps_256:
16019 case Intrinsic::x86_fma_vfnmadd_pd_256:
16020 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16021 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16022 return X86ISD::FNMADD;
16023 case Intrinsic::x86_fma_vfnmsub_ps:
16024 case Intrinsic::x86_fma_vfnmsub_pd:
16025 case Intrinsic::x86_fma_vfnmsub_ps_256:
16026 case Intrinsic::x86_fma_vfnmsub_pd_256:
16027 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16028 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16029 return X86ISD::FNMSUB;
16030 case Intrinsic::x86_fma_vfmaddsub_ps:
16031 case Intrinsic::x86_fma_vfmaddsub_pd:
16032 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16033 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16034 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16035 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16036 return X86ISD::FMADDSUB;
16037 case Intrinsic::x86_fma_vfmsubadd_ps:
16038 case Intrinsic::x86_fma_vfmsubadd_pd:
16039 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16040 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16041 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16042 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16043 return X86ISD::FMSUBADD;
16047 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16049 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16051 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16053 switch(IntrData->Type) {
16054 case INTR_TYPE_1OP:
16055 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16056 case INTR_TYPE_2OP:
16057 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16059 case INTR_TYPE_3OP:
16060 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16061 Op.getOperand(2), Op.getOperand(3));
16063 // Comparison intrinsics with masks.
16064 // Example of transformation:
16065 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16066 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16068 // (v8i1 (insert_subvector undef,
16069 // (v2i1 (and (PCMPEQM %a, %b),
16070 // (extract_subvector
16071 // (v8i1 (bitcast %mask)), 0))), 0))))
16072 EVT VT = Op.getOperand(1).getValueType();
16073 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16074 VT.getVectorNumElements());
16075 SDValue Mask = Op.getOperand(3);
16076 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16077 Mask.getValueType().getSizeInBits());
16078 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16079 Op.getOperand(1), Op.getOperand(2));
16080 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
16081 DAG.getTargetConstant(0, MaskVT), DAG);
16082 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16083 DAG.getUNDEF(BitcastVT), CmpMask,
16084 DAG.getIntPtrConstant(0));
16085 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16087 case COMI: { // Comparison intrinsics
16088 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16089 SDValue LHS = Op.getOperand(1);
16090 SDValue RHS = Op.getOperand(2);
16091 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16092 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16093 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16094 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16095 DAG.getConstant(X86CC, MVT::i8), Cond);
16096 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16099 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16100 Op.getOperand(1), Op.getOperand(2), DAG);
16107 default: return SDValue(); // Don't custom lower most intrinsics.
16109 // Arithmetic intrinsics.
16110 case Intrinsic::x86_sse2_pmulu_dq:
16111 case Intrinsic::x86_avx2_pmulu_dq:
16112 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16113 Op.getOperand(1), Op.getOperand(2));
16115 case Intrinsic::x86_sse41_pmuldq:
16116 case Intrinsic::x86_avx2_pmul_dq:
16117 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16118 Op.getOperand(1), Op.getOperand(2));
16120 case Intrinsic::x86_sse2_pmulhu_w:
16121 case Intrinsic::x86_avx2_pmulhu_w:
16122 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16123 Op.getOperand(1), Op.getOperand(2));
16125 case Intrinsic::x86_sse2_pmulh_w:
16126 case Intrinsic::x86_avx2_pmulh_w:
16127 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16128 Op.getOperand(1), Op.getOperand(2));
16130 // SSE/SSE2/AVX floating point max/min intrinsics.
16131 case Intrinsic::x86_sse_max_ps:
16132 case Intrinsic::x86_sse2_max_pd:
16133 case Intrinsic::x86_avx_max_ps_256:
16134 case Intrinsic::x86_avx_max_pd_256:
16135 case Intrinsic::x86_sse_min_ps:
16136 case Intrinsic::x86_sse2_min_pd:
16137 case Intrinsic::x86_avx_min_ps_256:
16138 case Intrinsic::x86_avx_min_pd_256: {
16141 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16142 case Intrinsic::x86_sse_max_ps:
16143 case Intrinsic::x86_sse2_max_pd:
16144 case Intrinsic::x86_avx_max_ps_256:
16145 case Intrinsic::x86_avx_max_pd_256:
16146 Opcode = X86ISD::FMAX;
16148 case Intrinsic::x86_sse_min_ps:
16149 case Intrinsic::x86_sse2_min_pd:
16150 case Intrinsic::x86_avx_min_ps_256:
16151 case Intrinsic::x86_avx_min_pd_256:
16152 Opcode = X86ISD::FMIN;
16155 return DAG.getNode(Opcode, dl, Op.getValueType(),
16156 Op.getOperand(1), Op.getOperand(2));
16159 // AVX2 variable shift intrinsics
16160 case Intrinsic::x86_avx2_psllv_d:
16161 case Intrinsic::x86_avx2_psllv_q:
16162 case Intrinsic::x86_avx2_psllv_d_256:
16163 case Intrinsic::x86_avx2_psllv_q_256:
16164 case Intrinsic::x86_avx2_psrlv_d:
16165 case Intrinsic::x86_avx2_psrlv_q:
16166 case Intrinsic::x86_avx2_psrlv_d_256:
16167 case Intrinsic::x86_avx2_psrlv_q_256:
16168 case Intrinsic::x86_avx2_psrav_d:
16169 case Intrinsic::x86_avx2_psrav_d_256: {
16172 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16173 case Intrinsic::x86_avx2_psllv_d:
16174 case Intrinsic::x86_avx2_psllv_q:
16175 case Intrinsic::x86_avx2_psllv_d_256:
16176 case Intrinsic::x86_avx2_psllv_q_256:
16179 case Intrinsic::x86_avx2_psrlv_d:
16180 case Intrinsic::x86_avx2_psrlv_q:
16181 case Intrinsic::x86_avx2_psrlv_d_256:
16182 case Intrinsic::x86_avx2_psrlv_q_256:
16185 case Intrinsic::x86_avx2_psrav_d:
16186 case Intrinsic::x86_avx2_psrav_d_256:
16190 return DAG.getNode(Opcode, dl, Op.getValueType(),
16191 Op.getOperand(1), Op.getOperand(2));
16194 case Intrinsic::x86_sse2_packssdw_128:
16195 case Intrinsic::x86_sse2_packsswb_128:
16196 case Intrinsic::x86_avx2_packssdw:
16197 case Intrinsic::x86_avx2_packsswb:
16198 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16199 Op.getOperand(1), Op.getOperand(2));
16201 case Intrinsic::x86_sse2_packuswb_128:
16202 case Intrinsic::x86_sse41_packusdw:
16203 case Intrinsic::x86_avx2_packuswb:
16204 case Intrinsic::x86_avx2_packusdw:
16205 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16206 Op.getOperand(1), Op.getOperand(2));
16208 case Intrinsic::x86_ssse3_pshuf_b_128:
16209 case Intrinsic::x86_avx2_pshuf_b:
16210 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16211 Op.getOperand(1), Op.getOperand(2));
16213 case Intrinsic::x86_sse2_pshuf_d:
16214 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16215 Op.getOperand(1), Op.getOperand(2));
16217 case Intrinsic::x86_sse2_pshufl_w:
16218 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16219 Op.getOperand(1), Op.getOperand(2));
16221 case Intrinsic::x86_sse2_pshufh_w:
16222 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16223 Op.getOperand(1), Op.getOperand(2));
16225 case Intrinsic::x86_ssse3_psign_b_128:
16226 case Intrinsic::x86_ssse3_psign_w_128:
16227 case Intrinsic::x86_ssse3_psign_d_128:
16228 case Intrinsic::x86_avx2_psign_b:
16229 case Intrinsic::x86_avx2_psign_w:
16230 case Intrinsic::x86_avx2_psign_d:
16231 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16232 Op.getOperand(1), Op.getOperand(2));
16234 case Intrinsic::x86_avx2_permd:
16235 case Intrinsic::x86_avx2_permps:
16236 // Operands intentionally swapped. Mask is last operand to intrinsic,
16237 // but second operand for node/instruction.
16238 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16239 Op.getOperand(2), Op.getOperand(1));
16241 case Intrinsic::x86_avx512_mask_valign_q_512:
16242 case Intrinsic::x86_avx512_mask_valign_d_512:
16243 // Vector source operands are swapped.
16244 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16245 Op.getValueType(), Op.getOperand(2),
16248 Op.getOperand(5), Op.getOperand(4), DAG);
16250 // ptest and testp intrinsics. The intrinsic these come from are designed to
16251 // return an integer value, not just an instruction so lower it to the ptest
16252 // or testp pattern and a setcc for the result.
16253 case Intrinsic::x86_sse41_ptestz:
16254 case Intrinsic::x86_sse41_ptestc:
16255 case Intrinsic::x86_sse41_ptestnzc:
16256 case Intrinsic::x86_avx_ptestz_256:
16257 case Intrinsic::x86_avx_ptestc_256:
16258 case Intrinsic::x86_avx_ptestnzc_256:
16259 case Intrinsic::x86_avx_vtestz_ps:
16260 case Intrinsic::x86_avx_vtestc_ps:
16261 case Intrinsic::x86_avx_vtestnzc_ps:
16262 case Intrinsic::x86_avx_vtestz_pd:
16263 case Intrinsic::x86_avx_vtestc_pd:
16264 case Intrinsic::x86_avx_vtestnzc_pd:
16265 case Intrinsic::x86_avx_vtestz_ps_256:
16266 case Intrinsic::x86_avx_vtestc_ps_256:
16267 case Intrinsic::x86_avx_vtestnzc_ps_256:
16268 case Intrinsic::x86_avx_vtestz_pd_256:
16269 case Intrinsic::x86_avx_vtestc_pd_256:
16270 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16271 bool IsTestPacked = false;
16274 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16275 case Intrinsic::x86_avx_vtestz_ps:
16276 case Intrinsic::x86_avx_vtestz_pd:
16277 case Intrinsic::x86_avx_vtestz_ps_256:
16278 case Intrinsic::x86_avx_vtestz_pd_256:
16279 IsTestPacked = true; // Fallthrough
16280 case Intrinsic::x86_sse41_ptestz:
16281 case Intrinsic::x86_avx_ptestz_256:
16283 X86CC = X86::COND_E;
16285 case Intrinsic::x86_avx_vtestc_ps:
16286 case Intrinsic::x86_avx_vtestc_pd:
16287 case Intrinsic::x86_avx_vtestc_ps_256:
16288 case Intrinsic::x86_avx_vtestc_pd_256:
16289 IsTestPacked = true; // Fallthrough
16290 case Intrinsic::x86_sse41_ptestc:
16291 case Intrinsic::x86_avx_ptestc_256:
16293 X86CC = X86::COND_B;
16295 case Intrinsic::x86_avx_vtestnzc_ps:
16296 case Intrinsic::x86_avx_vtestnzc_pd:
16297 case Intrinsic::x86_avx_vtestnzc_ps_256:
16298 case Intrinsic::x86_avx_vtestnzc_pd_256:
16299 IsTestPacked = true; // Fallthrough
16300 case Intrinsic::x86_sse41_ptestnzc:
16301 case Intrinsic::x86_avx_ptestnzc_256:
16303 X86CC = X86::COND_A;
16307 SDValue LHS = Op.getOperand(1);
16308 SDValue RHS = Op.getOperand(2);
16309 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16310 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16311 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16312 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16313 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16315 case Intrinsic::x86_avx512_kortestz_w:
16316 case Intrinsic::x86_avx512_kortestc_w: {
16317 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16318 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16319 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16320 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16321 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16322 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16323 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16326 case Intrinsic::x86_sse42_pcmpistria128:
16327 case Intrinsic::x86_sse42_pcmpestria128:
16328 case Intrinsic::x86_sse42_pcmpistric128:
16329 case Intrinsic::x86_sse42_pcmpestric128:
16330 case Intrinsic::x86_sse42_pcmpistrio128:
16331 case Intrinsic::x86_sse42_pcmpestrio128:
16332 case Intrinsic::x86_sse42_pcmpistris128:
16333 case Intrinsic::x86_sse42_pcmpestris128:
16334 case Intrinsic::x86_sse42_pcmpistriz128:
16335 case Intrinsic::x86_sse42_pcmpestriz128: {
16339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16340 case Intrinsic::x86_sse42_pcmpistria128:
16341 Opcode = X86ISD::PCMPISTRI;
16342 X86CC = X86::COND_A;
16344 case Intrinsic::x86_sse42_pcmpestria128:
16345 Opcode = X86ISD::PCMPESTRI;
16346 X86CC = X86::COND_A;
16348 case Intrinsic::x86_sse42_pcmpistric128:
16349 Opcode = X86ISD::PCMPISTRI;
16350 X86CC = X86::COND_B;
16352 case Intrinsic::x86_sse42_pcmpestric128:
16353 Opcode = X86ISD::PCMPESTRI;
16354 X86CC = X86::COND_B;
16356 case Intrinsic::x86_sse42_pcmpistrio128:
16357 Opcode = X86ISD::PCMPISTRI;
16358 X86CC = X86::COND_O;
16360 case Intrinsic::x86_sse42_pcmpestrio128:
16361 Opcode = X86ISD::PCMPESTRI;
16362 X86CC = X86::COND_O;
16364 case Intrinsic::x86_sse42_pcmpistris128:
16365 Opcode = X86ISD::PCMPISTRI;
16366 X86CC = X86::COND_S;
16368 case Intrinsic::x86_sse42_pcmpestris128:
16369 Opcode = X86ISD::PCMPESTRI;
16370 X86CC = X86::COND_S;
16372 case Intrinsic::x86_sse42_pcmpistriz128:
16373 Opcode = X86ISD::PCMPISTRI;
16374 X86CC = X86::COND_E;
16376 case Intrinsic::x86_sse42_pcmpestriz128:
16377 Opcode = X86ISD::PCMPESTRI;
16378 X86CC = X86::COND_E;
16381 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16382 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16383 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16384 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16385 DAG.getConstant(X86CC, MVT::i8),
16386 SDValue(PCMP.getNode(), 1));
16387 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16390 case Intrinsic::x86_sse42_pcmpistri128:
16391 case Intrinsic::x86_sse42_pcmpestri128: {
16393 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16394 Opcode = X86ISD::PCMPISTRI;
16396 Opcode = X86ISD::PCMPESTRI;
16398 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16399 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16400 return DAG.getNode(Opcode, dl, VTs, NewOps);
16403 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16404 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16405 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16406 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16407 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16408 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16409 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16410 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16411 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16412 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16413 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16414 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16415 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16416 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16417 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16418 dl, Op.getValueType(),
16422 Op.getOperand(4), Op.getOperand(1), DAG);
16427 case Intrinsic::x86_fma_vfmadd_ps:
16428 case Intrinsic::x86_fma_vfmadd_pd:
16429 case Intrinsic::x86_fma_vfmsub_ps:
16430 case Intrinsic::x86_fma_vfmsub_pd:
16431 case Intrinsic::x86_fma_vfnmadd_ps:
16432 case Intrinsic::x86_fma_vfnmadd_pd:
16433 case Intrinsic::x86_fma_vfnmsub_ps:
16434 case Intrinsic::x86_fma_vfnmsub_pd:
16435 case Intrinsic::x86_fma_vfmaddsub_ps:
16436 case Intrinsic::x86_fma_vfmaddsub_pd:
16437 case Intrinsic::x86_fma_vfmsubadd_ps:
16438 case Intrinsic::x86_fma_vfmsubadd_pd:
16439 case Intrinsic::x86_fma_vfmadd_ps_256:
16440 case Intrinsic::x86_fma_vfmadd_pd_256:
16441 case Intrinsic::x86_fma_vfmsub_ps_256:
16442 case Intrinsic::x86_fma_vfmsub_pd_256:
16443 case Intrinsic::x86_fma_vfnmadd_ps_256:
16444 case Intrinsic::x86_fma_vfnmadd_pd_256:
16445 case Intrinsic::x86_fma_vfnmsub_ps_256:
16446 case Intrinsic::x86_fma_vfnmsub_pd_256:
16447 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16448 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16449 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16450 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16451 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16452 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16456 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16457 SDValue Src, SDValue Mask, SDValue Base,
16458 SDValue Index, SDValue ScaleOp, SDValue Chain,
16459 const X86Subtarget * Subtarget) {
16461 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16462 assert(C && "Invalid scale type");
16463 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16464 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16465 Index.getSimpleValueType().getVectorNumElements());
16467 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16469 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16471 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16472 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16473 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16474 SDValue Segment = DAG.getRegister(0, MVT::i32);
16475 if (Src.getOpcode() == ISD::UNDEF)
16476 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16477 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16478 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16479 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16480 return DAG.getMergeValues(RetOps, dl);
16483 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16484 SDValue Src, SDValue Mask, SDValue Base,
16485 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16487 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16488 assert(C && "Invalid scale type");
16489 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16490 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16491 SDValue Segment = DAG.getRegister(0, MVT::i32);
16492 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16493 Index.getSimpleValueType().getVectorNumElements());
16495 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16497 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16499 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16500 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16501 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16502 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16503 return SDValue(Res, 1);
16506 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16507 SDValue Mask, SDValue Base, SDValue Index,
16508 SDValue ScaleOp, SDValue Chain) {
16510 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16511 assert(C && "Invalid scale type");
16512 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16513 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16514 SDValue Segment = DAG.getRegister(0, MVT::i32);
16516 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16518 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16520 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16522 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16523 //SDVTList VTs = DAG.getVTList(MVT::Other);
16524 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16525 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16526 return SDValue(Res, 0);
16529 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16530 // read performance monitor counters (x86_rdpmc).
16531 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16532 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16533 SmallVectorImpl<SDValue> &Results) {
16534 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16538 // The ECX register is used to select the index of the performance counter
16540 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16542 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16544 // Reads the content of a 64-bit performance counter and returns it in the
16545 // registers EDX:EAX.
16546 if (Subtarget->is64Bit()) {
16547 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16548 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16551 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16552 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16555 Chain = HI.getValue(1);
16557 if (Subtarget->is64Bit()) {
16558 // The EAX register is loaded with the low-order 32 bits. The EDX register
16559 // is loaded with the supported high-order bits of the counter.
16560 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16561 DAG.getConstant(32, MVT::i8));
16562 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16563 Results.push_back(Chain);
16567 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16568 SDValue Ops[] = { LO, HI };
16569 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16570 Results.push_back(Pair);
16571 Results.push_back(Chain);
16574 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16575 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16576 // also used to custom lower READCYCLECOUNTER nodes.
16577 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16578 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16579 SmallVectorImpl<SDValue> &Results) {
16580 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16581 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16584 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16585 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16586 // and the EAX register is loaded with the low-order 32 bits.
16587 if (Subtarget->is64Bit()) {
16588 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16589 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16592 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16593 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16596 SDValue Chain = HI.getValue(1);
16598 if (Opcode == X86ISD::RDTSCP_DAG) {
16599 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16601 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16602 // the ECX register. Add 'ecx' explicitly to the chain.
16603 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16605 // Explicitly store the content of ECX at the location passed in input
16606 // to the 'rdtscp' intrinsic.
16607 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16608 MachinePointerInfo(), false, false, 0);
16611 if (Subtarget->is64Bit()) {
16612 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16613 // the EAX register is loaded with the low-order 32 bits.
16614 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16615 DAG.getConstant(32, MVT::i8));
16616 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16617 Results.push_back(Chain);
16621 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16622 SDValue Ops[] = { LO, HI };
16623 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16624 Results.push_back(Pair);
16625 Results.push_back(Chain);
16628 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16629 SelectionDAG &DAG) {
16630 SmallVector<SDValue, 2> Results;
16632 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16634 return DAG.getMergeValues(Results, DL);
16638 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16639 SelectionDAG &DAG) {
16640 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16642 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16647 switch(IntrData->Type) {
16649 llvm_unreachable("Unknown Intrinsic Type");
16653 // Emit the node with the right value type.
16654 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16655 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16657 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16658 // Otherwise return the value from Rand, which is always 0, casted to i32.
16659 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16660 DAG.getConstant(1, Op->getValueType(1)),
16661 DAG.getConstant(X86::COND_B, MVT::i32),
16662 SDValue(Result.getNode(), 1) };
16663 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16664 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16667 // Return { result, isValid, chain }.
16668 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16669 SDValue(Result.getNode(), 2));
16672 //gather(v1, mask, index, base, scale);
16673 SDValue Chain = Op.getOperand(0);
16674 SDValue Src = Op.getOperand(2);
16675 SDValue Base = Op.getOperand(3);
16676 SDValue Index = Op.getOperand(4);
16677 SDValue Mask = Op.getOperand(5);
16678 SDValue Scale = Op.getOperand(6);
16679 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16683 //scatter(base, mask, index, v1, scale);
16684 SDValue Chain = Op.getOperand(0);
16685 SDValue Base = Op.getOperand(2);
16686 SDValue Mask = Op.getOperand(3);
16687 SDValue Index = Op.getOperand(4);
16688 SDValue Src = Op.getOperand(5);
16689 SDValue Scale = Op.getOperand(6);
16690 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16693 SDValue Hint = Op.getOperand(6);
16695 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16696 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16697 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16698 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16699 SDValue Chain = Op.getOperand(0);
16700 SDValue Mask = Op.getOperand(2);
16701 SDValue Index = Op.getOperand(3);
16702 SDValue Base = Op.getOperand(4);
16703 SDValue Scale = Op.getOperand(5);
16704 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16706 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16708 SmallVector<SDValue, 2> Results;
16709 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16710 return DAG.getMergeValues(Results, dl);
16712 // Read Performance Monitoring Counters.
16714 SmallVector<SDValue, 2> Results;
16715 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16716 return DAG.getMergeValues(Results, dl);
16718 // XTEST intrinsics.
16720 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16721 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16722 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16723 DAG.getConstant(X86::COND_NE, MVT::i8),
16725 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16726 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16727 Ret, SDValue(InTrans.getNode(), 1));
16731 SmallVector<SDValue, 2> Results;
16732 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16733 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16734 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16735 DAG.getConstant(-1, MVT::i8));
16736 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16737 Op.getOperand(4), GenCF.getValue(1));
16738 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16739 Op.getOperand(5), MachinePointerInfo(),
16741 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16742 DAG.getConstant(X86::COND_B, MVT::i8),
16744 Results.push_back(SetCC);
16745 Results.push_back(Store);
16746 return DAG.getMergeValues(Results, dl);
16751 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16752 SelectionDAG &DAG) const {
16753 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16754 MFI->setReturnAddressIsTaken(true);
16756 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16759 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16761 EVT PtrVT = getPointerTy();
16764 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16765 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16766 DAG.getSubtarget().getRegisterInfo());
16767 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16768 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16769 DAG.getNode(ISD::ADD, dl, PtrVT,
16770 FrameAddr, Offset),
16771 MachinePointerInfo(), false, false, false, 0);
16774 // Just load the return address.
16775 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16776 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16777 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16780 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16781 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16782 MFI->setFrameAddressIsTaken(true);
16784 EVT VT = Op.getValueType();
16785 SDLoc dl(Op); // FIXME probably not meaningful
16786 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16787 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16788 DAG.getSubtarget().getRegisterInfo());
16789 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16790 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16791 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16792 "Invalid Frame Register!");
16793 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16795 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16796 MachinePointerInfo(),
16797 false, false, false, 0);
16801 // FIXME? Maybe this could be a TableGen attribute on some registers and
16802 // this table could be generated automatically from RegInfo.
16803 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16805 unsigned Reg = StringSwitch<unsigned>(RegName)
16806 .Case("esp", X86::ESP)
16807 .Case("rsp", X86::RSP)
16811 report_fatal_error("Invalid register name global variable");
16814 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16815 SelectionDAG &DAG) const {
16816 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16817 DAG.getSubtarget().getRegisterInfo());
16818 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16821 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16822 SDValue Chain = Op.getOperand(0);
16823 SDValue Offset = Op.getOperand(1);
16824 SDValue Handler = Op.getOperand(2);
16827 EVT PtrVT = getPointerTy();
16828 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16829 DAG.getSubtarget().getRegisterInfo());
16830 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16831 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16832 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16833 "Invalid Frame Register!");
16834 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16835 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16837 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16838 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16839 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16840 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16842 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16844 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16845 DAG.getRegister(StoreAddrReg, PtrVT));
16848 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16849 SelectionDAG &DAG) const {
16851 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16852 DAG.getVTList(MVT::i32, MVT::Other),
16853 Op.getOperand(0), Op.getOperand(1));
16856 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16857 SelectionDAG &DAG) const {
16859 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16860 Op.getOperand(0), Op.getOperand(1));
16863 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16864 return Op.getOperand(0);
16867 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16868 SelectionDAG &DAG) const {
16869 SDValue Root = Op.getOperand(0);
16870 SDValue Trmp = Op.getOperand(1); // trampoline
16871 SDValue FPtr = Op.getOperand(2); // nested function
16872 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16875 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16876 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16878 if (Subtarget->is64Bit()) {
16879 SDValue OutChains[6];
16881 // Large code-model.
16882 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16883 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16885 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16886 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16888 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16890 // Load the pointer to the nested function into R11.
16891 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16892 SDValue Addr = Trmp;
16893 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16894 Addr, MachinePointerInfo(TrmpAddr),
16897 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16898 DAG.getConstant(2, MVT::i64));
16899 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16900 MachinePointerInfo(TrmpAddr, 2),
16903 // Load the 'nest' parameter value into R10.
16904 // R10 is specified in X86CallingConv.td
16905 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16906 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16907 DAG.getConstant(10, MVT::i64));
16908 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16909 Addr, MachinePointerInfo(TrmpAddr, 10),
16912 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16913 DAG.getConstant(12, MVT::i64));
16914 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16915 MachinePointerInfo(TrmpAddr, 12),
16918 // Jump to the nested function.
16919 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16920 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16921 DAG.getConstant(20, MVT::i64));
16922 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16923 Addr, MachinePointerInfo(TrmpAddr, 20),
16926 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16927 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16928 DAG.getConstant(22, MVT::i64));
16929 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16930 MachinePointerInfo(TrmpAddr, 22),
16933 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16935 const Function *Func =
16936 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16937 CallingConv::ID CC = Func->getCallingConv();
16942 llvm_unreachable("Unsupported calling convention");
16943 case CallingConv::C:
16944 case CallingConv::X86_StdCall: {
16945 // Pass 'nest' parameter in ECX.
16946 // Must be kept in sync with X86CallingConv.td
16947 NestReg = X86::ECX;
16949 // Check that ECX wasn't needed by an 'inreg' parameter.
16950 FunctionType *FTy = Func->getFunctionType();
16951 const AttributeSet &Attrs = Func->getAttributes();
16953 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16954 unsigned InRegCount = 0;
16957 for (FunctionType::param_iterator I = FTy->param_begin(),
16958 E = FTy->param_end(); I != E; ++I, ++Idx)
16959 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16960 // FIXME: should only count parameters that are lowered to integers.
16961 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16963 if (InRegCount > 2) {
16964 report_fatal_error("Nest register in use - reduce number of inreg"
16970 case CallingConv::X86_FastCall:
16971 case CallingConv::X86_ThisCall:
16972 case CallingConv::Fast:
16973 // Pass 'nest' parameter in EAX.
16974 // Must be kept in sync with X86CallingConv.td
16975 NestReg = X86::EAX;
16979 SDValue OutChains[4];
16980 SDValue Addr, Disp;
16982 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16983 DAG.getConstant(10, MVT::i32));
16984 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16986 // This is storing the opcode for MOV32ri.
16987 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16988 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16989 OutChains[0] = DAG.getStore(Root, dl,
16990 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16991 Trmp, MachinePointerInfo(TrmpAddr),
16994 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16995 DAG.getConstant(1, MVT::i32));
16996 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16997 MachinePointerInfo(TrmpAddr, 1),
17000 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17001 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17002 DAG.getConstant(5, MVT::i32));
17003 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17004 MachinePointerInfo(TrmpAddr, 5),
17007 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17008 DAG.getConstant(6, MVT::i32));
17009 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17010 MachinePointerInfo(TrmpAddr, 6),
17013 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17017 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17018 SelectionDAG &DAG) const {
17020 The rounding mode is in bits 11:10 of FPSR, and has the following
17022 00 Round to nearest
17027 FLT_ROUNDS, on the other hand, expects the following:
17034 To perform the conversion, we do:
17035 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17038 MachineFunction &MF = DAG.getMachineFunction();
17039 const TargetMachine &TM = MF.getTarget();
17040 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17041 unsigned StackAlignment = TFI.getStackAlignment();
17042 MVT VT = Op.getSimpleValueType();
17045 // Save FP Control Word to stack slot
17046 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17047 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17049 MachineMemOperand *MMO =
17050 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17051 MachineMemOperand::MOStore, 2, 2);
17053 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17054 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17055 DAG.getVTList(MVT::Other),
17056 Ops, MVT::i16, MMO);
17058 // Load FP Control Word from stack slot
17059 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17060 MachinePointerInfo(), false, false, false, 0);
17062 // Transform as necessary
17064 DAG.getNode(ISD::SRL, DL, MVT::i16,
17065 DAG.getNode(ISD::AND, DL, MVT::i16,
17066 CWD, DAG.getConstant(0x800, MVT::i16)),
17067 DAG.getConstant(11, MVT::i8));
17069 DAG.getNode(ISD::SRL, DL, MVT::i16,
17070 DAG.getNode(ISD::AND, DL, MVT::i16,
17071 CWD, DAG.getConstant(0x400, MVT::i16)),
17072 DAG.getConstant(9, MVT::i8));
17075 DAG.getNode(ISD::AND, DL, MVT::i16,
17076 DAG.getNode(ISD::ADD, DL, MVT::i16,
17077 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17078 DAG.getConstant(1, MVT::i16)),
17079 DAG.getConstant(3, MVT::i16));
17081 return DAG.getNode((VT.getSizeInBits() < 16 ?
17082 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17085 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17086 MVT VT = Op.getSimpleValueType();
17088 unsigned NumBits = VT.getSizeInBits();
17091 Op = Op.getOperand(0);
17092 if (VT == MVT::i8) {
17093 // Zero extend to i32 since there is not an i8 bsr.
17095 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17098 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17099 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17100 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17102 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17105 DAG.getConstant(NumBits+NumBits-1, OpVT),
17106 DAG.getConstant(X86::COND_E, MVT::i8),
17109 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17111 // Finally xor with NumBits-1.
17112 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17115 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17119 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17120 MVT VT = Op.getSimpleValueType();
17122 unsigned NumBits = VT.getSizeInBits();
17125 Op = Op.getOperand(0);
17126 if (VT == MVT::i8) {
17127 // Zero extend to i32 since there is not an i8 bsr.
17129 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17132 // Issue a bsr (scan bits in reverse).
17133 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17134 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17136 // And xor with NumBits-1.
17137 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17140 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17144 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17145 MVT VT = Op.getSimpleValueType();
17146 unsigned NumBits = VT.getSizeInBits();
17148 Op = Op.getOperand(0);
17150 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17151 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17152 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17154 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17157 DAG.getConstant(NumBits, VT),
17158 DAG.getConstant(X86::COND_E, MVT::i8),
17161 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17164 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17165 // ones, and then concatenate the result back.
17166 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17167 MVT VT = Op.getSimpleValueType();
17169 assert(VT.is256BitVector() && VT.isInteger() &&
17170 "Unsupported value type for operation");
17172 unsigned NumElems = VT.getVectorNumElements();
17175 // Extract the LHS vectors
17176 SDValue LHS = Op.getOperand(0);
17177 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17178 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17180 // Extract the RHS vectors
17181 SDValue RHS = Op.getOperand(1);
17182 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17183 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17185 MVT EltVT = VT.getVectorElementType();
17186 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17188 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17189 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17190 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17193 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17194 assert(Op.getSimpleValueType().is256BitVector() &&
17195 Op.getSimpleValueType().isInteger() &&
17196 "Only handle AVX 256-bit vector integer operation");
17197 return Lower256IntArith(Op, DAG);
17200 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17201 assert(Op.getSimpleValueType().is256BitVector() &&
17202 Op.getSimpleValueType().isInteger() &&
17203 "Only handle AVX 256-bit vector integer operation");
17204 return Lower256IntArith(Op, DAG);
17207 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17208 SelectionDAG &DAG) {
17210 MVT VT = Op.getSimpleValueType();
17212 // Decompose 256-bit ops into smaller 128-bit ops.
17213 if (VT.is256BitVector() && !Subtarget->hasInt256())
17214 return Lower256IntArith(Op, DAG);
17216 SDValue A = Op.getOperand(0);
17217 SDValue B = Op.getOperand(1);
17219 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17220 if (VT == MVT::v4i32) {
17221 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17222 "Should not custom lower when pmuldq is available!");
17224 // Extract the odd parts.
17225 static const int UnpackMask[] = { 1, -1, 3, -1 };
17226 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17227 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17229 // Multiply the even parts.
17230 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17231 // Now multiply odd parts.
17232 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17234 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17235 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17237 // Merge the two vectors back together with a shuffle. This expands into 2
17239 static const int ShufMask[] = { 0, 4, 2, 6 };
17240 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17243 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17244 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17246 // Ahi = psrlqi(a, 32);
17247 // Bhi = psrlqi(b, 32);
17249 // AloBlo = pmuludq(a, b);
17250 // AloBhi = pmuludq(a, Bhi);
17251 // AhiBlo = pmuludq(Ahi, b);
17253 // AloBhi = psllqi(AloBhi, 32);
17254 // AhiBlo = psllqi(AhiBlo, 32);
17255 // return AloBlo + AloBhi + AhiBlo;
17257 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17258 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17260 // Bit cast to 32-bit vectors for MULUDQ
17261 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17262 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17263 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17264 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17265 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17266 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17268 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17269 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17270 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17272 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17273 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17275 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17276 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17279 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17280 assert(Subtarget->isTargetWin64() && "Unexpected target");
17281 EVT VT = Op.getValueType();
17282 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17283 "Unexpected return type for lowering");
17287 switch (Op->getOpcode()) {
17288 default: llvm_unreachable("Unexpected request for libcall!");
17289 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17290 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17291 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17292 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17293 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17294 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17298 SDValue InChain = DAG.getEntryNode();
17300 TargetLowering::ArgListTy Args;
17301 TargetLowering::ArgListEntry Entry;
17302 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17303 EVT ArgVT = Op->getOperand(i).getValueType();
17304 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17305 "Unexpected argument type for lowering");
17306 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17307 Entry.Node = StackPtr;
17308 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17310 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17311 Entry.Ty = PointerType::get(ArgTy,0);
17312 Entry.isSExt = false;
17313 Entry.isZExt = false;
17314 Args.push_back(Entry);
17317 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17320 TargetLowering::CallLoweringInfo CLI(DAG);
17321 CLI.setDebugLoc(dl).setChain(InChain)
17322 .setCallee(getLibcallCallingConv(LC),
17323 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17324 Callee, std::move(Args), 0)
17325 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17327 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17328 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17331 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17332 SelectionDAG &DAG) {
17333 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17334 EVT VT = Op0.getValueType();
17337 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17338 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17340 // PMULxD operations multiply each even value (starting at 0) of LHS with
17341 // the related value of RHS and produce a widen result.
17342 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17343 // => <2 x i64> <ae|cg>
17345 // In other word, to have all the results, we need to perform two PMULxD:
17346 // 1. one with the even values.
17347 // 2. one with the odd values.
17348 // To achieve #2, with need to place the odd values at an even position.
17350 // Place the odd value at an even position (basically, shift all values 1
17351 // step to the left):
17352 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17353 // <a|b|c|d> => <b|undef|d|undef>
17354 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17355 // <e|f|g|h> => <f|undef|h|undef>
17356 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17358 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17360 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17361 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17363 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17364 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17365 // => <2 x i64> <ae|cg>
17366 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17367 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17368 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17369 // => <2 x i64> <bf|dh>
17370 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17371 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17373 // Shuffle it back into the right order.
17374 SDValue Highs, Lows;
17375 if (VT == MVT::v8i32) {
17376 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17377 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17378 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17379 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17381 const int HighMask[] = {1, 5, 3, 7};
17382 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17383 const int LowMask[] = {0, 4, 2, 6};
17384 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17387 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17388 // unsigned multiply.
17389 if (IsSigned && !Subtarget->hasSSE41()) {
17391 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17392 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17393 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17394 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17395 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17397 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17398 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17401 // The first result of MUL_LOHI is actually the low value, followed by the
17403 SDValue Ops[] = {Lows, Highs};
17404 return DAG.getMergeValues(Ops, dl);
17407 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17408 const X86Subtarget *Subtarget) {
17409 MVT VT = Op.getSimpleValueType();
17411 SDValue R = Op.getOperand(0);
17412 SDValue Amt = Op.getOperand(1);
17414 // Optimize shl/srl/sra with constant shift amount.
17415 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17416 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17417 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17419 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17420 (Subtarget->hasInt256() &&
17421 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17422 (Subtarget->hasAVX512() &&
17423 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17424 if (Op.getOpcode() == ISD::SHL)
17425 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17427 if (Op.getOpcode() == ISD::SRL)
17428 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17430 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17431 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17435 if (VT == MVT::v16i8) {
17436 if (Op.getOpcode() == ISD::SHL) {
17437 // Make a large shift.
17438 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17439 MVT::v8i16, R, ShiftAmt,
17441 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17442 // Zero out the rightmost bits.
17443 SmallVector<SDValue, 16> V(16,
17444 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17446 return DAG.getNode(ISD::AND, dl, VT, SHL,
17447 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17449 if (Op.getOpcode() == ISD::SRL) {
17450 // Make a large shift.
17451 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17452 MVT::v8i16, R, ShiftAmt,
17454 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17455 // Zero out the leftmost bits.
17456 SmallVector<SDValue, 16> V(16,
17457 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17459 return DAG.getNode(ISD::AND, dl, VT, SRL,
17460 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17462 if (Op.getOpcode() == ISD::SRA) {
17463 if (ShiftAmt == 7) {
17464 // R s>> 7 === R s< 0
17465 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17466 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17469 // R s>> a === ((R u>> a) ^ m) - m
17470 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17471 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17473 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17474 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17475 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17478 llvm_unreachable("Unknown shift opcode.");
17481 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17482 if (Op.getOpcode() == ISD::SHL) {
17483 // Make a large shift.
17484 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17485 MVT::v16i16, R, ShiftAmt,
17487 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17488 // Zero out the rightmost bits.
17489 SmallVector<SDValue, 32> V(32,
17490 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17492 return DAG.getNode(ISD::AND, dl, VT, SHL,
17493 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17495 if (Op.getOpcode() == ISD::SRL) {
17496 // Make a large shift.
17497 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17498 MVT::v16i16, R, ShiftAmt,
17500 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17501 // Zero out the leftmost bits.
17502 SmallVector<SDValue, 32> V(32,
17503 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17505 return DAG.getNode(ISD::AND, dl, VT, SRL,
17506 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17508 if (Op.getOpcode() == ISD::SRA) {
17509 if (ShiftAmt == 7) {
17510 // R s>> 7 === R s< 0
17511 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17512 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17515 // R s>> a === ((R u>> a) ^ m) - m
17516 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17517 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17519 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17520 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17521 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17524 llvm_unreachable("Unknown shift opcode.");
17529 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17530 if (!Subtarget->is64Bit() &&
17531 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17532 Amt.getOpcode() == ISD::BITCAST &&
17533 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17534 Amt = Amt.getOperand(0);
17535 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17536 VT.getVectorNumElements();
17537 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17538 uint64_t ShiftAmt = 0;
17539 for (unsigned i = 0; i != Ratio; ++i) {
17540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17544 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17546 // Check remaining shift amounts.
17547 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17548 uint64_t ShAmt = 0;
17549 for (unsigned j = 0; j != Ratio; ++j) {
17550 ConstantSDNode *C =
17551 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17555 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17557 if (ShAmt != ShiftAmt)
17560 switch (Op.getOpcode()) {
17562 llvm_unreachable("Unknown shift opcode!");
17564 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17567 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17570 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17578 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17579 const X86Subtarget* Subtarget) {
17580 MVT VT = Op.getSimpleValueType();
17582 SDValue R = Op.getOperand(0);
17583 SDValue Amt = Op.getOperand(1);
17585 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17586 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17587 (Subtarget->hasInt256() &&
17588 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17589 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17590 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17592 EVT EltVT = VT.getVectorElementType();
17594 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17595 unsigned NumElts = VT.getVectorNumElements();
17597 for (i = 0; i != NumElts; ++i) {
17598 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17602 for (j = i; j != NumElts; ++j) {
17603 SDValue Arg = Amt.getOperand(j);
17604 if (Arg.getOpcode() == ISD::UNDEF) continue;
17605 if (Arg != Amt.getOperand(i))
17608 if (i != NumElts && j == NumElts)
17609 BaseShAmt = Amt.getOperand(i);
17611 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17612 Amt = Amt.getOperand(0);
17613 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17614 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17615 SDValue InVec = Amt.getOperand(0);
17616 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17617 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17619 for (; i != NumElts; ++i) {
17620 SDValue Arg = InVec.getOperand(i);
17621 if (Arg.getOpcode() == ISD::UNDEF) continue;
17625 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17626 if (ConstantSDNode *C =
17627 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17628 unsigned SplatIdx =
17629 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17630 if (C->getZExtValue() == SplatIdx)
17631 BaseShAmt = InVec.getOperand(1);
17634 if (!BaseShAmt.getNode())
17635 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17636 DAG.getIntPtrConstant(0));
17640 if (BaseShAmt.getNode()) {
17641 if (EltVT.bitsGT(MVT::i32))
17642 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17643 else if (EltVT.bitsLT(MVT::i32))
17644 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17646 switch (Op.getOpcode()) {
17648 llvm_unreachable("Unknown shift opcode!");
17650 switch (VT.SimpleTy) {
17651 default: return SDValue();
17660 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17663 switch (VT.SimpleTy) {
17664 default: return SDValue();
17671 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17674 switch (VT.SimpleTy) {
17675 default: return SDValue();
17684 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17690 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17691 if (!Subtarget->is64Bit() &&
17692 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17693 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17694 Amt.getOpcode() == ISD::BITCAST &&
17695 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17696 Amt = Amt.getOperand(0);
17697 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17698 VT.getVectorNumElements();
17699 std::vector<SDValue> Vals(Ratio);
17700 for (unsigned i = 0; i != Ratio; ++i)
17701 Vals[i] = Amt.getOperand(i);
17702 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17703 for (unsigned j = 0; j != Ratio; ++j)
17704 if (Vals[j] != Amt.getOperand(i + j))
17707 switch (Op.getOpcode()) {
17709 llvm_unreachable("Unknown shift opcode!");
17711 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17713 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17715 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17722 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17723 SelectionDAG &DAG) {
17724 MVT VT = Op.getSimpleValueType();
17726 SDValue R = Op.getOperand(0);
17727 SDValue Amt = Op.getOperand(1);
17730 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17731 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17733 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17737 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17741 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17743 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17744 if (Subtarget->hasInt256()) {
17745 if (Op.getOpcode() == ISD::SRL &&
17746 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17747 VT == MVT::v4i64 || VT == MVT::v8i32))
17749 if (Op.getOpcode() == ISD::SHL &&
17750 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17751 VT == MVT::v4i64 || VT == MVT::v8i32))
17753 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17757 // If possible, lower this packed shift into a vector multiply instead of
17758 // expanding it into a sequence of scalar shifts.
17759 // Do this only if the vector shift count is a constant build_vector.
17760 if (Op.getOpcode() == ISD::SHL &&
17761 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17762 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17763 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17764 SmallVector<SDValue, 8> Elts;
17765 EVT SVT = VT.getScalarType();
17766 unsigned SVTBits = SVT.getSizeInBits();
17767 const APInt &One = APInt(SVTBits, 1);
17768 unsigned NumElems = VT.getVectorNumElements();
17770 for (unsigned i=0; i !=NumElems; ++i) {
17771 SDValue Op = Amt->getOperand(i);
17772 if (Op->getOpcode() == ISD::UNDEF) {
17773 Elts.push_back(Op);
17777 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17778 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17779 uint64_t ShAmt = C.getZExtValue();
17780 if (ShAmt >= SVTBits) {
17781 Elts.push_back(DAG.getUNDEF(SVT));
17784 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17786 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17787 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17790 // Lower SHL with variable shift amount.
17791 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17792 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17794 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17795 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17796 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17797 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17800 // If possible, lower this shift as a sequence of two shifts by
17801 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17803 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17805 // Could be rewritten as:
17806 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17808 // The advantage is that the two shifts from the example would be
17809 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17810 // the vector shift into four scalar shifts plus four pairs of vector
17812 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17813 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17814 unsigned TargetOpcode = X86ISD::MOVSS;
17815 bool CanBeSimplified;
17816 // The splat value for the first packed shift (the 'X' from the example).
17817 SDValue Amt1 = Amt->getOperand(0);
17818 // The splat value for the second packed shift (the 'Y' from the example).
17819 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17820 Amt->getOperand(2);
17822 // See if it is possible to replace this node with a sequence of
17823 // two shifts followed by a MOVSS/MOVSD
17824 if (VT == MVT::v4i32) {
17825 // Check if it is legal to use a MOVSS.
17826 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17827 Amt2 == Amt->getOperand(3);
17828 if (!CanBeSimplified) {
17829 // Otherwise, check if we can still simplify this node using a MOVSD.
17830 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17831 Amt->getOperand(2) == Amt->getOperand(3);
17832 TargetOpcode = X86ISD::MOVSD;
17833 Amt2 = Amt->getOperand(2);
17836 // Do similar checks for the case where the machine value type
17838 CanBeSimplified = Amt1 == Amt->getOperand(1);
17839 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17840 CanBeSimplified = Amt2 == Amt->getOperand(i);
17842 if (!CanBeSimplified) {
17843 TargetOpcode = X86ISD::MOVSD;
17844 CanBeSimplified = true;
17845 Amt2 = Amt->getOperand(4);
17846 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17847 CanBeSimplified = Amt1 == Amt->getOperand(i);
17848 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17849 CanBeSimplified = Amt2 == Amt->getOperand(j);
17853 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17854 isa<ConstantSDNode>(Amt2)) {
17855 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17856 EVT CastVT = MVT::v4i32;
17858 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17859 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17861 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17862 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17863 if (TargetOpcode == X86ISD::MOVSD)
17864 CastVT = MVT::v2i64;
17865 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17866 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17867 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17869 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17873 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17874 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17877 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17878 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17880 // Turn 'a' into a mask suitable for VSELECT
17881 SDValue VSelM = DAG.getConstant(0x80, VT);
17882 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17883 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17885 SDValue CM1 = DAG.getConstant(0x0f, VT);
17886 SDValue CM2 = DAG.getConstant(0x3f, VT);
17888 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17889 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17890 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17891 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17892 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17895 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17896 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17897 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17899 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17900 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17901 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17902 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17903 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17906 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17907 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17908 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17910 // return VSELECT(r, r+r, a);
17911 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17912 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17916 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17917 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17918 // solution better.
17919 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17920 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17922 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17923 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17924 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17925 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17926 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17929 // Decompose 256-bit shifts into smaller 128-bit shifts.
17930 if (VT.is256BitVector()) {
17931 unsigned NumElems = VT.getVectorNumElements();
17932 MVT EltVT = VT.getVectorElementType();
17933 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17935 // Extract the two vectors
17936 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17937 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17939 // Recreate the shift amount vectors
17940 SDValue Amt1, Amt2;
17941 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17942 // Constant shift amount
17943 SmallVector<SDValue, 4> Amt1Csts;
17944 SmallVector<SDValue, 4> Amt2Csts;
17945 for (unsigned i = 0; i != NumElems/2; ++i)
17946 Amt1Csts.push_back(Amt->getOperand(i));
17947 for (unsigned i = NumElems/2; i != NumElems; ++i)
17948 Amt2Csts.push_back(Amt->getOperand(i));
17950 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17951 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17953 // Variable shift amount
17954 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17955 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17958 // Issue new vector shifts for the smaller types
17959 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17960 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17962 // Concatenate the result back
17963 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17969 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17970 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17971 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17972 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17973 // has only one use.
17974 SDNode *N = Op.getNode();
17975 SDValue LHS = N->getOperand(0);
17976 SDValue RHS = N->getOperand(1);
17977 unsigned BaseOp = 0;
17980 switch (Op.getOpcode()) {
17981 default: llvm_unreachable("Unknown ovf instruction!");
17983 // A subtract of one will be selected as a INC. Note that INC doesn't
17984 // set CF, so we can't do this for UADDO.
17985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17987 BaseOp = X86ISD::INC;
17988 Cond = X86::COND_O;
17991 BaseOp = X86ISD::ADD;
17992 Cond = X86::COND_O;
17995 BaseOp = X86ISD::ADD;
17996 Cond = X86::COND_B;
17999 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18000 // set CF, so we can't do this for USUBO.
18001 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18003 BaseOp = X86ISD::DEC;
18004 Cond = X86::COND_O;
18007 BaseOp = X86ISD::SUB;
18008 Cond = X86::COND_O;
18011 BaseOp = X86ISD::SUB;
18012 Cond = X86::COND_B;
18015 BaseOp = X86ISD::SMUL;
18016 Cond = X86::COND_O;
18018 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18019 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18021 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18024 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18025 DAG.getConstant(X86::COND_O, MVT::i32),
18026 SDValue(Sum.getNode(), 2));
18028 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18032 // Also sets EFLAGS.
18033 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18034 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18037 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18038 DAG.getConstant(Cond, MVT::i32),
18039 SDValue(Sum.getNode(), 1));
18041 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18044 // Sign extension of the low part of vector elements. This may be used either
18045 // when sign extend instructions are not available or if the vector element
18046 // sizes already match the sign-extended size. If the vector elements are in
18047 // their pre-extended size and sign extend instructions are available, that will
18048 // be handled by LowerSIGN_EXTEND.
18049 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18050 SelectionDAG &DAG) const {
18052 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18053 MVT VT = Op.getSimpleValueType();
18055 if (!Subtarget->hasSSE2() || !VT.isVector())
18058 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18059 ExtraVT.getScalarType().getSizeInBits();
18061 switch (VT.SimpleTy) {
18062 default: return SDValue();
18065 if (!Subtarget->hasFp256())
18067 if (!Subtarget->hasInt256()) {
18068 // needs to be split
18069 unsigned NumElems = VT.getVectorNumElements();
18071 // Extract the LHS vectors
18072 SDValue LHS = Op.getOperand(0);
18073 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18074 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18076 MVT EltVT = VT.getVectorElementType();
18077 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18079 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18080 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18081 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18083 SDValue Extra = DAG.getValueType(ExtraVT);
18085 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18086 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18088 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18093 SDValue Op0 = Op.getOperand(0);
18095 // This is a sign extension of some low part of vector elements without
18096 // changing the size of the vector elements themselves:
18097 // Shift-Left + Shift-Right-Algebraic.
18098 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18100 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18106 /// Returns true if the operand type is exactly twice the native width, and
18107 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18108 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18109 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18110 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18111 const X86Subtarget &Subtarget =
18112 getTargetMachine().getSubtarget<X86Subtarget>();
18113 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18116 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18117 else if (OpWidth == 128)
18118 return Subtarget.hasCmpxchg16b();
18123 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18124 return needsCmpXchgNb(SI->getValueOperand()->getType());
18127 // Note: this turns large loads into lock cmpxchg8b/16b.
18128 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18129 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18130 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18131 return needsCmpXchgNb(PTy->getElementType());
18134 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18135 const X86Subtarget &Subtarget =
18136 getTargetMachine().getSubtarget<X86Subtarget>();
18137 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18138 const Type *MemType = AI->getType();
18140 // If the operand is too big, we must see if cmpxchg8/16b is available
18141 // and default to library calls otherwise.
18142 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18143 return needsCmpXchgNb(MemType);
18145 AtomicRMWInst::BinOp Op = AI->getOperation();
18148 llvm_unreachable("Unknown atomic operation");
18149 case AtomicRMWInst::Xchg:
18150 case AtomicRMWInst::Add:
18151 case AtomicRMWInst::Sub:
18152 // It's better to use xadd, xsub or xchg for these in all cases.
18154 case AtomicRMWInst::Or:
18155 case AtomicRMWInst::And:
18156 case AtomicRMWInst::Xor:
18157 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18158 // prefix to a normal instruction for these operations.
18159 return !AI->use_empty();
18160 case AtomicRMWInst::Nand:
18161 case AtomicRMWInst::Max:
18162 case AtomicRMWInst::Min:
18163 case AtomicRMWInst::UMax:
18164 case AtomicRMWInst::UMin:
18165 // These always require a non-trivial set of data operations on x86. We must
18166 // use a cmpxchg loop.
18171 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18172 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18173 // no-sse2). There isn't any reason to disable it if the target processor
18175 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18179 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18180 const X86Subtarget &Subtarget =
18181 getTargetMachine().getSubtarget<X86Subtarget>();
18182 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18183 const Type *MemType = AI->getType();
18184 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18185 // there is no benefit in turning such RMWs into loads, and it is actually
18186 // harmful as it introduces a mfence.
18187 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18190 auto Builder = IRBuilder<>(AI);
18191 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18192 auto SynchScope = AI->getSynchScope();
18193 // We must restrict the ordering to avoid generating loads with Release or
18194 // ReleaseAcquire orderings.
18195 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18196 auto Ptr = AI->getPointerOperand();
18198 // Before the load we need a fence. Here is an example lifted from
18199 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18202 // x.store(1, relaxed);
18203 // r1 = y.fetch_add(0, release);
18205 // y.fetch_add(42, acquire);
18206 // r2 = x.load(relaxed);
18207 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18208 // lowered to just a load without a fence. A mfence flushes the store buffer,
18209 // making the optimization clearly correct.
18210 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18211 // otherwise, we might be able to be more agressive on relaxed idempotent
18212 // rmw. In practice, they do not look useful, so we don't try to be
18213 // especially clever.
18214 if (SynchScope == SingleThread) {
18215 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18216 // the IR level, so we must wrap it in an intrinsic.
18218 } else if (hasMFENCE(Subtarget)) {
18219 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18220 Intrinsic::x86_sse2_mfence);
18221 Builder.CreateCall(MFence);
18223 // FIXME: it might make sense to use a locked operation here but on a
18224 // different cache-line to prevent cache-line bouncing. In practice it
18225 // is probably a small win, and x86 processors without mfence are rare
18226 // enough that we do not bother.
18230 // Finally we can emit the atomic load.
18231 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18232 AI->getType()->getPrimitiveSizeInBits());
18233 Loaded->setAtomic(Order, SynchScope);
18234 AI->replaceAllUsesWith(Loaded);
18235 AI->eraseFromParent();
18239 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18240 SelectionDAG &DAG) {
18242 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18243 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18244 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18245 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18247 // The only fence that needs an instruction is a sequentially-consistent
18248 // cross-thread fence.
18249 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18250 if (hasMFENCE(*Subtarget))
18251 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18253 SDValue Chain = Op.getOperand(0);
18254 SDValue Zero = DAG.getConstant(0, MVT::i32);
18256 DAG.getRegister(X86::ESP, MVT::i32), // Base
18257 DAG.getTargetConstant(1, MVT::i8), // Scale
18258 DAG.getRegister(0, MVT::i32), // Index
18259 DAG.getTargetConstant(0, MVT::i32), // Disp
18260 DAG.getRegister(0, MVT::i32), // Segment.
18264 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18265 return SDValue(Res, 0);
18268 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18269 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18272 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18273 SelectionDAG &DAG) {
18274 MVT T = Op.getSimpleValueType();
18278 switch(T.SimpleTy) {
18279 default: llvm_unreachable("Invalid value type!");
18280 case MVT::i8: Reg = X86::AL; size = 1; break;
18281 case MVT::i16: Reg = X86::AX; size = 2; break;
18282 case MVT::i32: Reg = X86::EAX; size = 4; break;
18284 assert(Subtarget->is64Bit() && "Node not type legal!");
18285 Reg = X86::RAX; size = 8;
18288 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18289 Op.getOperand(2), SDValue());
18290 SDValue Ops[] = { cpIn.getValue(0),
18293 DAG.getTargetConstant(size, MVT::i8),
18294 cpIn.getValue(1) };
18295 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18296 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18297 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18301 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18302 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18303 MVT::i32, cpOut.getValue(2));
18304 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18305 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18307 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18308 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18309 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18313 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18314 SelectionDAG &DAG) {
18315 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18316 MVT DstVT = Op.getSimpleValueType();
18318 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18319 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18320 if (DstVT != MVT::f64)
18321 // This conversion needs to be expanded.
18324 SDValue InVec = Op->getOperand(0);
18326 unsigned NumElts = SrcVT.getVectorNumElements();
18327 EVT SVT = SrcVT.getVectorElementType();
18329 // Widen the vector in input in the case of MVT::v2i32.
18330 // Example: from MVT::v2i32 to MVT::v4i32.
18331 SmallVector<SDValue, 16> Elts;
18332 for (unsigned i = 0, e = NumElts; i != e; ++i)
18333 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18334 DAG.getIntPtrConstant(i)));
18336 // Explicitly mark the extra elements as Undef.
18337 SDValue Undef = DAG.getUNDEF(SVT);
18338 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18339 Elts.push_back(Undef);
18341 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18342 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18343 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18344 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18345 DAG.getIntPtrConstant(0));
18348 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18349 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18350 assert((DstVT == MVT::i64 ||
18351 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18352 "Unexpected custom BITCAST");
18353 // i64 <=> MMX conversions are Legal.
18354 if (SrcVT==MVT::i64 && DstVT.isVector())
18356 if (DstVT==MVT::i64 && SrcVT.isVector())
18358 // MMX <=> MMX conversions are Legal.
18359 if (SrcVT.isVector() && DstVT.isVector())
18361 // All other conversions need to be expanded.
18365 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18366 SDNode *Node = Op.getNode();
18368 EVT T = Node->getValueType(0);
18369 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18370 DAG.getConstant(0, T), Node->getOperand(2));
18371 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18372 cast<AtomicSDNode>(Node)->getMemoryVT(),
18373 Node->getOperand(0),
18374 Node->getOperand(1), negOp,
18375 cast<AtomicSDNode>(Node)->getMemOperand(),
18376 cast<AtomicSDNode>(Node)->getOrdering(),
18377 cast<AtomicSDNode>(Node)->getSynchScope());
18380 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18381 SDNode *Node = Op.getNode();
18383 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18385 // Convert seq_cst store -> xchg
18386 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18387 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18388 // (The only way to get a 16-byte store is cmpxchg16b)
18389 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18390 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18391 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18392 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18393 cast<AtomicSDNode>(Node)->getMemoryVT(),
18394 Node->getOperand(0),
18395 Node->getOperand(1), Node->getOperand(2),
18396 cast<AtomicSDNode>(Node)->getMemOperand(),
18397 cast<AtomicSDNode>(Node)->getOrdering(),
18398 cast<AtomicSDNode>(Node)->getSynchScope());
18399 return Swap.getValue(1);
18401 // Other atomic stores have a simple pattern.
18405 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18406 EVT VT = Op.getNode()->getSimpleValueType(0);
18408 // Let legalize expand this if it isn't a legal type yet.
18409 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18412 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18415 bool ExtraOp = false;
18416 switch (Op.getOpcode()) {
18417 default: llvm_unreachable("Invalid code");
18418 case ISD::ADDC: Opc = X86ISD::ADD; break;
18419 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18420 case ISD::SUBC: Opc = X86ISD::SUB; break;
18421 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18425 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18427 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18428 Op.getOperand(1), Op.getOperand(2));
18431 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18432 SelectionDAG &DAG) {
18433 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18435 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18436 // which returns the values as { float, float } (in XMM0) or
18437 // { double, double } (which is returned in XMM0, XMM1).
18439 SDValue Arg = Op.getOperand(0);
18440 EVT ArgVT = Arg.getValueType();
18441 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18443 TargetLowering::ArgListTy Args;
18444 TargetLowering::ArgListEntry Entry;
18448 Entry.isSExt = false;
18449 Entry.isZExt = false;
18450 Args.push_back(Entry);
18452 bool isF64 = ArgVT == MVT::f64;
18453 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18454 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18455 // the results are returned via SRet in memory.
18456 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18458 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18460 Type *RetTy = isF64
18461 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18462 : (Type*)VectorType::get(ArgTy, 4);
18464 TargetLowering::CallLoweringInfo CLI(DAG);
18465 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18466 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18468 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18471 // Returned in xmm0 and xmm1.
18472 return CallResult.first;
18474 // Returned in bits 0:31 and 32:64 xmm0.
18475 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18476 CallResult.first, DAG.getIntPtrConstant(0));
18477 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18478 CallResult.first, DAG.getIntPtrConstant(1));
18479 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18480 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18483 /// LowerOperation - Provide custom lowering hooks for some operations.
18485 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18486 switch (Op.getOpcode()) {
18487 default: llvm_unreachable("Should not custom lower this!");
18488 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18489 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18490 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18491 return LowerCMP_SWAP(Op, Subtarget, DAG);
18492 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18493 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18494 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18495 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18496 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18497 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18498 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18499 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18500 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18501 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18502 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18503 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18504 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18505 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18506 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18507 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18508 case ISD::SHL_PARTS:
18509 case ISD::SRA_PARTS:
18510 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18511 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18512 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18513 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18514 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18515 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18516 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18517 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18518 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18519 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18520 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18522 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18523 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18524 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18525 case ISD::SETCC: return LowerSETCC(Op, DAG);
18526 case ISD::SELECT: return LowerSELECT(Op, DAG);
18527 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18528 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18529 case ISD::VASTART: return LowerVASTART(Op, DAG);
18530 case ISD::VAARG: return LowerVAARG(Op, DAG);
18531 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18532 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18533 case ISD::INTRINSIC_VOID:
18534 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18535 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18536 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18537 case ISD::FRAME_TO_ARGS_OFFSET:
18538 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18539 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18540 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18541 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18542 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18543 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18544 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18545 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18546 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18547 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18548 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18549 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18550 case ISD::UMUL_LOHI:
18551 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18554 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18560 case ISD::UMULO: return LowerXALUO(Op, DAG);
18561 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18562 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18566 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18567 case ISD::ADD: return LowerADD(Op, DAG);
18568 case ISD::SUB: return LowerSUB(Op, DAG);
18569 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18573 /// ReplaceNodeResults - Replace a node with an illegal result type
18574 /// with a new node built out of custom code.
18575 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18576 SmallVectorImpl<SDValue>&Results,
18577 SelectionDAG &DAG) const {
18579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18580 switch (N->getOpcode()) {
18582 llvm_unreachable("Do not know how to custom type legalize this operation!");
18583 case ISD::SIGN_EXTEND_INREG:
18588 // We don't want to expand or promote these.
18595 case ISD::UDIVREM: {
18596 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18597 Results.push_back(V);
18600 case ISD::FP_TO_SINT:
18601 case ISD::FP_TO_UINT: {
18602 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18604 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18607 std::pair<SDValue,SDValue> Vals =
18608 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18609 SDValue FIST = Vals.first, StackSlot = Vals.second;
18610 if (FIST.getNode()) {
18611 EVT VT = N->getValueType(0);
18612 // Return a load from the stack slot.
18613 if (StackSlot.getNode())
18614 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18615 MachinePointerInfo(),
18616 false, false, false, 0));
18618 Results.push_back(FIST);
18622 case ISD::UINT_TO_FP: {
18623 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18624 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18625 N->getValueType(0) != MVT::v2f32)
18627 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18629 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18631 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18632 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18633 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18634 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18635 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18636 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18639 case ISD::FP_ROUND: {
18640 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18642 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18643 Results.push_back(V);
18646 case ISD::INTRINSIC_W_CHAIN: {
18647 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18649 default : llvm_unreachable("Do not know how to custom type "
18650 "legalize this intrinsic operation!");
18651 case Intrinsic::x86_rdtsc:
18652 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18654 case Intrinsic::x86_rdtscp:
18655 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18657 case Intrinsic::x86_rdpmc:
18658 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18661 case ISD::READCYCLECOUNTER: {
18662 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18665 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18666 EVT T = N->getValueType(0);
18667 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18668 bool Regs64bit = T == MVT::i128;
18669 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18670 SDValue cpInL, cpInH;
18671 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18672 DAG.getConstant(0, HalfT));
18673 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18674 DAG.getConstant(1, HalfT));
18675 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18676 Regs64bit ? X86::RAX : X86::EAX,
18678 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18679 Regs64bit ? X86::RDX : X86::EDX,
18680 cpInH, cpInL.getValue(1));
18681 SDValue swapInL, swapInH;
18682 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18683 DAG.getConstant(0, HalfT));
18684 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18685 DAG.getConstant(1, HalfT));
18686 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18687 Regs64bit ? X86::RBX : X86::EBX,
18688 swapInL, cpInH.getValue(1));
18689 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18690 Regs64bit ? X86::RCX : X86::ECX,
18691 swapInH, swapInL.getValue(1));
18692 SDValue Ops[] = { swapInH.getValue(0),
18694 swapInH.getValue(1) };
18695 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18696 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18697 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18698 X86ISD::LCMPXCHG8_DAG;
18699 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18700 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18701 Regs64bit ? X86::RAX : X86::EAX,
18702 HalfT, Result.getValue(1));
18703 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18704 Regs64bit ? X86::RDX : X86::EDX,
18705 HalfT, cpOutL.getValue(2));
18706 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18708 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18709 MVT::i32, cpOutH.getValue(2));
18711 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18712 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18713 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18715 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18716 Results.push_back(Success);
18717 Results.push_back(EFLAGS.getValue(1));
18720 case ISD::ATOMIC_SWAP:
18721 case ISD::ATOMIC_LOAD_ADD:
18722 case ISD::ATOMIC_LOAD_SUB:
18723 case ISD::ATOMIC_LOAD_AND:
18724 case ISD::ATOMIC_LOAD_OR:
18725 case ISD::ATOMIC_LOAD_XOR:
18726 case ISD::ATOMIC_LOAD_NAND:
18727 case ISD::ATOMIC_LOAD_MIN:
18728 case ISD::ATOMIC_LOAD_MAX:
18729 case ISD::ATOMIC_LOAD_UMIN:
18730 case ISD::ATOMIC_LOAD_UMAX:
18731 case ISD::ATOMIC_LOAD: {
18732 // Delegate to generic TypeLegalization. Situations we can really handle
18733 // should have already been dealt with by AtomicExpandPass.cpp.
18736 case ISD::BITCAST: {
18737 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18738 EVT DstVT = N->getValueType(0);
18739 EVT SrcVT = N->getOperand(0)->getValueType(0);
18741 if (SrcVT != MVT::f64 ||
18742 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18745 unsigned NumElts = DstVT.getVectorNumElements();
18746 EVT SVT = DstVT.getVectorElementType();
18747 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18748 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18749 MVT::v2f64, N->getOperand(0));
18750 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18752 if (ExperimentalVectorWideningLegalization) {
18753 // If we are legalizing vectors by widening, we already have the desired
18754 // legal vector type, just return it.
18755 Results.push_back(ToVecInt);
18759 SmallVector<SDValue, 8> Elts;
18760 for (unsigned i = 0, e = NumElts; i != e; ++i)
18761 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18762 ToVecInt, DAG.getIntPtrConstant(i)));
18764 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18769 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18771 default: return nullptr;
18772 case X86ISD::BSF: return "X86ISD::BSF";
18773 case X86ISD::BSR: return "X86ISD::BSR";
18774 case X86ISD::SHLD: return "X86ISD::SHLD";
18775 case X86ISD::SHRD: return "X86ISD::SHRD";
18776 case X86ISD::FAND: return "X86ISD::FAND";
18777 case X86ISD::FANDN: return "X86ISD::FANDN";
18778 case X86ISD::FOR: return "X86ISD::FOR";
18779 case X86ISD::FXOR: return "X86ISD::FXOR";
18780 case X86ISD::FSRL: return "X86ISD::FSRL";
18781 case X86ISD::FILD: return "X86ISD::FILD";
18782 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18783 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18784 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18785 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18786 case X86ISD::FLD: return "X86ISD::FLD";
18787 case X86ISD::FST: return "X86ISD::FST";
18788 case X86ISD::CALL: return "X86ISD::CALL";
18789 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18790 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18791 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18792 case X86ISD::BT: return "X86ISD::BT";
18793 case X86ISD::CMP: return "X86ISD::CMP";
18794 case X86ISD::COMI: return "X86ISD::COMI";
18795 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18796 case X86ISD::CMPM: return "X86ISD::CMPM";
18797 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18798 case X86ISD::SETCC: return "X86ISD::SETCC";
18799 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18800 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18801 case X86ISD::CMOV: return "X86ISD::CMOV";
18802 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18803 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18804 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18805 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18806 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18807 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18808 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18809 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18810 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18811 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18812 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18813 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18814 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18815 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18816 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18817 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18818 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18819 case X86ISD::HADD: return "X86ISD::HADD";
18820 case X86ISD::HSUB: return "X86ISD::HSUB";
18821 case X86ISD::FHADD: return "X86ISD::FHADD";
18822 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18823 case X86ISD::UMAX: return "X86ISD::UMAX";
18824 case X86ISD::UMIN: return "X86ISD::UMIN";
18825 case X86ISD::SMAX: return "X86ISD::SMAX";
18826 case X86ISD::SMIN: return "X86ISD::SMIN";
18827 case X86ISD::FMAX: return "X86ISD::FMAX";
18828 case X86ISD::FMIN: return "X86ISD::FMIN";
18829 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18830 case X86ISD::FMINC: return "X86ISD::FMINC";
18831 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18832 case X86ISD::FRCP: return "X86ISD::FRCP";
18833 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18834 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18835 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18836 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18837 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18838 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18839 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18840 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18841 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18842 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18843 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18844 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18845 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18846 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18847 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18848 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18849 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18850 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18851 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18852 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18853 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18854 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18855 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18856 case X86ISD::VSHL: return "X86ISD::VSHL";
18857 case X86ISD::VSRL: return "X86ISD::VSRL";
18858 case X86ISD::VSRA: return "X86ISD::VSRA";
18859 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18860 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18861 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18862 case X86ISD::CMPP: return "X86ISD::CMPP";
18863 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18864 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18865 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18866 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18867 case X86ISD::ADD: return "X86ISD::ADD";
18868 case X86ISD::SUB: return "X86ISD::SUB";
18869 case X86ISD::ADC: return "X86ISD::ADC";
18870 case X86ISD::SBB: return "X86ISD::SBB";
18871 case X86ISD::SMUL: return "X86ISD::SMUL";
18872 case X86ISD::UMUL: return "X86ISD::UMUL";
18873 case X86ISD::INC: return "X86ISD::INC";
18874 case X86ISD::DEC: return "X86ISD::DEC";
18875 case X86ISD::OR: return "X86ISD::OR";
18876 case X86ISD::XOR: return "X86ISD::XOR";
18877 case X86ISD::AND: return "X86ISD::AND";
18878 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18879 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18880 case X86ISD::PTEST: return "X86ISD::PTEST";
18881 case X86ISD::TESTP: return "X86ISD::TESTP";
18882 case X86ISD::TESTM: return "X86ISD::TESTM";
18883 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18884 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18885 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18886 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18887 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18888 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18889 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18890 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18891 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18892 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18893 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18894 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18895 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18896 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18897 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18898 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18899 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18900 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18901 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18902 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18903 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18904 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18905 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18906 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18907 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18908 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18909 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18910 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18911 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18912 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18913 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18914 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18915 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18916 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18917 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18918 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18919 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18920 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18921 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18922 case X86ISD::SAHF: return "X86ISD::SAHF";
18923 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18924 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18925 case X86ISD::FMADD: return "X86ISD::FMADD";
18926 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18927 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18928 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18929 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18930 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18931 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18932 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18933 case X86ISD::XTEST: return "X86ISD::XTEST";
18937 // isLegalAddressingMode - Return true if the addressing mode represented
18938 // by AM is legal for this target, for a load/store of the specified type.
18939 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18941 // X86 supports extremely general addressing modes.
18942 CodeModel::Model M = getTargetMachine().getCodeModel();
18943 Reloc::Model R = getTargetMachine().getRelocationModel();
18945 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18946 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18951 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18953 // If a reference to this global requires an extra load, we can't fold it.
18954 if (isGlobalStubReference(GVFlags))
18957 // If BaseGV requires a register for the PIC base, we cannot also have a
18958 // BaseReg specified.
18959 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18962 // If lower 4G is not available, then we must use rip-relative addressing.
18963 if ((M != CodeModel::Small || R != Reloc::Static) &&
18964 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18968 switch (AM.Scale) {
18974 // These scales always work.
18979 // These scales are formed with basereg+scalereg. Only accept if there is
18984 default: // Other stuff never works.
18991 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18992 unsigned Bits = Ty->getScalarSizeInBits();
18994 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18995 // particularly cheaper than those without.
18999 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19000 // variable shifts just as cheap as scalar ones.
19001 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19004 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19005 // fully general vector.
19009 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19010 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19012 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19013 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19014 return NumBits1 > NumBits2;
19017 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19018 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19021 if (!isTypeLegal(EVT::getEVT(Ty1)))
19024 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19026 // Assuming the caller doesn't have a zeroext or signext return parameter,
19027 // truncation all the way down to i1 is valid.
19031 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19032 return isInt<32>(Imm);
19035 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19036 // Can also use sub to handle negated immediates.
19037 return isInt<32>(Imm);
19040 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19041 if (!VT1.isInteger() || !VT2.isInteger())
19043 unsigned NumBits1 = VT1.getSizeInBits();
19044 unsigned NumBits2 = VT2.getSizeInBits();
19045 return NumBits1 > NumBits2;
19048 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19049 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19050 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19053 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19054 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19055 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19058 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19059 EVT VT1 = Val.getValueType();
19060 if (isZExtFree(VT1, VT2))
19063 if (Val.getOpcode() != ISD::LOAD)
19066 if (!VT1.isSimple() || !VT1.isInteger() ||
19067 !VT2.isSimple() || !VT2.isInteger())
19070 switch (VT1.getSimpleVT().SimpleTy) {
19075 // X86 has 8, 16, and 32-bit zero-extending loads.
19083 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19084 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19087 VT = VT.getScalarType();
19089 if (!VT.isSimple())
19092 switch (VT.getSimpleVT().SimpleTy) {
19103 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19104 // i16 instructions are longer (0x66 prefix) and potentially slower.
19105 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19108 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19109 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19110 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19111 /// are assumed to be legal.
19113 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19115 if (!VT.isSimple())
19118 MVT SVT = VT.getSimpleVT();
19120 // Very little shuffling can be done for 64-bit vectors right now.
19121 if (VT.getSizeInBits() == 64)
19124 // If this is a single-input shuffle with no 128 bit lane crossings we can
19125 // lower it into pshufb.
19126 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19127 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19128 bool isLegal = true;
19129 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19130 if (M[I] >= (int)SVT.getVectorNumElements() ||
19131 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19140 // FIXME: blends, shifts.
19141 return (SVT.getVectorNumElements() == 2 ||
19142 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19143 isMOVLMask(M, SVT) ||
19144 isMOVHLPSMask(M, SVT) ||
19145 isSHUFPMask(M, SVT) ||
19146 isPSHUFDMask(M, SVT) ||
19147 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19148 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19149 isPALIGNRMask(M, SVT, Subtarget) ||
19150 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19151 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19152 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19153 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19154 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19158 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19160 if (!VT.isSimple())
19163 MVT SVT = VT.getSimpleVT();
19164 unsigned NumElts = SVT.getVectorNumElements();
19165 // FIXME: This collection of masks seems suspect.
19168 if (NumElts == 4 && SVT.is128BitVector()) {
19169 return (isMOVLMask(Mask, SVT) ||
19170 isCommutedMOVLMask(Mask, SVT, true) ||
19171 isSHUFPMask(Mask, SVT) ||
19172 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19177 //===----------------------------------------------------------------------===//
19178 // X86 Scheduler Hooks
19179 //===----------------------------------------------------------------------===//
19181 /// Utility function to emit xbegin specifying the start of an RTM region.
19182 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19183 const TargetInstrInfo *TII) {
19184 DebugLoc DL = MI->getDebugLoc();
19186 const BasicBlock *BB = MBB->getBasicBlock();
19187 MachineFunction::iterator I = MBB;
19190 // For the v = xbegin(), we generate
19201 MachineBasicBlock *thisMBB = MBB;
19202 MachineFunction *MF = MBB->getParent();
19203 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19204 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19205 MF->insert(I, mainMBB);
19206 MF->insert(I, sinkMBB);
19208 // Transfer the remainder of BB and its successor edges to sinkMBB.
19209 sinkMBB->splice(sinkMBB->begin(), MBB,
19210 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19211 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19215 // # fallthrough to mainMBB
19216 // # abortion to sinkMBB
19217 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19218 thisMBB->addSuccessor(mainMBB);
19219 thisMBB->addSuccessor(sinkMBB);
19223 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19224 mainMBB->addSuccessor(sinkMBB);
19227 // EAX is live into the sinkMBB
19228 sinkMBB->addLiveIn(X86::EAX);
19229 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19230 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19233 MI->eraseFromParent();
19237 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19238 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19239 // in the .td file.
19240 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19241 const TargetInstrInfo *TII) {
19243 switch (MI->getOpcode()) {
19244 default: llvm_unreachable("illegal opcode!");
19245 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19246 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19247 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19248 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19249 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19250 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19251 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19252 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19255 DebugLoc dl = MI->getDebugLoc();
19256 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19258 unsigned NumArgs = MI->getNumOperands();
19259 for (unsigned i = 1; i < NumArgs; ++i) {
19260 MachineOperand &Op = MI->getOperand(i);
19261 if (!(Op.isReg() && Op.isImplicit()))
19262 MIB.addOperand(Op);
19264 if (MI->hasOneMemOperand())
19265 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19267 BuildMI(*BB, MI, dl,
19268 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19269 .addReg(X86::XMM0);
19271 MI->eraseFromParent();
19275 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19276 // defs in an instruction pattern
19277 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19278 const TargetInstrInfo *TII) {
19280 switch (MI->getOpcode()) {
19281 default: llvm_unreachable("illegal opcode!");
19282 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19283 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19284 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19285 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19286 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19287 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19288 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19289 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19292 DebugLoc dl = MI->getDebugLoc();
19293 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19295 unsigned NumArgs = MI->getNumOperands(); // remove the results
19296 for (unsigned i = 1; i < NumArgs; ++i) {
19297 MachineOperand &Op = MI->getOperand(i);
19298 if (!(Op.isReg() && Op.isImplicit()))
19299 MIB.addOperand(Op);
19301 if (MI->hasOneMemOperand())
19302 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19304 BuildMI(*BB, MI, dl,
19305 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19308 MI->eraseFromParent();
19312 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19313 const TargetInstrInfo *TII,
19314 const X86Subtarget* Subtarget) {
19315 DebugLoc dl = MI->getDebugLoc();
19317 // Address into RAX/EAX, other two args into ECX, EDX.
19318 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19319 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19320 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19321 for (int i = 0; i < X86::AddrNumOperands; ++i)
19322 MIB.addOperand(MI->getOperand(i));
19324 unsigned ValOps = X86::AddrNumOperands;
19325 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19326 .addReg(MI->getOperand(ValOps).getReg());
19327 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19328 .addReg(MI->getOperand(ValOps+1).getReg());
19330 // The instruction doesn't actually take any operands though.
19331 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19333 MI->eraseFromParent(); // The pseudo is gone now.
19337 MachineBasicBlock *
19338 X86TargetLowering::EmitVAARG64WithCustomInserter(
19340 MachineBasicBlock *MBB) const {
19341 // Emit va_arg instruction on X86-64.
19343 // Operands to this pseudo-instruction:
19344 // 0 ) Output : destination address (reg)
19345 // 1-5) Input : va_list address (addr, i64mem)
19346 // 6 ) ArgSize : Size (in bytes) of vararg type
19347 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19348 // 8 ) Align : Alignment of type
19349 // 9 ) EFLAGS (implicit-def)
19351 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19352 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19354 unsigned DestReg = MI->getOperand(0).getReg();
19355 MachineOperand &Base = MI->getOperand(1);
19356 MachineOperand &Scale = MI->getOperand(2);
19357 MachineOperand &Index = MI->getOperand(3);
19358 MachineOperand &Disp = MI->getOperand(4);
19359 MachineOperand &Segment = MI->getOperand(5);
19360 unsigned ArgSize = MI->getOperand(6).getImm();
19361 unsigned ArgMode = MI->getOperand(7).getImm();
19362 unsigned Align = MI->getOperand(8).getImm();
19364 // Memory Reference
19365 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19366 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19367 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19369 // Machine Information
19370 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19371 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19372 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19373 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19374 DebugLoc DL = MI->getDebugLoc();
19376 // struct va_list {
19379 // i64 overflow_area (address)
19380 // i64 reg_save_area (address)
19382 // sizeof(va_list) = 24
19383 // alignment(va_list) = 8
19385 unsigned TotalNumIntRegs = 6;
19386 unsigned TotalNumXMMRegs = 8;
19387 bool UseGPOffset = (ArgMode == 1);
19388 bool UseFPOffset = (ArgMode == 2);
19389 unsigned MaxOffset = TotalNumIntRegs * 8 +
19390 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19392 /* Align ArgSize to a multiple of 8 */
19393 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19394 bool NeedsAlign = (Align > 8);
19396 MachineBasicBlock *thisMBB = MBB;
19397 MachineBasicBlock *overflowMBB;
19398 MachineBasicBlock *offsetMBB;
19399 MachineBasicBlock *endMBB;
19401 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19402 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19403 unsigned OffsetReg = 0;
19405 if (!UseGPOffset && !UseFPOffset) {
19406 // If we only pull from the overflow region, we don't create a branch.
19407 // We don't need to alter control flow.
19408 OffsetDestReg = 0; // unused
19409 OverflowDestReg = DestReg;
19411 offsetMBB = nullptr;
19412 overflowMBB = thisMBB;
19415 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19416 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19417 // If not, pull from overflow_area. (branch to overflowMBB)
19422 // offsetMBB overflowMBB
19427 // Registers for the PHI in endMBB
19428 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19429 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19431 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19432 MachineFunction *MF = MBB->getParent();
19433 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19434 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19435 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19437 MachineFunction::iterator MBBIter = MBB;
19440 // Insert the new basic blocks
19441 MF->insert(MBBIter, offsetMBB);
19442 MF->insert(MBBIter, overflowMBB);
19443 MF->insert(MBBIter, endMBB);
19445 // Transfer the remainder of MBB and its successor edges to endMBB.
19446 endMBB->splice(endMBB->begin(), thisMBB,
19447 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19448 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19450 // Make offsetMBB and overflowMBB successors of thisMBB
19451 thisMBB->addSuccessor(offsetMBB);
19452 thisMBB->addSuccessor(overflowMBB);
19454 // endMBB is a successor of both offsetMBB and overflowMBB
19455 offsetMBB->addSuccessor(endMBB);
19456 overflowMBB->addSuccessor(endMBB);
19458 // Load the offset value into a register
19459 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19460 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19464 .addDisp(Disp, UseFPOffset ? 4 : 0)
19465 .addOperand(Segment)
19466 .setMemRefs(MMOBegin, MMOEnd);
19468 // Check if there is enough room left to pull this argument.
19469 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19471 .addImm(MaxOffset + 8 - ArgSizeA8);
19473 // Branch to "overflowMBB" if offset >= max
19474 // Fall through to "offsetMBB" otherwise
19475 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19476 .addMBB(overflowMBB);
19479 // In offsetMBB, emit code to use the reg_save_area.
19481 assert(OffsetReg != 0);
19483 // Read the reg_save_area address.
19484 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19485 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19490 .addOperand(Segment)
19491 .setMemRefs(MMOBegin, MMOEnd);
19493 // Zero-extend the offset
19494 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19495 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19498 .addImm(X86::sub_32bit);
19500 // Add the offset to the reg_save_area to get the final address.
19501 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19502 .addReg(OffsetReg64)
19503 .addReg(RegSaveReg);
19505 // Compute the offset for the next argument
19506 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19507 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19509 .addImm(UseFPOffset ? 16 : 8);
19511 // Store it back into the va_list.
19512 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19516 .addDisp(Disp, UseFPOffset ? 4 : 0)
19517 .addOperand(Segment)
19518 .addReg(NextOffsetReg)
19519 .setMemRefs(MMOBegin, MMOEnd);
19522 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19527 // Emit code to use overflow area
19530 // Load the overflow_area address into a register.
19531 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19532 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19537 .addOperand(Segment)
19538 .setMemRefs(MMOBegin, MMOEnd);
19540 // If we need to align it, do so. Otherwise, just copy the address
19541 // to OverflowDestReg.
19543 // Align the overflow address
19544 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19545 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19547 // aligned_addr = (addr + (align-1)) & ~(align-1)
19548 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19549 .addReg(OverflowAddrReg)
19552 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19554 .addImm(~(uint64_t)(Align-1));
19556 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19557 .addReg(OverflowAddrReg);
19560 // Compute the next overflow address after this argument.
19561 // (the overflow address should be kept 8-byte aligned)
19562 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19563 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19564 .addReg(OverflowDestReg)
19565 .addImm(ArgSizeA8);
19567 // Store the new overflow address.
19568 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19573 .addOperand(Segment)
19574 .addReg(NextAddrReg)
19575 .setMemRefs(MMOBegin, MMOEnd);
19577 // If we branched, emit the PHI to the front of endMBB.
19579 BuildMI(*endMBB, endMBB->begin(), DL,
19580 TII->get(X86::PHI), DestReg)
19581 .addReg(OffsetDestReg).addMBB(offsetMBB)
19582 .addReg(OverflowDestReg).addMBB(overflowMBB);
19585 // Erase the pseudo instruction
19586 MI->eraseFromParent();
19591 MachineBasicBlock *
19592 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19594 MachineBasicBlock *MBB) const {
19595 // Emit code to save XMM registers to the stack. The ABI says that the
19596 // number of registers to save is given in %al, so it's theoretically
19597 // possible to do an indirect jump trick to avoid saving all of them,
19598 // however this code takes a simpler approach and just executes all
19599 // of the stores if %al is non-zero. It's less code, and it's probably
19600 // easier on the hardware branch predictor, and stores aren't all that
19601 // expensive anyway.
19603 // Create the new basic blocks. One block contains all the XMM stores,
19604 // and one block is the final destination regardless of whether any
19605 // stores were performed.
19606 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19607 MachineFunction *F = MBB->getParent();
19608 MachineFunction::iterator MBBIter = MBB;
19610 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19611 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19612 F->insert(MBBIter, XMMSaveMBB);
19613 F->insert(MBBIter, EndMBB);
19615 // Transfer the remainder of MBB and its successor edges to EndMBB.
19616 EndMBB->splice(EndMBB->begin(), MBB,
19617 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19618 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19620 // The original block will now fall through to the XMM save block.
19621 MBB->addSuccessor(XMMSaveMBB);
19622 // The XMMSaveMBB will fall through to the end block.
19623 XMMSaveMBB->addSuccessor(EndMBB);
19625 // Now add the instructions.
19626 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19627 DebugLoc DL = MI->getDebugLoc();
19629 unsigned CountReg = MI->getOperand(0).getReg();
19630 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19631 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19633 if (!Subtarget->isTargetWin64()) {
19634 // If %al is 0, branch around the XMM save block.
19635 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19636 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19637 MBB->addSuccessor(EndMBB);
19640 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19641 // that was just emitted, but clearly shouldn't be "saved".
19642 assert((MI->getNumOperands() <= 3 ||
19643 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19644 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19645 && "Expected last argument to be EFLAGS");
19646 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19647 // In the XMM save block, save all the XMM argument registers.
19648 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19649 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19650 MachineMemOperand *MMO =
19651 F->getMachineMemOperand(
19652 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19653 MachineMemOperand::MOStore,
19654 /*Size=*/16, /*Align=*/16);
19655 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19656 .addFrameIndex(RegSaveFrameIndex)
19657 .addImm(/*Scale=*/1)
19658 .addReg(/*IndexReg=*/0)
19659 .addImm(/*Disp=*/Offset)
19660 .addReg(/*Segment=*/0)
19661 .addReg(MI->getOperand(i).getReg())
19662 .addMemOperand(MMO);
19665 MI->eraseFromParent(); // The pseudo instruction is gone now.
19670 // The EFLAGS operand of SelectItr might be missing a kill marker
19671 // because there were multiple uses of EFLAGS, and ISel didn't know
19672 // which to mark. Figure out whether SelectItr should have had a
19673 // kill marker, and set it if it should. Returns the correct kill
19675 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19676 MachineBasicBlock* BB,
19677 const TargetRegisterInfo* TRI) {
19678 // Scan forward through BB for a use/def of EFLAGS.
19679 MachineBasicBlock::iterator miI(std::next(SelectItr));
19680 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19681 const MachineInstr& mi = *miI;
19682 if (mi.readsRegister(X86::EFLAGS))
19684 if (mi.definesRegister(X86::EFLAGS))
19685 break; // Should have kill-flag - update below.
19688 // If we hit the end of the block, check whether EFLAGS is live into a
19690 if (miI == BB->end()) {
19691 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19692 sEnd = BB->succ_end();
19693 sItr != sEnd; ++sItr) {
19694 MachineBasicBlock* succ = *sItr;
19695 if (succ->isLiveIn(X86::EFLAGS))
19700 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19701 // out. SelectMI should have a kill flag on EFLAGS.
19702 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19706 MachineBasicBlock *
19707 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19708 MachineBasicBlock *BB) const {
19709 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19710 DebugLoc DL = MI->getDebugLoc();
19712 // To "insert" a SELECT_CC instruction, we actually have to insert the
19713 // diamond control-flow pattern. The incoming instruction knows the
19714 // destination vreg to set, the condition code register to branch on, the
19715 // true/false values to select between, and a branch opcode to use.
19716 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19717 MachineFunction::iterator It = BB;
19723 // cmpTY ccX, r1, r2
19725 // fallthrough --> copy0MBB
19726 MachineBasicBlock *thisMBB = BB;
19727 MachineFunction *F = BB->getParent();
19728 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19729 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19730 F->insert(It, copy0MBB);
19731 F->insert(It, sinkMBB);
19733 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19734 // live into the sink and copy blocks.
19735 const TargetRegisterInfo *TRI =
19736 BB->getParent()->getSubtarget().getRegisterInfo();
19737 if (!MI->killsRegister(X86::EFLAGS) &&
19738 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19739 copy0MBB->addLiveIn(X86::EFLAGS);
19740 sinkMBB->addLiveIn(X86::EFLAGS);
19743 // Transfer the remainder of BB and its successor edges to sinkMBB.
19744 sinkMBB->splice(sinkMBB->begin(), BB,
19745 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19746 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19748 // Add the true and fallthrough blocks as its successors.
19749 BB->addSuccessor(copy0MBB);
19750 BB->addSuccessor(sinkMBB);
19752 // Create the conditional branch instruction.
19754 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19755 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19758 // %FalseValue = ...
19759 // # fallthrough to sinkMBB
19760 copy0MBB->addSuccessor(sinkMBB);
19763 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19765 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19766 TII->get(X86::PHI), MI->getOperand(0).getReg())
19767 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19768 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19770 MI->eraseFromParent(); // The pseudo instruction is gone now.
19774 MachineBasicBlock *
19775 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19776 MachineBasicBlock *BB) const {
19777 MachineFunction *MF = BB->getParent();
19778 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19779 DebugLoc DL = MI->getDebugLoc();
19780 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19782 assert(MF->shouldSplitStack());
19784 const bool Is64Bit = Subtarget->is64Bit();
19785 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19787 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19788 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19791 // ... [Till the alloca]
19792 // If stacklet is not large enough, jump to mallocMBB
19795 // Allocate by subtracting from RSP
19796 // Jump to continueMBB
19799 // Allocate by call to runtime
19803 // [rest of original BB]
19806 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19807 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19808 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19810 MachineRegisterInfo &MRI = MF->getRegInfo();
19811 const TargetRegisterClass *AddrRegClass =
19812 getRegClassFor(getPointerTy());
19814 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19815 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19816 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19817 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19818 sizeVReg = MI->getOperand(1).getReg(),
19819 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19821 MachineFunction::iterator MBBIter = BB;
19824 MF->insert(MBBIter, bumpMBB);
19825 MF->insert(MBBIter, mallocMBB);
19826 MF->insert(MBBIter, continueMBB);
19828 continueMBB->splice(continueMBB->begin(), BB,
19829 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19830 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19832 // Add code to the main basic block to check if the stack limit has been hit,
19833 // and if so, jump to mallocMBB otherwise to bumpMBB.
19834 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19835 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19836 .addReg(tmpSPVReg).addReg(sizeVReg);
19837 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19838 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19839 .addReg(SPLimitVReg);
19840 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19842 // bumpMBB simply decreases the stack pointer, since we know the current
19843 // stacklet has enough space.
19844 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19845 .addReg(SPLimitVReg);
19846 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19847 .addReg(SPLimitVReg);
19848 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19850 // Calls into a routine in libgcc to allocate more space from the heap.
19851 const uint32_t *RegMask = MF->getTarget()
19852 .getSubtargetImpl()
19853 ->getRegisterInfo()
19854 ->getCallPreservedMask(CallingConv::C);
19856 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19858 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19859 .addExternalSymbol("__morestack_allocate_stack_space")
19860 .addRegMask(RegMask)
19861 .addReg(X86::RDI, RegState::Implicit)
19862 .addReg(X86::RAX, RegState::ImplicitDefine);
19863 } else if (Is64Bit) {
19864 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19866 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19867 .addExternalSymbol("__morestack_allocate_stack_space")
19868 .addRegMask(RegMask)
19869 .addReg(X86::EDI, RegState::Implicit)
19870 .addReg(X86::EAX, RegState::ImplicitDefine);
19872 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19874 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19875 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19876 .addExternalSymbol("__morestack_allocate_stack_space")
19877 .addRegMask(RegMask)
19878 .addReg(X86::EAX, RegState::ImplicitDefine);
19882 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19885 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19886 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19887 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19889 // Set up the CFG correctly.
19890 BB->addSuccessor(bumpMBB);
19891 BB->addSuccessor(mallocMBB);
19892 mallocMBB->addSuccessor(continueMBB);
19893 bumpMBB->addSuccessor(continueMBB);
19895 // Take care of the PHI nodes.
19896 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19897 MI->getOperand(0).getReg())
19898 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19899 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19901 // Delete the original pseudo instruction.
19902 MI->eraseFromParent();
19905 return continueMBB;
19908 MachineBasicBlock *
19909 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19910 MachineBasicBlock *BB) const {
19911 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19912 DebugLoc DL = MI->getDebugLoc();
19914 assert(!Subtarget->isTargetMacho());
19916 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19917 // non-trivial part is impdef of ESP.
19919 if (Subtarget->isTargetWin64()) {
19920 if (Subtarget->isTargetCygMing()) {
19921 // ___chkstk(Mingw64):
19922 // Clobbers R10, R11, RAX and EFLAGS.
19924 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19925 .addExternalSymbol("___chkstk")
19926 .addReg(X86::RAX, RegState::Implicit)
19927 .addReg(X86::RSP, RegState::Implicit)
19928 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19929 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19930 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19932 // __chkstk(MSVCRT): does not update stack pointer.
19933 // Clobbers R10, R11 and EFLAGS.
19934 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19935 .addExternalSymbol("__chkstk")
19936 .addReg(X86::RAX, RegState::Implicit)
19937 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19938 // RAX has the offset to be subtracted from RSP.
19939 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19944 const char *StackProbeSymbol =
19945 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19947 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19948 .addExternalSymbol(StackProbeSymbol)
19949 .addReg(X86::EAX, RegState::Implicit)
19950 .addReg(X86::ESP, RegState::Implicit)
19951 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19952 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19953 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19956 MI->eraseFromParent(); // The pseudo instruction is gone now.
19960 MachineBasicBlock *
19961 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19962 MachineBasicBlock *BB) const {
19963 // This is pretty easy. We're taking the value that we received from
19964 // our load from the relocation, sticking it in either RDI (x86-64)
19965 // or EAX and doing an indirect call. The return value will then
19966 // be in the normal return register.
19967 MachineFunction *F = BB->getParent();
19968 const X86InstrInfo *TII =
19969 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19970 DebugLoc DL = MI->getDebugLoc();
19972 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19973 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19975 // Get a register mask for the lowered call.
19976 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19977 // proper register mask.
19978 const uint32_t *RegMask = F->getTarget()
19979 .getSubtargetImpl()
19980 ->getRegisterInfo()
19981 ->getCallPreservedMask(CallingConv::C);
19982 if (Subtarget->is64Bit()) {
19983 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19984 TII->get(X86::MOV64rm), X86::RDI)
19986 .addImm(0).addReg(0)
19987 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19988 MI->getOperand(3).getTargetFlags())
19990 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19991 addDirectMem(MIB, X86::RDI);
19992 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19993 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19994 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19995 TII->get(X86::MOV32rm), X86::EAX)
19997 .addImm(0).addReg(0)
19998 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19999 MI->getOperand(3).getTargetFlags())
20001 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20002 addDirectMem(MIB, X86::EAX);
20003 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20005 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20006 TII->get(X86::MOV32rm), X86::EAX)
20007 .addReg(TII->getGlobalBaseReg(F))
20008 .addImm(0).addReg(0)
20009 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20010 MI->getOperand(3).getTargetFlags())
20012 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20013 addDirectMem(MIB, X86::EAX);
20014 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20017 MI->eraseFromParent(); // The pseudo instruction is gone now.
20021 MachineBasicBlock *
20022 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20023 MachineBasicBlock *MBB) const {
20024 DebugLoc DL = MI->getDebugLoc();
20025 MachineFunction *MF = MBB->getParent();
20026 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20027 MachineRegisterInfo &MRI = MF->getRegInfo();
20029 const BasicBlock *BB = MBB->getBasicBlock();
20030 MachineFunction::iterator I = MBB;
20033 // Memory Reference
20034 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20035 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20038 unsigned MemOpndSlot = 0;
20040 unsigned CurOp = 0;
20042 DstReg = MI->getOperand(CurOp++).getReg();
20043 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20044 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20045 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20046 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20048 MemOpndSlot = CurOp;
20050 MVT PVT = getPointerTy();
20051 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20052 "Invalid Pointer Size!");
20054 // For v = setjmp(buf), we generate
20057 // buf[LabelOffset] = restoreMBB
20058 // SjLjSetup restoreMBB
20064 // v = phi(main, restore)
20069 MachineBasicBlock *thisMBB = MBB;
20070 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20071 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20072 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20073 MF->insert(I, mainMBB);
20074 MF->insert(I, sinkMBB);
20075 MF->push_back(restoreMBB);
20077 MachineInstrBuilder MIB;
20079 // Transfer the remainder of BB and its successor edges to sinkMBB.
20080 sinkMBB->splice(sinkMBB->begin(), MBB,
20081 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20082 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20085 unsigned PtrStoreOpc = 0;
20086 unsigned LabelReg = 0;
20087 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20088 Reloc::Model RM = MF->getTarget().getRelocationModel();
20089 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20090 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20092 // Prepare IP either in reg or imm.
20093 if (!UseImmLabel) {
20094 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20095 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20096 LabelReg = MRI.createVirtualRegister(PtrRC);
20097 if (Subtarget->is64Bit()) {
20098 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20102 .addMBB(restoreMBB)
20105 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20107 .addReg(XII->getGlobalBaseReg(MF))
20110 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20114 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20116 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20117 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20118 if (i == X86::AddrDisp)
20119 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20121 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20124 MIB.addReg(LabelReg);
20126 MIB.addMBB(restoreMBB);
20127 MIB.setMemRefs(MMOBegin, MMOEnd);
20129 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20130 .addMBB(restoreMBB);
20132 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20133 MF->getSubtarget().getRegisterInfo());
20134 MIB.addRegMask(RegInfo->getNoPreservedMask());
20135 thisMBB->addSuccessor(mainMBB);
20136 thisMBB->addSuccessor(restoreMBB);
20140 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20141 mainMBB->addSuccessor(sinkMBB);
20144 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20145 TII->get(X86::PHI), DstReg)
20146 .addReg(mainDstReg).addMBB(mainMBB)
20147 .addReg(restoreDstReg).addMBB(restoreMBB);
20150 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20151 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20152 restoreMBB->addSuccessor(sinkMBB);
20154 MI->eraseFromParent();
20158 MachineBasicBlock *
20159 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20160 MachineBasicBlock *MBB) const {
20161 DebugLoc DL = MI->getDebugLoc();
20162 MachineFunction *MF = MBB->getParent();
20163 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20164 MachineRegisterInfo &MRI = MF->getRegInfo();
20166 // Memory Reference
20167 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20168 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20170 MVT PVT = getPointerTy();
20171 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20172 "Invalid Pointer Size!");
20174 const TargetRegisterClass *RC =
20175 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20176 unsigned Tmp = MRI.createVirtualRegister(RC);
20177 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20178 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20179 MF->getSubtarget().getRegisterInfo());
20180 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20181 unsigned SP = RegInfo->getStackRegister();
20183 MachineInstrBuilder MIB;
20185 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20186 const int64_t SPOffset = 2 * PVT.getStoreSize();
20188 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20189 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20192 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20193 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20194 MIB.addOperand(MI->getOperand(i));
20195 MIB.setMemRefs(MMOBegin, MMOEnd);
20197 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20198 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20199 if (i == X86::AddrDisp)
20200 MIB.addDisp(MI->getOperand(i), LabelOffset);
20202 MIB.addOperand(MI->getOperand(i));
20204 MIB.setMemRefs(MMOBegin, MMOEnd);
20206 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20207 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20208 if (i == X86::AddrDisp)
20209 MIB.addDisp(MI->getOperand(i), SPOffset);
20211 MIB.addOperand(MI->getOperand(i));
20213 MIB.setMemRefs(MMOBegin, MMOEnd);
20215 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20217 MI->eraseFromParent();
20221 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20222 // accumulator loops. Writing back to the accumulator allows the coalescer
20223 // to remove extra copies in the loop.
20224 MachineBasicBlock *
20225 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20226 MachineBasicBlock *MBB) const {
20227 MachineOperand &AddendOp = MI->getOperand(3);
20229 // Bail out early if the addend isn't a register - we can't switch these.
20230 if (!AddendOp.isReg())
20233 MachineFunction &MF = *MBB->getParent();
20234 MachineRegisterInfo &MRI = MF.getRegInfo();
20236 // Check whether the addend is defined by a PHI:
20237 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20238 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20239 if (!AddendDef.isPHI())
20242 // Look for the following pattern:
20244 // %addend = phi [%entry, 0], [%loop, %result]
20246 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20250 // %addend = phi [%entry, 0], [%loop, %result]
20252 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20254 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20255 assert(AddendDef.getOperand(i).isReg());
20256 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20257 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20258 if (&PHISrcInst == MI) {
20259 // Found a matching instruction.
20260 unsigned NewFMAOpc = 0;
20261 switch (MI->getOpcode()) {
20262 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20263 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20264 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20265 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20266 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20267 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20268 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20269 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20270 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20271 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20272 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20273 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20274 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20275 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20276 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20277 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20278 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20279 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20280 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20281 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20282 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20283 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20284 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20285 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20286 default: llvm_unreachable("Unrecognized FMA variant.");
20289 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20290 MachineInstrBuilder MIB =
20291 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20292 .addOperand(MI->getOperand(0))
20293 .addOperand(MI->getOperand(3))
20294 .addOperand(MI->getOperand(2))
20295 .addOperand(MI->getOperand(1));
20296 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20297 MI->eraseFromParent();
20304 MachineBasicBlock *
20305 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20306 MachineBasicBlock *BB) const {
20307 switch (MI->getOpcode()) {
20308 default: llvm_unreachable("Unexpected instr type to insert");
20309 case X86::TAILJMPd64:
20310 case X86::TAILJMPr64:
20311 case X86::TAILJMPm64:
20312 llvm_unreachable("TAILJMP64 would not be touched here.");
20313 case X86::TCRETURNdi64:
20314 case X86::TCRETURNri64:
20315 case X86::TCRETURNmi64:
20317 case X86::WIN_ALLOCA:
20318 return EmitLoweredWinAlloca(MI, BB);
20319 case X86::SEG_ALLOCA_32:
20320 case X86::SEG_ALLOCA_64:
20321 return EmitLoweredSegAlloca(MI, BB);
20322 case X86::TLSCall_32:
20323 case X86::TLSCall_64:
20324 return EmitLoweredTLSCall(MI, BB);
20325 case X86::CMOV_GR8:
20326 case X86::CMOV_FR32:
20327 case X86::CMOV_FR64:
20328 case X86::CMOV_V4F32:
20329 case X86::CMOV_V2F64:
20330 case X86::CMOV_V2I64:
20331 case X86::CMOV_V8F32:
20332 case X86::CMOV_V4F64:
20333 case X86::CMOV_V4I64:
20334 case X86::CMOV_V16F32:
20335 case X86::CMOV_V8F64:
20336 case X86::CMOV_V8I64:
20337 case X86::CMOV_GR16:
20338 case X86::CMOV_GR32:
20339 case X86::CMOV_RFP32:
20340 case X86::CMOV_RFP64:
20341 case X86::CMOV_RFP80:
20342 return EmitLoweredSelect(MI, BB);
20344 case X86::FP32_TO_INT16_IN_MEM:
20345 case X86::FP32_TO_INT32_IN_MEM:
20346 case X86::FP32_TO_INT64_IN_MEM:
20347 case X86::FP64_TO_INT16_IN_MEM:
20348 case X86::FP64_TO_INT32_IN_MEM:
20349 case X86::FP64_TO_INT64_IN_MEM:
20350 case X86::FP80_TO_INT16_IN_MEM:
20351 case X86::FP80_TO_INT32_IN_MEM:
20352 case X86::FP80_TO_INT64_IN_MEM: {
20353 MachineFunction *F = BB->getParent();
20354 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20355 DebugLoc DL = MI->getDebugLoc();
20357 // Change the floating point control register to use "round towards zero"
20358 // mode when truncating to an integer value.
20359 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20360 addFrameReference(BuildMI(*BB, MI, DL,
20361 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20363 // Load the old value of the high byte of the control word...
20365 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20366 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20369 // Set the high part to be round to zero...
20370 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20373 // Reload the modified control word now...
20374 addFrameReference(BuildMI(*BB, MI, DL,
20375 TII->get(X86::FLDCW16m)), CWFrameIdx);
20377 // Restore the memory image of control word to original value
20378 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20381 // Get the X86 opcode to use.
20383 switch (MI->getOpcode()) {
20384 default: llvm_unreachable("illegal opcode!");
20385 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20386 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20387 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20388 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20389 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20390 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20391 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20392 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20393 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20397 MachineOperand &Op = MI->getOperand(0);
20399 AM.BaseType = X86AddressMode::RegBase;
20400 AM.Base.Reg = Op.getReg();
20402 AM.BaseType = X86AddressMode::FrameIndexBase;
20403 AM.Base.FrameIndex = Op.getIndex();
20405 Op = MI->getOperand(1);
20407 AM.Scale = Op.getImm();
20408 Op = MI->getOperand(2);
20410 AM.IndexReg = Op.getImm();
20411 Op = MI->getOperand(3);
20412 if (Op.isGlobal()) {
20413 AM.GV = Op.getGlobal();
20415 AM.Disp = Op.getImm();
20417 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20418 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20420 // Reload the original control word now.
20421 addFrameReference(BuildMI(*BB, MI, DL,
20422 TII->get(X86::FLDCW16m)), CWFrameIdx);
20424 MI->eraseFromParent(); // The pseudo instruction is gone now.
20427 // String/text processing lowering.
20428 case X86::PCMPISTRM128REG:
20429 case X86::VPCMPISTRM128REG:
20430 case X86::PCMPISTRM128MEM:
20431 case X86::VPCMPISTRM128MEM:
20432 case X86::PCMPESTRM128REG:
20433 case X86::VPCMPESTRM128REG:
20434 case X86::PCMPESTRM128MEM:
20435 case X86::VPCMPESTRM128MEM:
20436 assert(Subtarget->hasSSE42() &&
20437 "Target must have SSE4.2 or AVX features enabled");
20438 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20440 // String/text processing lowering.
20441 case X86::PCMPISTRIREG:
20442 case X86::VPCMPISTRIREG:
20443 case X86::PCMPISTRIMEM:
20444 case X86::VPCMPISTRIMEM:
20445 case X86::PCMPESTRIREG:
20446 case X86::VPCMPESTRIREG:
20447 case X86::PCMPESTRIMEM:
20448 case X86::VPCMPESTRIMEM:
20449 assert(Subtarget->hasSSE42() &&
20450 "Target must have SSE4.2 or AVX features enabled");
20451 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20453 // Thread synchronization.
20455 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20460 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20462 case X86::VASTART_SAVE_XMM_REGS:
20463 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20465 case X86::VAARG_64:
20466 return EmitVAARG64WithCustomInserter(MI, BB);
20468 case X86::EH_SjLj_SetJmp32:
20469 case X86::EH_SjLj_SetJmp64:
20470 return emitEHSjLjSetJmp(MI, BB);
20472 case X86::EH_SjLj_LongJmp32:
20473 case X86::EH_SjLj_LongJmp64:
20474 return emitEHSjLjLongJmp(MI, BB);
20476 case TargetOpcode::STACKMAP:
20477 case TargetOpcode::PATCHPOINT:
20478 return emitPatchPoint(MI, BB);
20480 case X86::VFMADDPDr213r:
20481 case X86::VFMADDPSr213r:
20482 case X86::VFMADDSDr213r:
20483 case X86::VFMADDSSr213r:
20484 case X86::VFMSUBPDr213r:
20485 case X86::VFMSUBPSr213r:
20486 case X86::VFMSUBSDr213r:
20487 case X86::VFMSUBSSr213r:
20488 case X86::VFNMADDPDr213r:
20489 case X86::VFNMADDPSr213r:
20490 case X86::VFNMADDSDr213r:
20491 case X86::VFNMADDSSr213r:
20492 case X86::VFNMSUBPDr213r:
20493 case X86::VFNMSUBPSr213r:
20494 case X86::VFNMSUBSDr213r:
20495 case X86::VFNMSUBSSr213r:
20496 case X86::VFMADDPDr213rY:
20497 case X86::VFMADDPSr213rY:
20498 case X86::VFMSUBPDr213rY:
20499 case X86::VFMSUBPSr213rY:
20500 case X86::VFNMADDPDr213rY:
20501 case X86::VFNMADDPSr213rY:
20502 case X86::VFNMSUBPDr213rY:
20503 case X86::VFNMSUBPSr213rY:
20504 return emitFMA3Instr(MI, BB);
20508 //===----------------------------------------------------------------------===//
20509 // X86 Optimization Hooks
20510 //===----------------------------------------------------------------------===//
20512 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20515 const SelectionDAG &DAG,
20516 unsigned Depth) const {
20517 unsigned BitWidth = KnownZero.getBitWidth();
20518 unsigned Opc = Op.getOpcode();
20519 assert((Opc >= ISD::BUILTIN_OP_END ||
20520 Opc == ISD::INTRINSIC_WO_CHAIN ||
20521 Opc == ISD::INTRINSIC_W_CHAIN ||
20522 Opc == ISD::INTRINSIC_VOID) &&
20523 "Should use MaskedValueIsZero if you don't know whether Op"
20524 " is a target node!");
20526 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20540 // These nodes' second result is a boolean.
20541 if (Op.getResNo() == 0)
20544 case X86ISD::SETCC:
20545 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20547 case ISD::INTRINSIC_WO_CHAIN: {
20548 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20549 unsigned NumLoBits = 0;
20552 case Intrinsic::x86_sse_movmsk_ps:
20553 case Intrinsic::x86_avx_movmsk_ps_256:
20554 case Intrinsic::x86_sse2_movmsk_pd:
20555 case Intrinsic::x86_avx_movmsk_pd_256:
20556 case Intrinsic::x86_mmx_pmovmskb:
20557 case Intrinsic::x86_sse2_pmovmskb_128:
20558 case Intrinsic::x86_avx2_pmovmskb: {
20559 // High bits of movmskp{s|d}, pmovmskb are known zero.
20561 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20562 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20563 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20564 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20565 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20566 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20567 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20568 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20570 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20579 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20581 const SelectionDAG &,
20582 unsigned Depth) const {
20583 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20584 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20585 return Op.getValueType().getScalarType().getSizeInBits();
20591 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20592 /// node is a GlobalAddress + offset.
20593 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20594 const GlobalValue* &GA,
20595 int64_t &Offset) const {
20596 if (N->getOpcode() == X86ISD::Wrapper) {
20597 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20598 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20599 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20603 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20606 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20607 /// same as extracting the high 128-bit part of 256-bit vector and then
20608 /// inserting the result into the low part of a new 256-bit vector
20609 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20610 EVT VT = SVOp->getValueType(0);
20611 unsigned NumElems = VT.getVectorNumElements();
20613 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20614 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20615 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20616 SVOp->getMaskElt(j) >= 0)
20622 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20623 /// same as extracting the low 128-bit part of 256-bit vector and then
20624 /// inserting the result into the high part of a new 256-bit vector
20625 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20626 EVT VT = SVOp->getValueType(0);
20627 unsigned NumElems = VT.getVectorNumElements();
20629 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20630 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20631 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20632 SVOp->getMaskElt(j) >= 0)
20638 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20639 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20640 TargetLowering::DAGCombinerInfo &DCI,
20641 const X86Subtarget* Subtarget) {
20643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20644 SDValue V1 = SVOp->getOperand(0);
20645 SDValue V2 = SVOp->getOperand(1);
20646 EVT VT = SVOp->getValueType(0);
20647 unsigned NumElems = VT.getVectorNumElements();
20649 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20650 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20654 // V UNDEF BUILD_VECTOR UNDEF
20656 // CONCAT_VECTOR CONCAT_VECTOR
20659 // RESULT: V + zero extended
20661 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20662 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20663 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20666 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20669 // To match the shuffle mask, the first half of the mask should
20670 // be exactly the first vector, and all the rest a splat with the
20671 // first element of the second one.
20672 for (unsigned i = 0; i != NumElems/2; ++i)
20673 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20674 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20677 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20678 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20679 if (Ld->hasNUsesOfValue(1, 0)) {
20680 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20681 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20683 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20685 Ld->getPointerInfo(),
20686 Ld->getAlignment(),
20687 false/*isVolatile*/, true/*ReadMem*/,
20688 false/*WriteMem*/);
20690 // Make sure the newly-created LOAD is in the same position as Ld in
20691 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20692 // and update uses of Ld's output chain to use the TokenFactor.
20693 if (Ld->hasAnyUseOfValue(1)) {
20694 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20695 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20696 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20697 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20698 SDValue(ResNode.getNode(), 1));
20701 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20705 // Emit a zeroed vector and insert the desired subvector on its
20707 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20708 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20709 return DCI.CombineTo(N, InsV);
20712 //===--------------------------------------------------------------------===//
20713 // Combine some shuffles into subvector extracts and inserts:
20716 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20717 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20718 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20719 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20720 return DCI.CombineTo(N, InsV);
20723 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20724 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20725 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20726 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20727 return DCI.CombineTo(N, InsV);
20733 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20736 /// This is the leaf of the recursive combinine below. When we have found some
20737 /// chain of single-use x86 shuffle instructions and accumulated the combined
20738 /// shuffle mask represented by them, this will try to pattern match that mask
20739 /// into either a single instruction if there is a special purpose instruction
20740 /// for this operation, or into a PSHUFB instruction which is a fully general
20741 /// instruction but should only be used to replace chains over a certain depth.
20742 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20743 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20744 TargetLowering::DAGCombinerInfo &DCI,
20745 const X86Subtarget *Subtarget) {
20746 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20748 // Find the operand that enters the chain. Note that multiple uses are OK
20749 // here, we're not going to remove the operand we find.
20750 SDValue Input = Op.getOperand(0);
20751 while (Input.getOpcode() == ISD::BITCAST)
20752 Input = Input.getOperand(0);
20754 MVT VT = Input.getSimpleValueType();
20755 MVT RootVT = Root.getSimpleValueType();
20758 // Just remove no-op shuffle masks.
20759 if (Mask.size() == 1) {
20760 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20765 // Use the float domain if the operand type is a floating point type.
20766 bool FloatDomain = VT.isFloatingPoint();
20768 // For floating point shuffles, we don't have free copies in the shuffle
20769 // instructions or the ability to load as part of the instruction, so
20770 // canonicalize their shuffles to UNPCK or MOV variants.
20772 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20773 // vectors because it can have a load folded into it that UNPCK cannot. This
20774 // doesn't preclude something switching to the shorter encoding post-RA.
20776 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20777 bool Lo = Mask.equals(0, 0);
20780 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20781 // is no slower than UNPCKLPD but has the option to fold the input operand
20782 // into even an unaligned memory load.
20783 if (Lo && Subtarget->hasSSE3()) {
20784 Shuffle = X86ISD::MOVDDUP;
20785 ShuffleVT = MVT::v2f64;
20787 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20788 // than the UNPCK variants.
20789 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20790 ShuffleVT = MVT::v4f32;
20792 if (Depth == 1 && Root->getOpcode() == Shuffle)
20793 return false; // Nothing to do!
20794 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20795 DCI.AddToWorklist(Op.getNode());
20796 if (Shuffle == X86ISD::MOVDDUP)
20797 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20799 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20800 DCI.AddToWorklist(Op.getNode());
20801 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20805 if (Subtarget->hasSSE3() &&
20806 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20807 bool Lo = Mask.equals(0, 0, 2, 2);
20808 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20809 MVT ShuffleVT = MVT::v4f32;
20810 if (Depth == 1 && Root->getOpcode() == Shuffle)
20811 return false; // Nothing to do!
20812 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20813 DCI.AddToWorklist(Op.getNode());
20814 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20815 DCI.AddToWorklist(Op.getNode());
20816 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20820 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20821 bool Lo = Mask.equals(0, 0, 1, 1);
20822 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20823 MVT ShuffleVT = MVT::v4f32;
20824 if (Depth == 1 && Root->getOpcode() == Shuffle)
20825 return false; // Nothing to do!
20826 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20827 DCI.AddToWorklist(Op.getNode());
20828 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20829 DCI.AddToWorklist(Op.getNode());
20830 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20836 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20837 // variants as none of these have single-instruction variants that are
20838 // superior to the UNPCK formulation.
20839 if (!FloatDomain &&
20840 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20841 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20842 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20843 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20845 bool Lo = Mask[0] == 0;
20846 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20847 if (Depth == 1 && Root->getOpcode() == Shuffle)
20848 return false; // Nothing to do!
20850 switch (Mask.size()) {
20852 ShuffleVT = MVT::v8i16;
20855 ShuffleVT = MVT::v16i8;
20858 llvm_unreachable("Impossible mask size!");
20860 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20861 DCI.AddToWorklist(Op.getNode());
20862 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20863 DCI.AddToWorklist(Op.getNode());
20864 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20869 // Don't try to re-form single instruction chains under any circumstances now
20870 // that we've done encoding canonicalization for them.
20874 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20875 // can replace them with a single PSHUFB instruction profitably. Intel's
20876 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20877 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20878 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20879 SmallVector<SDValue, 16> PSHUFBMask;
20880 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20881 int Ratio = 16 / Mask.size();
20882 for (unsigned i = 0; i < 16; ++i) {
20883 if (Mask[i / Ratio] == SM_SentinelUndef) {
20884 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20887 int M = Mask[i / Ratio] != SM_SentinelZero
20888 ? Ratio * Mask[i / Ratio] + i % Ratio
20890 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20892 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20893 DCI.AddToWorklist(Op.getNode());
20894 SDValue PSHUFBMaskOp =
20895 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20896 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20897 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20898 DCI.AddToWorklist(Op.getNode());
20899 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20904 // Failed to find any combines.
20908 /// \brief Fully generic combining of x86 shuffle instructions.
20910 /// This should be the last combine run over the x86 shuffle instructions. Once
20911 /// they have been fully optimized, this will recursively consider all chains
20912 /// of single-use shuffle instructions, build a generic model of the cumulative
20913 /// shuffle operation, and check for simpler instructions which implement this
20914 /// operation. We use this primarily for two purposes:
20916 /// 1) Collapse generic shuffles to specialized single instructions when
20917 /// equivalent. In most cases, this is just an encoding size win, but
20918 /// sometimes we will collapse multiple generic shuffles into a single
20919 /// special-purpose shuffle.
20920 /// 2) Look for sequences of shuffle instructions with 3 or more total
20921 /// instructions, and replace them with the slightly more expensive SSSE3
20922 /// PSHUFB instruction if available. We do this as the last combining step
20923 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20924 /// a suitable short sequence of other instructions. The PHUFB will either
20925 /// use a register or have to read from memory and so is slightly (but only
20926 /// slightly) more expensive than the other shuffle instructions.
20928 /// Because this is inherently a quadratic operation (for each shuffle in
20929 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20930 /// This should never be an issue in practice as the shuffle lowering doesn't
20931 /// produce sequences of more than 8 instructions.
20933 /// FIXME: We will currently miss some cases where the redundant shuffling
20934 /// would simplify under the threshold for PSHUFB formation because of
20935 /// combine-ordering. To fix this, we should do the redundant instruction
20936 /// combining in this recursive walk.
20937 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20938 ArrayRef<int> RootMask,
20939 int Depth, bool HasPSHUFB,
20941 TargetLowering::DAGCombinerInfo &DCI,
20942 const X86Subtarget *Subtarget) {
20943 // Bound the depth of our recursive combine because this is ultimately
20944 // quadratic in nature.
20948 // Directly rip through bitcasts to find the underlying operand.
20949 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20950 Op = Op.getOperand(0);
20952 MVT VT = Op.getSimpleValueType();
20953 if (!VT.isVector())
20954 return false; // Bail if we hit a non-vector.
20955 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20956 // version should be added.
20957 if (VT.getSizeInBits() != 128)
20960 assert(Root.getSimpleValueType().isVector() &&
20961 "Shuffles operate on vector types!");
20962 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20963 "Can only combine shuffles of the same vector register size.");
20965 if (!isTargetShuffle(Op.getOpcode()))
20967 SmallVector<int, 16> OpMask;
20969 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20970 // We only can combine unary shuffles which we can decode the mask for.
20971 if (!HaveMask || !IsUnary)
20974 assert(VT.getVectorNumElements() == OpMask.size() &&
20975 "Different mask size from vector size!");
20976 assert(((RootMask.size() > OpMask.size() &&
20977 RootMask.size() % OpMask.size() == 0) ||
20978 (OpMask.size() > RootMask.size() &&
20979 OpMask.size() % RootMask.size() == 0) ||
20980 OpMask.size() == RootMask.size()) &&
20981 "The smaller number of elements must divide the larger.");
20982 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20983 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20984 assert(((RootRatio == 1 && OpRatio == 1) ||
20985 (RootRatio == 1) != (OpRatio == 1)) &&
20986 "Must not have a ratio for both incoming and op masks!");
20988 SmallVector<int, 16> Mask;
20989 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20991 // Merge this shuffle operation's mask into our accumulated mask. Note that
20992 // this shuffle's mask will be the first applied to the input, followed by the
20993 // root mask to get us all the way to the root value arrangement. The reason
20994 // for this order is that we are recursing up the operation chain.
20995 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20996 int RootIdx = i / RootRatio;
20997 if (RootMask[RootIdx] < 0) {
20998 // This is a zero or undef lane, we're done.
20999 Mask.push_back(RootMask[RootIdx]);
21003 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21004 int OpIdx = RootMaskedIdx / OpRatio;
21005 if (OpMask[OpIdx] < 0) {
21006 // The incoming lanes are zero or undef, it doesn't matter which ones we
21008 Mask.push_back(OpMask[OpIdx]);
21012 // Ok, we have non-zero lanes, map them through.
21013 Mask.push_back(OpMask[OpIdx] * OpRatio +
21014 RootMaskedIdx % OpRatio);
21017 // See if we can recurse into the operand to combine more things.
21018 switch (Op.getOpcode()) {
21019 case X86ISD::PSHUFB:
21021 case X86ISD::PSHUFD:
21022 case X86ISD::PSHUFHW:
21023 case X86ISD::PSHUFLW:
21024 if (Op.getOperand(0).hasOneUse() &&
21025 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21026 HasPSHUFB, DAG, DCI, Subtarget))
21030 case X86ISD::UNPCKL:
21031 case X86ISD::UNPCKH:
21032 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21033 // We can't check for single use, we have to check that this shuffle is the only user.
21034 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21035 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21036 HasPSHUFB, DAG, DCI, Subtarget))
21041 // Minor canonicalization of the accumulated shuffle mask to make it easier
21042 // to match below. All this does is detect masks with squential pairs of
21043 // elements, and shrink them to the half-width mask. It does this in a loop
21044 // so it will reduce the size of the mask to the minimal width mask which
21045 // performs an equivalent shuffle.
21046 SmallVector<int, 16> WidenedMask;
21047 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21048 Mask = std::move(WidenedMask);
21049 WidenedMask.clear();
21052 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21056 /// \brief Get the PSHUF-style mask from PSHUF node.
21058 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21059 /// PSHUF-style masks that can be reused with such instructions.
21060 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21061 SmallVector<int, 4> Mask;
21063 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21067 switch (N.getOpcode()) {
21068 case X86ISD::PSHUFD:
21070 case X86ISD::PSHUFLW:
21073 case X86ISD::PSHUFHW:
21074 Mask.erase(Mask.begin(), Mask.begin() + 4);
21075 for (int &M : Mask)
21079 llvm_unreachable("No valid shuffle instruction found!");
21083 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21085 /// We walk up the chain and look for a combinable shuffle, skipping over
21086 /// shuffles that we could hoist this shuffle's transformation past without
21087 /// altering anything.
21089 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21091 TargetLowering::DAGCombinerInfo &DCI) {
21092 assert(N.getOpcode() == X86ISD::PSHUFD &&
21093 "Called with something other than an x86 128-bit half shuffle!");
21096 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21097 // of the shuffles in the chain so that we can form a fresh chain to replace
21099 SmallVector<SDValue, 8> Chain;
21100 SDValue V = N.getOperand(0);
21101 for (; V.hasOneUse(); V = V.getOperand(0)) {
21102 switch (V.getOpcode()) {
21104 return SDValue(); // Nothing combined!
21107 // Skip bitcasts as we always know the type for the target specific
21111 case X86ISD::PSHUFD:
21112 // Found another dword shuffle.
21115 case X86ISD::PSHUFLW:
21116 // Check that the low words (being shuffled) are the identity in the
21117 // dword shuffle, and the high words are self-contained.
21118 if (Mask[0] != 0 || Mask[1] != 1 ||
21119 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21122 Chain.push_back(V);
21125 case X86ISD::PSHUFHW:
21126 // Check that the high words (being shuffled) are the identity in the
21127 // dword shuffle, and the low words are self-contained.
21128 if (Mask[2] != 2 || Mask[3] != 3 ||
21129 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21132 Chain.push_back(V);
21135 case X86ISD::UNPCKL:
21136 case X86ISD::UNPCKH:
21137 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21138 // shuffle into a preceding word shuffle.
21139 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21142 // Search for a half-shuffle which we can combine with.
21143 unsigned CombineOp =
21144 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21145 if (V.getOperand(0) != V.getOperand(1) ||
21146 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21148 Chain.push_back(V);
21149 V = V.getOperand(0);
21151 switch (V.getOpcode()) {
21153 return SDValue(); // Nothing to combine.
21155 case X86ISD::PSHUFLW:
21156 case X86ISD::PSHUFHW:
21157 if (V.getOpcode() == CombineOp)
21160 Chain.push_back(V);
21164 V = V.getOperand(0);
21168 } while (V.hasOneUse());
21171 // Break out of the loop if we break out of the switch.
21175 if (!V.hasOneUse())
21176 // We fell out of the loop without finding a viable combining instruction.
21179 // Merge this node's mask and our incoming mask.
21180 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21181 for (int &M : Mask)
21183 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21184 getV4X86ShuffleImm8ForMask(Mask, DAG));
21186 // Rebuild the chain around this new shuffle.
21187 while (!Chain.empty()) {
21188 SDValue W = Chain.pop_back_val();
21190 if (V.getValueType() != W.getOperand(0).getValueType())
21191 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21193 switch (W.getOpcode()) {
21195 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21197 case X86ISD::UNPCKL:
21198 case X86ISD::UNPCKH:
21199 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21202 case X86ISD::PSHUFD:
21203 case X86ISD::PSHUFLW:
21204 case X86ISD::PSHUFHW:
21205 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21209 if (V.getValueType() != N.getValueType())
21210 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21212 // Return the new chain to replace N.
21216 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21218 /// We walk up the chain, skipping shuffles of the other half and looking
21219 /// through shuffles which switch halves trying to find a shuffle of the same
21220 /// pair of dwords.
21221 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21223 TargetLowering::DAGCombinerInfo &DCI) {
21225 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21226 "Called with something other than an x86 128-bit half shuffle!");
21228 unsigned CombineOpcode = N.getOpcode();
21230 // Walk up a single-use chain looking for a combinable shuffle.
21231 SDValue V = N.getOperand(0);
21232 for (; V.hasOneUse(); V = V.getOperand(0)) {
21233 switch (V.getOpcode()) {
21235 return false; // Nothing combined!
21238 // Skip bitcasts as we always know the type for the target specific
21242 case X86ISD::PSHUFLW:
21243 case X86ISD::PSHUFHW:
21244 if (V.getOpcode() == CombineOpcode)
21247 // Other-half shuffles are no-ops.
21250 // Break out of the loop if we break out of the switch.
21254 if (!V.hasOneUse())
21255 // We fell out of the loop without finding a viable combining instruction.
21258 // Combine away the bottom node as its shuffle will be accumulated into
21259 // a preceding shuffle.
21260 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21262 // Record the old value.
21265 // Merge this node's mask and our incoming mask (adjusted to account for all
21266 // the pshufd instructions encountered).
21267 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21268 for (int &M : Mask)
21270 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21271 getV4X86ShuffleImm8ForMask(Mask, DAG));
21273 // Check that the shuffles didn't cancel each other out. If not, we need to
21274 // combine to the new one.
21276 // Replace the combinable shuffle with the combined one, updating all users
21277 // so that we re-evaluate the chain here.
21278 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21283 /// \brief Try to combine x86 target specific shuffles.
21284 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21285 TargetLowering::DAGCombinerInfo &DCI,
21286 const X86Subtarget *Subtarget) {
21288 MVT VT = N.getSimpleValueType();
21289 SmallVector<int, 4> Mask;
21291 switch (N.getOpcode()) {
21292 case X86ISD::PSHUFD:
21293 case X86ISD::PSHUFLW:
21294 case X86ISD::PSHUFHW:
21295 Mask = getPSHUFShuffleMask(N);
21296 assert(Mask.size() == 4);
21302 // Nuke no-op shuffles that show up after combining.
21303 if (isNoopShuffleMask(Mask))
21304 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21306 // Look for simplifications involving one or two shuffle instructions.
21307 SDValue V = N.getOperand(0);
21308 switch (N.getOpcode()) {
21311 case X86ISD::PSHUFLW:
21312 case X86ISD::PSHUFHW:
21313 assert(VT == MVT::v8i16);
21316 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21317 return SDValue(); // We combined away this shuffle, so we're done.
21319 // See if this reduces to a PSHUFD which is no more expensive and can
21320 // combine with more operations. Note that it has to at least flip the
21321 // dwords as otherwise it would have been removed as a no-op.
21322 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21323 int DMask[] = {0, 1, 2, 3};
21324 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21325 DMask[DOffset + 0] = DOffset + 1;
21326 DMask[DOffset + 1] = DOffset + 0;
21327 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21328 DCI.AddToWorklist(V.getNode());
21329 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21330 getV4X86ShuffleImm8ForMask(DMask, DAG));
21331 DCI.AddToWorklist(V.getNode());
21332 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21335 // Look for shuffle patterns which can be implemented as a single unpack.
21336 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21337 // only works when we have a PSHUFD followed by two half-shuffles.
21338 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21339 (V.getOpcode() == X86ISD::PSHUFLW ||
21340 V.getOpcode() == X86ISD::PSHUFHW) &&
21341 V.getOpcode() != N.getOpcode() &&
21343 SDValue D = V.getOperand(0);
21344 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21345 D = D.getOperand(0);
21346 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21347 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21348 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21349 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21350 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21352 for (int i = 0; i < 4; ++i) {
21353 WordMask[i + NOffset] = Mask[i] + NOffset;
21354 WordMask[i + VOffset] = VMask[i] + VOffset;
21356 // Map the word mask through the DWord mask.
21358 for (int i = 0; i < 8; ++i)
21359 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21360 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21361 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21362 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21363 std::begin(UnpackLoMask)) ||
21364 std::equal(std::begin(MappedMask), std::end(MappedMask),
21365 std::begin(UnpackHiMask))) {
21366 // We can replace all three shuffles with an unpack.
21367 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21368 DCI.AddToWorklist(V.getNode());
21369 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21371 DL, MVT::v8i16, V, V);
21378 case X86ISD::PSHUFD:
21379 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21388 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21390 /// We combine this directly on the abstract vector shuffle nodes so it is
21391 /// easier to generically match. We also insert dummy vector shuffle nodes for
21392 /// the operands which explicitly discard the lanes which are unused by this
21393 /// operation to try to flow through the rest of the combiner the fact that
21394 /// they're unused.
21395 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21397 EVT VT = N->getValueType(0);
21399 // We only handle target-independent shuffles.
21400 // FIXME: It would be easy and harmless to use the target shuffle mask
21401 // extraction tool to support more.
21402 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21405 auto *SVN = cast<ShuffleVectorSDNode>(N);
21406 ArrayRef<int> Mask = SVN->getMask();
21407 SDValue V1 = N->getOperand(0);
21408 SDValue V2 = N->getOperand(1);
21410 // We require the first shuffle operand to be the SUB node, and the second to
21411 // be the ADD node.
21412 // FIXME: We should support the commuted patterns.
21413 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21416 // If there are other uses of these operations we can't fold them.
21417 if (!V1->hasOneUse() || !V2->hasOneUse())
21420 // Ensure that both operations have the same operands. Note that we can
21421 // commute the FADD operands.
21422 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21423 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21424 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21427 // We're looking for blends between FADD and FSUB nodes. We insist on these
21428 // nodes being lined up in a specific expected pattern.
21429 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21430 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21431 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21434 // Only specific types are legal at this point, assert so we notice if and
21435 // when these change.
21436 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21437 VT == MVT::v4f64) &&
21438 "Unknown vector type encountered!");
21440 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21443 /// PerformShuffleCombine - Performs several different shuffle combines.
21444 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21445 TargetLowering::DAGCombinerInfo &DCI,
21446 const X86Subtarget *Subtarget) {
21448 SDValue N0 = N->getOperand(0);
21449 SDValue N1 = N->getOperand(1);
21450 EVT VT = N->getValueType(0);
21452 // Don't create instructions with illegal types after legalize types has run.
21453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21454 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21457 // If we have legalized the vector types, look for blends of FADD and FSUB
21458 // nodes that we can fuse into an ADDSUB node.
21459 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21460 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21463 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21464 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21465 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21466 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21468 // During Type Legalization, when promoting illegal vector types,
21469 // the backend might introduce new shuffle dag nodes and bitcasts.
21471 // This code performs the following transformation:
21472 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21473 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21475 // We do this only if both the bitcast and the BINOP dag nodes have
21476 // one use. Also, perform this transformation only if the new binary
21477 // operation is legal. This is to avoid introducing dag nodes that
21478 // potentially need to be further expanded (or custom lowered) into a
21479 // less optimal sequence of dag nodes.
21480 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21481 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21482 N0.getOpcode() == ISD::BITCAST) {
21483 SDValue BC0 = N0.getOperand(0);
21484 EVT SVT = BC0.getValueType();
21485 unsigned Opcode = BC0.getOpcode();
21486 unsigned NumElts = VT.getVectorNumElements();
21488 if (BC0.hasOneUse() && SVT.isVector() &&
21489 SVT.getVectorNumElements() * 2 == NumElts &&
21490 TLI.isOperationLegal(Opcode, VT)) {
21491 bool CanFold = false;
21503 unsigned SVTNumElts = SVT.getVectorNumElements();
21504 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21505 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21506 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21507 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21508 CanFold = SVOp->getMaskElt(i) < 0;
21511 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21512 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21513 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21514 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21519 // Only handle 128 wide vector from here on.
21520 if (!VT.is128BitVector())
21523 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21524 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21525 // consecutive, non-overlapping, and in the right order.
21526 SmallVector<SDValue, 16> Elts;
21527 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21528 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21530 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21534 if (isTargetShuffle(N->getOpcode())) {
21536 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21537 if (Shuffle.getNode())
21540 // Try recursively combining arbitrary sequences of x86 shuffle
21541 // instructions into higher-order shuffles. We do this after combining
21542 // specific PSHUF instruction sequences into their minimal form so that we
21543 // can evaluate how many specialized shuffle instructions are involved in
21544 // a particular chain.
21545 SmallVector<int, 1> NonceMask; // Just a placeholder.
21546 NonceMask.push_back(0);
21547 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21548 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21550 return SDValue(); // This routine will use CombineTo to replace N.
21556 /// PerformTruncateCombine - Converts truncate operation to
21557 /// a sequence of vector shuffle operations.
21558 /// It is possible when we truncate 256-bit vector to 128-bit vector
21559 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21560 TargetLowering::DAGCombinerInfo &DCI,
21561 const X86Subtarget *Subtarget) {
21565 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21566 /// specific shuffle of a load can be folded into a single element load.
21567 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21568 /// shuffles have been customed lowered so we need to handle those here.
21569 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21570 TargetLowering::DAGCombinerInfo &DCI) {
21571 if (DCI.isBeforeLegalizeOps())
21574 SDValue InVec = N->getOperand(0);
21575 SDValue EltNo = N->getOperand(1);
21577 if (!isa<ConstantSDNode>(EltNo))
21580 EVT VT = InVec.getValueType();
21582 if (InVec.getOpcode() == ISD::BITCAST) {
21583 // Don't duplicate a load with other uses.
21584 if (!InVec.hasOneUse())
21586 EVT BCVT = InVec.getOperand(0).getValueType();
21587 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21589 InVec = InVec.getOperand(0);
21592 if (!isTargetShuffle(InVec.getOpcode()))
21595 // Don't duplicate a load with other uses.
21596 if (!InVec.hasOneUse())
21599 SmallVector<int, 16> ShuffleMask;
21601 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21605 // Select the input vector, guarding against out of range extract vector.
21606 unsigned NumElems = VT.getVectorNumElements();
21607 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21608 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21609 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21610 : InVec.getOperand(1);
21612 // If inputs to shuffle are the same for both ops, then allow 2 uses
21613 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21615 if (LdNode.getOpcode() == ISD::BITCAST) {
21616 // Don't duplicate a load with other uses.
21617 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21620 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21621 LdNode = LdNode.getOperand(0);
21624 if (!ISD::isNormalLoad(LdNode.getNode()))
21627 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21629 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21632 EVT EltVT = N->getValueType(0);
21633 // If there's a bitcast before the shuffle, check if the load type and
21634 // alignment is valid.
21635 unsigned Align = LN0->getAlignment();
21636 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21637 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21638 EltVT.getTypeForEVT(*DAG.getContext()));
21640 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21643 // All checks match so transform back to vector_shuffle so that DAG combiner
21644 // can finish the job
21647 // Create shuffle node taking into account the case that its a unary shuffle
21648 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21649 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21650 InVec.getOperand(0), Shuffle,
21652 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21653 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21657 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21658 /// generation and convert it from being a bunch of shuffles and extracts
21659 /// to a simple store and scalar loads to extract the elements.
21660 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21661 TargetLowering::DAGCombinerInfo &DCI) {
21662 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21663 if (NewOp.getNode())
21666 SDValue InputVector = N->getOperand(0);
21668 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21669 // from mmx to v2i32 has a single usage.
21670 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21671 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21672 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21673 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21674 N->getValueType(0),
21675 InputVector.getNode()->getOperand(0));
21677 // Only operate on vectors of 4 elements, where the alternative shuffling
21678 // gets to be more expensive.
21679 if (InputVector.getValueType() != MVT::v4i32)
21682 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21683 // single use which is a sign-extend or zero-extend, and all elements are
21685 SmallVector<SDNode *, 4> Uses;
21686 unsigned ExtractedElements = 0;
21687 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21688 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21689 if (UI.getUse().getResNo() != InputVector.getResNo())
21692 SDNode *Extract = *UI;
21693 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21696 if (Extract->getValueType(0) != MVT::i32)
21698 if (!Extract->hasOneUse())
21700 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21701 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21703 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21706 // Record which element was extracted.
21707 ExtractedElements |=
21708 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21710 Uses.push_back(Extract);
21713 // If not all the elements were used, this may not be worthwhile.
21714 if (ExtractedElements != 15)
21717 // Ok, we've now decided to do the transformation.
21718 SDLoc dl(InputVector);
21720 // Store the value to a temporary stack slot.
21721 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21722 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21723 MachinePointerInfo(), false, false, 0);
21725 // Replace each use (extract) with a load of the appropriate element.
21726 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21727 UE = Uses.end(); UI != UE; ++UI) {
21728 SDNode *Extract = *UI;
21730 // cOMpute the element's address.
21731 SDValue Idx = Extract->getOperand(1);
21733 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21734 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21735 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21736 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21738 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21739 StackPtr, OffsetVal);
21741 // Load the scalar.
21742 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21743 ScalarAddr, MachinePointerInfo(),
21744 false, false, false, 0);
21746 // Replace the exact with the load.
21747 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21750 // The replacement was made in place; don't return anything.
21754 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21755 static std::pair<unsigned, bool>
21756 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21757 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21758 if (!VT.isVector())
21759 return std::make_pair(0, false);
21761 bool NeedSplit = false;
21762 switch (VT.getSimpleVT().SimpleTy) {
21763 default: return std::make_pair(0, false);
21767 if (!Subtarget->hasAVX2())
21769 if (!Subtarget->hasAVX())
21770 return std::make_pair(0, false);
21775 if (!Subtarget->hasSSE2())
21776 return std::make_pair(0, false);
21779 // SSE2 has only a small subset of the operations.
21780 bool hasUnsigned = Subtarget->hasSSE41() ||
21781 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21782 bool hasSigned = Subtarget->hasSSE41() ||
21783 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21785 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21788 // Check for x CC y ? x : y.
21789 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21790 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21795 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21798 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21801 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21804 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21806 // Check for x CC y ? y : x -- a min/max with reversed arms.
21807 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21808 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21813 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21816 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21819 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21822 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21826 return std::make_pair(Opc, NeedSplit);
21830 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21831 const X86Subtarget *Subtarget) {
21833 SDValue Cond = N->getOperand(0);
21834 SDValue LHS = N->getOperand(1);
21835 SDValue RHS = N->getOperand(2);
21837 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21838 SDValue CondSrc = Cond->getOperand(0);
21839 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21840 Cond = CondSrc->getOperand(0);
21843 MVT VT = N->getSimpleValueType(0);
21844 MVT EltVT = VT.getVectorElementType();
21845 unsigned NumElems = VT.getVectorNumElements();
21846 // There is no blend with immediate in AVX-512.
21847 if (VT.is512BitVector())
21850 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21852 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21855 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21858 // A vselect where all conditions and data are constants can be optimized into
21859 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21860 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21861 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21864 unsigned MaskValue = 0;
21865 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21868 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21869 for (unsigned i = 0; i < NumElems; ++i) {
21870 // Be sure we emit undef where we can.
21871 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21872 ShuffleMask[i] = -1;
21874 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21877 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21880 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21882 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21883 TargetLowering::DAGCombinerInfo &DCI,
21884 const X86Subtarget *Subtarget) {
21886 SDValue Cond = N->getOperand(0);
21887 // Get the LHS/RHS of the select.
21888 SDValue LHS = N->getOperand(1);
21889 SDValue RHS = N->getOperand(2);
21890 EVT VT = LHS.getValueType();
21891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21893 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21894 // instructions match the semantics of the common C idiom x<y?x:y but not
21895 // x<=y?x:y, because of how they handle negative zero (which can be
21896 // ignored in unsafe-math mode).
21897 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21898 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21899 (Subtarget->hasSSE2() ||
21900 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21901 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21903 unsigned Opcode = 0;
21904 // Check for x CC y ? x : y.
21905 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21906 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21910 // Converting this to a min would handle NaNs incorrectly, and swapping
21911 // the operands would cause it to handle comparisons between positive
21912 // and negative zero incorrectly.
21913 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21914 if (!DAG.getTarget().Options.UnsafeFPMath &&
21915 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21917 std::swap(LHS, RHS);
21919 Opcode = X86ISD::FMIN;
21922 // Converting this to a min would handle comparisons between positive
21923 // and negative zero incorrectly.
21924 if (!DAG.getTarget().Options.UnsafeFPMath &&
21925 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21927 Opcode = X86ISD::FMIN;
21930 // Converting this to a min would handle both negative zeros and NaNs
21931 // incorrectly, but we can swap the operands to fix both.
21932 std::swap(LHS, RHS);
21936 Opcode = X86ISD::FMIN;
21940 // Converting this to a max would handle comparisons between positive
21941 // and negative zero incorrectly.
21942 if (!DAG.getTarget().Options.UnsafeFPMath &&
21943 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21945 Opcode = X86ISD::FMAX;
21948 // Converting this to a max would handle NaNs incorrectly, and swapping
21949 // the operands would cause it to handle comparisons between positive
21950 // and negative zero incorrectly.
21951 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21952 if (!DAG.getTarget().Options.UnsafeFPMath &&
21953 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21955 std::swap(LHS, RHS);
21957 Opcode = X86ISD::FMAX;
21960 // Converting this to a max would handle both negative zeros and NaNs
21961 // incorrectly, but we can swap the operands to fix both.
21962 std::swap(LHS, RHS);
21966 Opcode = X86ISD::FMAX;
21969 // Check for x CC y ? y : x -- a min/max with reversed arms.
21970 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21971 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21975 // Converting this to a min would handle comparisons between positive
21976 // and negative zero incorrectly, and swapping the operands would
21977 // cause it to handle NaNs incorrectly.
21978 if (!DAG.getTarget().Options.UnsafeFPMath &&
21979 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21980 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21982 std::swap(LHS, RHS);
21984 Opcode = X86ISD::FMIN;
21987 // Converting this to a min would handle NaNs incorrectly.
21988 if (!DAG.getTarget().Options.UnsafeFPMath &&
21989 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21991 Opcode = X86ISD::FMIN;
21994 // Converting this to a min would handle both negative zeros and NaNs
21995 // incorrectly, but we can swap the operands to fix both.
21996 std::swap(LHS, RHS);
22000 Opcode = X86ISD::FMIN;
22004 // Converting this to a max would handle NaNs incorrectly.
22005 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22007 Opcode = X86ISD::FMAX;
22010 // Converting this to a max would handle comparisons between positive
22011 // and negative zero incorrectly, and swapping the operands would
22012 // cause it to handle NaNs incorrectly.
22013 if (!DAG.getTarget().Options.UnsafeFPMath &&
22014 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22015 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22017 std::swap(LHS, RHS);
22019 Opcode = X86ISD::FMAX;
22022 // Converting this to a max would handle both negative zeros and NaNs
22023 // incorrectly, but we can swap the operands to fix both.
22024 std::swap(LHS, RHS);
22028 Opcode = X86ISD::FMAX;
22034 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22037 EVT CondVT = Cond.getValueType();
22038 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22039 CondVT.getVectorElementType() == MVT::i1) {
22040 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22041 // lowering on KNL. In this case we convert it to
22042 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22043 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22044 // Since SKX these selects have a proper lowering.
22045 EVT OpVT = LHS.getValueType();
22046 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22047 (OpVT.getVectorElementType() == MVT::i8 ||
22048 OpVT.getVectorElementType() == MVT::i16) &&
22049 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22050 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22051 DCI.AddToWorklist(Cond.getNode());
22052 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22055 // If this is a select between two integer constants, try to do some
22057 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22058 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22059 // Don't do this for crazy integer types.
22060 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22061 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22062 // so that TrueC (the true value) is larger than FalseC.
22063 bool NeedsCondInvert = false;
22065 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22066 // Efficiently invertible.
22067 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22068 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22069 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22070 NeedsCondInvert = true;
22071 std::swap(TrueC, FalseC);
22074 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22075 if (FalseC->getAPIntValue() == 0 &&
22076 TrueC->getAPIntValue().isPowerOf2()) {
22077 if (NeedsCondInvert) // Invert the condition if needed.
22078 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22079 DAG.getConstant(1, Cond.getValueType()));
22081 // Zero extend the condition if needed.
22082 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22084 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22085 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22086 DAG.getConstant(ShAmt, MVT::i8));
22089 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22090 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22091 if (NeedsCondInvert) // Invert the condition if needed.
22092 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22093 DAG.getConstant(1, Cond.getValueType()));
22095 // Zero extend the condition if needed.
22096 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22097 FalseC->getValueType(0), Cond);
22098 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22099 SDValue(FalseC, 0));
22102 // Optimize cases that will turn into an LEA instruction. This requires
22103 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22104 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22105 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22106 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22108 bool isFastMultiplier = false;
22110 switch ((unsigned char)Diff) {
22112 case 1: // result = add base, cond
22113 case 2: // result = lea base( , cond*2)
22114 case 3: // result = lea base(cond, cond*2)
22115 case 4: // result = lea base( , cond*4)
22116 case 5: // result = lea base(cond, cond*4)
22117 case 8: // result = lea base( , cond*8)
22118 case 9: // result = lea base(cond, cond*8)
22119 isFastMultiplier = true;
22124 if (isFastMultiplier) {
22125 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22126 if (NeedsCondInvert) // Invert the condition if needed.
22127 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22128 DAG.getConstant(1, Cond.getValueType()));
22130 // Zero extend the condition if needed.
22131 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22133 // Scale the condition by the difference.
22135 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22136 DAG.getConstant(Diff, Cond.getValueType()));
22138 // Add the base if non-zero.
22139 if (FalseC->getAPIntValue() != 0)
22140 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22141 SDValue(FalseC, 0));
22148 // Canonicalize max and min:
22149 // (x > y) ? x : y -> (x >= y) ? x : y
22150 // (x < y) ? x : y -> (x <= y) ? x : y
22151 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22152 // the need for an extra compare
22153 // against zero. e.g.
22154 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22156 // testl %edi, %edi
22158 // cmovgl %edi, %eax
22162 // cmovsl %eax, %edi
22163 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22164 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22165 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22166 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22171 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22172 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22173 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22174 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22179 // Early exit check
22180 if (!TLI.isTypeLegal(VT))
22183 // Match VSELECTs into subs with unsigned saturation.
22184 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22185 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22186 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22187 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22188 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22190 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22191 // left side invert the predicate to simplify logic below.
22193 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22195 CC = ISD::getSetCCInverse(CC, true);
22196 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22200 if (Other.getNode() && Other->getNumOperands() == 2 &&
22201 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22202 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22203 SDValue CondRHS = Cond->getOperand(1);
22205 // Look for a general sub with unsigned saturation first.
22206 // x >= y ? x-y : 0 --> subus x, y
22207 // x > y ? x-y : 0 --> subus x, y
22208 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22209 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22210 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22212 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22213 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22214 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22215 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22216 // If the RHS is a constant we have to reverse the const
22217 // canonicalization.
22218 // x > C-1 ? x+-C : 0 --> subus x, C
22219 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22220 CondRHSConst->getAPIntValue() ==
22221 (-OpRHSConst->getAPIntValue() - 1))
22222 return DAG.getNode(
22223 X86ISD::SUBUS, DL, VT, OpLHS,
22224 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22226 // Another special case: If C was a sign bit, the sub has been
22227 // canonicalized into a xor.
22228 // FIXME: Would it be better to use computeKnownBits to determine
22229 // whether it's safe to decanonicalize the xor?
22230 // x s< 0 ? x^C : 0 --> subus x, C
22231 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22232 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22233 OpRHSConst->getAPIntValue().isSignBit())
22234 // Note that we have to rebuild the RHS constant here to ensure we
22235 // don't rely on particular values of undef lanes.
22236 return DAG.getNode(
22237 X86ISD::SUBUS, DL, VT, OpLHS,
22238 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22243 // Try to match a min/max vector operation.
22244 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22245 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22246 unsigned Opc = ret.first;
22247 bool NeedSplit = ret.second;
22249 if (Opc && NeedSplit) {
22250 unsigned NumElems = VT.getVectorNumElements();
22251 // Extract the LHS vectors
22252 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22253 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22255 // Extract the RHS vectors
22256 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22257 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22259 // Create min/max for each subvector
22260 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22261 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22263 // Merge the result
22264 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22266 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22269 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22270 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22271 // Check if SETCC has already been promoted
22272 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22273 // Check that condition value type matches vselect operand type
22276 assert(Cond.getValueType().isVector() &&
22277 "vector select expects a vector selector!");
22279 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22280 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22282 if (!TValIsAllOnes && !FValIsAllZeros) {
22283 // Try invert the condition if true value is not all 1s and false value
22285 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22286 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22288 if (TValIsAllZeros || FValIsAllOnes) {
22289 SDValue CC = Cond.getOperand(2);
22290 ISD::CondCode NewCC =
22291 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22292 Cond.getOperand(0).getValueType().isInteger());
22293 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22294 std::swap(LHS, RHS);
22295 TValIsAllOnes = FValIsAllOnes;
22296 FValIsAllZeros = TValIsAllZeros;
22300 if (TValIsAllOnes || FValIsAllZeros) {
22303 if (TValIsAllOnes && FValIsAllZeros)
22305 else if (TValIsAllOnes)
22306 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22307 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22308 else if (FValIsAllZeros)
22309 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22310 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22312 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22316 // Try to fold this VSELECT into a MOVSS/MOVSD
22317 if (N->getOpcode() == ISD::VSELECT &&
22318 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22319 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22320 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22321 bool CanFold = false;
22322 unsigned NumElems = Cond.getNumOperands();
22326 if (isZero(Cond.getOperand(0))) {
22329 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22330 // fold (vselect <0,-1> -> (movsd A, B)
22331 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22332 CanFold = isAllOnes(Cond.getOperand(i));
22333 } else if (isAllOnes(Cond.getOperand(0))) {
22337 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22338 // fold (vselect <-1,0> -> (movsd B, A)
22339 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22340 CanFold = isZero(Cond.getOperand(i));
22344 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22345 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22346 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22349 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22350 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22351 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22352 // (v2i64 (bitcast B)))))
22354 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22355 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22356 // (v2f64 (bitcast B)))))
22358 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22359 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22360 // (v2i64 (bitcast A)))))
22362 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22363 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22364 // (v2f64 (bitcast A)))))
22366 CanFold = (isZero(Cond.getOperand(0)) &&
22367 isZero(Cond.getOperand(1)) &&
22368 isAllOnes(Cond.getOperand(2)) &&
22369 isAllOnes(Cond.getOperand(3)));
22371 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22372 isAllOnes(Cond.getOperand(1)) &&
22373 isZero(Cond.getOperand(2)) &&
22374 isZero(Cond.getOperand(3))) {
22376 std::swap(LHS, RHS);
22380 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22381 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22382 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22383 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22385 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22391 // If we know that this node is legal then we know that it is going to be
22392 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22393 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22394 // to simplify previous instructions.
22395 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22396 !DCI.isBeforeLegalize() &&
22397 // We explicitly check against v8i16 and v16i16 because, although
22398 // they're marked as Custom, they might only be legal when Cond is a
22399 // build_vector of constants. This will be taken care in a later
22401 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22402 VT != MVT::v8i16)) {
22403 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22405 // Don't optimize vector selects that map to mask-registers.
22409 // Check all uses of that condition operand to check whether it will be
22410 // consumed by non-BLEND instructions, which may depend on all bits are set
22412 for (SDNode::use_iterator I = Cond->use_begin(),
22413 E = Cond->use_end(); I != E; ++I)
22414 if (I->getOpcode() != ISD::VSELECT)
22415 // TODO: Add other opcodes eventually lowered into BLEND.
22418 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22419 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22421 APInt KnownZero, KnownOne;
22422 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22423 DCI.isBeforeLegalizeOps());
22424 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22425 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22426 DCI.CommitTargetLoweringOpt(TLO);
22429 // We should generate an X86ISD::BLENDI from a vselect if its argument
22430 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22431 // constants. This specific pattern gets generated when we split a
22432 // selector for a 512 bit vector in a machine without AVX512 (but with
22433 // 256-bit vectors), during legalization:
22435 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22437 // Iff we find this pattern and the build_vectors are built from
22438 // constants, we translate the vselect into a shuffle_vector that we
22439 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22440 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22441 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22442 if (Shuffle.getNode())
22449 // Check whether a boolean test is testing a boolean value generated by
22450 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22453 // Simplify the following patterns:
22454 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22455 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22456 // to (Op EFLAGS Cond)
22458 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22459 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22460 // to (Op EFLAGS !Cond)
22462 // where Op could be BRCOND or CMOV.
22464 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22465 // Quit if not CMP and SUB with its value result used.
22466 if (Cmp.getOpcode() != X86ISD::CMP &&
22467 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22470 // Quit if not used as a boolean value.
22471 if (CC != X86::COND_E && CC != X86::COND_NE)
22474 // Check CMP operands. One of them should be 0 or 1 and the other should be
22475 // an SetCC or extended from it.
22476 SDValue Op1 = Cmp.getOperand(0);
22477 SDValue Op2 = Cmp.getOperand(1);
22480 const ConstantSDNode* C = nullptr;
22481 bool needOppositeCond = (CC == X86::COND_E);
22482 bool checkAgainstTrue = false; // Is it a comparison against 1?
22484 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22486 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22488 else // Quit if all operands are not constants.
22491 if (C->getZExtValue() == 1) {
22492 needOppositeCond = !needOppositeCond;
22493 checkAgainstTrue = true;
22494 } else if (C->getZExtValue() != 0)
22495 // Quit if the constant is neither 0 or 1.
22498 bool truncatedToBoolWithAnd = false;
22499 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22500 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22501 SetCC.getOpcode() == ISD::TRUNCATE ||
22502 SetCC.getOpcode() == ISD::AND) {
22503 if (SetCC.getOpcode() == ISD::AND) {
22505 ConstantSDNode *CS;
22506 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22507 CS->getZExtValue() == 1)
22509 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22510 CS->getZExtValue() == 1)
22514 SetCC = SetCC.getOperand(OpIdx);
22515 truncatedToBoolWithAnd = true;
22517 SetCC = SetCC.getOperand(0);
22520 switch (SetCC.getOpcode()) {
22521 case X86ISD::SETCC_CARRY:
22522 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22523 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22524 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22525 // truncated to i1 using 'and'.
22526 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22528 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22529 "Invalid use of SETCC_CARRY!");
22531 case X86ISD::SETCC:
22532 // Set the condition code or opposite one if necessary.
22533 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22534 if (needOppositeCond)
22535 CC = X86::GetOppositeBranchCondition(CC);
22536 return SetCC.getOperand(1);
22537 case X86ISD::CMOV: {
22538 // Check whether false/true value has canonical one, i.e. 0 or 1.
22539 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22540 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22541 // Quit if true value is not a constant.
22544 // Quit if false value is not a constant.
22546 SDValue Op = SetCC.getOperand(0);
22547 // Skip 'zext' or 'trunc' node.
22548 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22549 Op.getOpcode() == ISD::TRUNCATE)
22550 Op = Op.getOperand(0);
22551 // A special case for rdrand/rdseed, where 0 is set if false cond is
22553 if ((Op.getOpcode() != X86ISD::RDRAND &&
22554 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22557 // Quit if false value is not the constant 0 or 1.
22558 bool FValIsFalse = true;
22559 if (FVal && FVal->getZExtValue() != 0) {
22560 if (FVal->getZExtValue() != 1)
22562 // If FVal is 1, opposite cond is needed.
22563 needOppositeCond = !needOppositeCond;
22564 FValIsFalse = false;
22566 // Quit if TVal is not the constant opposite of FVal.
22567 if (FValIsFalse && TVal->getZExtValue() != 1)
22569 if (!FValIsFalse && TVal->getZExtValue() != 0)
22571 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22572 if (needOppositeCond)
22573 CC = X86::GetOppositeBranchCondition(CC);
22574 return SetCC.getOperand(3);
22581 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22582 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22583 TargetLowering::DAGCombinerInfo &DCI,
22584 const X86Subtarget *Subtarget) {
22587 // If the flag operand isn't dead, don't touch this CMOV.
22588 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22591 SDValue FalseOp = N->getOperand(0);
22592 SDValue TrueOp = N->getOperand(1);
22593 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22594 SDValue Cond = N->getOperand(3);
22596 if (CC == X86::COND_E || CC == X86::COND_NE) {
22597 switch (Cond.getOpcode()) {
22601 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22602 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22603 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22609 Flags = checkBoolTestSetCCCombine(Cond, CC);
22610 if (Flags.getNode() &&
22611 // Extra check as FCMOV only supports a subset of X86 cond.
22612 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22613 SDValue Ops[] = { FalseOp, TrueOp,
22614 DAG.getConstant(CC, MVT::i8), Flags };
22615 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22618 // If this is a select between two integer constants, try to do some
22619 // optimizations. Note that the operands are ordered the opposite of SELECT
22621 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22622 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22623 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22624 // larger than FalseC (the false value).
22625 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22626 CC = X86::GetOppositeBranchCondition(CC);
22627 std::swap(TrueC, FalseC);
22628 std::swap(TrueOp, FalseOp);
22631 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22632 // This is efficient for any integer data type (including i8/i16) and
22634 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22635 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22636 DAG.getConstant(CC, MVT::i8), Cond);
22638 // Zero extend the condition if needed.
22639 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22641 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22642 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22643 DAG.getConstant(ShAmt, MVT::i8));
22644 if (N->getNumValues() == 2) // Dead flag value?
22645 return DCI.CombineTo(N, Cond, SDValue());
22649 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22650 // for any integer data type, including i8/i16.
22651 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22652 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22653 DAG.getConstant(CC, MVT::i8), Cond);
22655 // Zero extend the condition if needed.
22656 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22657 FalseC->getValueType(0), Cond);
22658 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22659 SDValue(FalseC, 0));
22661 if (N->getNumValues() == 2) // Dead flag value?
22662 return DCI.CombineTo(N, Cond, SDValue());
22666 // Optimize cases that will turn into an LEA instruction. This requires
22667 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22668 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22669 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22670 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22672 bool isFastMultiplier = false;
22674 switch ((unsigned char)Diff) {
22676 case 1: // result = add base, cond
22677 case 2: // result = lea base( , cond*2)
22678 case 3: // result = lea base(cond, cond*2)
22679 case 4: // result = lea base( , cond*4)
22680 case 5: // result = lea base(cond, cond*4)
22681 case 8: // result = lea base( , cond*8)
22682 case 9: // result = lea base(cond, cond*8)
22683 isFastMultiplier = true;
22688 if (isFastMultiplier) {
22689 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22690 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22691 DAG.getConstant(CC, MVT::i8), Cond);
22692 // Zero extend the condition if needed.
22693 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22695 // Scale the condition by the difference.
22697 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22698 DAG.getConstant(Diff, Cond.getValueType()));
22700 // Add the base if non-zero.
22701 if (FalseC->getAPIntValue() != 0)
22702 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22703 SDValue(FalseC, 0));
22704 if (N->getNumValues() == 2) // Dead flag value?
22705 return DCI.CombineTo(N, Cond, SDValue());
22712 // Handle these cases:
22713 // (select (x != c), e, c) -> select (x != c), e, x),
22714 // (select (x == c), c, e) -> select (x == c), x, e)
22715 // where the c is an integer constant, and the "select" is the combination
22716 // of CMOV and CMP.
22718 // The rationale for this change is that the conditional-move from a constant
22719 // needs two instructions, however, conditional-move from a register needs
22720 // only one instruction.
22722 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22723 // some instruction-combining opportunities. This opt needs to be
22724 // postponed as late as possible.
22726 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22727 // the DCI.xxxx conditions are provided to postpone the optimization as
22728 // late as possible.
22730 ConstantSDNode *CmpAgainst = nullptr;
22731 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22732 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22733 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22735 if (CC == X86::COND_NE &&
22736 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22737 CC = X86::GetOppositeBranchCondition(CC);
22738 std::swap(TrueOp, FalseOp);
22741 if (CC == X86::COND_E &&
22742 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22743 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22744 DAG.getConstant(CC, MVT::i8), Cond };
22745 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22753 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22754 const X86Subtarget *Subtarget) {
22755 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22757 default: return SDValue();
22758 // SSE/AVX/AVX2 blend intrinsics.
22759 case Intrinsic::x86_avx2_pblendvb:
22760 case Intrinsic::x86_avx2_pblendw:
22761 case Intrinsic::x86_avx2_pblendd_128:
22762 case Intrinsic::x86_avx2_pblendd_256:
22763 // Don't try to simplify this intrinsic if we don't have AVX2.
22764 if (!Subtarget->hasAVX2())
22767 case Intrinsic::x86_avx_blend_pd_256:
22768 case Intrinsic::x86_avx_blend_ps_256:
22769 case Intrinsic::x86_avx_blendv_pd_256:
22770 case Intrinsic::x86_avx_blendv_ps_256:
22771 // Don't try to simplify this intrinsic if we don't have AVX.
22772 if (!Subtarget->hasAVX())
22775 case Intrinsic::x86_sse41_pblendw:
22776 case Intrinsic::x86_sse41_blendpd:
22777 case Intrinsic::x86_sse41_blendps:
22778 case Intrinsic::x86_sse41_blendvps:
22779 case Intrinsic::x86_sse41_blendvpd:
22780 case Intrinsic::x86_sse41_pblendvb: {
22781 SDValue Op0 = N->getOperand(1);
22782 SDValue Op1 = N->getOperand(2);
22783 SDValue Mask = N->getOperand(3);
22785 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22786 if (!Subtarget->hasSSE41())
22789 // fold (blend A, A, Mask) -> A
22792 // fold (blend A, B, allZeros) -> A
22793 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22795 // fold (blend A, B, allOnes) -> B
22796 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22799 // Simplify the case where the mask is a constant i32 value.
22800 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22801 if (C->isNullValue())
22803 if (C->isAllOnesValue())
22810 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22811 case Intrinsic::x86_sse2_psrai_w:
22812 case Intrinsic::x86_sse2_psrai_d:
22813 case Intrinsic::x86_avx2_psrai_w:
22814 case Intrinsic::x86_avx2_psrai_d:
22815 case Intrinsic::x86_sse2_psra_w:
22816 case Intrinsic::x86_sse2_psra_d:
22817 case Intrinsic::x86_avx2_psra_w:
22818 case Intrinsic::x86_avx2_psra_d: {
22819 SDValue Op0 = N->getOperand(1);
22820 SDValue Op1 = N->getOperand(2);
22821 EVT VT = Op0.getValueType();
22822 assert(VT.isVector() && "Expected a vector type!");
22824 if (isa<BuildVectorSDNode>(Op1))
22825 Op1 = Op1.getOperand(0);
22827 if (!isa<ConstantSDNode>(Op1))
22830 EVT SVT = VT.getVectorElementType();
22831 unsigned SVTBits = SVT.getSizeInBits();
22833 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22834 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22835 uint64_t ShAmt = C.getZExtValue();
22837 // Don't try to convert this shift into a ISD::SRA if the shift
22838 // count is bigger than or equal to the element size.
22839 if (ShAmt >= SVTBits)
22842 // Trivial case: if the shift count is zero, then fold this
22843 // into the first operand.
22847 // Replace this packed shift intrinsic with a target independent
22849 SDValue Splat = DAG.getConstant(C, VT);
22850 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22855 /// PerformMulCombine - Optimize a single multiply with constant into two
22856 /// in order to implement it with two cheaper instructions, e.g.
22857 /// LEA + SHL, LEA + LEA.
22858 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22859 TargetLowering::DAGCombinerInfo &DCI) {
22860 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22863 EVT VT = N->getValueType(0);
22864 if (VT != MVT::i64)
22867 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22870 uint64_t MulAmt = C->getZExtValue();
22871 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22874 uint64_t MulAmt1 = 0;
22875 uint64_t MulAmt2 = 0;
22876 if ((MulAmt % 9) == 0) {
22878 MulAmt2 = MulAmt / 9;
22879 } else if ((MulAmt % 5) == 0) {
22881 MulAmt2 = MulAmt / 5;
22882 } else if ((MulAmt % 3) == 0) {
22884 MulAmt2 = MulAmt / 3;
22887 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22890 if (isPowerOf2_64(MulAmt2) &&
22891 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22892 // If second multiplifer is pow2, issue it first. We want the multiply by
22893 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22895 std::swap(MulAmt1, MulAmt2);
22898 if (isPowerOf2_64(MulAmt1))
22899 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22900 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22902 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22903 DAG.getConstant(MulAmt1, VT));
22905 if (isPowerOf2_64(MulAmt2))
22906 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22907 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22909 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22910 DAG.getConstant(MulAmt2, VT));
22912 // Do not add new nodes to DAG combiner worklist.
22913 DCI.CombineTo(N, NewMul, false);
22918 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22919 SDValue N0 = N->getOperand(0);
22920 SDValue N1 = N->getOperand(1);
22921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22922 EVT VT = N0.getValueType();
22924 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22925 // since the result of setcc_c is all zero's or all ones.
22926 if (VT.isInteger() && !VT.isVector() &&
22927 N1C && N0.getOpcode() == ISD::AND &&
22928 N0.getOperand(1).getOpcode() == ISD::Constant) {
22929 SDValue N00 = N0.getOperand(0);
22930 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22931 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22932 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22933 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22934 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22935 APInt ShAmt = N1C->getAPIntValue();
22936 Mask = Mask.shl(ShAmt);
22938 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22939 N00, DAG.getConstant(Mask, VT));
22943 // Hardware support for vector shifts is sparse which makes us scalarize the
22944 // vector operations in many cases. Also, on sandybridge ADD is faster than
22946 // (shl V, 1) -> add V,V
22947 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22948 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22949 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22950 // We shift all of the values by one. In many cases we do not have
22951 // hardware support for this operation. This is better expressed as an ADD
22953 if (N1SplatC->getZExtValue() == 1)
22954 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22960 /// \brief Returns a vector of 0s if the node in input is a vector logical
22961 /// shift by a constant amount which is known to be bigger than or equal
22962 /// to the vector element size in bits.
22963 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22964 const X86Subtarget *Subtarget) {
22965 EVT VT = N->getValueType(0);
22967 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22968 (!Subtarget->hasInt256() ||
22969 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22972 SDValue Amt = N->getOperand(1);
22974 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22975 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22976 APInt ShiftAmt = AmtSplat->getAPIntValue();
22977 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22979 // SSE2/AVX2 logical shifts always return a vector of 0s
22980 // if the shift amount is bigger than or equal to
22981 // the element size. The constant shift amount will be
22982 // encoded as a 8-bit immediate.
22983 if (ShiftAmt.trunc(8).uge(MaxAmount))
22984 return getZeroVector(VT, Subtarget, DAG, DL);
22990 /// PerformShiftCombine - Combine shifts.
22991 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22992 TargetLowering::DAGCombinerInfo &DCI,
22993 const X86Subtarget *Subtarget) {
22994 if (N->getOpcode() == ISD::SHL) {
22995 SDValue V = PerformSHLCombine(N, DAG);
22996 if (V.getNode()) return V;
22999 if (N->getOpcode() != ISD::SRA) {
23000 // Try to fold this logical shift into a zero vector.
23001 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23002 if (V.getNode()) return V;
23008 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23009 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23010 // and friends. Likewise for OR -> CMPNEQSS.
23011 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23012 TargetLowering::DAGCombinerInfo &DCI,
23013 const X86Subtarget *Subtarget) {
23016 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23017 // we're requiring SSE2 for both.
23018 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23019 SDValue N0 = N->getOperand(0);
23020 SDValue N1 = N->getOperand(1);
23021 SDValue CMP0 = N0->getOperand(1);
23022 SDValue CMP1 = N1->getOperand(1);
23025 // The SETCCs should both refer to the same CMP.
23026 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23029 SDValue CMP00 = CMP0->getOperand(0);
23030 SDValue CMP01 = CMP0->getOperand(1);
23031 EVT VT = CMP00.getValueType();
23033 if (VT == MVT::f32 || VT == MVT::f64) {
23034 bool ExpectingFlags = false;
23035 // Check for any users that want flags:
23036 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23037 !ExpectingFlags && UI != UE; ++UI)
23038 switch (UI->getOpcode()) {
23043 ExpectingFlags = true;
23045 case ISD::CopyToReg:
23046 case ISD::SIGN_EXTEND:
23047 case ISD::ZERO_EXTEND:
23048 case ISD::ANY_EXTEND:
23052 if (!ExpectingFlags) {
23053 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23054 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23056 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23057 X86::CondCode tmp = cc0;
23062 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23063 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23064 // FIXME: need symbolic constants for these magic numbers.
23065 // See X86ATTInstPrinter.cpp:printSSECC().
23066 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23067 if (Subtarget->hasAVX512()) {
23068 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23069 CMP01, DAG.getConstant(x86cc, MVT::i8));
23070 if (N->getValueType(0) != MVT::i1)
23071 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23075 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23076 CMP00.getValueType(), CMP00, CMP01,
23077 DAG.getConstant(x86cc, MVT::i8));
23079 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23080 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23082 if (is64BitFP && !Subtarget->is64Bit()) {
23083 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23084 // 64-bit integer, since that's not a legal type. Since
23085 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23086 // bits, but can do this little dance to extract the lowest 32 bits
23087 // and work with those going forward.
23088 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23090 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23092 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23093 Vector32, DAG.getIntPtrConstant(0));
23097 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23098 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23099 DAG.getConstant(1, IntVT));
23100 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23101 return OneBitOfTruth;
23109 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23110 /// so it can be folded inside ANDNP.
23111 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23112 EVT VT = N->getValueType(0);
23114 // Match direct AllOnes for 128 and 256-bit vectors
23115 if (ISD::isBuildVectorAllOnes(N))
23118 // Look through a bit convert.
23119 if (N->getOpcode() == ISD::BITCAST)
23120 N = N->getOperand(0).getNode();
23122 // Sometimes the operand may come from a insert_subvector building a 256-bit
23124 if (VT.is256BitVector() &&
23125 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23126 SDValue V1 = N->getOperand(0);
23127 SDValue V2 = N->getOperand(1);
23129 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23130 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23131 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23132 ISD::isBuildVectorAllOnes(V2.getNode()))
23139 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23140 // register. In most cases we actually compare or select YMM-sized registers
23141 // and mixing the two types creates horrible code. This method optimizes
23142 // some of the transition sequences.
23143 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23144 TargetLowering::DAGCombinerInfo &DCI,
23145 const X86Subtarget *Subtarget) {
23146 EVT VT = N->getValueType(0);
23147 if (!VT.is256BitVector())
23150 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23151 N->getOpcode() == ISD::ZERO_EXTEND ||
23152 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23154 SDValue Narrow = N->getOperand(0);
23155 EVT NarrowVT = Narrow->getValueType(0);
23156 if (!NarrowVT.is128BitVector())
23159 if (Narrow->getOpcode() != ISD::XOR &&
23160 Narrow->getOpcode() != ISD::AND &&
23161 Narrow->getOpcode() != ISD::OR)
23164 SDValue N0 = Narrow->getOperand(0);
23165 SDValue N1 = Narrow->getOperand(1);
23168 // The Left side has to be a trunc.
23169 if (N0.getOpcode() != ISD::TRUNCATE)
23172 // The type of the truncated inputs.
23173 EVT WideVT = N0->getOperand(0)->getValueType(0);
23177 // The right side has to be a 'trunc' or a constant vector.
23178 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23179 ConstantSDNode *RHSConstSplat = nullptr;
23180 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23181 RHSConstSplat = RHSBV->getConstantSplatNode();
23182 if (!RHSTrunc && !RHSConstSplat)
23185 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23187 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23190 // Set N0 and N1 to hold the inputs to the new wide operation.
23191 N0 = N0->getOperand(0);
23192 if (RHSConstSplat) {
23193 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23194 SDValue(RHSConstSplat, 0));
23195 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23196 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23197 } else if (RHSTrunc) {
23198 N1 = N1->getOperand(0);
23201 // Generate the wide operation.
23202 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23203 unsigned Opcode = N->getOpcode();
23205 case ISD::ANY_EXTEND:
23207 case ISD::ZERO_EXTEND: {
23208 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23209 APInt Mask = APInt::getAllOnesValue(InBits);
23210 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23211 return DAG.getNode(ISD::AND, DL, VT,
23212 Op, DAG.getConstant(Mask, VT));
23214 case ISD::SIGN_EXTEND:
23215 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23216 Op, DAG.getValueType(NarrowVT));
23218 llvm_unreachable("Unexpected opcode");
23222 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23223 TargetLowering::DAGCombinerInfo &DCI,
23224 const X86Subtarget *Subtarget) {
23225 EVT VT = N->getValueType(0);
23226 if (DCI.isBeforeLegalizeOps())
23229 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23233 // Create BEXTR instructions
23234 // BEXTR is ((X >> imm) & (2**size-1))
23235 if (VT == MVT::i32 || VT == MVT::i64) {
23236 SDValue N0 = N->getOperand(0);
23237 SDValue N1 = N->getOperand(1);
23240 // Check for BEXTR.
23241 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23242 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23243 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23244 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23245 if (MaskNode && ShiftNode) {
23246 uint64_t Mask = MaskNode->getZExtValue();
23247 uint64_t Shift = ShiftNode->getZExtValue();
23248 if (isMask_64(Mask)) {
23249 uint64_t MaskSize = CountPopulation_64(Mask);
23250 if (Shift + MaskSize <= VT.getSizeInBits())
23251 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23252 DAG.getConstant(Shift | (MaskSize << 8), VT));
23260 // Want to form ANDNP nodes:
23261 // 1) In the hopes of then easily combining them with OR and AND nodes
23262 // to form PBLEND/PSIGN.
23263 // 2) To match ANDN packed intrinsics
23264 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23267 SDValue N0 = N->getOperand(0);
23268 SDValue N1 = N->getOperand(1);
23271 // Check LHS for vnot
23272 if (N0.getOpcode() == ISD::XOR &&
23273 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23274 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23275 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23277 // Check RHS for vnot
23278 if (N1.getOpcode() == ISD::XOR &&
23279 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23280 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23281 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23286 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23287 TargetLowering::DAGCombinerInfo &DCI,
23288 const X86Subtarget *Subtarget) {
23289 if (DCI.isBeforeLegalizeOps())
23292 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23296 SDValue N0 = N->getOperand(0);
23297 SDValue N1 = N->getOperand(1);
23298 EVT VT = N->getValueType(0);
23300 // look for psign/blend
23301 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23302 if (!Subtarget->hasSSSE3() ||
23303 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23306 // Canonicalize pandn to RHS
23307 if (N0.getOpcode() == X86ISD::ANDNP)
23309 // or (and (m, y), (pandn m, x))
23310 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23311 SDValue Mask = N1.getOperand(0);
23312 SDValue X = N1.getOperand(1);
23314 if (N0.getOperand(0) == Mask)
23315 Y = N0.getOperand(1);
23316 if (N0.getOperand(1) == Mask)
23317 Y = N0.getOperand(0);
23319 // Check to see if the mask appeared in both the AND and ANDNP and
23323 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23324 // Look through mask bitcast.
23325 if (Mask.getOpcode() == ISD::BITCAST)
23326 Mask = Mask.getOperand(0);
23327 if (X.getOpcode() == ISD::BITCAST)
23328 X = X.getOperand(0);
23329 if (Y.getOpcode() == ISD::BITCAST)
23330 Y = Y.getOperand(0);
23332 EVT MaskVT = Mask.getValueType();
23334 // Validate that the Mask operand is a vector sra node.
23335 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23336 // there is no psrai.b
23337 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23338 unsigned SraAmt = ~0;
23339 if (Mask.getOpcode() == ISD::SRA) {
23340 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23341 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23342 SraAmt = AmtConst->getZExtValue();
23343 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23344 SDValue SraC = Mask.getOperand(1);
23345 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23347 if ((SraAmt + 1) != EltBits)
23352 // Now we know we at least have a plendvb with the mask val. See if
23353 // we can form a psignb/w/d.
23354 // psign = x.type == y.type == mask.type && y = sub(0, x);
23355 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23356 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23357 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23358 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23359 "Unsupported VT for PSIGN");
23360 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23361 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23363 // PBLENDVB only available on SSE 4.1
23364 if (!Subtarget->hasSSE41())
23367 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23369 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23370 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23371 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23372 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23373 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23377 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23380 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23381 MachineFunction &MF = DAG.getMachineFunction();
23382 bool OptForSize = MF.getFunction()->getAttributes().
23383 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23385 // SHLD/SHRD instructions have lower register pressure, but on some
23386 // platforms they have higher latency than the equivalent
23387 // series of shifts/or that would otherwise be generated.
23388 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23389 // have higher latencies and we are not optimizing for size.
23390 if (!OptForSize && Subtarget->isSHLDSlow())
23393 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23395 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23397 if (!N0.hasOneUse() || !N1.hasOneUse())
23400 SDValue ShAmt0 = N0.getOperand(1);
23401 if (ShAmt0.getValueType() != MVT::i8)
23403 SDValue ShAmt1 = N1.getOperand(1);
23404 if (ShAmt1.getValueType() != MVT::i8)
23406 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23407 ShAmt0 = ShAmt0.getOperand(0);
23408 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23409 ShAmt1 = ShAmt1.getOperand(0);
23412 unsigned Opc = X86ISD::SHLD;
23413 SDValue Op0 = N0.getOperand(0);
23414 SDValue Op1 = N1.getOperand(0);
23415 if (ShAmt0.getOpcode() == ISD::SUB) {
23416 Opc = X86ISD::SHRD;
23417 std::swap(Op0, Op1);
23418 std::swap(ShAmt0, ShAmt1);
23421 unsigned Bits = VT.getSizeInBits();
23422 if (ShAmt1.getOpcode() == ISD::SUB) {
23423 SDValue Sum = ShAmt1.getOperand(0);
23424 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23425 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23426 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23427 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23428 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23429 return DAG.getNode(Opc, DL, VT,
23431 DAG.getNode(ISD::TRUNCATE, DL,
23434 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23435 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23437 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23438 return DAG.getNode(Opc, DL, VT,
23439 N0.getOperand(0), N1.getOperand(0),
23440 DAG.getNode(ISD::TRUNCATE, DL,
23447 // Generate NEG and CMOV for integer abs.
23448 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23449 EVT VT = N->getValueType(0);
23451 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23452 // 8-bit integer abs to NEG and CMOV.
23453 if (VT.isInteger() && VT.getSizeInBits() == 8)
23456 SDValue N0 = N->getOperand(0);
23457 SDValue N1 = N->getOperand(1);
23460 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23461 // and change it to SUB and CMOV.
23462 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23463 N0.getOpcode() == ISD::ADD &&
23464 N0.getOperand(1) == N1 &&
23465 N1.getOpcode() == ISD::SRA &&
23466 N1.getOperand(0) == N0.getOperand(0))
23467 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23468 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23469 // Generate SUB & CMOV.
23470 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23471 DAG.getConstant(0, VT), N0.getOperand(0));
23473 SDValue Ops[] = { N0.getOperand(0), Neg,
23474 DAG.getConstant(X86::COND_GE, MVT::i8),
23475 SDValue(Neg.getNode(), 1) };
23476 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23481 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23482 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23483 TargetLowering::DAGCombinerInfo &DCI,
23484 const X86Subtarget *Subtarget) {
23485 if (DCI.isBeforeLegalizeOps())
23488 if (Subtarget->hasCMov()) {
23489 SDValue RV = performIntegerAbsCombine(N, DAG);
23497 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23498 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23499 TargetLowering::DAGCombinerInfo &DCI,
23500 const X86Subtarget *Subtarget) {
23501 LoadSDNode *Ld = cast<LoadSDNode>(N);
23502 EVT RegVT = Ld->getValueType(0);
23503 EVT MemVT = Ld->getMemoryVT();
23505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23507 // On Sandybridge unaligned 256bit loads are inefficient.
23508 ISD::LoadExtType Ext = Ld->getExtensionType();
23509 unsigned Alignment = Ld->getAlignment();
23510 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23511 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23512 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23513 unsigned NumElems = RegVT.getVectorNumElements();
23517 SDValue Ptr = Ld->getBasePtr();
23518 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23520 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23522 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23523 Ld->getPointerInfo(), Ld->isVolatile(),
23524 Ld->isNonTemporal(), Ld->isInvariant(),
23526 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23527 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23528 Ld->getPointerInfo(), Ld->isVolatile(),
23529 Ld->isNonTemporal(), Ld->isInvariant(),
23530 std::min(16U, Alignment));
23531 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23533 Load2.getValue(1));
23535 SDValue NewVec = DAG.getUNDEF(RegVT);
23536 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23537 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23538 return DCI.CombineTo(N, NewVec, TF, true);
23544 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23545 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23546 const X86Subtarget *Subtarget) {
23547 StoreSDNode *St = cast<StoreSDNode>(N);
23548 EVT VT = St->getValue().getValueType();
23549 EVT StVT = St->getMemoryVT();
23551 SDValue StoredVal = St->getOperand(1);
23552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23554 // If we are saving a concatenation of two XMM registers, perform two stores.
23555 // On Sandy Bridge, 256-bit memory operations are executed by two
23556 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23557 // memory operation.
23558 unsigned Alignment = St->getAlignment();
23559 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23560 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23561 StVT == VT && !IsAligned) {
23562 unsigned NumElems = VT.getVectorNumElements();
23566 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23567 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23569 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23570 SDValue Ptr0 = St->getBasePtr();
23571 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23573 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23574 St->getPointerInfo(), St->isVolatile(),
23575 St->isNonTemporal(), Alignment);
23576 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23577 St->getPointerInfo(), St->isVolatile(),
23578 St->isNonTemporal(),
23579 std::min(16U, Alignment));
23580 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23583 // Optimize trunc store (of multiple scalars) to shuffle and store.
23584 // First, pack all of the elements in one place. Next, store to memory
23585 // in fewer chunks.
23586 if (St->isTruncatingStore() && VT.isVector()) {
23587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23588 unsigned NumElems = VT.getVectorNumElements();
23589 assert(StVT != VT && "Cannot truncate to the same type");
23590 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23591 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23593 // From, To sizes and ElemCount must be pow of two
23594 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23595 // We are going to use the original vector elt for storing.
23596 // Accumulated smaller vector elements must be a multiple of the store size.
23597 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23599 unsigned SizeRatio = FromSz / ToSz;
23601 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23603 // Create a type on which we perform the shuffle
23604 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23605 StVT.getScalarType(), NumElems*SizeRatio);
23607 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23609 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23610 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23611 for (unsigned i = 0; i != NumElems; ++i)
23612 ShuffleVec[i] = i * SizeRatio;
23614 // Can't shuffle using an illegal type.
23615 if (!TLI.isTypeLegal(WideVecVT))
23618 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23619 DAG.getUNDEF(WideVecVT),
23621 // At this point all of the data is stored at the bottom of the
23622 // register. We now need to save it to mem.
23624 // Find the largest store unit
23625 MVT StoreType = MVT::i8;
23626 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23627 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23628 MVT Tp = (MVT::SimpleValueType)tp;
23629 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23633 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23634 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23635 (64 <= NumElems * ToSz))
23636 StoreType = MVT::f64;
23638 // Bitcast the original vector into a vector of store-size units
23639 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23640 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23641 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23642 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23643 SmallVector<SDValue, 8> Chains;
23644 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23645 TLI.getPointerTy());
23646 SDValue Ptr = St->getBasePtr();
23648 // Perform one or more big stores into memory.
23649 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23650 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23651 StoreType, ShuffWide,
23652 DAG.getIntPtrConstant(i));
23653 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23654 St->getPointerInfo(), St->isVolatile(),
23655 St->isNonTemporal(), St->getAlignment());
23656 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23657 Chains.push_back(Ch);
23660 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23663 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23664 // the FP state in cases where an emms may be missing.
23665 // A preferable solution to the general problem is to figure out the right
23666 // places to insert EMMS. This qualifies as a quick hack.
23668 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23669 if (VT.getSizeInBits() != 64)
23672 const Function *F = DAG.getMachineFunction().getFunction();
23673 bool NoImplicitFloatOps = F->getAttributes().
23674 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23675 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23676 && Subtarget->hasSSE2();
23677 if ((VT.isVector() ||
23678 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23679 isa<LoadSDNode>(St->getValue()) &&
23680 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23681 St->getChain().hasOneUse() && !St->isVolatile()) {
23682 SDNode* LdVal = St->getValue().getNode();
23683 LoadSDNode *Ld = nullptr;
23684 int TokenFactorIndex = -1;
23685 SmallVector<SDValue, 8> Ops;
23686 SDNode* ChainVal = St->getChain().getNode();
23687 // Must be a store of a load. We currently handle two cases: the load
23688 // is a direct child, and it's under an intervening TokenFactor. It is
23689 // possible to dig deeper under nested TokenFactors.
23690 if (ChainVal == LdVal)
23691 Ld = cast<LoadSDNode>(St->getChain());
23692 else if (St->getValue().hasOneUse() &&
23693 ChainVal->getOpcode() == ISD::TokenFactor) {
23694 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23695 if (ChainVal->getOperand(i).getNode() == LdVal) {
23696 TokenFactorIndex = i;
23697 Ld = cast<LoadSDNode>(St->getValue());
23699 Ops.push_back(ChainVal->getOperand(i));
23703 if (!Ld || !ISD::isNormalLoad(Ld))
23706 // If this is not the MMX case, i.e. we are just turning i64 load/store
23707 // into f64 load/store, avoid the transformation if there are multiple
23708 // uses of the loaded value.
23709 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23714 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23715 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23717 if (Subtarget->is64Bit() || F64IsLegal) {
23718 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23719 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23720 Ld->getPointerInfo(), Ld->isVolatile(),
23721 Ld->isNonTemporal(), Ld->isInvariant(),
23722 Ld->getAlignment());
23723 SDValue NewChain = NewLd.getValue(1);
23724 if (TokenFactorIndex != -1) {
23725 Ops.push_back(NewChain);
23726 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23728 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23729 St->getPointerInfo(),
23730 St->isVolatile(), St->isNonTemporal(),
23731 St->getAlignment());
23734 // Otherwise, lower to two pairs of 32-bit loads / stores.
23735 SDValue LoAddr = Ld->getBasePtr();
23736 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23737 DAG.getConstant(4, MVT::i32));
23739 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23740 Ld->getPointerInfo(),
23741 Ld->isVolatile(), Ld->isNonTemporal(),
23742 Ld->isInvariant(), Ld->getAlignment());
23743 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23744 Ld->getPointerInfo().getWithOffset(4),
23745 Ld->isVolatile(), Ld->isNonTemporal(),
23747 MinAlign(Ld->getAlignment(), 4));
23749 SDValue NewChain = LoLd.getValue(1);
23750 if (TokenFactorIndex != -1) {
23751 Ops.push_back(LoLd);
23752 Ops.push_back(HiLd);
23753 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23756 LoAddr = St->getBasePtr();
23757 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23758 DAG.getConstant(4, MVT::i32));
23760 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23761 St->getPointerInfo(),
23762 St->isVolatile(), St->isNonTemporal(),
23763 St->getAlignment());
23764 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23765 St->getPointerInfo().getWithOffset(4),
23767 St->isNonTemporal(),
23768 MinAlign(St->getAlignment(), 4));
23769 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23774 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23775 /// and return the operands for the horizontal operation in LHS and RHS. A
23776 /// horizontal operation performs the binary operation on successive elements
23777 /// of its first operand, then on successive elements of its second operand,
23778 /// returning the resulting values in a vector. For example, if
23779 /// A = < float a0, float a1, float a2, float a3 >
23781 /// B = < float b0, float b1, float b2, float b3 >
23782 /// then the result of doing a horizontal operation on A and B is
23783 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23784 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23785 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23786 /// set to A, RHS to B, and the routine returns 'true'.
23787 /// Note that the binary operation should have the property that if one of the
23788 /// operands is UNDEF then the result is UNDEF.
23789 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23790 // Look for the following pattern: if
23791 // A = < float a0, float a1, float a2, float a3 >
23792 // B = < float b0, float b1, float b2, float b3 >
23794 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23795 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23796 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23797 // which is A horizontal-op B.
23799 // At least one of the operands should be a vector shuffle.
23800 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23801 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23804 MVT VT = LHS.getSimpleValueType();
23806 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23807 "Unsupported vector type for horizontal add/sub");
23809 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23810 // operate independently on 128-bit lanes.
23811 unsigned NumElts = VT.getVectorNumElements();
23812 unsigned NumLanes = VT.getSizeInBits()/128;
23813 unsigned NumLaneElts = NumElts / NumLanes;
23814 assert((NumLaneElts % 2 == 0) &&
23815 "Vector type should have an even number of elements in each lane");
23816 unsigned HalfLaneElts = NumLaneElts/2;
23818 // View LHS in the form
23819 // LHS = VECTOR_SHUFFLE A, B, LMask
23820 // If LHS is not a shuffle then pretend it is the shuffle
23821 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23822 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23825 SmallVector<int, 16> LMask(NumElts);
23826 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23827 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23828 A = LHS.getOperand(0);
23829 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23830 B = LHS.getOperand(1);
23831 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23832 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23834 if (LHS.getOpcode() != ISD::UNDEF)
23836 for (unsigned i = 0; i != NumElts; ++i)
23840 // Likewise, view RHS in the form
23841 // RHS = VECTOR_SHUFFLE C, D, RMask
23843 SmallVector<int, 16> RMask(NumElts);
23844 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23845 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23846 C = RHS.getOperand(0);
23847 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23848 D = RHS.getOperand(1);
23849 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23850 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23852 if (RHS.getOpcode() != ISD::UNDEF)
23854 for (unsigned i = 0; i != NumElts; ++i)
23858 // Check that the shuffles are both shuffling the same vectors.
23859 if (!(A == C && B == D) && !(A == D && B == C))
23862 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23863 if (!A.getNode() && !B.getNode())
23866 // If A and B occur in reverse order in RHS, then "swap" them (which means
23867 // rewriting the mask).
23869 CommuteVectorShuffleMask(RMask, NumElts);
23871 // At this point LHS and RHS are equivalent to
23872 // LHS = VECTOR_SHUFFLE A, B, LMask
23873 // RHS = VECTOR_SHUFFLE A, B, RMask
23874 // Check that the masks correspond to performing a horizontal operation.
23875 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23876 for (unsigned i = 0; i != NumLaneElts; ++i) {
23877 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23879 // Ignore any UNDEF components.
23880 if (LIdx < 0 || RIdx < 0 ||
23881 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23882 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23885 // Check that successive elements are being operated on. If not, this is
23886 // not a horizontal operation.
23887 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23888 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23889 if (!(LIdx == Index && RIdx == Index + 1) &&
23890 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23895 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23896 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23900 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23901 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23902 const X86Subtarget *Subtarget) {
23903 EVT VT = N->getValueType(0);
23904 SDValue LHS = N->getOperand(0);
23905 SDValue RHS = N->getOperand(1);
23907 // Try to synthesize horizontal adds from adds of shuffles.
23908 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23909 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23910 isHorizontalBinOp(LHS, RHS, true))
23911 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23915 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23916 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23917 const X86Subtarget *Subtarget) {
23918 EVT VT = N->getValueType(0);
23919 SDValue LHS = N->getOperand(0);
23920 SDValue RHS = N->getOperand(1);
23922 // Try to synthesize horizontal subs from subs of shuffles.
23923 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23924 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23925 isHorizontalBinOp(LHS, RHS, false))
23926 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23930 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23931 /// X86ISD::FXOR nodes.
23932 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23933 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23934 // F[X]OR(0.0, x) -> x
23935 // F[X]OR(x, 0.0) -> x
23936 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23937 if (C->getValueAPF().isPosZero())
23938 return N->getOperand(1);
23939 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23940 if (C->getValueAPF().isPosZero())
23941 return N->getOperand(0);
23945 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23946 /// X86ISD::FMAX nodes.
23947 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23948 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23950 // Only perform optimizations if UnsafeMath is used.
23951 if (!DAG.getTarget().Options.UnsafeFPMath)
23954 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23955 // into FMINC and FMAXC, which are Commutative operations.
23956 unsigned NewOp = 0;
23957 switch (N->getOpcode()) {
23958 default: llvm_unreachable("unknown opcode");
23959 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23960 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23963 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23964 N->getOperand(0), N->getOperand(1));
23967 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23968 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23969 // FAND(0.0, x) -> 0.0
23970 // FAND(x, 0.0) -> 0.0
23971 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23972 if (C->getValueAPF().isPosZero())
23973 return N->getOperand(0);
23974 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23975 if (C->getValueAPF().isPosZero())
23976 return N->getOperand(1);
23980 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23981 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23982 // FANDN(x, 0.0) -> 0.0
23983 // FANDN(0.0, x) -> x
23984 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23985 if (C->getValueAPF().isPosZero())
23986 return N->getOperand(1);
23987 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23988 if (C->getValueAPF().isPosZero())
23989 return N->getOperand(1);
23993 static SDValue PerformBTCombine(SDNode *N,
23995 TargetLowering::DAGCombinerInfo &DCI) {
23996 // BT ignores high bits in the bit index operand.
23997 SDValue Op1 = N->getOperand(1);
23998 if (Op1.hasOneUse()) {
23999 unsigned BitWidth = Op1.getValueSizeInBits();
24000 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24001 APInt KnownZero, KnownOne;
24002 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24003 !DCI.isBeforeLegalizeOps());
24004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24005 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24006 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24007 DCI.CommitTargetLoweringOpt(TLO);
24012 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24013 SDValue Op = N->getOperand(0);
24014 if (Op.getOpcode() == ISD::BITCAST)
24015 Op = Op.getOperand(0);
24016 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24017 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24018 VT.getVectorElementType().getSizeInBits() ==
24019 OpVT.getVectorElementType().getSizeInBits()) {
24020 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24025 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24026 const X86Subtarget *Subtarget) {
24027 EVT VT = N->getValueType(0);
24028 if (!VT.isVector())
24031 SDValue N0 = N->getOperand(0);
24032 SDValue N1 = N->getOperand(1);
24033 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24036 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24037 // both SSE and AVX2 since there is no sign-extended shift right
24038 // operation on a vector with 64-bit elements.
24039 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24040 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24041 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24042 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24043 SDValue N00 = N0.getOperand(0);
24045 // EXTLOAD has a better solution on AVX2,
24046 // it may be replaced with X86ISD::VSEXT node.
24047 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24048 if (!ISD::isNormalLoad(N00.getNode()))
24051 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24052 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24054 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24060 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24061 TargetLowering::DAGCombinerInfo &DCI,
24062 const X86Subtarget *Subtarget) {
24063 if (!DCI.isBeforeLegalizeOps())
24066 if (!Subtarget->hasFp256())
24069 EVT VT = N->getValueType(0);
24070 if (VT.isVector() && VT.getSizeInBits() == 256) {
24071 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24079 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24080 const X86Subtarget* Subtarget) {
24082 EVT VT = N->getValueType(0);
24084 // Let legalize expand this if it isn't a legal type yet.
24085 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24088 EVT ScalarVT = VT.getScalarType();
24089 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24090 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24093 SDValue A = N->getOperand(0);
24094 SDValue B = N->getOperand(1);
24095 SDValue C = N->getOperand(2);
24097 bool NegA = (A.getOpcode() == ISD::FNEG);
24098 bool NegB = (B.getOpcode() == ISD::FNEG);
24099 bool NegC = (C.getOpcode() == ISD::FNEG);
24101 // Negative multiplication when NegA xor NegB
24102 bool NegMul = (NegA != NegB);
24104 A = A.getOperand(0);
24106 B = B.getOperand(0);
24108 C = C.getOperand(0);
24112 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24114 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24116 return DAG.getNode(Opcode, dl, VT, A, B, C);
24119 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24120 TargetLowering::DAGCombinerInfo &DCI,
24121 const X86Subtarget *Subtarget) {
24122 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24123 // (and (i32 x86isd::setcc_carry), 1)
24124 // This eliminates the zext. This transformation is necessary because
24125 // ISD::SETCC is always legalized to i8.
24127 SDValue N0 = N->getOperand(0);
24128 EVT VT = N->getValueType(0);
24130 if (N0.getOpcode() == ISD::AND &&
24132 N0.getOperand(0).hasOneUse()) {
24133 SDValue N00 = N0.getOperand(0);
24134 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24135 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24136 if (!C || C->getZExtValue() != 1)
24138 return DAG.getNode(ISD::AND, dl, VT,
24139 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24140 N00.getOperand(0), N00.getOperand(1)),
24141 DAG.getConstant(1, VT));
24145 if (N0.getOpcode() == ISD::TRUNCATE &&
24147 N0.getOperand(0).hasOneUse()) {
24148 SDValue N00 = N0.getOperand(0);
24149 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24150 return DAG.getNode(ISD::AND, dl, VT,
24151 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24152 N00.getOperand(0), N00.getOperand(1)),
24153 DAG.getConstant(1, VT));
24156 if (VT.is256BitVector()) {
24157 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24165 // Optimize x == -y --> x+y == 0
24166 // x != -y --> x+y != 0
24167 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24168 const X86Subtarget* Subtarget) {
24169 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24170 SDValue LHS = N->getOperand(0);
24171 SDValue RHS = N->getOperand(1);
24172 EVT VT = N->getValueType(0);
24175 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24177 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24178 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24179 LHS.getValueType(), RHS, LHS.getOperand(1));
24180 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24181 addV, DAG.getConstant(0, addV.getValueType()), CC);
24183 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24185 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24186 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24187 RHS.getValueType(), LHS, RHS.getOperand(1));
24188 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24189 addV, DAG.getConstant(0, addV.getValueType()), CC);
24192 if (VT.getScalarType() == MVT::i1) {
24193 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24194 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24195 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24196 if (!IsSEXT0 && !IsVZero0)
24198 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24199 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24200 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24202 if (!IsSEXT1 && !IsVZero1)
24205 if (IsSEXT0 && IsVZero1) {
24206 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24207 if (CC == ISD::SETEQ)
24208 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24209 return LHS.getOperand(0);
24211 if (IsSEXT1 && IsVZero0) {
24212 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24213 if (CC == ISD::SETEQ)
24214 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24215 return RHS.getOperand(0);
24222 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24223 const X86Subtarget *Subtarget) {
24225 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24226 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24227 "X86insertps is only defined for v4x32");
24229 SDValue Ld = N->getOperand(1);
24230 if (MayFoldLoad(Ld)) {
24231 // Extract the countS bits from the immediate so we can get the proper
24232 // address when narrowing the vector load to a specific element.
24233 // When the second source op is a memory address, interps doesn't use
24234 // countS and just gets an f32 from that address.
24235 unsigned DestIndex =
24236 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24237 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24241 // Create this as a scalar to vector to match the instruction pattern.
24242 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24243 // countS bits are ignored when loading from memory on insertps, which
24244 // means we don't need to explicitly set them to 0.
24245 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24246 LoadScalarToVector, N->getOperand(2));
24249 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24250 // as "sbb reg,reg", since it can be extended without zext and produces
24251 // an all-ones bit which is more useful than 0/1 in some cases.
24252 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24255 return DAG.getNode(ISD::AND, DL, VT,
24256 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24257 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24258 DAG.getConstant(1, VT));
24259 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24260 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24261 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24262 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24265 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24266 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24267 TargetLowering::DAGCombinerInfo &DCI,
24268 const X86Subtarget *Subtarget) {
24270 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24271 SDValue EFLAGS = N->getOperand(1);
24273 if (CC == X86::COND_A) {
24274 // Try to convert COND_A into COND_B in an attempt to facilitate
24275 // materializing "setb reg".
24277 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24278 // cannot take an immediate as its first operand.
24280 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24281 EFLAGS.getValueType().isInteger() &&
24282 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24283 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24284 EFLAGS.getNode()->getVTList(),
24285 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24286 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24287 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24291 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24292 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24294 if (CC == X86::COND_B)
24295 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24299 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24300 if (Flags.getNode()) {
24301 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24302 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24308 // Optimize branch condition evaluation.
24310 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24311 TargetLowering::DAGCombinerInfo &DCI,
24312 const X86Subtarget *Subtarget) {
24314 SDValue Chain = N->getOperand(0);
24315 SDValue Dest = N->getOperand(1);
24316 SDValue EFLAGS = N->getOperand(3);
24317 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24321 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24322 if (Flags.getNode()) {
24323 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24324 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24331 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24332 SelectionDAG &DAG) {
24333 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24334 // optimize away operation when it's from a constant.
24336 // The general transformation is:
24337 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24338 // AND(VECTOR_CMP(x,y), constant2)
24339 // constant2 = UNARYOP(constant)
24341 // Early exit if this isn't a vector operation, the operand of the
24342 // unary operation isn't a bitwise AND, or if the sizes of the operations
24343 // aren't the same.
24344 EVT VT = N->getValueType(0);
24345 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24346 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24347 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24350 // Now check that the other operand of the AND is a constant. We could
24351 // make the transformation for non-constant splats as well, but it's unclear
24352 // that would be a benefit as it would not eliminate any operations, just
24353 // perform one more step in scalar code before moving to the vector unit.
24354 if (BuildVectorSDNode *BV =
24355 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24356 // Bail out if the vector isn't a constant.
24357 if (!BV->isConstant())
24360 // Everything checks out. Build up the new and improved node.
24362 EVT IntVT = BV->getValueType(0);
24363 // Create a new constant of the appropriate type for the transformed
24365 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24366 // The AND node needs bitcasts to/from an integer vector type around it.
24367 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24368 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24369 N->getOperand(0)->getOperand(0), MaskConst);
24370 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24377 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24378 const X86TargetLowering *XTLI) {
24379 // First try to optimize away the conversion entirely when it's
24380 // conditionally from a constant. Vectors only.
24381 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24382 if (Res != SDValue())
24385 // Now move on to more general possibilities.
24386 SDValue Op0 = N->getOperand(0);
24387 EVT InVT = Op0->getValueType(0);
24389 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24390 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24392 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24393 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24394 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24397 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24398 // a 32-bit target where SSE doesn't support i64->FP operations.
24399 if (Op0.getOpcode() == ISD::LOAD) {
24400 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24401 EVT VT = Ld->getValueType(0);
24402 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24403 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24404 !XTLI->getSubtarget()->is64Bit() &&
24406 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24407 Ld->getChain(), Op0, DAG);
24408 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24415 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24416 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24417 X86TargetLowering::DAGCombinerInfo &DCI) {
24418 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24419 // the result is either zero or one (depending on the input carry bit).
24420 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24421 if (X86::isZeroNode(N->getOperand(0)) &&
24422 X86::isZeroNode(N->getOperand(1)) &&
24423 // We don't have a good way to replace an EFLAGS use, so only do this when
24425 SDValue(N, 1).use_empty()) {
24427 EVT VT = N->getValueType(0);
24428 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24429 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24430 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24431 DAG.getConstant(X86::COND_B,MVT::i8),
24433 DAG.getConstant(1, VT));
24434 return DCI.CombineTo(N, Res1, CarryOut);
24440 // fold (add Y, (sete X, 0)) -> adc 0, Y
24441 // (add Y, (setne X, 0)) -> sbb -1, Y
24442 // (sub (sete X, 0), Y) -> sbb 0, Y
24443 // (sub (setne X, 0), Y) -> adc -1, Y
24444 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24447 // Look through ZExts.
24448 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24449 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24452 SDValue SetCC = Ext.getOperand(0);
24453 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24456 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24457 if (CC != X86::COND_E && CC != X86::COND_NE)
24460 SDValue Cmp = SetCC.getOperand(1);
24461 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24462 !X86::isZeroNode(Cmp.getOperand(1)) ||
24463 !Cmp.getOperand(0).getValueType().isInteger())
24466 SDValue CmpOp0 = Cmp.getOperand(0);
24467 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24468 DAG.getConstant(1, CmpOp0.getValueType()));
24470 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24471 if (CC == X86::COND_NE)
24472 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24473 DL, OtherVal.getValueType(), OtherVal,
24474 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24475 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24476 DL, OtherVal.getValueType(), OtherVal,
24477 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24480 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24481 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24482 const X86Subtarget *Subtarget) {
24483 EVT VT = N->getValueType(0);
24484 SDValue Op0 = N->getOperand(0);
24485 SDValue Op1 = N->getOperand(1);
24487 // Try to synthesize horizontal adds from adds of shuffles.
24488 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24489 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24490 isHorizontalBinOp(Op0, Op1, true))
24491 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24493 return OptimizeConditionalInDecrement(N, DAG);
24496 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24497 const X86Subtarget *Subtarget) {
24498 SDValue Op0 = N->getOperand(0);
24499 SDValue Op1 = N->getOperand(1);
24501 // X86 can't encode an immediate LHS of a sub. See if we can push the
24502 // negation into a preceding instruction.
24503 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24504 // If the RHS of the sub is a XOR with one use and a constant, invert the
24505 // immediate. Then add one to the LHS of the sub so we can turn
24506 // X-Y -> X+~Y+1, saving one register.
24507 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24508 isa<ConstantSDNode>(Op1.getOperand(1))) {
24509 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24510 EVT VT = Op0.getValueType();
24511 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24513 DAG.getConstant(~XorC, VT));
24514 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24515 DAG.getConstant(C->getAPIntValue()+1, VT));
24519 // Try to synthesize horizontal adds from adds of shuffles.
24520 EVT VT = N->getValueType(0);
24521 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24522 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24523 isHorizontalBinOp(Op0, Op1, true))
24524 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24526 return OptimizeConditionalInDecrement(N, DAG);
24529 /// performVZEXTCombine - Performs build vector combines
24530 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24531 TargetLowering::DAGCombinerInfo &DCI,
24532 const X86Subtarget *Subtarget) {
24533 // (vzext (bitcast (vzext (x)) -> (vzext x)
24534 SDValue In = N->getOperand(0);
24535 while (In.getOpcode() == ISD::BITCAST)
24536 In = In.getOperand(0);
24538 if (In.getOpcode() != X86ISD::VZEXT)
24541 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24545 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24546 DAGCombinerInfo &DCI) const {
24547 SelectionDAG &DAG = DCI.DAG;
24548 switch (N->getOpcode()) {
24550 case ISD::EXTRACT_VECTOR_ELT:
24551 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24553 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24554 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24555 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24556 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24557 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24558 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24561 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24562 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24563 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24564 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24565 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24566 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24567 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24568 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24569 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24571 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24573 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24574 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24575 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24576 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24577 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24578 case ISD::ANY_EXTEND:
24579 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24580 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24581 case ISD::SIGN_EXTEND_INREG:
24582 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24583 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24584 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24585 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24586 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24587 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24588 case X86ISD::SHUFP: // Handle all target specific shuffles
24589 case X86ISD::PALIGNR:
24590 case X86ISD::UNPCKH:
24591 case X86ISD::UNPCKL:
24592 case X86ISD::MOVHLPS:
24593 case X86ISD::MOVLHPS:
24594 case X86ISD::PSHUFB:
24595 case X86ISD::PSHUFD:
24596 case X86ISD::PSHUFHW:
24597 case X86ISD::PSHUFLW:
24598 case X86ISD::MOVSS:
24599 case X86ISD::MOVSD:
24600 case X86ISD::VPERMILPI:
24601 case X86ISD::VPERM2X128:
24602 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24603 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24604 case ISD::INTRINSIC_WO_CHAIN:
24605 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24606 case X86ISD::INSERTPS:
24607 return PerformINSERTPSCombine(N, DAG, Subtarget);
24608 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24614 /// isTypeDesirableForOp - Return true if the target has native support for
24615 /// the specified value type and it is 'desirable' to use the type for the
24616 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24617 /// instruction encodings are longer and some i16 instructions are slow.
24618 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24619 if (!isTypeLegal(VT))
24621 if (VT != MVT::i16)
24628 case ISD::SIGN_EXTEND:
24629 case ISD::ZERO_EXTEND:
24630 case ISD::ANY_EXTEND:
24643 /// IsDesirableToPromoteOp - This method query the target whether it is
24644 /// beneficial for dag combiner to promote the specified node. If true, it
24645 /// should return the desired promotion type by reference.
24646 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24647 EVT VT = Op.getValueType();
24648 if (VT != MVT::i16)
24651 bool Promote = false;
24652 bool Commute = false;
24653 switch (Op.getOpcode()) {
24656 LoadSDNode *LD = cast<LoadSDNode>(Op);
24657 // If the non-extending load has a single use and it's not live out, then it
24658 // might be folded.
24659 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24660 Op.hasOneUse()*/) {
24661 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24662 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24663 // The only case where we'd want to promote LOAD (rather then it being
24664 // promoted as an operand is when it's only use is liveout.
24665 if (UI->getOpcode() != ISD::CopyToReg)
24672 case ISD::SIGN_EXTEND:
24673 case ISD::ZERO_EXTEND:
24674 case ISD::ANY_EXTEND:
24679 SDValue N0 = Op.getOperand(0);
24680 // Look out for (store (shl (load), x)).
24681 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24694 SDValue N0 = Op.getOperand(0);
24695 SDValue N1 = Op.getOperand(1);
24696 if (!Commute && MayFoldLoad(N1))
24698 // Avoid disabling potential load folding opportunities.
24699 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24701 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24711 //===----------------------------------------------------------------------===//
24712 // X86 Inline Assembly Support
24713 //===----------------------------------------------------------------------===//
24716 // Helper to match a string separated by whitespace.
24717 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24718 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24720 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24721 StringRef piece(*args[i]);
24722 if (!s.startswith(piece)) // Check if the piece matches.
24725 s = s.substr(piece.size());
24726 StringRef::size_type pos = s.find_first_not_of(" \t");
24727 if (pos == 0) // We matched a prefix.
24735 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24738 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24740 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24741 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24742 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24743 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24745 if (AsmPieces.size() == 3)
24747 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24754 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24755 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24757 std::string AsmStr = IA->getAsmString();
24759 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24760 if (!Ty || Ty->getBitWidth() % 16 != 0)
24763 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24764 SmallVector<StringRef, 4> AsmPieces;
24765 SplitString(AsmStr, AsmPieces, ";\n");
24767 switch (AsmPieces.size()) {
24768 default: return false;
24770 // FIXME: this should verify that we are targeting a 486 or better. If not,
24771 // we will turn this bswap into something that will be lowered to logical
24772 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24773 // lower so don't worry about this.
24775 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24776 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24777 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24778 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24779 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24780 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24781 // No need to check constraints, nothing other than the equivalent of
24782 // "=r,0" would be valid here.
24783 return IntrinsicLowering::LowerToByteSwap(CI);
24786 // rorw $$8, ${0:w} --> llvm.bswap.i16
24787 if (CI->getType()->isIntegerTy(16) &&
24788 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24789 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24790 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24792 const std::string &ConstraintsStr = IA->getConstraintString();
24793 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24794 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24795 if (clobbersFlagRegisters(AsmPieces))
24796 return IntrinsicLowering::LowerToByteSwap(CI);
24800 if (CI->getType()->isIntegerTy(32) &&
24801 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24802 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24803 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24804 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24806 const std::string &ConstraintsStr = IA->getConstraintString();
24807 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24808 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24809 if (clobbersFlagRegisters(AsmPieces))
24810 return IntrinsicLowering::LowerToByteSwap(CI);
24813 if (CI->getType()->isIntegerTy(64)) {
24814 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24815 if (Constraints.size() >= 2 &&
24816 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24817 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24818 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24819 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24820 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24821 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24822 return IntrinsicLowering::LowerToByteSwap(CI);
24830 /// getConstraintType - Given a constraint letter, return the type of
24831 /// constraint it is for this target.
24832 X86TargetLowering::ConstraintType
24833 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24834 if (Constraint.size() == 1) {
24835 switch (Constraint[0]) {
24846 return C_RegisterClass;
24870 return TargetLowering::getConstraintType(Constraint);
24873 /// Examine constraint type and operand type and determine a weight value.
24874 /// This object must already have been set up with the operand type
24875 /// and the current alternative constraint selected.
24876 TargetLowering::ConstraintWeight
24877 X86TargetLowering::getSingleConstraintMatchWeight(
24878 AsmOperandInfo &info, const char *constraint) const {
24879 ConstraintWeight weight = CW_Invalid;
24880 Value *CallOperandVal = info.CallOperandVal;
24881 // If we don't have a value, we can't do a match,
24882 // but allow it at the lowest weight.
24883 if (!CallOperandVal)
24885 Type *type = CallOperandVal->getType();
24886 // Look at the constraint type.
24887 switch (*constraint) {
24889 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24900 if (CallOperandVal->getType()->isIntegerTy())
24901 weight = CW_SpecificReg;
24906 if (type->isFloatingPointTy())
24907 weight = CW_SpecificReg;
24910 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24911 weight = CW_SpecificReg;
24915 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24916 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24917 weight = CW_Register;
24920 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24921 if (C->getZExtValue() <= 31)
24922 weight = CW_Constant;
24926 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24927 if (C->getZExtValue() <= 63)
24928 weight = CW_Constant;
24932 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24933 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24934 weight = CW_Constant;
24938 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24939 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24940 weight = CW_Constant;
24944 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24945 if (C->getZExtValue() <= 3)
24946 weight = CW_Constant;
24950 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24951 if (C->getZExtValue() <= 0xff)
24952 weight = CW_Constant;
24957 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24958 weight = CW_Constant;
24962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24963 if ((C->getSExtValue() >= -0x80000000LL) &&
24964 (C->getSExtValue() <= 0x7fffffffLL))
24965 weight = CW_Constant;
24969 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24970 if (C->getZExtValue() <= 0xffffffff)
24971 weight = CW_Constant;
24978 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24979 /// with another that has more specific requirements based on the type of the
24980 /// corresponding operand.
24981 const char *X86TargetLowering::
24982 LowerXConstraint(EVT ConstraintVT) const {
24983 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24984 // 'f' like normal targets.
24985 if (ConstraintVT.isFloatingPoint()) {
24986 if (Subtarget->hasSSE2())
24988 if (Subtarget->hasSSE1())
24992 return TargetLowering::LowerXConstraint(ConstraintVT);
24995 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24996 /// vector. If it is invalid, don't add anything to Ops.
24997 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24998 std::string &Constraint,
24999 std::vector<SDValue>&Ops,
25000 SelectionDAG &DAG) const {
25003 // Only support length 1 constraints for now.
25004 if (Constraint.length() > 1) return;
25006 char ConstraintLetter = Constraint[0];
25007 switch (ConstraintLetter) {
25010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25011 if (C->getZExtValue() <= 31) {
25012 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25018 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25019 if (C->getZExtValue() <= 63) {
25020 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25027 if (isInt<8>(C->getSExtValue())) {
25028 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25035 if (C->getZExtValue() <= 255) {
25036 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25042 // 32-bit signed value
25043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25044 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25045 C->getSExtValue())) {
25046 // Widen to 64 bits here to get it sign extended.
25047 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25050 // FIXME gcc accepts some relocatable values here too, but only in certain
25051 // memory models; it's complicated.
25056 // 32-bit unsigned value
25057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25058 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25059 C->getZExtValue())) {
25060 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25064 // FIXME gcc accepts some relocatable values here too, but only in certain
25065 // memory models; it's complicated.
25069 // Literal immediates are always ok.
25070 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25071 // Widen to 64 bits here to get it sign extended.
25072 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25076 // In any sort of PIC mode addresses need to be computed at runtime by
25077 // adding in a register or some sort of table lookup. These can't
25078 // be used as immediates.
25079 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25082 // If we are in non-pic codegen mode, we allow the address of a global (with
25083 // an optional displacement) to be used with 'i'.
25084 GlobalAddressSDNode *GA = nullptr;
25085 int64_t Offset = 0;
25087 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25089 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25090 Offset += GA->getOffset();
25092 } else if (Op.getOpcode() == ISD::ADD) {
25093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25094 Offset += C->getZExtValue();
25095 Op = Op.getOperand(0);
25098 } else if (Op.getOpcode() == ISD::SUB) {
25099 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25100 Offset += -C->getZExtValue();
25101 Op = Op.getOperand(0);
25106 // Otherwise, this isn't something we can handle, reject it.
25110 const GlobalValue *GV = GA->getGlobal();
25111 // If we require an extra load to get this address, as in PIC mode, we
25112 // can't accept it.
25113 if (isGlobalStubReference(
25114 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25117 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25118 GA->getValueType(0), Offset);
25123 if (Result.getNode()) {
25124 Ops.push_back(Result);
25127 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25130 std::pair<unsigned, const TargetRegisterClass*>
25131 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25133 // First, see if this is a constraint that directly corresponds to an LLVM
25135 if (Constraint.size() == 1) {
25136 // GCC Constraint Letters
25137 switch (Constraint[0]) {
25139 // TODO: Slight differences here in allocation order and leaving
25140 // RIP in the class. Do they matter any more here than they do
25141 // in the normal allocation?
25142 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25143 if (Subtarget->is64Bit()) {
25144 if (VT == MVT::i32 || VT == MVT::f32)
25145 return std::make_pair(0U, &X86::GR32RegClass);
25146 if (VT == MVT::i16)
25147 return std::make_pair(0U, &X86::GR16RegClass);
25148 if (VT == MVT::i8 || VT == MVT::i1)
25149 return std::make_pair(0U, &X86::GR8RegClass);
25150 if (VT == MVT::i64 || VT == MVT::f64)
25151 return std::make_pair(0U, &X86::GR64RegClass);
25154 // 32-bit fallthrough
25155 case 'Q': // Q_REGS
25156 if (VT == MVT::i32 || VT == MVT::f32)
25157 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25158 if (VT == MVT::i16)
25159 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25160 if (VT == MVT::i8 || VT == MVT::i1)
25161 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25162 if (VT == MVT::i64)
25163 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25165 case 'r': // GENERAL_REGS
25166 case 'l': // INDEX_REGS
25167 if (VT == MVT::i8 || VT == MVT::i1)
25168 return std::make_pair(0U, &X86::GR8RegClass);
25169 if (VT == MVT::i16)
25170 return std::make_pair(0U, &X86::GR16RegClass);
25171 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25172 return std::make_pair(0U, &X86::GR32RegClass);
25173 return std::make_pair(0U, &X86::GR64RegClass);
25174 case 'R': // LEGACY_REGS
25175 if (VT == MVT::i8 || VT == MVT::i1)
25176 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25177 if (VT == MVT::i16)
25178 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25179 if (VT == MVT::i32 || !Subtarget->is64Bit())
25180 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25181 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25182 case 'f': // FP Stack registers.
25183 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25184 // value to the correct fpstack register class.
25185 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25186 return std::make_pair(0U, &X86::RFP32RegClass);
25187 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25188 return std::make_pair(0U, &X86::RFP64RegClass);
25189 return std::make_pair(0U, &X86::RFP80RegClass);
25190 case 'y': // MMX_REGS if MMX allowed.
25191 if (!Subtarget->hasMMX()) break;
25192 return std::make_pair(0U, &X86::VR64RegClass);
25193 case 'Y': // SSE_REGS if SSE2 allowed
25194 if (!Subtarget->hasSSE2()) break;
25196 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25197 if (!Subtarget->hasSSE1()) break;
25199 switch (VT.SimpleTy) {
25201 // Scalar SSE types.
25204 return std::make_pair(0U, &X86::FR32RegClass);
25207 return std::make_pair(0U, &X86::FR64RegClass);
25215 return std::make_pair(0U, &X86::VR128RegClass);
25223 return std::make_pair(0U, &X86::VR256RegClass);
25228 return std::make_pair(0U, &X86::VR512RegClass);
25234 // Use the default implementation in TargetLowering to convert the register
25235 // constraint into a member of a register class.
25236 std::pair<unsigned, const TargetRegisterClass*> Res;
25237 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25239 // Not found as a standard register?
25241 // Map st(0) -> st(7) -> ST0
25242 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25243 tolower(Constraint[1]) == 's' &&
25244 tolower(Constraint[2]) == 't' &&
25245 Constraint[3] == '(' &&
25246 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25247 Constraint[5] == ')' &&
25248 Constraint[6] == '}') {
25250 Res.first = X86::FP0+Constraint[4]-'0';
25251 Res.second = &X86::RFP80RegClass;
25255 // GCC allows "st(0)" to be called just plain "st".
25256 if (StringRef("{st}").equals_lower(Constraint)) {
25257 Res.first = X86::FP0;
25258 Res.second = &X86::RFP80RegClass;
25263 if (StringRef("{flags}").equals_lower(Constraint)) {
25264 Res.first = X86::EFLAGS;
25265 Res.second = &X86::CCRRegClass;
25269 // 'A' means EAX + EDX.
25270 if (Constraint == "A") {
25271 Res.first = X86::EAX;
25272 Res.second = &X86::GR32_ADRegClass;
25278 // Otherwise, check to see if this is a register class of the wrong value
25279 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25280 // turn into {ax},{dx}.
25281 if (Res.second->hasType(VT))
25282 return Res; // Correct type already, nothing to do.
25284 // All of the single-register GCC register classes map their values onto
25285 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25286 // really want an 8-bit or 32-bit register, map to the appropriate register
25287 // class and return the appropriate register.
25288 if (Res.second == &X86::GR16RegClass) {
25289 if (VT == MVT::i8 || VT == MVT::i1) {
25290 unsigned DestReg = 0;
25291 switch (Res.first) {
25293 case X86::AX: DestReg = X86::AL; break;
25294 case X86::DX: DestReg = X86::DL; break;
25295 case X86::CX: DestReg = X86::CL; break;
25296 case X86::BX: DestReg = X86::BL; break;
25299 Res.first = DestReg;
25300 Res.second = &X86::GR8RegClass;
25302 } else if (VT == MVT::i32 || VT == MVT::f32) {
25303 unsigned DestReg = 0;
25304 switch (Res.first) {
25306 case X86::AX: DestReg = X86::EAX; break;
25307 case X86::DX: DestReg = X86::EDX; break;
25308 case X86::CX: DestReg = X86::ECX; break;
25309 case X86::BX: DestReg = X86::EBX; break;
25310 case X86::SI: DestReg = X86::ESI; break;
25311 case X86::DI: DestReg = X86::EDI; break;
25312 case X86::BP: DestReg = X86::EBP; break;
25313 case X86::SP: DestReg = X86::ESP; break;
25316 Res.first = DestReg;
25317 Res.second = &X86::GR32RegClass;
25319 } else if (VT == MVT::i64 || VT == MVT::f64) {
25320 unsigned DestReg = 0;
25321 switch (Res.first) {
25323 case X86::AX: DestReg = X86::RAX; break;
25324 case X86::DX: DestReg = X86::RDX; break;
25325 case X86::CX: DestReg = X86::RCX; break;
25326 case X86::BX: DestReg = X86::RBX; break;
25327 case X86::SI: DestReg = X86::RSI; break;
25328 case X86::DI: DestReg = X86::RDI; break;
25329 case X86::BP: DestReg = X86::RBP; break;
25330 case X86::SP: DestReg = X86::RSP; break;
25333 Res.first = DestReg;
25334 Res.second = &X86::GR64RegClass;
25337 } else if (Res.second == &X86::FR32RegClass ||
25338 Res.second == &X86::FR64RegClass ||
25339 Res.second == &X86::VR128RegClass ||
25340 Res.second == &X86::VR256RegClass ||
25341 Res.second == &X86::FR32XRegClass ||
25342 Res.second == &X86::FR64XRegClass ||
25343 Res.second == &X86::VR128XRegClass ||
25344 Res.second == &X86::VR256XRegClass ||
25345 Res.second == &X86::VR512RegClass) {
25346 // Handle references to XMM physical registers that got mapped into the
25347 // wrong class. This can happen with constraints like {xmm0} where the
25348 // target independent register mapper will just pick the first match it can
25349 // find, ignoring the required type.
25351 if (VT == MVT::f32 || VT == MVT::i32)
25352 Res.second = &X86::FR32RegClass;
25353 else if (VT == MVT::f64 || VT == MVT::i64)
25354 Res.second = &X86::FR64RegClass;
25355 else if (X86::VR128RegClass.hasType(VT))
25356 Res.second = &X86::VR128RegClass;
25357 else if (X86::VR256RegClass.hasType(VT))
25358 Res.second = &X86::VR256RegClass;
25359 else if (X86::VR512RegClass.hasType(VT))
25360 Res.second = &X86::VR512RegClass;
25366 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25368 // Scaling factors are not free at all.
25369 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25370 // will take 2 allocations in the out of order engine instead of 1
25371 // for plain addressing mode, i.e. inst (reg1).
25373 // vaddps (%rsi,%drx), %ymm0, %ymm1
25374 // Requires two allocations (one for the load, one for the computation)
25376 // vaddps (%rsi), %ymm0, %ymm1
25377 // Requires just 1 allocation, i.e., freeing allocations for other operations
25378 // and having less micro operations to execute.
25380 // For some X86 architectures, this is even worse because for instance for
25381 // stores, the complex addressing mode forces the instruction to use the
25382 // "load" ports instead of the dedicated "store" port.
25383 // E.g., on Haswell:
25384 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25385 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25386 if (isLegalAddressingMode(AM, Ty))
25387 // Scale represents reg2 * scale, thus account for 1
25388 // as soon as we use a second register.
25389 return AM.Scale != 0;
25393 bool X86TargetLowering::isTargetFTOL() const {
25394 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();