1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1737 return VT.changeVectorElementTypeToInteger();
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1810 if (Subtarget->hasInt256())
1812 if (Subtarget->hasFp256())
1815 if (Subtarget->hasSSE2())
1817 if (Subtarget->hasSSE1())
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1827 if (Subtarget->is64Bit() && Size >= 8)
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1906 switch (VT.SimpleTy) {
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1913 RRC = &X86::VR64RegClass;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1920 RRC = &X86::VR128RegClass;
1923 return std::make_pair(RRC, Cost);
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2098 if (!N->hasNUsesOfValue(1, 0))
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2210 enum StructReturnType {
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3948 for (i = 0; i != NumLaneElts; ++i) {
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4013 return isAlignrMask(Mask, VT, false);
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4023 return isAlignrMask(Mask, VT, true);
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4037 Mask[i] = idx - NumElems;
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4094 if ((signed)(Idx - l) != MaskVal[i])
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4108 unsigned NumElems = VT.getVectorNumElements();
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4127 unsigned NumElems = VT.getVectorNumElements();
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4201 else if (Mask[i] == i + 4)
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4214 // Some special combinations that can be optimized.
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4239 if (!MatchEvenMask && !MatchOddMask)
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4287 if (!isUndefOrEqual(BitI1, NumElts))
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4325 if (isUndefOrEqual(BitI1, NumElts))
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4371 if (!isUndefOrEqual(BitI1, j))
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4406 if (!isUndefOrEqual(BitI1, j))
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4442 if (!VT.is128BitVector())
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4489 return MatchA && MatchB;
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4513 return (FstHalf | (SndHalf << 4));
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4528 Imm8 |= Mask[i] << (i*2);
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4602 if (!isUndefOrEqual(Mask[0], 0))
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4669 unsigned NumElts = VT.getVectorNumElements();
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4707 // The index should be aligned on a vecWidth-bit boundary.
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4725 // The index should be aligned on a vecWidth-bit boundary.
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4937 bool X86::isZeroNode(SDValue Elt) {
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4952 if (VT.getVectorNumElements() != 4)
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4973 *LD = cast<LoadSDNode>(N);
4977 // Test whether the given value is a vector value which will be legalized
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4987 case ISD::ConstantFP:
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5158 Mask.push_back(i + NumElems);
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5258 return getLegalSplat(DAG, V1, EltNo);
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFB: {
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5375 DecodePSHUFBMask(RawMask, Mask);
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5398 DecodePSHUFBMask(C, Mask);
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6016 MVT VT = Op.getSimpleValueType();
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6025 switch (Op.getOpcode()) {
6027 // Unknown pattern found.
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6158 // Unsupported broadcast.
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6206 unsigned NumElems = Op.getNumOperands();
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6224 InsertIndices.push_back(i);
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6249 if (ExtractedFromVec == VecIn1)
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6255 if (!VecIn1.getNode())
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6310 if (In != Op.getOperand(0))
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6434 ExpectedVExtractIdx += 2;
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6587 if (InVec1 != Op1.getOperand(0))
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6653 if (!Subtarget->hasAVX())
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6709 // Convert this build_vector into a pair of horizontal binop followed by
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6737 // Convert this build_vector into two horizontal add/sub followed by
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6803 NonZeros |= (1 << i);
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6990 if (V.getNode()) return V;
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7016 V[i] = V[i*2]; // Must be a zero vector.
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7079 V[i] = DAG.getUNDEF(VT);
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7172 /// \brief Helper function to classify a mask as a single-input mask.
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7182 if (M >= (int)Mask.size())
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7294 /// \brief Try to emit a blend instruction for a shuffle.
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7316 switch (VT.SimpleTy) {
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7415 llvm_unreachable("Not a supported integer vector type!");
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7490 // The identity rotation isn't interesting, stop.
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7569 // If this is an index into a build_vector node, dig out the input value and
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7649 // Otherwise emit a sequence of unpacks.
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7685 auto Lower = [&](int Scale) -> SDValue {
7688 for (int i = 0; i < NumElements; ++i) {
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7696 // We no lorger are in the anyext case.
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7737 // No viable ext lowering found.
7741 /// \brief Try to lower insertion of a single element into a zero vector.
7743 /// This is a common pattern that we have especially efficient patterns to lower
7744 /// across all subtarget feature sets.
7745 static SDValue lowerVectorShuffleAsElementInsertion(
7746 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7747 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7748 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7750 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7751 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7753 if (Mask.size() == 2) {
7754 if (!Zeroable[V2Index ^ 1]) {
7755 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7756 // with 2 to flip from {2,3} to {0,1} and vice versa.
7757 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7758 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7759 if (Zeroable[V2Index])
7760 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7767 if (i != V2Index && !Zeroable[i])
7768 return SDValue(); // Not inserting into a zero vector.
7771 // Check for a single input from a SCALAR_TO_VECTOR node.
7772 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7773 // all the smarts here sunk into that routine. However, the current
7774 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7775 // vector shuffle lowering is dead.
7776 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7777 Mask[V2Index] == (int)Mask.size()) ||
7778 V2.getOpcode() == ISD::BUILD_VECTOR))
7781 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7783 // First, we need to zext the scalar if it is smaller than an i32.
7785 MVT EltVT = VT.getVectorElementType();
7786 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7787 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7788 // Zero-extend directly to i32.
7790 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7793 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7794 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7796 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7799 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7800 // the desired position. Otherwise it is more efficient to do a vector
7801 // shift left. We know that we can do a vector shift left because all
7802 // the inputs are zero.
7803 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7804 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7805 V2Shuffle[V2Index] = 0;
7806 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7808 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7810 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7812 V2Index * EltVT.getSizeInBits(),
7813 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7814 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7820 /// \brief Try to lower broadcast of a single element.
7822 /// For convenience, this code also bundles all of the subtarget feature set
7823 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7824 /// a convenient way to factor it out.
7825 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7827 const X86Subtarget *Subtarget,
7828 SelectionDAG &DAG) {
7829 if (!Subtarget->hasAVX())
7831 if (VT.isInteger() && !Subtarget->hasAVX2())
7834 // Check that the mask is a broadcast.
7835 int BroadcastIdx = -1;
7837 if (M >= 0 && BroadcastIdx == -1)
7839 else if (M >= 0 && M != BroadcastIdx)
7842 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7843 "a sorted mask where the broadcast "
7846 // Check if this is a broadcast of a scalar. We special case lowering for
7847 // scalars so that we can more effectively fold with loads.
7848 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7849 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7850 V = V.getOperand(BroadcastIdx);
7852 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7854 if (!Subtarget->hasAVX2() && !ISD::isNON_EXTLoad(V.getNode()))
7856 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7857 // We can't broadcast from a vector register w/o AVX2, and we can only
7858 // broadcast from the zero-element of a vector register.
7862 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7865 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7867 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7868 /// support for floating point shuffles but not integer shuffles. These
7869 /// instructions will incur a domain crossing penalty on some chips though so
7870 /// it is better to avoid lowering through this for integer vectors where
7872 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7873 const X86Subtarget *Subtarget,
7874 SelectionDAG &DAG) {
7876 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7877 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7878 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7879 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7880 ArrayRef<int> Mask = SVOp->getMask();
7881 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7883 if (isSingleInputShuffleMask(Mask)) {
7884 // Straight shuffle of a single input vector. Simulate this by using the
7885 // single input as both of the "inputs" to this instruction..
7886 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7888 if (Subtarget->hasAVX()) {
7889 // If we have AVX, we can use VPERMILPS which will allow folding a load
7890 // into the shuffle.
7891 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7892 DAG.getConstant(SHUFPDMask, MVT::i8));
7895 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7896 DAG.getConstant(SHUFPDMask, MVT::i8));
7898 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7899 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7901 // Use dedicated unpack instructions for masks that match their pattern.
7902 if (isShuffleEquivalent(Mask, 0, 2))
7903 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7904 if (isShuffleEquivalent(Mask, 1, 3))
7905 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7907 // If we have a single input, insert that into V1 if we can do so cheaply.
7908 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7909 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7910 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7913 if (Subtarget->hasSSE41())
7914 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7918 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7919 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7920 DAG.getConstant(SHUFPDMask, MVT::i8));
7923 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7925 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7926 /// the integer unit to minimize domain crossing penalties. However, for blends
7927 /// it falls back to the floating point shuffle operation with appropriate bit
7929 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7930 const X86Subtarget *Subtarget,
7931 SelectionDAG &DAG) {
7933 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7934 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7935 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7937 ArrayRef<int> Mask = SVOp->getMask();
7938 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7940 if (isSingleInputShuffleMask(Mask)) {
7941 // Check for being able to broadcast a single element.
7942 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
7943 Mask, Subtarget, DAG))
7946 // Straight shuffle of a single input vector. For everything from SSE2
7947 // onward this has a single fast instruction with no scary immediates.
7948 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7949 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7950 int WidenedMask[4] = {
7951 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7952 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7954 ISD::BITCAST, DL, MVT::v2i64,
7955 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7956 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7959 // Use dedicated unpack instructions for masks that match their pattern.
7960 if (isShuffleEquivalent(Mask, 0, 2))
7961 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7962 if (isShuffleEquivalent(Mask, 1, 3))
7963 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7965 // If we have a single input from V2 insert that into V1 if we can do so
7967 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7968 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7969 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7972 if (Subtarget->hasSSE41())
7973 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7977 // Try to use rotation instructions if available.
7978 if (Subtarget->hasSSSE3())
7979 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7980 DL, MVT::v2i64, V1, V2, Mask, DAG))
7983 // We implement this with SHUFPD which is pretty lame because it will likely
7984 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7985 // However, all the alternatives are still more cycles and newer chips don't
7986 // have this problem. It would be really nice if x86 had better shuffles here.
7987 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7988 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7989 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7990 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7993 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7995 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7996 /// It makes no assumptions about whether this is the *best* lowering, it simply
7998 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7999 ArrayRef<int> Mask, SDValue V1,
8000 SDValue V2, SelectionDAG &DAG) {
8001 SDValue LowV = V1, HighV = V2;
8002 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8005 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8007 if (NumV2Elements == 1) {
8009 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8012 // Compute the index adjacent to V2Index and in the same half by toggling
8014 int V2AdjIndex = V2Index ^ 1;
8016 if (Mask[V2AdjIndex] == -1) {
8017 // Handles all the cases where we have a single V2 element and an undef.
8018 // This will only ever happen in the high lanes because we commute the
8019 // vector otherwise.
8021 std::swap(LowV, HighV);
8022 NewMask[V2Index] -= 4;
8024 // Handle the case where the V2 element ends up adjacent to a V1 element.
8025 // To make this work, blend them together as the first step.
8026 int V1Index = V2AdjIndex;
8027 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8028 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8029 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8031 // Now proceed to reconstruct the final blend as we have the necessary
8032 // high or low half formed.
8039 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8040 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8042 } else if (NumV2Elements == 2) {
8043 if (Mask[0] < 4 && Mask[1] < 4) {
8044 // Handle the easy case where we have V1 in the low lanes and V2 in the
8048 } else if (Mask[2] < 4 && Mask[3] < 4) {
8049 // We also handle the reversed case because this utility may get called
8050 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8051 // arrange things in the right direction.
8057 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8058 // trying to place elements directly, just blend them and set up the final
8059 // shuffle to place them.
8061 // The first two blend mask elements are for V1, the second two are for
8063 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8064 Mask[2] < 4 ? Mask[2] : Mask[3],
8065 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8066 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8067 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8068 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8070 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8073 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8074 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8075 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8076 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8079 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8080 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8083 /// \brief Lower 4-lane 32-bit floating point shuffles.
8085 /// Uses instructions exclusively from the floating point unit to minimize
8086 /// domain crossing penalties, as these are sufficient to implement all v4f32
8088 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8089 const X86Subtarget *Subtarget,
8090 SelectionDAG &DAG) {
8092 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8093 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8094 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8096 ArrayRef<int> Mask = SVOp->getMask();
8097 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8100 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8102 if (NumV2Elements == 0) {
8103 // Check for being able to broadcast a single element.
8104 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8105 Mask, Subtarget, DAG))
8108 if (Subtarget->hasAVX()) {
8109 // If we have AVX, we can use VPERMILPS which will allow folding a load
8110 // into the shuffle.
8111 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8112 getV4X86ShuffleImm8ForMask(Mask, DAG));
8115 // Otherwise, use a straight shuffle of a single input vector. We pass the
8116 // input vector to both operands to simulate this with a SHUFPS.
8117 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8118 getV4X86ShuffleImm8ForMask(Mask, DAG));
8121 // Use dedicated unpack instructions for masks that match their pattern.
8122 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8123 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8124 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8125 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8127 // There are special ways we can lower some single-element blends. However, we
8128 // have custom ways we can lower more complex single-element blends below that
8129 // we defer to if both this and BLENDPS fail to match, so restrict this to
8130 // when the V2 input is targeting element 0 of the mask -- that is the fast
8132 if (NumV2Elements == 1 && Mask[0] >= 4)
8133 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8134 Mask, Subtarget, DAG))
8137 if (Subtarget->hasSSE41())
8138 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8142 // Check for whether we can use INSERTPS to perform the blend. We only use
8143 // INSERTPS when the V1 elements are already in the correct locations
8144 // because otherwise we can just always use two SHUFPS instructions which
8145 // are much smaller to encode than a SHUFPS and an INSERTPS.
8146 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8148 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8151 // When using INSERTPS we can zero any lane of the destination. Collect
8152 // the zero inputs into a mask and drop them from the lanes of V1 which
8153 // actually need to be present as inputs to the INSERTPS.
8154 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8156 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8157 bool InsertNeedsShuffle = false;
8159 for (int i = 0; i < 4; ++i)
8163 } else if (Mask[i] != i) {
8164 InsertNeedsShuffle = true;
8169 // We don't want to use INSERTPS or other insertion techniques if it will
8170 // require shuffling anyways.
8171 if (!InsertNeedsShuffle) {
8172 // If all of V1 is zeroable, replace it with undef.
8173 if ((ZMask | 1 << V2Index) == 0xF)
8174 V1 = DAG.getUNDEF(MVT::v4f32);
8176 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8177 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8179 // Insert the V2 element into the desired position.
8180 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8181 DAG.getConstant(InsertPSMask, MVT::i8));
8185 // Otherwise fall back to a SHUFPS lowering strategy.
8186 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8189 /// \brief Lower 4-lane i32 vector shuffles.
8191 /// We try to handle these with integer-domain shuffles where we can, but for
8192 /// blends we use the floating point domain blend instructions.
8193 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8194 const X86Subtarget *Subtarget,
8195 SelectionDAG &DAG) {
8197 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8198 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8199 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8201 ArrayRef<int> Mask = SVOp->getMask();
8202 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8204 // Whenever we can lower this as a zext, that instruction is strictly faster
8205 // than any alternative. It also allows us to fold memory operands into the
8206 // shuffle in many cases.
8207 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8208 Mask, Subtarget, DAG))
8212 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8214 if (NumV2Elements == 0) {
8215 // Check for being able to broadcast a single element.
8216 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8217 Mask, Subtarget, DAG))
8220 // Straight shuffle of a single input vector. For everything from SSE2
8221 // onward this has a single fast instruction with no scary immediates.
8222 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8223 // but we aren't actually going to use the UNPCK instruction because doing
8224 // so prevents folding a load into this instruction or making a copy.
8225 const int UnpackLoMask[] = {0, 0, 1, 1};
8226 const int UnpackHiMask[] = {2, 2, 3, 3};
8227 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8228 Mask = UnpackLoMask;
8229 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8230 Mask = UnpackHiMask;
8232 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8233 getV4X86ShuffleImm8ForMask(Mask, DAG));
8236 // Use dedicated unpack instructions for masks that match their pattern.
8237 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8239 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8242 // There are special ways we can lower some single-element blends.
8243 if (NumV2Elements == 1)
8244 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8245 Mask, Subtarget, DAG))
8248 if (Subtarget->hasSSE41())
8249 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8253 // Try to use rotation instructions if available.
8254 if (Subtarget->hasSSSE3())
8255 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8256 DL, MVT::v4i32, V1, V2, Mask, DAG))
8259 // We implement this with SHUFPS because it can blend from two vectors.
8260 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8261 // up the inputs, bypassing domain shift penalties that we would encur if we
8262 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8264 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8265 DAG.getVectorShuffle(
8267 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8268 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8271 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8272 /// shuffle lowering, and the most complex part.
8274 /// The lowering strategy is to try to form pairs of input lanes which are
8275 /// targeted at the same half of the final vector, and then use a dword shuffle
8276 /// to place them onto the right half, and finally unpack the paired lanes into
8277 /// their final position.
8279 /// The exact breakdown of how to form these dword pairs and align them on the
8280 /// correct sides is really tricky. See the comments within the function for
8281 /// more of the details.
8282 static SDValue lowerV8I16SingleInputVectorShuffle(
8283 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8284 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8285 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8286 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8287 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8289 SmallVector<int, 4> LoInputs;
8290 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8291 [](int M) { return M >= 0; });
8292 std::sort(LoInputs.begin(), LoInputs.end());
8293 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8294 SmallVector<int, 4> HiInputs;
8295 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8296 [](int M) { return M >= 0; });
8297 std::sort(HiInputs.begin(), HiInputs.end());
8298 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8300 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8301 int NumHToL = LoInputs.size() - NumLToL;
8303 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8304 int NumHToH = HiInputs.size() - NumLToH;
8305 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8306 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8307 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8308 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8310 // Check for being able to broadcast a single element.
8311 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8312 Mask, Subtarget, DAG))
8315 // Use dedicated unpack instructions for masks that match their pattern.
8316 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8317 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8318 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8319 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8321 // Try to use rotation instructions if available.
8322 if (Subtarget->hasSSSE3())
8323 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8324 DL, MVT::v8i16, V, V, Mask, DAG))
8327 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8328 // such inputs we can swap two of the dwords across the half mark and end up
8329 // with <=2 inputs to each half in each half. Once there, we can fall through
8330 // to the generic code below. For example:
8332 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8333 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8335 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8336 // and an existing 2-into-2 on the other half. In this case we may have to
8337 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8338 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8339 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8340 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8341 // half than the one we target for fixing) will be fixed when we re-enter this
8342 // path. We will also combine away any sequence of PSHUFD instructions that
8343 // result into a single instruction. Here is an example of the tricky case:
8345 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8346 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8348 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8350 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8351 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8353 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8354 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8356 // The result is fine to be handled by the generic logic.
8357 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8358 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8359 int AOffset, int BOffset) {
8360 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8361 "Must call this with A having 3 or 1 inputs from the A half.");
8362 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8363 "Must call this with B having 1 or 3 inputs from the B half.");
8364 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8365 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8367 // Compute the index of dword with only one word among the three inputs in
8368 // a half by taking the sum of the half with three inputs and subtracting
8369 // the sum of the actual three inputs. The difference is the remaining
8372 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8373 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8374 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8375 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8376 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8377 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8378 int TripleNonInputIdx =
8379 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8380 TripleDWord = TripleNonInputIdx / 2;
8382 // We use xor with one to compute the adjacent DWord to whichever one the
8384 OneInputDWord = (OneInput / 2) ^ 1;
8386 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8387 // and BToA inputs. If there is also such a problem with the BToB and AToB
8388 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8389 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8390 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8391 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8392 // Compute how many inputs will be flipped by swapping these DWords. We
8394 // to balance this to ensure we don't form a 3-1 shuffle in the other
8396 int NumFlippedAToBInputs =
8397 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8398 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8399 int NumFlippedBToBInputs =
8400 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8401 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8402 if ((NumFlippedAToBInputs == 1 &&
8403 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8404 (NumFlippedBToBInputs == 1 &&
8405 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8406 // We choose whether to fix the A half or B half based on whether that
8407 // half has zero flipped inputs. At zero, we may not be able to fix it
8408 // with that half. We also bias towards fixing the B half because that
8409 // will more commonly be the high half, and we have to bias one way.
8410 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8411 ArrayRef<int> Inputs) {
8412 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8413 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8414 PinnedIdx ^ 1) != Inputs.end();
8415 // Determine whether the free index is in the flipped dword or the
8416 // unflipped dword based on where the pinned index is. We use this bit
8417 // in an xor to conditionally select the adjacent dword.
8418 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8419 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8420 FixFreeIdx) != Inputs.end();
8421 if (IsFixIdxInput == IsFixFreeIdxInput)
8423 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8424 FixFreeIdx) != Inputs.end();
8425 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8426 "We need to be changing the number of flipped inputs!");
8427 int PSHUFHalfMask[] = {0, 1, 2, 3};
8428 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8429 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8431 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8434 if (M != -1 && M == FixIdx)
8436 else if (M != -1 && M == FixFreeIdx)
8439 if (NumFlippedBToBInputs != 0) {
8441 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8442 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8444 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8446 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8447 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8452 int PSHUFDMask[] = {0, 1, 2, 3};
8453 PSHUFDMask[ADWord] = BDWord;
8454 PSHUFDMask[BDWord] = ADWord;
8455 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8456 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8457 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8458 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8460 // Adjust the mask to match the new locations of A and B.
8462 if (M != -1 && M/2 == ADWord)
8463 M = 2 * BDWord + M % 2;
8464 else if (M != -1 && M/2 == BDWord)
8465 M = 2 * ADWord + M % 2;
8467 // Recurse back into this routine to re-compute state now that this isn't
8468 // a 3 and 1 problem.
8469 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8472 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8473 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8474 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8475 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8477 // At this point there are at most two inputs to the low and high halves from
8478 // each half. That means the inputs can always be grouped into dwords and
8479 // those dwords can then be moved to the correct half with a dword shuffle.
8480 // We use at most one low and one high word shuffle to collect these paired
8481 // inputs into dwords, and finally a dword shuffle to place them.
8482 int PSHUFLMask[4] = {-1, -1, -1, -1};
8483 int PSHUFHMask[4] = {-1, -1, -1, -1};
8484 int PSHUFDMask[4] = {-1, -1, -1, -1};
8486 // First fix the masks for all the inputs that are staying in their
8487 // original halves. This will then dictate the targets of the cross-half
8489 auto fixInPlaceInputs =
8490 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8491 MutableArrayRef<int> SourceHalfMask,
8492 MutableArrayRef<int> HalfMask, int HalfOffset) {
8493 if (InPlaceInputs.empty())
8495 if (InPlaceInputs.size() == 1) {
8496 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8497 InPlaceInputs[0] - HalfOffset;
8498 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8501 if (IncomingInputs.empty()) {
8502 // Just fix all of the in place inputs.
8503 for (int Input : InPlaceInputs) {
8504 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8505 PSHUFDMask[Input / 2] = Input / 2;
8510 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8511 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8512 InPlaceInputs[0] - HalfOffset;
8513 // Put the second input next to the first so that they are packed into
8514 // a dword. We find the adjacent index by toggling the low bit.
8515 int AdjIndex = InPlaceInputs[0] ^ 1;
8516 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8517 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8518 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8520 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8521 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8523 // Now gather the cross-half inputs and place them into a free dword of
8524 // their target half.
8525 // FIXME: This operation could almost certainly be simplified dramatically to
8526 // look more like the 3-1 fixing operation.
8527 auto moveInputsToRightHalf = [&PSHUFDMask](
8528 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8529 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8530 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8532 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8533 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8535 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8537 int LowWord = Word & ~1;
8538 int HighWord = Word | 1;
8539 return isWordClobbered(SourceHalfMask, LowWord) ||
8540 isWordClobbered(SourceHalfMask, HighWord);
8543 if (IncomingInputs.empty())
8546 if (ExistingInputs.empty()) {
8547 // Map any dwords with inputs from them into the right half.
8548 for (int Input : IncomingInputs) {
8549 // If the source half mask maps over the inputs, turn those into
8550 // swaps and use the swapped lane.
8551 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8552 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8553 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8554 Input - SourceOffset;
8555 // We have to swap the uses in our half mask in one sweep.
8556 for (int &M : HalfMask)
8557 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8559 else if (M == Input)
8560 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8562 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8563 Input - SourceOffset &&
8564 "Previous placement doesn't match!");
8566 // Note that this correctly re-maps both when we do a swap and when
8567 // we observe the other side of the swap above. We rely on that to
8568 // avoid swapping the members of the input list directly.
8569 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8572 // Map the input's dword into the correct half.
8573 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8574 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8576 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8578 "Previous placement doesn't match!");
8581 // And just directly shift any other-half mask elements to be same-half
8582 // as we will have mirrored the dword containing the element into the
8583 // same position within that half.
8584 for (int &M : HalfMask)
8585 if (M >= SourceOffset && M < SourceOffset + 4) {
8586 M = M - SourceOffset + DestOffset;
8587 assert(M >= 0 && "This should never wrap below zero!");
8592 // Ensure we have the input in a viable dword of its current half. This
8593 // is particularly tricky because the original position may be clobbered
8594 // by inputs being moved and *staying* in that half.
8595 if (IncomingInputs.size() == 1) {
8596 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8597 int InputFixed = std::find(std::begin(SourceHalfMask),
8598 std::end(SourceHalfMask), -1) -
8599 std::begin(SourceHalfMask) + SourceOffset;
8600 SourceHalfMask[InputFixed - SourceOffset] =
8601 IncomingInputs[0] - SourceOffset;
8602 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8604 IncomingInputs[0] = InputFixed;
8606 } else if (IncomingInputs.size() == 2) {
8607 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8608 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8609 // We have two non-adjacent or clobbered inputs we need to extract from
8610 // the source half. To do this, we need to map them into some adjacent
8611 // dword slot in the source mask.
8612 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8613 IncomingInputs[1] - SourceOffset};
8615 // If there is a free slot in the source half mask adjacent to one of
8616 // the inputs, place the other input in it. We use (Index XOR 1) to
8617 // compute an adjacent index.
8618 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8619 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8620 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8621 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8622 InputsFixed[1] = InputsFixed[0] ^ 1;
8623 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8624 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8625 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8626 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8627 InputsFixed[0] = InputsFixed[1] ^ 1;
8628 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8629 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8630 // The two inputs are in the same DWord but it is clobbered and the
8631 // adjacent DWord isn't used at all. Move both inputs to the free
8633 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8634 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8635 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8636 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8638 // The only way we hit this point is if there is no clobbering
8639 // (because there are no off-half inputs to this half) and there is no
8640 // free slot adjacent to one of the inputs. In this case, we have to
8641 // swap an input with a non-input.
8642 for (int i = 0; i < 4; ++i)
8643 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8644 "We can't handle any clobbers here!");
8645 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8646 "Cannot have adjacent inputs here!");
8648 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8649 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8651 // We also have to update the final source mask in this case because
8652 // it may need to undo the above swap.
8653 for (int &M : FinalSourceHalfMask)
8654 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8655 M = InputsFixed[1] + SourceOffset;
8656 else if (M == InputsFixed[1] + SourceOffset)
8657 M = (InputsFixed[0] ^ 1) + SourceOffset;
8659 InputsFixed[1] = InputsFixed[0] ^ 1;
8662 // Point everything at the fixed inputs.
8663 for (int &M : HalfMask)
8664 if (M == IncomingInputs[0])
8665 M = InputsFixed[0] + SourceOffset;
8666 else if (M == IncomingInputs[1])
8667 M = InputsFixed[1] + SourceOffset;
8669 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8670 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8673 llvm_unreachable("Unhandled input size!");
8676 // Now hoist the DWord down to the right half.
8677 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8678 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8679 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8680 for (int &M : HalfMask)
8681 for (int Input : IncomingInputs)
8683 M = FreeDWord * 2 + Input % 2;
8685 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8686 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8687 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8688 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8690 // Now enact all the shuffles we've computed to move the inputs into their
8692 if (!isNoopShuffleMask(PSHUFLMask))
8693 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8694 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8695 if (!isNoopShuffleMask(PSHUFHMask))
8696 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8697 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8698 if (!isNoopShuffleMask(PSHUFDMask))
8699 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8700 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8701 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8702 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8704 // At this point, each half should contain all its inputs, and we can then
8705 // just shuffle them into their final position.
8706 assert(std::count_if(LoMask.begin(), LoMask.end(),
8707 [](int M) { return M >= 4; }) == 0 &&
8708 "Failed to lift all the high half inputs to the low mask!");
8709 assert(std::count_if(HiMask.begin(), HiMask.end(),
8710 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8711 "Failed to lift all the low half inputs to the high mask!");
8713 // Do a half shuffle for the low mask.
8714 if (!isNoopShuffleMask(LoMask))
8715 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8716 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8718 // Do a half shuffle with the high mask after shifting its values down.
8719 for (int &M : HiMask)
8722 if (!isNoopShuffleMask(HiMask))
8723 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8724 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8729 /// \brief Detect whether the mask pattern should be lowered through
8732 /// This essentially tests whether viewing the mask as an interleaving of two
8733 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8734 /// lowering it through interleaving is a significantly better strategy.
8735 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8736 int NumEvenInputs[2] = {0, 0};
8737 int NumOddInputs[2] = {0, 0};
8738 int NumLoInputs[2] = {0, 0};
8739 int NumHiInputs[2] = {0, 0};
8740 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8744 int InputIdx = Mask[i] >= Size;
8747 ++NumLoInputs[InputIdx];
8749 ++NumHiInputs[InputIdx];
8752 ++NumEvenInputs[InputIdx];
8754 ++NumOddInputs[InputIdx];
8757 // The minimum number of cross-input results for both the interleaved and
8758 // split cases. If interleaving results in fewer cross-input results, return
8760 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8761 NumEvenInputs[0] + NumOddInputs[1]);
8762 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8763 NumLoInputs[0] + NumHiInputs[1]);
8764 return InterleavedCrosses < SplitCrosses;
8767 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8769 /// This strategy only works when the inputs from each vector fit into a single
8770 /// half of that vector, and generally there are not so many inputs as to leave
8771 /// the in-place shuffles required highly constrained (and thus expensive). It
8772 /// shifts all the inputs into a single side of both input vectors and then
8773 /// uses an unpack to interleave these inputs in a single vector. At that
8774 /// point, we will fall back on the generic single input shuffle lowering.
8775 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8777 MutableArrayRef<int> Mask,
8778 const X86Subtarget *Subtarget,
8779 SelectionDAG &DAG) {
8780 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8781 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8782 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8783 for (int i = 0; i < 8; ++i)
8784 if (Mask[i] >= 0 && Mask[i] < 4)
8785 LoV1Inputs.push_back(i);
8786 else if (Mask[i] >= 4 && Mask[i] < 8)
8787 HiV1Inputs.push_back(i);
8788 else if (Mask[i] >= 8 && Mask[i] < 12)
8789 LoV2Inputs.push_back(i);
8790 else if (Mask[i] >= 12)
8791 HiV2Inputs.push_back(i);
8793 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8794 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8797 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8798 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8799 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8801 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8802 HiV1Inputs.size() + HiV2Inputs.size();
8804 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8805 ArrayRef<int> HiInputs, bool MoveToLo,
8807 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8808 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8809 if (BadInputs.empty())
8812 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8813 int MoveOffset = MoveToLo ? 0 : 4;
8815 if (GoodInputs.empty()) {
8816 for (int BadInput : BadInputs) {
8817 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8818 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8821 if (GoodInputs.size() == 2) {
8822 // If the low inputs are spread across two dwords, pack them into
8824 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8825 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8826 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8827 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8829 // Otherwise pin the good inputs.
8830 for (int GoodInput : GoodInputs)
8831 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8834 if (BadInputs.size() == 2) {
8835 // If we have two bad inputs then there may be either one or two good
8836 // inputs fixed in place. Find a fixed input, and then find the *other*
8837 // two adjacent indices by using modular arithmetic.
8839 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8840 [](int M) { return M >= 0; }) -
8841 std::begin(MoveMask);
8843 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8844 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8845 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8846 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8847 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8848 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8849 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8851 assert(BadInputs.size() == 1 && "All sizes handled");
8852 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8853 std::end(MoveMask), -1) -
8854 std::begin(MoveMask);
8855 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8856 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8860 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8863 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8865 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8868 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8869 // cross-half traffic in the final shuffle.
8871 // Munge the mask to be a single-input mask after the unpack merges the
8875 M = 2 * (M % 4) + (M / 8);
8877 return DAG.getVectorShuffle(
8878 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8879 DL, MVT::v8i16, V1, V2),
8880 DAG.getUNDEF(MVT::v8i16), Mask);
8883 /// \brief Generic lowering of 8-lane i16 shuffles.
8885 /// This handles both single-input shuffles and combined shuffle/blends with
8886 /// two inputs. The single input shuffles are immediately delegated to
8887 /// a dedicated lowering routine.
8889 /// The blends are lowered in one of three fundamental ways. If there are few
8890 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8891 /// of the input is significantly cheaper when lowered as an interleaving of
8892 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8893 /// halves of the inputs separately (making them have relatively few inputs)
8894 /// and then concatenate them.
8895 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8896 const X86Subtarget *Subtarget,
8897 SelectionDAG &DAG) {
8899 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8900 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8901 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8903 ArrayRef<int> OrigMask = SVOp->getMask();
8904 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8905 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8906 MutableArrayRef<int> Mask(MaskStorage);
8908 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8910 // Whenever we can lower this as a zext, that instruction is strictly faster
8911 // than any alternative.
8912 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8913 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8916 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8917 auto isV2 = [](int M) { return M >= 8; };
8919 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8920 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8922 if (NumV2Inputs == 0)
8923 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8925 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8926 "to be V1-input shuffles.");
8928 // There are special ways we can lower some single-element blends.
8929 if (NumV2Inputs == 1)
8930 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8931 Mask, Subtarget, DAG))
8934 if (Subtarget->hasSSE41())
8935 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8939 // Try to use rotation instructions if available.
8940 if (Subtarget->hasSSSE3())
8941 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8944 if (NumV1Inputs + NumV2Inputs <= 4)
8945 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8947 // Check whether an interleaving lowering is likely to be more efficient.
8948 // This isn't perfect but it is a strong heuristic that tends to work well on
8949 // the kinds of shuffles that show up in practice.
8951 // FIXME: Handle 1x, 2x, and 4x interleaving.
8952 if (shouldLowerAsInterleaving(Mask)) {
8953 // FIXME: Figure out whether we should pack these into the low or high
8956 int EMask[8], OMask[8];
8957 for (int i = 0; i < 4; ++i) {
8958 EMask[i] = Mask[2*i];
8959 OMask[i] = Mask[2*i + 1];
8964 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8965 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8967 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8970 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8971 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8973 for (int i = 0; i < 4; ++i) {
8974 LoBlendMask[i] = Mask[i];
8975 HiBlendMask[i] = Mask[i + 4];
8978 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8979 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8980 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8981 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8983 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8984 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8987 /// \brief Check whether a compaction lowering can be done by dropping even
8988 /// elements and compute how many times even elements must be dropped.
8990 /// This handles shuffles which take every Nth element where N is a power of
8991 /// two. Example shuffle masks:
8993 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8994 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8995 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8996 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8997 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8998 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9000 /// Any of these lanes can of course be undef.
9002 /// This routine only supports N <= 3.
9003 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9006 /// \returns N above, or the number of times even elements must be dropped if
9007 /// there is such a number. Otherwise returns zero.
9008 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9009 // Figure out whether we're looping over two inputs or just one.
9010 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9012 // The modulus for the shuffle vector entries is based on whether this is
9013 // a single input or not.
9014 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9015 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9016 "We should only be called with masks with a power-of-2 size!");
9018 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9020 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9021 // and 2^3 simultaneously. This is because we may have ambiguity with
9022 // partially undef inputs.
9023 bool ViableForN[3] = {true, true, true};
9025 for (int i = 0, e = Mask.size(); i < e; ++i) {
9026 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9031 bool IsAnyViable = false;
9032 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9033 if (ViableForN[j]) {
9036 // The shuffle mask must be equal to (i * 2^N) % M.
9037 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9040 ViableForN[j] = false;
9042 // Early exit if we exhaust the possible powers of two.
9047 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9051 // Return 0 as there is no viable power of two.
9055 /// \brief Generic lowering of v16i8 shuffles.
9057 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9058 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9059 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9060 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9062 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9063 const X86Subtarget *Subtarget,
9064 SelectionDAG &DAG) {
9066 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9067 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9068 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9070 ArrayRef<int> OrigMask = SVOp->getMask();
9071 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9073 // Try to use rotation instructions if available.
9074 if (Subtarget->hasSSSE3())
9075 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9079 // Try to use a zext lowering.
9080 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9081 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9084 int MaskStorage[16] = {
9085 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9086 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9087 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9088 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9089 MutableArrayRef<int> Mask(MaskStorage);
9090 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9091 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9094 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9096 // For single-input shuffles, there are some nicer lowering tricks we can use.
9097 if (NumV2Elements == 0) {
9098 // Check for being able to broadcast a single element.
9099 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9100 Mask, Subtarget, DAG))
9103 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9104 // Notably, this handles splat and partial-splat shuffles more efficiently.
9105 // However, it only makes sense if the pre-duplication shuffle simplifies
9106 // things significantly. Currently, this means we need to be able to
9107 // express the pre-duplication shuffle as an i16 shuffle.
9109 // FIXME: We should check for other patterns which can be widened into an
9110 // i16 shuffle as well.
9111 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9112 for (int i = 0; i < 16; i += 2)
9113 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9118 auto tryToWidenViaDuplication = [&]() -> SDValue {
9119 if (!canWidenViaDuplication(Mask))
9121 SmallVector<int, 4> LoInputs;
9122 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9123 [](int M) { return M >= 0 && M < 8; });
9124 std::sort(LoInputs.begin(), LoInputs.end());
9125 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9127 SmallVector<int, 4> HiInputs;
9128 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9129 [](int M) { return M >= 8; });
9130 std::sort(HiInputs.begin(), HiInputs.end());
9131 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9134 bool TargetLo = LoInputs.size() >= HiInputs.size();
9135 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9136 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9138 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9139 SmallDenseMap<int, int, 8> LaneMap;
9140 for (int I : InPlaceInputs) {
9141 PreDupI16Shuffle[I/2] = I/2;
9144 int j = TargetLo ? 0 : 4, je = j + 4;
9145 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9146 // Check if j is already a shuffle of this input. This happens when
9147 // there are two adjacent bytes after we move the low one.
9148 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9149 // If we haven't yet mapped the input, search for a slot into which
9151 while (j < je && PreDupI16Shuffle[j] != -1)
9155 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9158 // Map this input with the i16 shuffle.
9159 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9162 // Update the lane map based on the mapping we ended up with.
9163 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9166 ISD::BITCAST, DL, MVT::v16i8,
9167 DAG.getVectorShuffle(MVT::v8i16, DL,
9168 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9169 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9171 // Unpack the bytes to form the i16s that will be shuffled into place.
9172 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9173 MVT::v16i8, V1, V1);
9175 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9176 for (int i = 0; i < 16; ++i)
9177 if (Mask[i] != -1) {
9178 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9179 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9180 if (PostDupI16Shuffle[i / 2] == -1)
9181 PostDupI16Shuffle[i / 2] = MappedMask;
9183 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9184 "Conflicting entrties in the original shuffle!");
9187 ISD::BITCAST, DL, MVT::v16i8,
9188 DAG.getVectorShuffle(MVT::v8i16, DL,
9189 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9190 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9192 if (SDValue V = tryToWidenViaDuplication())
9196 // Check whether an interleaving lowering is likely to be more efficient.
9197 // This isn't perfect but it is a strong heuristic that tends to work well on
9198 // the kinds of shuffles that show up in practice.
9200 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9201 if (shouldLowerAsInterleaving(Mask)) {
9202 // FIXME: Figure out whether we should pack these into the low or high
9205 int EMask[16], OMask[16];
9206 for (int i = 0; i < 8; ++i) {
9207 EMask[i] = Mask[2*i];
9208 OMask[i] = Mask[2*i + 1];
9213 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9214 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9216 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9219 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9220 // with PSHUFB. It is important to do this before we attempt to generate any
9221 // blends but after all of the single-input lowerings. If the single input
9222 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9223 // want to preserve that and we can DAG combine any longer sequences into
9224 // a PSHUFB in the end. But once we start blending from multiple inputs,
9225 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9226 // and there are *very* few patterns that would actually be faster than the
9227 // PSHUFB approach because of its ability to zero lanes.
9229 // FIXME: The only exceptions to the above are blends which are exact
9230 // interleavings with direct instructions supporting them. We currently don't
9231 // handle those well here.
9232 if (Subtarget->hasSSSE3()) {
9235 for (int i = 0; i < 16; ++i)
9236 if (Mask[i] == -1) {
9237 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9239 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9241 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9243 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9244 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9245 if (isSingleInputShuffleMask(Mask))
9246 return V1; // Single inputs are easy.
9248 // Otherwise, blend the two.
9249 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9250 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9251 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9254 // There are special ways we can lower some single-element blends.
9255 if (NumV2Elements == 1)
9256 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9257 Mask, Subtarget, DAG))
9260 // Check whether a compaction lowering can be done. This handles shuffles
9261 // which take every Nth element for some even N. See the helper function for
9264 // We special case these as they can be particularly efficiently handled with
9265 // the PACKUSB instruction on x86 and they show up in common patterns of
9266 // rearranging bytes to truncate wide elements.
9267 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9268 // NumEvenDrops is the power of two stride of the elements. Another way of
9269 // thinking about it is that we need to drop the even elements this many
9270 // times to get the original input.
9271 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9273 // First we need to zero all the dropped bytes.
9274 assert(NumEvenDrops <= 3 &&
9275 "No support for dropping even elements more than 3 times.");
9276 // We use the mask type to pick which bytes are preserved based on how many
9277 // elements are dropped.
9278 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9279 SDValue ByteClearMask =
9280 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9281 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9282 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9284 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9286 // Now pack things back together.
9287 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9288 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9289 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9290 for (int i = 1; i < NumEvenDrops; ++i) {
9291 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9292 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9298 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9299 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9300 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9301 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9303 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9304 MutableArrayRef<int> V1HalfBlendMask,
9305 MutableArrayRef<int> V2HalfBlendMask) {
9306 for (int i = 0; i < 8; ++i)
9307 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9308 V1HalfBlendMask[i] = HalfMask[i];
9310 } else if (HalfMask[i] >= 16) {
9311 V2HalfBlendMask[i] = HalfMask[i] - 16;
9312 HalfMask[i] = i + 8;
9315 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9316 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9318 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9320 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9321 MutableArrayRef<int> HiBlendMask) {
9323 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9324 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9326 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9327 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9328 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9329 [](int M) { return M >= 0 && M % 2 == 1; })) {
9330 // Use a mask to drop the high bytes.
9331 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9332 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9333 DAG.getConstant(0x00FF, MVT::v8i16));
9335 // This will be a single vector shuffle instead of a blend so nuke V2.
9336 V2 = DAG.getUNDEF(MVT::v8i16);
9338 // Squash the masks to point directly into V1.
9339 for (int &M : LoBlendMask)
9342 for (int &M : HiBlendMask)
9346 // Otherwise just unpack the low half of V into V1 and the high half into
9347 // V2 so that we can blend them as i16s.
9348 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9349 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9350 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9351 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9354 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9355 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9356 return std::make_pair(BlendedLo, BlendedHi);
9358 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9359 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9360 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9362 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9363 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9365 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9368 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9370 /// This routine breaks down the specific type of 128-bit shuffle and
9371 /// dispatches to the lowering routines accordingly.
9372 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9373 MVT VT, const X86Subtarget *Subtarget,
9374 SelectionDAG &DAG) {
9375 switch (VT.SimpleTy) {
9377 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9379 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9381 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9383 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9385 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9387 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9390 llvm_unreachable("Unimplemented!");
9394 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9396 /// This routine just extracts two subvectors, shuffles them independently, and
9397 /// then concatenates them back together. This should work effectively with all
9398 /// AVX vector shuffle types.
9399 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9400 SDValue V2, ArrayRef<int> Mask,
9401 SelectionDAG &DAG) {
9402 assert(VT.getSizeInBits() >= 256 &&
9403 "Only for 256-bit or wider vector shuffles!");
9404 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9405 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9407 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9408 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9410 int NumElements = VT.getVectorNumElements();
9411 int SplitNumElements = NumElements / 2;
9412 MVT ScalarVT = VT.getScalarType();
9413 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9415 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9416 DAG.getIntPtrConstant(0));
9417 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9418 DAG.getIntPtrConstant(SplitNumElements));
9419 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9420 DAG.getIntPtrConstant(0));
9421 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9422 DAG.getIntPtrConstant(SplitNumElements));
9424 // Now create two 4-way blends of these half-width vectors.
9425 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9426 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9427 for (int i = 0; i < SplitNumElements; ++i) {
9428 int M = HalfMask[i];
9429 if (M >= NumElements) {
9430 V2BlendMask.push_back(M - NumElements);
9431 V1BlendMask.push_back(-1);
9432 BlendMask.push_back(SplitNumElements + i);
9433 } else if (M >= 0) {
9434 V2BlendMask.push_back(-1);
9435 V1BlendMask.push_back(M);
9436 BlendMask.push_back(i);
9438 V2BlendMask.push_back(-1);
9439 V1BlendMask.push_back(-1);
9440 BlendMask.push_back(-1);
9444 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9446 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9447 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9449 SDValue Lo = HalfBlend(LoMask);
9450 SDValue Hi = HalfBlend(HiMask);
9451 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9454 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9455 /// a permutation and blend of those lanes.
9457 /// This essentially blends the out-of-lane inputs to each lane into the lane
9458 /// from a permuted copy of the vector. This lowering strategy results in four
9459 /// instructions in the worst case for a single-input cross lane shuffle which
9460 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9461 /// of. Special cases for each particular shuffle pattern should be handled
9462 /// prior to trying this lowering.
9463 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9464 SDValue V1, SDValue V2,
9466 SelectionDAG &DAG) {
9467 // FIXME: This should probably be generalized for 512-bit vectors as well.
9468 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9469 int LaneSize = Mask.size() / 2;
9471 // If there are only inputs from one 128-bit lane, splitting will in fact be
9472 // less expensive. The flags track wether the given lane contains an element
9473 // that crosses to another lane.
9474 bool LaneCrossing[2] = {false, false};
9475 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9476 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9477 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9478 if (!LaneCrossing[0] || !LaneCrossing[1])
9479 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9481 if (isSingleInputShuffleMask(Mask)) {
9482 SmallVector<int, 32> FlippedBlendMask;
9483 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9484 FlippedBlendMask.push_back(
9485 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9487 : Mask[i] % LaneSize +
9488 (i / LaneSize) * LaneSize + Size));
9490 // Flip the vector, and blend the results which should now be in-lane. The
9491 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9492 // 5 for the high source. The value 3 selects the high half of source 2 and
9493 // the value 2 selects the low half of source 2. We only use source 2 to
9494 // allow folding it into a memory operand.
9495 unsigned PERMMask = 3 | 2 << 4;
9496 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9497 V1, DAG.getConstant(PERMMask, MVT::i8));
9498 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9501 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9502 // will be handled by the above logic and a blend of the results, much like
9503 // other patterns in AVX.
9504 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9507 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9509 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9510 /// isn't available.
9511 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9512 const X86Subtarget *Subtarget,
9513 SelectionDAG &DAG) {
9515 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9516 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9518 ArrayRef<int> Mask = SVOp->getMask();
9519 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9521 if (isSingleInputShuffleMask(Mask)) {
9522 // Check for being able to broadcast a single element.
9523 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9524 Mask, Subtarget, DAG))
9527 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9528 // Non-half-crossing single input shuffles can be lowerid with an
9529 // interleaved permutation.
9530 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9531 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9532 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9533 DAG.getConstant(VPERMILPMask, MVT::i8));
9536 // With AVX2 we have direct support for this permutation.
9537 if (Subtarget->hasAVX2())
9538 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9539 getV4X86ShuffleImm8ForMask(Mask, DAG));
9541 // Otherwise, fall back.
9542 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9546 // X86 has dedicated unpack instructions that can handle specific blend
9547 // operations: UNPCKH and UNPCKL.
9548 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9549 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9550 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9553 // If we have a single input to the zero element, insert that into V1 if we
9554 // can do so cheaply.
9556 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9557 if (NumV2Elements == 1 && Mask[0] >= 4)
9558 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9559 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9562 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9566 // Check if the blend happens to exactly fit that of SHUFPD.
9567 if ((Mask[0] == -1 || Mask[0] < 2) &&
9568 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9569 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9570 (Mask[3] == -1 || Mask[3] >= 6)) {
9571 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9572 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9573 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9574 DAG.getConstant(SHUFPDMask, MVT::i8));
9576 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9577 (Mask[1] == -1 || Mask[1] < 2) &&
9578 (Mask[2] == -1 || Mask[2] >= 6) &&
9579 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9580 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9581 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9582 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9583 DAG.getConstant(SHUFPDMask, MVT::i8));
9586 // Otherwise fall back on generic blend lowering.
9587 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9591 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9593 /// This routine is only called when we have AVX2 and thus a reasonable
9594 /// instruction set for v4i64 shuffling..
9595 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9596 const X86Subtarget *Subtarget,
9597 SelectionDAG &DAG) {
9599 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9600 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9602 ArrayRef<int> Mask = SVOp->getMask();
9603 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9604 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9606 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9610 // Check for being able to broadcast a single element.
9611 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9612 Mask, Subtarget, DAG))
9615 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9616 // use lower latency instructions that will operate on both 128-bit lanes.
9617 SmallVector<int, 2> RepeatedMask;
9618 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9619 if (isSingleInputShuffleMask(Mask)) {
9620 int PSHUFDMask[] = {-1, -1, -1, -1};
9621 for (int i = 0; i < 2; ++i)
9622 if (RepeatedMask[i] >= 0) {
9623 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9624 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9627 ISD::BITCAST, DL, MVT::v4i64,
9628 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9630 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9633 // Use dedicated unpack instructions for masks that match their pattern.
9634 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9635 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9636 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9637 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9640 // AVX2 provides a direct instruction for permuting a single input across
9642 if (isSingleInputShuffleMask(Mask))
9643 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9644 getV4X86ShuffleImm8ForMask(Mask, DAG));
9646 // Otherwise fall back on generic blend lowering.
9647 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9651 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9653 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9654 /// isn't available.
9655 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9656 const X86Subtarget *Subtarget,
9657 SelectionDAG &DAG) {
9659 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9660 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9661 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9662 ArrayRef<int> Mask = SVOp->getMask();
9663 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9665 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9669 // Check for being able to broadcast a single element.
9670 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9671 Mask, Subtarget, DAG))
9674 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9675 // options to efficiently lower the shuffle.
9676 SmallVector<int, 4> RepeatedMask;
9677 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9678 assert(RepeatedMask.size() == 4 &&
9679 "Repeated masks must be half the mask width!");
9680 if (isSingleInputShuffleMask(Mask))
9681 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9682 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9684 // Use dedicated unpack instructions for masks that match their pattern.
9685 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9686 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9687 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9688 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9690 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9691 // have already handled any direct blends. We also need to squash the
9692 // repeated mask into a simulated v4f32 mask.
9693 for (int i = 0; i < 4; ++i)
9694 if (RepeatedMask[i] >= 8)
9695 RepeatedMask[i] -= 4;
9696 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9699 // If we have a single input shuffle with different shuffle patterns in the
9700 // two 128-bit lanes use the variable mask to VPERMILPS.
9701 if (isSingleInputShuffleMask(Mask)) {
9702 SDValue VPermMask[8];
9703 for (int i = 0; i < 8; ++i)
9704 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9705 : DAG.getConstant(Mask[i], MVT::i32);
9706 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9708 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9709 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9711 if (Subtarget->hasAVX2())
9712 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9713 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9714 DAG.getNode(ISD::BUILD_VECTOR, DL,
9715 MVT::v8i32, VPermMask)),
9718 // Otherwise, fall back.
9719 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9723 // Otherwise fall back on generic blend lowering.
9724 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9728 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9730 /// This routine is only called when we have AVX2 and thus a reasonable
9731 /// instruction set for v8i32 shuffling..
9732 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9733 const X86Subtarget *Subtarget,
9734 SelectionDAG &DAG) {
9736 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9737 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9739 ArrayRef<int> Mask = SVOp->getMask();
9740 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9741 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9743 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9747 // Check for being able to broadcast a single element.
9748 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9749 Mask, Subtarget, DAG))
9752 // If the shuffle mask is repeated in each 128-bit lane we can use more
9753 // efficient instructions that mirror the shuffles across the two 128-bit
9755 SmallVector<int, 4> RepeatedMask;
9756 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9757 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9758 if (isSingleInputShuffleMask(Mask))
9759 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9760 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9762 // Use dedicated unpack instructions for masks that match their pattern.
9763 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9764 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9765 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9766 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9769 // If the shuffle patterns aren't repeated but it is a single input, directly
9770 // generate a cross-lane VPERMD instruction.
9771 if (isSingleInputShuffleMask(Mask)) {
9772 SDValue VPermMask[8];
9773 for (int i = 0; i < 8; ++i)
9774 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9775 : DAG.getConstant(Mask[i], MVT::i32);
9777 X86ISD::VPERMV, DL, MVT::v8i32,
9778 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9781 // Otherwise fall back on generic blend lowering.
9782 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9786 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9788 /// This routine is only called when we have AVX2 and thus a reasonable
9789 /// instruction set for v16i16 shuffling..
9790 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9791 const X86Subtarget *Subtarget,
9792 SelectionDAG &DAG) {
9794 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9795 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9797 ArrayRef<int> Mask = SVOp->getMask();
9798 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9799 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9801 // Check for being able to broadcast a single element.
9802 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9803 Mask, Subtarget, DAG))
9806 // There are no generalized cross-lane shuffle operations available on i16
9808 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9809 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9812 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9816 // Use dedicated unpack instructions for masks that match their pattern.
9817 if (isShuffleEquivalent(Mask,
9818 // First 128-bit lane:
9819 0, 16, 1, 17, 2, 18, 3, 19,
9820 // Second 128-bit lane:
9821 8, 24, 9, 25, 10, 26, 11, 27))
9822 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9823 if (isShuffleEquivalent(Mask,
9824 // First 128-bit lane:
9825 4, 20, 5, 21, 6, 22, 7, 23,
9826 // Second 128-bit lane:
9827 12, 28, 13, 29, 14, 30, 15, 31))
9828 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9830 if (isSingleInputShuffleMask(Mask)) {
9831 SDValue PSHUFBMask[32];
9832 for (int i = 0; i < 16; ++i) {
9833 if (Mask[i] == -1) {
9834 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9838 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9839 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9840 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9841 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9844 ISD::BITCAST, DL, MVT::v16i16,
9846 X86ISD::PSHUFB, DL, MVT::v32i8,
9847 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9848 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9851 // Otherwise fall back on generic blend lowering.
9852 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9856 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9858 /// This routine is only called when we have AVX2 and thus a reasonable
9859 /// instruction set for v32i8 shuffling..
9860 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9861 const X86Subtarget *Subtarget,
9862 SelectionDAG &DAG) {
9864 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9865 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9866 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9867 ArrayRef<int> Mask = SVOp->getMask();
9868 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9869 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9871 // Check for being able to broadcast a single element.
9872 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
9873 Mask, Subtarget, DAG))
9876 // There are no generalized cross-lane shuffle operations available on i8
9878 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9879 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9882 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9886 // Use dedicated unpack instructions for masks that match their pattern.
9887 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9889 if (isShuffleEquivalent(
9891 // First 128-bit lane:
9892 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9893 // Second 128-bit lane:
9894 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9895 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9896 if (isShuffleEquivalent(
9898 // First 128-bit lane:
9899 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9900 // Second 128-bit lane:
9901 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9902 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9904 if (isSingleInputShuffleMask(Mask)) {
9905 SDValue PSHUFBMask[32];
9906 for (int i = 0; i < 32; ++i)
9909 ? DAG.getUNDEF(MVT::i8)
9910 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9913 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9914 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9917 // Otherwise fall back on generic blend lowering.
9918 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9922 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9924 /// This routine either breaks down the specific type of a 256-bit x86 vector
9925 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9926 /// together based on the available instructions.
9927 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9928 MVT VT, const X86Subtarget *Subtarget,
9929 SelectionDAG &DAG) {
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 ArrayRef<int> Mask = SVOp->getMask();
9934 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9935 // check for those subtargets here and avoid much of the subtarget querying in
9936 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9937 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9938 // floating point types there eventually, just immediately cast everything to
9939 // a float and operate entirely in that domain.
9940 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9941 int ElementBits = VT.getScalarSizeInBits();
9942 if (ElementBits < 32)
9943 // No floating point type available, decompose into 128-bit vectors.
9944 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9946 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9947 VT.getVectorNumElements());
9948 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9949 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9950 return DAG.getNode(ISD::BITCAST, DL, VT,
9951 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9954 switch (VT.SimpleTy) {
9956 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9958 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9960 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9962 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9964 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9966 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9969 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9973 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9974 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9975 const X86Subtarget *Subtarget,
9976 SelectionDAG &DAG) {
9978 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9979 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9980 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9981 ArrayRef<int> Mask = SVOp->getMask();
9982 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9984 // FIXME: Implement direct support for this type!
9985 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9988 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9989 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9990 const X86Subtarget *Subtarget,
9991 SelectionDAG &DAG) {
9993 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9994 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9996 ArrayRef<int> Mask = SVOp->getMask();
9997 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9999 // FIXME: Implement direct support for this type!
10000 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10003 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10004 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10005 const X86Subtarget *Subtarget,
10006 SelectionDAG &DAG) {
10008 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10009 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10011 ArrayRef<int> Mask = SVOp->getMask();
10012 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10013 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10015 // FIXME: Implement direct support for this type!
10016 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10019 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10020 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10021 const X86Subtarget *Subtarget,
10022 SelectionDAG &DAG) {
10024 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10025 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10027 ArrayRef<int> Mask = SVOp->getMask();
10028 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10029 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10031 // FIXME: Implement direct support for this type!
10032 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10035 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10036 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10037 const X86Subtarget *Subtarget,
10038 SelectionDAG &DAG) {
10040 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10041 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10042 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10043 ArrayRef<int> Mask = SVOp->getMask();
10044 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10045 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10047 // FIXME: Implement direct support for this type!
10048 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10051 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10052 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10053 const X86Subtarget *Subtarget,
10054 SelectionDAG &DAG) {
10056 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10057 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10059 ArrayRef<int> Mask = SVOp->getMask();
10060 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10061 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10063 // FIXME: Implement direct support for this type!
10064 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10067 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10069 /// This routine either breaks down the specific type of a 512-bit x86 vector
10070 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10071 /// together based on the available instructions.
10072 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10073 MVT VT, const X86Subtarget *Subtarget,
10074 SelectionDAG &DAG) {
10076 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10077 ArrayRef<int> Mask = SVOp->getMask();
10078 assert(Subtarget->hasAVX512() &&
10079 "Cannot lower 512-bit vectors w/ basic ISA!");
10081 // Dispatch to each element type for lowering. If we don't have supprot for
10082 // specific element type shuffles at 512 bits, immediately split them and
10083 // lower them. Each lowering routine of a given type is allowed to assume that
10084 // the requisite ISA extensions for that element type are available.
10085 switch (VT.SimpleTy) {
10087 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10089 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10091 if (Subtarget->hasDQI())
10092 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10095 if (Subtarget->hasDQI())
10096 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10099 if (Subtarget->hasBWI())
10100 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10103 if (Subtarget->hasBWI())
10104 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10108 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10111 // Otherwise fall back on splitting.
10112 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10115 /// \brief Helper function to test whether a shuffle mask could be
10116 /// simplified by widening the elements being shuffled.
10118 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10119 /// leaves it in an unspecified state.
10121 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10122 /// shuffle masks. The latter have the special property of a '-2' representing
10123 /// a zero-ed lane of a vector.
10124 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10125 SmallVectorImpl<int> &WidenedMask) {
10126 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10127 // If both elements are undef, its trivial.
10128 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10129 WidenedMask.push_back(SM_SentinelUndef);
10133 // Check for an undef mask and a mask value properly aligned to fit with
10134 // a pair of values. If we find such a case, use the non-undef mask's value.
10135 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10136 WidenedMask.push_back(Mask[i + 1] / 2);
10139 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10140 WidenedMask.push_back(Mask[i] / 2);
10144 // When zeroing, we need to spread the zeroing across both lanes to widen.
10145 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10146 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10147 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10148 WidenedMask.push_back(SM_SentinelZero);
10154 // Finally check if the two mask values are adjacent and aligned with
10156 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10157 WidenedMask.push_back(Mask[i] / 2);
10161 // Otherwise we can't safely widen the elements used in this shuffle.
10164 assert(WidenedMask.size() == Mask.size() / 2 &&
10165 "Incorrect size of mask after widening the elements!");
10170 /// \brief Top-level lowering for x86 vector shuffles.
10172 /// This handles decomposition, canonicalization, and lowering of all x86
10173 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10174 /// above in helper routines. The canonicalization attempts to widen shuffles
10175 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10176 /// s.t. only one of the two inputs needs to be tested, etc.
10177 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10178 SelectionDAG &DAG) {
10179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10180 ArrayRef<int> Mask = SVOp->getMask();
10181 SDValue V1 = Op.getOperand(0);
10182 SDValue V2 = Op.getOperand(1);
10183 MVT VT = Op.getSimpleValueType();
10184 int NumElements = VT.getVectorNumElements();
10187 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10189 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10190 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10191 if (V1IsUndef && V2IsUndef)
10192 return DAG.getUNDEF(VT);
10194 // When we create a shuffle node we put the UNDEF node to second operand,
10195 // but in some cases the first operand may be transformed to UNDEF.
10196 // In this case we should just commute the node.
10198 return DAG.getCommutedVectorShuffle(*SVOp);
10200 // Check for non-undef masks pointing at an undef vector and make the masks
10201 // undef as well. This makes it easier to match the shuffle based solely on
10205 if (M >= NumElements) {
10206 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10207 for (int &M : NewMask)
10208 if (M >= NumElements)
10210 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10213 // For integer vector shuffles, try to collapse them into a shuffle of fewer
10214 // lanes but wider integers. We cap this to not form integers larger than i64
10215 // but it might be interesting to form i128 integers to handle flipping the
10216 // low and high halves of AVX 256-bit vectors.
10217 SmallVector<int, 16> WidenedMask;
10218 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
10219 canWidenShuffleElements(Mask, WidenedMask)) {
10221 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
10222 VT.getVectorNumElements() / 2);
10223 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10224 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10225 return DAG.getNode(ISD::BITCAST, dl, VT,
10226 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10229 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10230 for (int M : SVOp->getMask())
10232 ++NumUndefElements;
10233 else if (M < NumElements)
10238 // Commute the shuffle as needed such that more elements come from V1 than
10239 // V2. This allows us to match the shuffle pattern strictly on how many
10240 // elements come from V1 without handling the symmetric cases.
10241 if (NumV2Elements > NumV1Elements)
10242 return DAG.getCommutedVectorShuffle(*SVOp);
10244 // When the number of V1 and V2 elements are the same, try to minimize the
10245 // number of uses of V2 in the low half of the vector. When that is tied,
10246 // ensure that the sum of indices for V1 is equal to or lower than the sum
10248 if (NumV1Elements == NumV2Elements) {
10249 int LowV1Elements = 0, LowV2Elements = 0;
10250 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10251 if (M >= NumElements)
10255 if (LowV2Elements > LowV1Elements) {
10256 return DAG.getCommutedVectorShuffle(*SVOp);
10257 } else if (LowV2Elements == LowV1Elements) {
10258 int SumV1Indices = 0, SumV2Indices = 0;
10259 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10260 if (SVOp->getMask()[i] >= NumElements)
10262 else if (SVOp->getMask()[i] >= 0)
10264 if (SumV2Indices < SumV1Indices)
10265 return DAG.getCommutedVectorShuffle(*SVOp);
10269 // For each vector width, delegate to a specialized lowering routine.
10270 if (VT.getSizeInBits() == 128)
10271 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10273 if (VT.getSizeInBits() == 256)
10274 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10276 // Force AVX-512 vectors to be scalarized for now.
10277 // FIXME: Implement AVX-512 support!
10278 if (VT.getSizeInBits() == 512)
10279 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10281 llvm_unreachable("Unimplemented!");
10285 //===----------------------------------------------------------------------===//
10286 // Legacy vector shuffle lowering
10288 // This code is the legacy code handling vector shuffles until the above
10289 // replaces its functionality and performance.
10290 //===----------------------------------------------------------------------===//
10292 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10293 bool hasInt256, unsigned *MaskOut = nullptr) {
10294 MVT EltVT = VT.getVectorElementType();
10296 // There is no blend with immediate in AVX-512.
10297 if (VT.is512BitVector())
10300 if (!hasSSE41 || EltVT == MVT::i8)
10302 if (!hasInt256 && VT == MVT::v16i16)
10305 unsigned MaskValue = 0;
10306 unsigned NumElems = VT.getVectorNumElements();
10307 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10308 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10309 unsigned NumElemsInLane = NumElems / NumLanes;
10311 // Blend for v16i16 should be symetric for the both lanes.
10312 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10314 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10315 int EltIdx = MaskVals[i];
10317 if ((EltIdx < 0 || EltIdx == (int)i) &&
10318 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10321 if (((unsigned)EltIdx == (i + NumElems)) &&
10322 (SndLaneEltIdx < 0 ||
10323 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10324 MaskValue |= (1 << i);
10330 *MaskOut = MaskValue;
10334 // Try to lower a shuffle node into a simple blend instruction.
10335 // This function assumes isBlendMask returns true for this
10336 // SuffleVectorSDNode
10337 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10338 unsigned MaskValue,
10339 const X86Subtarget *Subtarget,
10340 SelectionDAG &DAG) {
10341 MVT VT = SVOp->getSimpleValueType(0);
10342 MVT EltVT = VT.getVectorElementType();
10343 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10344 Subtarget->hasInt256() && "Trying to lower a "
10345 "VECTOR_SHUFFLE to a Blend but "
10346 "with the wrong mask"));
10347 SDValue V1 = SVOp->getOperand(0);
10348 SDValue V2 = SVOp->getOperand(1);
10350 unsigned NumElems = VT.getVectorNumElements();
10352 // Convert i32 vectors to floating point if it is not AVX2.
10353 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10355 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10356 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10358 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10359 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10362 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10363 DAG.getConstant(MaskValue, MVT::i32));
10364 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10367 /// In vector type \p VT, return true if the element at index \p InputIdx
10368 /// falls on a different 128-bit lane than \p OutputIdx.
10369 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10370 unsigned OutputIdx) {
10371 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10372 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10375 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10376 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10377 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10378 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10380 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10381 SelectionDAG &DAG) {
10382 MVT VT = V1.getSimpleValueType();
10383 assert(VT.is128BitVector() || VT.is256BitVector());
10385 MVT EltVT = VT.getVectorElementType();
10386 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10387 unsigned NumElts = VT.getVectorNumElements();
10389 SmallVector<SDValue, 32> PshufbMask;
10390 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10391 int InputIdx = MaskVals[OutputIdx];
10392 unsigned InputByteIdx;
10394 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10395 InputByteIdx = 0x80;
10397 // Cross lane is not allowed.
10398 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10400 InputByteIdx = InputIdx * EltSizeInBytes;
10401 // Index is an byte offset within the 128-bit lane.
10402 InputByteIdx &= 0xf;
10405 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10406 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10407 if (InputByteIdx != 0x80)
10412 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10414 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10415 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10416 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10419 // v8i16 shuffles - Prefer shuffles in the following order:
10420 // 1. [all] pshuflw, pshufhw, optional move
10421 // 2. [ssse3] 1 x pshufb
10422 // 3. [ssse3] 2 x pshufb + 1 x por
10423 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10425 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10427 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10428 SDValue V1 = SVOp->getOperand(0);
10429 SDValue V2 = SVOp->getOperand(1);
10431 SmallVector<int, 8> MaskVals;
10433 // Determine if more than 1 of the words in each of the low and high quadwords
10434 // of the result come from the same quadword of one of the two inputs. Undef
10435 // mask values count as coming from any quadword, for better codegen.
10437 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10438 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10439 unsigned LoQuad[] = { 0, 0, 0, 0 };
10440 unsigned HiQuad[] = { 0, 0, 0, 0 };
10441 // Indices of quads used.
10442 std::bitset<4> InputQuads;
10443 for (unsigned i = 0; i < 8; ++i) {
10444 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10445 int EltIdx = SVOp->getMaskElt(i);
10446 MaskVals.push_back(EltIdx);
10454 ++Quad[EltIdx / 4];
10455 InputQuads.set(EltIdx / 4);
10458 int BestLoQuad = -1;
10459 unsigned MaxQuad = 1;
10460 for (unsigned i = 0; i < 4; ++i) {
10461 if (LoQuad[i] > MaxQuad) {
10463 MaxQuad = LoQuad[i];
10467 int BestHiQuad = -1;
10469 for (unsigned i = 0; i < 4; ++i) {
10470 if (HiQuad[i] > MaxQuad) {
10472 MaxQuad = HiQuad[i];
10476 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10477 // of the two input vectors, shuffle them into one input vector so only a
10478 // single pshufb instruction is necessary. If there are more than 2 input
10479 // quads, disable the next transformation since it does not help SSSE3.
10480 bool V1Used = InputQuads[0] || InputQuads[1];
10481 bool V2Used = InputQuads[2] || InputQuads[3];
10482 if (Subtarget->hasSSSE3()) {
10483 if (InputQuads.count() == 2 && V1Used && V2Used) {
10484 BestLoQuad = InputQuads[0] ? 0 : 1;
10485 BestHiQuad = InputQuads[2] ? 2 : 3;
10487 if (InputQuads.count() > 2) {
10493 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10494 // the shuffle mask. If a quad is scored as -1, that means that it contains
10495 // words from all 4 input quadwords.
10497 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10499 BestLoQuad < 0 ? 0 : BestLoQuad,
10500 BestHiQuad < 0 ? 1 : BestHiQuad
10502 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10503 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10504 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10505 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10507 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10508 // source words for the shuffle, to aid later transformations.
10509 bool AllWordsInNewV = true;
10510 bool InOrder[2] = { true, true };
10511 for (unsigned i = 0; i != 8; ++i) {
10512 int idx = MaskVals[i];
10514 InOrder[i/4] = false;
10515 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10517 AllWordsInNewV = false;
10521 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10522 if (AllWordsInNewV) {
10523 for (int i = 0; i != 8; ++i) {
10524 int idx = MaskVals[i];
10527 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10528 if ((idx != i) && idx < 4)
10530 if ((idx != i) && idx > 3)
10539 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10540 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10541 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10542 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10543 unsigned TargetMask = 0;
10544 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10545 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10547 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10548 getShufflePSHUFLWImmediate(SVOp);
10549 V1 = NewV.getOperand(0);
10550 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10554 // Promote splats to a larger type which usually leads to more efficient code.
10555 // FIXME: Is this true if pshufb is available?
10556 if (SVOp->isSplat())
10557 return PromoteSplat(SVOp, DAG);
10559 // If we have SSSE3, and all words of the result are from 1 input vector,
10560 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10561 // is present, fall back to case 4.
10562 if (Subtarget->hasSSSE3()) {
10563 SmallVector<SDValue,16> pshufbMask;
10565 // If we have elements from both input vectors, set the high bit of the
10566 // shuffle mask element to zero out elements that come from V2 in the V1
10567 // mask, and elements that come from V1 in the V2 mask, so that the two
10568 // results can be OR'd together.
10569 bool TwoInputs = V1Used && V2Used;
10570 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10572 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10574 // Calculate the shuffle mask for the second input, shuffle it, and
10575 // OR it with the first shuffled input.
10576 CommuteVectorShuffleMask(MaskVals, 8);
10577 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10578 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10579 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10582 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10583 // and update MaskVals with new element order.
10584 std::bitset<8> InOrder;
10585 if (BestLoQuad >= 0) {
10586 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10587 for (int i = 0; i != 4; ++i) {
10588 int idx = MaskVals[i];
10591 } else if ((idx / 4) == BestLoQuad) {
10592 MaskV[i] = idx & 3;
10596 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10599 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10600 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10601 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10602 NewV.getOperand(0),
10603 getShufflePSHUFLWImmediate(SVOp), DAG);
10607 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10608 // and update MaskVals with the new element order.
10609 if (BestHiQuad >= 0) {
10610 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10611 for (unsigned i = 4; i != 8; ++i) {
10612 int idx = MaskVals[i];
10615 } else if ((idx / 4) == BestHiQuad) {
10616 MaskV[i] = (idx & 3) + 4;
10620 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10623 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10624 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10625 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10626 NewV.getOperand(0),
10627 getShufflePSHUFHWImmediate(SVOp), DAG);
10631 // In case BestHi & BestLo were both -1, which means each quadword has a word
10632 // from each of the four input quadwords, calculate the InOrder bitvector now
10633 // before falling through to the insert/extract cleanup.
10634 if (BestLoQuad == -1 && BestHiQuad == -1) {
10636 for (int i = 0; i != 8; ++i)
10637 if (MaskVals[i] < 0 || MaskVals[i] == i)
10641 // The other elements are put in the right place using pextrw and pinsrw.
10642 for (unsigned i = 0; i != 8; ++i) {
10645 int EltIdx = MaskVals[i];
10648 SDValue ExtOp = (EltIdx < 8) ?
10649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10650 DAG.getIntPtrConstant(EltIdx)) :
10651 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10652 DAG.getIntPtrConstant(EltIdx - 8));
10653 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10654 DAG.getIntPtrConstant(i));
10659 /// \brief v16i16 shuffles
10661 /// FIXME: We only support generation of a single pshufb currently. We can
10662 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10663 /// well (e.g 2 x pshufb + 1 x por).
10665 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10666 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10667 SDValue V1 = SVOp->getOperand(0);
10668 SDValue V2 = SVOp->getOperand(1);
10671 if (V2.getOpcode() != ISD::UNDEF)
10674 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10675 return getPSHUFB(MaskVals, V1, dl, DAG);
10678 // v16i8 shuffles - Prefer shuffles in the following order:
10679 // 1. [ssse3] 1 x pshufb
10680 // 2. [ssse3] 2 x pshufb + 1 x por
10681 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10682 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10683 const X86Subtarget* Subtarget,
10684 SelectionDAG &DAG) {
10685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10686 SDValue V1 = SVOp->getOperand(0);
10687 SDValue V2 = SVOp->getOperand(1);
10689 ArrayRef<int> MaskVals = SVOp->getMask();
10691 // Promote splats to a larger type which usually leads to more efficient code.
10692 // FIXME: Is this true if pshufb is available?
10693 if (SVOp->isSplat())
10694 return PromoteSplat(SVOp, DAG);
10696 // If we have SSSE3, case 1 is generated when all result bytes come from
10697 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10698 // present, fall back to case 3.
10700 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10701 if (Subtarget->hasSSSE3()) {
10702 SmallVector<SDValue,16> pshufbMask;
10704 // If all result elements are from one input vector, then only translate
10705 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10707 // Otherwise, we have elements from both input vectors, and must zero out
10708 // elements that come from V2 in the first mask, and V1 in the second mask
10709 // so that we can OR them together.
10710 for (unsigned i = 0; i != 16; ++i) {
10711 int EltIdx = MaskVals[i];
10712 if (EltIdx < 0 || EltIdx >= 16)
10714 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10716 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10717 DAG.getNode(ISD::BUILD_VECTOR, dl,
10718 MVT::v16i8, pshufbMask));
10720 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10721 // the 2nd operand if it's undefined or zero.
10722 if (V2.getOpcode() == ISD::UNDEF ||
10723 ISD::isBuildVectorAllZeros(V2.getNode()))
10726 // Calculate the shuffle mask for the second input, shuffle it, and
10727 // OR it with the first shuffled input.
10728 pshufbMask.clear();
10729 for (unsigned i = 0; i != 16; ++i) {
10730 int EltIdx = MaskVals[i];
10731 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10732 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10734 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10735 DAG.getNode(ISD::BUILD_VECTOR, dl,
10736 MVT::v16i8, pshufbMask));
10737 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10740 // No SSSE3 - Calculate in place words and then fix all out of place words
10741 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10742 // the 16 different words that comprise the two doublequadword input vectors.
10743 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10744 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10746 for (int i = 0; i != 8; ++i) {
10747 int Elt0 = MaskVals[i*2];
10748 int Elt1 = MaskVals[i*2+1];
10750 // This word of the result is all undef, skip it.
10751 if (Elt0 < 0 && Elt1 < 0)
10754 // This word of the result is already in the correct place, skip it.
10755 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10758 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10759 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10762 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10763 // using a single extract together, load it and store it.
10764 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10765 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10766 DAG.getIntPtrConstant(Elt1 / 2));
10767 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10768 DAG.getIntPtrConstant(i));
10772 // If Elt1 is defined, extract it from the appropriate source. If the
10773 // source byte is not also odd, shift the extracted word left 8 bits
10774 // otherwise clear the bottom 8 bits if we need to do an or.
10776 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10777 DAG.getIntPtrConstant(Elt1 / 2));
10778 if ((Elt1 & 1) == 0)
10779 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10781 TLI.getShiftAmountTy(InsElt.getValueType())));
10782 else if (Elt0 >= 0)
10783 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10784 DAG.getConstant(0xFF00, MVT::i16));
10786 // If Elt0 is defined, extract it from the appropriate source. If the
10787 // source byte is not also even, shift the extracted word right 8 bits. If
10788 // Elt1 was also defined, OR the extracted values together before
10789 // inserting them in the result.
10791 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10792 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10793 if ((Elt0 & 1) != 0)
10794 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10796 TLI.getShiftAmountTy(InsElt0.getValueType())));
10797 else if (Elt1 >= 0)
10798 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10799 DAG.getConstant(0x00FF, MVT::i16));
10800 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10803 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10804 DAG.getIntPtrConstant(i));
10806 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10809 // v32i8 shuffles - Translate to VPSHUFB if possible.
10811 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10812 const X86Subtarget *Subtarget,
10813 SelectionDAG &DAG) {
10814 MVT VT = SVOp->getSimpleValueType(0);
10815 SDValue V1 = SVOp->getOperand(0);
10816 SDValue V2 = SVOp->getOperand(1);
10818 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10820 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10821 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10822 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10824 // VPSHUFB may be generated if
10825 // (1) one of input vector is undefined or zeroinitializer.
10826 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10827 // And (2) the mask indexes don't cross the 128-bit lane.
10828 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10829 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10832 if (V1IsAllZero && !V2IsAllZero) {
10833 CommuteVectorShuffleMask(MaskVals, 32);
10836 return getPSHUFB(MaskVals, V1, dl, DAG);
10839 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10840 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10841 /// done when every pair / quad of shuffle mask elements point to elements in
10842 /// the right sequence. e.g.
10843 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10845 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10846 SelectionDAG &DAG) {
10847 MVT VT = SVOp->getSimpleValueType(0);
10849 unsigned NumElems = VT.getVectorNumElements();
10852 switch (VT.SimpleTy) {
10853 default: llvm_unreachable("Unexpected!");
10856 return SDValue(SVOp, 0);
10857 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10858 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10859 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10860 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10861 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10862 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10865 SmallVector<int, 8> MaskVec;
10866 for (unsigned i = 0; i != NumElems; i += Scale) {
10868 for (unsigned j = 0; j != Scale; ++j) {
10869 int EltIdx = SVOp->getMaskElt(i+j);
10873 StartIdx = (EltIdx / Scale);
10874 if (EltIdx != (int)(StartIdx*Scale + j))
10877 MaskVec.push_back(StartIdx);
10880 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10881 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10882 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10885 /// getVZextMovL - Return a zero-extending vector move low node.
10887 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10888 SDValue SrcOp, SelectionDAG &DAG,
10889 const X86Subtarget *Subtarget, SDLoc dl) {
10890 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10891 LoadSDNode *LD = nullptr;
10892 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10893 LD = dyn_cast<LoadSDNode>(SrcOp);
10895 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10897 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10898 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10899 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10900 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10901 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10903 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10904 return DAG.getNode(ISD::BITCAST, dl, VT,
10905 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10906 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10908 SrcOp.getOperand(0)
10914 return DAG.getNode(ISD::BITCAST, dl, VT,
10915 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10916 DAG.getNode(ISD::BITCAST, dl,
10920 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10921 /// which could not be matched by any known target speficic shuffle
10923 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10925 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10926 if (NewOp.getNode())
10929 MVT VT = SVOp->getSimpleValueType(0);
10931 unsigned NumElems = VT.getVectorNumElements();
10932 unsigned NumLaneElems = NumElems / 2;
10935 MVT EltVT = VT.getVectorElementType();
10936 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10939 SmallVector<int, 16> Mask;
10940 for (unsigned l = 0; l < 2; ++l) {
10941 // Build a shuffle mask for the output, discovering on the fly which
10942 // input vectors to use as shuffle operands (recorded in InputUsed).
10943 // If building a suitable shuffle vector proves too hard, then bail
10944 // out with UseBuildVector set.
10945 bool UseBuildVector = false;
10946 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10947 unsigned LaneStart = l * NumLaneElems;
10948 for (unsigned i = 0; i != NumLaneElems; ++i) {
10949 // The mask element. This indexes into the input.
10950 int Idx = SVOp->getMaskElt(i+LaneStart);
10952 // the mask element does not index into any input vector.
10953 Mask.push_back(-1);
10957 // The input vector this mask element indexes into.
10958 int Input = Idx / NumLaneElems;
10960 // Turn the index into an offset from the start of the input vector.
10961 Idx -= Input * NumLaneElems;
10963 // Find or create a shuffle vector operand to hold this input.
10965 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10966 if (InputUsed[OpNo] == Input)
10967 // This input vector is already an operand.
10969 if (InputUsed[OpNo] < 0) {
10970 // Create a new operand for this input vector.
10971 InputUsed[OpNo] = Input;
10976 if (OpNo >= array_lengthof(InputUsed)) {
10977 // More than two input vectors used! Give up on trying to create a
10978 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10979 UseBuildVector = true;
10983 // Add the mask index for the new shuffle vector.
10984 Mask.push_back(Idx + OpNo * NumLaneElems);
10987 if (UseBuildVector) {
10988 SmallVector<SDValue, 16> SVOps;
10989 for (unsigned i = 0; i != NumLaneElems; ++i) {
10990 // The mask element. This indexes into the input.
10991 int Idx = SVOp->getMaskElt(i+LaneStart);
10993 SVOps.push_back(DAG.getUNDEF(EltVT));
10997 // The input vector this mask element indexes into.
10998 int Input = Idx / NumElems;
11000 // Turn the index into an offset from the start of the input vector.
11001 Idx -= Input * NumElems;
11003 // Extract the vector element by hand.
11004 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11005 SVOp->getOperand(Input),
11006 DAG.getIntPtrConstant(Idx)));
11009 // Construct the output using a BUILD_VECTOR.
11010 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11011 } else if (InputUsed[0] < 0) {
11012 // No input vectors were used! The result is undefined.
11013 Output[l] = DAG.getUNDEF(NVT);
11015 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11016 (InputUsed[0] % 2) * NumLaneElems,
11018 // If only one input was used, use an undefined vector for the other.
11019 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11020 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11021 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11022 // At least one input vector was used. Create a new shuffle vector.
11023 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11029 // Concatenate the result back
11030 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11033 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11034 /// 4 elements, and match them with several different shuffle types.
11036 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11037 SDValue V1 = SVOp->getOperand(0);
11038 SDValue V2 = SVOp->getOperand(1);
11040 MVT VT = SVOp->getSimpleValueType(0);
11042 assert(VT.is128BitVector() && "Unsupported vector size");
11044 std::pair<int, int> Locs[4];
11045 int Mask1[] = { -1, -1, -1, -1 };
11046 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11048 unsigned NumHi = 0;
11049 unsigned NumLo = 0;
11050 for (unsigned i = 0; i != 4; ++i) {
11051 int Idx = PermMask[i];
11053 Locs[i] = std::make_pair(-1, -1);
11055 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11057 Locs[i] = std::make_pair(0, NumLo);
11058 Mask1[NumLo] = Idx;
11061 Locs[i] = std::make_pair(1, NumHi);
11063 Mask1[2+NumHi] = Idx;
11069 if (NumLo <= 2 && NumHi <= 2) {
11070 // If no more than two elements come from either vector. This can be
11071 // implemented with two shuffles. First shuffle gather the elements.
11072 // The second shuffle, which takes the first shuffle as both of its
11073 // vector operands, put the elements into the right order.
11074 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11076 int Mask2[] = { -1, -1, -1, -1 };
11078 for (unsigned i = 0; i != 4; ++i)
11079 if (Locs[i].first != -1) {
11080 unsigned Idx = (i < 2) ? 0 : 4;
11081 Idx += Locs[i].first * 2 + Locs[i].second;
11085 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11088 if (NumLo == 3 || NumHi == 3) {
11089 // Otherwise, we must have three elements from one vector, call it X, and
11090 // one element from the other, call it Y. First, use a shufps to build an
11091 // intermediate vector with the one element from Y and the element from X
11092 // that will be in the same half in the final destination (the indexes don't
11093 // matter). Then, use a shufps to build the final vector, taking the half
11094 // containing the element from Y from the intermediate, and the other half
11097 // Normalize it so the 3 elements come from V1.
11098 CommuteVectorShuffleMask(PermMask, 4);
11102 // Find the element from V2.
11104 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11105 int Val = PermMask[HiIndex];
11112 Mask1[0] = PermMask[HiIndex];
11114 Mask1[2] = PermMask[HiIndex^1];
11116 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11118 if (HiIndex >= 2) {
11119 Mask1[0] = PermMask[0];
11120 Mask1[1] = PermMask[1];
11121 Mask1[2] = HiIndex & 1 ? 6 : 4;
11122 Mask1[3] = HiIndex & 1 ? 4 : 6;
11123 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11126 Mask1[0] = HiIndex & 1 ? 2 : 0;
11127 Mask1[1] = HiIndex & 1 ? 0 : 2;
11128 Mask1[2] = PermMask[2];
11129 Mask1[3] = PermMask[3];
11134 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11137 // Break it into (shuffle shuffle_hi, shuffle_lo).
11138 int LoMask[] = { -1, -1, -1, -1 };
11139 int HiMask[] = { -1, -1, -1, -1 };
11141 int *MaskPtr = LoMask;
11142 unsigned MaskIdx = 0;
11143 unsigned LoIdx = 0;
11144 unsigned HiIdx = 2;
11145 for (unsigned i = 0; i != 4; ++i) {
11152 int Idx = PermMask[i];
11154 Locs[i] = std::make_pair(-1, -1);
11155 } else if (Idx < 4) {
11156 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11157 MaskPtr[LoIdx] = Idx;
11160 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11161 MaskPtr[HiIdx] = Idx;
11166 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11167 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11168 int MaskOps[] = { -1, -1, -1, -1 };
11169 for (unsigned i = 0; i != 4; ++i)
11170 if (Locs[i].first != -1)
11171 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11172 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11175 static bool MayFoldVectorLoad(SDValue V) {
11176 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11177 V = V.getOperand(0);
11179 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11180 V = V.getOperand(0);
11181 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11182 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11183 // BUILD_VECTOR (load), undef
11184 V = V.getOperand(0);
11186 return MayFoldLoad(V);
11190 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11191 MVT VT = Op.getSimpleValueType();
11193 // Canonizalize to v2f64.
11194 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11195 return DAG.getNode(ISD::BITCAST, dl, VT,
11196 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11201 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11203 SDValue V1 = Op.getOperand(0);
11204 SDValue V2 = Op.getOperand(1);
11205 MVT VT = Op.getSimpleValueType();
11207 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11209 if (HasSSE2 && VT == MVT::v2f64)
11210 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11212 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11213 return DAG.getNode(ISD::BITCAST, dl, VT,
11214 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11215 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11216 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11220 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11221 SDValue V1 = Op.getOperand(0);
11222 SDValue V2 = Op.getOperand(1);
11223 MVT VT = Op.getSimpleValueType();
11225 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11226 "unsupported shuffle type");
11228 if (V2.getOpcode() == ISD::UNDEF)
11232 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11236 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11237 SDValue V1 = Op.getOperand(0);
11238 SDValue V2 = Op.getOperand(1);
11239 MVT VT = Op.getSimpleValueType();
11240 unsigned NumElems = VT.getVectorNumElements();
11242 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11243 // operand of these instructions is only memory, so check if there's a
11244 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11246 bool CanFoldLoad = false;
11248 // Trivial case, when V2 comes from a load.
11249 if (MayFoldVectorLoad(V2))
11250 CanFoldLoad = true;
11252 // When V1 is a load, it can be folded later into a store in isel, example:
11253 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11255 // (MOVLPSmr addr:$src1, VR128:$src2)
11256 // So, recognize this potential and also use MOVLPS or MOVLPD
11257 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11258 CanFoldLoad = true;
11260 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11262 if (HasSSE2 && NumElems == 2)
11263 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11266 // If we don't care about the second element, proceed to use movss.
11267 if (SVOp->getMaskElt(1) != -1)
11268 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11271 // movl and movlp will both match v2i64, but v2i64 is never matched by
11272 // movl earlier because we make it strict to avoid messing with the movlp load
11273 // folding logic (see the code above getMOVLP call). Match it here then,
11274 // this is horrible, but will stay like this until we move all shuffle
11275 // matching to x86 specific nodes. Note that for the 1st condition all
11276 // types are matched with movsd.
11278 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11279 // as to remove this logic from here, as much as possible
11280 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11281 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11282 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11285 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11287 // Invert the operand order and use SHUFPS to match it.
11288 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11289 getShuffleSHUFImmediate(SVOp), DAG);
11292 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11293 SelectionDAG &DAG) {
11295 MVT VT = Load->getSimpleValueType(0);
11296 MVT EVT = VT.getVectorElementType();
11297 SDValue Addr = Load->getOperand(1);
11298 SDValue NewAddr = DAG.getNode(
11299 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11300 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11303 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11304 DAG.getMachineFunction().getMachineMemOperand(
11305 Load->getMemOperand(), 0, EVT.getStoreSize()));
11309 // It is only safe to call this function if isINSERTPSMask is true for
11310 // this shufflevector mask.
11311 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11312 SelectionDAG &DAG) {
11313 // Generate an insertps instruction when inserting an f32 from memory onto a
11314 // v4f32 or when copying a member from one v4f32 to another.
11315 // We also use it for transferring i32 from one register to another,
11316 // since it simply copies the same bits.
11317 // If we're transferring an i32 from memory to a specific element in a
11318 // register, we output a generic DAG that will match the PINSRD
11320 MVT VT = SVOp->getSimpleValueType(0);
11321 MVT EVT = VT.getVectorElementType();
11322 SDValue V1 = SVOp->getOperand(0);
11323 SDValue V2 = SVOp->getOperand(1);
11324 auto Mask = SVOp->getMask();
11325 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11326 "unsupported vector type for insertps/pinsrd");
11328 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11329 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11330 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11334 unsigned DestIndex;
11338 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11341 // If we have 1 element from each vector, we have to check if we're
11342 // changing V1's element's place. If so, we're done. Otherwise, we
11343 // should assume we're changing V2's element's place and behave
11345 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11346 assert(DestIndex <= INT32_MAX && "truncated destination index");
11347 if (FromV1 == FromV2 &&
11348 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11352 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11355 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11356 "More than one element from V1 and from V2, or no elements from one "
11357 "of the vectors. This case should not have returned true from "
11362 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11365 // Get an index into the source vector in the range [0,4) (the mask is
11366 // in the range [0,8) because it can address V1 and V2)
11367 unsigned SrcIndex = Mask[DestIndex] % 4;
11368 if (MayFoldLoad(From)) {
11369 // Trivial case, when From comes from a load and is only used by the
11370 // shuffle. Make it use insertps from the vector that we need from that
11373 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11374 if (!NewLoad.getNode())
11377 if (EVT == MVT::f32) {
11378 // Create this as a scalar to vector to match the instruction pattern.
11379 SDValue LoadScalarToVector =
11380 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11381 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11382 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11384 } else { // EVT == MVT::i32
11385 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11386 // instruction, to match the PINSRD instruction, which loads an i32 to a
11387 // certain vector element.
11388 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11389 DAG.getConstant(DestIndex, MVT::i32));
11393 // Vector-element-to-vector
11394 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11395 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11398 // Reduce a vector shuffle to zext.
11399 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11400 SelectionDAG &DAG) {
11401 // PMOVZX is only available from SSE41.
11402 if (!Subtarget->hasSSE41())
11405 MVT VT = Op.getSimpleValueType();
11407 // Only AVX2 support 256-bit vector integer extending.
11408 if (!Subtarget->hasInt256() && VT.is256BitVector())
11411 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11413 SDValue V1 = Op.getOperand(0);
11414 SDValue V2 = Op.getOperand(1);
11415 unsigned NumElems = VT.getVectorNumElements();
11417 // Extending is an unary operation and the element type of the source vector
11418 // won't be equal to or larger than i64.
11419 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11420 VT.getVectorElementType() == MVT::i64)
11423 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11424 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11425 while ((1U << Shift) < NumElems) {
11426 if (SVOp->getMaskElt(1U << Shift) == 1)
11429 // The maximal ratio is 8, i.e. from i8 to i64.
11434 // Check the shuffle mask.
11435 unsigned Mask = (1U << Shift) - 1;
11436 for (unsigned i = 0; i != NumElems; ++i) {
11437 int EltIdx = SVOp->getMaskElt(i);
11438 if ((i & Mask) != 0 && EltIdx != -1)
11440 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11444 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11445 MVT NeVT = MVT::getIntegerVT(NBits);
11446 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11448 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11451 // Simplify the operand as it's prepared to be fed into shuffle.
11452 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11453 if (V1.getOpcode() == ISD::BITCAST &&
11454 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11455 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11456 V1.getOperand(0).getOperand(0)
11457 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11458 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11459 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11460 ConstantSDNode *CIdx =
11461 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11462 // If it's foldable, i.e. normal load with single use, we will let code
11463 // selection to fold it. Otherwise, we will short the conversion sequence.
11464 if (CIdx && CIdx->getZExtValue() == 0 &&
11465 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11466 MVT FullVT = V.getSimpleValueType();
11467 MVT V1VT = V1.getSimpleValueType();
11468 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11469 // The "ext_vec_elt" node is wider than the result node.
11470 // In this case we should extract subvector from V.
11471 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11472 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11473 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11474 FullVT.getVectorNumElements()/Ratio);
11475 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11476 DAG.getIntPtrConstant(0));
11478 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11482 return DAG.getNode(ISD::BITCAST, DL, VT,
11483 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11486 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11487 SelectionDAG &DAG) {
11488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11489 MVT VT = Op.getSimpleValueType();
11491 SDValue V1 = Op.getOperand(0);
11492 SDValue V2 = Op.getOperand(1);
11494 if (isZeroShuffle(SVOp))
11495 return getZeroVector(VT, Subtarget, DAG, dl);
11497 // Handle splat operations
11498 if (SVOp->isSplat()) {
11499 // Use vbroadcast whenever the splat comes from a foldable load
11500 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11501 if (Broadcast.getNode())
11505 // Check integer expanding shuffles.
11506 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11507 if (NewOp.getNode())
11510 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11512 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11513 VT == MVT::v32i8) {
11514 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11515 if (NewOp.getNode())
11516 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11517 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11518 // FIXME: Figure out a cleaner way to do this.
11519 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11520 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11521 if (NewOp.getNode()) {
11522 MVT NewVT = NewOp.getSimpleValueType();
11523 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11524 NewVT, true, false))
11525 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11528 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11529 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11530 if (NewOp.getNode()) {
11531 MVT NewVT = NewOp.getSimpleValueType();
11532 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11533 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11542 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11543 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11544 SDValue V1 = Op.getOperand(0);
11545 SDValue V2 = Op.getOperand(1);
11546 MVT VT = Op.getSimpleValueType();
11548 unsigned NumElems = VT.getVectorNumElements();
11549 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11550 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11551 bool V1IsSplat = false;
11552 bool V2IsSplat = false;
11553 bool HasSSE2 = Subtarget->hasSSE2();
11554 bool HasFp256 = Subtarget->hasFp256();
11555 bool HasInt256 = Subtarget->hasInt256();
11556 MachineFunction &MF = DAG.getMachineFunction();
11557 bool OptForSize = MF.getFunction()->getAttributes().
11558 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11560 // Check if we should use the experimental vector shuffle lowering. If so,
11561 // delegate completely to that code path.
11562 if (ExperimentalVectorShuffleLowering)
11563 return lowerVectorShuffle(Op, Subtarget, DAG);
11565 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11567 if (V1IsUndef && V2IsUndef)
11568 return DAG.getUNDEF(VT);
11570 // When we create a shuffle node we put the UNDEF node to second operand,
11571 // but in some cases the first operand may be transformed to UNDEF.
11572 // In this case we should just commute the node.
11574 return DAG.getCommutedVectorShuffle(*SVOp);
11576 // Vector shuffle lowering takes 3 steps:
11578 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11579 // narrowing and commutation of operands should be handled.
11580 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11582 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11583 // so the shuffle can be broken into other shuffles and the legalizer can
11584 // try the lowering again.
11586 // The general idea is that no vector_shuffle operation should be left to
11587 // be matched during isel, all of them must be converted to a target specific
11590 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11591 // narrowing and commutation of operands should be handled. The actual code
11592 // doesn't include all of those, work in progress...
11593 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11594 if (NewOp.getNode())
11597 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11599 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11600 // unpckh_undef). Only use pshufd if speed is more important than size.
11601 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11602 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11603 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11604 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11606 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11607 V2IsUndef && MayFoldVectorLoad(V1))
11608 return getMOVDDup(Op, dl, V1, DAG);
11610 if (isMOVHLPS_v_undef_Mask(M, VT))
11611 return getMOVHighToLow(Op, dl, DAG);
11613 // Use to match splats
11614 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11615 (VT == MVT::v2f64 || VT == MVT::v2i64))
11616 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11618 if (isPSHUFDMask(M, VT)) {
11619 // The actual implementation will match the mask in the if above and then
11620 // during isel it can match several different instructions, not only pshufd
11621 // as its name says, sad but true, emulate the behavior for now...
11622 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11623 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11625 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11627 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11628 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11630 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11631 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11634 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11638 if (isPALIGNRMask(M, VT, Subtarget))
11639 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11640 getShufflePALIGNRImmediate(SVOp),
11643 if (isVALIGNMask(M, VT, Subtarget))
11644 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11645 getShuffleVALIGNImmediate(SVOp),
11648 // Check if this can be converted into a logical shift.
11649 bool isLeft = false;
11650 unsigned ShAmt = 0;
11652 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11653 if (isShift && ShVal.hasOneUse()) {
11654 // If the shifted value has multiple uses, it may be cheaper to use
11655 // v_set0 + movlhps or movhlps, etc.
11656 MVT EltVT = VT.getVectorElementType();
11657 ShAmt *= EltVT.getSizeInBits();
11658 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11661 if (isMOVLMask(M, VT)) {
11662 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11663 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11664 if (!isMOVLPMask(M, VT)) {
11665 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11666 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11668 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11669 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11673 // FIXME: fold these into legal mask.
11674 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11675 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11677 if (isMOVHLPSMask(M, VT))
11678 return getMOVHighToLow(Op, dl, DAG);
11680 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11681 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11683 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11684 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11686 if (isMOVLPMask(M, VT))
11687 return getMOVLP(Op, dl, DAG, HasSSE2);
11689 if (ShouldXformToMOVHLPS(M, VT) ||
11690 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11691 return DAG.getCommutedVectorShuffle(*SVOp);
11694 // No better options. Use a vshldq / vsrldq.
11695 MVT EltVT = VT.getVectorElementType();
11696 ShAmt *= EltVT.getSizeInBits();
11697 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11700 bool Commuted = false;
11701 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11702 // 1,1,1,1 -> v8i16 though.
11703 BitVector UndefElements;
11704 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11705 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11707 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11708 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11711 // Canonicalize the splat or undef, if present, to be on the RHS.
11712 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11713 CommuteVectorShuffleMask(M, NumElems);
11715 std::swap(V1IsSplat, V2IsSplat);
11719 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11720 // Shuffling low element of v1 into undef, just return v1.
11723 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11724 // the instruction selector will not match, so get a canonical MOVL with
11725 // swapped operands to undo the commute.
11726 return getMOVL(DAG, dl, VT, V2, V1);
11729 if (isUNPCKLMask(M, VT, HasInt256))
11730 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11732 if (isUNPCKHMask(M, VT, HasInt256))
11733 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11736 // Normalize mask so all entries that point to V2 points to its first
11737 // element then try to match unpck{h|l} again. If match, return a
11738 // new vector_shuffle with the corrected mask.p
11739 SmallVector<int, 8> NewMask(M.begin(), M.end());
11740 NormalizeMask(NewMask, NumElems);
11741 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11742 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11743 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11744 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11748 // Commute is back and try unpck* again.
11749 // FIXME: this seems wrong.
11750 CommuteVectorShuffleMask(M, NumElems);
11752 std::swap(V1IsSplat, V2IsSplat);
11754 if (isUNPCKLMask(M, VT, HasInt256))
11755 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11757 if (isUNPCKHMask(M, VT, HasInt256))
11758 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11761 // Normalize the node to match x86 shuffle ops if needed
11762 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11763 return DAG.getCommutedVectorShuffle(*SVOp);
11765 // The checks below are all present in isShuffleMaskLegal, but they are
11766 // inlined here right now to enable us to directly emit target specific
11767 // nodes, and remove one by one until they don't return Op anymore.
11769 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11770 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11771 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11772 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11775 if (isPSHUFHWMask(M, VT, HasInt256))
11776 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11777 getShufflePSHUFHWImmediate(SVOp),
11780 if (isPSHUFLWMask(M, VT, HasInt256))
11781 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11782 getShufflePSHUFLWImmediate(SVOp),
11785 unsigned MaskValue;
11786 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11788 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11790 if (isSHUFPMask(M, VT))
11791 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11792 getShuffleSHUFImmediate(SVOp), DAG);
11794 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11795 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11796 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11797 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11799 //===--------------------------------------------------------------------===//
11800 // Generate target specific nodes for 128 or 256-bit shuffles only
11801 // supported in the AVX instruction set.
11804 // Handle VMOVDDUPY permutations
11805 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11806 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11808 // Handle VPERMILPS/D* permutations
11809 if (isVPERMILPMask(M, VT)) {
11810 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11811 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11812 getShuffleSHUFImmediate(SVOp), DAG);
11813 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11814 getShuffleSHUFImmediate(SVOp), DAG);
11818 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11819 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11820 Idx*(NumElems/2), DAG, dl);
11822 // Handle VPERM2F128/VPERM2I128 permutations
11823 if (isVPERM2X128Mask(M, VT, HasFp256))
11824 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11825 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11827 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11828 return getINSERTPS(SVOp, dl, DAG);
11831 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11832 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11834 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11835 VT.is512BitVector()) {
11836 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11837 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11838 SmallVector<SDValue, 16> permclMask;
11839 for (unsigned i = 0; i != NumElems; ++i) {
11840 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11843 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11845 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11846 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11847 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11848 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11849 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11852 //===--------------------------------------------------------------------===//
11853 // Since no target specific shuffle was selected for this generic one,
11854 // lower it into other known shuffles. FIXME: this isn't true yet, but
11855 // this is the plan.
11858 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11859 if (VT == MVT::v8i16) {
11860 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11861 if (NewOp.getNode())
11865 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11866 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11867 if (NewOp.getNode())
11871 if (VT == MVT::v16i8) {
11872 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11873 if (NewOp.getNode())
11877 if (VT == MVT::v32i8) {
11878 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11879 if (NewOp.getNode())
11883 // Handle all 128-bit wide vectors with 4 elements, and match them with
11884 // several different shuffle types.
11885 if (NumElems == 4 && VT.is128BitVector())
11886 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11888 // Handle general 256-bit shuffles
11889 if (VT.is256BitVector())
11890 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11895 // This function assumes its argument is a BUILD_VECTOR of constants or
11896 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11898 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11899 unsigned &MaskValue) {
11901 unsigned NumElems = BuildVector->getNumOperands();
11902 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11903 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11904 unsigned NumElemsInLane = NumElems / NumLanes;
11906 // Blend for v16i16 should be symetric for the both lanes.
11907 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11908 SDValue EltCond = BuildVector->getOperand(i);
11909 SDValue SndLaneEltCond =
11910 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11912 int Lane1Cond = -1, Lane2Cond = -1;
11913 if (isa<ConstantSDNode>(EltCond))
11914 Lane1Cond = !isZero(EltCond);
11915 if (isa<ConstantSDNode>(SndLaneEltCond))
11916 Lane2Cond = !isZero(SndLaneEltCond);
11918 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11919 // Lane1Cond != 0, means we want the first argument.
11920 // Lane1Cond == 0, means we want the second argument.
11921 // The encoding of this argument is 0 for the first argument, 1
11922 // for the second. Therefore, invert the condition.
11923 MaskValue |= !Lane1Cond << i;
11924 else if (Lane1Cond < 0)
11925 MaskValue |= !Lane2Cond << i;
11932 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11934 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11935 SelectionDAG &DAG) {
11936 SDValue Cond = Op.getOperand(0);
11937 SDValue LHS = Op.getOperand(1);
11938 SDValue RHS = Op.getOperand(2);
11940 MVT VT = Op.getSimpleValueType();
11941 MVT EltVT = VT.getVectorElementType();
11942 unsigned NumElems = VT.getVectorNumElements();
11944 // There is no blend with immediate in AVX-512.
11945 if (VT.is512BitVector())
11948 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11950 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11953 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11956 // Check the mask for BLEND and build the value.
11957 unsigned MaskValue = 0;
11958 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11961 // Convert i32 vectors to floating point if it is not AVX2.
11962 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11964 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11965 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11967 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11968 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11971 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11972 DAG.getConstant(MaskValue, MVT::i32));
11973 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11976 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11977 // A vselect where all conditions and data are constants can be optimized into
11978 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11979 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11980 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11981 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11984 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
11985 if (BlendOp.getNode())
11988 // Some types for vselect were previously set to Expand, not Legal or
11989 // Custom. Return an empty SDValue so we fall-through to Expand, after
11990 // the Custom lowering phase.
11991 MVT VT = Op.getSimpleValueType();
11992 switch (VT.SimpleTy) {
11997 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12002 // We couldn't create a "Blend with immediate" node.
12003 // This node should still be legal, but we'll have to emit a blendv*
12008 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12009 MVT VT = Op.getSimpleValueType();
12012 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12015 if (VT.getSizeInBits() == 8) {
12016 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12017 Op.getOperand(0), Op.getOperand(1));
12018 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12019 DAG.getValueType(VT));
12020 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12023 if (VT.getSizeInBits() == 16) {
12024 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12025 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12027 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12028 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12029 DAG.getNode(ISD::BITCAST, dl,
12032 Op.getOperand(1)));
12033 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12034 Op.getOperand(0), Op.getOperand(1));
12035 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12036 DAG.getValueType(VT));
12037 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12040 if (VT == MVT::f32) {
12041 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12042 // the result back to FR32 register. It's only worth matching if the
12043 // result has a single use which is a store or a bitcast to i32. And in
12044 // the case of a store, it's not worth it if the index is a constant 0,
12045 // because a MOVSSmr can be used instead, which is smaller and faster.
12046 if (!Op.hasOneUse())
12048 SDNode *User = *Op.getNode()->use_begin();
12049 if ((User->getOpcode() != ISD::STORE ||
12050 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12051 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12052 (User->getOpcode() != ISD::BITCAST ||
12053 User->getValueType(0) != MVT::i32))
12055 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12056 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12059 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12062 if (VT == MVT::i32 || VT == MVT::i64) {
12063 // ExtractPS/pextrq works with constant index.
12064 if (isa<ConstantSDNode>(Op.getOperand(1)))
12070 /// Extract one bit from mask vector, like v16i1 or v8i1.
12071 /// AVX-512 feature.
12073 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12074 SDValue Vec = Op.getOperand(0);
12076 MVT VecVT = Vec.getSimpleValueType();
12077 SDValue Idx = Op.getOperand(1);
12078 MVT EltVT = Op.getSimpleValueType();
12080 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12082 // variable index can't be handled in mask registers,
12083 // extend vector to VR512
12084 if (!isa<ConstantSDNode>(Idx)) {
12085 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12086 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12087 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12088 ExtVT.getVectorElementType(), Ext, Idx);
12089 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12092 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12093 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12094 unsigned MaxSift = rc->getSize()*8 - 1;
12095 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12096 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12097 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12098 DAG.getConstant(MaxSift, MVT::i8));
12099 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12100 DAG.getIntPtrConstant(0));
12104 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12105 SelectionDAG &DAG) const {
12107 SDValue Vec = Op.getOperand(0);
12108 MVT VecVT = Vec.getSimpleValueType();
12109 SDValue Idx = Op.getOperand(1);
12111 if (Op.getSimpleValueType() == MVT::i1)
12112 return ExtractBitFromMaskVector(Op, DAG);
12114 if (!isa<ConstantSDNode>(Idx)) {
12115 if (VecVT.is512BitVector() ||
12116 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12117 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12120 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12121 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12122 MaskEltVT.getSizeInBits());
12124 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12125 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12126 getZeroVector(MaskVT, Subtarget, DAG, dl),
12127 Idx, DAG.getConstant(0, getPointerTy()));
12128 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12129 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12130 Perm, DAG.getConstant(0, getPointerTy()));
12135 // If this is a 256-bit vector result, first extract the 128-bit vector and
12136 // then extract the element from the 128-bit vector.
12137 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12139 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12140 // Get the 128-bit vector.
12141 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12142 MVT EltVT = VecVT.getVectorElementType();
12144 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12146 //if (IdxVal >= NumElems/2)
12147 // IdxVal -= NumElems/2;
12148 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12149 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12150 DAG.getConstant(IdxVal, MVT::i32));
12153 assert(VecVT.is128BitVector() && "Unexpected vector length");
12155 if (Subtarget->hasSSE41()) {
12156 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12161 MVT VT = Op.getSimpleValueType();
12162 // TODO: handle v16i8.
12163 if (VT.getSizeInBits() == 16) {
12164 SDValue Vec = Op.getOperand(0);
12165 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12167 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12168 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12169 DAG.getNode(ISD::BITCAST, dl,
12171 Op.getOperand(1)));
12172 // Transform it so it match pextrw which produces a 32-bit result.
12173 MVT EltVT = MVT::i32;
12174 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12175 Op.getOperand(0), Op.getOperand(1));
12176 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12177 DAG.getValueType(VT));
12178 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12181 if (VT.getSizeInBits() == 32) {
12182 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12186 // SHUFPS the element to the lowest double word, then movss.
12187 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12188 MVT VVT = Op.getOperand(0).getSimpleValueType();
12189 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12190 DAG.getUNDEF(VVT), Mask);
12191 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12192 DAG.getIntPtrConstant(0));
12195 if (VT.getSizeInBits() == 64) {
12196 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12197 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12198 // to match extract_elt for f64.
12199 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12203 // UNPCKHPD the element to the lowest double word, then movsd.
12204 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12205 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12206 int Mask[2] = { 1, -1 };
12207 MVT VVT = Op.getOperand(0).getSimpleValueType();
12208 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12209 DAG.getUNDEF(VVT), Mask);
12210 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12211 DAG.getIntPtrConstant(0));
12217 /// Insert one bit to mask vector, like v16i1 or v8i1.
12218 /// AVX-512 feature.
12220 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12222 SDValue Vec = Op.getOperand(0);
12223 SDValue Elt = Op.getOperand(1);
12224 SDValue Idx = Op.getOperand(2);
12225 MVT VecVT = Vec.getSimpleValueType();
12227 if (!isa<ConstantSDNode>(Idx)) {
12228 // Non constant index. Extend source and destination,
12229 // insert element and then truncate the result.
12230 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12231 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12232 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12233 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12234 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12235 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12238 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12239 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12240 if (Vec.getOpcode() == ISD::UNDEF)
12241 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12242 DAG.getConstant(IdxVal, MVT::i8));
12243 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12244 unsigned MaxSift = rc->getSize()*8 - 1;
12245 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12246 DAG.getConstant(MaxSift, MVT::i8));
12247 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12248 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12249 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12252 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12253 SelectionDAG &DAG) const {
12254 MVT VT = Op.getSimpleValueType();
12255 MVT EltVT = VT.getVectorElementType();
12257 if (EltVT == MVT::i1)
12258 return InsertBitToMaskVector(Op, DAG);
12261 SDValue N0 = Op.getOperand(0);
12262 SDValue N1 = Op.getOperand(1);
12263 SDValue N2 = Op.getOperand(2);
12264 if (!isa<ConstantSDNode>(N2))
12266 auto *N2C = cast<ConstantSDNode>(N2);
12267 unsigned IdxVal = N2C->getZExtValue();
12269 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12270 // into that, and then insert the subvector back into the result.
12271 if (VT.is256BitVector() || VT.is512BitVector()) {
12272 // Get the desired 128-bit vector half.
12273 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12275 // Insert the element into the desired half.
12276 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12277 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12279 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12280 DAG.getConstant(IdxIn128, MVT::i32));
12282 // Insert the changed part back to the 256-bit vector
12283 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12285 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12287 if (Subtarget->hasSSE41()) {
12288 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12290 if (VT == MVT::v8i16) {
12291 Opc = X86ISD::PINSRW;
12293 assert(VT == MVT::v16i8);
12294 Opc = X86ISD::PINSRB;
12297 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12299 if (N1.getValueType() != MVT::i32)
12300 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12301 if (N2.getValueType() != MVT::i32)
12302 N2 = DAG.getIntPtrConstant(IdxVal);
12303 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12306 if (EltVT == MVT::f32) {
12307 // Bits [7:6] of the constant are the source select. This will always be
12308 // zero here. The DAG Combiner may combine an extract_elt index into
12310 // bits. For example (insert (extract, 3), 2) could be matched by
12312 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12313 // Bits [5:4] of the constant are the destination select. This is the
12314 // value of the incoming immediate.
12315 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12316 // combine either bitwise AND or insert of float 0.0 to set these bits.
12317 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12318 // Create this as a scalar to vector..
12319 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12320 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12323 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12324 // PINSR* works with constant index.
12329 if (EltVT == MVT::i8)
12332 if (EltVT.getSizeInBits() == 16) {
12333 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12334 // as its second argument.
12335 if (N1.getValueType() != MVT::i32)
12336 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12337 if (N2.getValueType() != MVT::i32)
12338 N2 = DAG.getIntPtrConstant(IdxVal);
12339 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12344 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12346 MVT OpVT = Op.getSimpleValueType();
12348 // If this is a 256-bit vector result, first insert into a 128-bit
12349 // vector and then insert into the 256-bit vector.
12350 if (!OpVT.is128BitVector()) {
12351 // Insert into a 128-bit vector.
12352 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12353 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12354 OpVT.getVectorNumElements() / SizeFactor);
12356 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12358 // Insert the 128-bit vector.
12359 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12362 if (OpVT == MVT::v1i64 &&
12363 Op.getOperand(0).getValueType() == MVT::i64)
12364 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12366 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12367 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12368 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12369 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12372 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12373 // a simple subregister reference or explicit instructions to grab
12374 // upper bits of a vector.
12375 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12376 SelectionDAG &DAG) {
12378 SDValue In = Op.getOperand(0);
12379 SDValue Idx = Op.getOperand(1);
12380 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12381 MVT ResVT = Op.getSimpleValueType();
12382 MVT InVT = In.getSimpleValueType();
12384 if (Subtarget->hasFp256()) {
12385 if (ResVT.is128BitVector() &&
12386 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12387 isa<ConstantSDNode>(Idx)) {
12388 return Extract128BitVector(In, IdxVal, DAG, dl);
12390 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12391 isa<ConstantSDNode>(Idx)) {
12392 return Extract256BitVector(In, IdxVal, DAG, dl);
12398 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12399 // simple superregister reference or explicit instructions to insert
12400 // the upper bits of a vector.
12401 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12402 SelectionDAG &DAG) {
12403 if (Subtarget->hasFp256()) {
12404 SDLoc dl(Op.getNode());
12405 SDValue Vec = Op.getNode()->getOperand(0);
12406 SDValue SubVec = Op.getNode()->getOperand(1);
12407 SDValue Idx = Op.getNode()->getOperand(2);
12409 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12410 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12411 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12412 isa<ConstantSDNode>(Idx)) {
12413 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12414 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12417 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12418 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12419 isa<ConstantSDNode>(Idx)) {
12420 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12421 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12427 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12428 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12429 // one of the above mentioned nodes. It has to be wrapped because otherwise
12430 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12431 // be used to form addressing mode. These wrapped nodes will be selected
12434 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12435 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12437 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12438 // global base reg.
12439 unsigned char OpFlag = 0;
12440 unsigned WrapperKind = X86ISD::Wrapper;
12441 CodeModel::Model M = DAG.getTarget().getCodeModel();
12443 if (Subtarget->isPICStyleRIPRel() &&
12444 (M == CodeModel::Small || M == CodeModel::Kernel))
12445 WrapperKind = X86ISD::WrapperRIP;
12446 else if (Subtarget->isPICStyleGOT())
12447 OpFlag = X86II::MO_GOTOFF;
12448 else if (Subtarget->isPICStyleStubPIC())
12449 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12451 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12452 CP->getAlignment(),
12453 CP->getOffset(), OpFlag);
12455 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12456 // With PIC, the address is actually $g + Offset.
12458 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12459 DAG.getNode(X86ISD::GlobalBaseReg,
12460 SDLoc(), getPointerTy()),
12467 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12468 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12470 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12471 // global base reg.
12472 unsigned char OpFlag = 0;
12473 unsigned WrapperKind = X86ISD::Wrapper;
12474 CodeModel::Model M = DAG.getTarget().getCodeModel();
12476 if (Subtarget->isPICStyleRIPRel() &&
12477 (M == CodeModel::Small || M == CodeModel::Kernel))
12478 WrapperKind = X86ISD::WrapperRIP;
12479 else if (Subtarget->isPICStyleGOT())
12480 OpFlag = X86II::MO_GOTOFF;
12481 else if (Subtarget->isPICStyleStubPIC())
12482 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12484 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12487 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12489 // With PIC, the address is actually $g + Offset.
12491 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12492 DAG.getNode(X86ISD::GlobalBaseReg,
12493 SDLoc(), getPointerTy()),
12500 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12501 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12503 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12504 // global base reg.
12505 unsigned char OpFlag = 0;
12506 unsigned WrapperKind = X86ISD::Wrapper;
12507 CodeModel::Model M = DAG.getTarget().getCodeModel();
12509 if (Subtarget->isPICStyleRIPRel() &&
12510 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12511 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12512 OpFlag = X86II::MO_GOTPCREL;
12513 WrapperKind = X86ISD::WrapperRIP;
12514 } else if (Subtarget->isPICStyleGOT()) {
12515 OpFlag = X86II::MO_GOT;
12516 } else if (Subtarget->isPICStyleStubPIC()) {
12517 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12518 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12519 OpFlag = X86II::MO_DARWIN_NONLAZY;
12522 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12525 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12527 // With PIC, the address is actually $g + Offset.
12528 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12529 !Subtarget->is64Bit()) {
12530 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12531 DAG.getNode(X86ISD::GlobalBaseReg,
12532 SDLoc(), getPointerTy()),
12536 // For symbols that require a load from a stub to get the address, emit the
12538 if (isGlobalStubReference(OpFlag))
12539 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12540 MachinePointerInfo::getGOT(), false, false, false, 0);
12546 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12547 // Create the TargetBlockAddressAddress node.
12548 unsigned char OpFlags =
12549 Subtarget->ClassifyBlockAddressReference();
12550 CodeModel::Model M = DAG.getTarget().getCodeModel();
12551 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12552 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12554 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12557 if (Subtarget->isPICStyleRIPRel() &&
12558 (M == CodeModel::Small || M == CodeModel::Kernel))
12559 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12561 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12563 // With PIC, the address is actually $g + Offset.
12564 if (isGlobalRelativeToPICBase(OpFlags)) {
12565 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12566 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12574 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12575 int64_t Offset, SelectionDAG &DAG) const {
12576 // Create the TargetGlobalAddress node, folding in the constant
12577 // offset if it is legal.
12578 unsigned char OpFlags =
12579 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12580 CodeModel::Model M = DAG.getTarget().getCodeModel();
12582 if (OpFlags == X86II::MO_NO_FLAG &&
12583 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12584 // A direct static reference to a global.
12585 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12588 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12591 if (Subtarget->isPICStyleRIPRel() &&
12592 (M == CodeModel::Small || M == CodeModel::Kernel))
12593 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12595 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12597 // With PIC, the address is actually $g + Offset.
12598 if (isGlobalRelativeToPICBase(OpFlags)) {
12599 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12600 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12604 // For globals that require a load from a stub to get the address, emit the
12606 if (isGlobalStubReference(OpFlags))
12607 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12608 MachinePointerInfo::getGOT(), false, false, false, 0);
12610 // If there was a non-zero offset that we didn't fold, create an explicit
12611 // addition for it.
12613 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12614 DAG.getConstant(Offset, getPointerTy()));
12620 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12621 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12622 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12623 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12627 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12628 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12629 unsigned char OperandFlags, bool LocalDynamic = false) {
12630 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12631 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12633 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12634 GA->getValueType(0),
12638 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12642 SDValue Ops[] = { Chain, TGA, *InFlag };
12643 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12645 SDValue Ops[] = { Chain, TGA };
12646 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12649 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12650 MFI->setAdjustsStack(true);
12652 SDValue Flag = Chain.getValue(1);
12653 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12656 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12658 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12661 SDLoc dl(GA); // ? function entry point might be better
12662 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12663 DAG.getNode(X86ISD::GlobalBaseReg,
12664 SDLoc(), PtrVT), InFlag);
12665 InFlag = Chain.getValue(1);
12667 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12670 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12672 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12674 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12675 X86::RAX, X86II::MO_TLSGD);
12678 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12684 // Get the start address of the TLS block for this module.
12685 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12686 .getInfo<X86MachineFunctionInfo>();
12687 MFI->incNumLocalDynamicTLSAccesses();
12691 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12692 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12695 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12696 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12697 InFlag = Chain.getValue(1);
12698 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12699 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12702 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12706 unsigned char OperandFlags = X86II::MO_DTPOFF;
12707 unsigned WrapperKind = X86ISD::Wrapper;
12708 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12709 GA->getValueType(0),
12710 GA->getOffset(), OperandFlags);
12711 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12713 // Add x@dtpoff with the base.
12714 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12717 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12718 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12719 const EVT PtrVT, TLSModel::Model model,
12720 bool is64Bit, bool isPIC) {
12723 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12724 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12725 is64Bit ? 257 : 256));
12727 SDValue ThreadPointer =
12728 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12729 MachinePointerInfo(Ptr), false, false, false, 0);
12731 unsigned char OperandFlags = 0;
12732 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12734 unsigned WrapperKind = X86ISD::Wrapper;
12735 if (model == TLSModel::LocalExec) {
12736 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12737 } else if (model == TLSModel::InitialExec) {
12739 OperandFlags = X86II::MO_GOTTPOFF;
12740 WrapperKind = X86ISD::WrapperRIP;
12742 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12745 llvm_unreachable("Unexpected model");
12748 // emit "addl x@ntpoff,%eax" (local exec)
12749 // or "addl x@indntpoff,%eax" (initial exec)
12750 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12752 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12753 GA->getOffset(), OperandFlags);
12754 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12756 if (model == TLSModel::InitialExec) {
12757 if (isPIC && !is64Bit) {
12758 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12759 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12763 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12764 MachinePointerInfo::getGOT(), false, false, false, 0);
12767 // The address of the thread local variable is the add of the thread
12768 // pointer with the offset of the variable.
12769 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12773 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12775 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12776 const GlobalValue *GV = GA->getGlobal();
12778 if (Subtarget->isTargetELF()) {
12779 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12782 case TLSModel::GeneralDynamic:
12783 if (Subtarget->is64Bit())
12784 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12785 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12786 case TLSModel::LocalDynamic:
12787 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12788 Subtarget->is64Bit());
12789 case TLSModel::InitialExec:
12790 case TLSModel::LocalExec:
12791 return LowerToTLSExecModel(
12792 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12793 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12795 llvm_unreachable("Unknown TLS model.");
12798 if (Subtarget->isTargetDarwin()) {
12799 // Darwin only has one model of TLS. Lower to that.
12800 unsigned char OpFlag = 0;
12801 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12802 X86ISD::WrapperRIP : X86ISD::Wrapper;
12804 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12805 // global base reg.
12806 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12807 !Subtarget->is64Bit();
12809 OpFlag = X86II::MO_TLVP_PIC_BASE;
12811 OpFlag = X86II::MO_TLVP;
12813 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12814 GA->getValueType(0),
12815 GA->getOffset(), OpFlag);
12816 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12818 // With PIC32, the address is actually $g + Offset.
12820 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12821 DAG.getNode(X86ISD::GlobalBaseReg,
12822 SDLoc(), getPointerTy()),
12825 // Lowering the machine isd will make sure everything is in the right
12827 SDValue Chain = DAG.getEntryNode();
12828 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12829 SDValue Args[] = { Chain, Offset };
12830 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12832 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12833 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12834 MFI->setAdjustsStack(true);
12836 // And our return value (tls address) is in the standard call return value
12838 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12839 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12840 Chain.getValue(1));
12843 if (Subtarget->isTargetKnownWindowsMSVC() ||
12844 Subtarget->isTargetWindowsGNU()) {
12845 // Just use the implicit TLS architecture
12846 // Need to generate someting similar to:
12847 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12849 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12850 // mov rcx, qword [rdx+rcx*8]
12851 // mov eax, .tls$:tlsvar
12852 // [rax+rcx] contains the address
12853 // Windows 64bit: gs:0x58
12854 // Windows 32bit: fs:__tls_array
12857 SDValue Chain = DAG.getEntryNode();
12859 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12860 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12861 // use its literal value of 0x2C.
12862 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12863 ? Type::getInt8PtrTy(*DAG.getContext(),
12865 : Type::getInt32PtrTy(*DAG.getContext(),
12869 Subtarget->is64Bit()
12870 ? DAG.getIntPtrConstant(0x58)
12871 : (Subtarget->isTargetWindowsGNU()
12872 ? DAG.getIntPtrConstant(0x2C)
12873 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12875 SDValue ThreadPointer =
12876 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12877 MachinePointerInfo(Ptr), false, false, false, 0);
12879 // Load the _tls_index variable
12880 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12881 if (Subtarget->is64Bit())
12882 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12883 IDX, MachinePointerInfo(), MVT::i32,
12884 false, false, false, 0);
12886 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12887 false, false, false, 0);
12889 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12891 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12893 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12894 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12895 false, false, false, 0);
12897 // Get the offset of start of .tls section
12898 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12899 GA->getValueType(0),
12900 GA->getOffset(), X86II::MO_SECREL);
12901 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12903 // The address of the thread local variable is the add of the thread
12904 // pointer with the offset of the variable.
12905 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12908 llvm_unreachable("TLS not implemented for this target.");
12911 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12912 /// and take a 2 x i32 value to shift plus a shift amount.
12913 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12914 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12915 MVT VT = Op.getSimpleValueType();
12916 unsigned VTBits = VT.getSizeInBits();
12918 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12919 SDValue ShOpLo = Op.getOperand(0);
12920 SDValue ShOpHi = Op.getOperand(1);
12921 SDValue ShAmt = Op.getOperand(2);
12922 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12923 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12925 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12926 DAG.getConstant(VTBits - 1, MVT::i8));
12927 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12928 DAG.getConstant(VTBits - 1, MVT::i8))
12929 : DAG.getConstant(0, VT);
12931 SDValue Tmp2, Tmp3;
12932 if (Op.getOpcode() == ISD::SHL_PARTS) {
12933 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12934 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12936 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12937 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12940 // If the shift amount is larger or equal than the width of a part we can't
12941 // rely on the results of shld/shrd. Insert a test and select the appropriate
12942 // values for large shift amounts.
12943 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12944 DAG.getConstant(VTBits, MVT::i8));
12945 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12946 AndNode, DAG.getConstant(0, MVT::i8));
12949 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12950 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12951 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12953 if (Op.getOpcode() == ISD::SHL_PARTS) {
12954 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12955 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12957 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12958 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12961 SDValue Ops[2] = { Lo, Hi };
12962 return DAG.getMergeValues(Ops, dl);
12965 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12966 SelectionDAG &DAG) const {
12967 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12969 if (SrcVT.isVector())
12972 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12973 "Unknown SINT_TO_FP to lower!");
12975 // These are really Legal; return the operand so the caller accepts it as
12977 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12979 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12980 Subtarget->is64Bit()) {
12985 unsigned Size = SrcVT.getSizeInBits()/8;
12986 MachineFunction &MF = DAG.getMachineFunction();
12987 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12988 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12989 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12991 MachinePointerInfo::getFixedStack(SSFI),
12993 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12996 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12998 SelectionDAG &DAG) const {
13002 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13004 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13006 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13008 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13010 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13011 MachineMemOperand *MMO;
13013 int SSFI = FI->getIndex();
13015 DAG.getMachineFunction()
13016 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13017 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13019 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13020 StackSlot = StackSlot.getOperand(1);
13022 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13023 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13025 Tys, Ops, SrcVT, MMO);
13028 Chain = Result.getValue(1);
13029 SDValue InFlag = Result.getValue(2);
13031 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13032 // shouldn't be necessary except that RFP cannot be live across
13033 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13034 MachineFunction &MF = DAG.getMachineFunction();
13035 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13036 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13037 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13038 Tys = DAG.getVTList(MVT::Other);
13040 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13042 MachineMemOperand *MMO =
13043 DAG.getMachineFunction()
13044 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13045 MachineMemOperand::MOStore, SSFISize, SSFISize);
13047 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13048 Ops, Op.getValueType(), MMO);
13049 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13050 MachinePointerInfo::getFixedStack(SSFI),
13051 false, false, false, 0);
13057 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13058 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13059 SelectionDAG &DAG) const {
13060 // This algorithm is not obvious. Here it is what we're trying to output:
13063 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13064 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13066 haddpd %xmm0, %xmm0
13068 pshufd $0x4e, %xmm0, %xmm1
13074 LLVMContext *Context = DAG.getContext();
13076 // Build some magic constants.
13077 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13078 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13079 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13081 SmallVector<Constant*,2> CV1;
13083 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13084 APInt(64, 0x4330000000000000ULL))));
13086 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13087 APInt(64, 0x4530000000000000ULL))));
13088 Constant *C1 = ConstantVector::get(CV1);
13089 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13091 // Load the 64-bit value into an XMM register.
13092 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13094 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13095 MachinePointerInfo::getConstantPool(),
13096 false, false, false, 16);
13097 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13098 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13101 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13102 MachinePointerInfo::getConstantPool(),
13103 false, false, false, 16);
13104 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13105 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13108 if (Subtarget->hasSSE3()) {
13109 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13110 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13112 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13113 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13115 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13116 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13120 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13121 DAG.getIntPtrConstant(0));
13124 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13125 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13126 SelectionDAG &DAG) const {
13128 // FP constant to bias correct the final result.
13129 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13132 // Load the 32-bit value into an XMM register.
13133 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13136 // Zero out the upper parts of the register.
13137 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13139 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13140 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13141 DAG.getIntPtrConstant(0));
13143 // Or the load with the bias.
13144 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13145 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13146 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13147 MVT::v2f64, Load)),
13148 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13149 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13150 MVT::v2f64, Bias)));
13151 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13152 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13153 DAG.getIntPtrConstant(0));
13155 // Subtract the bias.
13156 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13158 // Handle final rounding.
13159 EVT DestVT = Op.getValueType();
13161 if (DestVT.bitsLT(MVT::f64))
13162 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13163 DAG.getIntPtrConstant(0));
13164 if (DestVT.bitsGT(MVT::f64))
13165 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13167 // Handle final rounding.
13171 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13172 SelectionDAG &DAG) const {
13173 SDValue N0 = Op.getOperand(0);
13174 MVT SVT = N0.getSimpleValueType();
13177 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13178 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13179 "Custom UINT_TO_FP is not supported!");
13181 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13182 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13183 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13186 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13187 SelectionDAG &DAG) const {
13188 SDValue N0 = Op.getOperand(0);
13191 if (Op.getValueType().isVector())
13192 return lowerUINT_TO_FP_vec(Op, DAG);
13194 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13195 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13196 // the optimization here.
13197 if (DAG.SignBitIsZero(N0))
13198 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13200 MVT SrcVT = N0.getSimpleValueType();
13201 MVT DstVT = Op.getSimpleValueType();
13202 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13203 return LowerUINT_TO_FP_i64(Op, DAG);
13204 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13205 return LowerUINT_TO_FP_i32(Op, DAG);
13206 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13209 // Make a 64-bit buffer, and use it to build an FILD.
13210 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13211 if (SrcVT == MVT::i32) {
13212 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13213 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13214 getPointerTy(), StackSlot, WordOff);
13215 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13216 StackSlot, MachinePointerInfo(),
13218 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13219 OffsetSlot, MachinePointerInfo(),
13221 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13225 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13226 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13227 StackSlot, MachinePointerInfo(),
13229 // For i64 source, we need to add the appropriate power of 2 if the input
13230 // was negative. This is the same as the optimization in
13231 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13232 // we must be careful to do the computation in x87 extended precision, not
13233 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13234 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13235 MachineMemOperand *MMO =
13236 DAG.getMachineFunction()
13237 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13238 MachineMemOperand::MOLoad, 8, 8);
13240 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13241 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13242 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13245 APInt FF(32, 0x5F800000ULL);
13247 // Check whether the sign bit is set.
13248 SDValue SignSet = DAG.getSetCC(dl,
13249 getSetCCResultType(*DAG.getContext(), MVT::i64),
13250 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13253 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13254 SDValue FudgePtr = DAG.getConstantPool(
13255 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13258 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13259 SDValue Zero = DAG.getIntPtrConstant(0);
13260 SDValue Four = DAG.getIntPtrConstant(4);
13261 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13263 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13265 // Load the value out, extending it from f32 to f80.
13266 // FIXME: Avoid the extend by constructing the right constant pool?
13267 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13268 FudgePtr, MachinePointerInfo::getConstantPool(),
13269 MVT::f32, false, false, false, 4);
13270 // Extend everything to 80 bits to force it to be done on x87.
13271 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13272 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13275 std::pair<SDValue,SDValue>
13276 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13277 bool IsSigned, bool IsReplace) const {
13280 EVT DstTy = Op.getValueType();
13282 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13283 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13287 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13288 DstTy.getSimpleVT() >= MVT::i16 &&
13289 "Unknown FP_TO_INT to lower!");
13291 // These are really Legal.
13292 if (DstTy == MVT::i32 &&
13293 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13294 return std::make_pair(SDValue(), SDValue());
13295 if (Subtarget->is64Bit() &&
13296 DstTy == MVT::i64 &&
13297 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13298 return std::make_pair(SDValue(), SDValue());
13300 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13301 // stack slot, or into the FTOL runtime function.
13302 MachineFunction &MF = DAG.getMachineFunction();
13303 unsigned MemSize = DstTy.getSizeInBits()/8;
13304 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13305 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13308 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13309 Opc = X86ISD::WIN_FTOL;
13311 switch (DstTy.getSimpleVT().SimpleTy) {
13312 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13313 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13314 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13315 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13318 SDValue Chain = DAG.getEntryNode();
13319 SDValue Value = Op.getOperand(0);
13320 EVT TheVT = Op.getOperand(0).getValueType();
13321 // FIXME This causes a redundant load/store if the SSE-class value is already
13322 // in memory, such as if it is on the callstack.
13323 if (isScalarFPTypeInSSEReg(TheVT)) {
13324 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13325 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13326 MachinePointerInfo::getFixedStack(SSFI),
13328 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13330 Chain, StackSlot, DAG.getValueType(TheVT)
13333 MachineMemOperand *MMO =
13334 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13335 MachineMemOperand::MOLoad, MemSize, MemSize);
13336 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13337 Chain = Value.getValue(1);
13338 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13339 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13342 MachineMemOperand *MMO =
13343 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13344 MachineMemOperand::MOStore, MemSize, MemSize);
13346 if (Opc != X86ISD::WIN_FTOL) {
13347 // Build the FP_TO_INT*_IN_MEM
13348 SDValue Ops[] = { Chain, Value, StackSlot };
13349 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13351 return std::make_pair(FIST, StackSlot);
13353 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13354 DAG.getVTList(MVT::Other, MVT::Glue),
13356 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13357 MVT::i32, ftol.getValue(1));
13358 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13359 MVT::i32, eax.getValue(2));
13360 SDValue Ops[] = { eax, edx };
13361 SDValue pair = IsReplace
13362 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13363 : DAG.getMergeValues(Ops, DL);
13364 return std::make_pair(pair, SDValue());
13368 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13369 const X86Subtarget *Subtarget) {
13370 MVT VT = Op->getSimpleValueType(0);
13371 SDValue In = Op->getOperand(0);
13372 MVT InVT = In.getSimpleValueType();
13375 // Optimize vectors in AVX mode:
13378 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13379 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13380 // Concat upper and lower parts.
13383 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13384 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13385 // Concat upper and lower parts.
13388 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13389 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13390 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13393 if (Subtarget->hasInt256())
13394 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13396 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13397 SDValue Undef = DAG.getUNDEF(InVT);
13398 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13399 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13400 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13402 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13403 VT.getVectorNumElements()/2);
13405 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13406 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13408 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13411 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13412 SelectionDAG &DAG) {
13413 MVT VT = Op->getSimpleValueType(0);
13414 SDValue In = Op->getOperand(0);
13415 MVT InVT = In.getSimpleValueType();
13417 unsigned int NumElts = VT.getVectorNumElements();
13418 if (NumElts != 8 && NumElts != 16)
13421 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13422 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13424 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13426 // Now we have only mask extension
13427 assert(InVT.getVectorElementType() == MVT::i1);
13428 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13429 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13430 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13431 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13432 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13433 MachinePointerInfo::getConstantPool(),
13434 false, false, false, Alignment);
13436 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13437 if (VT.is512BitVector())
13439 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13442 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13443 SelectionDAG &DAG) {
13444 if (Subtarget->hasFp256()) {
13445 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13453 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13454 SelectionDAG &DAG) {
13456 MVT VT = Op.getSimpleValueType();
13457 SDValue In = Op.getOperand(0);
13458 MVT SVT = In.getSimpleValueType();
13460 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13461 return LowerZERO_EXTEND_AVX512(Op, DAG);
13463 if (Subtarget->hasFp256()) {
13464 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13469 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13470 VT.getVectorNumElements() != SVT.getVectorNumElements());
13474 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13476 MVT VT = Op.getSimpleValueType();
13477 SDValue In = Op.getOperand(0);
13478 MVT InVT = In.getSimpleValueType();
13480 if (VT == MVT::i1) {
13481 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13482 "Invalid scalar TRUNCATE operation");
13483 if (InVT.getSizeInBits() >= 32)
13485 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13486 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13488 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13489 "Invalid TRUNCATE operation");
13491 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13492 if (VT.getVectorElementType().getSizeInBits() >=8)
13493 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13495 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13496 unsigned NumElts = InVT.getVectorNumElements();
13497 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13498 if (InVT.getSizeInBits() < 512) {
13499 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13500 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13504 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13505 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13506 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13507 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13508 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13509 MachinePointerInfo::getConstantPool(),
13510 false, false, false, Alignment);
13511 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13512 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13513 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13516 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13517 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13518 if (Subtarget->hasInt256()) {
13519 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13520 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13521 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13523 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13524 DAG.getIntPtrConstant(0));
13527 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13528 DAG.getIntPtrConstant(0));
13529 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13530 DAG.getIntPtrConstant(2));
13531 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13532 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13533 static const int ShufMask[] = {0, 2, 4, 6};
13534 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13537 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13538 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13539 if (Subtarget->hasInt256()) {
13540 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13542 SmallVector<SDValue,32> pshufbMask;
13543 for (unsigned i = 0; i < 2; ++i) {
13544 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13545 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13546 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13547 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13548 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13549 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13550 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13551 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13552 for (unsigned j = 0; j < 8; ++j)
13553 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13555 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13556 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13557 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13559 static const int ShufMask[] = {0, 2, -1, -1};
13560 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13562 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13563 DAG.getIntPtrConstant(0));
13564 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13567 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13568 DAG.getIntPtrConstant(0));
13570 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13571 DAG.getIntPtrConstant(4));
13573 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13574 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13576 // The PSHUFB mask:
13577 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13578 -1, -1, -1, -1, -1, -1, -1, -1};
13580 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13581 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13582 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13584 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13585 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13587 // The MOVLHPS Mask:
13588 static const int ShufMask2[] = {0, 1, 4, 5};
13589 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13590 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13593 // Handle truncation of V256 to V128 using shuffles.
13594 if (!VT.is128BitVector() || !InVT.is256BitVector())
13597 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13599 unsigned NumElems = VT.getVectorNumElements();
13600 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13602 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13603 // Prepare truncation shuffle mask
13604 for (unsigned i = 0; i != NumElems; ++i)
13605 MaskVec[i] = i * 2;
13606 SDValue V = DAG.getVectorShuffle(NVT, DL,
13607 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13608 DAG.getUNDEF(NVT), &MaskVec[0]);
13609 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13610 DAG.getIntPtrConstant(0));
13613 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13614 SelectionDAG &DAG) const {
13615 assert(!Op.getSimpleValueType().isVector());
13617 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13618 /*IsSigned=*/ true, /*IsReplace=*/ false);
13619 SDValue FIST = Vals.first, StackSlot = Vals.second;
13620 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13621 if (!FIST.getNode()) return Op;
13623 if (StackSlot.getNode())
13624 // Load the result.
13625 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13626 FIST, StackSlot, MachinePointerInfo(),
13627 false, false, false, 0);
13629 // The node is the result.
13633 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13634 SelectionDAG &DAG) const {
13635 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13636 /*IsSigned=*/ false, /*IsReplace=*/ false);
13637 SDValue FIST = Vals.first, StackSlot = Vals.second;
13638 assert(FIST.getNode() && "Unexpected failure");
13640 if (StackSlot.getNode())
13641 // Load the result.
13642 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13643 FIST, StackSlot, MachinePointerInfo(),
13644 false, false, false, 0);
13646 // The node is the result.
13650 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13652 MVT VT = Op.getSimpleValueType();
13653 SDValue In = Op.getOperand(0);
13654 MVT SVT = In.getSimpleValueType();
13656 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13658 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13659 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13660 In, DAG.getUNDEF(SVT)));
13663 // The only differences between FABS and FNEG are the mask and the logic op.
13664 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13665 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13666 "Wrong opcode for lowering FABS or FNEG.");
13668 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13670 MVT VT = Op.getSimpleValueType();
13671 // Assume scalar op for initialization; update for vector if needed.
13672 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13673 // generate a 16-byte vector constant and logic op even for the scalar case.
13674 // Using a 16-byte mask allows folding the load of the mask with
13675 // the logic op, so it can save (~4 bytes) on code size.
13677 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13678 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13679 // decide if we should generate a 16-byte constant mask when we only need 4 or
13680 // 8 bytes for the scalar case.
13681 if (VT.isVector()) {
13682 EltVT = VT.getVectorElementType();
13683 NumElts = VT.getVectorNumElements();
13686 unsigned EltBits = EltVT.getSizeInBits();
13687 LLVMContext *Context = DAG.getContext();
13688 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13690 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13691 Constant *C = ConstantInt::get(*Context, MaskElt);
13692 C = ConstantVector::getSplat(NumElts, C);
13693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13694 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13695 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13696 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13697 MachinePointerInfo::getConstantPool(),
13698 false, false, false, Alignment);
13700 if (VT.isVector()) {
13701 // For a vector, cast operands to a vector type, perform the logic op,
13702 // and cast the result back to the original value type.
13703 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13704 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13705 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13706 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13707 return DAG.getNode(ISD::BITCAST, dl, VT,
13708 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13710 // If not vector, then scalar.
13711 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13712 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13715 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13717 LLVMContext *Context = DAG.getContext();
13718 SDValue Op0 = Op.getOperand(0);
13719 SDValue Op1 = Op.getOperand(1);
13721 MVT VT = Op.getSimpleValueType();
13722 MVT SrcVT = Op1.getSimpleValueType();
13724 // If second operand is smaller, extend it first.
13725 if (SrcVT.bitsLT(VT)) {
13726 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13729 // And if it is bigger, shrink it first.
13730 if (SrcVT.bitsGT(VT)) {
13731 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13735 // At this point the operands and the result should have the same
13736 // type, and that won't be f80 since that is not custom lowered.
13738 // First get the sign bit of second operand.
13739 SmallVector<Constant*,4> CV;
13740 if (SrcVT == MVT::f64) {
13741 const fltSemantics &Sem = APFloat::IEEEdouble;
13742 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13743 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13745 const fltSemantics &Sem = APFloat::IEEEsingle;
13746 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13747 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13748 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13749 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13751 Constant *C = ConstantVector::get(CV);
13752 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13753 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13754 MachinePointerInfo::getConstantPool(),
13755 false, false, false, 16);
13756 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13758 // Shift sign bit right or left if the two operands have different types.
13759 if (SrcVT.bitsGT(VT)) {
13760 // Op0 is MVT::f32, Op1 is MVT::f64.
13761 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13762 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13763 DAG.getConstant(32, MVT::i32));
13764 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13765 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13766 DAG.getIntPtrConstant(0));
13769 // Clear first operand sign bit.
13771 if (VT == MVT::f64) {
13772 const fltSemantics &Sem = APFloat::IEEEdouble;
13773 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13774 APInt(64, ~(1ULL << 63)))));
13775 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13777 const fltSemantics &Sem = APFloat::IEEEsingle;
13778 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13779 APInt(32, ~(1U << 31)))));
13780 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13781 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13782 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13784 C = ConstantVector::get(CV);
13785 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13786 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13787 MachinePointerInfo::getConstantPool(),
13788 false, false, false, 16);
13789 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13791 // Or the value with the sign bit.
13792 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13795 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13796 SDValue N0 = Op.getOperand(0);
13798 MVT VT = Op.getSimpleValueType();
13800 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13801 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13802 DAG.getConstant(1, VT));
13803 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13806 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13808 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13809 SelectionDAG &DAG) {
13810 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13812 if (!Subtarget->hasSSE41())
13815 if (!Op->hasOneUse())
13818 SDNode *N = Op.getNode();
13821 SmallVector<SDValue, 8> Opnds;
13822 DenseMap<SDValue, unsigned> VecInMap;
13823 SmallVector<SDValue, 8> VecIns;
13824 EVT VT = MVT::Other;
13826 // Recognize a special case where a vector is casted into wide integer to
13828 Opnds.push_back(N->getOperand(0));
13829 Opnds.push_back(N->getOperand(1));
13831 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13832 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13833 // BFS traverse all OR'd operands.
13834 if (I->getOpcode() == ISD::OR) {
13835 Opnds.push_back(I->getOperand(0));
13836 Opnds.push_back(I->getOperand(1));
13837 // Re-evaluate the number of nodes to be traversed.
13838 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13842 // Quit if a non-EXTRACT_VECTOR_ELT
13843 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13846 // Quit if without a constant index.
13847 SDValue Idx = I->getOperand(1);
13848 if (!isa<ConstantSDNode>(Idx))
13851 SDValue ExtractedFromVec = I->getOperand(0);
13852 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13853 if (M == VecInMap.end()) {
13854 VT = ExtractedFromVec.getValueType();
13855 // Quit if not 128/256-bit vector.
13856 if (!VT.is128BitVector() && !VT.is256BitVector())
13858 // Quit if not the same type.
13859 if (VecInMap.begin() != VecInMap.end() &&
13860 VT != VecInMap.begin()->first.getValueType())
13862 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13863 VecIns.push_back(ExtractedFromVec);
13865 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13868 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13869 "Not extracted from 128-/256-bit vector.");
13871 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13873 for (DenseMap<SDValue, unsigned>::const_iterator
13874 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13875 // Quit if not all elements are used.
13876 if (I->second != FullMask)
13880 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13882 // Cast all vectors into TestVT for PTEST.
13883 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13884 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13886 // If more than one full vectors are evaluated, OR them first before PTEST.
13887 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13888 // Each iteration will OR 2 nodes and append the result until there is only
13889 // 1 node left, i.e. the final OR'd value of all vectors.
13890 SDValue LHS = VecIns[Slot];
13891 SDValue RHS = VecIns[Slot + 1];
13892 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13895 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13896 VecIns.back(), VecIns.back());
13899 /// \brief return true if \c Op has a use that doesn't just read flags.
13900 static bool hasNonFlagsUse(SDValue Op) {
13901 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13903 SDNode *User = *UI;
13904 unsigned UOpNo = UI.getOperandNo();
13905 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13906 // Look pass truncate.
13907 UOpNo = User->use_begin().getOperandNo();
13908 User = *User->use_begin();
13911 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13912 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13918 /// Emit nodes that will be selected as "test Op0,Op0", or something
13920 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13921 SelectionDAG &DAG) const {
13922 if (Op.getValueType() == MVT::i1)
13923 // KORTEST instruction should be selected
13924 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13925 DAG.getConstant(0, Op.getValueType()));
13927 // CF and OF aren't always set the way we want. Determine which
13928 // of these we need.
13929 bool NeedCF = false;
13930 bool NeedOF = false;
13933 case X86::COND_A: case X86::COND_AE:
13934 case X86::COND_B: case X86::COND_BE:
13937 case X86::COND_G: case X86::COND_GE:
13938 case X86::COND_L: case X86::COND_LE:
13939 case X86::COND_O: case X86::COND_NO: {
13940 // Check if we really need to set the
13941 // Overflow flag. If NoSignedWrap is present
13942 // that is not actually needed.
13943 switch (Op->getOpcode()) {
13948 const BinaryWithFlagsSDNode *BinNode =
13949 cast<BinaryWithFlagsSDNode>(Op.getNode());
13950 if (BinNode->hasNoSignedWrap())
13960 // See if we can use the EFLAGS value from the operand instead of
13961 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13962 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13963 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13964 // Emit a CMP with 0, which is the TEST pattern.
13965 //if (Op.getValueType() == MVT::i1)
13966 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13967 // DAG.getConstant(0, MVT::i1));
13968 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13969 DAG.getConstant(0, Op.getValueType()));
13971 unsigned Opcode = 0;
13972 unsigned NumOperands = 0;
13974 // Truncate operations may prevent the merge of the SETCC instruction
13975 // and the arithmetic instruction before it. Attempt to truncate the operands
13976 // of the arithmetic instruction and use a reduced bit-width instruction.
13977 bool NeedTruncation = false;
13978 SDValue ArithOp = Op;
13979 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13980 SDValue Arith = Op->getOperand(0);
13981 // Both the trunc and the arithmetic op need to have one user each.
13982 if (Arith->hasOneUse())
13983 switch (Arith.getOpcode()) {
13990 NeedTruncation = true;
13996 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13997 // which may be the result of a CAST. We use the variable 'Op', which is the
13998 // non-casted variable when we check for possible users.
13999 switch (ArithOp.getOpcode()) {
14001 // Due to an isel shortcoming, be conservative if this add is likely to be
14002 // selected as part of a load-modify-store instruction. When the root node
14003 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14004 // uses of other nodes in the match, such as the ADD in this case. This
14005 // leads to the ADD being left around and reselected, with the result being
14006 // two adds in the output. Alas, even if none our users are stores, that
14007 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14008 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14009 // climbing the DAG back to the root, and it doesn't seem to be worth the
14011 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14012 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14013 if (UI->getOpcode() != ISD::CopyToReg &&
14014 UI->getOpcode() != ISD::SETCC &&
14015 UI->getOpcode() != ISD::STORE)
14018 if (ConstantSDNode *C =
14019 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14020 // An add of one will be selected as an INC.
14021 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14022 Opcode = X86ISD::INC;
14027 // An add of negative one (subtract of one) will be selected as a DEC.
14028 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14029 Opcode = X86ISD::DEC;
14035 // Otherwise use a regular EFLAGS-setting add.
14036 Opcode = X86ISD::ADD;
14041 // If we have a constant logical shift that's only used in a comparison
14042 // against zero turn it into an equivalent AND. This allows turning it into
14043 // a TEST instruction later.
14044 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14045 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14046 EVT VT = Op.getValueType();
14047 unsigned BitWidth = VT.getSizeInBits();
14048 unsigned ShAmt = Op->getConstantOperandVal(1);
14049 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14051 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14052 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14053 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14054 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14056 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14057 DAG.getConstant(Mask, VT));
14058 DAG.ReplaceAllUsesWith(Op, New);
14064 // If the primary and result isn't used, don't bother using X86ISD::AND,
14065 // because a TEST instruction will be better.
14066 if (!hasNonFlagsUse(Op))
14072 // Due to the ISEL shortcoming noted above, be conservative if this op is
14073 // likely to be selected as part of a load-modify-store instruction.
14074 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14075 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14076 if (UI->getOpcode() == ISD::STORE)
14079 // Otherwise use a regular EFLAGS-setting instruction.
14080 switch (ArithOp.getOpcode()) {
14081 default: llvm_unreachable("unexpected operator!");
14082 case ISD::SUB: Opcode = X86ISD::SUB; break;
14083 case ISD::XOR: Opcode = X86ISD::XOR; break;
14084 case ISD::AND: Opcode = X86ISD::AND; break;
14086 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14087 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14088 if (EFLAGS.getNode())
14091 Opcode = X86ISD::OR;
14105 return SDValue(Op.getNode(), 1);
14111 // If we found that truncation is beneficial, perform the truncation and
14113 if (NeedTruncation) {
14114 EVT VT = Op.getValueType();
14115 SDValue WideVal = Op->getOperand(0);
14116 EVT WideVT = WideVal.getValueType();
14117 unsigned ConvertedOp = 0;
14118 // Use a target machine opcode to prevent further DAGCombine
14119 // optimizations that may separate the arithmetic operations
14120 // from the setcc node.
14121 switch (WideVal.getOpcode()) {
14123 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14124 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14125 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14126 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14127 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14132 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14133 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14134 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14135 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14141 // Emit a CMP with 0, which is the TEST pattern.
14142 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14143 DAG.getConstant(0, Op.getValueType()));
14145 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14146 SmallVector<SDValue, 4> Ops;
14147 for (unsigned i = 0; i != NumOperands; ++i)
14148 Ops.push_back(Op.getOperand(i));
14150 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14151 DAG.ReplaceAllUsesWith(Op, New);
14152 return SDValue(New.getNode(), 1);
14155 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14157 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14158 SDLoc dl, SelectionDAG &DAG) const {
14159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14160 if (C->getAPIntValue() == 0)
14161 return EmitTest(Op0, X86CC, dl, DAG);
14163 if (Op0.getValueType() == MVT::i1)
14164 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14167 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14168 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14169 // Do the comparison at i32 if it's smaller, besides the Atom case.
14170 // This avoids subregister aliasing issues. Keep the smaller reference
14171 // if we're optimizing for size, however, as that'll allow better folding
14172 // of memory operations.
14173 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14174 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14175 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14176 !Subtarget->isAtom()) {
14177 unsigned ExtendOp =
14178 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14179 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14180 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14182 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14183 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14184 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14186 return SDValue(Sub.getNode(), 1);
14188 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14191 /// Convert a comparison if required by the subtarget.
14192 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14193 SelectionDAG &DAG) const {
14194 // If the subtarget does not support the FUCOMI instruction, floating-point
14195 // comparisons have to be converted.
14196 if (Subtarget->hasCMov() ||
14197 Cmp.getOpcode() != X86ISD::CMP ||
14198 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14199 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14202 // The instruction selector will select an FUCOM instruction instead of
14203 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14204 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14205 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14207 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14208 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14209 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14210 DAG.getConstant(8, MVT::i8));
14211 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14212 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14215 static bool isAllOnes(SDValue V) {
14216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14217 return C && C->isAllOnesValue();
14220 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14221 /// if it's possible.
14222 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14223 SDLoc dl, SelectionDAG &DAG) const {
14224 SDValue Op0 = And.getOperand(0);
14225 SDValue Op1 = And.getOperand(1);
14226 if (Op0.getOpcode() == ISD::TRUNCATE)
14227 Op0 = Op0.getOperand(0);
14228 if (Op1.getOpcode() == ISD::TRUNCATE)
14229 Op1 = Op1.getOperand(0);
14232 if (Op1.getOpcode() == ISD::SHL)
14233 std::swap(Op0, Op1);
14234 if (Op0.getOpcode() == ISD::SHL) {
14235 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14236 if (And00C->getZExtValue() == 1) {
14237 // If we looked past a truncate, check that it's only truncating away
14239 unsigned BitWidth = Op0.getValueSizeInBits();
14240 unsigned AndBitWidth = And.getValueSizeInBits();
14241 if (BitWidth > AndBitWidth) {
14243 DAG.computeKnownBits(Op0, Zeros, Ones);
14244 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14248 RHS = Op0.getOperand(1);
14250 } else if (Op1.getOpcode() == ISD::Constant) {
14251 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14252 uint64_t AndRHSVal = AndRHS->getZExtValue();
14253 SDValue AndLHS = Op0;
14255 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14256 LHS = AndLHS.getOperand(0);
14257 RHS = AndLHS.getOperand(1);
14260 // Use BT if the immediate can't be encoded in a TEST instruction.
14261 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14263 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14267 if (LHS.getNode()) {
14268 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14269 // instruction. Since the shift amount is in-range-or-undefined, we know
14270 // that doing a bittest on the i32 value is ok. We extend to i32 because
14271 // the encoding for the i16 version is larger than the i32 version.
14272 // Also promote i16 to i32 for performance / code size reason.
14273 if (LHS.getValueType() == MVT::i8 ||
14274 LHS.getValueType() == MVT::i16)
14275 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14277 // If the operand types disagree, extend the shift amount to match. Since
14278 // BT ignores high bits (like shifts) we can use anyextend.
14279 if (LHS.getValueType() != RHS.getValueType())
14280 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14282 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14283 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14284 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14285 DAG.getConstant(Cond, MVT::i8), BT);
14291 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14293 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14298 // SSE Condition code mapping:
14307 switch (SetCCOpcode) {
14308 default: llvm_unreachable("Unexpected SETCC condition");
14310 case ISD::SETEQ: SSECC = 0; break;
14312 case ISD::SETGT: Swap = true; // Fallthrough
14314 case ISD::SETOLT: SSECC = 1; break;
14316 case ISD::SETGE: Swap = true; // Fallthrough
14318 case ISD::SETOLE: SSECC = 2; break;
14319 case ISD::SETUO: SSECC = 3; break;
14321 case ISD::SETNE: SSECC = 4; break;
14322 case ISD::SETULE: Swap = true; // Fallthrough
14323 case ISD::SETUGE: SSECC = 5; break;
14324 case ISD::SETULT: Swap = true; // Fallthrough
14325 case ISD::SETUGT: SSECC = 6; break;
14326 case ISD::SETO: SSECC = 7; break;
14328 case ISD::SETONE: SSECC = 8; break;
14331 std::swap(Op0, Op1);
14336 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14337 // ones, and then concatenate the result back.
14338 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14339 MVT VT = Op.getSimpleValueType();
14341 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14342 "Unsupported value type for operation");
14344 unsigned NumElems = VT.getVectorNumElements();
14346 SDValue CC = Op.getOperand(2);
14348 // Extract the LHS vectors
14349 SDValue LHS = Op.getOperand(0);
14350 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14351 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14353 // Extract the RHS vectors
14354 SDValue RHS = Op.getOperand(1);
14355 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14356 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14358 // Issue the operation on the smaller types and concatenate the result back
14359 MVT EltVT = VT.getVectorElementType();
14360 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14361 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14362 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14363 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14366 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14367 const X86Subtarget *Subtarget) {
14368 SDValue Op0 = Op.getOperand(0);
14369 SDValue Op1 = Op.getOperand(1);
14370 SDValue CC = Op.getOperand(2);
14371 MVT VT = Op.getSimpleValueType();
14374 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14375 Op.getValueType().getScalarType() == MVT::i1 &&
14376 "Cannot set masked compare for this operation");
14378 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14380 bool Unsigned = false;
14383 switch (SetCCOpcode) {
14384 default: llvm_unreachable("Unexpected SETCC condition");
14385 case ISD::SETNE: SSECC = 4; break;
14386 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14387 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14388 case ISD::SETLT: Swap = true; //fall-through
14389 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14390 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14391 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14392 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14393 case ISD::SETULE: Unsigned = true; //fall-through
14394 case ISD::SETLE: SSECC = 2; break;
14398 std::swap(Op0, Op1);
14400 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14401 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14402 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14403 DAG.getConstant(SSECC, MVT::i8));
14406 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14407 /// operand \p Op1. If non-trivial (for example because it's not constant)
14408 /// return an empty value.
14409 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14411 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14415 MVT VT = Op1.getSimpleValueType();
14416 MVT EVT = VT.getVectorElementType();
14417 unsigned n = VT.getVectorNumElements();
14418 SmallVector<SDValue, 8> ULTOp1;
14420 for (unsigned i = 0; i < n; ++i) {
14421 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14422 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14425 // Avoid underflow.
14426 APInt Val = Elt->getAPIntValue();
14430 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14433 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14436 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14437 SelectionDAG &DAG) {
14438 SDValue Op0 = Op.getOperand(0);
14439 SDValue Op1 = Op.getOperand(1);
14440 SDValue CC = Op.getOperand(2);
14441 MVT VT = Op.getSimpleValueType();
14442 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14443 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14448 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14449 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14452 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14453 unsigned Opc = X86ISD::CMPP;
14454 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14455 assert(VT.getVectorNumElements() <= 16);
14456 Opc = X86ISD::CMPM;
14458 // In the two special cases we can't handle, emit two comparisons.
14461 unsigned CombineOpc;
14462 if (SetCCOpcode == ISD::SETUEQ) {
14463 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14465 assert(SetCCOpcode == ISD::SETONE);
14466 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14469 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14470 DAG.getConstant(CC0, MVT::i8));
14471 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14472 DAG.getConstant(CC1, MVT::i8));
14473 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14475 // Handle all other FP comparisons here.
14476 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14477 DAG.getConstant(SSECC, MVT::i8));
14480 // Break 256-bit integer vector compare into smaller ones.
14481 if (VT.is256BitVector() && !Subtarget->hasInt256())
14482 return Lower256IntVSETCC(Op, DAG);
14484 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14485 EVT OpVT = Op1.getValueType();
14486 if (Subtarget->hasAVX512()) {
14487 if (Op1.getValueType().is512BitVector() ||
14488 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14489 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14490 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14492 // In AVX-512 architecture setcc returns mask with i1 elements,
14493 // But there is no compare instruction for i8 and i16 elements in KNL.
14494 // We are not talking about 512-bit operands in this case, these
14495 // types are illegal.
14497 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14498 OpVT.getVectorElementType().getSizeInBits() >= 8))
14499 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14500 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14503 // We are handling one of the integer comparisons here. Since SSE only has
14504 // GT and EQ comparisons for integer, swapping operands and multiple
14505 // operations may be required for some comparisons.
14507 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14508 bool Subus = false;
14510 switch (SetCCOpcode) {
14511 default: llvm_unreachable("Unexpected SETCC condition");
14512 case ISD::SETNE: Invert = true;
14513 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14514 case ISD::SETLT: Swap = true;
14515 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14516 case ISD::SETGE: Swap = true;
14517 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14518 Invert = true; break;
14519 case ISD::SETULT: Swap = true;
14520 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14521 FlipSigns = true; break;
14522 case ISD::SETUGE: Swap = true;
14523 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14524 FlipSigns = true; Invert = true; break;
14527 // Special case: Use min/max operations for SETULE/SETUGE
14528 MVT VET = VT.getVectorElementType();
14530 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14531 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14534 switch (SetCCOpcode) {
14536 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14537 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14540 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14543 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14544 if (!MinMax && hasSubus) {
14545 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14547 // t = psubus Op0, Op1
14548 // pcmpeq t, <0..0>
14549 switch (SetCCOpcode) {
14551 case ISD::SETULT: {
14552 // If the comparison is against a constant we can turn this into a
14553 // setule. With psubus, setule does not require a swap. This is
14554 // beneficial because the constant in the register is no longer
14555 // destructed as the destination so it can be hoisted out of a loop.
14556 // Only do this pre-AVX since vpcmp* is no longer destructive.
14557 if (Subtarget->hasAVX())
14559 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14560 if (ULEOp1.getNode()) {
14562 Subus = true; Invert = false; Swap = false;
14566 // Psubus is better than flip-sign because it requires no inversion.
14567 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14568 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14572 Opc = X86ISD::SUBUS;
14578 std::swap(Op0, Op1);
14580 // Check that the operation in question is available (most are plain SSE2,
14581 // but PCMPGTQ and PCMPEQQ have different requirements).
14582 if (VT == MVT::v2i64) {
14583 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14584 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14586 // First cast everything to the right type.
14587 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14588 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14590 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14591 // bits of the inputs before performing those operations. The lower
14592 // compare is always unsigned.
14595 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14597 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14598 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14599 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14600 Sign, Zero, Sign, Zero);
14602 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14603 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14605 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14606 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14607 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14609 // Create masks for only the low parts/high parts of the 64 bit integers.
14610 static const int MaskHi[] = { 1, 1, 3, 3 };
14611 static const int MaskLo[] = { 0, 0, 2, 2 };
14612 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14613 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14614 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14616 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14617 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14620 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14622 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14625 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14626 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14627 // pcmpeqd + pshufd + pand.
14628 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14630 // First cast everything to the right type.
14631 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14632 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14635 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14637 // Make sure the lower and upper halves are both all-ones.
14638 static const int Mask[] = { 1, 0, 3, 2 };
14639 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14640 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14643 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14645 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14649 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14650 // bits of the inputs before performing those operations.
14652 EVT EltVT = VT.getVectorElementType();
14653 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14654 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14655 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14658 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14660 // If the logical-not of the result is required, perform that now.
14662 Result = DAG.getNOT(dl, Result, VT);
14665 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14668 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14669 getZeroVector(VT, Subtarget, DAG, dl));
14674 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14676 MVT VT = Op.getSimpleValueType();
14678 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14680 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14681 && "SetCC type must be 8-bit or 1-bit integer");
14682 SDValue Op0 = Op.getOperand(0);
14683 SDValue Op1 = Op.getOperand(1);
14685 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14687 // Optimize to BT if possible.
14688 // Lower (X & (1 << N)) == 0 to BT(X, N).
14689 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14690 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14691 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14692 Op1.getOpcode() == ISD::Constant &&
14693 cast<ConstantSDNode>(Op1)->isNullValue() &&
14694 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14695 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14696 if (NewSetCC.getNode())
14700 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14702 if (Op1.getOpcode() == ISD::Constant &&
14703 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14704 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14705 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14707 // If the input is a setcc, then reuse the input setcc or use a new one with
14708 // the inverted condition.
14709 if (Op0.getOpcode() == X86ISD::SETCC) {
14710 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14711 bool Invert = (CC == ISD::SETNE) ^
14712 cast<ConstantSDNode>(Op1)->isNullValue();
14716 CCode = X86::GetOppositeBranchCondition(CCode);
14717 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14718 DAG.getConstant(CCode, MVT::i8),
14719 Op0.getOperand(1));
14721 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14725 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14726 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14727 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14729 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14730 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14733 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14734 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14735 if (X86CC == X86::COND_INVALID)
14738 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14739 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14740 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14741 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14743 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14747 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14748 static bool isX86LogicalCmp(SDValue Op) {
14749 unsigned Opc = Op.getNode()->getOpcode();
14750 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14751 Opc == X86ISD::SAHF)
14753 if (Op.getResNo() == 1 &&
14754 (Opc == X86ISD::ADD ||
14755 Opc == X86ISD::SUB ||
14756 Opc == X86ISD::ADC ||
14757 Opc == X86ISD::SBB ||
14758 Opc == X86ISD::SMUL ||
14759 Opc == X86ISD::UMUL ||
14760 Opc == X86ISD::INC ||
14761 Opc == X86ISD::DEC ||
14762 Opc == X86ISD::OR ||
14763 Opc == X86ISD::XOR ||
14764 Opc == X86ISD::AND))
14767 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14773 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14774 if (V.getOpcode() != ISD::TRUNCATE)
14777 SDValue VOp0 = V.getOperand(0);
14778 unsigned InBits = VOp0.getValueSizeInBits();
14779 unsigned Bits = V.getValueSizeInBits();
14780 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14783 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14784 bool addTest = true;
14785 SDValue Cond = Op.getOperand(0);
14786 SDValue Op1 = Op.getOperand(1);
14787 SDValue Op2 = Op.getOperand(2);
14789 EVT VT = Op1.getValueType();
14792 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14793 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14794 // sequence later on.
14795 if (Cond.getOpcode() == ISD::SETCC &&
14796 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14797 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14798 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14799 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14800 int SSECC = translateX86FSETCC(
14801 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14804 if (Subtarget->hasAVX512()) {
14805 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14806 DAG.getConstant(SSECC, MVT::i8));
14807 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14809 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14810 DAG.getConstant(SSECC, MVT::i8));
14811 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14812 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14813 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14817 if (Cond.getOpcode() == ISD::SETCC) {
14818 SDValue NewCond = LowerSETCC(Cond, DAG);
14819 if (NewCond.getNode())
14823 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14824 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14825 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14826 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14827 if (Cond.getOpcode() == X86ISD::SETCC &&
14828 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14829 isZero(Cond.getOperand(1).getOperand(1))) {
14830 SDValue Cmp = Cond.getOperand(1);
14832 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14834 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14835 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14836 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14838 SDValue CmpOp0 = Cmp.getOperand(0);
14839 // Apply further optimizations for special cases
14840 // (select (x != 0), -1, 0) -> neg & sbb
14841 // (select (x == 0), 0, -1) -> neg & sbb
14842 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14843 if (YC->isNullValue() &&
14844 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14845 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14846 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14847 DAG.getConstant(0, CmpOp0.getValueType()),
14849 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14850 DAG.getConstant(X86::COND_B, MVT::i8),
14851 SDValue(Neg.getNode(), 1));
14855 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14856 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14857 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14859 SDValue Res = // Res = 0 or -1.
14860 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14861 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14863 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14864 Res = DAG.getNOT(DL, Res, Res.getValueType());
14866 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14867 if (!N2C || !N2C->isNullValue())
14868 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14873 // Look past (and (setcc_carry (cmp ...)), 1).
14874 if (Cond.getOpcode() == ISD::AND &&
14875 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14876 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14877 if (C && C->getAPIntValue() == 1)
14878 Cond = Cond.getOperand(0);
14881 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14882 // setting operand in place of the X86ISD::SETCC.
14883 unsigned CondOpcode = Cond.getOpcode();
14884 if (CondOpcode == X86ISD::SETCC ||
14885 CondOpcode == X86ISD::SETCC_CARRY) {
14886 CC = Cond.getOperand(0);
14888 SDValue Cmp = Cond.getOperand(1);
14889 unsigned Opc = Cmp.getOpcode();
14890 MVT VT = Op.getSimpleValueType();
14892 bool IllegalFPCMov = false;
14893 if (VT.isFloatingPoint() && !VT.isVector() &&
14894 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14895 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14897 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14898 Opc == X86ISD::BT) { // FIXME
14902 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14903 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14904 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14905 Cond.getOperand(0).getValueType() != MVT::i8)) {
14906 SDValue LHS = Cond.getOperand(0);
14907 SDValue RHS = Cond.getOperand(1);
14908 unsigned X86Opcode;
14911 switch (CondOpcode) {
14912 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14913 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14914 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14915 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14916 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14917 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14918 default: llvm_unreachable("unexpected overflowing operator");
14920 if (CondOpcode == ISD::UMULO)
14921 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14924 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14926 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14928 if (CondOpcode == ISD::UMULO)
14929 Cond = X86Op.getValue(2);
14931 Cond = X86Op.getValue(1);
14933 CC = DAG.getConstant(X86Cond, MVT::i8);
14938 // Look pass the truncate if the high bits are known zero.
14939 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14940 Cond = Cond.getOperand(0);
14942 // We know the result of AND is compared against zero. Try to match
14944 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14945 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14946 if (NewSetCC.getNode()) {
14947 CC = NewSetCC.getOperand(0);
14948 Cond = NewSetCC.getOperand(1);
14955 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14956 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14959 // a < b ? -1 : 0 -> RES = ~setcc_carry
14960 // a < b ? 0 : -1 -> RES = setcc_carry
14961 // a >= b ? -1 : 0 -> RES = setcc_carry
14962 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14963 if (Cond.getOpcode() == X86ISD::SUB) {
14964 Cond = ConvertCmpIfNecessary(Cond, DAG);
14965 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14967 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14968 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14969 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14970 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14971 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14972 return DAG.getNOT(DL, Res, Res.getValueType());
14977 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14978 // widen the cmov and push the truncate through. This avoids introducing a new
14979 // branch during isel and doesn't add any extensions.
14980 if (Op.getValueType() == MVT::i8 &&
14981 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14982 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14983 if (T1.getValueType() == T2.getValueType() &&
14984 // Blacklist CopyFromReg to avoid partial register stalls.
14985 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14986 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14987 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14988 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14992 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14993 // condition is true.
14994 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14995 SDValue Ops[] = { Op2, Op1, CC, Cond };
14996 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14999 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
15000 MVT VT = Op->getSimpleValueType(0);
15001 SDValue In = Op->getOperand(0);
15002 MVT InVT = In.getSimpleValueType();
15005 unsigned int NumElts = VT.getVectorNumElements();
15006 if (NumElts != 8 && NumElts != 16)
15009 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15010 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15013 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15015 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15016 Constant *C = ConstantInt::get(*DAG.getContext(),
15017 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15019 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15020 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15021 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15022 MachinePointerInfo::getConstantPool(),
15023 false, false, false, Alignment);
15024 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15025 if (VT.is512BitVector())
15027 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15030 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15031 SelectionDAG &DAG) {
15032 MVT VT = Op->getSimpleValueType(0);
15033 SDValue In = Op->getOperand(0);
15034 MVT InVT = In.getSimpleValueType();
15037 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15038 return LowerSIGN_EXTEND_AVX512(Op, DAG);
15040 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15041 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15042 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15045 if (Subtarget->hasInt256())
15046 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15048 // Optimize vectors in AVX mode
15049 // Sign extend v8i16 to v8i32 and
15052 // Divide input vector into two parts
15053 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15054 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15055 // concat the vectors to original VT
15057 unsigned NumElems = InVT.getVectorNumElements();
15058 SDValue Undef = DAG.getUNDEF(InVT);
15060 SmallVector<int,8> ShufMask1(NumElems, -1);
15061 for (unsigned i = 0; i != NumElems/2; ++i)
15064 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15066 SmallVector<int,8> ShufMask2(NumElems, -1);
15067 for (unsigned i = 0; i != NumElems/2; ++i)
15068 ShufMask2[i] = i + NumElems/2;
15070 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15072 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15073 VT.getVectorNumElements()/2);
15075 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15076 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15078 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15081 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15082 // may emit an illegal shuffle but the expansion is still better than scalar
15083 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15084 // we'll emit a shuffle and a arithmetic shift.
15085 // TODO: It is possible to support ZExt by zeroing the undef values during
15086 // the shuffle phase or after the shuffle.
15087 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15088 SelectionDAG &DAG) {
15089 MVT RegVT = Op.getSimpleValueType();
15090 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15091 assert(RegVT.isInteger() &&
15092 "We only custom lower integer vector sext loads.");
15094 // Nothing useful we can do without SSE2 shuffles.
15095 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15097 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15099 EVT MemVT = Ld->getMemoryVT();
15100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15101 unsigned RegSz = RegVT.getSizeInBits();
15103 ISD::LoadExtType Ext = Ld->getExtensionType();
15105 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15106 && "Only anyext and sext are currently implemented.");
15107 assert(MemVT != RegVT && "Cannot extend to the same type");
15108 assert(MemVT.isVector() && "Must load a vector from memory");
15110 unsigned NumElems = RegVT.getVectorNumElements();
15111 unsigned MemSz = MemVT.getSizeInBits();
15112 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15114 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15115 // The only way in which we have a legal 256-bit vector result but not the
15116 // integer 256-bit operations needed to directly lower a sextload is if we
15117 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15118 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15119 // correctly legalized. We do this late to allow the canonical form of
15120 // sextload to persist throughout the rest of the DAG combiner -- it wants
15121 // to fold together any extensions it can, and so will fuse a sign_extend
15122 // of an sextload into a sextload targeting a wider value.
15124 if (MemSz == 128) {
15125 // Just switch this to a normal load.
15126 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15127 "it must be a legal 128-bit vector "
15129 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15130 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15131 Ld->isInvariant(), Ld->getAlignment());
15133 assert(MemSz < 128 &&
15134 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15135 // Do an sext load to a 128-bit vector type. We want to use the same
15136 // number of elements, but elements half as wide. This will end up being
15137 // recursively lowered by this routine, but will succeed as we definitely
15138 // have all the necessary features if we're using AVX1.
15140 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15141 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15143 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15144 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15145 Ld->isNonTemporal(), Ld->isInvariant(),
15146 Ld->getAlignment());
15149 // Replace chain users with the new chain.
15150 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15151 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15153 // Finally, do a normal sign-extend to the desired register.
15154 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15157 // All sizes must be a power of two.
15158 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15159 "Non-power-of-two elements are not custom lowered!");
15161 // Attempt to load the original value using scalar loads.
15162 // Find the largest scalar type that divides the total loaded size.
15163 MVT SclrLoadTy = MVT::i8;
15164 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15165 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15166 MVT Tp = (MVT::SimpleValueType)tp;
15167 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15172 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15173 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15175 SclrLoadTy = MVT::f64;
15177 // Calculate the number of scalar loads that we need to perform
15178 // in order to load our vector from memory.
15179 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15181 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15182 "Can only lower sext loads with a single scalar load!");
15184 unsigned loadRegZize = RegSz;
15185 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15188 // Represent our vector as a sequence of elements which are the
15189 // largest scalar that we can load.
15190 EVT LoadUnitVecVT = EVT::getVectorVT(
15191 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15193 // Represent the data using the same element type that is stored in
15194 // memory. In practice, we ''widen'' MemVT.
15196 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15197 loadRegZize / MemVT.getScalarType().getSizeInBits());
15199 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15200 "Invalid vector type");
15202 // We can't shuffle using an illegal type.
15203 assert(TLI.isTypeLegal(WideVecVT) &&
15204 "We only lower types that form legal widened vector types");
15206 SmallVector<SDValue, 8> Chains;
15207 SDValue Ptr = Ld->getBasePtr();
15208 SDValue Increment =
15209 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15210 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15212 for (unsigned i = 0; i < NumLoads; ++i) {
15213 // Perform a single load.
15214 SDValue ScalarLoad =
15215 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15216 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15217 Ld->getAlignment());
15218 Chains.push_back(ScalarLoad.getValue(1));
15219 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15220 // another round of DAGCombining.
15222 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15224 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15225 ScalarLoad, DAG.getIntPtrConstant(i));
15227 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15230 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15232 // Bitcast the loaded value to a vector of the original element type, in
15233 // the size of the target vector type.
15234 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15235 unsigned SizeRatio = RegSz / MemSz;
15237 if (Ext == ISD::SEXTLOAD) {
15238 // If we have SSE4.1, we can directly emit a VSEXT node.
15239 if (Subtarget->hasSSE41()) {
15240 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15241 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15245 // Otherwise we'll shuffle the small elements in the high bits of the
15246 // larger type and perform an arithmetic shift. If the shift is not legal
15247 // it's better to scalarize.
15248 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15249 "We can't implement a sext load without an arithmetic right shift!");
15251 // Redistribute the loaded elements into the different locations.
15252 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15253 for (unsigned i = 0; i != NumElems; ++i)
15254 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15256 SDValue Shuff = DAG.getVectorShuffle(
15257 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15259 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15261 // Build the arithmetic shift.
15262 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15263 MemVT.getVectorElementType().getSizeInBits();
15265 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15267 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15271 // Redistribute the loaded elements into the different locations.
15272 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15273 for (unsigned i = 0; i != NumElems; ++i)
15274 ShuffleVec[i * SizeRatio] = i;
15276 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15277 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15279 // Bitcast to the requested type.
15280 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15281 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15285 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15286 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15287 // from the AND / OR.
15288 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15289 Opc = Op.getOpcode();
15290 if (Opc != ISD::OR && Opc != ISD::AND)
15292 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15293 Op.getOperand(0).hasOneUse() &&
15294 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15295 Op.getOperand(1).hasOneUse());
15298 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15299 // 1 and that the SETCC node has a single use.
15300 static bool isXor1OfSetCC(SDValue Op) {
15301 if (Op.getOpcode() != ISD::XOR)
15303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15304 if (N1C && N1C->getAPIntValue() == 1) {
15305 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15306 Op.getOperand(0).hasOneUse();
15311 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15312 bool addTest = true;
15313 SDValue Chain = Op.getOperand(0);
15314 SDValue Cond = Op.getOperand(1);
15315 SDValue Dest = Op.getOperand(2);
15318 bool Inverted = false;
15320 if (Cond.getOpcode() == ISD::SETCC) {
15321 // Check for setcc([su]{add,sub,mul}o == 0).
15322 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15323 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15324 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15325 Cond.getOperand(0).getResNo() == 1 &&
15326 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15327 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15328 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15329 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15330 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15331 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15333 Cond = Cond.getOperand(0);
15335 SDValue NewCond = LowerSETCC(Cond, DAG);
15336 if (NewCond.getNode())
15341 // FIXME: LowerXALUO doesn't handle these!!
15342 else if (Cond.getOpcode() == X86ISD::ADD ||
15343 Cond.getOpcode() == X86ISD::SUB ||
15344 Cond.getOpcode() == X86ISD::SMUL ||
15345 Cond.getOpcode() == X86ISD::UMUL)
15346 Cond = LowerXALUO(Cond, DAG);
15349 // Look pass (and (setcc_carry (cmp ...)), 1).
15350 if (Cond.getOpcode() == ISD::AND &&
15351 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15352 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15353 if (C && C->getAPIntValue() == 1)
15354 Cond = Cond.getOperand(0);
15357 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15358 // setting operand in place of the X86ISD::SETCC.
15359 unsigned CondOpcode = Cond.getOpcode();
15360 if (CondOpcode == X86ISD::SETCC ||
15361 CondOpcode == X86ISD::SETCC_CARRY) {
15362 CC = Cond.getOperand(0);
15364 SDValue Cmp = Cond.getOperand(1);
15365 unsigned Opc = Cmp.getOpcode();
15366 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15367 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15371 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15375 // These can only come from an arithmetic instruction with overflow,
15376 // e.g. SADDO, UADDO.
15377 Cond = Cond.getNode()->getOperand(1);
15383 CondOpcode = Cond.getOpcode();
15384 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15385 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15386 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15387 Cond.getOperand(0).getValueType() != MVT::i8)) {
15388 SDValue LHS = Cond.getOperand(0);
15389 SDValue RHS = Cond.getOperand(1);
15390 unsigned X86Opcode;
15393 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15394 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15396 switch (CondOpcode) {
15397 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15399 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15401 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15404 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15405 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15409 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15412 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15413 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15414 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15415 default: llvm_unreachable("unexpected overflowing operator");
15418 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15419 if (CondOpcode == ISD::UMULO)
15420 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15423 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15425 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15427 if (CondOpcode == ISD::UMULO)
15428 Cond = X86Op.getValue(2);
15430 Cond = X86Op.getValue(1);
15432 CC = DAG.getConstant(X86Cond, MVT::i8);
15436 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15437 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15438 if (CondOpc == ISD::OR) {
15439 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15440 // two branches instead of an explicit OR instruction with a
15442 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15443 isX86LogicalCmp(Cmp)) {
15444 CC = Cond.getOperand(0).getOperand(0);
15445 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15446 Chain, Dest, CC, Cmp);
15447 CC = Cond.getOperand(1).getOperand(0);
15451 } else { // ISD::AND
15452 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15453 // two branches instead of an explicit AND instruction with a
15454 // separate test. However, we only do this if this block doesn't
15455 // have a fall-through edge, because this requires an explicit
15456 // jmp when the condition is false.
15457 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15458 isX86LogicalCmp(Cmp) &&
15459 Op.getNode()->hasOneUse()) {
15460 X86::CondCode CCode =
15461 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15462 CCode = X86::GetOppositeBranchCondition(CCode);
15463 CC = DAG.getConstant(CCode, MVT::i8);
15464 SDNode *User = *Op.getNode()->use_begin();
15465 // Look for an unconditional branch following this conditional branch.
15466 // We need this because we need to reverse the successors in order
15467 // to implement FCMP_OEQ.
15468 if (User->getOpcode() == ISD::BR) {
15469 SDValue FalseBB = User->getOperand(1);
15471 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15472 assert(NewBR == User);
15476 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15477 Chain, Dest, CC, Cmp);
15478 X86::CondCode CCode =
15479 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15480 CCode = X86::GetOppositeBranchCondition(CCode);
15481 CC = DAG.getConstant(CCode, MVT::i8);
15487 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15488 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15489 // It should be transformed during dag combiner except when the condition
15490 // is set by a arithmetics with overflow node.
15491 X86::CondCode CCode =
15492 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15493 CCode = X86::GetOppositeBranchCondition(CCode);
15494 CC = DAG.getConstant(CCode, MVT::i8);
15495 Cond = Cond.getOperand(0).getOperand(1);
15497 } else if (Cond.getOpcode() == ISD::SETCC &&
15498 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15499 // For FCMP_OEQ, we can emit
15500 // two branches instead of an explicit AND instruction with a
15501 // separate test. However, we only do this if this block doesn't
15502 // have a fall-through edge, because this requires an explicit
15503 // jmp when the condition is false.
15504 if (Op.getNode()->hasOneUse()) {
15505 SDNode *User = *Op.getNode()->use_begin();
15506 // Look for an unconditional branch following this conditional branch.
15507 // We need this because we need to reverse the successors in order
15508 // to implement FCMP_OEQ.
15509 if (User->getOpcode() == ISD::BR) {
15510 SDValue FalseBB = User->getOperand(1);
15512 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15513 assert(NewBR == User);
15517 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15518 Cond.getOperand(0), Cond.getOperand(1));
15519 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15520 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15521 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15522 Chain, Dest, CC, Cmp);
15523 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15528 } else if (Cond.getOpcode() == ISD::SETCC &&
15529 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15530 // For FCMP_UNE, we can emit
15531 // two branches instead of an explicit AND instruction with a
15532 // separate test. However, we only do this if this block doesn't
15533 // have a fall-through edge, because this requires an explicit
15534 // jmp when the condition is false.
15535 if (Op.getNode()->hasOneUse()) {
15536 SDNode *User = *Op.getNode()->use_begin();
15537 // Look for an unconditional branch following this conditional branch.
15538 // We need this because we need to reverse the successors in order
15539 // to implement FCMP_UNE.
15540 if (User->getOpcode() == ISD::BR) {
15541 SDValue FalseBB = User->getOperand(1);
15543 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15544 assert(NewBR == User);
15547 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15548 Cond.getOperand(0), Cond.getOperand(1));
15549 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15550 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15551 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15552 Chain, Dest, CC, Cmp);
15553 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15563 // Look pass the truncate if the high bits are known zero.
15564 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15565 Cond = Cond.getOperand(0);
15567 // We know the result of AND is compared against zero. Try to match
15569 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15570 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15571 if (NewSetCC.getNode()) {
15572 CC = NewSetCC.getOperand(0);
15573 Cond = NewSetCC.getOperand(1);
15580 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15581 CC = DAG.getConstant(X86Cond, MVT::i8);
15582 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15584 Cond = ConvertCmpIfNecessary(Cond, DAG);
15585 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15586 Chain, Dest, CC, Cond);
15589 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15590 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15591 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15592 // that the guard pages used by the OS virtual memory manager are allocated in
15593 // correct sequence.
15595 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15596 SelectionDAG &DAG) const {
15597 MachineFunction &MF = DAG.getMachineFunction();
15598 bool SplitStack = MF.shouldSplitStack();
15599 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15604 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15605 SDNode* Node = Op.getNode();
15607 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15608 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15609 " not tell us which reg is the stack pointer!");
15610 EVT VT = Node->getValueType(0);
15611 SDValue Tmp1 = SDValue(Node, 0);
15612 SDValue Tmp2 = SDValue(Node, 1);
15613 SDValue Tmp3 = Node->getOperand(2);
15614 SDValue Chain = Tmp1.getOperand(0);
15616 // Chain the dynamic stack allocation so that it doesn't modify the stack
15617 // pointer when other instructions are using the stack.
15618 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15621 SDValue Size = Tmp2.getOperand(1);
15622 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15623 Chain = SP.getValue(1);
15624 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15625 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15626 unsigned StackAlign = TFI.getStackAlignment();
15627 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15628 if (Align > StackAlign)
15629 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15630 DAG.getConstant(-(uint64_t)Align, VT));
15631 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15633 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15634 DAG.getIntPtrConstant(0, true), SDValue(),
15637 SDValue Ops[2] = { Tmp1, Tmp2 };
15638 return DAG.getMergeValues(Ops, dl);
15642 SDValue Chain = Op.getOperand(0);
15643 SDValue Size = Op.getOperand(1);
15644 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15645 EVT VT = Op.getNode()->getValueType(0);
15647 bool Is64Bit = Subtarget->is64Bit();
15648 EVT SPTy = getPointerTy();
15651 MachineRegisterInfo &MRI = MF.getRegInfo();
15654 // The 64 bit implementation of segmented stacks needs to clobber both r10
15655 // r11. This makes it impossible to use it along with nested parameters.
15656 const Function *F = MF.getFunction();
15658 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15660 if (I->hasNestAttr())
15661 report_fatal_error("Cannot use segmented stacks with functions that "
15662 "have nested arguments.");
15665 const TargetRegisterClass *AddrRegClass =
15666 getRegClassFor(getPointerTy());
15667 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15668 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15669 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15670 DAG.getRegister(Vreg, SPTy));
15671 SDValue Ops1[2] = { Value, Chain };
15672 return DAG.getMergeValues(Ops1, dl);
15675 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15677 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15678 Flag = Chain.getValue(1);
15679 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15681 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15683 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15684 DAG.getSubtarget().getRegisterInfo());
15685 unsigned SPReg = RegInfo->getStackRegister();
15686 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15687 Chain = SP.getValue(1);
15690 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15691 DAG.getConstant(-(uint64_t)Align, VT));
15692 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15695 SDValue Ops1[2] = { SP, Chain };
15696 return DAG.getMergeValues(Ops1, dl);
15700 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15701 MachineFunction &MF = DAG.getMachineFunction();
15702 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15704 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15707 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15708 // vastart just stores the address of the VarArgsFrameIndex slot into the
15709 // memory location argument.
15710 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15712 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15713 MachinePointerInfo(SV), false, false, 0);
15717 // gp_offset (0 - 6 * 8)
15718 // fp_offset (48 - 48 + 8 * 16)
15719 // overflow_arg_area (point to parameters coming in memory).
15721 SmallVector<SDValue, 8> MemOps;
15722 SDValue FIN = Op.getOperand(1);
15724 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15725 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15727 FIN, MachinePointerInfo(SV), false, false, 0);
15728 MemOps.push_back(Store);
15731 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15732 FIN, DAG.getIntPtrConstant(4));
15733 Store = DAG.getStore(Op.getOperand(0), DL,
15734 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15736 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15737 MemOps.push_back(Store);
15739 // Store ptr to overflow_arg_area
15740 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15741 FIN, DAG.getIntPtrConstant(4));
15742 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15744 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15745 MachinePointerInfo(SV, 8),
15747 MemOps.push_back(Store);
15749 // Store ptr to reg_save_area.
15750 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15751 FIN, DAG.getIntPtrConstant(8));
15752 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15754 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15755 MachinePointerInfo(SV, 16), false, false, 0);
15756 MemOps.push_back(Store);
15757 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15760 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15761 assert(Subtarget->is64Bit() &&
15762 "LowerVAARG only handles 64-bit va_arg!");
15763 assert((Subtarget->isTargetLinux() ||
15764 Subtarget->isTargetDarwin()) &&
15765 "Unhandled target in LowerVAARG");
15766 assert(Op.getNode()->getNumOperands() == 4);
15767 SDValue Chain = Op.getOperand(0);
15768 SDValue SrcPtr = Op.getOperand(1);
15769 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15770 unsigned Align = Op.getConstantOperandVal(3);
15773 EVT ArgVT = Op.getNode()->getValueType(0);
15774 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15775 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15778 // Decide which area this value should be read from.
15779 // TODO: Implement the AMD64 ABI in its entirety. This simple
15780 // selection mechanism works only for the basic types.
15781 if (ArgVT == MVT::f80) {
15782 llvm_unreachable("va_arg for f80 not yet implemented");
15783 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15784 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15785 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15786 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15788 llvm_unreachable("Unhandled argument type in LowerVAARG");
15791 if (ArgMode == 2) {
15792 // Sanity Check: Make sure using fp_offset makes sense.
15793 assert(!DAG.getTarget().Options.UseSoftFloat &&
15794 !(DAG.getMachineFunction()
15795 .getFunction()->getAttributes()
15796 .hasAttribute(AttributeSet::FunctionIndex,
15797 Attribute::NoImplicitFloat)) &&
15798 Subtarget->hasSSE1());
15801 // Insert VAARG_64 node into the DAG
15802 // VAARG_64 returns two values: Variable Argument Address, Chain
15803 SmallVector<SDValue, 11> InstOps;
15804 InstOps.push_back(Chain);
15805 InstOps.push_back(SrcPtr);
15806 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15807 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15808 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15809 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15810 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15811 VTs, InstOps, MVT::i64,
15812 MachinePointerInfo(SV),
15814 /*Volatile=*/false,
15816 /*WriteMem=*/true);
15817 Chain = VAARG.getValue(1);
15819 // Load the next argument and return it
15820 return DAG.getLoad(ArgVT, dl,
15823 MachinePointerInfo(),
15824 false, false, false, 0);
15827 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15828 SelectionDAG &DAG) {
15829 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15830 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15831 SDValue Chain = Op.getOperand(0);
15832 SDValue DstPtr = Op.getOperand(1);
15833 SDValue SrcPtr = Op.getOperand(2);
15834 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15835 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15838 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15839 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15841 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15844 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15845 // amount is a constant. Takes immediate version of shift as input.
15846 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15847 SDValue SrcOp, uint64_t ShiftAmt,
15848 SelectionDAG &DAG) {
15849 MVT ElementType = VT.getVectorElementType();
15851 // Fold this packed shift into its first operand if ShiftAmt is 0.
15855 // Check for ShiftAmt >= element width
15856 if (ShiftAmt >= ElementType.getSizeInBits()) {
15857 if (Opc == X86ISD::VSRAI)
15858 ShiftAmt = ElementType.getSizeInBits() - 1;
15860 return DAG.getConstant(0, VT);
15863 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15864 && "Unknown target vector shift-by-constant node");
15866 // Fold this packed vector shift into a build vector if SrcOp is a
15867 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15868 if (VT == SrcOp.getSimpleValueType() &&
15869 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15870 SmallVector<SDValue, 8> Elts;
15871 unsigned NumElts = SrcOp->getNumOperands();
15872 ConstantSDNode *ND;
15875 default: llvm_unreachable(nullptr);
15876 case X86ISD::VSHLI:
15877 for (unsigned i=0; i!=NumElts; ++i) {
15878 SDValue CurrentOp = SrcOp->getOperand(i);
15879 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15880 Elts.push_back(CurrentOp);
15883 ND = cast<ConstantSDNode>(CurrentOp);
15884 const APInt &C = ND->getAPIntValue();
15885 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15888 case X86ISD::VSRLI:
15889 for (unsigned i=0; i!=NumElts; ++i) {
15890 SDValue CurrentOp = SrcOp->getOperand(i);
15891 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15892 Elts.push_back(CurrentOp);
15895 ND = cast<ConstantSDNode>(CurrentOp);
15896 const APInt &C = ND->getAPIntValue();
15897 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15900 case X86ISD::VSRAI:
15901 for (unsigned i=0; i!=NumElts; ++i) {
15902 SDValue CurrentOp = SrcOp->getOperand(i);
15903 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15904 Elts.push_back(CurrentOp);
15907 ND = cast<ConstantSDNode>(CurrentOp);
15908 const APInt &C = ND->getAPIntValue();
15909 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15914 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15917 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15920 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15921 // may or may not be a constant. Takes immediate version of shift as input.
15922 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15923 SDValue SrcOp, SDValue ShAmt,
15924 SelectionDAG &DAG) {
15925 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15927 // Catch shift-by-constant.
15928 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15929 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15930 CShAmt->getZExtValue(), DAG);
15932 // Change opcode to non-immediate version
15934 default: llvm_unreachable("Unknown target vector shift node");
15935 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15936 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15937 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15940 // Need to build a vector containing shift amount
15941 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15944 ShOps[1] = DAG.getConstant(0, MVT::i32);
15945 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15946 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15948 // The return type has to be a 128-bit type with the same element
15949 // type as the input type.
15950 MVT EltVT = VT.getVectorElementType();
15951 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15953 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15954 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15957 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15958 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15959 /// necessary casting for \p Mask when lowering masking intrinsics.
15960 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15961 SDValue PreservedSrc, SelectionDAG &DAG) {
15962 EVT VT = Op.getValueType();
15963 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15964 MVT::i1, VT.getVectorNumElements());
15965 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15966 Mask.getValueType().getSizeInBits());
15969 assert(MaskVT.isSimple() && "invalid mask type");
15971 if (isAllOnes(Mask))
15974 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15975 // are extracted by EXTRACT_SUBVECTOR.
15976 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15977 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15978 DAG.getIntPtrConstant(0));
15980 switch (Op.getOpcode()) {
15982 case X86ISD::PCMPEQM:
15983 case X86ISD::PCMPGTM:
15985 case X86ISD::CMPMU:
15986 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15989 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15992 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15994 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15995 case Intrinsic::x86_fma_vfmadd_ps:
15996 case Intrinsic::x86_fma_vfmadd_pd:
15997 case Intrinsic::x86_fma_vfmadd_ps_256:
15998 case Intrinsic::x86_fma_vfmadd_pd_256:
15999 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16000 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16001 return X86ISD::FMADD;
16002 case Intrinsic::x86_fma_vfmsub_ps:
16003 case Intrinsic::x86_fma_vfmsub_pd:
16004 case Intrinsic::x86_fma_vfmsub_ps_256:
16005 case Intrinsic::x86_fma_vfmsub_pd_256:
16006 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16007 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16008 return X86ISD::FMSUB;
16009 case Intrinsic::x86_fma_vfnmadd_ps:
16010 case Intrinsic::x86_fma_vfnmadd_pd:
16011 case Intrinsic::x86_fma_vfnmadd_ps_256:
16012 case Intrinsic::x86_fma_vfnmadd_pd_256:
16013 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16014 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16015 return X86ISD::FNMADD;
16016 case Intrinsic::x86_fma_vfnmsub_ps:
16017 case Intrinsic::x86_fma_vfnmsub_pd:
16018 case Intrinsic::x86_fma_vfnmsub_ps_256:
16019 case Intrinsic::x86_fma_vfnmsub_pd_256:
16020 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16021 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16022 return X86ISD::FNMSUB;
16023 case Intrinsic::x86_fma_vfmaddsub_ps:
16024 case Intrinsic::x86_fma_vfmaddsub_pd:
16025 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16026 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16027 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16028 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16029 return X86ISD::FMADDSUB;
16030 case Intrinsic::x86_fma_vfmsubadd_ps:
16031 case Intrinsic::x86_fma_vfmsubadd_pd:
16032 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16033 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16034 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16035 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16036 return X86ISD::FMSUBADD;
16040 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16042 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16044 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16046 switch(IntrData->Type) {
16047 case INTR_TYPE_1OP:
16048 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16049 case INTR_TYPE_2OP:
16050 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16052 case INTR_TYPE_3OP:
16053 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16054 Op.getOperand(2), Op.getOperand(3));
16056 // Comparison intrinsics with masks.
16057 // Example of transformation:
16058 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16059 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16061 // (v8i1 (insert_subvector undef,
16062 // (v2i1 (and (PCMPEQM %a, %b),
16063 // (extract_subvector
16064 // (v8i1 (bitcast %mask)), 0))), 0))))
16065 EVT VT = Op.getOperand(1).getValueType();
16066 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16067 VT.getVectorNumElements());
16068 SDValue Mask = Op.getOperand(3);
16069 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16070 Mask.getValueType().getSizeInBits());
16071 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16072 Op.getOperand(1), Op.getOperand(2));
16073 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
16074 DAG.getTargetConstant(0, MaskVT), DAG);
16075 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16076 DAG.getUNDEF(BitcastVT), CmpMask,
16077 DAG.getIntPtrConstant(0));
16078 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16080 case COMI: { // Comparison intrinsics
16081 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16082 SDValue LHS = Op.getOperand(1);
16083 SDValue RHS = Op.getOperand(2);
16084 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16085 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16086 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16087 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16088 DAG.getConstant(X86CC, MVT::i8), Cond);
16089 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16092 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16093 Op.getOperand(1), Op.getOperand(2), DAG);
16100 default: return SDValue(); // Don't custom lower most intrinsics.
16102 // Arithmetic intrinsics.
16103 case Intrinsic::x86_sse2_pmulu_dq:
16104 case Intrinsic::x86_avx2_pmulu_dq:
16105 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16106 Op.getOperand(1), Op.getOperand(2));
16108 case Intrinsic::x86_sse41_pmuldq:
16109 case Intrinsic::x86_avx2_pmul_dq:
16110 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16111 Op.getOperand(1), Op.getOperand(2));
16113 case Intrinsic::x86_sse2_pmulhu_w:
16114 case Intrinsic::x86_avx2_pmulhu_w:
16115 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16116 Op.getOperand(1), Op.getOperand(2));
16118 case Intrinsic::x86_sse2_pmulh_w:
16119 case Intrinsic::x86_avx2_pmulh_w:
16120 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16121 Op.getOperand(1), Op.getOperand(2));
16123 // SSE/SSE2/AVX floating point max/min intrinsics.
16124 case Intrinsic::x86_sse_max_ps:
16125 case Intrinsic::x86_sse2_max_pd:
16126 case Intrinsic::x86_avx_max_ps_256:
16127 case Intrinsic::x86_avx_max_pd_256:
16128 case Intrinsic::x86_sse_min_ps:
16129 case Intrinsic::x86_sse2_min_pd:
16130 case Intrinsic::x86_avx_min_ps_256:
16131 case Intrinsic::x86_avx_min_pd_256: {
16134 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16135 case Intrinsic::x86_sse_max_ps:
16136 case Intrinsic::x86_sse2_max_pd:
16137 case Intrinsic::x86_avx_max_ps_256:
16138 case Intrinsic::x86_avx_max_pd_256:
16139 Opcode = X86ISD::FMAX;
16141 case Intrinsic::x86_sse_min_ps:
16142 case Intrinsic::x86_sse2_min_pd:
16143 case Intrinsic::x86_avx_min_ps_256:
16144 case Intrinsic::x86_avx_min_pd_256:
16145 Opcode = X86ISD::FMIN;
16148 return DAG.getNode(Opcode, dl, Op.getValueType(),
16149 Op.getOperand(1), Op.getOperand(2));
16152 // AVX2 variable shift intrinsics
16153 case Intrinsic::x86_avx2_psllv_d:
16154 case Intrinsic::x86_avx2_psllv_q:
16155 case Intrinsic::x86_avx2_psllv_d_256:
16156 case Intrinsic::x86_avx2_psllv_q_256:
16157 case Intrinsic::x86_avx2_psrlv_d:
16158 case Intrinsic::x86_avx2_psrlv_q:
16159 case Intrinsic::x86_avx2_psrlv_d_256:
16160 case Intrinsic::x86_avx2_psrlv_q_256:
16161 case Intrinsic::x86_avx2_psrav_d:
16162 case Intrinsic::x86_avx2_psrav_d_256: {
16165 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16166 case Intrinsic::x86_avx2_psllv_d:
16167 case Intrinsic::x86_avx2_psllv_q:
16168 case Intrinsic::x86_avx2_psllv_d_256:
16169 case Intrinsic::x86_avx2_psllv_q_256:
16172 case Intrinsic::x86_avx2_psrlv_d:
16173 case Intrinsic::x86_avx2_psrlv_q:
16174 case Intrinsic::x86_avx2_psrlv_d_256:
16175 case Intrinsic::x86_avx2_psrlv_q_256:
16178 case Intrinsic::x86_avx2_psrav_d:
16179 case Intrinsic::x86_avx2_psrav_d_256:
16183 return DAG.getNode(Opcode, dl, Op.getValueType(),
16184 Op.getOperand(1), Op.getOperand(2));
16187 case Intrinsic::x86_sse2_packssdw_128:
16188 case Intrinsic::x86_sse2_packsswb_128:
16189 case Intrinsic::x86_avx2_packssdw:
16190 case Intrinsic::x86_avx2_packsswb:
16191 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16192 Op.getOperand(1), Op.getOperand(2));
16194 case Intrinsic::x86_sse2_packuswb_128:
16195 case Intrinsic::x86_sse41_packusdw:
16196 case Intrinsic::x86_avx2_packuswb:
16197 case Intrinsic::x86_avx2_packusdw:
16198 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16199 Op.getOperand(1), Op.getOperand(2));
16201 case Intrinsic::x86_ssse3_pshuf_b_128:
16202 case Intrinsic::x86_avx2_pshuf_b:
16203 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16204 Op.getOperand(1), Op.getOperand(2));
16206 case Intrinsic::x86_sse2_pshuf_d:
16207 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16208 Op.getOperand(1), Op.getOperand(2));
16210 case Intrinsic::x86_sse2_pshufl_w:
16211 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16212 Op.getOperand(1), Op.getOperand(2));
16214 case Intrinsic::x86_sse2_pshufh_w:
16215 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16216 Op.getOperand(1), Op.getOperand(2));
16218 case Intrinsic::x86_ssse3_psign_b_128:
16219 case Intrinsic::x86_ssse3_psign_w_128:
16220 case Intrinsic::x86_ssse3_psign_d_128:
16221 case Intrinsic::x86_avx2_psign_b:
16222 case Intrinsic::x86_avx2_psign_w:
16223 case Intrinsic::x86_avx2_psign_d:
16224 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16225 Op.getOperand(1), Op.getOperand(2));
16227 case Intrinsic::x86_avx2_permd:
16228 case Intrinsic::x86_avx2_permps:
16229 // Operands intentionally swapped. Mask is last operand to intrinsic,
16230 // but second operand for node/instruction.
16231 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16232 Op.getOperand(2), Op.getOperand(1));
16234 case Intrinsic::x86_avx512_mask_valign_q_512:
16235 case Intrinsic::x86_avx512_mask_valign_d_512:
16236 // Vector source operands are swapped.
16237 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16238 Op.getValueType(), Op.getOperand(2),
16241 Op.getOperand(5), Op.getOperand(4), DAG);
16243 // ptest and testp intrinsics. The intrinsic these come from are designed to
16244 // return an integer value, not just an instruction so lower it to the ptest
16245 // or testp pattern and a setcc for the result.
16246 case Intrinsic::x86_sse41_ptestz:
16247 case Intrinsic::x86_sse41_ptestc:
16248 case Intrinsic::x86_sse41_ptestnzc:
16249 case Intrinsic::x86_avx_ptestz_256:
16250 case Intrinsic::x86_avx_ptestc_256:
16251 case Intrinsic::x86_avx_ptestnzc_256:
16252 case Intrinsic::x86_avx_vtestz_ps:
16253 case Intrinsic::x86_avx_vtestc_ps:
16254 case Intrinsic::x86_avx_vtestnzc_ps:
16255 case Intrinsic::x86_avx_vtestz_pd:
16256 case Intrinsic::x86_avx_vtestc_pd:
16257 case Intrinsic::x86_avx_vtestnzc_pd:
16258 case Intrinsic::x86_avx_vtestz_ps_256:
16259 case Intrinsic::x86_avx_vtestc_ps_256:
16260 case Intrinsic::x86_avx_vtestnzc_ps_256:
16261 case Intrinsic::x86_avx_vtestz_pd_256:
16262 case Intrinsic::x86_avx_vtestc_pd_256:
16263 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16264 bool IsTestPacked = false;
16267 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16268 case Intrinsic::x86_avx_vtestz_ps:
16269 case Intrinsic::x86_avx_vtestz_pd:
16270 case Intrinsic::x86_avx_vtestz_ps_256:
16271 case Intrinsic::x86_avx_vtestz_pd_256:
16272 IsTestPacked = true; // Fallthrough
16273 case Intrinsic::x86_sse41_ptestz:
16274 case Intrinsic::x86_avx_ptestz_256:
16276 X86CC = X86::COND_E;
16278 case Intrinsic::x86_avx_vtestc_ps:
16279 case Intrinsic::x86_avx_vtestc_pd:
16280 case Intrinsic::x86_avx_vtestc_ps_256:
16281 case Intrinsic::x86_avx_vtestc_pd_256:
16282 IsTestPacked = true; // Fallthrough
16283 case Intrinsic::x86_sse41_ptestc:
16284 case Intrinsic::x86_avx_ptestc_256:
16286 X86CC = X86::COND_B;
16288 case Intrinsic::x86_avx_vtestnzc_ps:
16289 case Intrinsic::x86_avx_vtestnzc_pd:
16290 case Intrinsic::x86_avx_vtestnzc_ps_256:
16291 case Intrinsic::x86_avx_vtestnzc_pd_256:
16292 IsTestPacked = true; // Fallthrough
16293 case Intrinsic::x86_sse41_ptestnzc:
16294 case Intrinsic::x86_avx_ptestnzc_256:
16296 X86CC = X86::COND_A;
16300 SDValue LHS = Op.getOperand(1);
16301 SDValue RHS = Op.getOperand(2);
16302 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16303 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16304 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16305 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16306 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16308 case Intrinsic::x86_avx512_kortestz_w:
16309 case Intrinsic::x86_avx512_kortestc_w: {
16310 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16311 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16312 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16313 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16314 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16315 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16316 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16319 case Intrinsic::x86_sse42_pcmpistria128:
16320 case Intrinsic::x86_sse42_pcmpestria128:
16321 case Intrinsic::x86_sse42_pcmpistric128:
16322 case Intrinsic::x86_sse42_pcmpestric128:
16323 case Intrinsic::x86_sse42_pcmpistrio128:
16324 case Intrinsic::x86_sse42_pcmpestrio128:
16325 case Intrinsic::x86_sse42_pcmpistris128:
16326 case Intrinsic::x86_sse42_pcmpestris128:
16327 case Intrinsic::x86_sse42_pcmpistriz128:
16328 case Intrinsic::x86_sse42_pcmpestriz128: {
16332 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16333 case Intrinsic::x86_sse42_pcmpistria128:
16334 Opcode = X86ISD::PCMPISTRI;
16335 X86CC = X86::COND_A;
16337 case Intrinsic::x86_sse42_pcmpestria128:
16338 Opcode = X86ISD::PCMPESTRI;
16339 X86CC = X86::COND_A;
16341 case Intrinsic::x86_sse42_pcmpistric128:
16342 Opcode = X86ISD::PCMPISTRI;
16343 X86CC = X86::COND_B;
16345 case Intrinsic::x86_sse42_pcmpestric128:
16346 Opcode = X86ISD::PCMPESTRI;
16347 X86CC = X86::COND_B;
16349 case Intrinsic::x86_sse42_pcmpistrio128:
16350 Opcode = X86ISD::PCMPISTRI;
16351 X86CC = X86::COND_O;
16353 case Intrinsic::x86_sse42_pcmpestrio128:
16354 Opcode = X86ISD::PCMPESTRI;
16355 X86CC = X86::COND_O;
16357 case Intrinsic::x86_sse42_pcmpistris128:
16358 Opcode = X86ISD::PCMPISTRI;
16359 X86CC = X86::COND_S;
16361 case Intrinsic::x86_sse42_pcmpestris128:
16362 Opcode = X86ISD::PCMPESTRI;
16363 X86CC = X86::COND_S;
16365 case Intrinsic::x86_sse42_pcmpistriz128:
16366 Opcode = X86ISD::PCMPISTRI;
16367 X86CC = X86::COND_E;
16369 case Intrinsic::x86_sse42_pcmpestriz128:
16370 Opcode = X86ISD::PCMPESTRI;
16371 X86CC = X86::COND_E;
16374 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16375 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16376 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16377 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16378 DAG.getConstant(X86CC, MVT::i8),
16379 SDValue(PCMP.getNode(), 1));
16380 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16383 case Intrinsic::x86_sse42_pcmpistri128:
16384 case Intrinsic::x86_sse42_pcmpestri128: {
16386 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16387 Opcode = X86ISD::PCMPISTRI;
16389 Opcode = X86ISD::PCMPESTRI;
16391 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16392 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16393 return DAG.getNode(Opcode, dl, VTs, NewOps);
16396 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16397 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16398 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16399 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16400 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16401 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16402 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16403 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16404 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16405 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16406 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16407 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16408 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16409 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16410 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16411 dl, Op.getValueType(),
16415 Op.getOperand(4), Op.getOperand(1), DAG);
16420 case Intrinsic::x86_fma_vfmadd_ps:
16421 case Intrinsic::x86_fma_vfmadd_pd:
16422 case Intrinsic::x86_fma_vfmsub_ps:
16423 case Intrinsic::x86_fma_vfmsub_pd:
16424 case Intrinsic::x86_fma_vfnmadd_ps:
16425 case Intrinsic::x86_fma_vfnmadd_pd:
16426 case Intrinsic::x86_fma_vfnmsub_ps:
16427 case Intrinsic::x86_fma_vfnmsub_pd:
16428 case Intrinsic::x86_fma_vfmaddsub_ps:
16429 case Intrinsic::x86_fma_vfmaddsub_pd:
16430 case Intrinsic::x86_fma_vfmsubadd_ps:
16431 case Intrinsic::x86_fma_vfmsubadd_pd:
16432 case Intrinsic::x86_fma_vfmadd_ps_256:
16433 case Intrinsic::x86_fma_vfmadd_pd_256:
16434 case Intrinsic::x86_fma_vfmsub_ps_256:
16435 case Intrinsic::x86_fma_vfmsub_pd_256:
16436 case Intrinsic::x86_fma_vfnmadd_ps_256:
16437 case Intrinsic::x86_fma_vfnmadd_pd_256:
16438 case Intrinsic::x86_fma_vfnmsub_ps_256:
16439 case Intrinsic::x86_fma_vfnmsub_pd_256:
16440 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16441 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16442 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16443 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16444 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16445 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16449 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16450 SDValue Src, SDValue Mask, SDValue Base,
16451 SDValue Index, SDValue ScaleOp, SDValue Chain,
16452 const X86Subtarget * Subtarget) {
16454 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16455 assert(C && "Invalid scale type");
16456 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16457 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16458 Index.getSimpleValueType().getVectorNumElements());
16460 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16462 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16464 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16465 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16466 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16467 SDValue Segment = DAG.getRegister(0, MVT::i32);
16468 if (Src.getOpcode() == ISD::UNDEF)
16469 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16470 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16471 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16472 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16473 return DAG.getMergeValues(RetOps, dl);
16476 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16477 SDValue Src, SDValue Mask, SDValue Base,
16478 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16480 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16481 assert(C && "Invalid scale type");
16482 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16483 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16484 SDValue Segment = DAG.getRegister(0, MVT::i32);
16485 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16486 Index.getSimpleValueType().getVectorNumElements());
16488 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16490 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16492 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16493 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16494 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16495 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16496 return SDValue(Res, 1);
16499 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16500 SDValue Mask, SDValue Base, SDValue Index,
16501 SDValue ScaleOp, SDValue Chain) {
16503 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16504 assert(C && "Invalid scale type");
16505 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16506 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16507 SDValue Segment = DAG.getRegister(0, MVT::i32);
16509 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16511 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16513 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16515 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16516 //SDVTList VTs = DAG.getVTList(MVT::Other);
16517 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16518 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16519 return SDValue(Res, 0);
16522 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16523 // read performance monitor counters (x86_rdpmc).
16524 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16525 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16526 SmallVectorImpl<SDValue> &Results) {
16527 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16528 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16531 // The ECX register is used to select the index of the performance counter
16533 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16535 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16537 // Reads the content of a 64-bit performance counter and returns it in the
16538 // registers EDX:EAX.
16539 if (Subtarget->is64Bit()) {
16540 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16541 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16544 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16545 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16548 Chain = HI.getValue(1);
16550 if (Subtarget->is64Bit()) {
16551 // The EAX register is loaded with the low-order 32 bits. The EDX register
16552 // is loaded with the supported high-order bits of the counter.
16553 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16554 DAG.getConstant(32, MVT::i8));
16555 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16556 Results.push_back(Chain);
16560 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16561 SDValue Ops[] = { LO, HI };
16562 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16563 Results.push_back(Pair);
16564 Results.push_back(Chain);
16567 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16568 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16569 // also used to custom lower READCYCLECOUNTER nodes.
16570 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16571 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16572 SmallVectorImpl<SDValue> &Results) {
16573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16574 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16577 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16578 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16579 // and the EAX register is loaded with the low-order 32 bits.
16580 if (Subtarget->is64Bit()) {
16581 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16582 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16585 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16586 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16589 SDValue Chain = HI.getValue(1);
16591 if (Opcode == X86ISD::RDTSCP_DAG) {
16592 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16594 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16595 // the ECX register. Add 'ecx' explicitly to the chain.
16596 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16598 // Explicitly store the content of ECX at the location passed in input
16599 // to the 'rdtscp' intrinsic.
16600 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16601 MachinePointerInfo(), false, false, 0);
16604 if (Subtarget->is64Bit()) {
16605 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16606 // the EAX register is loaded with the low-order 32 bits.
16607 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16608 DAG.getConstant(32, MVT::i8));
16609 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16610 Results.push_back(Chain);
16614 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16615 SDValue Ops[] = { LO, HI };
16616 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16617 Results.push_back(Pair);
16618 Results.push_back(Chain);
16621 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16622 SelectionDAG &DAG) {
16623 SmallVector<SDValue, 2> Results;
16625 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16627 return DAG.getMergeValues(Results, DL);
16631 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16632 SelectionDAG &DAG) {
16633 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16635 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16640 switch(IntrData->Type) {
16642 llvm_unreachable("Unknown Intrinsic Type");
16646 // Emit the node with the right value type.
16647 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16648 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16650 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16651 // Otherwise return the value from Rand, which is always 0, casted to i32.
16652 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16653 DAG.getConstant(1, Op->getValueType(1)),
16654 DAG.getConstant(X86::COND_B, MVT::i32),
16655 SDValue(Result.getNode(), 1) };
16656 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16657 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16660 // Return { result, isValid, chain }.
16661 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16662 SDValue(Result.getNode(), 2));
16665 //gather(v1, mask, index, base, scale);
16666 SDValue Chain = Op.getOperand(0);
16667 SDValue Src = Op.getOperand(2);
16668 SDValue Base = Op.getOperand(3);
16669 SDValue Index = Op.getOperand(4);
16670 SDValue Mask = Op.getOperand(5);
16671 SDValue Scale = Op.getOperand(6);
16672 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16676 //scatter(base, mask, index, v1, scale);
16677 SDValue Chain = Op.getOperand(0);
16678 SDValue Base = Op.getOperand(2);
16679 SDValue Mask = Op.getOperand(3);
16680 SDValue Index = Op.getOperand(4);
16681 SDValue Src = Op.getOperand(5);
16682 SDValue Scale = Op.getOperand(6);
16683 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16686 SDValue Hint = Op.getOperand(6);
16688 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16689 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16690 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16691 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16692 SDValue Chain = Op.getOperand(0);
16693 SDValue Mask = Op.getOperand(2);
16694 SDValue Index = Op.getOperand(3);
16695 SDValue Base = Op.getOperand(4);
16696 SDValue Scale = Op.getOperand(5);
16697 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16699 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16701 SmallVector<SDValue, 2> Results;
16702 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16703 return DAG.getMergeValues(Results, dl);
16705 // Read Performance Monitoring Counters.
16707 SmallVector<SDValue, 2> Results;
16708 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16709 return DAG.getMergeValues(Results, dl);
16711 // XTEST intrinsics.
16713 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16714 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16715 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16716 DAG.getConstant(X86::COND_NE, MVT::i8),
16718 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16719 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16720 Ret, SDValue(InTrans.getNode(), 1));
16724 SmallVector<SDValue, 2> Results;
16725 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16726 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16727 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16728 DAG.getConstant(-1, MVT::i8));
16729 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16730 Op.getOperand(4), GenCF.getValue(1));
16731 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16732 Op.getOperand(5), MachinePointerInfo(),
16734 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16735 DAG.getConstant(X86::COND_B, MVT::i8),
16737 Results.push_back(SetCC);
16738 Results.push_back(Store);
16739 return DAG.getMergeValues(Results, dl);
16744 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16745 SelectionDAG &DAG) const {
16746 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16747 MFI->setReturnAddressIsTaken(true);
16749 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16752 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16754 EVT PtrVT = getPointerTy();
16757 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16758 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16759 DAG.getSubtarget().getRegisterInfo());
16760 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16761 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16762 DAG.getNode(ISD::ADD, dl, PtrVT,
16763 FrameAddr, Offset),
16764 MachinePointerInfo(), false, false, false, 0);
16767 // Just load the return address.
16768 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16769 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16770 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16773 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16774 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16775 MFI->setFrameAddressIsTaken(true);
16777 EVT VT = Op.getValueType();
16778 SDLoc dl(Op); // FIXME probably not meaningful
16779 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16780 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16781 DAG.getSubtarget().getRegisterInfo());
16782 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16783 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16784 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16785 "Invalid Frame Register!");
16786 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16788 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16789 MachinePointerInfo(),
16790 false, false, false, 0);
16794 // FIXME? Maybe this could be a TableGen attribute on some registers and
16795 // this table could be generated automatically from RegInfo.
16796 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16798 unsigned Reg = StringSwitch<unsigned>(RegName)
16799 .Case("esp", X86::ESP)
16800 .Case("rsp", X86::RSP)
16804 report_fatal_error("Invalid register name global variable");
16807 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16808 SelectionDAG &DAG) const {
16809 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16810 DAG.getSubtarget().getRegisterInfo());
16811 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16814 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16815 SDValue Chain = Op.getOperand(0);
16816 SDValue Offset = Op.getOperand(1);
16817 SDValue Handler = Op.getOperand(2);
16820 EVT PtrVT = getPointerTy();
16821 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16822 DAG.getSubtarget().getRegisterInfo());
16823 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16824 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16825 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16826 "Invalid Frame Register!");
16827 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16828 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16830 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16831 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16832 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16833 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16835 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16837 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16838 DAG.getRegister(StoreAddrReg, PtrVT));
16841 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16842 SelectionDAG &DAG) const {
16844 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16845 DAG.getVTList(MVT::i32, MVT::Other),
16846 Op.getOperand(0), Op.getOperand(1));
16849 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16850 SelectionDAG &DAG) const {
16852 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16853 Op.getOperand(0), Op.getOperand(1));
16856 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16857 return Op.getOperand(0);
16860 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16861 SelectionDAG &DAG) const {
16862 SDValue Root = Op.getOperand(0);
16863 SDValue Trmp = Op.getOperand(1); // trampoline
16864 SDValue FPtr = Op.getOperand(2); // nested function
16865 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16868 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16869 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16871 if (Subtarget->is64Bit()) {
16872 SDValue OutChains[6];
16874 // Large code-model.
16875 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16876 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16878 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16879 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16881 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16883 // Load the pointer to the nested function into R11.
16884 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16885 SDValue Addr = Trmp;
16886 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16887 Addr, MachinePointerInfo(TrmpAddr),
16890 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16891 DAG.getConstant(2, MVT::i64));
16892 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16893 MachinePointerInfo(TrmpAddr, 2),
16896 // Load the 'nest' parameter value into R10.
16897 // R10 is specified in X86CallingConv.td
16898 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16900 DAG.getConstant(10, MVT::i64));
16901 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16902 Addr, MachinePointerInfo(TrmpAddr, 10),
16905 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16906 DAG.getConstant(12, MVT::i64));
16907 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16908 MachinePointerInfo(TrmpAddr, 12),
16911 // Jump to the nested function.
16912 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16913 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16914 DAG.getConstant(20, MVT::i64));
16915 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16916 Addr, MachinePointerInfo(TrmpAddr, 20),
16919 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16920 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16921 DAG.getConstant(22, MVT::i64));
16922 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16923 MachinePointerInfo(TrmpAddr, 22),
16926 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16928 const Function *Func =
16929 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16930 CallingConv::ID CC = Func->getCallingConv();
16935 llvm_unreachable("Unsupported calling convention");
16936 case CallingConv::C:
16937 case CallingConv::X86_StdCall: {
16938 // Pass 'nest' parameter in ECX.
16939 // Must be kept in sync with X86CallingConv.td
16940 NestReg = X86::ECX;
16942 // Check that ECX wasn't needed by an 'inreg' parameter.
16943 FunctionType *FTy = Func->getFunctionType();
16944 const AttributeSet &Attrs = Func->getAttributes();
16946 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16947 unsigned InRegCount = 0;
16950 for (FunctionType::param_iterator I = FTy->param_begin(),
16951 E = FTy->param_end(); I != E; ++I, ++Idx)
16952 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16953 // FIXME: should only count parameters that are lowered to integers.
16954 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16956 if (InRegCount > 2) {
16957 report_fatal_error("Nest register in use - reduce number of inreg"
16963 case CallingConv::X86_FastCall:
16964 case CallingConv::X86_ThisCall:
16965 case CallingConv::Fast:
16966 // Pass 'nest' parameter in EAX.
16967 // Must be kept in sync with X86CallingConv.td
16968 NestReg = X86::EAX;
16972 SDValue OutChains[4];
16973 SDValue Addr, Disp;
16975 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16976 DAG.getConstant(10, MVT::i32));
16977 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16979 // This is storing the opcode for MOV32ri.
16980 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16981 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16982 OutChains[0] = DAG.getStore(Root, dl,
16983 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16984 Trmp, MachinePointerInfo(TrmpAddr),
16987 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16988 DAG.getConstant(1, MVT::i32));
16989 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16990 MachinePointerInfo(TrmpAddr, 1),
16993 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16994 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16995 DAG.getConstant(5, MVT::i32));
16996 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16997 MachinePointerInfo(TrmpAddr, 5),
17000 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17001 DAG.getConstant(6, MVT::i32));
17002 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17003 MachinePointerInfo(TrmpAddr, 6),
17006 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17010 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17011 SelectionDAG &DAG) const {
17013 The rounding mode is in bits 11:10 of FPSR, and has the following
17015 00 Round to nearest
17020 FLT_ROUNDS, on the other hand, expects the following:
17027 To perform the conversion, we do:
17028 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17031 MachineFunction &MF = DAG.getMachineFunction();
17032 const TargetMachine &TM = MF.getTarget();
17033 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17034 unsigned StackAlignment = TFI.getStackAlignment();
17035 MVT VT = Op.getSimpleValueType();
17038 // Save FP Control Word to stack slot
17039 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17040 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17042 MachineMemOperand *MMO =
17043 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17044 MachineMemOperand::MOStore, 2, 2);
17046 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17047 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17048 DAG.getVTList(MVT::Other),
17049 Ops, MVT::i16, MMO);
17051 // Load FP Control Word from stack slot
17052 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17053 MachinePointerInfo(), false, false, false, 0);
17055 // Transform as necessary
17057 DAG.getNode(ISD::SRL, DL, MVT::i16,
17058 DAG.getNode(ISD::AND, DL, MVT::i16,
17059 CWD, DAG.getConstant(0x800, MVT::i16)),
17060 DAG.getConstant(11, MVT::i8));
17062 DAG.getNode(ISD::SRL, DL, MVT::i16,
17063 DAG.getNode(ISD::AND, DL, MVT::i16,
17064 CWD, DAG.getConstant(0x400, MVT::i16)),
17065 DAG.getConstant(9, MVT::i8));
17068 DAG.getNode(ISD::AND, DL, MVT::i16,
17069 DAG.getNode(ISD::ADD, DL, MVT::i16,
17070 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17071 DAG.getConstant(1, MVT::i16)),
17072 DAG.getConstant(3, MVT::i16));
17074 return DAG.getNode((VT.getSizeInBits() < 16 ?
17075 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17078 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17079 MVT VT = Op.getSimpleValueType();
17081 unsigned NumBits = VT.getSizeInBits();
17084 Op = Op.getOperand(0);
17085 if (VT == MVT::i8) {
17086 // Zero extend to i32 since there is not an i8 bsr.
17088 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17091 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17092 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17093 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17095 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17098 DAG.getConstant(NumBits+NumBits-1, OpVT),
17099 DAG.getConstant(X86::COND_E, MVT::i8),
17102 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17104 // Finally xor with NumBits-1.
17105 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17108 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17112 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17113 MVT VT = Op.getSimpleValueType();
17115 unsigned NumBits = VT.getSizeInBits();
17118 Op = Op.getOperand(0);
17119 if (VT == MVT::i8) {
17120 // Zero extend to i32 since there is not an i8 bsr.
17122 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17125 // Issue a bsr (scan bits in reverse).
17126 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17127 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17129 // And xor with NumBits-1.
17130 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17133 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17137 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17138 MVT VT = Op.getSimpleValueType();
17139 unsigned NumBits = VT.getSizeInBits();
17141 Op = Op.getOperand(0);
17143 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17144 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17145 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17147 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17150 DAG.getConstant(NumBits, VT),
17151 DAG.getConstant(X86::COND_E, MVT::i8),
17154 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17157 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17158 // ones, and then concatenate the result back.
17159 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17160 MVT VT = Op.getSimpleValueType();
17162 assert(VT.is256BitVector() && VT.isInteger() &&
17163 "Unsupported value type for operation");
17165 unsigned NumElems = VT.getVectorNumElements();
17168 // Extract the LHS vectors
17169 SDValue LHS = Op.getOperand(0);
17170 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17171 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17173 // Extract the RHS vectors
17174 SDValue RHS = Op.getOperand(1);
17175 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17176 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17178 MVT EltVT = VT.getVectorElementType();
17179 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17181 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17182 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17183 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17186 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17187 assert(Op.getSimpleValueType().is256BitVector() &&
17188 Op.getSimpleValueType().isInteger() &&
17189 "Only handle AVX 256-bit vector integer operation");
17190 return Lower256IntArith(Op, DAG);
17193 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17194 assert(Op.getSimpleValueType().is256BitVector() &&
17195 Op.getSimpleValueType().isInteger() &&
17196 "Only handle AVX 256-bit vector integer operation");
17197 return Lower256IntArith(Op, DAG);
17200 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17201 SelectionDAG &DAG) {
17203 MVT VT = Op.getSimpleValueType();
17205 // Decompose 256-bit ops into smaller 128-bit ops.
17206 if (VT.is256BitVector() && !Subtarget->hasInt256())
17207 return Lower256IntArith(Op, DAG);
17209 SDValue A = Op.getOperand(0);
17210 SDValue B = Op.getOperand(1);
17212 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17213 if (VT == MVT::v4i32) {
17214 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17215 "Should not custom lower when pmuldq is available!");
17217 // Extract the odd parts.
17218 static const int UnpackMask[] = { 1, -1, 3, -1 };
17219 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17220 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17222 // Multiply the even parts.
17223 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17224 // Now multiply odd parts.
17225 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17227 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17228 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17230 // Merge the two vectors back together with a shuffle. This expands into 2
17232 static const int ShufMask[] = { 0, 4, 2, 6 };
17233 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17236 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17237 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17239 // Ahi = psrlqi(a, 32);
17240 // Bhi = psrlqi(b, 32);
17242 // AloBlo = pmuludq(a, b);
17243 // AloBhi = pmuludq(a, Bhi);
17244 // AhiBlo = pmuludq(Ahi, b);
17246 // AloBhi = psllqi(AloBhi, 32);
17247 // AhiBlo = psllqi(AhiBlo, 32);
17248 // return AloBlo + AloBhi + AhiBlo;
17250 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17251 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17253 // Bit cast to 32-bit vectors for MULUDQ
17254 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17255 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17256 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17257 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17258 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17259 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17261 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17262 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17263 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17265 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17266 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17268 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17269 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17272 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17273 assert(Subtarget->isTargetWin64() && "Unexpected target");
17274 EVT VT = Op.getValueType();
17275 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17276 "Unexpected return type for lowering");
17280 switch (Op->getOpcode()) {
17281 default: llvm_unreachable("Unexpected request for libcall!");
17282 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17283 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17284 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17285 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17286 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17287 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17291 SDValue InChain = DAG.getEntryNode();
17293 TargetLowering::ArgListTy Args;
17294 TargetLowering::ArgListEntry Entry;
17295 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17296 EVT ArgVT = Op->getOperand(i).getValueType();
17297 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17298 "Unexpected argument type for lowering");
17299 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17300 Entry.Node = StackPtr;
17301 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17303 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17304 Entry.Ty = PointerType::get(ArgTy,0);
17305 Entry.isSExt = false;
17306 Entry.isZExt = false;
17307 Args.push_back(Entry);
17310 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17313 TargetLowering::CallLoweringInfo CLI(DAG);
17314 CLI.setDebugLoc(dl).setChain(InChain)
17315 .setCallee(getLibcallCallingConv(LC),
17316 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17317 Callee, std::move(Args), 0)
17318 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17320 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17321 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17324 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17325 SelectionDAG &DAG) {
17326 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17327 EVT VT = Op0.getValueType();
17330 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17331 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17333 // PMULxD operations multiply each even value (starting at 0) of LHS with
17334 // the related value of RHS and produce a widen result.
17335 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17336 // => <2 x i64> <ae|cg>
17338 // In other word, to have all the results, we need to perform two PMULxD:
17339 // 1. one with the even values.
17340 // 2. one with the odd values.
17341 // To achieve #2, with need to place the odd values at an even position.
17343 // Place the odd value at an even position (basically, shift all values 1
17344 // step to the left):
17345 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17346 // <a|b|c|d> => <b|undef|d|undef>
17347 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17348 // <e|f|g|h> => <f|undef|h|undef>
17349 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17351 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17353 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17354 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17356 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17357 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17358 // => <2 x i64> <ae|cg>
17359 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17360 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17361 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17362 // => <2 x i64> <bf|dh>
17363 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17364 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17366 // Shuffle it back into the right order.
17367 SDValue Highs, Lows;
17368 if (VT == MVT::v8i32) {
17369 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17370 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17371 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17372 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17374 const int HighMask[] = {1, 5, 3, 7};
17375 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17376 const int LowMask[] = {0, 4, 2, 6};
17377 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17380 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17381 // unsigned multiply.
17382 if (IsSigned && !Subtarget->hasSSE41()) {
17384 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17385 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17386 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17387 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17388 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17390 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17391 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17394 // The first result of MUL_LOHI is actually the low value, followed by the
17396 SDValue Ops[] = {Lows, Highs};
17397 return DAG.getMergeValues(Ops, dl);
17400 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17401 const X86Subtarget *Subtarget) {
17402 MVT VT = Op.getSimpleValueType();
17404 SDValue R = Op.getOperand(0);
17405 SDValue Amt = Op.getOperand(1);
17407 // Optimize shl/srl/sra with constant shift amount.
17408 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17409 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17410 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17412 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17413 (Subtarget->hasInt256() &&
17414 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17415 (Subtarget->hasAVX512() &&
17416 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17417 if (Op.getOpcode() == ISD::SHL)
17418 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17420 if (Op.getOpcode() == ISD::SRL)
17421 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17423 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17424 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17428 if (VT == MVT::v16i8) {
17429 if (Op.getOpcode() == ISD::SHL) {
17430 // Make a large shift.
17431 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17432 MVT::v8i16, R, ShiftAmt,
17434 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17435 // Zero out the rightmost bits.
17436 SmallVector<SDValue, 16> V(16,
17437 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17439 return DAG.getNode(ISD::AND, dl, VT, SHL,
17440 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17442 if (Op.getOpcode() == ISD::SRL) {
17443 // Make a large shift.
17444 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17445 MVT::v8i16, R, ShiftAmt,
17447 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17448 // Zero out the leftmost bits.
17449 SmallVector<SDValue, 16> V(16,
17450 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17452 return DAG.getNode(ISD::AND, dl, VT, SRL,
17453 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17455 if (Op.getOpcode() == ISD::SRA) {
17456 if (ShiftAmt == 7) {
17457 // R s>> 7 === R s< 0
17458 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17459 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17462 // R s>> a === ((R u>> a) ^ m) - m
17463 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17464 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17466 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17467 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17468 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17471 llvm_unreachable("Unknown shift opcode.");
17474 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17475 if (Op.getOpcode() == ISD::SHL) {
17476 // Make a large shift.
17477 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17478 MVT::v16i16, R, ShiftAmt,
17480 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17481 // Zero out the rightmost bits.
17482 SmallVector<SDValue, 32> V(32,
17483 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17485 return DAG.getNode(ISD::AND, dl, VT, SHL,
17486 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17488 if (Op.getOpcode() == ISD::SRL) {
17489 // Make a large shift.
17490 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17491 MVT::v16i16, R, ShiftAmt,
17493 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17494 // Zero out the leftmost bits.
17495 SmallVector<SDValue, 32> V(32,
17496 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17498 return DAG.getNode(ISD::AND, dl, VT, SRL,
17499 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17501 if (Op.getOpcode() == ISD::SRA) {
17502 if (ShiftAmt == 7) {
17503 // R s>> 7 === R s< 0
17504 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17505 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17508 // R s>> a === ((R u>> a) ^ m) - m
17509 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17510 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17512 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17513 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17514 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17517 llvm_unreachable("Unknown shift opcode.");
17522 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17523 if (!Subtarget->is64Bit() &&
17524 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17525 Amt.getOpcode() == ISD::BITCAST &&
17526 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17527 Amt = Amt.getOperand(0);
17528 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17529 VT.getVectorNumElements();
17530 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17531 uint64_t ShiftAmt = 0;
17532 for (unsigned i = 0; i != Ratio; ++i) {
17533 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17537 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17539 // Check remaining shift amounts.
17540 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17541 uint64_t ShAmt = 0;
17542 for (unsigned j = 0; j != Ratio; ++j) {
17543 ConstantSDNode *C =
17544 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17548 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17550 if (ShAmt != ShiftAmt)
17553 switch (Op.getOpcode()) {
17555 llvm_unreachable("Unknown shift opcode!");
17557 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17560 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17563 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17571 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17572 const X86Subtarget* Subtarget) {
17573 MVT VT = Op.getSimpleValueType();
17575 SDValue R = Op.getOperand(0);
17576 SDValue Amt = Op.getOperand(1);
17578 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17579 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17580 (Subtarget->hasInt256() &&
17581 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17582 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17583 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17585 EVT EltVT = VT.getVectorElementType();
17587 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17588 unsigned NumElts = VT.getVectorNumElements();
17590 for (i = 0; i != NumElts; ++i) {
17591 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17595 for (j = i; j != NumElts; ++j) {
17596 SDValue Arg = Amt.getOperand(j);
17597 if (Arg.getOpcode() == ISD::UNDEF) continue;
17598 if (Arg != Amt.getOperand(i))
17601 if (i != NumElts && j == NumElts)
17602 BaseShAmt = Amt.getOperand(i);
17604 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17605 Amt = Amt.getOperand(0);
17606 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17607 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17608 SDValue InVec = Amt.getOperand(0);
17609 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17610 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17612 for (; i != NumElts; ++i) {
17613 SDValue Arg = InVec.getOperand(i);
17614 if (Arg.getOpcode() == ISD::UNDEF) continue;
17618 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17619 if (ConstantSDNode *C =
17620 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17621 unsigned SplatIdx =
17622 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17623 if (C->getZExtValue() == SplatIdx)
17624 BaseShAmt = InVec.getOperand(1);
17627 if (!BaseShAmt.getNode())
17628 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17629 DAG.getIntPtrConstant(0));
17633 if (BaseShAmt.getNode()) {
17634 if (EltVT.bitsGT(MVT::i32))
17635 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17636 else if (EltVT.bitsLT(MVT::i32))
17637 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17639 switch (Op.getOpcode()) {
17641 llvm_unreachable("Unknown shift opcode!");
17643 switch (VT.SimpleTy) {
17644 default: return SDValue();
17653 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17656 switch (VT.SimpleTy) {
17657 default: return SDValue();
17664 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17667 switch (VT.SimpleTy) {
17668 default: return SDValue();
17677 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17683 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17684 if (!Subtarget->is64Bit() &&
17685 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17686 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17687 Amt.getOpcode() == ISD::BITCAST &&
17688 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17689 Amt = Amt.getOperand(0);
17690 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17691 VT.getVectorNumElements();
17692 std::vector<SDValue> Vals(Ratio);
17693 for (unsigned i = 0; i != Ratio; ++i)
17694 Vals[i] = Amt.getOperand(i);
17695 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17696 for (unsigned j = 0; j != Ratio; ++j)
17697 if (Vals[j] != Amt.getOperand(i + j))
17700 switch (Op.getOpcode()) {
17702 llvm_unreachable("Unknown shift opcode!");
17704 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17706 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17708 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17715 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17716 SelectionDAG &DAG) {
17717 MVT VT = Op.getSimpleValueType();
17719 SDValue R = Op.getOperand(0);
17720 SDValue Amt = Op.getOperand(1);
17723 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17724 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17726 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17730 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17734 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17736 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17737 if (Subtarget->hasInt256()) {
17738 if (Op.getOpcode() == ISD::SRL &&
17739 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17740 VT == MVT::v4i64 || VT == MVT::v8i32))
17742 if (Op.getOpcode() == ISD::SHL &&
17743 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17744 VT == MVT::v4i64 || VT == MVT::v8i32))
17746 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17750 // If possible, lower this packed shift into a vector multiply instead of
17751 // expanding it into a sequence of scalar shifts.
17752 // Do this only if the vector shift count is a constant build_vector.
17753 if (Op.getOpcode() == ISD::SHL &&
17754 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17755 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17756 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17757 SmallVector<SDValue, 8> Elts;
17758 EVT SVT = VT.getScalarType();
17759 unsigned SVTBits = SVT.getSizeInBits();
17760 const APInt &One = APInt(SVTBits, 1);
17761 unsigned NumElems = VT.getVectorNumElements();
17763 for (unsigned i=0; i !=NumElems; ++i) {
17764 SDValue Op = Amt->getOperand(i);
17765 if (Op->getOpcode() == ISD::UNDEF) {
17766 Elts.push_back(Op);
17770 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17771 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17772 uint64_t ShAmt = C.getZExtValue();
17773 if (ShAmt >= SVTBits) {
17774 Elts.push_back(DAG.getUNDEF(SVT));
17777 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17779 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17780 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17783 // Lower SHL with variable shift amount.
17784 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17785 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17787 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17788 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17789 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17790 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17793 // If possible, lower this shift as a sequence of two shifts by
17794 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17796 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17798 // Could be rewritten as:
17799 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17801 // The advantage is that the two shifts from the example would be
17802 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17803 // the vector shift into four scalar shifts plus four pairs of vector
17805 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17806 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17807 unsigned TargetOpcode = X86ISD::MOVSS;
17808 bool CanBeSimplified;
17809 // The splat value for the first packed shift (the 'X' from the example).
17810 SDValue Amt1 = Amt->getOperand(0);
17811 // The splat value for the second packed shift (the 'Y' from the example).
17812 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17813 Amt->getOperand(2);
17815 // See if it is possible to replace this node with a sequence of
17816 // two shifts followed by a MOVSS/MOVSD
17817 if (VT == MVT::v4i32) {
17818 // Check if it is legal to use a MOVSS.
17819 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17820 Amt2 == Amt->getOperand(3);
17821 if (!CanBeSimplified) {
17822 // Otherwise, check if we can still simplify this node using a MOVSD.
17823 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17824 Amt->getOperand(2) == Amt->getOperand(3);
17825 TargetOpcode = X86ISD::MOVSD;
17826 Amt2 = Amt->getOperand(2);
17829 // Do similar checks for the case where the machine value type
17831 CanBeSimplified = Amt1 == Amt->getOperand(1);
17832 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17833 CanBeSimplified = Amt2 == Amt->getOperand(i);
17835 if (!CanBeSimplified) {
17836 TargetOpcode = X86ISD::MOVSD;
17837 CanBeSimplified = true;
17838 Amt2 = Amt->getOperand(4);
17839 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17840 CanBeSimplified = Amt1 == Amt->getOperand(i);
17841 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17842 CanBeSimplified = Amt2 == Amt->getOperand(j);
17846 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17847 isa<ConstantSDNode>(Amt2)) {
17848 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17849 EVT CastVT = MVT::v4i32;
17851 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17852 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17854 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17855 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17856 if (TargetOpcode == X86ISD::MOVSD)
17857 CastVT = MVT::v2i64;
17858 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17859 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17860 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17862 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17866 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17867 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17870 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17871 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17873 // Turn 'a' into a mask suitable for VSELECT
17874 SDValue VSelM = DAG.getConstant(0x80, VT);
17875 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17876 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17878 SDValue CM1 = DAG.getConstant(0x0f, VT);
17879 SDValue CM2 = DAG.getConstant(0x3f, VT);
17881 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17882 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17883 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17884 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17885 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17888 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17889 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17890 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17892 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17893 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17894 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17895 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17896 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17899 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17900 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17901 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17903 // return VSELECT(r, r+r, a);
17904 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17905 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17909 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17910 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17911 // solution better.
17912 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17913 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17915 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17916 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17917 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17918 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17919 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17922 // Decompose 256-bit shifts into smaller 128-bit shifts.
17923 if (VT.is256BitVector()) {
17924 unsigned NumElems = VT.getVectorNumElements();
17925 MVT EltVT = VT.getVectorElementType();
17926 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17928 // Extract the two vectors
17929 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17930 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17932 // Recreate the shift amount vectors
17933 SDValue Amt1, Amt2;
17934 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17935 // Constant shift amount
17936 SmallVector<SDValue, 4> Amt1Csts;
17937 SmallVector<SDValue, 4> Amt2Csts;
17938 for (unsigned i = 0; i != NumElems/2; ++i)
17939 Amt1Csts.push_back(Amt->getOperand(i));
17940 for (unsigned i = NumElems/2; i != NumElems; ++i)
17941 Amt2Csts.push_back(Amt->getOperand(i));
17943 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17944 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17946 // Variable shift amount
17947 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17948 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17951 // Issue new vector shifts for the smaller types
17952 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17953 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17955 // Concatenate the result back
17956 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17962 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17963 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17964 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17965 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17966 // has only one use.
17967 SDNode *N = Op.getNode();
17968 SDValue LHS = N->getOperand(0);
17969 SDValue RHS = N->getOperand(1);
17970 unsigned BaseOp = 0;
17973 switch (Op.getOpcode()) {
17974 default: llvm_unreachable("Unknown ovf instruction!");
17976 // A subtract of one will be selected as a INC. Note that INC doesn't
17977 // set CF, so we can't do this for UADDO.
17978 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17980 BaseOp = X86ISD::INC;
17981 Cond = X86::COND_O;
17984 BaseOp = X86ISD::ADD;
17985 Cond = X86::COND_O;
17988 BaseOp = X86ISD::ADD;
17989 Cond = X86::COND_B;
17992 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17993 // set CF, so we can't do this for USUBO.
17994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17996 BaseOp = X86ISD::DEC;
17997 Cond = X86::COND_O;
18000 BaseOp = X86ISD::SUB;
18001 Cond = X86::COND_O;
18004 BaseOp = X86ISD::SUB;
18005 Cond = X86::COND_B;
18008 BaseOp = X86ISD::SMUL;
18009 Cond = X86::COND_O;
18011 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18012 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18014 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18017 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18018 DAG.getConstant(X86::COND_O, MVT::i32),
18019 SDValue(Sum.getNode(), 2));
18021 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18025 // Also sets EFLAGS.
18026 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18027 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18030 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18031 DAG.getConstant(Cond, MVT::i32),
18032 SDValue(Sum.getNode(), 1));
18034 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18037 // Sign extension of the low part of vector elements. This may be used either
18038 // when sign extend instructions are not available or if the vector element
18039 // sizes already match the sign-extended size. If the vector elements are in
18040 // their pre-extended size and sign extend instructions are available, that will
18041 // be handled by LowerSIGN_EXTEND.
18042 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18043 SelectionDAG &DAG) const {
18045 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18046 MVT VT = Op.getSimpleValueType();
18048 if (!Subtarget->hasSSE2() || !VT.isVector())
18051 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18052 ExtraVT.getScalarType().getSizeInBits();
18054 switch (VT.SimpleTy) {
18055 default: return SDValue();
18058 if (!Subtarget->hasFp256())
18060 if (!Subtarget->hasInt256()) {
18061 // needs to be split
18062 unsigned NumElems = VT.getVectorNumElements();
18064 // Extract the LHS vectors
18065 SDValue LHS = Op.getOperand(0);
18066 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18067 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18069 MVT EltVT = VT.getVectorElementType();
18070 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18072 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18073 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18074 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18076 SDValue Extra = DAG.getValueType(ExtraVT);
18078 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18079 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18081 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18086 SDValue Op0 = Op.getOperand(0);
18088 // This is a sign extension of some low part of vector elements without
18089 // changing the size of the vector elements themselves:
18090 // Shift-Left + Shift-Right-Algebraic.
18091 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18093 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18099 /// Returns true if the operand type is exactly twice the native width, and
18100 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18101 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18102 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18103 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18104 const X86Subtarget &Subtarget =
18105 getTargetMachine().getSubtarget<X86Subtarget>();
18106 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18109 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18110 else if (OpWidth == 128)
18111 return Subtarget.hasCmpxchg16b();
18116 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18117 return needsCmpXchgNb(SI->getValueOperand()->getType());
18120 // Note: this turns large loads into lock cmpxchg8b/16b.
18121 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18122 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18123 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18124 return needsCmpXchgNb(PTy->getElementType());
18127 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18128 const X86Subtarget &Subtarget =
18129 getTargetMachine().getSubtarget<X86Subtarget>();
18130 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18131 const Type *MemType = AI->getType();
18133 // If the operand is too big, we must see if cmpxchg8/16b is available
18134 // and default to library calls otherwise.
18135 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18136 return needsCmpXchgNb(MemType);
18138 AtomicRMWInst::BinOp Op = AI->getOperation();
18141 llvm_unreachable("Unknown atomic operation");
18142 case AtomicRMWInst::Xchg:
18143 case AtomicRMWInst::Add:
18144 case AtomicRMWInst::Sub:
18145 // It's better to use xadd, xsub or xchg for these in all cases.
18147 case AtomicRMWInst::Or:
18148 case AtomicRMWInst::And:
18149 case AtomicRMWInst::Xor:
18150 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18151 // prefix to a normal instruction for these operations.
18152 return !AI->use_empty();
18153 case AtomicRMWInst::Nand:
18154 case AtomicRMWInst::Max:
18155 case AtomicRMWInst::Min:
18156 case AtomicRMWInst::UMax:
18157 case AtomicRMWInst::UMin:
18158 // These always require a non-trivial set of data operations on x86. We must
18159 // use a cmpxchg loop.
18164 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18165 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18166 // no-sse2). There isn't any reason to disable it if the target processor
18168 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18172 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18173 const X86Subtarget &Subtarget =
18174 getTargetMachine().getSubtarget<X86Subtarget>();
18175 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18176 const Type *MemType = AI->getType();
18177 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18178 // there is no benefit in turning such RMWs into loads, and it is actually
18179 // harmful as it introduces a mfence.
18180 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18183 auto Builder = IRBuilder<>(AI);
18184 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18185 auto SynchScope = AI->getSynchScope();
18186 // We must restrict the ordering to avoid generating loads with Release or
18187 // ReleaseAcquire orderings.
18188 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18189 auto Ptr = AI->getPointerOperand();
18191 // Before the load we need a fence. Here is an example lifted from
18192 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18195 // x.store(1, relaxed);
18196 // r1 = y.fetch_add(0, release);
18198 // y.fetch_add(42, acquire);
18199 // r2 = x.load(relaxed);
18200 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18201 // lowered to just a load without a fence. A mfence flushes the store buffer,
18202 // making the optimization clearly correct.
18203 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18204 // otherwise, we might be able to be more agressive on relaxed idempotent
18205 // rmw. In practice, they do not look useful, so we don't try to be
18206 // especially clever.
18207 if (SynchScope == SingleThread) {
18208 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18209 // the IR level, so we must wrap it in an intrinsic.
18211 } else if (hasMFENCE(Subtarget)) {
18212 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18213 Intrinsic::x86_sse2_mfence);
18214 Builder.CreateCall(MFence);
18216 // FIXME: it might make sense to use a locked operation here but on a
18217 // different cache-line to prevent cache-line bouncing. In practice it
18218 // is probably a small win, and x86 processors without mfence are rare
18219 // enough that we do not bother.
18223 // Finally we can emit the atomic load.
18224 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18225 AI->getType()->getPrimitiveSizeInBits());
18226 Loaded->setAtomic(Order, SynchScope);
18227 AI->replaceAllUsesWith(Loaded);
18228 AI->eraseFromParent();
18232 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18233 SelectionDAG &DAG) {
18235 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18236 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18237 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18238 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18240 // The only fence that needs an instruction is a sequentially-consistent
18241 // cross-thread fence.
18242 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18243 if (hasMFENCE(*Subtarget))
18244 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18246 SDValue Chain = Op.getOperand(0);
18247 SDValue Zero = DAG.getConstant(0, MVT::i32);
18249 DAG.getRegister(X86::ESP, MVT::i32), // Base
18250 DAG.getTargetConstant(1, MVT::i8), // Scale
18251 DAG.getRegister(0, MVT::i32), // Index
18252 DAG.getTargetConstant(0, MVT::i32), // Disp
18253 DAG.getRegister(0, MVT::i32), // Segment.
18257 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18258 return SDValue(Res, 0);
18261 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18262 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18265 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18266 SelectionDAG &DAG) {
18267 MVT T = Op.getSimpleValueType();
18271 switch(T.SimpleTy) {
18272 default: llvm_unreachable("Invalid value type!");
18273 case MVT::i8: Reg = X86::AL; size = 1; break;
18274 case MVT::i16: Reg = X86::AX; size = 2; break;
18275 case MVT::i32: Reg = X86::EAX; size = 4; break;
18277 assert(Subtarget->is64Bit() && "Node not type legal!");
18278 Reg = X86::RAX; size = 8;
18281 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18282 Op.getOperand(2), SDValue());
18283 SDValue Ops[] = { cpIn.getValue(0),
18286 DAG.getTargetConstant(size, MVT::i8),
18287 cpIn.getValue(1) };
18288 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18289 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18290 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18294 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18295 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18296 MVT::i32, cpOut.getValue(2));
18297 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18298 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18300 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18301 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18302 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18306 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18307 SelectionDAG &DAG) {
18308 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18309 MVT DstVT = Op.getSimpleValueType();
18311 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18312 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18313 if (DstVT != MVT::f64)
18314 // This conversion needs to be expanded.
18317 SDValue InVec = Op->getOperand(0);
18319 unsigned NumElts = SrcVT.getVectorNumElements();
18320 EVT SVT = SrcVT.getVectorElementType();
18322 // Widen the vector in input in the case of MVT::v2i32.
18323 // Example: from MVT::v2i32 to MVT::v4i32.
18324 SmallVector<SDValue, 16> Elts;
18325 for (unsigned i = 0, e = NumElts; i != e; ++i)
18326 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18327 DAG.getIntPtrConstant(i)));
18329 // Explicitly mark the extra elements as Undef.
18330 SDValue Undef = DAG.getUNDEF(SVT);
18331 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18332 Elts.push_back(Undef);
18334 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18335 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18336 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18337 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18338 DAG.getIntPtrConstant(0));
18341 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18342 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18343 assert((DstVT == MVT::i64 ||
18344 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18345 "Unexpected custom BITCAST");
18346 // i64 <=> MMX conversions are Legal.
18347 if (SrcVT==MVT::i64 && DstVT.isVector())
18349 if (DstVT==MVT::i64 && SrcVT.isVector())
18351 // MMX <=> MMX conversions are Legal.
18352 if (SrcVT.isVector() && DstVT.isVector())
18354 // All other conversions need to be expanded.
18358 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18359 SDNode *Node = Op.getNode();
18361 EVT T = Node->getValueType(0);
18362 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18363 DAG.getConstant(0, T), Node->getOperand(2));
18364 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18365 cast<AtomicSDNode>(Node)->getMemoryVT(),
18366 Node->getOperand(0),
18367 Node->getOperand(1), negOp,
18368 cast<AtomicSDNode>(Node)->getMemOperand(),
18369 cast<AtomicSDNode>(Node)->getOrdering(),
18370 cast<AtomicSDNode>(Node)->getSynchScope());
18373 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18374 SDNode *Node = Op.getNode();
18376 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18378 // Convert seq_cst store -> xchg
18379 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18380 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18381 // (The only way to get a 16-byte store is cmpxchg16b)
18382 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18383 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18384 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18385 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18386 cast<AtomicSDNode>(Node)->getMemoryVT(),
18387 Node->getOperand(0),
18388 Node->getOperand(1), Node->getOperand(2),
18389 cast<AtomicSDNode>(Node)->getMemOperand(),
18390 cast<AtomicSDNode>(Node)->getOrdering(),
18391 cast<AtomicSDNode>(Node)->getSynchScope());
18392 return Swap.getValue(1);
18394 // Other atomic stores have a simple pattern.
18398 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18399 EVT VT = Op.getNode()->getSimpleValueType(0);
18401 // Let legalize expand this if it isn't a legal type yet.
18402 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18405 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18408 bool ExtraOp = false;
18409 switch (Op.getOpcode()) {
18410 default: llvm_unreachable("Invalid code");
18411 case ISD::ADDC: Opc = X86ISD::ADD; break;
18412 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18413 case ISD::SUBC: Opc = X86ISD::SUB; break;
18414 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18418 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18420 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18421 Op.getOperand(1), Op.getOperand(2));
18424 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18425 SelectionDAG &DAG) {
18426 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18428 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18429 // which returns the values as { float, float } (in XMM0) or
18430 // { double, double } (which is returned in XMM0, XMM1).
18432 SDValue Arg = Op.getOperand(0);
18433 EVT ArgVT = Arg.getValueType();
18434 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18436 TargetLowering::ArgListTy Args;
18437 TargetLowering::ArgListEntry Entry;
18441 Entry.isSExt = false;
18442 Entry.isZExt = false;
18443 Args.push_back(Entry);
18445 bool isF64 = ArgVT == MVT::f64;
18446 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18447 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18448 // the results are returned via SRet in memory.
18449 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18451 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18453 Type *RetTy = isF64
18454 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18455 : (Type*)VectorType::get(ArgTy, 4);
18457 TargetLowering::CallLoweringInfo CLI(DAG);
18458 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18459 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18461 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18464 // Returned in xmm0 and xmm1.
18465 return CallResult.first;
18467 // Returned in bits 0:31 and 32:64 xmm0.
18468 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18469 CallResult.first, DAG.getIntPtrConstant(0));
18470 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18471 CallResult.first, DAG.getIntPtrConstant(1));
18472 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18473 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18476 /// LowerOperation - Provide custom lowering hooks for some operations.
18478 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18479 switch (Op.getOpcode()) {
18480 default: llvm_unreachable("Should not custom lower this!");
18481 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18482 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18483 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18484 return LowerCMP_SWAP(Op, Subtarget, DAG);
18485 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18486 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18487 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18488 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18489 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18490 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18491 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18492 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18493 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18494 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18495 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18496 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18497 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18498 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18499 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18500 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18501 case ISD::SHL_PARTS:
18502 case ISD::SRA_PARTS:
18503 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18504 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18505 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18506 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18507 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18508 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18509 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18510 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18511 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18512 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18513 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18515 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18516 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18517 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18518 case ISD::SETCC: return LowerSETCC(Op, DAG);
18519 case ISD::SELECT: return LowerSELECT(Op, DAG);
18520 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18521 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18522 case ISD::VASTART: return LowerVASTART(Op, DAG);
18523 case ISD::VAARG: return LowerVAARG(Op, DAG);
18524 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18525 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18526 case ISD::INTRINSIC_VOID:
18527 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18528 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18529 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18530 case ISD::FRAME_TO_ARGS_OFFSET:
18531 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18532 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18533 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18534 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18535 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18536 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18537 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18538 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18539 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18540 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18541 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18542 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18543 case ISD::UMUL_LOHI:
18544 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18547 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18553 case ISD::UMULO: return LowerXALUO(Op, DAG);
18554 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18555 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18559 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18560 case ISD::ADD: return LowerADD(Op, DAG);
18561 case ISD::SUB: return LowerSUB(Op, DAG);
18562 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18566 /// ReplaceNodeResults - Replace a node with an illegal result type
18567 /// with a new node built out of custom code.
18568 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18569 SmallVectorImpl<SDValue>&Results,
18570 SelectionDAG &DAG) const {
18572 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18573 switch (N->getOpcode()) {
18575 llvm_unreachable("Do not know how to custom type legalize this operation!");
18576 case ISD::SIGN_EXTEND_INREG:
18581 // We don't want to expand or promote these.
18588 case ISD::UDIVREM: {
18589 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18590 Results.push_back(V);
18593 case ISD::FP_TO_SINT:
18594 case ISD::FP_TO_UINT: {
18595 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18597 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18600 std::pair<SDValue,SDValue> Vals =
18601 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18602 SDValue FIST = Vals.first, StackSlot = Vals.second;
18603 if (FIST.getNode()) {
18604 EVT VT = N->getValueType(0);
18605 // Return a load from the stack slot.
18606 if (StackSlot.getNode())
18607 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18608 MachinePointerInfo(),
18609 false, false, false, 0));
18611 Results.push_back(FIST);
18615 case ISD::UINT_TO_FP: {
18616 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18617 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18618 N->getValueType(0) != MVT::v2f32)
18620 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18622 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18624 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18625 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18626 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18627 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18628 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18629 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18632 case ISD::FP_ROUND: {
18633 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18635 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18636 Results.push_back(V);
18639 case ISD::INTRINSIC_W_CHAIN: {
18640 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18642 default : llvm_unreachable("Do not know how to custom type "
18643 "legalize this intrinsic operation!");
18644 case Intrinsic::x86_rdtsc:
18645 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18647 case Intrinsic::x86_rdtscp:
18648 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18650 case Intrinsic::x86_rdpmc:
18651 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18654 case ISD::READCYCLECOUNTER: {
18655 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18658 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18659 EVT T = N->getValueType(0);
18660 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18661 bool Regs64bit = T == MVT::i128;
18662 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18663 SDValue cpInL, cpInH;
18664 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18665 DAG.getConstant(0, HalfT));
18666 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18667 DAG.getConstant(1, HalfT));
18668 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18669 Regs64bit ? X86::RAX : X86::EAX,
18671 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18672 Regs64bit ? X86::RDX : X86::EDX,
18673 cpInH, cpInL.getValue(1));
18674 SDValue swapInL, swapInH;
18675 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18676 DAG.getConstant(0, HalfT));
18677 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18678 DAG.getConstant(1, HalfT));
18679 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18680 Regs64bit ? X86::RBX : X86::EBX,
18681 swapInL, cpInH.getValue(1));
18682 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18683 Regs64bit ? X86::RCX : X86::ECX,
18684 swapInH, swapInL.getValue(1));
18685 SDValue Ops[] = { swapInH.getValue(0),
18687 swapInH.getValue(1) };
18688 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18689 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18690 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18691 X86ISD::LCMPXCHG8_DAG;
18692 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18693 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18694 Regs64bit ? X86::RAX : X86::EAX,
18695 HalfT, Result.getValue(1));
18696 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18697 Regs64bit ? X86::RDX : X86::EDX,
18698 HalfT, cpOutL.getValue(2));
18699 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18701 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18702 MVT::i32, cpOutH.getValue(2));
18704 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18705 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18706 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18708 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18709 Results.push_back(Success);
18710 Results.push_back(EFLAGS.getValue(1));
18713 case ISD::ATOMIC_SWAP:
18714 case ISD::ATOMIC_LOAD_ADD:
18715 case ISD::ATOMIC_LOAD_SUB:
18716 case ISD::ATOMIC_LOAD_AND:
18717 case ISD::ATOMIC_LOAD_OR:
18718 case ISD::ATOMIC_LOAD_XOR:
18719 case ISD::ATOMIC_LOAD_NAND:
18720 case ISD::ATOMIC_LOAD_MIN:
18721 case ISD::ATOMIC_LOAD_MAX:
18722 case ISD::ATOMIC_LOAD_UMIN:
18723 case ISD::ATOMIC_LOAD_UMAX:
18724 case ISD::ATOMIC_LOAD: {
18725 // Delegate to generic TypeLegalization. Situations we can really handle
18726 // should have already been dealt with by AtomicExpandPass.cpp.
18729 case ISD::BITCAST: {
18730 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18731 EVT DstVT = N->getValueType(0);
18732 EVT SrcVT = N->getOperand(0)->getValueType(0);
18734 if (SrcVT != MVT::f64 ||
18735 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18738 unsigned NumElts = DstVT.getVectorNumElements();
18739 EVT SVT = DstVT.getVectorElementType();
18740 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18741 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18742 MVT::v2f64, N->getOperand(0));
18743 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18745 if (ExperimentalVectorWideningLegalization) {
18746 // If we are legalizing vectors by widening, we already have the desired
18747 // legal vector type, just return it.
18748 Results.push_back(ToVecInt);
18752 SmallVector<SDValue, 8> Elts;
18753 for (unsigned i = 0, e = NumElts; i != e; ++i)
18754 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18755 ToVecInt, DAG.getIntPtrConstant(i)));
18757 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18762 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18764 default: return nullptr;
18765 case X86ISD::BSF: return "X86ISD::BSF";
18766 case X86ISD::BSR: return "X86ISD::BSR";
18767 case X86ISD::SHLD: return "X86ISD::SHLD";
18768 case X86ISD::SHRD: return "X86ISD::SHRD";
18769 case X86ISD::FAND: return "X86ISD::FAND";
18770 case X86ISD::FANDN: return "X86ISD::FANDN";
18771 case X86ISD::FOR: return "X86ISD::FOR";
18772 case X86ISD::FXOR: return "X86ISD::FXOR";
18773 case X86ISD::FSRL: return "X86ISD::FSRL";
18774 case X86ISD::FILD: return "X86ISD::FILD";
18775 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18776 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18777 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18778 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18779 case X86ISD::FLD: return "X86ISD::FLD";
18780 case X86ISD::FST: return "X86ISD::FST";
18781 case X86ISD::CALL: return "X86ISD::CALL";
18782 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18783 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18784 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18785 case X86ISD::BT: return "X86ISD::BT";
18786 case X86ISD::CMP: return "X86ISD::CMP";
18787 case X86ISD::COMI: return "X86ISD::COMI";
18788 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18789 case X86ISD::CMPM: return "X86ISD::CMPM";
18790 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18791 case X86ISD::SETCC: return "X86ISD::SETCC";
18792 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18793 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18794 case X86ISD::CMOV: return "X86ISD::CMOV";
18795 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18796 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18797 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18798 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18799 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18800 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18801 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18802 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18803 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18804 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18805 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18806 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18807 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18808 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18809 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18810 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18811 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18812 case X86ISD::HADD: return "X86ISD::HADD";
18813 case X86ISD::HSUB: return "X86ISD::HSUB";
18814 case X86ISD::FHADD: return "X86ISD::FHADD";
18815 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18816 case X86ISD::UMAX: return "X86ISD::UMAX";
18817 case X86ISD::UMIN: return "X86ISD::UMIN";
18818 case X86ISD::SMAX: return "X86ISD::SMAX";
18819 case X86ISD::SMIN: return "X86ISD::SMIN";
18820 case X86ISD::FMAX: return "X86ISD::FMAX";
18821 case X86ISD::FMIN: return "X86ISD::FMIN";
18822 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18823 case X86ISD::FMINC: return "X86ISD::FMINC";
18824 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18825 case X86ISD::FRCP: return "X86ISD::FRCP";
18826 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18827 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18828 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18829 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18830 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18831 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18832 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18833 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18834 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18835 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18836 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18837 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18838 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18839 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18840 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18841 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18842 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18843 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18844 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18845 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18846 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18847 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18848 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18849 case X86ISD::VSHL: return "X86ISD::VSHL";
18850 case X86ISD::VSRL: return "X86ISD::VSRL";
18851 case X86ISD::VSRA: return "X86ISD::VSRA";
18852 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18853 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18854 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18855 case X86ISD::CMPP: return "X86ISD::CMPP";
18856 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18857 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18858 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18859 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18860 case X86ISD::ADD: return "X86ISD::ADD";
18861 case X86ISD::SUB: return "X86ISD::SUB";
18862 case X86ISD::ADC: return "X86ISD::ADC";
18863 case X86ISD::SBB: return "X86ISD::SBB";
18864 case X86ISD::SMUL: return "X86ISD::SMUL";
18865 case X86ISD::UMUL: return "X86ISD::UMUL";
18866 case X86ISD::INC: return "X86ISD::INC";
18867 case X86ISD::DEC: return "X86ISD::DEC";
18868 case X86ISD::OR: return "X86ISD::OR";
18869 case X86ISD::XOR: return "X86ISD::XOR";
18870 case X86ISD::AND: return "X86ISD::AND";
18871 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18872 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18873 case X86ISD::PTEST: return "X86ISD::PTEST";
18874 case X86ISD::TESTP: return "X86ISD::TESTP";
18875 case X86ISD::TESTM: return "X86ISD::TESTM";
18876 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18877 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18878 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18879 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18880 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18881 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18882 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18883 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18884 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18885 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18886 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18887 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18888 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18889 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18890 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18891 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18892 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18893 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18894 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18895 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18896 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18897 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18898 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18899 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18900 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18901 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18902 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18903 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18904 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18905 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18906 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18907 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18908 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18909 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18910 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18911 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18912 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18913 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18914 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18915 case X86ISD::SAHF: return "X86ISD::SAHF";
18916 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18917 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18918 case X86ISD::FMADD: return "X86ISD::FMADD";
18919 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18920 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18921 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18922 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18923 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18924 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18925 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18926 case X86ISD::XTEST: return "X86ISD::XTEST";
18930 // isLegalAddressingMode - Return true if the addressing mode represented
18931 // by AM is legal for this target, for a load/store of the specified type.
18932 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18934 // X86 supports extremely general addressing modes.
18935 CodeModel::Model M = getTargetMachine().getCodeModel();
18936 Reloc::Model R = getTargetMachine().getRelocationModel();
18938 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18939 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18944 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18946 // If a reference to this global requires an extra load, we can't fold it.
18947 if (isGlobalStubReference(GVFlags))
18950 // If BaseGV requires a register for the PIC base, we cannot also have a
18951 // BaseReg specified.
18952 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18955 // If lower 4G is not available, then we must use rip-relative addressing.
18956 if ((M != CodeModel::Small || R != Reloc::Static) &&
18957 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18961 switch (AM.Scale) {
18967 // These scales always work.
18972 // These scales are formed with basereg+scalereg. Only accept if there is
18977 default: // Other stuff never works.
18984 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18985 unsigned Bits = Ty->getScalarSizeInBits();
18987 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18988 // particularly cheaper than those without.
18992 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18993 // variable shifts just as cheap as scalar ones.
18994 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18997 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18998 // fully general vector.
19002 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19003 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19005 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19006 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19007 return NumBits1 > NumBits2;
19010 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19011 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19014 if (!isTypeLegal(EVT::getEVT(Ty1)))
19017 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19019 // Assuming the caller doesn't have a zeroext or signext return parameter,
19020 // truncation all the way down to i1 is valid.
19024 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19025 return isInt<32>(Imm);
19028 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19029 // Can also use sub to handle negated immediates.
19030 return isInt<32>(Imm);
19033 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19034 if (!VT1.isInteger() || !VT2.isInteger())
19036 unsigned NumBits1 = VT1.getSizeInBits();
19037 unsigned NumBits2 = VT2.getSizeInBits();
19038 return NumBits1 > NumBits2;
19041 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19042 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19043 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19046 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19047 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19048 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19051 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19052 EVT VT1 = Val.getValueType();
19053 if (isZExtFree(VT1, VT2))
19056 if (Val.getOpcode() != ISD::LOAD)
19059 if (!VT1.isSimple() || !VT1.isInteger() ||
19060 !VT2.isSimple() || !VT2.isInteger())
19063 switch (VT1.getSimpleVT().SimpleTy) {
19068 // X86 has 8, 16, and 32-bit zero-extending loads.
19076 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19077 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19080 VT = VT.getScalarType();
19082 if (!VT.isSimple())
19085 switch (VT.getSimpleVT().SimpleTy) {
19096 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19097 // i16 instructions are longer (0x66 prefix) and potentially slower.
19098 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19101 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19102 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19103 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19104 /// are assumed to be legal.
19106 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19108 if (!VT.isSimple())
19111 MVT SVT = VT.getSimpleVT();
19113 // Very little shuffling can be done for 64-bit vectors right now.
19114 if (VT.getSizeInBits() == 64)
19117 // If this is a single-input shuffle with no 128 bit lane crossings we can
19118 // lower it into pshufb.
19119 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19120 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19121 bool isLegal = true;
19122 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19123 if (M[I] >= (int)SVT.getVectorNumElements() ||
19124 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19133 // FIXME: blends, shifts.
19134 return (SVT.getVectorNumElements() == 2 ||
19135 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19136 isMOVLMask(M, SVT) ||
19137 isMOVHLPSMask(M, SVT) ||
19138 isSHUFPMask(M, SVT) ||
19139 isPSHUFDMask(M, SVT) ||
19140 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19141 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19142 isPALIGNRMask(M, SVT, Subtarget) ||
19143 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19144 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19145 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19146 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19147 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19151 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19153 if (!VT.isSimple())
19156 MVT SVT = VT.getSimpleVT();
19157 unsigned NumElts = SVT.getVectorNumElements();
19158 // FIXME: This collection of masks seems suspect.
19161 if (NumElts == 4 && SVT.is128BitVector()) {
19162 return (isMOVLMask(Mask, SVT) ||
19163 isCommutedMOVLMask(Mask, SVT, true) ||
19164 isSHUFPMask(Mask, SVT) ||
19165 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19170 //===----------------------------------------------------------------------===//
19171 // X86 Scheduler Hooks
19172 //===----------------------------------------------------------------------===//
19174 /// Utility function to emit xbegin specifying the start of an RTM region.
19175 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19176 const TargetInstrInfo *TII) {
19177 DebugLoc DL = MI->getDebugLoc();
19179 const BasicBlock *BB = MBB->getBasicBlock();
19180 MachineFunction::iterator I = MBB;
19183 // For the v = xbegin(), we generate
19194 MachineBasicBlock *thisMBB = MBB;
19195 MachineFunction *MF = MBB->getParent();
19196 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19197 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19198 MF->insert(I, mainMBB);
19199 MF->insert(I, sinkMBB);
19201 // Transfer the remainder of BB and its successor edges to sinkMBB.
19202 sinkMBB->splice(sinkMBB->begin(), MBB,
19203 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19204 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19208 // # fallthrough to mainMBB
19209 // # abortion to sinkMBB
19210 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19211 thisMBB->addSuccessor(mainMBB);
19212 thisMBB->addSuccessor(sinkMBB);
19216 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19217 mainMBB->addSuccessor(sinkMBB);
19220 // EAX is live into the sinkMBB
19221 sinkMBB->addLiveIn(X86::EAX);
19222 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19223 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19226 MI->eraseFromParent();
19230 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19231 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19232 // in the .td file.
19233 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19234 const TargetInstrInfo *TII) {
19236 switch (MI->getOpcode()) {
19237 default: llvm_unreachable("illegal opcode!");
19238 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19239 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19240 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19241 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19242 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19243 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19244 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19245 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19248 DebugLoc dl = MI->getDebugLoc();
19249 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19251 unsigned NumArgs = MI->getNumOperands();
19252 for (unsigned i = 1; i < NumArgs; ++i) {
19253 MachineOperand &Op = MI->getOperand(i);
19254 if (!(Op.isReg() && Op.isImplicit()))
19255 MIB.addOperand(Op);
19257 if (MI->hasOneMemOperand())
19258 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19260 BuildMI(*BB, MI, dl,
19261 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19262 .addReg(X86::XMM0);
19264 MI->eraseFromParent();
19268 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19269 // defs in an instruction pattern
19270 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19271 const TargetInstrInfo *TII) {
19273 switch (MI->getOpcode()) {
19274 default: llvm_unreachable("illegal opcode!");
19275 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19276 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19277 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19278 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19279 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19280 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19281 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19282 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19285 DebugLoc dl = MI->getDebugLoc();
19286 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19288 unsigned NumArgs = MI->getNumOperands(); // remove the results
19289 for (unsigned i = 1; i < NumArgs; ++i) {
19290 MachineOperand &Op = MI->getOperand(i);
19291 if (!(Op.isReg() && Op.isImplicit()))
19292 MIB.addOperand(Op);
19294 if (MI->hasOneMemOperand())
19295 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19297 BuildMI(*BB, MI, dl,
19298 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19301 MI->eraseFromParent();
19305 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19306 const TargetInstrInfo *TII,
19307 const X86Subtarget* Subtarget) {
19308 DebugLoc dl = MI->getDebugLoc();
19310 // Address into RAX/EAX, other two args into ECX, EDX.
19311 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19312 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19313 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19314 for (int i = 0; i < X86::AddrNumOperands; ++i)
19315 MIB.addOperand(MI->getOperand(i));
19317 unsigned ValOps = X86::AddrNumOperands;
19318 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19319 .addReg(MI->getOperand(ValOps).getReg());
19320 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19321 .addReg(MI->getOperand(ValOps+1).getReg());
19323 // The instruction doesn't actually take any operands though.
19324 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19326 MI->eraseFromParent(); // The pseudo is gone now.
19330 MachineBasicBlock *
19331 X86TargetLowering::EmitVAARG64WithCustomInserter(
19333 MachineBasicBlock *MBB) const {
19334 // Emit va_arg instruction on X86-64.
19336 // Operands to this pseudo-instruction:
19337 // 0 ) Output : destination address (reg)
19338 // 1-5) Input : va_list address (addr, i64mem)
19339 // 6 ) ArgSize : Size (in bytes) of vararg type
19340 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19341 // 8 ) Align : Alignment of type
19342 // 9 ) EFLAGS (implicit-def)
19344 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19345 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19347 unsigned DestReg = MI->getOperand(0).getReg();
19348 MachineOperand &Base = MI->getOperand(1);
19349 MachineOperand &Scale = MI->getOperand(2);
19350 MachineOperand &Index = MI->getOperand(3);
19351 MachineOperand &Disp = MI->getOperand(4);
19352 MachineOperand &Segment = MI->getOperand(5);
19353 unsigned ArgSize = MI->getOperand(6).getImm();
19354 unsigned ArgMode = MI->getOperand(7).getImm();
19355 unsigned Align = MI->getOperand(8).getImm();
19357 // Memory Reference
19358 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19359 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19360 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19362 // Machine Information
19363 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19364 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19365 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19366 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19367 DebugLoc DL = MI->getDebugLoc();
19369 // struct va_list {
19372 // i64 overflow_area (address)
19373 // i64 reg_save_area (address)
19375 // sizeof(va_list) = 24
19376 // alignment(va_list) = 8
19378 unsigned TotalNumIntRegs = 6;
19379 unsigned TotalNumXMMRegs = 8;
19380 bool UseGPOffset = (ArgMode == 1);
19381 bool UseFPOffset = (ArgMode == 2);
19382 unsigned MaxOffset = TotalNumIntRegs * 8 +
19383 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19385 /* Align ArgSize to a multiple of 8 */
19386 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19387 bool NeedsAlign = (Align > 8);
19389 MachineBasicBlock *thisMBB = MBB;
19390 MachineBasicBlock *overflowMBB;
19391 MachineBasicBlock *offsetMBB;
19392 MachineBasicBlock *endMBB;
19394 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19395 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19396 unsigned OffsetReg = 0;
19398 if (!UseGPOffset && !UseFPOffset) {
19399 // If we only pull from the overflow region, we don't create a branch.
19400 // We don't need to alter control flow.
19401 OffsetDestReg = 0; // unused
19402 OverflowDestReg = DestReg;
19404 offsetMBB = nullptr;
19405 overflowMBB = thisMBB;
19408 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19409 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19410 // If not, pull from overflow_area. (branch to overflowMBB)
19415 // offsetMBB overflowMBB
19420 // Registers for the PHI in endMBB
19421 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19422 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19424 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19425 MachineFunction *MF = MBB->getParent();
19426 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19427 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19428 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19430 MachineFunction::iterator MBBIter = MBB;
19433 // Insert the new basic blocks
19434 MF->insert(MBBIter, offsetMBB);
19435 MF->insert(MBBIter, overflowMBB);
19436 MF->insert(MBBIter, endMBB);
19438 // Transfer the remainder of MBB and its successor edges to endMBB.
19439 endMBB->splice(endMBB->begin(), thisMBB,
19440 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19441 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19443 // Make offsetMBB and overflowMBB successors of thisMBB
19444 thisMBB->addSuccessor(offsetMBB);
19445 thisMBB->addSuccessor(overflowMBB);
19447 // endMBB is a successor of both offsetMBB and overflowMBB
19448 offsetMBB->addSuccessor(endMBB);
19449 overflowMBB->addSuccessor(endMBB);
19451 // Load the offset value into a register
19452 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19453 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19457 .addDisp(Disp, UseFPOffset ? 4 : 0)
19458 .addOperand(Segment)
19459 .setMemRefs(MMOBegin, MMOEnd);
19461 // Check if there is enough room left to pull this argument.
19462 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19464 .addImm(MaxOffset + 8 - ArgSizeA8);
19466 // Branch to "overflowMBB" if offset >= max
19467 // Fall through to "offsetMBB" otherwise
19468 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19469 .addMBB(overflowMBB);
19472 // In offsetMBB, emit code to use the reg_save_area.
19474 assert(OffsetReg != 0);
19476 // Read the reg_save_area address.
19477 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19478 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19483 .addOperand(Segment)
19484 .setMemRefs(MMOBegin, MMOEnd);
19486 // Zero-extend the offset
19487 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19488 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19491 .addImm(X86::sub_32bit);
19493 // Add the offset to the reg_save_area to get the final address.
19494 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19495 .addReg(OffsetReg64)
19496 .addReg(RegSaveReg);
19498 // Compute the offset for the next argument
19499 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19500 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19502 .addImm(UseFPOffset ? 16 : 8);
19504 // Store it back into the va_list.
19505 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19509 .addDisp(Disp, UseFPOffset ? 4 : 0)
19510 .addOperand(Segment)
19511 .addReg(NextOffsetReg)
19512 .setMemRefs(MMOBegin, MMOEnd);
19515 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19520 // Emit code to use overflow area
19523 // Load the overflow_area address into a register.
19524 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19525 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19530 .addOperand(Segment)
19531 .setMemRefs(MMOBegin, MMOEnd);
19533 // If we need to align it, do so. Otherwise, just copy the address
19534 // to OverflowDestReg.
19536 // Align the overflow address
19537 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19538 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19540 // aligned_addr = (addr + (align-1)) & ~(align-1)
19541 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19542 .addReg(OverflowAddrReg)
19545 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19547 .addImm(~(uint64_t)(Align-1));
19549 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19550 .addReg(OverflowAddrReg);
19553 // Compute the next overflow address after this argument.
19554 // (the overflow address should be kept 8-byte aligned)
19555 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19556 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19557 .addReg(OverflowDestReg)
19558 .addImm(ArgSizeA8);
19560 // Store the new overflow address.
19561 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19566 .addOperand(Segment)
19567 .addReg(NextAddrReg)
19568 .setMemRefs(MMOBegin, MMOEnd);
19570 // If we branched, emit the PHI to the front of endMBB.
19572 BuildMI(*endMBB, endMBB->begin(), DL,
19573 TII->get(X86::PHI), DestReg)
19574 .addReg(OffsetDestReg).addMBB(offsetMBB)
19575 .addReg(OverflowDestReg).addMBB(overflowMBB);
19578 // Erase the pseudo instruction
19579 MI->eraseFromParent();
19584 MachineBasicBlock *
19585 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19587 MachineBasicBlock *MBB) const {
19588 // Emit code to save XMM registers to the stack. The ABI says that the
19589 // number of registers to save is given in %al, so it's theoretically
19590 // possible to do an indirect jump trick to avoid saving all of them,
19591 // however this code takes a simpler approach and just executes all
19592 // of the stores if %al is non-zero. It's less code, and it's probably
19593 // easier on the hardware branch predictor, and stores aren't all that
19594 // expensive anyway.
19596 // Create the new basic blocks. One block contains all the XMM stores,
19597 // and one block is the final destination regardless of whether any
19598 // stores were performed.
19599 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19600 MachineFunction *F = MBB->getParent();
19601 MachineFunction::iterator MBBIter = MBB;
19603 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19604 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19605 F->insert(MBBIter, XMMSaveMBB);
19606 F->insert(MBBIter, EndMBB);
19608 // Transfer the remainder of MBB and its successor edges to EndMBB.
19609 EndMBB->splice(EndMBB->begin(), MBB,
19610 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19611 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19613 // The original block will now fall through to the XMM save block.
19614 MBB->addSuccessor(XMMSaveMBB);
19615 // The XMMSaveMBB will fall through to the end block.
19616 XMMSaveMBB->addSuccessor(EndMBB);
19618 // Now add the instructions.
19619 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19620 DebugLoc DL = MI->getDebugLoc();
19622 unsigned CountReg = MI->getOperand(0).getReg();
19623 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19624 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19626 if (!Subtarget->isTargetWin64()) {
19627 // If %al is 0, branch around the XMM save block.
19628 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19629 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19630 MBB->addSuccessor(EndMBB);
19633 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19634 // that was just emitted, but clearly shouldn't be "saved".
19635 assert((MI->getNumOperands() <= 3 ||
19636 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19637 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19638 && "Expected last argument to be EFLAGS");
19639 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19640 // In the XMM save block, save all the XMM argument registers.
19641 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19642 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19643 MachineMemOperand *MMO =
19644 F->getMachineMemOperand(
19645 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19646 MachineMemOperand::MOStore,
19647 /*Size=*/16, /*Align=*/16);
19648 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19649 .addFrameIndex(RegSaveFrameIndex)
19650 .addImm(/*Scale=*/1)
19651 .addReg(/*IndexReg=*/0)
19652 .addImm(/*Disp=*/Offset)
19653 .addReg(/*Segment=*/0)
19654 .addReg(MI->getOperand(i).getReg())
19655 .addMemOperand(MMO);
19658 MI->eraseFromParent(); // The pseudo instruction is gone now.
19663 // The EFLAGS operand of SelectItr might be missing a kill marker
19664 // because there were multiple uses of EFLAGS, and ISel didn't know
19665 // which to mark. Figure out whether SelectItr should have had a
19666 // kill marker, and set it if it should. Returns the correct kill
19668 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19669 MachineBasicBlock* BB,
19670 const TargetRegisterInfo* TRI) {
19671 // Scan forward through BB for a use/def of EFLAGS.
19672 MachineBasicBlock::iterator miI(std::next(SelectItr));
19673 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19674 const MachineInstr& mi = *miI;
19675 if (mi.readsRegister(X86::EFLAGS))
19677 if (mi.definesRegister(X86::EFLAGS))
19678 break; // Should have kill-flag - update below.
19681 // If we hit the end of the block, check whether EFLAGS is live into a
19683 if (miI == BB->end()) {
19684 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19685 sEnd = BB->succ_end();
19686 sItr != sEnd; ++sItr) {
19687 MachineBasicBlock* succ = *sItr;
19688 if (succ->isLiveIn(X86::EFLAGS))
19693 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19694 // out. SelectMI should have a kill flag on EFLAGS.
19695 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19699 MachineBasicBlock *
19700 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19701 MachineBasicBlock *BB) const {
19702 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19703 DebugLoc DL = MI->getDebugLoc();
19705 // To "insert" a SELECT_CC instruction, we actually have to insert the
19706 // diamond control-flow pattern. The incoming instruction knows the
19707 // destination vreg to set, the condition code register to branch on, the
19708 // true/false values to select between, and a branch opcode to use.
19709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19710 MachineFunction::iterator It = BB;
19716 // cmpTY ccX, r1, r2
19718 // fallthrough --> copy0MBB
19719 MachineBasicBlock *thisMBB = BB;
19720 MachineFunction *F = BB->getParent();
19721 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19722 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19723 F->insert(It, copy0MBB);
19724 F->insert(It, sinkMBB);
19726 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19727 // live into the sink and copy blocks.
19728 const TargetRegisterInfo *TRI =
19729 BB->getParent()->getSubtarget().getRegisterInfo();
19730 if (!MI->killsRegister(X86::EFLAGS) &&
19731 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19732 copy0MBB->addLiveIn(X86::EFLAGS);
19733 sinkMBB->addLiveIn(X86::EFLAGS);
19736 // Transfer the remainder of BB and its successor edges to sinkMBB.
19737 sinkMBB->splice(sinkMBB->begin(), BB,
19738 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19739 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19741 // Add the true and fallthrough blocks as its successors.
19742 BB->addSuccessor(copy0MBB);
19743 BB->addSuccessor(sinkMBB);
19745 // Create the conditional branch instruction.
19747 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19748 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19751 // %FalseValue = ...
19752 // # fallthrough to sinkMBB
19753 copy0MBB->addSuccessor(sinkMBB);
19756 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19758 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19759 TII->get(X86::PHI), MI->getOperand(0).getReg())
19760 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19761 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19763 MI->eraseFromParent(); // The pseudo instruction is gone now.
19767 MachineBasicBlock *
19768 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19769 MachineBasicBlock *BB) const {
19770 MachineFunction *MF = BB->getParent();
19771 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19772 DebugLoc DL = MI->getDebugLoc();
19773 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19775 assert(MF->shouldSplitStack());
19777 const bool Is64Bit = Subtarget->is64Bit();
19778 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19780 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19781 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19784 // ... [Till the alloca]
19785 // If stacklet is not large enough, jump to mallocMBB
19788 // Allocate by subtracting from RSP
19789 // Jump to continueMBB
19792 // Allocate by call to runtime
19796 // [rest of original BB]
19799 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19800 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19801 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19803 MachineRegisterInfo &MRI = MF->getRegInfo();
19804 const TargetRegisterClass *AddrRegClass =
19805 getRegClassFor(getPointerTy());
19807 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19808 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19809 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19810 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19811 sizeVReg = MI->getOperand(1).getReg(),
19812 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19814 MachineFunction::iterator MBBIter = BB;
19817 MF->insert(MBBIter, bumpMBB);
19818 MF->insert(MBBIter, mallocMBB);
19819 MF->insert(MBBIter, continueMBB);
19821 continueMBB->splice(continueMBB->begin(), BB,
19822 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19823 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19825 // Add code to the main basic block to check if the stack limit has been hit,
19826 // and if so, jump to mallocMBB otherwise to bumpMBB.
19827 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19828 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19829 .addReg(tmpSPVReg).addReg(sizeVReg);
19830 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19831 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19832 .addReg(SPLimitVReg);
19833 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19835 // bumpMBB simply decreases the stack pointer, since we know the current
19836 // stacklet has enough space.
19837 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19838 .addReg(SPLimitVReg);
19839 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19840 .addReg(SPLimitVReg);
19841 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19843 // Calls into a routine in libgcc to allocate more space from the heap.
19844 const uint32_t *RegMask = MF->getTarget()
19845 .getSubtargetImpl()
19846 ->getRegisterInfo()
19847 ->getCallPreservedMask(CallingConv::C);
19849 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19851 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19852 .addExternalSymbol("__morestack_allocate_stack_space")
19853 .addRegMask(RegMask)
19854 .addReg(X86::RDI, RegState::Implicit)
19855 .addReg(X86::RAX, RegState::ImplicitDefine);
19856 } else if (Is64Bit) {
19857 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19859 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19860 .addExternalSymbol("__morestack_allocate_stack_space")
19861 .addRegMask(RegMask)
19862 .addReg(X86::EDI, RegState::Implicit)
19863 .addReg(X86::EAX, RegState::ImplicitDefine);
19865 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19867 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19868 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19869 .addExternalSymbol("__morestack_allocate_stack_space")
19870 .addRegMask(RegMask)
19871 .addReg(X86::EAX, RegState::ImplicitDefine);
19875 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19878 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19879 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19880 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19882 // Set up the CFG correctly.
19883 BB->addSuccessor(bumpMBB);
19884 BB->addSuccessor(mallocMBB);
19885 mallocMBB->addSuccessor(continueMBB);
19886 bumpMBB->addSuccessor(continueMBB);
19888 // Take care of the PHI nodes.
19889 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19890 MI->getOperand(0).getReg())
19891 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19892 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19894 // Delete the original pseudo instruction.
19895 MI->eraseFromParent();
19898 return continueMBB;
19901 MachineBasicBlock *
19902 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19903 MachineBasicBlock *BB) const {
19904 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19905 DebugLoc DL = MI->getDebugLoc();
19907 assert(!Subtarget->isTargetMacho());
19909 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19910 // non-trivial part is impdef of ESP.
19912 if (Subtarget->isTargetWin64()) {
19913 if (Subtarget->isTargetCygMing()) {
19914 // ___chkstk(Mingw64):
19915 // Clobbers R10, R11, RAX and EFLAGS.
19917 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19918 .addExternalSymbol("___chkstk")
19919 .addReg(X86::RAX, RegState::Implicit)
19920 .addReg(X86::RSP, RegState::Implicit)
19921 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19922 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19923 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19925 // __chkstk(MSVCRT): does not update stack pointer.
19926 // Clobbers R10, R11 and EFLAGS.
19927 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19928 .addExternalSymbol("__chkstk")
19929 .addReg(X86::RAX, RegState::Implicit)
19930 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19931 // RAX has the offset to be subtracted from RSP.
19932 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19937 const char *StackProbeSymbol =
19938 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19940 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19941 .addExternalSymbol(StackProbeSymbol)
19942 .addReg(X86::EAX, RegState::Implicit)
19943 .addReg(X86::ESP, RegState::Implicit)
19944 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19945 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19946 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19949 MI->eraseFromParent(); // The pseudo instruction is gone now.
19953 MachineBasicBlock *
19954 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19955 MachineBasicBlock *BB) const {
19956 // This is pretty easy. We're taking the value that we received from
19957 // our load from the relocation, sticking it in either RDI (x86-64)
19958 // or EAX and doing an indirect call. The return value will then
19959 // be in the normal return register.
19960 MachineFunction *F = BB->getParent();
19961 const X86InstrInfo *TII =
19962 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19963 DebugLoc DL = MI->getDebugLoc();
19965 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19966 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19968 // Get a register mask for the lowered call.
19969 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19970 // proper register mask.
19971 const uint32_t *RegMask = F->getTarget()
19972 .getSubtargetImpl()
19973 ->getRegisterInfo()
19974 ->getCallPreservedMask(CallingConv::C);
19975 if (Subtarget->is64Bit()) {
19976 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19977 TII->get(X86::MOV64rm), X86::RDI)
19979 .addImm(0).addReg(0)
19980 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19981 MI->getOperand(3).getTargetFlags())
19983 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19984 addDirectMem(MIB, X86::RDI);
19985 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19986 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19987 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19988 TII->get(X86::MOV32rm), X86::EAX)
19990 .addImm(0).addReg(0)
19991 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19992 MI->getOperand(3).getTargetFlags())
19994 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19995 addDirectMem(MIB, X86::EAX);
19996 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19998 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19999 TII->get(X86::MOV32rm), X86::EAX)
20000 .addReg(TII->getGlobalBaseReg(F))
20001 .addImm(0).addReg(0)
20002 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20003 MI->getOperand(3).getTargetFlags())
20005 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20006 addDirectMem(MIB, X86::EAX);
20007 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20010 MI->eraseFromParent(); // The pseudo instruction is gone now.
20014 MachineBasicBlock *
20015 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20016 MachineBasicBlock *MBB) const {
20017 DebugLoc DL = MI->getDebugLoc();
20018 MachineFunction *MF = MBB->getParent();
20019 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20020 MachineRegisterInfo &MRI = MF->getRegInfo();
20022 const BasicBlock *BB = MBB->getBasicBlock();
20023 MachineFunction::iterator I = MBB;
20026 // Memory Reference
20027 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20028 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20031 unsigned MemOpndSlot = 0;
20033 unsigned CurOp = 0;
20035 DstReg = MI->getOperand(CurOp++).getReg();
20036 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20037 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20038 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20039 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20041 MemOpndSlot = CurOp;
20043 MVT PVT = getPointerTy();
20044 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20045 "Invalid Pointer Size!");
20047 // For v = setjmp(buf), we generate
20050 // buf[LabelOffset] = restoreMBB
20051 // SjLjSetup restoreMBB
20057 // v = phi(main, restore)
20062 MachineBasicBlock *thisMBB = MBB;
20063 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20064 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20065 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20066 MF->insert(I, mainMBB);
20067 MF->insert(I, sinkMBB);
20068 MF->push_back(restoreMBB);
20070 MachineInstrBuilder MIB;
20072 // Transfer the remainder of BB and its successor edges to sinkMBB.
20073 sinkMBB->splice(sinkMBB->begin(), MBB,
20074 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20075 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20078 unsigned PtrStoreOpc = 0;
20079 unsigned LabelReg = 0;
20080 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20081 Reloc::Model RM = MF->getTarget().getRelocationModel();
20082 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20083 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20085 // Prepare IP either in reg or imm.
20086 if (!UseImmLabel) {
20087 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20088 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20089 LabelReg = MRI.createVirtualRegister(PtrRC);
20090 if (Subtarget->is64Bit()) {
20091 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20095 .addMBB(restoreMBB)
20098 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20099 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20100 .addReg(XII->getGlobalBaseReg(MF))
20103 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20107 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20109 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20110 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20111 if (i == X86::AddrDisp)
20112 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20114 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20117 MIB.addReg(LabelReg);
20119 MIB.addMBB(restoreMBB);
20120 MIB.setMemRefs(MMOBegin, MMOEnd);
20122 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20123 .addMBB(restoreMBB);
20125 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20126 MF->getSubtarget().getRegisterInfo());
20127 MIB.addRegMask(RegInfo->getNoPreservedMask());
20128 thisMBB->addSuccessor(mainMBB);
20129 thisMBB->addSuccessor(restoreMBB);
20133 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20134 mainMBB->addSuccessor(sinkMBB);
20137 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20138 TII->get(X86::PHI), DstReg)
20139 .addReg(mainDstReg).addMBB(mainMBB)
20140 .addReg(restoreDstReg).addMBB(restoreMBB);
20143 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20144 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20145 restoreMBB->addSuccessor(sinkMBB);
20147 MI->eraseFromParent();
20151 MachineBasicBlock *
20152 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20153 MachineBasicBlock *MBB) const {
20154 DebugLoc DL = MI->getDebugLoc();
20155 MachineFunction *MF = MBB->getParent();
20156 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20157 MachineRegisterInfo &MRI = MF->getRegInfo();
20159 // Memory Reference
20160 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20161 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20163 MVT PVT = getPointerTy();
20164 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20165 "Invalid Pointer Size!");
20167 const TargetRegisterClass *RC =
20168 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20169 unsigned Tmp = MRI.createVirtualRegister(RC);
20170 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20171 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20172 MF->getSubtarget().getRegisterInfo());
20173 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20174 unsigned SP = RegInfo->getStackRegister();
20176 MachineInstrBuilder MIB;
20178 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20179 const int64_t SPOffset = 2 * PVT.getStoreSize();
20181 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20182 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20185 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20186 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20187 MIB.addOperand(MI->getOperand(i));
20188 MIB.setMemRefs(MMOBegin, MMOEnd);
20190 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20191 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20192 if (i == X86::AddrDisp)
20193 MIB.addDisp(MI->getOperand(i), LabelOffset);
20195 MIB.addOperand(MI->getOperand(i));
20197 MIB.setMemRefs(MMOBegin, MMOEnd);
20199 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20200 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20201 if (i == X86::AddrDisp)
20202 MIB.addDisp(MI->getOperand(i), SPOffset);
20204 MIB.addOperand(MI->getOperand(i));
20206 MIB.setMemRefs(MMOBegin, MMOEnd);
20208 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20210 MI->eraseFromParent();
20214 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20215 // accumulator loops. Writing back to the accumulator allows the coalescer
20216 // to remove extra copies in the loop.
20217 MachineBasicBlock *
20218 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20219 MachineBasicBlock *MBB) const {
20220 MachineOperand &AddendOp = MI->getOperand(3);
20222 // Bail out early if the addend isn't a register - we can't switch these.
20223 if (!AddendOp.isReg())
20226 MachineFunction &MF = *MBB->getParent();
20227 MachineRegisterInfo &MRI = MF.getRegInfo();
20229 // Check whether the addend is defined by a PHI:
20230 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20231 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20232 if (!AddendDef.isPHI())
20235 // Look for the following pattern:
20237 // %addend = phi [%entry, 0], [%loop, %result]
20239 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20243 // %addend = phi [%entry, 0], [%loop, %result]
20245 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20247 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20248 assert(AddendDef.getOperand(i).isReg());
20249 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20250 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20251 if (&PHISrcInst == MI) {
20252 // Found a matching instruction.
20253 unsigned NewFMAOpc = 0;
20254 switch (MI->getOpcode()) {
20255 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20256 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20257 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20258 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20259 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20260 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20261 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20262 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20263 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20264 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20265 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20266 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20267 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20268 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20269 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20270 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20271 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20272 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20273 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20274 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20275 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20276 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20277 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20278 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20279 default: llvm_unreachable("Unrecognized FMA variant.");
20282 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20283 MachineInstrBuilder MIB =
20284 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20285 .addOperand(MI->getOperand(0))
20286 .addOperand(MI->getOperand(3))
20287 .addOperand(MI->getOperand(2))
20288 .addOperand(MI->getOperand(1));
20289 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20290 MI->eraseFromParent();
20297 MachineBasicBlock *
20298 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20299 MachineBasicBlock *BB) const {
20300 switch (MI->getOpcode()) {
20301 default: llvm_unreachable("Unexpected instr type to insert");
20302 case X86::TAILJMPd64:
20303 case X86::TAILJMPr64:
20304 case X86::TAILJMPm64:
20305 llvm_unreachable("TAILJMP64 would not be touched here.");
20306 case X86::TCRETURNdi64:
20307 case X86::TCRETURNri64:
20308 case X86::TCRETURNmi64:
20310 case X86::WIN_ALLOCA:
20311 return EmitLoweredWinAlloca(MI, BB);
20312 case X86::SEG_ALLOCA_32:
20313 case X86::SEG_ALLOCA_64:
20314 return EmitLoweredSegAlloca(MI, BB);
20315 case X86::TLSCall_32:
20316 case X86::TLSCall_64:
20317 return EmitLoweredTLSCall(MI, BB);
20318 case X86::CMOV_GR8:
20319 case X86::CMOV_FR32:
20320 case X86::CMOV_FR64:
20321 case X86::CMOV_V4F32:
20322 case X86::CMOV_V2F64:
20323 case X86::CMOV_V2I64:
20324 case X86::CMOV_V8F32:
20325 case X86::CMOV_V4F64:
20326 case X86::CMOV_V4I64:
20327 case X86::CMOV_V16F32:
20328 case X86::CMOV_V8F64:
20329 case X86::CMOV_V8I64:
20330 case X86::CMOV_GR16:
20331 case X86::CMOV_GR32:
20332 case X86::CMOV_RFP32:
20333 case X86::CMOV_RFP64:
20334 case X86::CMOV_RFP80:
20335 return EmitLoweredSelect(MI, BB);
20337 case X86::FP32_TO_INT16_IN_MEM:
20338 case X86::FP32_TO_INT32_IN_MEM:
20339 case X86::FP32_TO_INT64_IN_MEM:
20340 case X86::FP64_TO_INT16_IN_MEM:
20341 case X86::FP64_TO_INT32_IN_MEM:
20342 case X86::FP64_TO_INT64_IN_MEM:
20343 case X86::FP80_TO_INT16_IN_MEM:
20344 case X86::FP80_TO_INT32_IN_MEM:
20345 case X86::FP80_TO_INT64_IN_MEM: {
20346 MachineFunction *F = BB->getParent();
20347 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20348 DebugLoc DL = MI->getDebugLoc();
20350 // Change the floating point control register to use "round towards zero"
20351 // mode when truncating to an integer value.
20352 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20353 addFrameReference(BuildMI(*BB, MI, DL,
20354 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20356 // Load the old value of the high byte of the control word...
20358 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20359 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20362 // Set the high part to be round to zero...
20363 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20366 // Reload the modified control word now...
20367 addFrameReference(BuildMI(*BB, MI, DL,
20368 TII->get(X86::FLDCW16m)), CWFrameIdx);
20370 // Restore the memory image of control word to original value
20371 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20374 // Get the X86 opcode to use.
20376 switch (MI->getOpcode()) {
20377 default: llvm_unreachable("illegal opcode!");
20378 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20379 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20380 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20381 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20382 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20383 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20384 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20385 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20386 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20390 MachineOperand &Op = MI->getOperand(0);
20392 AM.BaseType = X86AddressMode::RegBase;
20393 AM.Base.Reg = Op.getReg();
20395 AM.BaseType = X86AddressMode::FrameIndexBase;
20396 AM.Base.FrameIndex = Op.getIndex();
20398 Op = MI->getOperand(1);
20400 AM.Scale = Op.getImm();
20401 Op = MI->getOperand(2);
20403 AM.IndexReg = Op.getImm();
20404 Op = MI->getOperand(3);
20405 if (Op.isGlobal()) {
20406 AM.GV = Op.getGlobal();
20408 AM.Disp = Op.getImm();
20410 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20411 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20413 // Reload the original control word now.
20414 addFrameReference(BuildMI(*BB, MI, DL,
20415 TII->get(X86::FLDCW16m)), CWFrameIdx);
20417 MI->eraseFromParent(); // The pseudo instruction is gone now.
20420 // String/text processing lowering.
20421 case X86::PCMPISTRM128REG:
20422 case X86::VPCMPISTRM128REG:
20423 case X86::PCMPISTRM128MEM:
20424 case X86::VPCMPISTRM128MEM:
20425 case X86::PCMPESTRM128REG:
20426 case X86::VPCMPESTRM128REG:
20427 case X86::PCMPESTRM128MEM:
20428 case X86::VPCMPESTRM128MEM:
20429 assert(Subtarget->hasSSE42() &&
20430 "Target must have SSE4.2 or AVX features enabled");
20431 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20433 // String/text processing lowering.
20434 case X86::PCMPISTRIREG:
20435 case X86::VPCMPISTRIREG:
20436 case X86::PCMPISTRIMEM:
20437 case X86::VPCMPISTRIMEM:
20438 case X86::PCMPESTRIREG:
20439 case X86::VPCMPESTRIREG:
20440 case X86::PCMPESTRIMEM:
20441 case X86::VPCMPESTRIMEM:
20442 assert(Subtarget->hasSSE42() &&
20443 "Target must have SSE4.2 or AVX features enabled");
20444 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20446 // Thread synchronization.
20448 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20453 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20455 case X86::VASTART_SAVE_XMM_REGS:
20456 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20458 case X86::VAARG_64:
20459 return EmitVAARG64WithCustomInserter(MI, BB);
20461 case X86::EH_SjLj_SetJmp32:
20462 case X86::EH_SjLj_SetJmp64:
20463 return emitEHSjLjSetJmp(MI, BB);
20465 case X86::EH_SjLj_LongJmp32:
20466 case X86::EH_SjLj_LongJmp64:
20467 return emitEHSjLjLongJmp(MI, BB);
20469 case TargetOpcode::STACKMAP:
20470 case TargetOpcode::PATCHPOINT:
20471 return emitPatchPoint(MI, BB);
20473 case X86::VFMADDPDr213r:
20474 case X86::VFMADDPSr213r:
20475 case X86::VFMADDSDr213r:
20476 case X86::VFMADDSSr213r:
20477 case X86::VFMSUBPDr213r:
20478 case X86::VFMSUBPSr213r:
20479 case X86::VFMSUBSDr213r:
20480 case X86::VFMSUBSSr213r:
20481 case X86::VFNMADDPDr213r:
20482 case X86::VFNMADDPSr213r:
20483 case X86::VFNMADDSDr213r:
20484 case X86::VFNMADDSSr213r:
20485 case X86::VFNMSUBPDr213r:
20486 case X86::VFNMSUBPSr213r:
20487 case X86::VFNMSUBSDr213r:
20488 case X86::VFNMSUBSSr213r:
20489 case X86::VFMADDPDr213rY:
20490 case X86::VFMADDPSr213rY:
20491 case X86::VFMSUBPDr213rY:
20492 case X86::VFMSUBPSr213rY:
20493 case X86::VFNMADDPDr213rY:
20494 case X86::VFNMADDPSr213rY:
20495 case X86::VFNMSUBPDr213rY:
20496 case X86::VFNMSUBPSr213rY:
20497 return emitFMA3Instr(MI, BB);
20501 //===----------------------------------------------------------------------===//
20502 // X86 Optimization Hooks
20503 //===----------------------------------------------------------------------===//
20505 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20508 const SelectionDAG &DAG,
20509 unsigned Depth) const {
20510 unsigned BitWidth = KnownZero.getBitWidth();
20511 unsigned Opc = Op.getOpcode();
20512 assert((Opc >= ISD::BUILTIN_OP_END ||
20513 Opc == ISD::INTRINSIC_WO_CHAIN ||
20514 Opc == ISD::INTRINSIC_W_CHAIN ||
20515 Opc == ISD::INTRINSIC_VOID) &&
20516 "Should use MaskedValueIsZero if you don't know whether Op"
20517 " is a target node!");
20519 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20533 // These nodes' second result is a boolean.
20534 if (Op.getResNo() == 0)
20537 case X86ISD::SETCC:
20538 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20540 case ISD::INTRINSIC_WO_CHAIN: {
20541 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20542 unsigned NumLoBits = 0;
20545 case Intrinsic::x86_sse_movmsk_ps:
20546 case Intrinsic::x86_avx_movmsk_ps_256:
20547 case Intrinsic::x86_sse2_movmsk_pd:
20548 case Intrinsic::x86_avx_movmsk_pd_256:
20549 case Intrinsic::x86_mmx_pmovmskb:
20550 case Intrinsic::x86_sse2_pmovmskb_128:
20551 case Intrinsic::x86_avx2_pmovmskb: {
20552 // High bits of movmskp{s|d}, pmovmskb are known zero.
20554 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20555 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20556 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20557 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20558 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20559 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20560 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20561 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20563 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20572 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20574 const SelectionDAG &,
20575 unsigned Depth) const {
20576 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20577 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20578 return Op.getValueType().getScalarType().getSizeInBits();
20584 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20585 /// node is a GlobalAddress + offset.
20586 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20587 const GlobalValue* &GA,
20588 int64_t &Offset) const {
20589 if (N->getOpcode() == X86ISD::Wrapper) {
20590 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20591 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20592 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20596 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20599 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20600 /// same as extracting the high 128-bit part of 256-bit vector and then
20601 /// inserting the result into the low part of a new 256-bit vector
20602 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20603 EVT VT = SVOp->getValueType(0);
20604 unsigned NumElems = VT.getVectorNumElements();
20606 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20607 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20608 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20609 SVOp->getMaskElt(j) >= 0)
20615 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20616 /// same as extracting the low 128-bit part of 256-bit vector and then
20617 /// inserting the result into the high part of a new 256-bit vector
20618 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20619 EVT VT = SVOp->getValueType(0);
20620 unsigned NumElems = VT.getVectorNumElements();
20622 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20623 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20624 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20625 SVOp->getMaskElt(j) >= 0)
20631 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20632 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20633 TargetLowering::DAGCombinerInfo &DCI,
20634 const X86Subtarget* Subtarget) {
20636 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20637 SDValue V1 = SVOp->getOperand(0);
20638 SDValue V2 = SVOp->getOperand(1);
20639 EVT VT = SVOp->getValueType(0);
20640 unsigned NumElems = VT.getVectorNumElements();
20642 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20643 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20647 // V UNDEF BUILD_VECTOR UNDEF
20649 // CONCAT_VECTOR CONCAT_VECTOR
20652 // RESULT: V + zero extended
20654 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20655 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20656 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20659 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20662 // To match the shuffle mask, the first half of the mask should
20663 // be exactly the first vector, and all the rest a splat with the
20664 // first element of the second one.
20665 for (unsigned i = 0; i != NumElems/2; ++i)
20666 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20667 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20670 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20671 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20672 if (Ld->hasNUsesOfValue(1, 0)) {
20673 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20674 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20676 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20678 Ld->getPointerInfo(),
20679 Ld->getAlignment(),
20680 false/*isVolatile*/, true/*ReadMem*/,
20681 false/*WriteMem*/);
20683 // Make sure the newly-created LOAD is in the same position as Ld in
20684 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20685 // and update uses of Ld's output chain to use the TokenFactor.
20686 if (Ld->hasAnyUseOfValue(1)) {
20687 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20688 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20689 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20690 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20691 SDValue(ResNode.getNode(), 1));
20694 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20698 // Emit a zeroed vector and insert the desired subvector on its
20700 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20701 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20702 return DCI.CombineTo(N, InsV);
20705 //===--------------------------------------------------------------------===//
20706 // Combine some shuffles into subvector extracts and inserts:
20709 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20710 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20711 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20712 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20713 return DCI.CombineTo(N, InsV);
20716 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20717 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20718 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20719 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20720 return DCI.CombineTo(N, InsV);
20726 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20729 /// This is the leaf of the recursive combinine below. When we have found some
20730 /// chain of single-use x86 shuffle instructions and accumulated the combined
20731 /// shuffle mask represented by them, this will try to pattern match that mask
20732 /// into either a single instruction if there is a special purpose instruction
20733 /// for this operation, or into a PSHUFB instruction which is a fully general
20734 /// instruction but should only be used to replace chains over a certain depth.
20735 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20736 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20737 TargetLowering::DAGCombinerInfo &DCI,
20738 const X86Subtarget *Subtarget) {
20739 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20741 // Find the operand that enters the chain. Note that multiple uses are OK
20742 // here, we're not going to remove the operand we find.
20743 SDValue Input = Op.getOperand(0);
20744 while (Input.getOpcode() == ISD::BITCAST)
20745 Input = Input.getOperand(0);
20747 MVT VT = Input.getSimpleValueType();
20748 MVT RootVT = Root.getSimpleValueType();
20751 // Just remove no-op shuffle masks.
20752 if (Mask.size() == 1) {
20753 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20758 // Use the float domain if the operand type is a floating point type.
20759 bool FloatDomain = VT.isFloatingPoint();
20761 // For floating point shuffles, we don't have free copies in the shuffle
20762 // instructions or the ability to load as part of the instruction, so
20763 // canonicalize their shuffles to UNPCK or MOV variants.
20765 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20766 // vectors because it can have a load folded into it that UNPCK cannot. This
20767 // doesn't preclude something switching to the shorter encoding post-RA.
20769 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20770 bool Lo = Mask.equals(0, 0);
20773 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20774 // is no slower than UNPCKLPD but has the option to fold the input operand
20775 // into even an unaligned memory load.
20776 if (Lo && Subtarget->hasSSE3()) {
20777 Shuffle = X86ISD::MOVDDUP;
20778 ShuffleVT = MVT::v2f64;
20780 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20781 // than the UNPCK variants.
20782 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20783 ShuffleVT = MVT::v4f32;
20785 if (Depth == 1 && Root->getOpcode() == Shuffle)
20786 return false; // Nothing to do!
20787 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20788 DCI.AddToWorklist(Op.getNode());
20789 if (Shuffle == X86ISD::MOVDDUP)
20790 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20792 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20793 DCI.AddToWorklist(Op.getNode());
20794 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20798 if (Subtarget->hasSSE3() &&
20799 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20800 bool Lo = Mask.equals(0, 0, 2, 2);
20801 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20802 MVT ShuffleVT = MVT::v4f32;
20803 if (Depth == 1 && Root->getOpcode() == Shuffle)
20804 return false; // Nothing to do!
20805 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20806 DCI.AddToWorklist(Op.getNode());
20807 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20808 DCI.AddToWorklist(Op.getNode());
20809 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20813 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20814 bool Lo = Mask.equals(0, 0, 1, 1);
20815 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20816 MVT ShuffleVT = MVT::v4f32;
20817 if (Depth == 1 && Root->getOpcode() == Shuffle)
20818 return false; // Nothing to do!
20819 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20820 DCI.AddToWorklist(Op.getNode());
20821 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20822 DCI.AddToWorklist(Op.getNode());
20823 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20829 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20830 // variants as none of these have single-instruction variants that are
20831 // superior to the UNPCK formulation.
20832 if (!FloatDomain &&
20833 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20834 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20835 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20836 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20838 bool Lo = Mask[0] == 0;
20839 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20840 if (Depth == 1 && Root->getOpcode() == Shuffle)
20841 return false; // Nothing to do!
20843 switch (Mask.size()) {
20845 ShuffleVT = MVT::v8i16;
20848 ShuffleVT = MVT::v16i8;
20851 llvm_unreachable("Impossible mask size!");
20853 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20854 DCI.AddToWorklist(Op.getNode());
20855 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20856 DCI.AddToWorklist(Op.getNode());
20857 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20862 // Don't try to re-form single instruction chains under any circumstances now
20863 // that we've done encoding canonicalization for them.
20867 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20868 // can replace them with a single PSHUFB instruction profitably. Intel's
20869 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20870 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20871 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20872 SmallVector<SDValue, 16> PSHUFBMask;
20873 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20874 int Ratio = 16 / Mask.size();
20875 for (unsigned i = 0; i < 16; ++i) {
20876 if (Mask[i / Ratio] == SM_SentinelUndef) {
20877 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20880 int M = Mask[i / Ratio] != SM_SentinelZero
20881 ? Ratio * Mask[i / Ratio] + i % Ratio
20883 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20885 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20886 DCI.AddToWorklist(Op.getNode());
20887 SDValue PSHUFBMaskOp =
20888 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20889 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20890 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20891 DCI.AddToWorklist(Op.getNode());
20892 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20897 // Failed to find any combines.
20901 /// \brief Fully generic combining of x86 shuffle instructions.
20903 /// This should be the last combine run over the x86 shuffle instructions. Once
20904 /// they have been fully optimized, this will recursively consider all chains
20905 /// of single-use shuffle instructions, build a generic model of the cumulative
20906 /// shuffle operation, and check for simpler instructions which implement this
20907 /// operation. We use this primarily for two purposes:
20909 /// 1) Collapse generic shuffles to specialized single instructions when
20910 /// equivalent. In most cases, this is just an encoding size win, but
20911 /// sometimes we will collapse multiple generic shuffles into a single
20912 /// special-purpose shuffle.
20913 /// 2) Look for sequences of shuffle instructions with 3 or more total
20914 /// instructions, and replace them with the slightly more expensive SSSE3
20915 /// PSHUFB instruction if available. We do this as the last combining step
20916 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20917 /// a suitable short sequence of other instructions. The PHUFB will either
20918 /// use a register or have to read from memory and so is slightly (but only
20919 /// slightly) more expensive than the other shuffle instructions.
20921 /// Because this is inherently a quadratic operation (for each shuffle in
20922 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20923 /// This should never be an issue in practice as the shuffle lowering doesn't
20924 /// produce sequences of more than 8 instructions.
20926 /// FIXME: We will currently miss some cases where the redundant shuffling
20927 /// would simplify under the threshold for PSHUFB formation because of
20928 /// combine-ordering. To fix this, we should do the redundant instruction
20929 /// combining in this recursive walk.
20930 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20931 ArrayRef<int> RootMask,
20932 int Depth, bool HasPSHUFB,
20934 TargetLowering::DAGCombinerInfo &DCI,
20935 const X86Subtarget *Subtarget) {
20936 // Bound the depth of our recursive combine because this is ultimately
20937 // quadratic in nature.
20941 // Directly rip through bitcasts to find the underlying operand.
20942 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20943 Op = Op.getOperand(0);
20945 MVT VT = Op.getSimpleValueType();
20946 if (!VT.isVector())
20947 return false; // Bail if we hit a non-vector.
20948 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20949 // version should be added.
20950 if (VT.getSizeInBits() != 128)
20953 assert(Root.getSimpleValueType().isVector() &&
20954 "Shuffles operate on vector types!");
20955 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20956 "Can only combine shuffles of the same vector register size.");
20958 if (!isTargetShuffle(Op.getOpcode()))
20960 SmallVector<int, 16> OpMask;
20962 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20963 // We only can combine unary shuffles which we can decode the mask for.
20964 if (!HaveMask || !IsUnary)
20967 assert(VT.getVectorNumElements() == OpMask.size() &&
20968 "Different mask size from vector size!");
20969 assert(((RootMask.size() > OpMask.size() &&
20970 RootMask.size() % OpMask.size() == 0) ||
20971 (OpMask.size() > RootMask.size() &&
20972 OpMask.size() % RootMask.size() == 0) ||
20973 OpMask.size() == RootMask.size()) &&
20974 "The smaller number of elements must divide the larger.");
20975 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20976 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20977 assert(((RootRatio == 1 && OpRatio == 1) ||
20978 (RootRatio == 1) != (OpRatio == 1)) &&
20979 "Must not have a ratio for both incoming and op masks!");
20981 SmallVector<int, 16> Mask;
20982 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20984 // Merge this shuffle operation's mask into our accumulated mask. Note that
20985 // this shuffle's mask will be the first applied to the input, followed by the
20986 // root mask to get us all the way to the root value arrangement. The reason
20987 // for this order is that we are recursing up the operation chain.
20988 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20989 int RootIdx = i / RootRatio;
20990 if (RootMask[RootIdx] < 0) {
20991 // This is a zero or undef lane, we're done.
20992 Mask.push_back(RootMask[RootIdx]);
20996 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20997 int OpIdx = RootMaskedIdx / OpRatio;
20998 if (OpMask[OpIdx] < 0) {
20999 // The incoming lanes are zero or undef, it doesn't matter which ones we
21001 Mask.push_back(OpMask[OpIdx]);
21005 // Ok, we have non-zero lanes, map them through.
21006 Mask.push_back(OpMask[OpIdx] * OpRatio +
21007 RootMaskedIdx % OpRatio);
21010 // See if we can recurse into the operand to combine more things.
21011 switch (Op.getOpcode()) {
21012 case X86ISD::PSHUFB:
21014 case X86ISD::PSHUFD:
21015 case X86ISD::PSHUFHW:
21016 case X86ISD::PSHUFLW:
21017 if (Op.getOperand(0).hasOneUse() &&
21018 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21019 HasPSHUFB, DAG, DCI, Subtarget))
21023 case X86ISD::UNPCKL:
21024 case X86ISD::UNPCKH:
21025 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21026 // We can't check for single use, we have to check that this shuffle is the only user.
21027 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21028 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21029 HasPSHUFB, DAG, DCI, Subtarget))
21034 // Minor canonicalization of the accumulated shuffle mask to make it easier
21035 // to match below. All this does is detect masks with squential pairs of
21036 // elements, and shrink them to the half-width mask. It does this in a loop
21037 // so it will reduce the size of the mask to the minimal width mask which
21038 // performs an equivalent shuffle.
21039 SmallVector<int, 16> WidenedMask;
21040 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21041 Mask = std::move(WidenedMask);
21042 WidenedMask.clear();
21045 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21049 /// \brief Get the PSHUF-style mask from PSHUF node.
21051 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21052 /// PSHUF-style masks that can be reused with such instructions.
21053 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21054 SmallVector<int, 4> Mask;
21056 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21060 switch (N.getOpcode()) {
21061 case X86ISD::PSHUFD:
21063 case X86ISD::PSHUFLW:
21066 case X86ISD::PSHUFHW:
21067 Mask.erase(Mask.begin(), Mask.begin() + 4);
21068 for (int &M : Mask)
21072 llvm_unreachable("No valid shuffle instruction found!");
21076 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21078 /// We walk up the chain and look for a combinable shuffle, skipping over
21079 /// shuffles that we could hoist this shuffle's transformation past without
21080 /// altering anything.
21082 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21084 TargetLowering::DAGCombinerInfo &DCI) {
21085 assert(N.getOpcode() == X86ISD::PSHUFD &&
21086 "Called with something other than an x86 128-bit half shuffle!");
21089 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21090 // of the shuffles in the chain so that we can form a fresh chain to replace
21092 SmallVector<SDValue, 8> Chain;
21093 SDValue V = N.getOperand(0);
21094 for (; V.hasOneUse(); V = V.getOperand(0)) {
21095 switch (V.getOpcode()) {
21097 return SDValue(); // Nothing combined!
21100 // Skip bitcasts as we always know the type for the target specific
21104 case X86ISD::PSHUFD:
21105 // Found another dword shuffle.
21108 case X86ISD::PSHUFLW:
21109 // Check that the low words (being shuffled) are the identity in the
21110 // dword shuffle, and the high words are self-contained.
21111 if (Mask[0] != 0 || Mask[1] != 1 ||
21112 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21115 Chain.push_back(V);
21118 case X86ISD::PSHUFHW:
21119 // Check that the high words (being shuffled) are the identity in the
21120 // dword shuffle, and the low words are self-contained.
21121 if (Mask[2] != 2 || Mask[3] != 3 ||
21122 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21125 Chain.push_back(V);
21128 case X86ISD::UNPCKL:
21129 case X86ISD::UNPCKH:
21130 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21131 // shuffle into a preceding word shuffle.
21132 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21135 // Search for a half-shuffle which we can combine with.
21136 unsigned CombineOp =
21137 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21138 if (V.getOperand(0) != V.getOperand(1) ||
21139 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21141 Chain.push_back(V);
21142 V = V.getOperand(0);
21144 switch (V.getOpcode()) {
21146 return SDValue(); // Nothing to combine.
21148 case X86ISD::PSHUFLW:
21149 case X86ISD::PSHUFHW:
21150 if (V.getOpcode() == CombineOp)
21153 Chain.push_back(V);
21157 V = V.getOperand(0);
21161 } while (V.hasOneUse());
21164 // Break out of the loop if we break out of the switch.
21168 if (!V.hasOneUse())
21169 // We fell out of the loop without finding a viable combining instruction.
21172 // Merge this node's mask and our incoming mask.
21173 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21174 for (int &M : Mask)
21176 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21177 getV4X86ShuffleImm8ForMask(Mask, DAG));
21179 // Rebuild the chain around this new shuffle.
21180 while (!Chain.empty()) {
21181 SDValue W = Chain.pop_back_val();
21183 if (V.getValueType() != W.getOperand(0).getValueType())
21184 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21186 switch (W.getOpcode()) {
21188 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21190 case X86ISD::UNPCKL:
21191 case X86ISD::UNPCKH:
21192 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21195 case X86ISD::PSHUFD:
21196 case X86ISD::PSHUFLW:
21197 case X86ISD::PSHUFHW:
21198 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21202 if (V.getValueType() != N.getValueType())
21203 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21205 // Return the new chain to replace N.
21209 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21211 /// We walk up the chain, skipping shuffles of the other half and looking
21212 /// through shuffles which switch halves trying to find a shuffle of the same
21213 /// pair of dwords.
21214 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21216 TargetLowering::DAGCombinerInfo &DCI) {
21218 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21219 "Called with something other than an x86 128-bit half shuffle!");
21221 unsigned CombineOpcode = N.getOpcode();
21223 // Walk up a single-use chain looking for a combinable shuffle.
21224 SDValue V = N.getOperand(0);
21225 for (; V.hasOneUse(); V = V.getOperand(0)) {
21226 switch (V.getOpcode()) {
21228 return false; // Nothing combined!
21231 // Skip bitcasts as we always know the type for the target specific
21235 case X86ISD::PSHUFLW:
21236 case X86ISD::PSHUFHW:
21237 if (V.getOpcode() == CombineOpcode)
21240 // Other-half shuffles are no-ops.
21243 // Break out of the loop if we break out of the switch.
21247 if (!V.hasOneUse())
21248 // We fell out of the loop without finding a viable combining instruction.
21251 // Combine away the bottom node as its shuffle will be accumulated into
21252 // a preceding shuffle.
21253 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21255 // Record the old value.
21258 // Merge this node's mask and our incoming mask (adjusted to account for all
21259 // the pshufd instructions encountered).
21260 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21261 for (int &M : Mask)
21263 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21264 getV4X86ShuffleImm8ForMask(Mask, DAG));
21266 // Check that the shuffles didn't cancel each other out. If not, we need to
21267 // combine to the new one.
21269 // Replace the combinable shuffle with the combined one, updating all users
21270 // so that we re-evaluate the chain here.
21271 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21276 /// \brief Try to combine x86 target specific shuffles.
21277 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21278 TargetLowering::DAGCombinerInfo &DCI,
21279 const X86Subtarget *Subtarget) {
21281 MVT VT = N.getSimpleValueType();
21282 SmallVector<int, 4> Mask;
21284 switch (N.getOpcode()) {
21285 case X86ISD::PSHUFD:
21286 case X86ISD::PSHUFLW:
21287 case X86ISD::PSHUFHW:
21288 Mask = getPSHUFShuffleMask(N);
21289 assert(Mask.size() == 4);
21295 // Nuke no-op shuffles that show up after combining.
21296 if (isNoopShuffleMask(Mask))
21297 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21299 // Look for simplifications involving one or two shuffle instructions.
21300 SDValue V = N.getOperand(0);
21301 switch (N.getOpcode()) {
21304 case X86ISD::PSHUFLW:
21305 case X86ISD::PSHUFHW:
21306 assert(VT == MVT::v8i16);
21309 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21310 return SDValue(); // We combined away this shuffle, so we're done.
21312 // See if this reduces to a PSHUFD which is no more expensive and can
21313 // combine with more operations. Note that it has to at least flip the
21314 // dwords as otherwise it would have been removed as a no-op.
21315 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21316 int DMask[] = {0, 1, 2, 3};
21317 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21318 DMask[DOffset + 0] = DOffset + 1;
21319 DMask[DOffset + 1] = DOffset + 0;
21320 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21321 DCI.AddToWorklist(V.getNode());
21322 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21323 getV4X86ShuffleImm8ForMask(DMask, DAG));
21324 DCI.AddToWorklist(V.getNode());
21325 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21328 // Look for shuffle patterns which can be implemented as a single unpack.
21329 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21330 // only works when we have a PSHUFD followed by two half-shuffles.
21331 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21332 (V.getOpcode() == X86ISD::PSHUFLW ||
21333 V.getOpcode() == X86ISD::PSHUFHW) &&
21334 V.getOpcode() != N.getOpcode() &&
21336 SDValue D = V.getOperand(0);
21337 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21338 D = D.getOperand(0);
21339 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21340 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21341 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21342 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21343 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21345 for (int i = 0; i < 4; ++i) {
21346 WordMask[i + NOffset] = Mask[i] + NOffset;
21347 WordMask[i + VOffset] = VMask[i] + VOffset;
21349 // Map the word mask through the DWord mask.
21351 for (int i = 0; i < 8; ++i)
21352 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21353 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21354 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21355 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21356 std::begin(UnpackLoMask)) ||
21357 std::equal(std::begin(MappedMask), std::end(MappedMask),
21358 std::begin(UnpackHiMask))) {
21359 // We can replace all three shuffles with an unpack.
21360 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21361 DCI.AddToWorklist(V.getNode());
21362 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21364 DL, MVT::v8i16, V, V);
21371 case X86ISD::PSHUFD:
21372 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21381 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21383 /// We combine this directly on the abstract vector shuffle nodes so it is
21384 /// easier to generically match. We also insert dummy vector shuffle nodes for
21385 /// the operands which explicitly discard the lanes which are unused by this
21386 /// operation to try to flow through the rest of the combiner the fact that
21387 /// they're unused.
21388 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21390 EVT VT = N->getValueType(0);
21392 // We only handle target-independent shuffles.
21393 // FIXME: It would be easy and harmless to use the target shuffle mask
21394 // extraction tool to support more.
21395 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21398 auto *SVN = cast<ShuffleVectorSDNode>(N);
21399 ArrayRef<int> Mask = SVN->getMask();
21400 SDValue V1 = N->getOperand(0);
21401 SDValue V2 = N->getOperand(1);
21403 // We require the first shuffle operand to be the SUB node, and the second to
21404 // be the ADD node.
21405 // FIXME: We should support the commuted patterns.
21406 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21409 // If there are other uses of these operations we can't fold them.
21410 if (!V1->hasOneUse() || !V2->hasOneUse())
21413 // Ensure that both operations have the same operands. Note that we can
21414 // commute the FADD operands.
21415 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21416 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21417 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21420 // We're looking for blends between FADD and FSUB nodes. We insist on these
21421 // nodes being lined up in a specific expected pattern.
21422 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21423 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21424 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21427 // Only specific types are legal at this point, assert so we notice if and
21428 // when these change.
21429 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21430 VT == MVT::v4f64) &&
21431 "Unknown vector type encountered!");
21433 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21436 /// PerformShuffleCombine - Performs several different shuffle combines.
21437 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21438 TargetLowering::DAGCombinerInfo &DCI,
21439 const X86Subtarget *Subtarget) {
21441 SDValue N0 = N->getOperand(0);
21442 SDValue N1 = N->getOperand(1);
21443 EVT VT = N->getValueType(0);
21445 // Don't create instructions with illegal types after legalize types has run.
21446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21447 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21450 // If we have legalized the vector types, look for blends of FADD and FSUB
21451 // nodes that we can fuse into an ADDSUB node.
21452 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21453 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21456 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21457 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21458 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21459 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21461 // During Type Legalization, when promoting illegal vector types,
21462 // the backend might introduce new shuffle dag nodes and bitcasts.
21464 // This code performs the following transformation:
21465 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21466 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21468 // We do this only if both the bitcast and the BINOP dag nodes have
21469 // one use. Also, perform this transformation only if the new binary
21470 // operation is legal. This is to avoid introducing dag nodes that
21471 // potentially need to be further expanded (or custom lowered) into a
21472 // less optimal sequence of dag nodes.
21473 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21474 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21475 N0.getOpcode() == ISD::BITCAST) {
21476 SDValue BC0 = N0.getOperand(0);
21477 EVT SVT = BC0.getValueType();
21478 unsigned Opcode = BC0.getOpcode();
21479 unsigned NumElts = VT.getVectorNumElements();
21481 if (BC0.hasOneUse() && SVT.isVector() &&
21482 SVT.getVectorNumElements() * 2 == NumElts &&
21483 TLI.isOperationLegal(Opcode, VT)) {
21484 bool CanFold = false;
21496 unsigned SVTNumElts = SVT.getVectorNumElements();
21497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21498 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21499 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21500 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21501 CanFold = SVOp->getMaskElt(i) < 0;
21504 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21505 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21506 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21507 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21512 // Only handle 128 wide vector from here on.
21513 if (!VT.is128BitVector())
21516 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21517 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21518 // consecutive, non-overlapping, and in the right order.
21519 SmallVector<SDValue, 16> Elts;
21520 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21521 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21523 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21527 if (isTargetShuffle(N->getOpcode())) {
21529 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21530 if (Shuffle.getNode())
21533 // Try recursively combining arbitrary sequences of x86 shuffle
21534 // instructions into higher-order shuffles. We do this after combining
21535 // specific PSHUF instruction sequences into their minimal form so that we
21536 // can evaluate how many specialized shuffle instructions are involved in
21537 // a particular chain.
21538 SmallVector<int, 1> NonceMask; // Just a placeholder.
21539 NonceMask.push_back(0);
21540 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21541 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21543 return SDValue(); // This routine will use CombineTo to replace N.
21549 /// PerformTruncateCombine - Converts truncate operation to
21550 /// a sequence of vector shuffle operations.
21551 /// It is possible when we truncate 256-bit vector to 128-bit vector
21552 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21553 TargetLowering::DAGCombinerInfo &DCI,
21554 const X86Subtarget *Subtarget) {
21558 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21559 /// specific shuffle of a load can be folded into a single element load.
21560 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21561 /// shuffles have been customed lowered so we need to handle those here.
21562 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21563 TargetLowering::DAGCombinerInfo &DCI) {
21564 if (DCI.isBeforeLegalizeOps())
21567 SDValue InVec = N->getOperand(0);
21568 SDValue EltNo = N->getOperand(1);
21570 if (!isa<ConstantSDNode>(EltNo))
21573 EVT VT = InVec.getValueType();
21575 if (InVec.getOpcode() == ISD::BITCAST) {
21576 // Don't duplicate a load with other uses.
21577 if (!InVec.hasOneUse())
21579 EVT BCVT = InVec.getOperand(0).getValueType();
21580 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21582 InVec = InVec.getOperand(0);
21585 if (!isTargetShuffle(InVec.getOpcode()))
21588 // Don't duplicate a load with other uses.
21589 if (!InVec.hasOneUse())
21592 SmallVector<int, 16> ShuffleMask;
21594 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21598 // Select the input vector, guarding against out of range extract vector.
21599 unsigned NumElems = VT.getVectorNumElements();
21600 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21601 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21602 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21603 : InVec.getOperand(1);
21605 // If inputs to shuffle are the same for both ops, then allow 2 uses
21606 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21608 if (LdNode.getOpcode() == ISD::BITCAST) {
21609 // Don't duplicate a load with other uses.
21610 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21613 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21614 LdNode = LdNode.getOperand(0);
21617 if (!ISD::isNormalLoad(LdNode.getNode()))
21620 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21622 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21625 EVT EltVT = N->getValueType(0);
21626 // If there's a bitcast before the shuffle, check if the load type and
21627 // alignment is valid.
21628 unsigned Align = LN0->getAlignment();
21629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21630 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21631 EltVT.getTypeForEVT(*DAG.getContext()));
21633 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21636 // All checks match so transform back to vector_shuffle so that DAG combiner
21637 // can finish the job
21640 // Create shuffle node taking into account the case that its a unary shuffle
21641 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21642 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21643 InVec.getOperand(0), Shuffle,
21645 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21646 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21650 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21651 /// generation and convert it from being a bunch of shuffles and extracts
21652 /// to a simple store and scalar loads to extract the elements.
21653 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21654 TargetLowering::DAGCombinerInfo &DCI) {
21655 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21656 if (NewOp.getNode())
21659 SDValue InputVector = N->getOperand(0);
21661 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21662 // from mmx to v2i32 has a single usage.
21663 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21664 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21665 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21666 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21667 N->getValueType(0),
21668 InputVector.getNode()->getOperand(0));
21670 // Only operate on vectors of 4 elements, where the alternative shuffling
21671 // gets to be more expensive.
21672 if (InputVector.getValueType() != MVT::v4i32)
21675 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21676 // single use which is a sign-extend or zero-extend, and all elements are
21678 SmallVector<SDNode *, 4> Uses;
21679 unsigned ExtractedElements = 0;
21680 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21681 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21682 if (UI.getUse().getResNo() != InputVector.getResNo())
21685 SDNode *Extract = *UI;
21686 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21689 if (Extract->getValueType(0) != MVT::i32)
21691 if (!Extract->hasOneUse())
21693 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21694 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21696 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21699 // Record which element was extracted.
21700 ExtractedElements |=
21701 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21703 Uses.push_back(Extract);
21706 // If not all the elements were used, this may not be worthwhile.
21707 if (ExtractedElements != 15)
21710 // Ok, we've now decided to do the transformation.
21711 SDLoc dl(InputVector);
21713 // Store the value to a temporary stack slot.
21714 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21715 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21716 MachinePointerInfo(), false, false, 0);
21718 // Replace each use (extract) with a load of the appropriate element.
21719 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21720 UE = Uses.end(); UI != UE; ++UI) {
21721 SDNode *Extract = *UI;
21723 // cOMpute the element's address.
21724 SDValue Idx = Extract->getOperand(1);
21726 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21727 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21729 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21731 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21732 StackPtr, OffsetVal);
21734 // Load the scalar.
21735 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21736 ScalarAddr, MachinePointerInfo(),
21737 false, false, false, 0);
21739 // Replace the exact with the load.
21740 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21743 // The replacement was made in place; don't return anything.
21747 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21748 static std::pair<unsigned, bool>
21749 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21750 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21751 if (!VT.isVector())
21752 return std::make_pair(0, false);
21754 bool NeedSplit = false;
21755 switch (VT.getSimpleVT().SimpleTy) {
21756 default: return std::make_pair(0, false);
21760 if (!Subtarget->hasAVX2())
21762 if (!Subtarget->hasAVX())
21763 return std::make_pair(0, false);
21768 if (!Subtarget->hasSSE2())
21769 return std::make_pair(0, false);
21772 // SSE2 has only a small subset of the operations.
21773 bool hasUnsigned = Subtarget->hasSSE41() ||
21774 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21775 bool hasSigned = Subtarget->hasSSE41() ||
21776 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21778 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21781 // Check for x CC y ? x : y.
21782 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21783 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21788 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21791 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21794 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21797 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21799 // Check for x CC y ? y : x -- a min/max with reversed arms.
21800 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21801 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21806 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21809 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21812 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21815 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21819 return std::make_pair(Opc, NeedSplit);
21823 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21824 const X86Subtarget *Subtarget) {
21826 SDValue Cond = N->getOperand(0);
21827 SDValue LHS = N->getOperand(1);
21828 SDValue RHS = N->getOperand(2);
21830 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21831 SDValue CondSrc = Cond->getOperand(0);
21832 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21833 Cond = CondSrc->getOperand(0);
21836 MVT VT = N->getSimpleValueType(0);
21837 MVT EltVT = VT.getVectorElementType();
21838 unsigned NumElems = VT.getVectorNumElements();
21839 // There is no blend with immediate in AVX-512.
21840 if (VT.is512BitVector())
21843 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21845 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21848 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21851 // A vselect where all conditions and data are constants can be optimized into
21852 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21853 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21854 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21857 unsigned MaskValue = 0;
21858 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21861 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21862 for (unsigned i = 0; i < NumElems; ++i) {
21863 // Be sure we emit undef where we can.
21864 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21865 ShuffleMask[i] = -1;
21867 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21870 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21873 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21875 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21876 TargetLowering::DAGCombinerInfo &DCI,
21877 const X86Subtarget *Subtarget) {
21879 SDValue Cond = N->getOperand(0);
21880 // Get the LHS/RHS of the select.
21881 SDValue LHS = N->getOperand(1);
21882 SDValue RHS = N->getOperand(2);
21883 EVT VT = LHS.getValueType();
21884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21886 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21887 // instructions match the semantics of the common C idiom x<y?x:y but not
21888 // x<=y?x:y, because of how they handle negative zero (which can be
21889 // ignored in unsafe-math mode).
21890 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21891 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21892 (Subtarget->hasSSE2() ||
21893 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21894 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21896 unsigned Opcode = 0;
21897 // Check for x CC y ? x : y.
21898 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21899 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21903 // Converting this to a min would handle NaNs incorrectly, and swapping
21904 // the operands would cause it to handle comparisons between positive
21905 // and negative zero incorrectly.
21906 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21907 if (!DAG.getTarget().Options.UnsafeFPMath &&
21908 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21910 std::swap(LHS, RHS);
21912 Opcode = X86ISD::FMIN;
21915 // Converting this to a min would handle comparisons between positive
21916 // and negative zero incorrectly.
21917 if (!DAG.getTarget().Options.UnsafeFPMath &&
21918 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21920 Opcode = X86ISD::FMIN;
21923 // Converting this to a min would handle both negative zeros and NaNs
21924 // incorrectly, but we can swap the operands to fix both.
21925 std::swap(LHS, RHS);
21929 Opcode = X86ISD::FMIN;
21933 // Converting this to a max would handle comparisons between positive
21934 // and negative zero incorrectly.
21935 if (!DAG.getTarget().Options.UnsafeFPMath &&
21936 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21938 Opcode = X86ISD::FMAX;
21941 // Converting this to a max would handle NaNs incorrectly, and swapping
21942 // the operands would cause it to handle comparisons between positive
21943 // and negative zero incorrectly.
21944 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21945 if (!DAG.getTarget().Options.UnsafeFPMath &&
21946 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21948 std::swap(LHS, RHS);
21950 Opcode = X86ISD::FMAX;
21953 // Converting this to a max would handle both negative zeros and NaNs
21954 // incorrectly, but we can swap the operands to fix both.
21955 std::swap(LHS, RHS);
21959 Opcode = X86ISD::FMAX;
21962 // Check for x CC y ? y : x -- a min/max with reversed arms.
21963 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21964 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21968 // Converting this to a min would handle comparisons between positive
21969 // and negative zero incorrectly, and swapping the operands would
21970 // cause it to handle NaNs incorrectly.
21971 if (!DAG.getTarget().Options.UnsafeFPMath &&
21972 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21973 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21975 std::swap(LHS, RHS);
21977 Opcode = X86ISD::FMIN;
21980 // Converting this to a min would handle NaNs incorrectly.
21981 if (!DAG.getTarget().Options.UnsafeFPMath &&
21982 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21984 Opcode = X86ISD::FMIN;
21987 // Converting this to a min would handle both negative zeros and NaNs
21988 // incorrectly, but we can swap the operands to fix both.
21989 std::swap(LHS, RHS);
21993 Opcode = X86ISD::FMIN;
21997 // Converting this to a max would handle NaNs incorrectly.
21998 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22000 Opcode = X86ISD::FMAX;
22003 // Converting this to a max would handle comparisons between positive
22004 // and negative zero incorrectly, and swapping the operands would
22005 // cause it to handle NaNs incorrectly.
22006 if (!DAG.getTarget().Options.UnsafeFPMath &&
22007 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22008 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22010 std::swap(LHS, RHS);
22012 Opcode = X86ISD::FMAX;
22015 // Converting this to a max would handle both negative zeros and NaNs
22016 // incorrectly, but we can swap the operands to fix both.
22017 std::swap(LHS, RHS);
22021 Opcode = X86ISD::FMAX;
22027 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22030 EVT CondVT = Cond.getValueType();
22031 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22032 CondVT.getVectorElementType() == MVT::i1) {
22033 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22034 // lowering on KNL. In this case we convert it to
22035 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22036 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22037 // Since SKX these selects have a proper lowering.
22038 EVT OpVT = LHS.getValueType();
22039 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22040 (OpVT.getVectorElementType() == MVT::i8 ||
22041 OpVT.getVectorElementType() == MVT::i16) &&
22042 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22043 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22044 DCI.AddToWorklist(Cond.getNode());
22045 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22048 // If this is a select between two integer constants, try to do some
22050 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22051 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22052 // Don't do this for crazy integer types.
22053 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22054 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22055 // so that TrueC (the true value) is larger than FalseC.
22056 bool NeedsCondInvert = false;
22058 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22059 // Efficiently invertible.
22060 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22061 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22062 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22063 NeedsCondInvert = true;
22064 std::swap(TrueC, FalseC);
22067 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22068 if (FalseC->getAPIntValue() == 0 &&
22069 TrueC->getAPIntValue().isPowerOf2()) {
22070 if (NeedsCondInvert) // Invert the condition if needed.
22071 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22072 DAG.getConstant(1, Cond.getValueType()));
22074 // Zero extend the condition if needed.
22075 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22077 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22078 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22079 DAG.getConstant(ShAmt, MVT::i8));
22082 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22083 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22084 if (NeedsCondInvert) // Invert the condition if needed.
22085 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22086 DAG.getConstant(1, Cond.getValueType()));
22088 // Zero extend the condition if needed.
22089 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22090 FalseC->getValueType(0), Cond);
22091 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22092 SDValue(FalseC, 0));
22095 // Optimize cases that will turn into an LEA instruction. This requires
22096 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22097 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22098 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22099 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22101 bool isFastMultiplier = false;
22103 switch ((unsigned char)Diff) {
22105 case 1: // result = add base, cond
22106 case 2: // result = lea base( , cond*2)
22107 case 3: // result = lea base(cond, cond*2)
22108 case 4: // result = lea base( , cond*4)
22109 case 5: // result = lea base(cond, cond*4)
22110 case 8: // result = lea base( , cond*8)
22111 case 9: // result = lea base(cond, cond*8)
22112 isFastMultiplier = true;
22117 if (isFastMultiplier) {
22118 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22119 if (NeedsCondInvert) // Invert the condition if needed.
22120 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22121 DAG.getConstant(1, Cond.getValueType()));
22123 // Zero extend the condition if needed.
22124 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22126 // Scale the condition by the difference.
22128 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22129 DAG.getConstant(Diff, Cond.getValueType()));
22131 // Add the base if non-zero.
22132 if (FalseC->getAPIntValue() != 0)
22133 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22134 SDValue(FalseC, 0));
22141 // Canonicalize max and min:
22142 // (x > y) ? x : y -> (x >= y) ? x : y
22143 // (x < y) ? x : y -> (x <= y) ? x : y
22144 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22145 // the need for an extra compare
22146 // against zero. e.g.
22147 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22149 // testl %edi, %edi
22151 // cmovgl %edi, %eax
22155 // cmovsl %eax, %edi
22156 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22157 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22158 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22159 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22164 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22165 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22166 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22167 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22172 // Early exit check
22173 if (!TLI.isTypeLegal(VT))
22176 // Match VSELECTs into subs with unsigned saturation.
22177 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22178 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22179 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22180 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22181 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22183 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22184 // left side invert the predicate to simplify logic below.
22186 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22188 CC = ISD::getSetCCInverse(CC, true);
22189 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22193 if (Other.getNode() && Other->getNumOperands() == 2 &&
22194 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22195 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22196 SDValue CondRHS = Cond->getOperand(1);
22198 // Look for a general sub with unsigned saturation first.
22199 // x >= y ? x-y : 0 --> subus x, y
22200 // x > y ? x-y : 0 --> subus x, y
22201 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22202 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22203 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22205 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22206 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22207 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22208 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22209 // If the RHS is a constant we have to reverse the const
22210 // canonicalization.
22211 // x > C-1 ? x+-C : 0 --> subus x, C
22212 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22213 CondRHSConst->getAPIntValue() ==
22214 (-OpRHSConst->getAPIntValue() - 1))
22215 return DAG.getNode(
22216 X86ISD::SUBUS, DL, VT, OpLHS,
22217 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22219 // Another special case: If C was a sign bit, the sub has been
22220 // canonicalized into a xor.
22221 // FIXME: Would it be better to use computeKnownBits to determine
22222 // whether it's safe to decanonicalize the xor?
22223 // x s< 0 ? x^C : 0 --> subus x, C
22224 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22225 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22226 OpRHSConst->getAPIntValue().isSignBit())
22227 // Note that we have to rebuild the RHS constant here to ensure we
22228 // don't rely on particular values of undef lanes.
22229 return DAG.getNode(
22230 X86ISD::SUBUS, DL, VT, OpLHS,
22231 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22236 // Try to match a min/max vector operation.
22237 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22238 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22239 unsigned Opc = ret.first;
22240 bool NeedSplit = ret.second;
22242 if (Opc && NeedSplit) {
22243 unsigned NumElems = VT.getVectorNumElements();
22244 // Extract the LHS vectors
22245 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22246 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22248 // Extract the RHS vectors
22249 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22250 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22252 // Create min/max for each subvector
22253 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22254 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22256 // Merge the result
22257 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22259 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22262 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22263 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22264 // Check if SETCC has already been promoted
22265 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22266 // Check that condition value type matches vselect operand type
22269 assert(Cond.getValueType().isVector() &&
22270 "vector select expects a vector selector!");
22272 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22273 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22275 if (!TValIsAllOnes && !FValIsAllZeros) {
22276 // Try invert the condition if true value is not all 1s and false value
22278 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22279 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22281 if (TValIsAllZeros || FValIsAllOnes) {
22282 SDValue CC = Cond.getOperand(2);
22283 ISD::CondCode NewCC =
22284 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22285 Cond.getOperand(0).getValueType().isInteger());
22286 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22287 std::swap(LHS, RHS);
22288 TValIsAllOnes = FValIsAllOnes;
22289 FValIsAllZeros = TValIsAllZeros;
22293 if (TValIsAllOnes || FValIsAllZeros) {
22296 if (TValIsAllOnes && FValIsAllZeros)
22298 else if (TValIsAllOnes)
22299 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22300 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22301 else if (FValIsAllZeros)
22302 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22303 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22305 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22309 // Try to fold this VSELECT into a MOVSS/MOVSD
22310 if (N->getOpcode() == ISD::VSELECT &&
22311 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22312 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22313 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22314 bool CanFold = false;
22315 unsigned NumElems = Cond.getNumOperands();
22319 if (isZero(Cond.getOperand(0))) {
22322 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22323 // fold (vselect <0,-1> -> (movsd A, B)
22324 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22325 CanFold = isAllOnes(Cond.getOperand(i));
22326 } else if (isAllOnes(Cond.getOperand(0))) {
22330 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22331 // fold (vselect <-1,0> -> (movsd B, A)
22332 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22333 CanFold = isZero(Cond.getOperand(i));
22337 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22338 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22339 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22342 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22343 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22344 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22345 // (v2i64 (bitcast B)))))
22347 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22348 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22349 // (v2f64 (bitcast B)))))
22351 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22352 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22353 // (v2i64 (bitcast A)))))
22355 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22356 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22357 // (v2f64 (bitcast A)))))
22359 CanFold = (isZero(Cond.getOperand(0)) &&
22360 isZero(Cond.getOperand(1)) &&
22361 isAllOnes(Cond.getOperand(2)) &&
22362 isAllOnes(Cond.getOperand(3)));
22364 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22365 isAllOnes(Cond.getOperand(1)) &&
22366 isZero(Cond.getOperand(2)) &&
22367 isZero(Cond.getOperand(3))) {
22369 std::swap(LHS, RHS);
22373 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22374 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22375 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22376 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22378 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22384 // If we know that this node is legal then we know that it is going to be
22385 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22386 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22387 // to simplify previous instructions.
22388 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22389 !DCI.isBeforeLegalize() &&
22390 // We explicitly check against v8i16 and v16i16 because, although
22391 // they're marked as Custom, they might only be legal when Cond is a
22392 // build_vector of constants. This will be taken care in a later
22394 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22395 VT != MVT::v8i16)) {
22396 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22398 // Don't optimize vector selects that map to mask-registers.
22402 // Check all uses of that condition operand to check whether it will be
22403 // consumed by non-BLEND instructions, which may depend on all bits are set
22405 for (SDNode::use_iterator I = Cond->use_begin(),
22406 E = Cond->use_end(); I != E; ++I)
22407 if (I->getOpcode() != ISD::VSELECT)
22408 // TODO: Add other opcodes eventually lowered into BLEND.
22411 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22412 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22414 APInt KnownZero, KnownOne;
22415 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22416 DCI.isBeforeLegalizeOps());
22417 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22418 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22419 DCI.CommitTargetLoweringOpt(TLO);
22422 // We should generate an X86ISD::BLENDI from a vselect if its argument
22423 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22424 // constants. This specific pattern gets generated when we split a
22425 // selector for a 512 bit vector in a machine without AVX512 (but with
22426 // 256-bit vectors), during legalization:
22428 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22430 // Iff we find this pattern and the build_vectors are built from
22431 // constants, we translate the vselect into a shuffle_vector that we
22432 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22433 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22434 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22435 if (Shuffle.getNode())
22442 // Check whether a boolean test is testing a boolean value generated by
22443 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22446 // Simplify the following patterns:
22447 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22448 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22449 // to (Op EFLAGS Cond)
22451 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22452 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22453 // to (Op EFLAGS !Cond)
22455 // where Op could be BRCOND or CMOV.
22457 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22458 // Quit if not CMP and SUB with its value result used.
22459 if (Cmp.getOpcode() != X86ISD::CMP &&
22460 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22463 // Quit if not used as a boolean value.
22464 if (CC != X86::COND_E && CC != X86::COND_NE)
22467 // Check CMP operands. One of them should be 0 or 1 and the other should be
22468 // an SetCC or extended from it.
22469 SDValue Op1 = Cmp.getOperand(0);
22470 SDValue Op2 = Cmp.getOperand(1);
22473 const ConstantSDNode* C = nullptr;
22474 bool needOppositeCond = (CC == X86::COND_E);
22475 bool checkAgainstTrue = false; // Is it a comparison against 1?
22477 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22479 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22481 else // Quit if all operands are not constants.
22484 if (C->getZExtValue() == 1) {
22485 needOppositeCond = !needOppositeCond;
22486 checkAgainstTrue = true;
22487 } else if (C->getZExtValue() != 0)
22488 // Quit if the constant is neither 0 or 1.
22491 bool truncatedToBoolWithAnd = false;
22492 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22493 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22494 SetCC.getOpcode() == ISD::TRUNCATE ||
22495 SetCC.getOpcode() == ISD::AND) {
22496 if (SetCC.getOpcode() == ISD::AND) {
22498 ConstantSDNode *CS;
22499 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22500 CS->getZExtValue() == 1)
22502 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22503 CS->getZExtValue() == 1)
22507 SetCC = SetCC.getOperand(OpIdx);
22508 truncatedToBoolWithAnd = true;
22510 SetCC = SetCC.getOperand(0);
22513 switch (SetCC.getOpcode()) {
22514 case X86ISD::SETCC_CARRY:
22515 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22516 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22517 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22518 // truncated to i1 using 'and'.
22519 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22521 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22522 "Invalid use of SETCC_CARRY!");
22524 case X86ISD::SETCC:
22525 // Set the condition code or opposite one if necessary.
22526 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22527 if (needOppositeCond)
22528 CC = X86::GetOppositeBranchCondition(CC);
22529 return SetCC.getOperand(1);
22530 case X86ISD::CMOV: {
22531 // Check whether false/true value has canonical one, i.e. 0 or 1.
22532 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22533 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22534 // Quit if true value is not a constant.
22537 // Quit if false value is not a constant.
22539 SDValue Op = SetCC.getOperand(0);
22540 // Skip 'zext' or 'trunc' node.
22541 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22542 Op.getOpcode() == ISD::TRUNCATE)
22543 Op = Op.getOperand(0);
22544 // A special case for rdrand/rdseed, where 0 is set if false cond is
22546 if ((Op.getOpcode() != X86ISD::RDRAND &&
22547 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22550 // Quit if false value is not the constant 0 or 1.
22551 bool FValIsFalse = true;
22552 if (FVal && FVal->getZExtValue() != 0) {
22553 if (FVal->getZExtValue() != 1)
22555 // If FVal is 1, opposite cond is needed.
22556 needOppositeCond = !needOppositeCond;
22557 FValIsFalse = false;
22559 // Quit if TVal is not the constant opposite of FVal.
22560 if (FValIsFalse && TVal->getZExtValue() != 1)
22562 if (!FValIsFalse && TVal->getZExtValue() != 0)
22564 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22565 if (needOppositeCond)
22566 CC = X86::GetOppositeBranchCondition(CC);
22567 return SetCC.getOperand(3);
22574 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22575 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22576 TargetLowering::DAGCombinerInfo &DCI,
22577 const X86Subtarget *Subtarget) {
22580 // If the flag operand isn't dead, don't touch this CMOV.
22581 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22584 SDValue FalseOp = N->getOperand(0);
22585 SDValue TrueOp = N->getOperand(1);
22586 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22587 SDValue Cond = N->getOperand(3);
22589 if (CC == X86::COND_E || CC == X86::COND_NE) {
22590 switch (Cond.getOpcode()) {
22594 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22595 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22596 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22602 Flags = checkBoolTestSetCCCombine(Cond, CC);
22603 if (Flags.getNode() &&
22604 // Extra check as FCMOV only supports a subset of X86 cond.
22605 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22606 SDValue Ops[] = { FalseOp, TrueOp,
22607 DAG.getConstant(CC, MVT::i8), Flags };
22608 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22611 // If this is a select between two integer constants, try to do some
22612 // optimizations. Note that the operands are ordered the opposite of SELECT
22614 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22615 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22616 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22617 // larger than FalseC (the false value).
22618 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22619 CC = X86::GetOppositeBranchCondition(CC);
22620 std::swap(TrueC, FalseC);
22621 std::swap(TrueOp, FalseOp);
22624 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22625 // This is efficient for any integer data type (including i8/i16) and
22627 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22628 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22629 DAG.getConstant(CC, MVT::i8), Cond);
22631 // Zero extend the condition if needed.
22632 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22634 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22635 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22636 DAG.getConstant(ShAmt, MVT::i8));
22637 if (N->getNumValues() == 2) // Dead flag value?
22638 return DCI.CombineTo(N, Cond, SDValue());
22642 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22643 // for any integer data type, including i8/i16.
22644 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22645 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22646 DAG.getConstant(CC, MVT::i8), Cond);
22648 // Zero extend the condition if needed.
22649 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22650 FalseC->getValueType(0), Cond);
22651 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22652 SDValue(FalseC, 0));
22654 if (N->getNumValues() == 2) // Dead flag value?
22655 return DCI.CombineTo(N, Cond, SDValue());
22659 // Optimize cases that will turn into an LEA instruction. This requires
22660 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22661 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22662 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22663 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22665 bool isFastMultiplier = false;
22667 switch ((unsigned char)Diff) {
22669 case 1: // result = add base, cond
22670 case 2: // result = lea base( , cond*2)
22671 case 3: // result = lea base(cond, cond*2)
22672 case 4: // result = lea base( , cond*4)
22673 case 5: // result = lea base(cond, cond*4)
22674 case 8: // result = lea base( , cond*8)
22675 case 9: // result = lea base(cond, cond*8)
22676 isFastMultiplier = true;
22681 if (isFastMultiplier) {
22682 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22683 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22684 DAG.getConstant(CC, MVT::i8), Cond);
22685 // Zero extend the condition if needed.
22686 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22688 // Scale the condition by the difference.
22690 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22691 DAG.getConstant(Diff, Cond.getValueType()));
22693 // Add the base if non-zero.
22694 if (FalseC->getAPIntValue() != 0)
22695 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22696 SDValue(FalseC, 0));
22697 if (N->getNumValues() == 2) // Dead flag value?
22698 return DCI.CombineTo(N, Cond, SDValue());
22705 // Handle these cases:
22706 // (select (x != c), e, c) -> select (x != c), e, x),
22707 // (select (x == c), c, e) -> select (x == c), x, e)
22708 // where the c is an integer constant, and the "select" is the combination
22709 // of CMOV and CMP.
22711 // The rationale for this change is that the conditional-move from a constant
22712 // needs two instructions, however, conditional-move from a register needs
22713 // only one instruction.
22715 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22716 // some instruction-combining opportunities. This opt needs to be
22717 // postponed as late as possible.
22719 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22720 // the DCI.xxxx conditions are provided to postpone the optimization as
22721 // late as possible.
22723 ConstantSDNode *CmpAgainst = nullptr;
22724 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22725 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22726 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22728 if (CC == X86::COND_NE &&
22729 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22730 CC = X86::GetOppositeBranchCondition(CC);
22731 std::swap(TrueOp, FalseOp);
22734 if (CC == X86::COND_E &&
22735 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22736 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22737 DAG.getConstant(CC, MVT::i8), Cond };
22738 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22746 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22747 const X86Subtarget *Subtarget) {
22748 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22750 default: return SDValue();
22751 // SSE/AVX/AVX2 blend intrinsics.
22752 case Intrinsic::x86_avx2_pblendvb:
22753 case Intrinsic::x86_avx2_pblendw:
22754 case Intrinsic::x86_avx2_pblendd_128:
22755 case Intrinsic::x86_avx2_pblendd_256:
22756 // Don't try to simplify this intrinsic if we don't have AVX2.
22757 if (!Subtarget->hasAVX2())
22760 case Intrinsic::x86_avx_blend_pd_256:
22761 case Intrinsic::x86_avx_blend_ps_256:
22762 case Intrinsic::x86_avx_blendv_pd_256:
22763 case Intrinsic::x86_avx_blendv_ps_256:
22764 // Don't try to simplify this intrinsic if we don't have AVX.
22765 if (!Subtarget->hasAVX())
22768 case Intrinsic::x86_sse41_pblendw:
22769 case Intrinsic::x86_sse41_blendpd:
22770 case Intrinsic::x86_sse41_blendps:
22771 case Intrinsic::x86_sse41_blendvps:
22772 case Intrinsic::x86_sse41_blendvpd:
22773 case Intrinsic::x86_sse41_pblendvb: {
22774 SDValue Op0 = N->getOperand(1);
22775 SDValue Op1 = N->getOperand(2);
22776 SDValue Mask = N->getOperand(3);
22778 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22779 if (!Subtarget->hasSSE41())
22782 // fold (blend A, A, Mask) -> A
22785 // fold (blend A, B, allZeros) -> A
22786 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22788 // fold (blend A, B, allOnes) -> B
22789 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22792 // Simplify the case where the mask is a constant i32 value.
22793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22794 if (C->isNullValue())
22796 if (C->isAllOnesValue())
22803 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22804 case Intrinsic::x86_sse2_psrai_w:
22805 case Intrinsic::x86_sse2_psrai_d:
22806 case Intrinsic::x86_avx2_psrai_w:
22807 case Intrinsic::x86_avx2_psrai_d:
22808 case Intrinsic::x86_sse2_psra_w:
22809 case Intrinsic::x86_sse2_psra_d:
22810 case Intrinsic::x86_avx2_psra_w:
22811 case Intrinsic::x86_avx2_psra_d: {
22812 SDValue Op0 = N->getOperand(1);
22813 SDValue Op1 = N->getOperand(2);
22814 EVT VT = Op0.getValueType();
22815 assert(VT.isVector() && "Expected a vector type!");
22817 if (isa<BuildVectorSDNode>(Op1))
22818 Op1 = Op1.getOperand(0);
22820 if (!isa<ConstantSDNode>(Op1))
22823 EVT SVT = VT.getVectorElementType();
22824 unsigned SVTBits = SVT.getSizeInBits();
22826 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22827 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22828 uint64_t ShAmt = C.getZExtValue();
22830 // Don't try to convert this shift into a ISD::SRA if the shift
22831 // count is bigger than or equal to the element size.
22832 if (ShAmt >= SVTBits)
22835 // Trivial case: if the shift count is zero, then fold this
22836 // into the first operand.
22840 // Replace this packed shift intrinsic with a target independent
22842 SDValue Splat = DAG.getConstant(C, VT);
22843 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22848 /// PerformMulCombine - Optimize a single multiply with constant into two
22849 /// in order to implement it with two cheaper instructions, e.g.
22850 /// LEA + SHL, LEA + LEA.
22851 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22852 TargetLowering::DAGCombinerInfo &DCI) {
22853 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22856 EVT VT = N->getValueType(0);
22857 if (VT != MVT::i64)
22860 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22863 uint64_t MulAmt = C->getZExtValue();
22864 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22867 uint64_t MulAmt1 = 0;
22868 uint64_t MulAmt2 = 0;
22869 if ((MulAmt % 9) == 0) {
22871 MulAmt2 = MulAmt / 9;
22872 } else if ((MulAmt % 5) == 0) {
22874 MulAmt2 = MulAmt / 5;
22875 } else if ((MulAmt % 3) == 0) {
22877 MulAmt2 = MulAmt / 3;
22880 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22883 if (isPowerOf2_64(MulAmt2) &&
22884 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22885 // If second multiplifer is pow2, issue it first. We want the multiply by
22886 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22888 std::swap(MulAmt1, MulAmt2);
22891 if (isPowerOf2_64(MulAmt1))
22892 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22893 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22895 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22896 DAG.getConstant(MulAmt1, VT));
22898 if (isPowerOf2_64(MulAmt2))
22899 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22900 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22902 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22903 DAG.getConstant(MulAmt2, VT));
22905 // Do not add new nodes to DAG combiner worklist.
22906 DCI.CombineTo(N, NewMul, false);
22911 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22912 SDValue N0 = N->getOperand(0);
22913 SDValue N1 = N->getOperand(1);
22914 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22915 EVT VT = N0.getValueType();
22917 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22918 // since the result of setcc_c is all zero's or all ones.
22919 if (VT.isInteger() && !VT.isVector() &&
22920 N1C && N0.getOpcode() == ISD::AND &&
22921 N0.getOperand(1).getOpcode() == ISD::Constant) {
22922 SDValue N00 = N0.getOperand(0);
22923 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22924 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22925 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22926 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22927 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22928 APInt ShAmt = N1C->getAPIntValue();
22929 Mask = Mask.shl(ShAmt);
22931 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22932 N00, DAG.getConstant(Mask, VT));
22936 // Hardware support for vector shifts is sparse which makes us scalarize the
22937 // vector operations in many cases. Also, on sandybridge ADD is faster than
22939 // (shl V, 1) -> add V,V
22940 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22941 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22942 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22943 // We shift all of the values by one. In many cases we do not have
22944 // hardware support for this operation. This is better expressed as an ADD
22946 if (N1SplatC->getZExtValue() == 1)
22947 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22953 /// \brief Returns a vector of 0s if the node in input is a vector logical
22954 /// shift by a constant amount which is known to be bigger than or equal
22955 /// to the vector element size in bits.
22956 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22957 const X86Subtarget *Subtarget) {
22958 EVT VT = N->getValueType(0);
22960 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22961 (!Subtarget->hasInt256() ||
22962 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22965 SDValue Amt = N->getOperand(1);
22967 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22968 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22969 APInt ShiftAmt = AmtSplat->getAPIntValue();
22970 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22972 // SSE2/AVX2 logical shifts always return a vector of 0s
22973 // if the shift amount is bigger than or equal to
22974 // the element size. The constant shift amount will be
22975 // encoded as a 8-bit immediate.
22976 if (ShiftAmt.trunc(8).uge(MaxAmount))
22977 return getZeroVector(VT, Subtarget, DAG, DL);
22983 /// PerformShiftCombine - Combine shifts.
22984 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22985 TargetLowering::DAGCombinerInfo &DCI,
22986 const X86Subtarget *Subtarget) {
22987 if (N->getOpcode() == ISD::SHL) {
22988 SDValue V = PerformSHLCombine(N, DAG);
22989 if (V.getNode()) return V;
22992 if (N->getOpcode() != ISD::SRA) {
22993 // Try to fold this logical shift into a zero vector.
22994 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22995 if (V.getNode()) return V;
23001 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23002 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23003 // and friends. Likewise for OR -> CMPNEQSS.
23004 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23005 TargetLowering::DAGCombinerInfo &DCI,
23006 const X86Subtarget *Subtarget) {
23009 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23010 // we're requiring SSE2 for both.
23011 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23012 SDValue N0 = N->getOperand(0);
23013 SDValue N1 = N->getOperand(1);
23014 SDValue CMP0 = N0->getOperand(1);
23015 SDValue CMP1 = N1->getOperand(1);
23018 // The SETCCs should both refer to the same CMP.
23019 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23022 SDValue CMP00 = CMP0->getOperand(0);
23023 SDValue CMP01 = CMP0->getOperand(1);
23024 EVT VT = CMP00.getValueType();
23026 if (VT == MVT::f32 || VT == MVT::f64) {
23027 bool ExpectingFlags = false;
23028 // Check for any users that want flags:
23029 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23030 !ExpectingFlags && UI != UE; ++UI)
23031 switch (UI->getOpcode()) {
23036 ExpectingFlags = true;
23038 case ISD::CopyToReg:
23039 case ISD::SIGN_EXTEND:
23040 case ISD::ZERO_EXTEND:
23041 case ISD::ANY_EXTEND:
23045 if (!ExpectingFlags) {
23046 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23047 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23049 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23050 X86::CondCode tmp = cc0;
23055 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23056 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23057 // FIXME: need symbolic constants for these magic numbers.
23058 // See X86ATTInstPrinter.cpp:printSSECC().
23059 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23060 if (Subtarget->hasAVX512()) {
23061 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23062 CMP01, DAG.getConstant(x86cc, MVT::i8));
23063 if (N->getValueType(0) != MVT::i1)
23064 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23068 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23069 CMP00.getValueType(), CMP00, CMP01,
23070 DAG.getConstant(x86cc, MVT::i8));
23072 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23073 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23075 if (is64BitFP && !Subtarget->is64Bit()) {
23076 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23077 // 64-bit integer, since that's not a legal type. Since
23078 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23079 // bits, but can do this little dance to extract the lowest 32 bits
23080 // and work with those going forward.
23081 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23083 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23085 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23086 Vector32, DAG.getIntPtrConstant(0));
23090 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23091 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23092 DAG.getConstant(1, IntVT));
23093 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23094 return OneBitOfTruth;
23102 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23103 /// so it can be folded inside ANDNP.
23104 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23105 EVT VT = N->getValueType(0);
23107 // Match direct AllOnes for 128 and 256-bit vectors
23108 if (ISD::isBuildVectorAllOnes(N))
23111 // Look through a bit convert.
23112 if (N->getOpcode() == ISD::BITCAST)
23113 N = N->getOperand(0).getNode();
23115 // Sometimes the operand may come from a insert_subvector building a 256-bit
23117 if (VT.is256BitVector() &&
23118 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23119 SDValue V1 = N->getOperand(0);
23120 SDValue V2 = N->getOperand(1);
23122 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23123 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23124 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23125 ISD::isBuildVectorAllOnes(V2.getNode()))
23132 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23133 // register. In most cases we actually compare or select YMM-sized registers
23134 // and mixing the two types creates horrible code. This method optimizes
23135 // some of the transition sequences.
23136 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23137 TargetLowering::DAGCombinerInfo &DCI,
23138 const X86Subtarget *Subtarget) {
23139 EVT VT = N->getValueType(0);
23140 if (!VT.is256BitVector())
23143 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23144 N->getOpcode() == ISD::ZERO_EXTEND ||
23145 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23147 SDValue Narrow = N->getOperand(0);
23148 EVT NarrowVT = Narrow->getValueType(0);
23149 if (!NarrowVT.is128BitVector())
23152 if (Narrow->getOpcode() != ISD::XOR &&
23153 Narrow->getOpcode() != ISD::AND &&
23154 Narrow->getOpcode() != ISD::OR)
23157 SDValue N0 = Narrow->getOperand(0);
23158 SDValue N1 = Narrow->getOperand(1);
23161 // The Left side has to be a trunc.
23162 if (N0.getOpcode() != ISD::TRUNCATE)
23165 // The type of the truncated inputs.
23166 EVT WideVT = N0->getOperand(0)->getValueType(0);
23170 // The right side has to be a 'trunc' or a constant vector.
23171 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23172 ConstantSDNode *RHSConstSplat = nullptr;
23173 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23174 RHSConstSplat = RHSBV->getConstantSplatNode();
23175 if (!RHSTrunc && !RHSConstSplat)
23178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23180 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23183 // Set N0 and N1 to hold the inputs to the new wide operation.
23184 N0 = N0->getOperand(0);
23185 if (RHSConstSplat) {
23186 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23187 SDValue(RHSConstSplat, 0));
23188 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23189 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23190 } else if (RHSTrunc) {
23191 N1 = N1->getOperand(0);
23194 // Generate the wide operation.
23195 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23196 unsigned Opcode = N->getOpcode();
23198 case ISD::ANY_EXTEND:
23200 case ISD::ZERO_EXTEND: {
23201 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23202 APInt Mask = APInt::getAllOnesValue(InBits);
23203 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23204 return DAG.getNode(ISD::AND, DL, VT,
23205 Op, DAG.getConstant(Mask, VT));
23207 case ISD::SIGN_EXTEND:
23208 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23209 Op, DAG.getValueType(NarrowVT));
23211 llvm_unreachable("Unexpected opcode");
23215 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23216 TargetLowering::DAGCombinerInfo &DCI,
23217 const X86Subtarget *Subtarget) {
23218 EVT VT = N->getValueType(0);
23219 if (DCI.isBeforeLegalizeOps())
23222 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23226 // Create BEXTR instructions
23227 // BEXTR is ((X >> imm) & (2**size-1))
23228 if (VT == MVT::i32 || VT == MVT::i64) {
23229 SDValue N0 = N->getOperand(0);
23230 SDValue N1 = N->getOperand(1);
23233 // Check for BEXTR.
23234 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23235 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23236 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23237 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23238 if (MaskNode && ShiftNode) {
23239 uint64_t Mask = MaskNode->getZExtValue();
23240 uint64_t Shift = ShiftNode->getZExtValue();
23241 if (isMask_64(Mask)) {
23242 uint64_t MaskSize = CountPopulation_64(Mask);
23243 if (Shift + MaskSize <= VT.getSizeInBits())
23244 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23245 DAG.getConstant(Shift | (MaskSize << 8), VT));
23253 // Want to form ANDNP nodes:
23254 // 1) In the hopes of then easily combining them with OR and AND nodes
23255 // to form PBLEND/PSIGN.
23256 // 2) To match ANDN packed intrinsics
23257 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23260 SDValue N0 = N->getOperand(0);
23261 SDValue N1 = N->getOperand(1);
23264 // Check LHS for vnot
23265 if (N0.getOpcode() == ISD::XOR &&
23266 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23267 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23268 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23270 // Check RHS for vnot
23271 if (N1.getOpcode() == ISD::XOR &&
23272 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23273 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23274 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23279 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23280 TargetLowering::DAGCombinerInfo &DCI,
23281 const X86Subtarget *Subtarget) {
23282 if (DCI.isBeforeLegalizeOps())
23285 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23289 SDValue N0 = N->getOperand(0);
23290 SDValue N1 = N->getOperand(1);
23291 EVT VT = N->getValueType(0);
23293 // look for psign/blend
23294 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23295 if (!Subtarget->hasSSSE3() ||
23296 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23299 // Canonicalize pandn to RHS
23300 if (N0.getOpcode() == X86ISD::ANDNP)
23302 // or (and (m, y), (pandn m, x))
23303 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23304 SDValue Mask = N1.getOperand(0);
23305 SDValue X = N1.getOperand(1);
23307 if (N0.getOperand(0) == Mask)
23308 Y = N0.getOperand(1);
23309 if (N0.getOperand(1) == Mask)
23310 Y = N0.getOperand(0);
23312 // Check to see if the mask appeared in both the AND and ANDNP and
23316 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23317 // Look through mask bitcast.
23318 if (Mask.getOpcode() == ISD::BITCAST)
23319 Mask = Mask.getOperand(0);
23320 if (X.getOpcode() == ISD::BITCAST)
23321 X = X.getOperand(0);
23322 if (Y.getOpcode() == ISD::BITCAST)
23323 Y = Y.getOperand(0);
23325 EVT MaskVT = Mask.getValueType();
23327 // Validate that the Mask operand is a vector sra node.
23328 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23329 // there is no psrai.b
23330 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23331 unsigned SraAmt = ~0;
23332 if (Mask.getOpcode() == ISD::SRA) {
23333 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23334 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23335 SraAmt = AmtConst->getZExtValue();
23336 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23337 SDValue SraC = Mask.getOperand(1);
23338 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23340 if ((SraAmt + 1) != EltBits)
23345 // Now we know we at least have a plendvb with the mask val. See if
23346 // we can form a psignb/w/d.
23347 // psign = x.type == y.type == mask.type && y = sub(0, x);
23348 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23349 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23350 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23351 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23352 "Unsupported VT for PSIGN");
23353 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23354 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23356 // PBLENDVB only available on SSE 4.1
23357 if (!Subtarget->hasSSE41())
23360 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23362 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23363 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23364 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23365 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23366 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23370 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23373 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23374 MachineFunction &MF = DAG.getMachineFunction();
23375 bool OptForSize = MF.getFunction()->getAttributes().
23376 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23378 // SHLD/SHRD instructions have lower register pressure, but on some
23379 // platforms they have higher latency than the equivalent
23380 // series of shifts/or that would otherwise be generated.
23381 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23382 // have higher latencies and we are not optimizing for size.
23383 if (!OptForSize && Subtarget->isSHLDSlow())
23386 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23388 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23390 if (!N0.hasOneUse() || !N1.hasOneUse())
23393 SDValue ShAmt0 = N0.getOperand(1);
23394 if (ShAmt0.getValueType() != MVT::i8)
23396 SDValue ShAmt1 = N1.getOperand(1);
23397 if (ShAmt1.getValueType() != MVT::i8)
23399 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23400 ShAmt0 = ShAmt0.getOperand(0);
23401 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23402 ShAmt1 = ShAmt1.getOperand(0);
23405 unsigned Opc = X86ISD::SHLD;
23406 SDValue Op0 = N0.getOperand(0);
23407 SDValue Op1 = N1.getOperand(0);
23408 if (ShAmt0.getOpcode() == ISD::SUB) {
23409 Opc = X86ISD::SHRD;
23410 std::swap(Op0, Op1);
23411 std::swap(ShAmt0, ShAmt1);
23414 unsigned Bits = VT.getSizeInBits();
23415 if (ShAmt1.getOpcode() == ISD::SUB) {
23416 SDValue Sum = ShAmt1.getOperand(0);
23417 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23418 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23419 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23420 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23421 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23422 return DAG.getNode(Opc, DL, VT,
23424 DAG.getNode(ISD::TRUNCATE, DL,
23427 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23428 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23430 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23431 return DAG.getNode(Opc, DL, VT,
23432 N0.getOperand(0), N1.getOperand(0),
23433 DAG.getNode(ISD::TRUNCATE, DL,
23440 // Generate NEG and CMOV for integer abs.
23441 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23442 EVT VT = N->getValueType(0);
23444 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23445 // 8-bit integer abs to NEG and CMOV.
23446 if (VT.isInteger() && VT.getSizeInBits() == 8)
23449 SDValue N0 = N->getOperand(0);
23450 SDValue N1 = N->getOperand(1);
23453 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23454 // and change it to SUB and CMOV.
23455 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23456 N0.getOpcode() == ISD::ADD &&
23457 N0.getOperand(1) == N1 &&
23458 N1.getOpcode() == ISD::SRA &&
23459 N1.getOperand(0) == N0.getOperand(0))
23460 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23461 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23462 // Generate SUB & CMOV.
23463 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23464 DAG.getConstant(0, VT), N0.getOperand(0));
23466 SDValue Ops[] = { N0.getOperand(0), Neg,
23467 DAG.getConstant(X86::COND_GE, MVT::i8),
23468 SDValue(Neg.getNode(), 1) };
23469 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23474 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23475 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23476 TargetLowering::DAGCombinerInfo &DCI,
23477 const X86Subtarget *Subtarget) {
23478 if (DCI.isBeforeLegalizeOps())
23481 if (Subtarget->hasCMov()) {
23482 SDValue RV = performIntegerAbsCombine(N, DAG);
23490 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23491 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23492 TargetLowering::DAGCombinerInfo &DCI,
23493 const X86Subtarget *Subtarget) {
23494 LoadSDNode *Ld = cast<LoadSDNode>(N);
23495 EVT RegVT = Ld->getValueType(0);
23496 EVT MemVT = Ld->getMemoryVT();
23498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23500 // On Sandybridge unaligned 256bit loads are inefficient.
23501 ISD::LoadExtType Ext = Ld->getExtensionType();
23502 unsigned Alignment = Ld->getAlignment();
23503 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23504 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23505 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23506 unsigned NumElems = RegVT.getVectorNumElements();
23510 SDValue Ptr = Ld->getBasePtr();
23511 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23513 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23515 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23516 Ld->getPointerInfo(), Ld->isVolatile(),
23517 Ld->isNonTemporal(), Ld->isInvariant(),
23519 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23520 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23521 Ld->getPointerInfo(), Ld->isVolatile(),
23522 Ld->isNonTemporal(), Ld->isInvariant(),
23523 std::min(16U, Alignment));
23524 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23526 Load2.getValue(1));
23528 SDValue NewVec = DAG.getUNDEF(RegVT);
23529 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23530 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23531 return DCI.CombineTo(N, NewVec, TF, true);
23537 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23538 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23539 const X86Subtarget *Subtarget) {
23540 StoreSDNode *St = cast<StoreSDNode>(N);
23541 EVT VT = St->getValue().getValueType();
23542 EVT StVT = St->getMemoryVT();
23544 SDValue StoredVal = St->getOperand(1);
23545 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23547 // If we are saving a concatenation of two XMM registers, perform two stores.
23548 // On Sandy Bridge, 256-bit memory operations are executed by two
23549 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23550 // memory operation.
23551 unsigned Alignment = St->getAlignment();
23552 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23553 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23554 StVT == VT && !IsAligned) {
23555 unsigned NumElems = VT.getVectorNumElements();
23559 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23560 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23562 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23563 SDValue Ptr0 = St->getBasePtr();
23564 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23566 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23567 St->getPointerInfo(), St->isVolatile(),
23568 St->isNonTemporal(), Alignment);
23569 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23570 St->getPointerInfo(), St->isVolatile(),
23571 St->isNonTemporal(),
23572 std::min(16U, Alignment));
23573 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23576 // Optimize trunc store (of multiple scalars) to shuffle and store.
23577 // First, pack all of the elements in one place. Next, store to memory
23578 // in fewer chunks.
23579 if (St->isTruncatingStore() && VT.isVector()) {
23580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23581 unsigned NumElems = VT.getVectorNumElements();
23582 assert(StVT != VT && "Cannot truncate to the same type");
23583 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23584 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23586 // From, To sizes and ElemCount must be pow of two
23587 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23588 // We are going to use the original vector elt for storing.
23589 // Accumulated smaller vector elements must be a multiple of the store size.
23590 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23592 unsigned SizeRatio = FromSz / ToSz;
23594 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23596 // Create a type on which we perform the shuffle
23597 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23598 StVT.getScalarType(), NumElems*SizeRatio);
23600 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23602 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23603 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23604 for (unsigned i = 0; i != NumElems; ++i)
23605 ShuffleVec[i] = i * SizeRatio;
23607 // Can't shuffle using an illegal type.
23608 if (!TLI.isTypeLegal(WideVecVT))
23611 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23612 DAG.getUNDEF(WideVecVT),
23614 // At this point all of the data is stored at the bottom of the
23615 // register. We now need to save it to mem.
23617 // Find the largest store unit
23618 MVT StoreType = MVT::i8;
23619 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23620 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23621 MVT Tp = (MVT::SimpleValueType)tp;
23622 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23626 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23627 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23628 (64 <= NumElems * ToSz))
23629 StoreType = MVT::f64;
23631 // Bitcast the original vector into a vector of store-size units
23632 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23633 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23634 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23635 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23636 SmallVector<SDValue, 8> Chains;
23637 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23638 TLI.getPointerTy());
23639 SDValue Ptr = St->getBasePtr();
23641 // Perform one or more big stores into memory.
23642 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23643 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23644 StoreType, ShuffWide,
23645 DAG.getIntPtrConstant(i));
23646 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23647 St->getPointerInfo(), St->isVolatile(),
23648 St->isNonTemporal(), St->getAlignment());
23649 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23650 Chains.push_back(Ch);
23653 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23656 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23657 // the FP state in cases where an emms may be missing.
23658 // A preferable solution to the general problem is to figure out the right
23659 // places to insert EMMS. This qualifies as a quick hack.
23661 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23662 if (VT.getSizeInBits() != 64)
23665 const Function *F = DAG.getMachineFunction().getFunction();
23666 bool NoImplicitFloatOps = F->getAttributes().
23667 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23668 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23669 && Subtarget->hasSSE2();
23670 if ((VT.isVector() ||
23671 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23672 isa<LoadSDNode>(St->getValue()) &&
23673 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23674 St->getChain().hasOneUse() && !St->isVolatile()) {
23675 SDNode* LdVal = St->getValue().getNode();
23676 LoadSDNode *Ld = nullptr;
23677 int TokenFactorIndex = -1;
23678 SmallVector<SDValue, 8> Ops;
23679 SDNode* ChainVal = St->getChain().getNode();
23680 // Must be a store of a load. We currently handle two cases: the load
23681 // is a direct child, and it's under an intervening TokenFactor. It is
23682 // possible to dig deeper under nested TokenFactors.
23683 if (ChainVal == LdVal)
23684 Ld = cast<LoadSDNode>(St->getChain());
23685 else if (St->getValue().hasOneUse() &&
23686 ChainVal->getOpcode() == ISD::TokenFactor) {
23687 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23688 if (ChainVal->getOperand(i).getNode() == LdVal) {
23689 TokenFactorIndex = i;
23690 Ld = cast<LoadSDNode>(St->getValue());
23692 Ops.push_back(ChainVal->getOperand(i));
23696 if (!Ld || !ISD::isNormalLoad(Ld))
23699 // If this is not the MMX case, i.e. we are just turning i64 load/store
23700 // into f64 load/store, avoid the transformation if there are multiple
23701 // uses of the loaded value.
23702 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23707 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23708 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23710 if (Subtarget->is64Bit() || F64IsLegal) {
23711 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23712 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23713 Ld->getPointerInfo(), Ld->isVolatile(),
23714 Ld->isNonTemporal(), Ld->isInvariant(),
23715 Ld->getAlignment());
23716 SDValue NewChain = NewLd.getValue(1);
23717 if (TokenFactorIndex != -1) {
23718 Ops.push_back(NewChain);
23719 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23721 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23722 St->getPointerInfo(),
23723 St->isVolatile(), St->isNonTemporal(),
23724 St->getAlignment());
23727 // Otherwise, lower to two pairs of 32-bit loads / stores.
23728 SDValue LoAddr = Ld->getBasePtr();
23729 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23730 DAG.getConstant(4, MVT::i32));
23732 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23733 Ld->getPointerInfo(),
23734 Ld->isVolatile(), Ld->isNonTemporal(),
23735 Ld->isInvariant(), Ld->getAlignment());
23736 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23737 Ld->getPointerInfo().getWithOffset(4),
23738 Ld->isVolatile(), Ld->isNonTemporal(),
23740 MinAlign(Ld->getAlignment(), 4));
23742 SDValue NewChain = LoLd.getValue(1);
23743 if (TokenFactorIndex != -1) {
23744 Ops.push_back(LoLd);
23745 Ops.push_back(HiLd);
23746 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23749 LoAddr = St->getBasePtr();
23750 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23751 DAG.getConstant(4, MVT::i32));
23753 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23754 St->getPointerInfo(),
23755 St->isVolatile(), St->isNonTemporal(),
23756 St->getAlignment());
23757 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23758 St->getPointerInfo().getWithOffset(4),
23760 St->isNonTemporal(),
23761 MinAlign(St->getAlignment(), 4));
23762 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23767 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23768 /// and return the operands for the horizontal operation in LHS and RHS. A
23769 /// horizontal operation performs the binary operation on successive elements
23770 /// of its first operand, then on successive elements of its second operand,
23771 /// returning the resulting values in a vector. For example, if
23772 /// A = < float a0, float a1, float a2, float a3 >
23774 /// B = < float b0, float b1, float b2, float b3 >
23775 /// then the result of doing a horizontal operation on A and B is
23776 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23777 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23778 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23779 /// set to A, RHS to B, and the routine returns 'true'.
23780 /// Note that the binary operation should have the property that if one of the
23781 /// operands is UNDEF then the result is UNDEF.
23782 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23783 // Look for the following pattern: if
23784 // A = < float a0, float a1, float a2, float a3 >
23785 // B = < float b0, float b1, float b2, float b3 >
23787 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23788 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23789 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23790 // which is A horizontal-op B.
23792 // At least one of the operands should be a vector shuffle.
23793 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23794 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23797 MVT VT = LHS.getSimpleValueType();
23799 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23800 "Unsupported vector type for horizontal add/sub");
23802 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23803 // operate independently on 128-bit lanes.
23804 unsigned NumElts = VT.getVectorNumElements();
23805 unsigned NumLanes = VT.getSizeInBits()/128;
23806 unsigned NumLaneElts = NumElts / NumLanes;
23807 assert((NumLaneElts % 2 == 0) &&
23808 "Vector type should have an even number of elements in each lane");
23809 unsigned HalfLaneElts = NumLaneElts/2;
23811 // View LHS in the form
23812 // LHS = VECTOR_SHUFFLE A, B, LMask
23813 // If LHS is not a shuffle then pretend it is the shuffle
23814 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23815 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23818 SmallVector<int, 16> LMask(NumElts);
23819 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23820 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23821 A = LHS.getOperand(0);
23822 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23823 B = LHS.getOperand(1);
23824 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23825 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23827 if (LHS.getOpcode() != ISD::UNDEF)
23829 for (unsigned i = 0; i != NumElts; ++i)
23833 // Likewise, view RHS in the form
23834 // RHS = VECTOR_SHUFFLE C, D, RMask
23836 SmallVector<int, 16> RMask(NumElts);
23837 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23838 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23839 C = RHS.getOperand(0);
23840 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23841 D = RHS.getOperand(1);
23842 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23843 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23845 if (RHS.getOpcode() != ISD::UNDEF)
23847 for (unsigned i = 0; i != NumElts; ++i)
23851 // Check that the shuffles are both shuffling the same vectors.
23852 if (!(A == C && B == D) && !(A == D && B == C))
23855 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23856 if (!A.getNode() && !B.getNode())
23859 // If A and B occur in reverse order in RHS, then "swap" them (which means
23860 // rewriting the mask).
23862 CommuteVectorShuffleMask(RMask, NumElts);
23864 // At this point LHS and RHS are equivalent to
23865 // LHS = VECTOR_SHUFFLE A, B, LMask
23866 // RHS = VECTOR_SHUFFLE A, B, RMask
23867 // Check that the masks correspond to performing a horizontal operation.
23868 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23869 for (unsigned i = 0; i != NumLaneElts; ++i) {
23870 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23872 // Ignore any UNDEF components.
23873 if (LIdx < 0 || RIdx < 0 ||
23874 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23875 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23878 // Check that successive elements are being operated on. If not, this is
23879 // not a horizontal operation.
23880 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23881 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23882 if (!(LIdx == Index && RIdx == Index + 1) &&
23883 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23888 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23889 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23893 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23894 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23895 const X86Subtarget *Subtarget) {
23896 EVT VT = N->getValueType(0);
23897 SDValue LHS = N->getOperand(0);
23898 SDValue RHS = N->getOperand(1);
23900 // Try to synthesize horizontal adds from adds of shuffles.
23901 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23902 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23903 isHorizontalBinOp(LHS, RHS, true))
23904 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23908 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23909 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23910 const X86Subtarget *Subtarget) {
23911 EVT VT = N->getValueType(0);
23912 SDValue LHS = N->getOperand(0);
23913 SDValue RHS = N->getOperand(1);
23915 // Try to synthesize horizontal subs from subs of shuffles.
23916 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23917 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23918 isHorizontalBinOp(LHS, RHS, false))
23919 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23923 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23924 /// X86ISD::FXOR nodes.
23925 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23926 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23927 // F[X]OR(0.0, x) -> x
23928 // F[X]OR(x, 0.0) -> x
23929 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23930 if (C->getValueAPF().isPosZero())
23931 return N->getOperand(1);
23932 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23933 if (C->getValueAPF().isPosZero())
23934 return N->getOperand(0);
23938 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23939 /// X86ISD::FMAX nodes.
23940 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23941 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23943 // Only perform optimizations if UnsafeMath is used.
23944 if (!DAG.getTarget().Options.UnsafeFPMath)
23947 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23948 // into FMINC and FMAXC, which are Commutative operations.
23949 unsigned NewOp = 0;
23950 switch (N->getOpcode()) {
23951 default: llvm_unreachable("unknown opcode");
23952 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23953 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23956 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23957 N->getOperand(0), N->getOperand(1));
23960 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23961 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23962 // FAND(0.0, x) -> 0.0
23963 // FAND(x, 0.0) -> 0.0
23964 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23965 if (C->getValueAPF().isPosZero())
23966 return N->getOperand(0);
23967 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23968 if (C->getValueAPF().isPosZero())
23969 return N->getOperand(1);
23973 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23974 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23975 // FANDN(x, 0.0) -> 0.0
23976 // FANDN(0.0, x) -> x
23977 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23978 if (C->getValueAPF().isPosZero())
23979 return N->getOperand(1);
23980 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23981 if (C->getValueAPF().isPosZero())
23982 return N->getOperand(1);
23986 static SDValue PerformBTCombine(SDNode *N,
23988 TargetLowering::DAGCombinerInfo &DCI) {
23989 // BT ignores high bits in the bit index operand.
23990 SDValue Op1 = N->getOperand(1);
23991 if (Op1.hasOneUse()) {
23992 unsigned BitWidth = Op1.getValueSizeInBits();
23993 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23994 APInt KnownZero, KnownOne;
23995 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23996 !DCI.isBeforeLegalizeOps());
23997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23998 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23999 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24000 DCI.CommitTargetLoweringOpt(TLO);
24005 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24006 SDValue Op = N->getOperand(0);
24007 if (Op.getOpcode() == ISD::BITCAST)
24008 Op = Op.getOperand(0);
24009 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24010 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24011 VT.getVectorElementType().getSizeInBits() ==
24012 OpVT.getVectorElementType().getSizeInBits()) {
24013 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24018 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24019 const X86Subtarget *Subtarget) {
24020 EVT VT = N->getValueType(0);
24021 if (!VT.isVector())
24024 SDValue N0 = N->getOperand(0);
24025 SDValue N1 = N->getOperand(1);
24026 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24029 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24030 // both SSE and AVX2 since there is no sign-extended shift right
24031 // operation on a vector with 64-bit elements.
24032 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24033 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24034 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24035 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24036 SDValue N00 = N0.getOperand(0);
24038 // EXTLOAD has a better solution on AVX2,
24039 // it may be replaced with X86ISD::VSEXT node.
24040 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24041 if (!ISD::isNormalLoad(N00.getNode()))
24044 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24045 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24047 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24053 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24054 TargetLowering::DAGCombinerInfo &DCI,
24055 const X86Subtarget *Subtarget) {
24056 if (!DCI.isBeforeLegalizeOps())
24059 if (!Subtarget->hasFp256())
24062 EVT VT = N->getValueType(0);
24063 if (VT.isVector() && VT.getSizeInBits() == 256) {
24064 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24072 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24073 const X86Subtarget* Subtarget) {
24075 EVT VT = N->getValueType(0);
24077 // Let legalize expand this if it isn't a legal type yet.
24078 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24081 EVT ScalarVT = VT.getScalarType();
24082 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24083 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24086 SDValue A = N->getOperand(0);
24087 SDValue B = N->getOperand(1);
24088 SDValue C = N->getOperand(2);
24090 bool NegA = (A.getOpcode() == ISD::FNEG);
24091 bool NegB = (B.getOpcode() == ISD::FNEG);
24092 bool NegC = (C.getOpcode() == ISD::FNEG);
24094 // Negative multiplication when NegA xor NegB
24095 bool NegMul = (NegA != NegB);
24097 A = A.getOperand(0);
24099 B = B.getOperand(0);
24101 C = C.getOperand(0);
24105 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24107 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24109 return DAG.getNode(Opcode, dl, VT, A, B, C);
24112 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24113 TargetLowering::DAGCombinerInfo &DCI,
24114 const X86Subtarget *Subtarget) {
24115 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24116 // (and (i32 x86isd::setcc_carry), 1)
24117 // This eliminates the zext. This transformation is necessary because
24118 // ISD::SETCC is always legalized to i8.
24120 SDValue N0 = N->getOperand(0);
24121 EVT VT = N->getValueType(0);
24123 if (N0.getOpcode() == ISD::AND &&
24125 N0.getOperand(0).hasOneUse()) {
24126 SDValue N00 = N0.getOperand(0);
24127 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24129 if (!C || C->getZExtValue() != 1)
24131 return DAG.getNode(ISD::AND, dl, VT,
24132 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24133 N00.getOperand(0), N00.getOperand(1)),
24134 DAG.getConstant(1, VT));
24138 if (N0.getOpcode() == ISD::TRUNCATE &&
24140 N0.getOperand(0).hasOneUse()) {
24141 SDValue N00 = N0.getOperand(0);
24142 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24143 return DAG.getNode(ISD::AND, dl, VT,
24144 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24145 N00.getOperand(0), N00.getOperand(1)),
24146 DAG.getConstant(1, VT));
24149 if (VT.is256BitVector()) {
24150 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24158 // Optimize x == -y --> x+y == 0
24159 // x != -y --> x+y != 0
24160 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24161 const X86Subtarget* Subtarget) {
24162 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24163 SDValue LHS = N->getOperand(0);
24164 SDValue RHS = N->getOperand(1);
24165 EVT VT = N->getValueType(0);
24168 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24170 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24171 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24172 LHS.getValueType(), RHS, LHS.getOperand(1));
24173 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24174 addV, DAG.getConstant(0, addV.getValueType()), CC);
24176 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24178 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24179 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24180 RHS.getValueType(), LHS, RHS.getOperand(1));
24181 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24182 addV, DAG.getConstant(0, addV.getValueType()), CC);
24185 if (VT.getScalarType() == MVT::i1) {
24186 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24187 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24188 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24189 if (!IsSEXT0 && !IsVZero0)
24191 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24192 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24193 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24195 if (!IsSEXT1 && !IsVZero1)
24198 if (IsSEXT0 && IsVZero1) {
24199 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24200 if (CC == ISD::SETEQ)
24201 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24202 return LHS.getOperand(0);
24204 if (IsSEXT1 && IsVZero0) {
24205 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24206 if (CC == ISD::SETEQ)
24207 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24208 return RHS.getOperand(0);
24215 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24216 const X86Subtarget *Subtarget) {
24218 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24219 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24220 "X86insertps is only defined for v4x32");
24222 SDValue Ld = N->getOperand(1);
24223 if (MayFoldLoad(Ld)) {
24224 // Extract the countS bits from the immediate so we can get the proper
24225 // address when narrowing the vector load to a specific element.
24226 // When the second source op is a memory address, interps doesn't use
24227 // countS and just gets an f32 from that address.
24228 unsigned DestIndex =
24229 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24230 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24234 // Create this as a scalar to vector to match the instruction pattern.
24235 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24236 // countS bits are ignored when loading from memory on insertps, which
24237 // means we don't need to explicitly set them to 0.
24238 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24239 LoadScalarToVector, N->getOperand(2));
24242 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24243 // as "sbb reg,reg", since it can be extended without zext and produces
24244 // an all-ones bit which is more useful than 0/1 in some cases.
24245 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24248 return DAG.getNode(ISD::AND, DL, VT,
24249 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24250 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24251 DAG.getConstant(1, VT));
24252 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24253 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24254 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24255 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24258 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24259 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24260 TargetLowering::DAGCombinerInfo &DCI,
24261 const X86Subtarget *Subtarget) {
24263 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24264 SDValue EFLAGS = N->getOperand(1);
24266 if (CC == X86::COND_A) {
24267 // Try to convert COND_A into COND_B in an attempt to facilitate
24268 // materializing "setb reg".
24270 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24271 // cannot take an immediate as its first operand.
24273 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24274 EFLAGS.getValueType().isInteger() &&
24275 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24276 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24277 EFLAGS.getNode()->getVTList(),
24278 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24279 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24280 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24284 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24285 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24287 if (CC == X86::COND_B)
24288 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24292 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24293 if (Flags.getNode()) {
24294 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24295 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24301 // Optimize branch condition evaluation.
24303 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24304 TargetLowering::DAGCombinerInfo &DCI,
24305 const X86Subtarget *Subtarget) {
24307 SDValue Chain = N->getOperand(0);
24308 SDValue Dest = N->getOperand(1);
24309 SDValue EFLAGS = N->getOperand(3);
24310 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24314 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24315 if (Flags.getNode()) {
24316 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24317 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24324 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24325 SelectionDAG &DAG) {
24326 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24327 // optimize away operation when it's from a constant.
24329 // The general transformation is:
24330 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24331 // AND(VECTOR_CMP(x,y), constant2)
24332 // constant2 = UNARYOP(constant)
24334 // Early exit if this isn't a vector operation, the operand of the
24335 // unary operation isn't a bitwise AND, or if the sizes of the operations
24336 // aren't the same.
24337 EVT VT = N->getValueType(0);
24338 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24339 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24340 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24343 // Now check that the other operand of the AND is a constant. We could
24344 // make the transformation for non-constant splats as well, but it's unclear
24345 // that would be a benefit as it would not eliminate any operations, just
24346 // perform one more step in scalar code before moving to the vector unit.
24347 if (BuildVectorSDNode *BV =
24348 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24349 // Bail out if the vector isn't a constant.
24350 if (!BV->isConstant())
24353 // Everything checks out. Build up the new and improved node.
24355 EVT IntVT = BV->getValueType(0);
24356 // Create a new constant of the appropriate type for the transformed
24358 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24359 // The AND node needs bitcasts to/from an integer vector type around it.
24360 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24361 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24362 N->getOperand(0)->getOperand(0), MaskConst);
24363 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24370 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24371 const X86TargetLowering *XTLI) {
24372 // First try to optimize away the conversion entirely when it's
24373 // conditionally from a constant. Vectors only.
24374 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24375 if (Res != SDValue())
24378 // Now move on to more general possibilities.
24379 SDValue Op0 = N->getOperand(0);
24380 EVT InVT = Op0->getValueType(0);
24382 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24383 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24385 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24386 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24387 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24390 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24391 // a 32-bit target where SSE doesn't support i64->FP operations.
24392 if (Op0.getOpcode() == ISD::LOAD) {
24393 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24394 EVT VT = Ld->getValueType(0);
24395 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24396 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24397 !XTLI->getSubtarget()->is64Bit() &&
24399 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24400 Ld->getChain(), Op0, DAG);
24401 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24408 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24409 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24410 X86TargetLowering::DAGCombinerInfo &DCI) {
24411 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24412 // the result is either zero or one (depending on the input carry bit).
24413 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24414 if (X86::isZeroNode(N->getOperand(0)) &&
24415 X86::isZeroNode(N->getOperand(1)) &&
24416 // We don't have a good way to replace an EFLAGS use, so only do this when
24418 SDValue(N, 1).use_empty()) {
24420 EVT VT = N->getValueType(0);
24421 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24422 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24423 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24424 DAG.getConstant(X86::COND_B,MVT::i8),
24426 DAG.getConstant(1, VT));
24427 return DCI.CombineTo(N, Res1, CarryOut);
24433 // fold (add Y, (sete X, 0)) -> adc 0, Y
24434 // (add Y, (setne X, 0)) -> sbb -1, Y
24435 // (sub (sete X, 0), Y) -> sbb 0, Y
24436 // (sub (setne X, 0), Y) -> adc -1, Y
24437 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24440 // Look through ZExts.
24441 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24442 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24445 SDValue SetCC = Ext.getOperand(0);
24446 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24449 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24450 if (CC != X86::COND_E && CC != X86::COND_NE)
24453 SDValue Cmp = SetCC.getOperand(1);
24454 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24455 !X86::isZeroNode(Cmp.getOperand(1)) ||
24456 !Cmp.getOperand(0).getValueType().isInteger())
24459 SDValue CmpOp0 = Cmp.getOperand(0);
24460 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24461 DAG.getConstant(1, CmpOp0.getValueType()));
24463 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24464 if (CC == X86::COND_NE)
24465 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24466 DL, OtherVal.getValueType(), OtherVal,
24467 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24468 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24469 DL, OtherVal.getValueType(), OtherVal,
24470 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24473 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24474 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24475 const X86Subtarget *Subtarget) {
24476 EVT VT = N->getValueType(0);
24477 SDValue Op0 = N->getOperand(0);
24478 SDValue Op1 = N->getOperand(1);
24480 // Try to synthesize horizontal adds from adds of shuffles.
24481 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24482 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24483 isHorizontalBinOp(Op0, Op1, true))
24484 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24486 return OptimizeConditionalInDecrement(N, DAG);
24489 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24490 const X86Subtarget *Subtarget) {
24491 SDValue Op0 = N->getOperand(0);
24492 SDValue Op1 = N->getOperand(1);
24494 // X86 can't encode an immediate LHS of a sub. See if we can push the
24495 // negation into a preceding instruction.
24496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24497 // If the RHS of the sub is a XOR with one use and a constant, invert the
24498 // immediate. Then add one to the LHS of the sub so we can turn
24499 // X-Y -> X+~Y+1, saving one register.
24500 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24501 isa<ConstantSDNode>(Op1.getOperand(1))) {
24502 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24503 EVT VT = Op0.getValueType();
24504 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24506 DAG.getConstant(~XorC, VT));
24507 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24508 DAG.getConstant(C->getAPIntValue()+1, VT));
24512 // Try to synthesize horizontal adds from adds of shuffles.
24513 EVT VT = N->getValueType(0);
24514 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24515 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24516 isHorizontalBinOp(Op0, Op1, true))
24517 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24519 return OptimizeConditionalInDecrement(N, DAG);
24522 /// performVZEXTCombine - Performs build vector combines
24523 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24524 TargetLowering::DAGCombinerInfo &DCI,
24525 const X86Subtarget *Subtarget) {
24526 // (vzext (bitcast (vzext (x)) -> (vzext x)
24527 SDValue In = N->getOperand(0);
24528 while (In.getOpcode() == ISD::BITCAST)
24529 In = In.getOperand(0);
24531 if (In.getOpcode() != X86ISD::VZEXT)
24534 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24538 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24539 DAGCombinerInfo &DCI) const {
24540 SelectionDAG &DAG = DCI.DAG;
24541 switch (N->getOpcode()) {
24543 case ISD::EXTRACT_VECTOR_ELT:
24544 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24546 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24547 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24548 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24549 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24550 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24551 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24554 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24555 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24556 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24557 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24558 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24559 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24560 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24561 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24562 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24564 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24566 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24567 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24568 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24569 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24570 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24571 case ISD::ANY_EXTEND:
24572 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24573 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24574 case ISD::SIGN_EXTEND_INREG:
24575 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24576 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24577 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24578 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24579 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24580 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24581 case X86ISD::SHUFP: // Handle all target specific shuffles
24582 case X86ISD::PALIGNR:
24583 case X86ISD::UNPCKH:
24584 case X86ISD::UNPCKL:
24585 case X86ISD::MOVHLPS:
24586 case X86ISD::MOVLHPS:
24587 case X86ISD::PSHUFB:
24588 case X86ISD::PSHUFD:
24589 case X86ISD::PSHUFHW:
24590 case X86ISD::PSHUFLW:
24591 case X86ISD::MOVSS:
24592 case X86ISD::MOVSD:
24593 case X86ISD::VPERMILPI:
24594 case X86ISD::VPERM2X128:
24595 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24596 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24597 case ISD::INTRINSIC_WO_CHAIN:
24598 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24599 case X86ISD::INSERTPS:
24600 return PerformINSERTPSCombine(N, DAG, Subtarget);
24601 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24607 /// isTypeDesirableForOp - Return true if the target has native support for
24608 /// the specified value type and it is 'desirable' to use the type for the
24609 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24610 /// instruction encodings are longer and some i16 instructions are slow.
24611 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24612 if (!isTypeLegal(VT))
24614 if (VT != MVT::i16)
24621 case ISD::SIGN_EXTEND:
24622 case ISD::ZERO_EXTEND:
24623 case ISD::ANY_EXTEND:
24636 /// IsDesirableToPromoteOp - This method query the target whether it is
24637 /// beneficial for dag combiner to promote the specified node. If true, it
24638 /// should return the desired promotion type by reference.
24639 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24640 EVT VT = Op.getValueType();
24641 if (VT != MVT::i16)
24644 bool Promote = false;
24645 bool Commute = false;
24646 switch (Op.getOpcode()) {
24649 LoadSDNode *LD = cast<LoadSDNode>(Op);
24650 // If the non-extending load has a single use and it's not live out, then it
24651 // might be folded.
24652 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24653 Op.hasOneUse()*/) {
24654 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24655 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24656 // The only case where we'd want to promote LOAD (rather then it being
24657 // promoted as an operand is when it's only use is liveout.
24658 if (UI->getOpcode() != ISD::CopyToReg)
24665 case ISD::SIGN_EXTEND:
24666 case ISD::ZERO_EXTEND:
24667 case ISD::ANY_EXTEND:
24672 SDValue N0 = Op.getOperand(0);
24673 // Look out for (store (shl (load), x)).
24674 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24687 SDValue N0 = Op.getOperand(0);
24688 SDValue N1 = Op.getOperand(1);
24689 if (!Commute && MayFoldLoad(N1))
24691 // Avoid disabling potential load folding opportunities.
24692 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24694 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24704 //===----------------------------------------------------------------------===//
24705 // X86 Inline Assembly Support
24706 //===----------------------------------------------------------------------===//
24709 // Helper to match a string separated by whitespace.
24710 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24711 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24713 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24714 StringRef piece(*args[i]);
24715 if (!s.startswith(piece)) // Check if the piece matches.
24718 s = s.substr(piece.size());
24719 StringRef::size_type pos = s.find_first_not_of(" \t");
24720 if (pos == 0) // We matched a prefix.
24728 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24731 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24733 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24734 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24735 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24736 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24738 if (AsmPieces.size() == 3)
24740 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24747 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24748 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24750 std::string AsmStr = IA->getAsmString();
24752 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24753 if (!Ty || Ty->getBitWidth() % 16 != 0)
24756 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24757 SmallVector<StringRef, 4> AsmPieces;
24758 SplitString(AsmStr, AsmPieces, ";\n");
24760 switch (AsmPieces.size()) {
24761 default: return false;
24763 // FIXME: this should verify that we are targeting a 486 or better. If not,
24764 // we will turn this bswap into something that will be lowered to logical
24765 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24766 // lower so don't worry about this.
24768 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24769 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24770 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24771 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24772 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24773 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24774 // No need to check constraints, nothing other than the equivalent of
24775 // "=r,0" would be valid here.
24776 return IntrinsicLowering::LowerToByteSwap(CI);
24779 // rorw $$8, ${0:w} --> llvm.bswap.i16
24780 if (CI->getType()->isIntegerTy(16) &&
24781 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24782 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24783 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24785 const std::string &ConstraintsStr = IA->getConstraintString();
24786 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24787 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24788 if (clobbersFlagRegisters(AsmPieces))
24789 return IntrinsicLowering::LowerToByteSwap(CI);
24793 if (CI->getType()->isIntegerTy(32) &&
24794 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24795 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24796 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24797 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24799 const std::string &ConstraintsStr = IA->getConstraintString();
24800 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24801 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24802 if (clobbersFlagRegisters(AsmPieces))
24803 return IntrinsicLowering::LowerToByteSwap(CI);
24806 if (CI->getType()->isIntegerTy(64)) {
24807 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24808 if (Constraints.size() >= 2 &&
24809 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24810 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24811 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24812 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24813 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24814 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24815 return IntrinsicLowering::LowerToByteSwap(CI);
24823 /// getConstraintType - Given a constraint letter, return the type of
24824 /// constraint it is for this target.
24825 X86TargetLowering::ConstraintType
24826 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24827 if (Constraint.size() == 1) {
24828 switch (Constraint[0]) {
24839 return C_RegisterClass;
24863 return TargetLowering::getConstraintType(Constraint);
24866 /// Examine constraint type and operand type and determine a weight value.
24867 /// This object must already have been set up with the operand type
24868 /// and the current alternative constraint selected.
24869 TargetLowering::ConstraintWeight
24870 X86TargetLowering::getSingleConstraintMatchWeight(
24871 AsmOperandInfo &info, const char *constraint) const {
24872 ConstraintWeight weight = CW_Invalid;
24873 Value *CallOperandVal = info.CallOperandVal;
24874 // If we don't have a value, we can't do a match,
24875 // but allow it at the lowest weight.
24876 if (!CallOperandVal)
24878 Type *type = CallOperandVal->getType();
24879 // Look at the constraint type.
24880 switch (*constraint) {
24882 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24893 if (CallOperandVal->getType()->isIntegerTy())
24894 weight = CW_SpecificReg;
24899 if (type->isFloatingPointTy())
24900 weight = CW_SpecificReg;
24903 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24904 weight = CW_SpecificReg;
24908 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24909 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24910 weight = CW_Register;
24913 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24914 if (C->getZExtValue() <= 31)
24915 weight = CW_Constant;
24919 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24920 if (C->getZExtValue() <= 63)
24921 weight = CW_Constant;
24925 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24926 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24927 weight = CW_Constant;
24931 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24932 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24933 weight = CW_Constant;
24937 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24938 if (C->getZExtValue() <= 3)
24939 weight = CW_Constant;
24943 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24944 if (C->getZExtValue() <= 0xff)
24945 weight = CW_Constant;
24950 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24951 weight = CW_Constant;
24955 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24956 if ((C->getSExtValue() >= -0x80000000LL) &&
24957 (C->getSExtValue() <= 0x7fffffffLL))
24958 weight = CW_Constant;
24962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24963 if (C->getZExtValue() <= 0xffffffff)
24964 weight = CW_Constant;
24971 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24972 /// with another that has more specific requirements based on the type of the
24973 /// corresponding operand.
24974 const char *X86TargetLowering::
24975 LowerXConstraint(EVT ConstraintVT) const {
24976 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24977 // 'f' like normal targets.
24978 if (ConstraintVT.isFloatingPoint()) {
24979 if (Subtarget->hasSSE2())
24981 if (Subtarget->hasSSE1())
24985 return TargetLowering::LowerXConstraint(ConstraintVT);
24988 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24989 /// vector. If it is invalid, don't add anything to Ops.
24990 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24991 std::string &Constraint,
24992 std::vector<SDValue>&Ops,
24993 SelectionDAG &DAG) const {
24996 // Only support length 1 constraints for now.
24997 if (Constraint.length() > 1) return;
24999 char ConstraintLetter = Constraint[0];
25000 switch (ConstraintLetter) {
25003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25004 if (C->getZExtValue() <= 31) {
25005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25012 if (C->getZExtValue() <= 63) {
25013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25020 if (isInt<8>(C->getSExtValue())) {
25021 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25028 if (C->getZExtValue() <= 255) {
25029 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25035 // 32-bit signed value
25036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25037 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25038 C->getSExtValue())) {
25039 // Widen to 64 bits here to get it sign extended.
25040 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25043 // FIXME gcc accepts some relocatable values here too, but only in certain
25044 // memory models; it's complicated.
25049 // 32-bit unsigned value
25050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25051 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25052 C->getZExtValue())) {
25053 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25057 // FIXME gcc accepts some relocatable values here too, but only in certain
25058 // memory models; it's complicated.
25062 // Literal immediates are always ok.
25063 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25064 // Widen to 64 bits here to get it sign extended.
25065 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25069 // In any sort of PIC mode addresses need to be computed at runtime by
25070 // adding in a register or some sort of table lookup. These can't
25071 // be used as immediates.
25072 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25075 // If we are in non-pic codegen mode, we allow the address of a global (with
25076 // an optional displacement) to be used with 'i'.
25077 GlobalAddressSDNode *GA = nullptr;
25078 int64_t Offset = 0;
25080 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25082 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25083 Offset += GA->getOffset();
25085 } else if (Op.getOpcode() == ISD::ADD) {
25086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25087 Offset += C->getZExtValue();
25088 Op = Op.getOperand(0);
25091 } else if (Op.getOpcode() == ISD::SUB) {
25092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25093 Offset += -C->getZExtValue();
25094 Op = Op.getOperand(0);
25099 // Otherwise, this isn't something we can handle, reject it.
25103 const GlobalValue *GV = GA->getGlobal();
25104 // If we require an extra load to get this address, as in PIC mode, we
25105 // can't accept it.
25106 if (isGlobalStubReference(
25107 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25110 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25111 GA->getValueType(0), Offset);
25116 if (Result.getNode()) {
25117 Ops.push_back(Result);
25120 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25123 std::pair<unsigned, const TargetRegisterClass*>
25124 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25126 // First, see if this is a constraint that directly corresponds to an LLVM
25128 if (Constraint.size() == 1) {
25129 // GCC Constraint Letters
25130 switch (Constraint[0]) {
25132 // TODO: Slight differences here in allocation order and leaving
25133 // RIP in the class. Do they matter any more here than they do
25134 // in the normal allocation?
25135 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25136 if (Subtarget->is64Bit()) {
25137 if (VT == MVT::i32 || VT == MVT::f32)
25138 return std::make_pair(0U, &X86::GR32RegClass);
25139 if (VT == MVT::i16)
25140 return std::make_pair(0U, &X86::GR16RegClass);
25141 if (VT == MVT::i8 || VT == MVT::i1)
25142 return std::make_pair(0U, &X86::GR8RegClass);
25143 if (VT == MVT::i64 || VT == MVT::f64)
25144 return std::make_pair(0U, &X86::GR64RegClass);
25147 // 32-bit fallthrough
25148 case 'Q': // Q_REGS
25149 if (VT == MVT::i32 || VT == MVT::f32)
25150 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25151 if (VT == MVT::i16)
25152 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25153 if (VT == MVT::i8 || VT == MVT::i1)
25154 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25155 if (VT == MVT::i64)
25156 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25158 case 'r': // GENERAL_REGS
25159 case 'l': // INDEX_REGS
25160 if (VT == MVT::i8 || VT == MVT::i1)
25161 return std::make_pair(0U, &X86::GR8RegClass);
25162 if (VT == MVT::i16)
25163 return std::make_pair(0U, &X86::GR16RegClass);
25164 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25165 return std::make_pair(0U, &X86::GR32RegClass);
25166 return std::make_pair(0U, &X86::GR64RegClass);
25167 case 'R': // LEGACY_REGS
25168 if (VT == MVT::i8 || VT == MVT::i1)
25169 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25170 if (VT == MVT::i16)
25171 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25172 if (VT == MVT::i32 || !Subtarget->is64Bit())
25173 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25174 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25175 case 'f': // FP Stack registers.
25176 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25177 // value to the correct fpstack register class.
25178 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25179 return std::make_pair(0U, &X86::RFP32RegClass);
25180 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25181 return std::make_pair(0U, &X86::RFP64RegClass);
25182 return std::make_pair(0U, &X86::RFP80RegClass);
25183 case 'y': // MMX_REGS if MMX allowed.
25184 if (!Subtarget->hasMMX()) break;
25185 return std::make_pair(0U, &X86::VR64RegClass);
25186 case 'Y': // SSE_REGS if SSE2 allowed
25187 if (!Subtarget->hasSSE2()) break;
25189 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25190 if (!Subtarget->hasSSE1()) break;
25192 switch (VT.SimpleTy) {
25194 // Scalar SSE types.
25197 return std::make_pair(0U, &X86::FR32RegClass);
25200 return std::make_pair(0U, &X86::FR64RegClass);
25208 return std::make_pair(0U, &X86::VR128RegClass);
25216 return std::make_pair(0U, &X86::VR256RegClass);
25221 return std::make_pair(0U, &X86::VR512RegClass);
25227 // Use the default implementation in TargetLowering to convert the register
25228 // constraint into a member of a register class.
25229 std::pair<unsigned, const TargetRegisterClass*> Res;
25230 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25232 // Not found as a standard register?
25234 // Map st(0) -> st(7) -> ST0
25235 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25236 tolower(Constraint[1]) == 's' &&
25237 tolower(Constraint[2]) == 't' &&
25238 Constraint[3] == '(' &&
25239 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25240 Constraint[5] == ')' &&
25241 Constraint[6] == '}') {
25243 Res.first = X86::FP0+Constraint[4]-'0';
25244 Res.second = &X86::RFP80RegClass;
25248 // GCC allows "st(0)" to be called just plain "st".
25249 if (StringRef("{st}").equals_lower(Constraint)) {
25250 Res.first = X86::FP0;
25251 Res.second = &X86::RFP80RegClass;
25256 if (StringRef("{flags}").equals_lower(Constraint)) {
25257 Res.first = X86::EFLAGS;
25258 Res.second = &X86::CCRRegClass;
25262 // 'A' means EAX + EDX.
25263 if (Constraint == "A") {
25264 Res.first = X86::EAX;
25265 Res.second = &X86::GR32_ADRegClass;
25271 // Otherwise, check to see if this is a register class of the wrong value
25272 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25273 // turn into {ax},{dx}.
25274 if (Res.second->hasType(VT))
25275 return Res; // Correct type already, nothing to do.
25277 // All of the single-register GCC register classes map their values onto
25278 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25279 // really want an 8-bit or 32-bit register, map to the appropriate register
25280 // class and return the appropriate register.
25281 if (Res.second == &X86::GR16RegClass) {
25282 if (VT == MVT::i8 || VT == MVT::i1) {
25283 unsigned DestReg = 0;
25284 switch (Res.first) {
25286 case X86::AX: DestReg = X86::AL; break;
25287 case X86::DX: DestReg = X86::DL; break;
25288 case X86::CX: DestReg = X86::CL; break;
25289 case X86::BX: DestReg = X86::BL; break;
25292 Res.first = DestReg;
25293 Res.second = &X86::GR8RegClass;
25295 } else if (VT == MVT::i32 || VT == MVT::f32) {
25296 unsigned DestReg = 0;
25297 switch (Res.first) {
25299 case X86::AX: DestReg = X86::EAX; break;
25300 case X86::DX: DestReg = X86::EDX; break;
25301 case X86::CX: DestReg = X86::ECX; break;
25302 case X86::BX: DestReg = X86::EBX; break;
25303 case X86::SI: DestReg = X86::ESI; break;
25304 case X86::DI: DestReg = X86::EDI; break;
25305 case X86::BP: DestReg = X86::EBP; break;
25306 case X86::SP: DestReg = X86::ESP; break;
25309 Res.first = DestReg;
25310 Res.second = &X86::GR32RegClass;
25312 } else if (VT == MVT::i64 || VT == MVT::f64) {
25313 unsigned DestReg = 0;
25314 switch (Res.first) {
25316 case X86::AX: DestReg = X86::RAX; break;
25317 case X86::DX: DestReg = X86::RDX; break;
25318 case X86::CX: DestReg = X86::RCX; break;
25319 case X86::BX: DestReg = X86::RBX; break;
25320 case X86::SI: DestReg = X86::RSI; break;
25321 case X86::DI: DestReg = X86::RDI; break;
25322 case X86::BP: DestReg = X86::RBP; break;
25323 case X86::SP: DestReg = X86::RSP; break;
25326 Res.first = DestReg;
25327 Res.second = &X86::GR64RegClass;
25330 } else if (Res.second == &X86::FR32RegClass ||
25331 Res.second == &X86::FR64RegClass ||
25332 Res.second == &X86::VR128RegClass ||
25333 Res.second == &X86::VR256RegClass ||
25334 Res.second == &X86::FR32XRegClass ||
25335 Res.second == &X86::FR64XRegClass ||
25336 Res.second == &X86::VR128XRegClass ||
25337 Res.second == &X86::VR256XRegClass ||
25338 Res.second == &X86::VR512RegClass) {
25339 // Handle references to XMM physical registers that got mapped into the
25340 // wrong class. This can happen with constraints like {xmm0} where the
25341 // target independent register mapper will just pick the first match it can
25342 // find, ignoring the required type.
25344 if (VT == MVT::f32 || VT == MVT::i32)
25345 Res.second = &X86::FR32RegClass;
25346 else if (VT == MVT::f64 || VT == MVT::i64)
25347 Res.second = &X86::FR64RegClass;
25348 else if (X86::VR128RegClass.hasType(VT))
25349 Res.second = &X86::VR128RegClass;
25350 else if (X86::VR256RegClass.hasType(VT))
25351 Res.second = &X86::VR256RegClass;
25352 else if (X86::VR512RegClass.hasType(VT))
25353 Res.second = &X86::VR512RegClass;
25359 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25361 // Scaling factors are not free at all.
25362 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25363 // will take 2 allocations in the out of order engine instead of 1
25364 // for plain addressing mode, i.e. inst (reg1).
25366 // vaddps (%rsi,%drx), %ymm0, %ymm1
25367 // Requires two allocations (one for the load, one for the computation)
25369 // vaddps (%rsi), %ymm0, %ymm1
25370 // Requires just 1 allocation, i.e., freeing allocations for other operations
25371 // and having less micro operations to execute.
25373 // For some X86 architectures, this is even worse because for instance for
25374 // stores, the complex addressing mode forces the instruction to use the
25375 // "load" ports instead of the dedicated "store" port.
25376 // E.g., on Haswell:
25377 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25378 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25379 if (isLegalAddressingMode(AM, Ty))
25380 // Scale represents reg2 * scale, thus account for 1
25381 // as soon as we use a second register.
25382 return AM.Scale != 0;
25386 bool X86TargetLowering::isTargetFTOL() const {
25387 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();