1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1737 return VT.changeVectorElementTypeToInteger();
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1810 if (Subtarget->hasInt256())
1812 if (Subtarget->hasFp256())
1815 if (Subtarget->hasSSE2())
1817 if (Subtarget->hasSSE1())
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1827 if (Subtarget->is64Bit() && Size >= 8)
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1906 switch (VT.SimpleTy) {
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1913 RRC = &X86::VR64RegClass;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1920 RRC = &X86::VR128RegClass;
1923 return std::make_pair(RRC, Cost);
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2098 if (!N->hasNUsesOfValue(1, 0))
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2210 enum StructReturnType {
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3948 for (i = 0; i != NumLaneElts; ++i) {
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4013 return isAlignrMask(Mask, VT, false);
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4023 return isAlignrMask(Mask, VT, true);
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4037 Mask[i] = idx - NumElems;
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4094 if ((signed)(Idx - l) != MaskVal[i])
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4108 unsigned NumElems = VT.getVectorNumElements();
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4127 unsigned NumElems = VT.getVectorNumElements();
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4201 else if (Mask[i] == i + 4)
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4214 // Some special combinations that can be optimized.
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4239 if (!MatchEvenMask && !MatchOddMask)
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4287 if (!isUndefOrEqual(BitI1, NumElts))
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4325 if (isUndefOrEqual(BitI1, NumElts))
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4371 if (!isUndefOrEqual(BitI1, j))
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4406 if (!isUndefOrEqual(BitI1, j))
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4442 if (!VT.is128BitVector())
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4489 return MatchA && MatchB;
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4513 return (FstHalf | (SndHalf << 4));
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4528 Imm8 |= Mask[i] << (i*2);
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4602 if (!isUndefOrEqual(Mask[0], 0))
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4669 unsigned NumElts = VT.getVectorNumElements();
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4707 // The index should be aligned on a vecWidth-bit boundary.
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4725 // The index should be aligned on a vecWidth-bit boundary.
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4937 bool X86::isZeroNode(SDValue Elt) {
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4952 if (VT.getVectorNumElements() != 4)
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4973 *LD = cast<LoadSDNode>(N);
4977 // Test whether the given value is a vector value which will be legalized
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4987 case ISD::ConstantFP:
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5158 Mask.push_back(i + NumElems);
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5258 return getLegalSplat(DAG, V1, EltNo);
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFB: {
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5375 DecodePSHUFBMask(RawMask, Mask);
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5398 DecodePSHUFBMask(C, Mask);
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6016 MVT VT = Op.getSimpleValueType();
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6025 switch (Op.getOpcode()) {
6027 // Unknown pattern found.
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6158 // Unsupported broadcast.
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6206 unsigned NumElems = Op.getNumOperands();
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6224 InsertIndices.push_back(i);
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6249 if (ExtractedFromVec == VecIn1)
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6255 if (!VecIn1.getNode())
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6310 if (In != Op.getOperand(0))
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6434 ExpectedVExtractIdx += 2;
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6587 if (InVec1 != Op1.getOperand(0))
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6653 if (!Subtarget->hasAVX())
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6709 // Convert this build_vector into a pair of horizontal binop followed by
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6737 // Convert this build_vector into two horizontal add/sub followed by
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6803 NonZeros |= (1 << i);
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6990 if (V.getNode()) return V;
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7016 V[i] = V[i*2]; // Must be a zero vector.
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7079 V[i] = DAG.getUNDEF(VT);
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7172 /// \brief Helper function to classify a mask as a single-input mask.
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7182 if (M >= (int)Mask.size())
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7294 /// \brief Try to emit a blend instruction for a shuffle.
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7316 switch (VT.SimpleTy) {
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7415 llvm_unreachable("Not a supported integer vector type!");
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of the concatenation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7490 // The identity rotation isn't interesting, stop.
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7569 // If this is an index into a build_vector node, dig out the input value and
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7649 // Otherwise emit a sequence of unpacks.
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7685 auto Lower = [&](int Scale) -> SDValue {
7688 for (int i = 0; i < NumElements; ++i) {
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7696 // We no lorger are in the anyext case.
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7737 // No viable ext lowering found.
7741 /// \brief Try to get a scalar value for a specific element of a vector.
7743 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7744 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7745 SelectionDAG &DAG) {
7746 MVT VT = V.getSimpleValueType();
7747 MVT EltVT = VT.getVectorElementType();
7748 while (V.getOpcode() == ISD::BITCAST)
7749 V = V.getOperand(0);
7750 // If the bitcasts shift the element size, we can't extract an equivalent
7752 MVT NewVT = V.getSimpleValueType();
7753 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7756 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7757 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7758 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7763 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7765 /// This is particularly important because the set of instructions varies
7766 /// significantly based on whether the operand is a load or not.
7767 static bool isShuffleFoldableLoad(SDValue V) {
7768 while (V.getOpcode() == ISD::BITCAST)
7769 V = V.getOperand(0);
7771 return ISD::isNON_EXTLoad(V.getNode());
7774 /// \brief Try to lower insertion of a single element into a zero vector.
7776 /// This is a common pattern that we have especially efficient patterns to lower
7777 /// across all subtarget feature sets.
7778 static SDValue lowerVectorShuffleAsElementInsertion(
7779 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7780 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7781 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7783 MVT EltVT = VT.getVectorElementType();
7785 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7786 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7788 bool IsV1Zeroable = true;
7789 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7790 if (i != V2Index && !Zeroable[i]) {
7791 IsV1Zeroable = false;
7795 // Check for a single input from a SCALAR_TO_VECTOR node.
7796 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7797 // all the smarts here sunk into that routine. However, the current
7798 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7799 // vector shuffle lowering is dead.
7800 if (SDValue V2S = getScalarValueForVectorElement(
7801 V2, Mask[V2Index] - Mask.size(), DAG)) {
7802 // We need to zext the scalar if it is smaller than an i32.
7803 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7804 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7805 // Using zext to expand a narrow element won't work for non-zero
7810 // Zero-extend directly to i32.
7812 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7814 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7815 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7816 EltVT == MVT::i16) {
7817 // Either not inserting from the low element of the input or the input
7818 // element size is too small to use VZEXT_MOVL to clear the high bits.
7822 if (!IsV1Zeroable) {
7823 // If V1 can't be treated as a zero vector we have fewer options to lower
7824 // this. We can't support integer vectors or non-zero targets cheaply, and
7825 // the V1 elements can't be permuted in any way.
7826 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7827 if (!VT.isFloatingPoint() || V2Index != 0)
7829 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7830 V1Mask[V2Index] = -1;
7831 if (!isNoopShuffleMask(V1Mask))
7833 // This is essentially a special case blend operation, but if we have
7834 // general purpose blend operations, they are always faster. Bail and let
7835 // the rest of the lowering handle these as blends.
7836 if (Subtarget->hasSSE41())
7839 // Otherwise, use MOVSD or MOVSS.
7840 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7841 "Only two types of floating point element types to handle!");
7842 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7846 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7848 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7851 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7852 // the desired position. Otherwise it is more efficient to do a vector
7853 // shift left. We know that we can do a vector shift left because all
7854 // the inputs are zero.
7855 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7856 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7857 V2Shuffle[V2Index] = 0;
7858 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7860 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7862 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7864 V2Index * EltVT.getSizeInBits(),
7865 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7866 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7872 /// \brief Try to lower broadcast of a single element.
7874 /// For convenience, this code also bundles all of the subtarget feature set
7875 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7876 /// a convenient way to factor it out.
7877 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7881 if (!Subtarget->hasAVX())
7883 if (VT.isInteger() && !Subtarget->hasAVX2())
7886 // Check that the mask is a broadcast.
7887 int BroadcastIdx = -1;
7889 if (M >= 0 && BroadcastIdx == -1)
7891 else if (M >= 0 && M != BroadcastIdx)
7894 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7895 "a sorted mask where the broadcast "
7898 // Go up the chain of (vector) values to try and find a scalar load that
7899 // we can combine with the broadcast.
7901 switch (V.getOpcode()) {
7902 case ISD::CONCAT_VECTORS: {
7903 int OperandSize = Mask.size() / V.getNumOperands();
7904 V = V.getOperand(BroadcastIdx / OperandSize);
7905 BroadcastIdx %= OperandSize;
7909 case ISD::INSERT_SUBVECTOR: {
7910 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7911 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7915 int BeginIdx = (int)ConstantIdx->getZExtValue();
7917 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7918 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7919 BroadcastIdx -= BeginIdx;
7930 // Check if this is a broadcast of a scalar. We special case lowering
7931 // for scalars so that we can more effectively fold with loads.
7932 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7933 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7934 V = V.getOperand(BroadcastIdx);
7936 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7938 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7940 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7941 // We can't broadcast from a vector register w/o AVX2, and we can only
7942 // broadcast from the zero-element of a vector register.
7946 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7949 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7951 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7952 /// support for floating point shuffles but not integer shuffles. These
7953 /// instructions will incur a domain crossing penalty on some chips though so
7954 /// it is better to avoid lowering through this for integer vectors where
7956 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7957 const X86Subtarget *Subtarget,
7958 SelectionDAG &DAG) {
7960 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7961 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7962 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7964 ArrayRef<int> Mask = SVOp->getMask();
7965 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7967 if (isSingleInputShuffleMask(Mask)) {
7968 // Straight shuffle of a single input vector. Simulate this by using the
7969 // single input as both of the "inputs" to this instruction..
7970 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7972 if (Subtarget->hasAVX()) {
7973 // If we have AVX, we can use VPERMILPS which will allow folding a load
7974 // into the shuffle.
7975 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7976 DAG.getConstant(SHUFPDMask, MVT::i8));
7979 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7980 DAG.getConstant(SHUFPDMask, MVT::i8));
7982 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7983 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7985 // Use dedicated unpack instructions for masks that match their pattern.
7986 if (isShuffleEquivalent(Mask, 0, 2))
7987 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7988 if (isShuffleEquivalent(Mask, 1, 3))
7989 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7991 // If we have a single input, insert that into V1 if we can do so cheaply.
7992 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7993 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7994 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7996 // Try inverting the insertion since for v2 masks it is easy to do and we
7997 // can't reliably sort the mask one way or the other.
7998 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7999 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8000 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8001 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8005 // Try to use one of the special instruction patterns to handle two common
8006 // blend patterns if a zero-blend above didn't work.
8007 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8008 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8009 // We can either use a special instruction to load over the low double or
8010 // to move just the low double.
8012 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8014 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8016 if (Subtarget->hasSSE41())
8017 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8021 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8022 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8023 DAG.getConstant(SHUFPDMask, MVT::i8));
8026 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8028 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8029 /// the integer unit to minimize domain crossing penalties. However, for blends
8030 /// it falls back to the floating point shuffle operation with appropriate bit
8032 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8033 const X86Subtarget *Subtarget,
8034 SelectionDAG &DAG) {
8036 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8037 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8038 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8040 ArrayRef<int> Mask = SVOp->getMask();
8041 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8043 if (isSingleInputShuffleMask(Mask)) {
8044 // Check for being able to broadcast a single element.
8045 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8046 Mask, Subtarget, DAG))
8049 // Straight shuffle of a single input vector. For everything from SSE2
8050 // onward this has a single fast instruction with no scary immediates.
8051 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8052 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8053 int WidenedMask[4] = {
8054 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8055 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8057 ISD::BITCAST, DL, MVT::v2i64,
8058 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8059 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8062 // If we have a single input from V2 insert that into V1 if we can do so
8064 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8065 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8066 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8068 // Try inverting the insertion since for v2 masks it is easy to do and we
8069 // can't reliably sort the mask one way or the other.
8070 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8071 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8072 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8073 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8077 // Use dedicated unpack instructions for masks that match their pattern.
8078 if (isShuffleEquivalent(Mask, 0, 2))
8079 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8080 if (isShuffleEquivalent(Mask, 1, 3))
8081 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8083 if (Subtarget->hasSSE41())
8084 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8088 // Try to use rotation instructions if available.
8089 if (Subtarget->hasSSSE3())
8090 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8091 DL, MVT::v2i64, V1, V2, Mask, DAG))
8094 // We implement this with SHUFPD which is pretty lame because it will likely
8095 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8096 // However, all the alternatives are still more cycles and newer chips don't
8097 // have this problem. It would be really nice if x86 had better shuffles here.
8098 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8099 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8100 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8101 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8104 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8106 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8107 /// It makes no assumptions about whether this is the *best* lowering, it simply
8109 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8110 ArrayRef<int> Mask, SDValue V1,
8111 SDValue V2, SelectionDAG &DAG) {
8112 SDValue LowV = V1, HighV = V2;
8113 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8116 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8118 if (NumV2Elements == 1) {
8120 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8123 // Compute the index adjacent to V2Index and in the same half by toggling
8125 int V2AdjIndex = V2Index ^ 1;
8127 if (Mask[V2AdjIndex] == -1) {
8128 // Handles all the cases where we have a single V2 element and an undef.
8129 // This will only ever happen in the high lanes because we commute the
8130 // vector otherwise.
8132 std::swap(LowV, HighV);
8133 NewMask[V2Index] -= 4;
8135 // Handle the case where the V2 element ends up adjacent to a V1 element.
8136 // To make this work, blend them together as the first step.
8137 int V1Index = V2AdjIndex;
8138 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8139 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8140 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8142 // Now proceed to reconstruct the final blend as we have the necessary
8143 // high or low half formed.
8150 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8151 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8153 } else if (NumV2Elements == 2) {
8154 if (Mask[0] < 4 && Mask[1] < 4) {
8155 // Handle the easy case where we have V1 in the low lanes and V2 in the
8159 } else if (Mask[2] < 4 && Mask[3] < 4) {
8160 // We also handle the reversed case because this utility may get called
8161 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8162 // arrange things in the right direction.
8168 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8169 // trying to place elements directly, just blend them and set up the final
8170 // shuffle to place them.
8172 // The first two blend mask elements are for V1, the second two are for
8174 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8175 Mask[2] < 4 ? Mask[2] : Mask[3],
8176 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8177 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8178 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8179 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8181 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8184 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8185 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8186 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8187 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8190 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8191 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8194 /// \brief Lower 4-lane 32-bit floating point shuffles.
8196 /// Uses instructions exclusively from the floating point unit to minimize
8197 /// domain crossing penalties, as these are sufficient to implement all v4f32
8199 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8200 const X86Subtarget *Subtarget,
8201 SelectionDAG &DAG) {
8203 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8204 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8205 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8207 ArrayRef<int> Mask = SVOp->getMask();
8208 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8211 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8213 if (NumV2Elements == 0) {
8214 // Check for being able to broadcast a single element.
8215 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8216 Mask, Subtarget, DAG))
8219 if (Subtarget->hasAVX()) {
8220 // If we have AVX, we can use VPERMILPS which will allow folding a load
8221 // into the shuffle.
8222 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8223 getV4X86ShuffleImm8ForMask(Mask, DAG));
8226 // Otherwise, use a straight shuffle of a single input vector. We pass the
8227 // input vector to both operands to simulate this with a SHUFPS.
8228 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8229 getV4X86ShuffleImm8ForMask(Mask, DAG));
8232 // Use dedicated unpack instructions for masks that match their pattern.
8233 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8234 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8235 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8236 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8238 // There are special ways we can lower some single-element blends. However, we
8239 // have custom ways we can lower more complex single-element blends below that
8240 // we defer to if both this and BLENDPS fail to match, so restrict this to
8241 // when the V2 input is targeting element 0 of the mask -- that is the fast
8243 if (NumV2Elements == 1 && Mask[0] >= 4)
8244 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8245 Mask, Subtarget, DAG))
8248 if (Subtarget->hasSSE41())
8249 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8253 // Check for whether we can use INSERTPS to perform the blend. We only use
8254 // INSERTPS when the V1 elements are already in the correct locations
8255 // because otherwise we can just always use two SHUFPS instructions which
8256 // are much smaller to encode than a SHUFPS and an INSERTPS.
8257 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8259 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8262 // When using INSERTPS we can zero any lane of the destination. Collect
8263 // the zero inputs into a mask and drop them from the lanes of V1 which
8264 // actually need to be present as inputs to the INSERTPS.
8265 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8267 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8268 bool InsertNeedsShuffle = false;
8270 for (int i = 0; i < 4; ++i)
8274 } else if (Mask[i] != i) {
8275 InsertNeedsShuffle = true;
8280 // We don't want to use INSERTPS or other insertion techniques if it will
8281 // require shuffling anyways.
8282 if (!InsertNeedsShuffle) {
8283 // If all of V1 is zeroable, replace it with undef.
8284 if ((ZMask | 1 << V2Index) == 0xF)
8285 V1 = DAG.getUNDEF(MVT::v4f32);
8287 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8288 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8290 // Insert the V2 element into the desired position.
8291 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8292 DAG.getConstant(InsertPSMask, MVT::i8));
8296 // Otherwise fall back to a SHUFPS lowering strategy.
8297 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8300 /// \brief Lower 4-lane i32 vector shuffles.
8302 /// We try to handle these with integer-domain shuffles where we can, but for
8303 /// blends we use the floating point domain blend instructions.
8304 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8305 const X86Subtarget *Subtarget,
8306 SelectionDAG &DAG) {
8308 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8309 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8310 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8312 ArrayRef<int> Mask = SVOp->getMask();
8313 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8315 // Whenever we can lower this as a zext, that instruction is strictly faster
8316 // than any alternative. It also allows us to fold memory operands into the
8317 // shuffle in many cases.
8318 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8319 Mask, Subtarget, DAG))
8323 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8325 if (NumV2Elements == 0) {
8326 // Check for being able to broadcast a single element.
8327 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8328 Mask, Subtarget, DAG))
8331 // Straight shuffle of a single input vector. For everything from SSE2
8332 // onward this has a single fast instruction with no scary immediates.
8333 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8334 // but we aren't actually going to use the UNPCK instruction because doing
8335 // so prevents folding a load into this instruction or making a copy.
8336 const int UnpackLoMask[] = {0, 0, 1, 1};
8337 const int UnpackHiMask[] = {2, 2, 3, 3};
8338 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8339 Mask = UnpackLoMask;
8340 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8341 Mask = UnpackHiMask;
8343 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8344 getV4X86ShuffleImm8ForMask(Mask, DAG));
8347 // There are special ways we can lower some single-element blends.
8348 if (NumV2Elements == 1)
8349 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8350 Mask, Subtarget, DAG))
8353 // Use dedicated unpack instructions for masks that match their pattern.
8354 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8355 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8356 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8357 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8359 if (Subtarget->hasSSE41())
8360 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8364 // Try to use rotation instructions if available.
8365 if (Subtarget->hasSSSE3())
8366 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8367 DL, MVT::v4i32, V1, V2, Mask, DAG))
8370 // We implement this with SHUFPS because it can blend from two vectors.
8371 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8372 // up the inputs, bypassing domain shift penalties that we would encur if we
8373 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8375 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8376 DAG.getVectorShuffle(
8378 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8379 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8382 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8383 /// shuffle lowering, and the most complex part.
8385 /// The lowering strategy is to try to form pairs of input lanes which are
8386 /// targeted at the same half of the final vector, and then use a dword shuffle
8387 /// to place them onto the right half, and finally unpack the paired lanes into
8388 /// their final position.
8390 /// The exact breakdown of how to form these dword pairs and align them on the
8391 /// correct sides is really tricky. See the comments within the function for
8392 /// more of the details.
8393 static SDValue lowerV8I16SingleInputVectorShuffle(
8394 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8395 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8396 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8397 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8398 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8400 SmallVector<int, 4> LoInputs;
8401 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8402 [](int M) { return M >= 0; });
8403 std::sort(LoInputs.begin(), LoInputs.end());
8404 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8405 SmallVector<int, 4> HiInputs;
8406 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8407 [](int M) { return M >= 0; });
8408 std::sort(HiInputs.begin(), HiInputs.end());
8409 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8411 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8412 int NumHToL = LoInputs.size() - NumLToL;
8414 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8415 int NumHToH = HiInputs.size() - NumLToH;
8416 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8417 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8418 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8419 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8421 // Check for being able to broadcast a single element.
8422 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8423 Mask, Subtarget, DAG))
8426 // Use dedicated unpack instructions for masks that match their pattern.
8427 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8429 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8430 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8432 // Try to use rotation instructions if available.
8433 if (Subtarget->hasSSSE3())
8434 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8435 DL, MVT::v8i16, V, V, Mask, DAG))
8438 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8439 // such inputs we can swap two of the dwords across the half mark and end up
8440 // with <=2 inputs to each half in each half. Once there, we can fall through
8441 // to the generic code below. For example:
8443 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8444 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8446 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8447 // and an existing 2-into-2 on the other half. In this case we may have to
8448 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8449 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8450 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8451 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8452 // half than the one we target for fixing) will be fixed when we re-enter this
8453 // path. We will also combine away any sequence of PSHUFD instructions that
8454 // result into a single instruction. Here is an example of the tricky case:
8456 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8457 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8459 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8461 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8462 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8464 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8465 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8467 // The result is fine to be handled by the generic logic.
8468 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8469 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8470 int AOffset, int BOffset) {
8471 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8472 "Must call this with A having 3 or 1 inputs from the A half.");
8473 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8474 "Must call this with B having 1 or 3 inputs from the B half.");
8475 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8476 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8478 // Compute the index of dword with only one word among the three inputs in
8479 // a half by taking the sum of the half with three inputs and subtracting
8480 // the sum of the actual three inputs. The difference is the remaining
8483 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8484 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8485 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8486 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8487 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8488 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8489 int TripleNonInputIdx =
8490 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8491 TripleDWord = TripleNonInputIdx / 2;
8493 // We use xor with one to compute the adjacent DWord to whichever one the
8495 OneInputDWord = (OneInput / 2) ^ 1;
8497 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8498 // and BToA inputs. If there is also such a problem with the BToB and AToB
8499 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8500 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8501 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8502 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8503 // Compute how many inputs will be flipped by swapping these DWords. We
8505 // to balance this to ensure we don't form a 3-1 shuffle in the other
8507 int NumFlippedAToBInputs =
8508 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8509 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8510 int NumFlippedBToBInputs =
8511 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8512 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8513 if ((NumFlippedAToBInputs == 1 &&
8514 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8515 (NumFlippedBToBInputs == 1 &&
8516 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8517 // We choose whether to fix the A half or B half based on whether that
8518 // half has zero flipped inputs. At zero, we may not be able to fix it
8519 // with that half. We also bias towards fixing the B half because that
8520 // will more commonly be the high half, and we have to bias one way.
8521 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8522 ArrayRef<int> Inputs) {
8523 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8524 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8525 PinnedIdx ^ 1) != Inputs.end();
8526 // Determine whether the free index is in the flipped dword or the
8527 // unflipped dword based on where the pinned index is. We use this bit
8528 // in an xor to conditionally select the adjacent dword.
8529 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8530 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8531 FixFreeIdx) != Inputs.end();
8532 if (IsFixIdxInput == IsFixFreeIdxInput)
8534 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8535 FixFreeIdx) != Inputs.end();
8536 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8537 "We need to be changing the number of flipped inputs!");
8538 int PSHUFHalfMask[] = {0, 1, 2, 3};
8539 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8540 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8542 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8545 if (M != -1 && M == FixIdx)
8547 else if (M != -1 && M == FixFreeIdx)
8550 if (NumFlippedBToBInputs != 0) {
8552 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8553 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8555 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8557 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8558 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8563 int PSHUFDMask[] = {0, 1, 2, 3};
8564 PSHUFDMask[ADWord] = BDWord;
8565 PSHUFDMask[BDWord] = ADWord;
8566 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8567 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8568 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8569 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8571 // Adjust the mask to match the new locations of A and B.
8573 if (M != -1 && M/2 == ADWord)
8574 M = 2 * BDWord + M % 2;
8575 else if (M != -1 && M/2 == BDWord)
8576 M = 2 * ADWord + M % 2;
8578 // Recurse back into this routine to re-compute state now that this isn't
8579 // a 3 and 1 problem.
8580 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8583 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8584 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8585 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8586 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8588 // At this point there are at most two inputs to the low and high halves from
8589 // each half. That means the inputs can always be grouped into dwords and
8590 // those dwords can then be moved to the correct half with a dword shuffle.
8591 // We use at most one low and one high word shuffle to collect these paired
8592 // inputs into dwords, and finally a dword shuffle to place them.
8593 int PSHUFLMask[4] = {-1, -1, -1, -1};
8594 int PSHUFHMask[4] = {-1, -1, -1, -1};
8595 int PSHUFDMask[4] = {-1, -1, -1, -1};
8597 // First fix the masks for all the inputs that are staying in their
8598 // original halves. This will then dictate the targets of the cross-half
8600 auto fixInPlaceInputs =
8601 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8602 MutableArrayRef<int> SourceHalfMask,
8603 MutableArrayRef<int> HalfMask, int HalfOffset) {
8604 if (InPlaceInputs.empty())
8606 if (InPlaceInputs.size() == 1) {
8607 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8608 InPlaceInputs[0] - HalfOffset;
8609 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8612 if (IncomingInputs.empty()) {
8613 // Just fix all of the in place inputs.
8614 for (int Input : InPlaceInputs) {
8615 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8616 PSHUFDMask[Input / 2] = Input / 2;
8621 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8622 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8623 InPlaceInputs[0] - HalfOffset;
8624 // Put the second input next to the first so that they are packed into
8625 // a dword. We find the adjacent index by toggling the low bit.
8626 int AdjIndex = InPlaceInputs[0] ^ 1;
8627 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8628 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8629 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8631 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8632 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8634 // Now gather the cross-half inputs and place them into a free dword of
8635 // their target half.
8636 // FIXME: This operation could almost certainly be simplified dramatically to
8637 // look more like the 3-1 fixing operation.
8638 auto moveInputsToRightHalf = [&PSHUFDMask](
8639 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8640 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8641 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8643 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8644 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8646 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8648 int LowWord = Word & ~1;
8649 int HighWord = Word | 1;
8650 return isWordClobbered(SourceHalfMask, LowWord) ||
8651 isWordClobbered(SourceHalfMask, HighWord);
8654 if (IncomingInputs.empty())
8657 if (ExistingInputs.empty()) {
8658 // Map any dwords with inputs from them into the right half.
8659 for (int Input : IncomingInputs) {
8660 // If the source half mask maps over the inputs, turn those into
8661 // swaps and use the swapped lane.
8662 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8663 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8664 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8665 Input - SourceOffset;
8666 // We have to swap the uses in our half mask in one sweep.
8667 for (int &M : HalfMask)
8668 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8670 else if (M == Input)
8671 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8673 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8674 Input - SourceOffset &&
8675 "Previous placement doesn't match!");
8677 // Note that this correctly re-maps both when we do a swap and when
8678 // we observe the other side of the swap above. We rely on that to
8679 // avoid swapping the members of the input list directly.
8680 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8683 // Map the input's dword into the correct half.
8684 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8685 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8687 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8689 "Previous placement doesn't match!");
8692 // And just directly shift any other-half mask elements to be same-half
8693 // as we will have mirrored the dword containing the element into the
8694 // same position within that half.
8695 for (int &M : HalfMask)
8696 if (M >= SourceOffset && M < SourceOffset + 4) {
8697 M = M - SourceOffset + DestOffset;
8698 assert(M >= 0 && "This should never wrap below zero!");
8703 // Ensure we have the input in a viable dword of its current half. This
8704 // is particularly tricky because the original position may be clobbered
8705 // by inputs being moved and *staying* in that half.
8706 if (IncomingInputs.size() == 1) {
8707 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8708 int InputFixed = std::find(std::begin(SourceHalfMask),
8709 std::end(SourceHalfMask), -1) -
8710 std::begin(SourceHalfMask) + SourceOffset;
8711 SourceHalfMask[InputFixed - SourceOffset] =
8712 IncomingInputs[0] - SourceOffset;
8713 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8715 IncomingInputs[0] = InputFixed;
8717 } else if (IncomingInputs.size() == 2) {
8718 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8719 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8720 // We have two non-adjacent or clobbered inputs we need to extract from
8721 // the source half. To do this, we need to map them into some adjacent
8722 // dword slot in the source mask.
8723 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8724 IncomingInputs[1] - SourceOffset};
8726 // If there is a free slot in the source half mask adjacent to one of
8727 // the inputs, place the other input in it. We use (Index XOR 1) to
8728 // compute an adjacent index.
8729 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8730 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8731 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8732 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8733 InputsFixed[1] = InputsFixed[0] ^ 1;
8734 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8735 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8736 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8737 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8738 InputsFixed[0] = InputsFixed[1] ^ 1;
8739 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8740 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8741 // The two inputs are in the same DWord but it is clobbered and the
8742 // adjacent DWord isn't used at all. Move both inputs to the free
8744 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8745 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8746 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8747 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8749 // The only way we hit this point is if there is no clobbering
8750 // (because there are no off-half inputs to this half) and there is no
8751 // free slot adjacent to one of the inputs. In this case, we have to
8752 // swap an input with a non-input.
8753 for (int i = 0; i < 4; ++i)
8754 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8755 "We can't handle any clobbers here!");
8756 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8757 "Cannot have adjacent inputs here!");
8759 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8760 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8762 // We also have to update the final source mask in this case because
8763 // it may need to undo the above swap.
8764 for (int &M : FinalSourceHalfMask)
8765 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8766 M = InputsFixed[1] + SourceOffset;
8767 else if (M == InputsFixed[1] + SourceOffset)
8768 M = (InputsFixed[0] ^ 1) + SourceOffset;
8770 InputsFixed[1] = InputsFixed[0] ^ 1;
8773 // Point everything at the fixed inputs.
8774 for (int &M : HalfMask)
8775 if (M == IncomingInputs[0])
8776 M = InputsFixed[0] + SourceOffset;
8777 else if (M == IncomingInputs[1])
8778 M = InputsFixed[1] + SourceOffset;
8780 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8781 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8784 llvm_unreachable("Unhandled input size!");
8787 // Now hoist the DWord down to the right half.
8788 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8789 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8790 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8791 for (int &M : HalfMask)
8792 for (int Input : IncomingInputs)
8794 M = FreeDWord * 2 + Input % 2;
8796 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8797 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8798 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8799 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8801 // Now enact all the shuffles we've computed to move the inputs into their
8803 if (!isNoopShuffleMask(PSHUFLMask))
8804 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8805 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8806 if (!isNoopShuffleMask(PSHUFHMask))
8807 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8808 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8809 if (!isNoopShuffleMask(PSHUFDMask))
8810 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8811 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8812 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8813 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8815 // At this point, each half should contain all its inputs, and we can then
8816 // just shuffle them into their final position.
8817 assert(std::count_if(LoMask.begin(), LoMask.end(),
8818 [](int M) { return M >= 4; }) == 0 &&
8819 "Failed to lift all the high half inputs to the low mask!");
8820 assert(std::count_if(HiMask.begin(), HiMask.end(),
8821 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8822 "Failed to lift all the low half inputs to the high mask!");
8824 // Do a half shuffle for the low mask.
8825 if (!isNoopShuffleMask(LoMask))
8826 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8827 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8829 // Do a half shuffle with the high mask after shifting its values down.
8830 for (int &M : HiMask)
8833 if (!isNoopShuffleMask(HiMask))
8834 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8835 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8840 /// \brief Detect whether the mask pattern should be lowered through
8843 /// This essentially tests whether viewing the mask as an interleaving of two
8844 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8845 /// lowering it through interleaving is a significantly better strategy.
8846 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8847 int NumEvenInputs[2] = {0, 0};
8848 int NumOddInputs[2] = {0, 0};
8849 int NumLoInputs[2] = {0, 0};
8850 int NumHiInputs[2] = {0, 0};
8851 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8855 int InputIdx = Mask[i] >= Size;
8858 ++NumLoInputs[InputIdx];
8860 ++NumHiInputs[InputIdx];
8863 ++NumEvenInputs[InputIdx];
8865 ++NumOddInputs[InputIdx];
8868 // The minimum number of cross-input results for both the interleaved and
8869 // split cases. If interleaving results in fewer cross-input results, return
8871 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8872 NumEvenInputs[0] + NumOddInputs[1]);
8873 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8874 NumLoInputs[0] + NumHiInputs[1]);
8875 return InterleavedCrosses < SplitCrosses;
8878 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8880 /// This strategy only works when the inputs from each vector fit into a single
8881 /// half of that vector, and generally there are not so many inputs as to leave
8882 /// the in-place shuffles required highly constrained (and thus expensive). It
8883 /// shifts all the inputs into a single side of both input vectors and then
8884 /// uses an unpack to interleave these inputs in a single vector. At that
8885 /// point, we will fall back on the generic single input shuffle lowering.
8886 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8888 MutableArrayRef<int> Mask,
8889 const X86Subtarget *Subtarget,
8890 SelectionDAG &DAG) {
8891 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8892 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8893 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8894 for (int i = 0; i < 8; ++i)
8895 if (Mask[i] >= 0 && Mask[i] < 4)
8896 LoV1Inputs.push_back(i);
8897 else if (Mask[i] >= 4 && Mask[i] < 8)
8898 HiV1Inputs.push_back(i);
8899 else if (Mask[i] >= 8 && Mask[i] < 12)
8900 LoV2Inputs.push_back(i);
8901 else if (Mask[i] >= 12)
8902 HiV2Inputs.push_back(i);
8904 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8905 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8908 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8909 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8910 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8912 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8913 HiV1Inputs.size() + HiV2Inputs.size();
8915 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8916 ArrayRef<int> HiInputs, bool MoveToLo,
8918 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8919 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8920 if (BadInputs.empty())
8923 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8924 int MoveOffset = MoveToLo ? 0 : 4;
8926 if (GoodInputs.empty()) {
8927 for (int BadInput : BadInputs) {
8928 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8929 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8932 if (GoodInputs.size() == 2) {
8933 // If the low inputs are spread across two dwords, pack them into
8935 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8936 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8937 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8938 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8940 // Otherwise pin the good inputs.
8941 for (int GoodInput : GoodInputs)
8942 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8945 if (BadInputs.size() == 2) {
8946 // If we have two bad inputs then there may be either one or two good
8947 // inputs fixed in place. Find a fixed input, and then find the *other*
8948 // two adjacent indices by using modular arithmetic.
8950 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8951 [](int M) { return M >= 0; }) -
8952 std::begin(MoveMask);
8954 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8955 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8956 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8957 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8958 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8959 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8960 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8962 assert(BadInputs.size() == 1 && "All sizes handled");
8963 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8964 std::end(MoveMask), -1) -
8965 std::begin(MoveMask);
8966 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8967 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8971 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8974 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8976 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8979 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8980 // cross-half traffic in the final shuffle.
8982 // Munge the mask to be a single-input mask after the unpack merges the
8986 M = 2 * (M % 4) + (M / 8);
8988 return DAG.getVectorShuffle(
8989 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8990 DL, MVT::v8i16, V1, V2),
8991 DAG.getUNDEF(MVT::v8i16), Mask);
8994 /// \brief Generic lowering of 8-lane i16 shuffles.
8996 /// This handles both single-input shuffles and combined shuffle/blends with
8997 /// two inputs. The single input shuffles are immediately delegated to
8998 /// a dedicated lowering routine.
9000 /// The blends are lowered in one of three fundamental ways. If there are few
9001 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9002 /// of the input is significantly cheaper when lowered as an interleaving of
9003 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9004 /// halves of the inputs separately (making them have relatively few inputs)
9005 /// and then concatenate them.
9006 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9007 const X86Subtarget *Subtarget,
9008 SelectionDAG &DAG) {
9010 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9011 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9012 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9014 ArrayRef<int> OrigMask = SVOp->getMask();
9015 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9016 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9017 MutableArrayRef<int> Mask(MaskStorage);
9019 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9021 // Whenever we can lower this as a zext, that instruction is strictly faster
9022 // than any alternative.
9023 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9024 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9027 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9028 auto isV2 = [](int M) { return M >= 8; };
9030 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9031 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9033 if (NumV2Inputs == 0)
9034 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9036 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9037 "to be V1-input shuffles.");
9039 // There are special ways we can lower some single-element blends.
9040 if (NumV2Inputs == 1)
9041 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9042 Mask, Subtarget, DAG))
9045 if (Subtarget->hasSSE41())
9046 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9050 // Try to use rotation instructions if available.
9051 if (Subtarget->hasSSSE3())
9052 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9053 DL, MVT::v8i16, V1, V2, Mask, DAG))
9056 if (NumV1Inputs + NumV2Inputs <= 4)
9057 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9059 // Check whether an interleaving lowering is likely to be more efficient.
9060 // This isn't perfect but it is a strong heuristic that tends to work well on
9061 // the kinds of shuffles that show up in practice.
9063 // FIXME: Handle 1x, 2x, and 4x interleaving.
9064 if (shouldLowerAsInterleaving(Mask)) {
9065 // FIXME: Figure out whether we should pack these into the low or high
9068 int EMask[8], OMask[8];
9069 for (int i = 0; i < 4; ++i) {
9070 EMask[i] = Mask[2*i];
9071 OMask[i] = Mask[2*i + 1];
9076 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9077 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9079 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9082 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9083 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9085 for (int i = 0; i < 4; ++i) {
9086 LoBlendMask[i] = Mask[i];
9087 HiBlendMask[i] = Mask[i + 4];
9090 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9091 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9092 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9093 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9095 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9096 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9099 /// \brief Check whether a compaction lowering can be done by dropping even
9100 /// elements and compute how many times even elements must be dropped.
9102 /// This handles shuffles which take every Nth element where N is a power of
9103 /// two. Example shuffle masks:
9105 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9106 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9107 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9108 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9109 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9110 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9112 /// Any of these lanes can of course be undef.
9114 /// This routine only supports N <= 3.
9115 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9118 /// \returns N above, or the number of times even elements must be dropped if
9119 /// there is such a number. Otherwise returns zero.
9120 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9121 // Figure out whether we're looping over two inputs or just one.
9122 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9124 // The modulus for the shuffle vector entries is based on whether this is
9125 // a single input or not.
9126 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9127 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9128 "We should only be called with masks with a power-of-2 size!");
9130 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9132 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9133 // and 2^3 simultaneously. This is because we may have ambiguity with
9134 // partially undef inputs.
9135 bool ViableForN[3] = {true, true, true};
9137 for (int i = 0, e = Mask.size(); i < e; ++i) {
9138 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9143 bool IsAnyViable = false;
9144 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9145 if (ViableForN[j]) {
9148 // The shuffle mask must be equal to (i * 2^N) % M.
9149 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9152 ViableForN[j] = false;
9154 // Early exit if we exhaust the possible powers of two.
9159 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9163 // Return 0 as there is no viable power of two.
9167 /// \brief Generic lowering of v16i8 shuffles.
9169 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9170 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9171 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9172 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9174 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9175 const X86Subtarget *Subtarget,
9176 SelectionDAG &DAG) {
9178 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9179 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9180 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9182 ArrayRef<int> OrigMask = SVOp->getMask();
9183 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9185 // Try to use rotation instructions if available.
9186 if (Subtarget->hasSSSE3())
9187 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9188 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9191 // Try to use a zext lowering.
9192 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9193 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9196 int MaskStorage[16] = {
9197 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9198 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9199 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9200 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9201 MutableArrayRef<int> Mask(MaskStorage);
9202 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9203 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9206 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9208 // For single-input shuffles, there are some nicer lowering tricks we can use.
9209 if (NumV2Elements == 0) {
9210 // Check for being able to broadcast a single element.
9211 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9212 Mask, Subtarget, DAG))
9215 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9216 // Notably, this handles splat and partial-splat shuffles more efficiently.
9217 // However, it only makes sense if the pre-duplication shuffle simplifies
9218 // things significantly. Currently, this means we need to be able to
9219 // express the pre-duplication shuffle as an i16 shuffle.
9221 // FIXME: We should check for other patterns which can be widened into an
9222 // i16 shuffle as well.
9223 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9224 for (int i = 0; i < 16; i += 2)
9225 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9230 auto tryToWidenViaDuplication = [&]() -> SDValue {
9231 if (!canWidenViaDuplication(Mask))
9233 SmallVector<int, 4> LoInputs;
9234 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9235 [](int M) { return M >= 0 && M < 8; });
9236 std::sort(LoInputs.begin(), LoInputs.end());
9237 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9239 SmallVector<int, 4> HiInputs;
9240 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9241 [](int M) { return M >= 8; });
9242 std::sort(HiInputs.begin(), HiInputs.end());
9243 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9246 bool TargetLo = LoInputs.size() >= HiInputs.size();
9247 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9248 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9250 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9251 SmallDenseMap<int, int, 8> LaneMap;
9252 for (int I : InPlaceInputs) {
9253 PreDupI16Shuffle[I/2] = I/2;
9256 int j = TargetLo ? 0 : 4, je = j + 4;
9257 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9258 // Check if j is already a shuffle of this input. This happens when
9259 // there are two adjacent bytes after we move the low one.
9260 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9261 // If we haven't yet mapped the input, search for a slot into which
9263 while (j < je && PreDupI16Shuffle[j] != -1)
9267 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9270 // Map this input with the i16 shuffle.
9271 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9274 // Update the lane map based on the mapping we ended up with.
9275 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9278 ISD::BITCAST, DL, MVT::v16i8,
9279 DAG.getVectorShuffle(MVT::v8i16, DL,
9280 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9281 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9283 // Unpack the bytes to form the i16s that will be shuffled into place.
9284 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9285 MVT::v16i8, V1, V1);
9287 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9288 for (int i = 0; i < 16; ++i)
9289 if (Mask[i] != -1) {
9290 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9291 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9292 if (PostDupI16Shuffle[i / 2] == -1)
9293 PostDupI16Shuffle[i / 2] = MappedMask;
9295 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9296 "Conflicting entrties in the original shuffle!");
9299 ISD::BITCAST, DL, MVT::v16i8,
9300 DAG.getVectorShuffle(MVT::v8i16, DL,
9301 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9302 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9304 if (SDValue V = tryToWidenViaDuplication())
9308 // Check whether an interleaving lowering is likely to be more efficient.
9309 // This isn't perfect but it is a strong heuristic that tends to work well on
9310 // the kinds of shuffles that show up in practice.
9312 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9313 if (shouldLowerAsInterleaving(Mask)) {
9314 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9315 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9317 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9318 return (M >= 8 && M < 16) || M >= 24;
9320 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9321 -1, -1, -1, -1, -1, -1, -1, -1};
9322 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9323 -1, -1, -1, -1, -1, -1, -1, -1};
9324 bool UnpackLo = NumLoHalf >= NumHiHalf;
9325 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9326 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9327 for (int i = 0; i < 8; ++i) {
9328 TargetEMask[i] = Mask[2 * i];
9329 TargetOMask[i] = Mask[2 * i + 1];
9332 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9333 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9335 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9336 MVT::v16i8, Evens, Odds);
9339 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9340 // with PSHUFB. It is important to do this before we attempt to generate any
9341 // blends but after all of the single-input lowerings. If the single input
9342 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9343 // want to preserve that and we can DAG combine any longer sequences into
9344 // a PSHUFB in the end. But once we start blending from multiple inputs,
9345 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9346 // and there are *very* few patterns that would actually be faster than the
9347 // PSHUFB approach because of its ability to zero lanes.
9349 // FIXME: The only exceptions to the above are blends which are exact
9350 // interleavings with direct instructions supporting them. We currently don't
9351 // handle those well here.
9352 if (Subtarget->hasSSSE3()) {
9355 for (int i = 0; i < 16; ++i)
9356 if (Mask[i] == -1) {
9357 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9359 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9361 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9363 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9364 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9365 if (isSingleInputShuffleMask(Mask))
9366 return V1; // Single inputs are easy.
9368 // Otherwise, blend the two.
9369 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9370 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9371 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9374 // There are special ways we can lower some single-element blends.
9375 if (NumV2Elements == 1)
9376 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9377 Mask, Subtarget, DAG))
9380 // Check whether a compaction lowering can be done. This handles shuffles
9381 // which take every Nth element for some even N. See the helper function for
9384 // We special case these as they can be particularly efficiently handled with
9385 // the PACKUSB instruction on x86 and they show up in common patterns of
9386 // rearranging bytes to truncate wide elements.
9387 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9388 // NumEvenDrops is the power of two stride of the elements. Another way of
9389 // thinking about it is that we need to drop the even elements this many
9390 // times to get the original input.
9391 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9393 // First we need to zero all the dropped bytes.
9394 assert(NumEvenDrops <= 3 &&
9395 "No support for dropping even elements more than 3 times.");
9396 // We use the mask type to pick which bytes are preserved based on how many
9397 // elements are dropped.
9398 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9399 SDValue ByteClearMask =
9400 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9401 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9402 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9404 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9406 // Now pack things back together.
9407 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9408 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9409 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9410 for (int i = 1; i < NumEvenDrops; ++i) {
9411 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9412 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9418 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9419 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9420 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9424 MutableArrayRef<int> V1HalfBlendMask,
9425 MutableArrayRef<int> V2HalfBlendMask) {
9426 for (int i = 0; i < 8; ++i)
9427 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9428 V1HalfBlendMask[i] = HalfMask[i];
9430 } else if (HalfMask[i] >= 16) {
9431 V2HalfBlendMask[i] = HalfMask[i] - 16;
9432 HalfMask[i] = i + 8;
9435 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9436 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9438 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9440 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9441 MutableArrayRef<int> HiBlendMask) {
9443 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9444 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9446 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9447 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9448 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9449 [](int M) { return M >= 0 && M % 2 == 1; })) {
9450 // Use a mask to drop the high bytes.
9451 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9452 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9453 DAG.getConstant(0x00FF, MVT::v8i16));
9455 // This will be a single vector shuffle instead of a blend so nuke V2.
9456 V2 = DAG.getUNDEF(MVT::v8i16);
9458 // Squash the masks to point directly into V1.
9459 for (int &M : LoBlendMask)
9462 for (int &M : HiBlendMask)
9466 // Otherwise just unpack the low half of V into V1 and the high half into
9467 // V2 so that we can blend them as i16s.
9468 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9469 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9470 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9471 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9474 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9475 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9476 return std::make_pair(BlendedLo, BlendedHi);
9478 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9479 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9480 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9482 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9483 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9485 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9488 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9490 /// This routine breaks down the specific type of 128-bit shuffle and
9491 /// dispatches to the lowering routines accordingly.
9492 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9493 MVT VT, const X86Subtarget *Subtarget,
9494 SelectionDAG &DAG) {
9495 switch (VT.SimpleTy) {
9497 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9499 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9501 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9503 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9505 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9507 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9510 llvm_unreachable("Unimplemented!");
9514 /// \brief Helper function to test whether a shuffle mask could be
9515 /// simplified by widening the elements being shuffled.
9517 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9518 /// leaves it in an unspecified state.
9520 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9521 /// shuffle masks. The latter have the special property of a '-2' representing
9522 /// a zero-ed lane of a vector.
9523 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9524 SmallVectorImpl<int> &WidenedMask) {
9525 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9526 // If both elements are undef, its trivial.
9527 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9528 WidenedMask.push_back(SM_SentinelUndef);
9532 // Check for an undef mask and a mask value properly aligned to fit with
9533 // a pair of values. If we find such a case, use the non-undef mask's value.
9534 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9535 WidenedMask.push_back(Mask[i + 1] / 2);
9538 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9539 WidenedMask.push_back(Mask[i] / 2);
9543 // When zeroing, we need to spread the zeroing across both lanes to widen.
9544 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9545 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9546 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9547 WidenedMask.push_back(SM_SentinelZero);
9553 // Finally check if the two mask values are adjacent and aligned with
9555 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9556 WidenedMask.push_back(Mask[i] / 2);
9560 // Otherwise we can't safely widen the elements used in this shuffle.
9563 assert(WidenedMask.size() == Mask.size() / 2 &&
9564 "Incorrect size of mask after widening the elements!");
9569 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9571 /// This routine just extracts two subvectors, shuffles them independently, and
9572 /// then concatenates them back together. This should work effectively with all
9573 /// AVX vector shuffle types.
9574 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9575 SDValue V2, ArrayRef<int> Mask,
9576 SelectionDAG &DAG) {
9577 assert(VT.getSizeInBits() >= 256 &&
9578 "Only for 256-bit or wider vector shuffles!");
9579 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9580 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9582 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9583 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9585 int NumElements = VT.getVectorNumElements();
9586 int SplitNumElements = NumElements / 2;
9587 MVT ScalarVT = VT.getScalarType();
9588 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9590 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9591 DAG.getIntPtrConstant(0));
9592 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9593 DAG.getIntPtrConstant(SplitNumElements));
9594 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9595 DAG.getIntPtrConstant(0));
9596 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9597 DAG.getIntPtrConstant(SplitNumElements));
9599 // Now create two 4-way blends of these half-width vectors.
9600 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9601 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9602 for (int i = 0; i < SplitNumElements; ++i) {
9603 int M = HalfMask[i];
9604 if (M >= NumElements) {
9605 V2BlendMask.push_back(M - NumElements);
9606 V1BlendMask.push_back(-1);
9607 BlendMask.push_back(SplitNumElements + i);
9608 } else if (M >= 0) {
9609 V2BlendMask.push_back(-1);
9610 V1BlendMask.push_back(M);
9611 BlendMask.push_back(i);
9613 V2BlendMask.push_back(-1);
9614 V1BlendMask.push_back(-1);
9615 BlendMask.push_back(-1);
9619 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9621 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9622 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9624 SDValue Lo = HalfBlend(LoMask);
9625 SDValue Hi = HalfBlend(HiMask);
9626 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9629 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9630 /// a permutation and blend of those lanes.
9632 /// This essentially blends the out-of-lane inputs to each lane into the lane
9633 /// from a permuted copy of the vector. This lowering strategy results in four
9634 /// instructions in the worst case for a single-input cross lane shuffle which
9635 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9636 /// of. Special cases for each particular shuffle pattern should be handled
9637 /// prior to trying this lowering.
9638 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9639 SDValue V1, SDValue V2,
9641 SelectionDAG &DAG) {
9642 // FIXME: This should probably be generalized for 512-bit vectors as well.
9643 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9644 int LaneSize = Mask.size() / 2;
9646 // If there are only inputs from one 128-bit lane, splitting will in fact be
9647 // less expensive. The flags track wether the given lane contains an element
9648 // that crosses to another lane.
9649 bool LaneCrossing[2] = {false, false};
9650 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9651 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9652 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9653 if (!LaneCrossing[0] || !LaneCrossing[1])
9654 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9656 if (isSingleInputShuffleMask(Mask)) {
9657 SmallVector<int, 32> FlippedBlendMask;
9658 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9659 FlippedBlendMask.push_back(
9660 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9662 : Mask[i] % LaneSize +
9663 (i / LaneSize) * LaneSize + Size));
9665 // Flip the vector, and blend the results which should now be in-lane. The
9666 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9667 // 5 for the high source. The value 3 selects the high half of source 2 and
9668 // the value 2 selects the low half of source 2. We only use source 2 to
9669 // allow folding it into a memory operand.
9670 unsigned PERMMask = 3 | 2 << 4;
9671 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9672 V1, DAG.getConstant(PERMMask, MVT::i8));
9673 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9676 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9677 // will be handled by the above logic and a blend of the results, much like
9678 // other patterns in AVX.
9679 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9682 /// \brief Handle lowering 2-lane 128-bit shuffles.
9683 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9684 SDValue V2, ArrayRef<int> Mask,
9685 const X86Subtarget *Subtarget,
9686 SelectionDAG &DAG) {
9687 // Blends are faster and handle all the non-lane-crossing cases.
9688 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9692 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9693 VT.getVectorNumElements() / 2);
9694 // Check for patterns which can be matched with a single insert of a 128-bit
9696 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9697 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9698 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9699 DAG.getIntPtrConstant(0));
9700 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9701 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9702 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9704 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9705 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9706 DAG.getIntPtrConstant(0));
9707 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9708 DAG.getIntPtrConstant(2));
9709 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9712 // Otherwise form a 128-bit permutation.
9713 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9714 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9715 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9716 DAG.getConstant(PermMask, MVT::i8));
9719 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9721 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9722 /// isn't available.
9723 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9724 const X86Subtarget *Subtarget,
9725 SelectionDAG &DAG) {
9727 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9728 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9729 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9730 ArrayRef<int> Mask = SVOp->getMask();
9731 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9733 SmallVector<int, 4> WidenedMask;
9734 if (canWidenShuffleElements(Mask, WidenedMask))
9735 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9738 if (isSingleInputShuffleMask(Mask)) {
9739 // Check for being able to broadcast a single element.
9740 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9741 Mask, Subtarget, DAG))
9744 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9745 // Non-half-crossing single input shuffles can be lowerid with an
9746 // interleaved permutation.
9747 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9748 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9749 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9750 DAG.getConstant(VPERMILPMask, MVT::i8));
9753 // With AVX2 we have direct support for this permutation.
9754 if (Subtarget->hasAVX2())
9755 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9756 getV4X86ShuffleImm8ForMask(Mask, DAG));
9758 // Otherwise, fall back.
9759 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9763 // X86 has dedicated unpack instructions that can handle specific blend
9764 // operations: UNPCKH and UNPCKL.
9765 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9766 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9767 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9768 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9770 // If we have a single input to the zero element, insert that into V1 if we
9771 // can do so cheaply.
9773 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9774 if (NumV2Elements == 1 && Mask[0] >= 4)
9775 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9776 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9779 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9783 // Check if the blend happens to exactly fit that of SHUFPD.
9784 if ((Mask[0] == -1 || Mask[0] < 2) &&
9785 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9786 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9787 (Mask[3] == -1 || Mask[3] >= 6)) {
9788 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9789 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9790 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9791 DAG.getConstant(SHUFPDMask, MVT::i8));
9793 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9794 (Mask[1] == -1 || Mask[1] < 2) &&
9795 (Mask[2] == -1 || Mask[2] >= 6) &&
9796 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9797 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9798 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9799 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9800 DAG.getConstant(SHUFPDMask, MVT::i8));
9803 // Otherwise fall back on generic blend lowering.
9804 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9808 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9810 /// This routine is only called when we have AVX2 and thus a reasonable
9811 /// instruction set for v4i64 shuffling..
9812 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9813 const X86Subtarget *Subtarget,
9814 SelectionDAG &DAG) {
9816 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9817 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9819 ArrayRef<int> Mask = SVOp->getMask();
9820 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9821 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9823 SmallVector<int, 4> WidenedMask;
9824 if (canWidenShuffleElements(Mask, WidenedMask))
9825 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9828 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9832 // Check for being able to broadcast a single element.
9833 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9834 Mask, Subtarget, DAG))
9837 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9838 // use lower latency instructions that will operate on both 128-bit lanes.
9839 SmallVector<int, 2> RepeatedMask;
9840 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9841 if (isSingleInputShuffleMask(Mask)) {
9842 int PSHUFDMask[] = {-1, -1, -1, -1};
9843 for (int i = 0; i < 2; ++i)
9844 if (RepeatedMask[i] >= 0) {
9845 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9846 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9849 ISD::BITCAST, DL, MVT::v4i64,
9850 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9851 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9852 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9855 // Use dedicated unpack instructions for masks that match their pattern.
9856 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9857 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9858 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9859 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9862 // AVX2 provides a direct instruction for permuting a single input across
9864 if (isSingleInputShuffleMask(Mask))
9865 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9866 getV4X86ShuffleImm8ForMask(Mask, DAG));
9868 // Otherwise fall back on generic blend lowering.
9869 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9873 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9875 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9876 /// isn't available.
9877 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9878 const X86Subtarget *Subtarget,
9879 SelectionDAG &DAG) {
9881 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9882 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9883 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9884 ArrayRef<int> Mask = SVOp->getMask();
9885 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9887 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9891 // Check for being able to broadcast a single element.
9892 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9893 Mask, Subtarget, DAG))
9896 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9897 // options to efficiently lower the shuffle.
9898 SmallVector<int, 4> RepeatedMask;
9899 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9900 assert(RepeatedMask.size() == 4 &&
9901 "Repeated masks must be half the mask width!");
9902 if (isSingleInputShuffleMask(Mask))
9903 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9904 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9906 // Use dedicated unpack instructions for masks that match their pattern.
9907 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9908 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9909 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9910 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9912 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9913 // have already handled any direct blends. We also need to squash the
9914 // repeated mask into a simulated v4f32 mask.
9915 for (int i = 0; i < 4; ++i)
9916 if (RepeatedMask[i] >= 8)
9917 RepeatedMask[i] -= 4;
9918 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9921 // If we have a single input shuffle with different shuffle patterns in the
9922 // two 128-bit lanes use the variable mask to VPERMILPS.
9923 if (isSingleInputShuffleMask(Mask)) {
9924 SDValue VPermMask[8];
9925 for (int i = 0; i < 8; ++i)
9926 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9927 : DAG.getConstant(Mask[i], MVT::i32);
9928 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9930 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9931 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9933 if (Subtarget->hasAVX2())
9934 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9935 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9936 DAG.getNode(ISD::BUILD_VECTOR, DL,
9937 MVT::v8i32, VPermMask)),
9940 // Otherwise, fall back.
9941 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9945 // Otherwise fall back on generic blend lowering.
9946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9950 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9952 /// This routine is only called when we have AVX2 and thus a reasonable
9953 /// instruction set for v8i32 shuffling..
9954 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9955 const X86Subtarget *Subtarget,
9956 SelectionDAG &DAG) {
9958 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9959 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9960 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9961 ArrayRef<int> Mask = SVOp->getMask();
9962 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9963 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9965 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9969 // Check for being able to broadcast a single element.
9970 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9971 Mask, Subtarget, DAG))
9974 // If the shuffle mask is repeated in each 128-bit lane we can use more
9975 // efficient instructions that mirror the shuffles across the two 128-bit
9977 SmallVector<int, 4> RepeatedMask;
9978 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9979 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9980 if (isSingleInputShuffleMask(Mask))
9981 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9982 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9984 // Use dedicated unpack instructions for masks that match their pattern.
9985 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9986 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9987 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9988 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9991 // If the shuffle patterns aren't repeated but it is a single input, directly
9992 // generate a cross-lane VPERMD instruction.
9993 if (isSingleInputShuffleMask(Mask)) {
9994 SDValue VPermMask[8];
9995 for (int i = 0; i < 8; ++i)
9996 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9997 : DAG.getConstant(Mask[i], MVT::i32);
9999 X86ISD::VPERMV, DL, MVT::v8i32,
10000 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10003 // Otherwise fall back on generic blend lowering.
10004 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10008 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10010 /// This routine is only called when we have AVX2 and thus a reasonable
10011 /// instruction set for v16i16 shuffling..
10012 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10013 const X86Subtarget *Subtarget,
10014 SelectionDAG &DAG) {
10016 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10017 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10019 ArrayRef<int> Mask = SVOp->getMask();
10020 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10021 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10023 // Check for being able to broadcast a single element.
10024 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10025 Mask, Subtarget, DAG))
10028 // There are no generalized cross-lane shuffle operations available on i16
10030 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10031 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10034 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10038 // Use dedicated unpack instructions for masks that match their pattern.
10039 if (isShuffleEquivalent(Mask,
10040 // First 128-bit lane:
10041 0, 16, 1, 17, 2, 18, 3, 19,
10042 // Second 128-bit lane:
10043 8, 24, 9, 25, 10, 26, 11, 27))
10044 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10045 if (isShuffleEquivalent(Mask,
10046 // First 128-bit lane:
10047 4, 20, 5, 21, 6, 22, 7, 23,
10048 // Second 128-bit lane:
10049 12, 28, 13, 29, 14, 30, 15, 31))
10050 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10052 if (isSingleInputShuffleMask(Mask)) {
10053 SDValue PSHUFBMask[32];
10054 for (int i = 0; i < 16; ++i) {
10055 if (Mask[i] == -1) {
10056 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10060 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10061 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10062 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10063 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10065 return DAG.getNode(
10066 ISD::BITCAST, DL, MVT::v16i16,
10068 X86ISD::PSHUFB, DL, MVT::v32i8,
10069 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10070 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10073 // Otherwise fall back on generic blend lowering.
10074 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
10078 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10080 /// This routine is only called when we have AVX2 and thus a reasonable
10081 /// instruction set for v32i8 shuffling..
10082 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10083 const X86Subtarget *Subtarget,
10084 SelectionDAG &DAG) {
10086 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10087 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10089 ArrayRef<int> Mask = SVOp->getMask();
10090 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10091 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10093 // Check for being able to broadcast a single element.
10094 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10095 Mask, Subtarget, DAG))
10098 // There are no generalized cross-lane shuffle operations available on i8
10100 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10101 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10104 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10108 // Use dedicated unpack instructions for masks that match their pattern.
10109 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10111 if (isShuffleEquivalent(
10113 // First 128-bit lane:
10114 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10115 // Second 128-bit lane:
10116 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10117 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10118 if (isShuffleEquivalent(
10120 // First 128-bit lane:
10121 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10122 // Second 128-bit lane:
10123 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10124 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10126 if (isSingleInputShuffleMask(Mask)) {
10127 SDValue PSHUFBMask[32];
10128 for (int i = 0; i < 32; ++i)
10131 ? DAG.getUNDEF(MVT::i8)
10132 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10134 return DAG.getNode(
10135 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10136 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10139 // Otherwise fall back on generic blend lowering.
10140 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10144 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10146 /// This routine either breaks down the specific type of a 256-bit x86 vector
10147 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10148 /// together based on the available instructions.
10149 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10150 MVT VT, const X86Subtarget *Subtarget,
10151 SelectionDAG &DAG) {
10153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10154 ArrayRef<int> Mask = SVOp->getMask();
10156 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10157 // check for those subtargets here and avoid much of the subtarget querying in
10158 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10159 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10160 // floating point types there eventually, just immediately cast everything to
10161 // a float and operate entirely in that domain.
10162 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10163 int ElementBits = VT.getScalarSizeInBits();
10164 if (ElementBits < 32)
10165 // No floating point type available, decompose into 128-bit vectors.
10166 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10168 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10169 VT.getVectorNumElements());
10170 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10171 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10172 return DAG.getNode(ISD::BITCAST, DL, VT,
10173 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10176 switch (VT.SimpleTy) {
10178 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10180 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10182 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10184 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10186 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10188 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10191 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10195 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10196 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10197 const X86Subtarget *Subtarget,
10198 SelectionDAG &DAG) {
10200 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10201 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10203 ArrayRef<int> Mask = SVOp->getMask();
10204 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10206 // FIXME: Implement direct support for this type!
10207 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10210 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10211 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10212 const X86Subtarget *Subtarget,
10213 SelectionDAG &DAG) {
10215 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10216 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10218 ArrayRef<int> Mask = SVOp->getMask();
10219 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10221 // FIXME: Implement direct support for this type!
10222 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10225 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10226 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10227 const X86Subtarget *Subtarget,
10228 SelectionDAG &DAG) {
10230 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10231 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10233 ArrayRef<int> Mask = SVOp->getMask();
10234 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10235 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10237 // FIXME: Implement direct support for this type!
10238 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10241 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10242 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10243 const X86Subtarget *Subtarget,
10244 SelectionDAG &DAG) {
10246 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10247 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10248 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10249 ArrayRef<int> Mask = SVOp->getMask();
10250 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10251 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10253 // FIXME: Implement direct support for this type!
10254 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10257 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10258 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10259 const X86Subtarget *Subtarget,
10260 SelectionDAG &DAG) {
10262 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10263 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10265 ArrayRef<int> Mask = SVOp->getMask();
10266 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10267 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10269 // FIXME: Implement direct support for this type!
10270 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10273 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10274 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10275 const X86Subtarget *Subtarget,
10276 SelectionDAG &DAG) {
10278 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10279 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10281 ArrayRef<int> Mask = SVOp->getMask();
10282 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10283 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10285 // FIXME: Implement direct support for this type!
10286 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10289 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10291 /// This routine either breaks down the specific type of a 512-bit x86 vector
10292 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10293 /// together based on the available instructions.
10294 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10295 MVT VT, const X86Subtarget *Subtarget,
10296 SelectionDAG &DAG) {
10298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10299 ArrayRef<int> Mask = SVOp->getMask();
10300 assert(Subtarget->hasAVX512() &&
10301 "Cannot lower 512-bit vectors w/ basic ISA!");
10303 // Dispatch to each element type for lowering. If we don't have supprot for
10304 // specific element type shuffles at 512 bits, immediately split them and
10305 // lower them. Each lowering routine of a given type is allowed to assume that
10306 // the requisite ISA extensions for that element type are available.
10307 switch (VT.SimpleTy) {
10309 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10311 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10313 if (Subtarget->hasDQI())
10314 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10317 if (Subtarget->hasDQI())
10318 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10321 if (Subtarget->hasBWI())
10322 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10325 if (Subtarget->hasBWI())
10326 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10330 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10333 // Otherwise fall back on splitting.
10334 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10337 /// \brief Top-level lowering for x86 vector shuffles.
10339 /// This handles decomposition, canonicalization, and lowering of all x86
10340 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10341 /// above in helper routines. The canonicalization attempts to widen shuffles
10342 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10343 /// s.t. only one of the two inputs needs to be tested, etc.
10344 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10345 SelectionDAG &DAG) {
10346 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10347 ArrayRef<int> Mask = SVOp->getMask();
10348 SDValue V1 = Op.getOperand(0);
10349 SDValue V2 = Op.getOperand(1);
10350 MVT VT = Op.getSimpleValueType();
10351 int NumElements = VT.getVectorNumElements();
10354 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10356 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10357 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10358 if (V1IsUndef && V2IsUndef)
10359 return DAG.getUNDEF(VT);
10361 // When we create a shuffle node we put the UNDEF node to second operand,
10362 // but in some cases the first operand may be transformed to UNDEF.
10363 // In this case we should just commute the node.
10365 return DAG.getCommutedVectorShuffle(*SVOp);
10367 // Check for non-undef masks pointing at an undef vector and make the masks
10368 // undef as well. This makes it easier to match the shuffle based solely on
10372 if (M >= NumElements) {
10373 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10374 for (int &M : NewMask)
10375 if (M >= NumElements)
10377 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10380 // Try to collapse shuffles into using a vector type with fewer elements but
10381 // wider element types. We cap this to not form integers or floating point
10382 // elements wider than 64 bits, but it might be interesting to form i128
10383 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10384 SmallVector<int, 16> WidenedMask;
10385 if (VT.getScalarSizeInBits() < 64 &&
10386 canWidenShuffleElements(Mask, WidenedMask)) {
10387 MVT NewEltVT = VT.isFloatingPoint()
10388 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10389 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10390 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10391 // Make sure that the new vector type is legal. For example, v2f64 isn't
10393 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10394 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10395 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10396 return DAG.getNode(ISD::BITCAST, dl, VT,
10397 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10401 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10402 for (int M : SVOp->getMask())
10404 ++NumUndefElements;
10405 else if (M < NumElements)
10410 // Commute the shuffle as needed such that more elements come from V1 than
10411 // V2. This allows us to match the shuffle pattern strictly on how many
10412 // elements come from V1 without handling the symmetric cases.
10413 if (NumV2Elements > NumV1Elements)
10414 return DAG.getCommutedVectorShuffle(*SVOp);
10416 // When the number of V1 and V2 elements are the same, try to minimize the
10417 // number of uses of V2 in the low half of the vector. When that is tied,
10418 // ensure that the sum of indices for V1 is equal to or lower than the sum
10420 if (NumV1Elements == NumV2Elements) {
10421 int LowV1Elements = 0, LowV2Elements = 0;
10422 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10423 if (M >= NumElements)
10427 if (LowV2Elements > LowV1Elements) {
10428 return DAG.getCommutedVectorShuffle(*SVOp);
10429 } else if (LowV2Elements == LowV1Elements) {
10430 int SumV1Indices = 0, SumV2Indices = 0;
10431 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10432 if (SVOp->getMask()[i] >= NumElements)
10434 else if (SVOp->getMask()[i] >= 0)
10436 if (SumV2Indices < SumV1Indices)
10437 return DAG.getCommutedVectorShuffle(*SVOp);
10441 // For each vector width, delegate to a specialized lowering routine.
10442 if (VT.getSizeInBits() == 128)
10443 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10445 if (VT.getSizeInBits() == 256)
10446 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10448 // Force AVX-512 vectors to be scalarized for now.
10449 // FIXME: Implement AVX-512 support!
10450 if (VT.getSizeInBits() == 512)
10451 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10453 llvm_unreachable("Unimplemented!");
10457 //===----------------------------------------------------------------------===//
10458 // Legacy vector shuffle lowering
10460 // This code is the legacy code handling vector shuffles until the above
10461 // replaces its functionality and performance.
10462 //===----------------------------------------------------------------------===//
10464 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10465 bool hasInt256, unsigned *MaskOut = nullptr) {
10466 MVT EltVT = VT.getVectorElementType();
10468 // There is no blend with immediate in AVX-512.
10469 if (VT.is512BitVector())
10472 if (!hasSSE41 || EltVT == MVT::i8)
10474 if (!hasInt256 && VT == MVT::v16i16)
10477 unsigned MaskValue = 0;
10478 unsigned NumElems = VT.getVectorNumElements();
10479 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10480 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10481 unsigned NumElemsInLane = NumElems / NumLanes;
10483 // Blend for v16i16 should be symetric for the both lanes.
10484 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10486 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10487 int EltIdx = MaskVals[i];
10489 if ((EltIdx < 0 || EltIdx == (int)i) &&
10490 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10493 if (((unsigned)EltIdx == (i + NumElems)) &&
10494 (SndLaneEltIdx < 0 ||
10495 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10496 MaskValue |= (1 << i);
10502 *MaskOut = MaskValue;
10506 // Try to lower a shuffle node into a simple blend instruction.
10507 // This function assumes isBlendMask returns true for this
10508 // SuffleVectorSDNode
10509 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10510 unsigned MaskValue,
10511 const X86Subtarget *Subtarget,
10512 SelectionDAG &DAG) {
10513 MVT VT = SVOp->getSimpleValueType(0);
10514 MVT EltVT = VT.getVectorElementType();
10515 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10516 Subtarget->hasInt256() && "Trying to lower a "
10517 "VECTOR_SHUFFLE to a Blend but "
10518 "with the wrong mask"));
10519 SDValue V1 = SVOp->getOperand(0);
10520 SDValue V2 = SVOp->getOperand(1);
10522 unsigned NumElems = VT.getVectorNumElements();
10524 // Convert i32 vectors to floating point if it is not AVX2.
10525 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10527 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10528 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10530 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10531 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10534 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10535 DAG.getConstant(MaskValue, MVT::i32));
10536 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10539 /// In vector type \p VT, return true if the element at index \p InputIdx
10540 /// falls on a different 128-bit lane than \p OutputIdx.
10541 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10542 unsigned OutputIdx) {
10543 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10544 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10547 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10548 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10549 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10550 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10552 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10553 SelectionDAG &DAG) {
10554 MVT VT = V1.getSimpleValueType();
10555 assert(VT.is128BitVector() || VT.is256BitVector());
10557 MVT EltVT = VT.getVectorElementType();
10558 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10559 unsigned NumElts = VT.getVectorNumElements();
10561 SmallVector<SDValue, 32> PshufbMask;
10562 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10563 int InputIdx = MaskVals[OutputIdx];
10564 unsigned InputByteIdx;
10566 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10567 InputByteIdx = 0x80;
10569 // Cross lane is not allowed.
10570 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10572 InputByteIdx = InputIdx * EltSizeInBytes;
10573 // Index is an byte offset within the 128-bit lane.
10574 InputByteIdx &= 0xf;
10577 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10578 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10579 if (InputByteIdx != 0x80)
10584 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10586 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10587 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10588 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10591 // v8i16 shuffles - Prefer shuffles in the following order:
10592 // 1. [all] pshuflw, pshufhw, optional move
10593 // 2. [ssse3] 1 x pshufb
10594 // 3. [ssse3] 2 x pshufb + 1 x por
10595 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10597 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10598 SelectionDAG &DAG) {
10599 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10600 SDValue V1 = SVOp->getOperand(0);
10601 SDValue V2 = SVOp->getOperand(1);
10603 SmallVector<int, 8> MaskVals;
10605 // Determine if more than 1 of the words in each of the low and high quadwords
10606 // of the result come from the same quadword of one of the two inputs. Undef
10607 // mask values count as coming from any quadword, for better codegen.
10609 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10610 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10611 unsigned LoQuad[] = { 0, 0, 0, 0 };
10612 unsigned HiQuad[] = { 0, 0, 0, 0 };
10613 // Indices of quads used.
10614 std::bitset<4> InputQuads;
10615 for (unsigned i = 0; i < 8; ++i) {
10616 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10617 int EltIdx = SVOp->getMaskElt(i);
10618 MaskVals.push_back(EltIdx);
10626 ++Quad[EltIdx / 4];
10627 InputQuads.set(EltIdx / 4);
10630 int BestLoQuad = -1;
10631 unsigned MaxQuad = 1;
10632 for (unsigned i = 0; i < 4; ++i) {
10633 if (LoQuad[i] > MaxQuad) {
10635 MaxQuad = LoQuad[i];
10639 int BestHiQuad = -1;
10641 for (unsigned i = 0; i < 4; ++i) {
10642 if (HiQuad[i] > MaxQuad) {
10644 MaxQuad = HiQuad[i];
10648 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10649 // of the two input vectors, shuffle them into one input vector so only a
10650 // single pshufb instruction is necessary. If there are more than 2 input
10651 // quads, disable the next transformation since it does not help SSSE3.
10652 bool V1Used = InputQuads[0] || InputQuads[1];
10653 bool V2Used = InputQuads[2] || InputQuads[3];
10654 if (Subtarget->hasSSSE3()) {
10655 if (InputQuads.count() == 2 && V1Used && V2Used) {
10656 BestLoQuad = InputQuads[0] ? 0 : 1;
10657 BestHiQuad = InputQuads[2] ? 2 : 3;
10659 if (InputQuads.count() > 2) {
10665 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10666 // the shuffle mask. If a quad is scored as -1, that means that it contains
10667 // words from all 4 input quadwords.
10669 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10671 BestLoQuad < 0 ? 0 : BestLoQuad,
10672 BestHiQuad < 0 ? 1 : BestHiQuad
10674 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10675 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10676 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10677 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10679 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10680 // source words for the shuffle, to aid later transformations.
10681 bool AllWordsInNewV = true;
10682 bool InOrder[2] = { true, true };
10683 for (unsigned i = 0; i != 8; ++i) {
10684 int idx = MaskVals[i];
10686 InOrder[i/4] = false;
10687 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10689 AllWordsInNewV = false;
10693 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10694 if (AllWordsInNewV) {
10695 for (int i = 0; i != 8; ++i) {
10696 int idx = MaskVals[i];
10699 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10700 if ((idx != i) && idx < 4)
10702 if ((idx != i) && idx > 3)
10711 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10712 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10713 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10714 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10715 unsigned TargetMask = 0;
10716 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10717 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10718 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10719 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10720 getShufflePSHUFLWImmediate(SVOp);
10721 V1 = NewV.getOperand(0);
10722 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10726 // Promote splats to a larger type which usually leads to more efficient code.
10727 // FIXME: Is this true if pshufb is available?
10728 if (SVOp->isSplat())
10729 return PromoteSplat(SVOp, DAG);
10731 // If we have SSSE3, and all words of the result are from 1 input vector,
10732 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10733 // is present, fall back to case 4.
10734 if (Subtarget->hasSSSE3()) {
10735 SmallVector<SDValue,16> pshufbMask;
10737 // If we have elements from both input vectors, set the high bit of the
10738 // shuffle mask element to zero out elements that come from V2 in the V1
10739 // mask, and elements that come from V1 in the V2 mask, so that the two
10740 // results can be OR'd together.
10741 bool TwoInputs = V1Used && V2Used;
10742 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10744 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10746 // Calculate the shuffle mask for the second input, shuffle it, and
10747 // OR it with the first shuffled input.
10748 CommuteVectorShuffleMask(MaskVals, 8);
10749 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10750 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10751 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10754 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10755 // and update MaskVals with new element order.
10756 std::bitset<8> InOrder;
10757 if (BestLoQuad >= 0) {
10758 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10759 for (int i = 0; i != 4; ++i) {
10760 int idx = MaskVals[i];
10763 } else if ((idx / 4) == BestLoQuad) {
10764 MaskV[i] = idx & 3;
10768 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10771 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10772 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10773 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10774 NewV.getOperand(0),
10775 getShufflePSHUFLWImmediate(SVOp), DAG);
10779 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10780 // and update MaskVals with the new element order.
10781 if (BestHiQuad >= 0) {
10782 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10783 for (unsigned i = 4; i != 8; ++i) {
10784 int idx = MaskVals[i];
10787 } else if ((idx / 4) == BestHiQuad) {
10788 MaskV[i] = (idx & 3) + 4;
10792 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10795 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10797 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10798 NewV.getOperand(0),
10799 getShufflePSHUFHWImmediate(SVOp), DAG);
10803 // In case BestHi & BestLo were both -1, which means each quadword has a word
10804 // from each of the four input quadwords, calculate the InOrder bitvector now
10805 // before falling through to the insert/extract cleanup.
10806 if (BestLoQuad == -1 && BestHiQuad == -1) {
10808 for (int i = 0; i != 8; ++i)
10809 if (MaskVals[i] < 0 || MaskVals[i] == i)
10813 // The other elements are put in the right place using pextrw and pinsrw.
10814 for (unsigned i = 0; i != 8; ++i) {
10817 int EltIdx = MaskVals[i];
10820 SDValue ExtOp = (EltIdx < 8) ?
10821 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10822 DAG.getIntPtrConstant(EltIdx)) :
10823 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10824 DAG.getIntPtrConstant(EltIdx - 8));
10825 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10826 DAG.getIntPtrConstant(i));
10831 /// \brief v16i16 shuffles
10833 /// FIXME: We only support generation of a single pshufb currently. We can
10834 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10835 /// well (e.g 2 x pshufb + 1 x por).
10837 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10839 SDValue V1 = SVOp->getOperand(0);
10840 SDValue V2 = SVOp->getOperand(1);
10843 if (V2.getOpcode() != ISD::UNDEF)
10846 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10847 return getPSHUFB(MaskVals, V1, dl, DAG);
10850 // v16i8 shuffles - Prefer shuffles in the following order:
10851 // 1. [ssse3] 1 x pshufb
10852 // 2. [ssse3] 2 x pshufb + 1 x por
10853 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10854 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10855 const X86Subtarget* Subtarget,
10856 SelectionDAG &DAG) {
10857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10858 SDValue V1 = SVOp->getOperand(0);
10859 SDValue V2 = SVOp->getOperand(1);
10861 ArrayRef<int> MaskVals = SVOp->getMask();
10863 // Promote splats to a larger type which usually leads to more efficient code.
10864 // FIXME: Is this true if pshufb is available?
10865 if (SVOp->isSplat())
10866 return PromoteSplat(SVOp, DAG);
10868 // If we have SSSE3, case 1 is generated when all result bytes come from
10869 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10870 // present, fall back to case 3.
10872 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10873 if (Subtarget->hasSSSE3()) {
10874 SmallVector<SDValue,16> pshufbMask;
10876 // If all result elements are from one input vector, then only translate
10877 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10879 // Otherwise, we have elements from both input vectors, and must zero out
10880 // elements that come from V2 in the first mask, and V1 in the second mask
10881 // so that we can OR them together.
10882 for (unsigned i = 0; i != 16; ++i) {
10883 int EltIdx = MaskVals[i];
10884 if (EltIdx < 0 || EltIdx >= 16)
10886 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10888 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10889 DAG.getNode(ISD::BUILD_VECTOR, dl,
10890 MVT::v16i8, pshufbMask));
10892 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10893 // the 2nd operand if it's undefined or zero.
10894 if (V2.getOpcode() == ISD::UNDEF ||
10895 ISD::isBuildVectorAllZeros(V2.getNode()))
10898 // Calculate the shuffle mask for the second input, shuffle it, and
10899 // OR it with the first shuffled input.
10900 pshufbMask.clear();
10901 for (unsigned i = 0; i != 16; ++i) {
10902 int EltIdx = MaskVals[i];
10903 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10904 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10906 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10907 DAG.getNode(ISD::BUILD_VECTOR, dl,
10908 MVT::v16i8, pshufbMask));
10909 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10912 // No SSSE3 - Calculate in place words and then fix all out of place words
10913 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10914 // the 16 different words that comprise the two doublequadword input vectors.
10915 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10916 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10918 for (int i = 0; i != 8; ++i) {
10919 int Elt0 = MaskVals[i*2];
10920 int Elt1 = MaskVals[i*2+1];
10922 // This word of the result is all undef, skip it.
10923 if (Elt0 < 0 && Elt1 < 0)
10926 // This word of the result is already in the correct place, skip it.
10927 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10930 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10931 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10934 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10935 // using a single extract together, load it and store it.
10936 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10937 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10938 DAG.getIntPtrConstant(Elt1 / 2));
10939 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10940 DAG.getIntPtrConstant(i));
10944 // If Elt1 is defined, extract it from the appropriate source. If the
10945 // source byte is not also odd, shift the extracted word left 8 bits
10946 // otherwise clear the bottom 8 bits if we need to do an or.
10948 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10949 DAG.getIntPtrConstant(Elt1 / 2));
10950 if ((Elt1 & 1) == 0)
10951 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10953 TLI.getShiftAmountTy(InsElt.getValueType())));
10954 else if (Elt0 >= 0)
10955 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10956 DAG.getConstant(0xFF00, MVT::i16));
10958 // If Elt0 is defined, extract it from the appropriate source. If the
10959 // source byte is not also even, shift the extracted word right 8 bits. If
10960 // Elt1 was also defined, OR the extracted values together before
10961 // inserting them in the result.
10963 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10964 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10965 if ((Elt0 & 1) != 0)
10966 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10968 TLI.getShiftAmountTy(InsElt0.getValueType())));
10969 else if (Elt1 >= 0)
10970 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10971 DAG.getConstant(0x00FF, MVT::i16));
10972 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10975 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10976 DAG.getIntPtrConstant(i));
10978 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10981 // v32i8 shuffles - Translate to VPSHUFB if possible.
10983 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10984 const X86Subtarget *Subtarget,
10985 SelectionDAG &DAG) {
10986 MVT VT = SVOp->getSimpleValueType(0);
10987 SDValue V1 = SVOp->getOperand(0);
10988 SDValue V2 = SVOp->getOperand(1);
10990 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10992 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10993 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10994 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10996 // VPSHUFB may be generated if
10997 // (1) one of input vector is undefined or zeroinitializer.
10998 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10999 // And (2) the mask indexes don't cross the 128-bit lane.
11000 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11001 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11004 if (V1IsAllZero && !V2IsAllZero) {
11005 CommuteVectorShuffleMask(MaskVals, 32);
11008 return getPSHUFB(MaskVals, V1, dl, DAG);
11011 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11012 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11013 /// done when every pair / quad of shuffle mask elements point to elements in
11014 /// the right sequence. e.g.
11015 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11017 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11018 SelectionDAG &DAG) {
11019 MVT VT = SVOp->getSimpleValueType(0);
11021 unsigned NumElems = VT.getVectorNumElements();
11024 switch (VT.SimpleTy) {
11025 default: llvm_unreachable("Unexpected!");
11028 return SDValue(SVOp, 0);
11029 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11030 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11031 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11032 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11033 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11034 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11037 SmallVector<int, 8> MaskVec;
11038 for (unsigned i = 0; i != NumElems; i += Scale) {
11040 for (unsigned j = 0; j != Scale; ++j) {
11041 int EltIdx = SVOp->getMaskElt(i+j);
11045 StartIdx = (EltIdx / Scale);
11046 if (EltIdx != (int)(StartIdx*Scale + j))
11049 MaskVec.push_back(StartIdx);
11052 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11053 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11054 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11057 /// getVZextMovL - Return a zero-extending vector move low node.
11059 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11060 SDValue SrcOp, SelectionDAG &DAG,
11061 const X86Subtarget *Subtarget, SDLoc dl) {
11062 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11063 LoadSDNode *LD = nullptr;
11064 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11065 LD = dyn_cast<LoadSDNode>(SrcOp);
11067 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11069 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11070 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11071 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11072 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11073 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11075 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11076 return DAG.getNode(ISD::BITCAST, dl, VT,
11077 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11078 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11080 SrcOp.getOperand(0)
11086 return DAG.getNode(ISD::BITCAST, dl, VT,
11087 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11088 DAG.getNode(ISD::BITCAST, dl,
11092 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11093 /// which could not be matched by any known target speficic shuffle
11095 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11097 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11098 if (NewOp.getNode())
11101 MVT VT = SVOp->getSimpleValueType(0);
11103 unsigned NumElems = VT.getVectorNumElements();
11104 unsigned NumLaneElems = NumElems / 2;
11107 MVT EltVT = VT.getVectorElementType();
11108 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11111 SmallVector<int, 16> Mask;
11112 for (unsigned l = 0; l < 2; ++l) {
11113 // Build a shuffle mask for the output, discovering on the fly which
11114 // input vectors to use as shuffle operands (recorded in InputUsed).
11115 // If building a suitable shuffle vector proves too hard, then bail
11116 // out with UseBuildVector set.
11117 bool UseBuildVector = false;
11118 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11119 unsigned LaneStart = l * NumLaneElems;
11120 for (unsigned i = 0; i != NumLaneElems; ++i) {
11121 // The mask element. This indexes into the input.
11122 int Idx = SVOp->getMaskElt(i+LaneStart);
11124 // the mask element does not index into any input vector.
11125 Mask.push_back(-1);
11129 // The input vector this mask element indexes into.
11130 int Input = Idx / NumLaneElems;
11132 // Turn the index into an offset from the start of the input vector.
11133 Idx -= Input * NumLaneElems;
11135 // Find or create a shuffle vector operand to hold this input.
11137 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11138 if (InputUsed[OpNo] == Input)
11139 // This input vector is already an operand.
11141 if (InputUsed[OpNo] < 0) {
11142 // Create a new operand for this input vector.
11143 InputUsed[OpNo] = Input;
11148 if (OpNo >= array_lengthof(InputUsed)) {
11149 // More than two input vectors used! Give up on trying to create a
11150 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11151 UseBuildVector = true;
11155 // Add the mask index for the new shuffle vector.
11156 Mask.push_back(Idx + OpNo * NumLaneElems);
11159 if (UseBuildVector) {
11160 SmallVector<SDValue, 16> SVOps;
11161 for (unsigned i = 0; i != NumLaneElems; ++i) {
11162 // The mask element. This indexes into the input.
11163 int Idx = SVOp->getMaskElt(i+LaneStart);
11165 SVOps.push_back(DAG.getUNDEF(EltVT));
11169 // The input vector this mask element indexes into.
11170 int Input = Idx / NumElems;
11172 // Turn the index into an offset from the start of the input vector.
11173 Idx -= Input * NumElems;
11175 // Extract the vector element by hand.
11176 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11177 SVOp->getOperand(Input),
11178 DAG.getIntPtrConstant(Idx)));
11181 // Construct the output using a BUILD_VECTOR.
11182 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11183 } else if (InputUsed[0] < 0) {
11184 // No input vectors were used! The result is undefined.
11185 Output[l] = DAG.getUNDEF(NVT);
11187 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11188 (InputUsed[0] % 2) * NumLaneElems,
11190 // If only one input was used, use an undefined vector for the other.
11191 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11192 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11193 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11194 // At least one input vector was used. Create a new shuffle vector.
11195 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11201 // Concatenate the result back
11202 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11205 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11206 /// 4 elements, and match them with several different shuffle types.
11208 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11209 SDValue V1 = SVOp->getOperand(0);
11210 SDValue V2 = SVOp->getOperand(1);
11212 MVT VT = SVOp->getSimpleValueType(0);
11214 assert(VT.is128BitVector() && "Unsupported vector size");
11216 std::pair<int, int> Locs[4];
11217 int Mask1[] = { -1, -1, -1, -1 };
11218 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11220 unsigned NumHi = 0;
11221 unsigned NumLo = 0;
11222 for (unsigned i = 0; i != 4; ++i) {
11223 int Idx = PermMask[i];
11225 Locs[i] = std::make_pair(-1, -1);
11227 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11229 Locs[i] = std::make_pair(0, NumLo);
11230 Mask1[NumLo] = Idx;
11233 Locs[i] = std::make_pair(1, NumHi);
11235 Mask1[2+NumHi] = Idx;
11241 if (NumLo <= 2 && NumHi <= 2) {
11242 // If no more than two elements come from either vector. This can be
11243 // implemented with two shuffles. First shuffle gather the elements.
11244 // The second shuffle, which takes the first shuffle as both of its
11245 // vector operands, put the elements into the right order.
11246 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11248 int Mask2[] = { -1, -1, -1, -1 };
11250 for (unsigned i = 0; i != 4; ++i)
11251 if (Locs[i].first != -1) {
11252 unsigned Idx = (i < 2) ? 0 : 4;
11253 Idx += Locs[i].first * 2 + Locs[i].second;
11257 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11260 if (NumLo == 3 || NumHi == 3) {
11261 // Otherwise, we must have three elements from one vector, call it X, and
11262 // one element from the other, call it Y. First, use a shufps to build an
11263 // intermediate vector with the one element from Y and the element from X
11264 // that will be in the same half in the final destination (the indexes don't
11265 // matter). Then, use a shufps to build the final vector, taking the half
11266 // containing the element from Y from the intermediate, and the other half
11269 // Normalize it so the 3 elements come from V1.
11270 CommuteVectorShuffleMask(PermMask, 4);
11274 // Find the element from V2.
11276 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11277 int Val = PermMask[HiIndex];
11284 Mask1[0] = PermMask[HiIndex];
11286 Mask1[2] = PermMask[HiIndex^1];
11288 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11290 if (HiIndex >= 2) {
11291 Mask1[0] = PermMask[0];
11292 Mask1[1] = PermMask[1];
11293 Mask1[2] = HiIndex & 1 ? 6 : 4;
11294 Mask1[3] = HiIndex & 1 ? 4 : 6;
11295 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11298 Mask1[0] = HiIndex & 1 ? 2 : 0;
11299 Mask1[1] = HiIndex & 1 ? 0 : 2;
11300 Mask1[2] = PermMask[2];
11301 Mask1[3] = PermMask[3];
11306 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11309 // Break it into (shuffle shuffle_hi, shuffle_lo).
11310 int LoMask[] = { -1, -1, -1, -1 };
11311 int HiMask[] = { -1, -1, -1, -1 };
11313 int *MaskPtr = LoMask;
11314 unsigned MaskIdx = 0;
11315 unsigned LoIdx = 0;
11316 unsigned HiIdx = 2;
11317 for (unsigned i = 0; i != 4; ++i) {
11324 int Idx = PermMask[i];
11326 Locs[i] = std::make_pair(-1, -1);
11327 } else if (Idx < 4) {
11328 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11329 MaskPtr[LoIdx] = Idx;
11332 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11333 MaskPtr[HiIdx] = Idx;
11338 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11339 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11340 int MaskOps[] = { -1, -1, -1, -1 };
11341 for (unsigned i = 0; i != 4; ++i)
11342 if (Locs[i].first != -1)
11343 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11344 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11347 static bool MayFoldVectorLoad(SDValue V) {
11348 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11349 V = V.getOperand(0);
11351 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11352 V = V.getOperand(0);
11353 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11354 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11355 // BUILD_VECTOR (load), undef
11356 V = V.getOperand(0);
11358 return MayFoldLoad(V);
11362 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11363 MVT VT = Op.getSimpleValueType();
11365 // Canonizalize to v2f64.
11366 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11367 return DAG.getNode(ISD::BITCAST, dl, VT,
11368 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11373 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11375 SDValue V1 = Op.getOperand(0);
11376 SDValue V2 = Op.getOperand(1);
11377 MVT VT = Op.getSimpleValueType();
11379 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11381 if (HasSSE2 && VT == MVT::v2f64)
11382 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11384 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11385 return DAG.getNode(ISD::BITCAST, dl, VT,
11386 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11387 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11388 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11392 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11393 SDValue V1 = Op.getOperand(0);
11394 SDValue V2 = Op.getOperand(1);
11395 MVT VT = Op.getSimpleValueType();
11397 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11398 "unsupported shuffle type");
11400 if (V2.getOpcode() == ISD::UNDEF)
11404 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11408 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11409 SDValue V1 = Op.getOperand(0);
11410 SDValue V2 = Op.getOperand(1);
11411 MVT VT = Op.getSimpleValueType();
11412 unsigned NumElems = VT.getVectorNumElements();
11414 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11415 // operand of these instructions is only memory, so check if there's a
11416 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11418 bool CanFoldLoad = false;
11420 // Trivial case, when V2 comes from a load.
11421 if (MayFoldVectorLoad(V2))
11422 CanFoldLoad = true;
11424 // When V1 is a load, it can be folded later into a store in isel, example:
11425 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11427 // (MOVLPSmr addr:$src1, VR128:$src2)
11428 // So, recognize this potential and also use MOVLPS or MOVLPD
11429 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11430 CanFoldLoad = true;
11432 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11434 if (HasSSE2 && NumElems == 2)
11435 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11438 // If we don't care about the second element, proceed to use movss.
11439 if (SVOp->getMaskElt(1) != -1)
11440 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11443 // movl and movlp will both match v2i64, but v2i64 is never matched by
11444 // movl earlier because we make it strict to avoid messing with the movlp load
11445 // folding logic (see the code above getMOVLP call). Match it here then,
11446 // this is horrible, but will stay like this until we move all shuffle
11447 // matching to x86 specific nodes. Note that for the 1st condition all
11448 // types are matched with movsd.
11450 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11451 // as to remove this logic from here, as much as possible
11452 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11453 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11454 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11457 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11459 // Invert the operand order and use SHUFPS to match it.
11460 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11461 getShuffleSHUFImmediate(SVOp), DAG);
11464 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11465 SelectionDAG &DAG) {
11467 MVT VT = Load->getSimpleValueType(0);
11468 MVT EVT = VT.getVectorElementType();
11469 SDValue Addr = Load->getOperand(1);
11470 SDValue NewAddr = DAG.getNode(
11471 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11472 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11475 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11476 DAG.getMachineFunction().getMachineMemOperand(
11477 Load->getMemOperand(), 0, EVT.getStoreSize()));
11481 // It is only safe to call this function if isINSERTPSMask is true for
11482 // this shufflevector mask.
11483 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11484 SelectionDAG &DAG) {
11485 // Generate an insertps instruction when inserting an f32 from memory onto a
11486 // v4f32 or when copying a member from one v4f32 to another.
11487 // We also use it for transferring i32 from one register to another,
11488 // since it simply copies the same bits.
11489 // If we're transferring an i32 from memory to a specific element in a
11490 // register, we output a generic DAG that will match the PINSRD
11492 MVT VT = SVOp->getSimpleValueType(0);
11493 MVT EVT = VT.getVectorElementType();
11494 SDValue V1 = SVOp->getOperand(0);
11495 SDValue V2 = SVOp->getOperand(1);
11496 auto Mask = SVOp->getMask();
11497 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11498 "unsupported vector type for insertps/pinsrd");
11500 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11501 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11502 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11506 unsigned DestIndex;
11510 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11513 // If we have 1 element from each vector, we have to check if we're
11514 // changing V1's element's place. If so, we're done. Otherwise, we
11515 // should assume we're changing V2's element's place and behave
11517 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11518 assert(DestIndex <= INT32_MAX && "truncated destination index");
11519 if (FromV1 == FromV2 &&
11520 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11524 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11527 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11528 "More than one element from V1 and from V2, or no elements from one "
11529 "of the vectors. This case should not have returned true from "
11534 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11537 // Get an index into the source vector in the range [0,4) (the mask is
11538 // in the range [0,8) because it can address V1 and V2)
11539 unsigned SrcIndex = Mask[DestIndex] % 4;
11540 if (MayFoldLoad(From)) {
11541 // Trivial case, when From comes from a load and is only used by the
11542 // shuffle. Make it use insertps from the vector that we need from that
11545 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11546 if (!NewLoad.getNode())
11549 if (EVT == MVT::f32) {
11550 // Create this as a scalar to vector to match the instruction pattern.
11551 SDValue LoadScalarToVector =
11552 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11553 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11554 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11556 } else { // EVT == MVT::i32
11557 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11558 // instruction, to match the PINSRD instruction, which loads an i32 to a
11559 // certain vector element.
11560 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11561 DAG.getConstant(DestIndex, MVT::i32));
11565 // Vector-element-to-vector
11566 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11567 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11570 // Reduce a vector shuffle to zext.
11571 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11572 SelectionDAG &DAG) {
11573 // PMOVZX is only available from SSE41.
11574 if (!Subtarget->hasSSE41())
11577 MVT VT = Op.getSimpleValueType();
11579 // Only AVX2 support 256-bit vector integer extending.
11580 if (!Subtarget->hasInt256() && VT.is256BitVector())
11583 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11585 SDValue V1 = Op.getOperand(0);
11586 SDValue V2 = Op.getOperand(1);
11587 unsigned NumElems = VT.getVectorNumElements();
11589 // Extending is an unary operation and the element type of the source vector
11590 // won't be equal to or larger than i64.
11591 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11592 VT.getVectorElementType() == MVT::i64)
11595 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11596 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11597 while ((1U << Shift) < NumElems) {
11598 if (SVOp->getMaskElt(1U << Shift) == 1)
11601 // The maximal ratio is 8, i.e. from i8 to i64.
11606 // Check the shuffle mask.
11607 unsigned Mask = (1U << Shift) - 1;
11608 for (unsigned i = 0; i != NumElems; ++i) {
11609 int EltIdx = SVOp->getMaskElt(i);
11610 if ((i & Mask) != 0 && EltIdx != -1)
11612 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11616 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11617 MVT NeVT = MVT::getIntegerVT(NBits);
11618 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11620 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11623 return DAG.getNode(ISD::BITCAST, DL, VT,
11624 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11627 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11628 SelectionDAG &DAG) {
11629 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11630 MVT VT = Op.getSimpleValueType();
11632 SDValue V1 = Op.getOperand(0);
11633 SDValue V2 = Op.getOperand(1);
11635 if (isZeroShuffle(SVOp))
11636 return getZeroVector(VT, Subtarget, DAG, dl);
11638 // Handle splat operations
11639 if (SVOp->isSplat()) {
11640 // Use vbroadcast whenever the splat comes from a foldable load
11641 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11642 if (Broadcast.getNode())
11646 // Check integer expanding shuffles.
11647 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11648 if (NewOp.getNode())
11651 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11653 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11654 VT == MVT::v32i8) {
11655 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11656 if (NewOp.getNode())
11657 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11658 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11659 // FIXME: Figure out a cleaner way to do this.
11660 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11661 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11662 if (NewOp.getNode()) {
11663 MVT NewVT = NewOp.getSimpleValueType();
11664 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11665 NewVT, true, false))
11666 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11669 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11670 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11671 if (NewOp.getNode()) {
11672 MVT NewVT = NewOp.getSimpleValueType();
11673 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11674 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11683 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11685 SDValue V1 = Op.getOperand(0);
11686 SDValue V2 = Op.getOperand(1);
11687 MVT VT = Op.getSimpleValueType();
11689 unsigned NumElems = VT.getVectorNumElements();
11690 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11691 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11692 bool V1IsSplat = false;
11693 bool V2IsSplat = false;
11694 bool HasSSE2 = Subtarget->hasSSE2();
11695 bool HasFp256 = Subtarget->hasFp256();
11696 bool HasInt256 = Subtarget->hasInt256();
11697 MachineFunction &MF = DAG.getMachineFunction();
11698 bool OptForSize = MF.getFunction()->getAttributes().
11699 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11701 // Check if we should use the experimental vector shuffle lowering. If so,
11702 // delegate completely to that code path.
11703 if (ExperimentalVectorShuffleLowering)
11704 return lowerVectorShuffle(Op, Subtarget, DAG);
11706 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11708 if (V1IsUndef && V2IsUndef)
11709 return DAG.getUNDEF(VT);
11711 // When we create a shuffle node we put the UNDEF node to second operand,
11712 // but in some cases the first operand may be transformed to UNDEF.
11713 // In this case we should just commute the node.
11715 return DAG.getCommutedVectorShuffle(*SVOp);
11717 // Vector shuffle lowering takes 3 steps:
11719 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11720 // narrowing and commutation of operands should be handled.
11721 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11723 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11724 // so the shuffle can be broken into other shuffles and the legalizer can
11725 // try the lowering again.
11727 // The general idea is that no vector_shuffle operation should be left to
11728 // be matched during isel, all of them must be converted to a target specific
11731 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11732 // narrowing and commutation of operands should be handled. The actual code
11733 // doesn't include all of those, work in progress...
11734 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11735 if (NewOp.getNode())
11738 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11740 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11741 // unpckh_undef). Only use pshufd if speed is more important than size.
11742 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11743 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11744 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11745 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11747 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11748 V2IsUndef && MayFoldVectorLoad(V1))
11749 return getMOVDDup(Op, dl, V1, DAG);
11751 if (isMOVHLPS_v_undef_Mask(M, VT))
11752 return getMOVHighToLow(Op, dl, DAG);
11754 // Use to match splats
11755 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11756 (VT == MVT::v2f64 || VT == MVT::v2i64))
11757 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11759 if (isPSHUFDMask(M, VT)) {
11760 // The actual implementation will match the mask in the if above and then
11761 // during isel it can match several different instructions, not only pshufd
11762 // as its name says, sad but true, emulate the behavior for now...
11763 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11764 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11766 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11768 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11769 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11771 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11772 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11775 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11779 if (isPALIGNRMask(M, VT, Subtarget))
11780 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11781 getShufflePALIGNRImmediate(SVOp),
11784 if (isVALIGNMask(M, VT, Subtarget))
11785 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11786 getShuffleVALIGNImmediate(SVOp),
11789 // Check if this can be converted into a logical shift.
11790 bool isLeft = false;
11791 unsigned ShAmt = 0;
11793 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11794 if (isShift && ShVal.hasOneUse()) {
11795 // If the shifted value has multiple uses, it may be cheaper to use
11796 // v_set0 + movlhps or movhlps, etc.
11797 MVT EltVT = VT.getVectorElementType();
11798 ShAmt *= EltVT.getSizeInBits();
11799 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11802 if (isMOVLMask(M, VT)) {
11803 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11804 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11805 if (!isMOVLPMask(M, VT)) {
11806 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11807 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11809 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11810 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11814 // FIXME: fold these into legal mask.
11815 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11816 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11818 if (isMOVHLPSMask(M, VT))
11819 return getMOVHighToLow(Op, dl, DAG);
11821 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11822 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11824 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11825 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11827 if (isMOVLPMask(M, VT))
11828 return getMOVLP(Op, dl, DAG, HasSSE2);
11830 if (ShouldXformToMOVHLPS(M, VT) ||
11831 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11832 return DAG.getCommutedVectorShuffle(*SVOp);
11835 // No better options. Use a vshldq / vsrldq.
11836 MVT EltVT = VT.getVectorElementType();
11837 ShAmt *= EltVT.getSizeInBits();
11838 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11841 bool Commuted = false;
11842 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11843 // 1,1,1,1 -> v8i16 though.
11844 BitVector UndefElements;
11845 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11846 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11848 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11849 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11852 // Canonicalize the splat or undef, if present, to be on the RHS.
11853 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11854 CommuteVectorShuffleMask(M, NumElems);
11856 std::swap(V1IsSplat, V2IsSplat);
11860 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11861 // Shuffling low element of v1 into undef, just return v1.
11864 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11865 // the instruction selector will not match, so get a canonical MOVL with
11866 // swapped operands to undo the commute.
11867 return getMOVL(DAG, dl, VT, V2, V1);
11870 if (isUNPCKLMask(M, VT, HasInt256))
11871 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11873 if (isUNPCKHMask(M, VT, HasInt256))
11874 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11877 // Normalize mask so all entries that point to V2 points to its first
11878 // element then try to match unpck{h|l} again. If match, return a
11879 // new vector_shuffle with the corrected mask.p
11880 SmallVector<int, 8> NewMask(M.begin(), M.end());
11881 NormalizeMask(NewMask, NumElems);
11882 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11883 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11884 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11885 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11889 // Commute is back and try unpck* again.
11890 // FIXME: this seems wrong.
11891 CommuteVectorShuffleMask(M, NumElems);
11893 std::swap(V1IsSplat, V2IsSplat);
11895 if (isUNPCKLMask(M, VT, HasInt256))
11896 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11898 if (isUNPCKHMask(M, VT, HasInt256))
11899 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11902 // Normalize the node to match x86 shuffle ops if needed
11903 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11904 return DAG.getCommutedVectorShuffle(*SVOp);
11906 // The checks below are all present in isShuffleMaskLegal, but they are
11907 // inlined here right now to enable us to directly emit target specific
11908 // nodes, and remove one by one until they don't return Op anymore.
11910 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11911 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11912 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11913 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11916 if (isPSHUFHWMask(M, VT, HasInt256))
11917 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11918 getShufflePSHUFHWImmediate(SVOp),
11921 if (isPSHUFLWMask(M, VT, HasInt256))
11922 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11923 getShufflePSHUFLWImmediate(SVOp),
11926 unsigned MaskValue;
11927 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11929 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11931 if (isSHUFPMask(M, VT))
11932 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11933 getShuffleSHUFImmediate(SVOp), DAG);
11935 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11936 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11937 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11938 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11940 //===--------------------------------------------------------------------===//
11941 // Generate target specific nodes for 128 or 256-bit shuffles only
11942 // supported in the AVX instruction set.
11945 // Handle VMOVDDUPY permutations
11946 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11947 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11949 // Handle VPERMILPS/D* permutations
11950 if (isVPERMILPMask(M, VT)) {
11951 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11952 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11953 getShuffleSHUFImmediate(SVOp), DAG);
11954 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11955 getShuffleSHUFImmediate(SVOp), DAG);
11959 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11960 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11961 Idx*(NumElems/2), DAG, dl);
11963 // Handle VPERM2F128/VPERM2I128 permutations
11964 if (isVPERM2X128Mask(M, VT, HasFp256))
11965 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11966 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11968 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11969 return getINSERTPS(SVOp, dl, DAG);
11972 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11973 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11975 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11976 VT.is512BitVector()) {
11977 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11978 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11979 SmallVector<SDValue, 16> permclMask;
11980 for (unsigned i = 0; i != NumElems; ++i) {
11981 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11984 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11986 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11987 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11988 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11989 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11990 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11993 //===--------------------------------------------------------------------===//
11994 // Since no target specific shuffle was selected for this generic one,
11995 // lower it into other known shuffles. FIXME: this isn't true yet, but
11996 // this is the plan.
11999 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12000 if (VT == MVT::v8i16) {
12001 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12002 if (NewOp.getNode())
12006 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12007 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12008 if (NewOp.getNode())
12012 if (VT == MVT::v16i8) {
12013 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12014 if (NewOp.getNode())
12018 if (VT == MVT::v32i8) {
12019 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12020 if (NewOp.getNode())
12024 // Handle all 128-bit wide vectors with 4 elements, and match them with
12025 // several different shuffle types.
12026 if (NumElems == 4 && VT.is128BitVector())
12027 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12029 // Handle general 256-bit shuffles
12030 if (VT.is256BitVector())
12031 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12036 // This function assumes its argument is a BUILD_VECTOR of constants or
12037 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12039 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12040 unsigned &MaskValue) {
12042 unsigned NumElems = BuildVector->getNumOperands();
12043 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12044 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12045 unsigned NumElemsInLane = NumElems / NumLanes;
12047 // Blend for v16i16 should be symetric for the both lanes.
12048 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12049 SDValue EltCond = BuildVector->getOperand(i);
12050 SDValue SndLaneEltCond =
12051 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12053 int Lane1Cond = -1, Lane2Cond = -1;
12054 if (isa<ConstantSDNode>(EltCond))
12055 Lane1Cond = !isZero(EltCond);
12056 if (isa<ConstantSDNode>(SndLaneEltCond))
12057 Lane2Cond = !isZero(SndLaneEltCond);
12059 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12060 // Lane1Cond != 0, means we want the first argument.
12061 // Lane1Cond == 0, means we want the second argument.
12062 // The encoding of this argument is 0 for the first argument, 1
12063 // for the second. Therefore, invert the condition.
12064 MaskValue |= !Lane1Cond << i;
12065 else if (Lane1Cond < 0)
12066 MaskValue |= !Lane2Cond << i;
12073 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12075 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12076 SelectionDAG &DAG) {
12077 SDValue Cond = Op.getOperand(0);
12078 SDValue LHS = Op.getOperand(1);
12079 SDValue RHS = Op.getOperand(2);
12081 MVT VT = Op.getSimpleValueType();
12082 MVT EltVT = VT.getVectorElementType();
12083 unsigned NumElems = VT.getVectorNumElements();
12085 // There is no blend with immediate in AVX-512.
12086 if (VT.is512BitVector())
12089 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12091 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12094 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12097 // Check the mask for BLEND and build the value.
12098 unsigned MaskValue = 0;
12099 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12102 // Convert i32 vectors to floating point if it is not AVX2.
12103 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12105 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12106 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12108 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12109 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12112 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12113 DAG.getConstant(MaskValue, MVT::i32));
12114 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12117 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12118 // A vselect where all conditions and data are constants can be optimized into
12119 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12120 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12121 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12122 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12125 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12126 if (BlendOp.getNode())
12129 // Some types for vselect were previously set to Expand, not Legal or
12130 // Custom. Return an empty SDValue so we fall-through to Expand, after
12131 // the Custom lowering phase.
12132 MVT VT = Op.getSimpleValueType();
12133 switch (VT.SimpleTy) {
12138 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12143 // We couldn't create a "Blend with immediate" node.
12144 // This node should still be legal, but we'll have to emit a blendv*
12149 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12150 MVT VT = Op.getSimpleValueType();
12153 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12156 if (VT.getSizeInBits() == 8) {
12157 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12158 Op.getOperand(0), Op.getOperand(1));
12159 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12160 DAG.getValueType(VT));
12161 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12164 if (VT.getSizeInBits() == 16) {
12165 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12166 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12168 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12169 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12170 DAG.getNode(ISD::BITCAST, dl,
12173 Op.getOperand(1)));
12174 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12175 Op.getOperand(0), Op.getOperand(1));
12176 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12177 DAG.getValueType(VT));
12178 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12181 if (VT == MVT::f32) {
12182 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12183 // the result back to FR32 register. It's only worth matching if the
12184 // result has a single use which is a store or a bitcast to i32. And in
12185 // the case of a store, it's not worth it if the index is a constant 0,
12186 // because a MOVSSmr can be used instead, which is smaller and faster.
12187 if (!Op.hasOneUse())
12189 SDNode *User = *Op.getNode()->use_begin();
12190 if ((User->getOpcode() != ISD::STORE ||
12191 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12192 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12193 (User->getOpcode() != ISD::BITCAST ||
12194 User->getValueType(0) != MVT::i32))
12196 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12197 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12200 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12203 if (VT == MVT::i32 || VT == MVT::i64) {
12204 // ExtractPS/pextrq works with constant index.
12205 if (isa<ConstantSDNode>(Op.getOperand(1)))
12211 /// Extract one bit from mask vector, like v16i1 or v8i1.
12212 /// AVX-512 feature.
12214 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12215 SDValue Vec = Op.getOperand(0);
12217 MVT VecVT = Vec.getSimpleValueType();
12218 SDValue Idx = Op.getOperand(1);
12219 MVT EltVT = Op.getSimpleValueType();
12221 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12223 // variable index can't be handled in mask registers,
12224 // extend vector to VR512
12225 if (!isa<ConstantSDNode>(Idx)) {
12226 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12227 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12228 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12229 ExtVT.getVectorElementType(), Ext, Idx);
12230 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12233 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12234 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12235 unsigned MaxSift = rc->getSize()*8 - 1;
12236 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12237 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12238 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12239 DAG.getConstant(MaxSift, MVT::i8));
12240 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12241 DAG.getIntPtrConstant(0));
12245 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12246 SelectionDAG &DAG) const {
12248 SDValue Vec = Op.getOperand(0);
12249 MVT VecVT = Vec.getSimpleValueType();
12250 SDValue Idx = Op.getOperand(1);
12252 if (Op.getSimpleValueType() == MVT::i1)
12253 return ExtractBitFromMaskVector(Op, DAG);
12255 if (!isa<ConstantSDNode>(Idx)) {
12256 if (VecVT.is512BitVector() ||
12257 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12258 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12261 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12262 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12263 MaskEltVT.getSizeInBits());
12265 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12266 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12267 getZeroVector(MaskVT, Subtarget, DAG, dl),
12268 Idx, DAG.getConstant(0, getPointerTy()));
12269 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12270 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12271 Perm, DAG.getConstant(0, getPointerTy()));
12276 // If this is a 256-bit vector result, first extract the 128-bit vector and
12277 // then extract the element from the 128-bit vector.
12278 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12280 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12281 // Get the 128-bit vector.
12282 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12283 MVT EltVT = VecVT.getVectorElementType();
12285 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12287 //if (IdxVal >= NumElems/2)
12288 // IdxVal -= NumElems/2;
12289 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12290 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12291 DAG.getConstant(IdxVal, MVT::i32));
12294 assert(VecVT.is128BitVector() && "Unexpected vector length");
12296 if (Subtarget->hasSSE41()) {
12297 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12302 MVT VT = Op.getSimpleValueType();
12303 // TODO: handle v16i8.
12304 if (VT.getSizeInBits() == 16) {
12305 SDValue Vec = Op.getOperand(0);
12306 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12308 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12309 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12310 DAG.getNode(ISD::BITCAST, dl,
12312 Op.getOperand(1)));
12313 // Transform it so it match pextrw which produces a 32-bit result.
12314 MVT EltVT = MVT::i32;
12315 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12316 Op.getOperand(0), Op.getOperand(1));
12317 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12318 DAG.getValueType(VT));
12319 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12322 if (VT.getSizeInBits() == 32) {
12323 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12327 // SHUFPS the element to the lowest double word, then movss.
12328 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12329 MVT VVT = Op.getOperand(0).getSimpleValueType();
12330 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12331 DAG.getUNDEF(VVT), Mask);
12332 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12333 DAG.getIntPtrConstant(0));
12336 if (VT.getSizeInBits() == 64) {
12337 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12338 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12339 // to match extract_elt for f64.
12340 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12344 // UNPCKHPD the element to the lowest double word, then movsd.
12345 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12346 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12347 int Mask[2] = { 1, -1 };
12348 MVT VVT = Op.getOperand(0).getSimpleValueType();
12349 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12350 DAG.getUNDEF(VVT), Mask);
12351 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12352 DAG.getIntPtrConstant(0));
12358 /// Insert one bit to mask vector, like v16i1 or v8i1.
12359 /// AVX-512 feature.
12361 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12363 SDValue Vec = Op.getOperand(0);
12364 SDValue Elt = Op.getOperand(1);
12365 SDValue Idx = Op.getOperand(2);
12366 MVT VecVT = Vec.getSimpleValueType();
12368 if (!isa<ConstantSDNode>(Idx)) {
12369 // Non constant index. Extend source and destination,
12370 // insert element and then truncate the result.
12371 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12372 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12373 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12374 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12375 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12376 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12379 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12380 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12381 if (Vec.getOpcode() == ISD::UNDEF)
12382 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12383 DAG.getConstant(IdxVal, MVT::i8));
12384 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12385 unsigned MaxSift = rc->getSize()*8 - 1;
12386 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12387 DAG.getConstant(MaxSift, MVT::i8));
12388 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12389 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12390 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12393 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12394 SelectionDAG &DAG) const {
12395 MVT VT = Op.getSimpleValueType();
12396 MVT EltVT = VT.getVectorElementType();
12398 if (EltVT == MVT::i1)
12399 return InsertBitToMaskVector(Op, DAG);
12402 SDValue N0 = Op.getOperand(0);
12403 SDValue N1 = Op.getOperand(1);
12404 SDValue N2 = Op.getOperand(2);
12405 if (!isa<ConstantSDNode>(N2))
12407 auto *N2C = cast<ConstantSDNode>(N2);
12408 unsigned IdxVal = N2C->getZExtValue();
12410 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12411 // into that, and then insert the subvector back into the result.
12412 if (VT.is256BitVector() || VT.is512BitVector()) {
12413 // Get the desired 128-bit vector half.
12414 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12416 // Insert the element into the desired half.
12417 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12418 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12420 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12421 DAG.getConstant(IdxIn128, MVT::i32));
12423 // Insert the changed part back to the 256-bit vector
12424 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12426 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12428 if (Subtarget->hasSSE41()) {
12429 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12431 if (VT == MVT::v8i16) {
12432 Opc = X86ISD::PINSRW;
12434 assert(VT == MVT::v16i8);
12435 Opc = X86ISD::PINSRB;
12438 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12440 if (N1.getValueType() != MVT::i32)
12441 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12442 if (N2.getValueType() != MVT::i32)
12443 N2 = DAG.getIntPtrConstant(IdxVal);
12444 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12447 if (EltVT == MVT::f32) {
12448 // Bits [7:6] of the constant are the source select. This will always be
12449 // zero here. The DAG Combiner may combine an extract_elt index into
12451 // bits. For example (insert (extract, 3), 2) could be matched by
12453 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12454 // Bits [5:4] of the constant are the destination select. This is the
12455 // value of the incoming immediate.
12456 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12457 // combine either bitwise AND or insert of float 0.0 to set these bits.
12458 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12459 // Create this as a scalar to vector..
12460 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12461 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12464 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12465 // PINSR* works with constant index.
12470 if (EltVT == MVT::i8)
12473 if (EltVT.getSizeInBits() == 16) {
12474 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12475 // as its second argument.
12476 if (N1.getValueType() != MVT::i32)
12477 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12478 if (N2.getValueType() != MVT::i32)
12479 N2 = DAG.getIntPtrConstant(IdxVal);
12480 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12485 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12487 MVT OpVT = Op.getSimpleValueType();
12489 // If this is a 256-bit vector result, first insert into a 128-bit
12490 // vector and then insert into the 256-bit vector.
12491 if (!OpVT.is128BitVector()) {
12492 // Insert into a 128-bit vector.
12493 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12494 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12495 OpVT.getVectorNumElements() / SizeFactor);
12497 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12499 // Insert the 128-bit vector.
12500 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12503 if (OpVT == MVT::v1i64 &&
12504 Op.getOperand(0).getValueType() == MVT::i64)
12505 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12507 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12508 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12509 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12510 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12513 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12514 // a simple subregister reference or explicit instructions to grab
12515 // upper bits of a vector.
12516 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12517 SelectionDAG &DAG) {
12519 SDValue In = Op.getOperand(0);
12520 SDValue Idx = Op.getOperand(1);
12521 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12522 MVT ResVT = Op.getSimpleValueType();
12523 MVT InVT = In.getSimpleValueType();
12525 if (Subtarget->hasFp256()) {
12526 if (ResVT.is128BitVector() &&
12527 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12528 isa<ConstantSDNode>(Idx)) {
12529 return Extract128BitVector(In, IdxVal, DAG, dl);
12531 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12532 isa<ConstantSDNode>(Idx)) {
12533 return Extract256BitVector(In, IdxVal, DAG, dl);
12539 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12540 // simple superregister reference or explicit instructions to insert
12541 // the upper bits of a vector.
12542 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12543 SelectionDAG &DAG) {
12544 if (Subtarget->hasFp256()) {
12545 SDLoc dl(Op.getNode());
12546 SDValue Vec = Op.getNode()->getOperand(0);
12547 SDValue SubVec = Op.getNode()->getOperand(1);
12548 SDValue Idx = Op.getNode()->getOperand(2);
12550 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12551 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12552 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12553 isa<ConstantSDNode>(Idx)) {
12554 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12555 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12558 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12559 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12560 isa<ConstantSDNode>(Idx)) {
12561 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12562 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12568 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12569 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12570 // one of the above mentioned nodes. It has to be wrapped because otherwise
12571 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12572 // be used to form addressing mode. These wrapped nodes will be selected
12575 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12576 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12578 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12579 // global base reg.
12580 unsigned char OpFlag = 0;
12581 unsigned WrapperKind = X86ISD::Wrapper;
12582 CodeModel::Model M = DAG.getTarget().getCodeModel();
12584 if (Subtarget->isPICStyleRIPRel() &&
12585 (M == CodeModel::Small || M == CodeModel::Kernel))
12586 WrapperKind = X86ISD::WrapperRIP;
12587 else if (Subtarget->isPICStyleGOT())
12588 OpFlag = X86II::MO_GOTOFF;
12589 else if (Subtarget->isPICStyleStubPIC())
12590 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12592 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12593 CP->getAlignment(),
12594 CP->getOffset(), OpFlag);
12596 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12597 // With PIC, the address is actually $g + Offset.
12599 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12600 DAG.getNode(X86ISD::GlobalBaseReg,
12601 SDLoc(), getPointerTy()),
12608 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12609 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12611 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12612 // global base reg.
12613 unsigned char OpFlag = 0;
12614 unsigned WrapperKind = X86ISD::Wrapper;
12615 CodeModel::Model M = DAG.getTarget().getCodeModel();
12617 if (Subtarget->isPICStyleRIPRel() &&
12618 (M == CodeModel::Small || M == CodeModel::Kernel))
12619 WrapperKind = X86ISD::WrapperRIP;
12620 else if (Subtarget->isPICStyleGOT())
12621 OpFlag = X86II::MO_GOTOFF;
12622 else if (Subtarget->isPICStyleStubPIC())
12623 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12625 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12628 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12630 // With PIC, the address is actually $g + Offset.
12632 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12633 DAG.getNode(X86ISD::GlobalBaseReg,
12634 SDLoc(), getPointerTy()),
12641 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12642 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12644 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12645 // global base reg.
12646 unsigned char OpFlag = 0;
12647 unsigned WrapperKind = X86ISD::Wrapper;
12648 CodeModel::Model M = DAG.getTarget().getCodeModel();
12650 if (Subtarget->isPICStyleRIPRel() &&
12651 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12652 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12653 OpFlag = X86II::MO_GOTPCREL;
12654 WrapperKind = X86ISD::WrapperRIP;
12655 } else if (Subtarget->isPICStyleGOT()) {
12656 OpFlag = X86II::MO_GOT;
12657 } else if (Subtarget->isPICStyleStubPIC()) {
12658 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12659 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12660 OpFlag = X86II::MO_DARWIN_NONLAZY;
12663 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12666 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12668 // With PIC, the address is actually $g + Offset.
12669 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12670 !Subtarget->is64Bit()) {
12671 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12672 DAG.getNode(X86ISD::GlobalBaseReg,
12673 SDLoc(), getPointerTy()),
12677 // For symbols that require a load from a stub to get the address, emit the
12679 if (isGlobalStubReference(OpFlag))
12680 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12681 MachinePointerInfo::getGOT(), false, false, false, 0);
12687 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12688 // Create the TargetBlockAddressAddress node.
12689 unsigned char OpFlags =
12690 Subtarget->ClassifyBlockAddressReference();
12691 CodeModel::Model M = DAG.getTarget().getCodeModel();
12692 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12693 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12695 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12698 if (Subtarget->isPICStyleRIPRel() &&
12699 (M == CodeModel::Small || M == CodeModel::Kernel))
12700 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12702 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12704 // With PIC, the address is actually $g + Offset.
12705 if (isGlobalRelativeToPICBase(OpFlags)) {
12706 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12707 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12715 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12716 int64_t Offset, SelectionDAG &DAG) const {
12717 // Create the TargetGlobalAddress node, folding in the constant
12718 // offset if it is legal.
12719 unsigned char OpFlags =
12720 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12721 CodeModel::Model M = DAG.getTarget().getCodeModel();
12723 if (OpFlags == X86II::MO_NO_FLAG &&
12724 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12725 // A direct static reference to a global.
12726 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12729 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12732 if (Subtarget->isPICStyleRIPRel() &&
12733 (M == CodeModel::Small || M == CodeModel::Kernel))
12734 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12736 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12738 // With PIC, the address is actually $g + Offset.
12739 if (isGlobalRelativeToPICBase(OpFlags)) {
12740 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12741 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12745 // For globals that require a load from a stub to get the address, emit the
12747 if (isGlobalStubReference(OpFlags))
12748 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12749 MachinePointerInfo::getGOT(), false, false, false, 0);
12751 // If there was a non-zero offset that we didn't fold, create an explicit
12752 // addition for it.
12754 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12755 DAG.getConstant(Offset, getPointerTy()));
12761 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12762 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12763 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12764 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12768 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12769 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12770 unsigned char OperandFlags, bool LocalDynamic = false) {
12771 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12772 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12774 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12775 GA->getValueType(0),
12779 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12783 SDValue Ops[] = { Chain, TGA, *InFlag };
12784 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12786 SDValue Ops[] = { Chain, TGA };
12787 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12790 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12791 MFI->setAdjustsStack(true);
12793 SDValue Flag = Chain.getValue(1);
12794 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12797 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12799 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12802 SDLoc dl(GA); // ? function entry point might be better
12803 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12804 DAG.getNode(X86ISD::GlobalBaseReg,
12805 SDLoc(), PtrVT), InFlag);
12806 InFlag = Chain.getValue(1);
12808 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12811 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12813 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12815 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12816 X86::RAX, X86II::MO_TLSGD);
12819 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12825 // Get the start address of the TLS block for this module.
12826 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12827 .getInfo<X86MachineFunctionInfo>();
12828 MFI->incNumLocalDynamicTLSAccesses();
12832 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12833 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12836 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12837 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12838 InFlag = Chain.getValue(1);
12839 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12840 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12843 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12847 unsigned char OperandFlags = X86II::MO_DTPOFF;
12848 unsigned WrapperKind = X86ISD::Wrapper;
12849 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12850 GA->getValueType(0),
12851 GA->getOffset(), OperandFlags);
12852 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12854 // Add x@dtpoff with the base.
12855 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12858 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12859 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12860 const EVT PtrVT, TLSModel::Model model,
12861 bool is64Bit, bool isPIC) {
12864 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12865 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12866 is64Bit ? 257 : 256));
12868 SDValue ThreadPointer =
12869 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12870 MachinePointerInfo(Ptr), false, false, false, 0);
12872 unsigned char OperandFlags = 0;
12873 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12875 unsigned WrapperKind = X86ISD::Wrapper;
12876 if (model == TLSModel::LocalExec) {
12877 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12878 } else if (model == TLSModel::InitialExec) {
12880 OperandFlags = X86II::MO_GOTTPOFF;
12881 WrapperKind = X86ISD::WrapperRIP;
12883 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12886 llvm_unreachable("Unexpected model");
12889 // emit "addl x@ntpoff,%eax" (local exec)
12890 // or "addl x@indntpoff,%eax" (initial exec)
12891 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12893 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12894 GA->getOffset(), OperandFlags);
12895 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12897 if (model == TLSModel::InitialExec) {
12898 if (isPIC && !is64Bit) {
12899 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12900 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12904 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12905 MachinePointerInfo::getGOT(), false, false, false, 0);
12908 // The address of the thread local variable is the add of the thread
12909 // pointer with the offset of the variable.
12910 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12914 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12916 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12917 const GlobalValue *GV = GA->getGlobal();
12919 if (Subtarget->isTargetELF()) {
12920 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12923 case TLSModel::GeneralDynamic:
12924 if (Subtarget->is64Bit())
12925 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12926 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12927 case TLSModel::LocalDynamic:
12928 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12929 Subtarget->is64Bit());
12930 case TLSModel::InitialExec:
12931 case TLSModel::LocalExec:
12932 return LowerToTLSExecModel(
12933 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12934 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12936 llvm_unreachable("Unknown TLS model.");
12939 if (Subtarget->isTargetDarwin()) {
12940 // Darwin only has one model of TLS. Lower to that.
12941 unsigned char OpFlag = 0;
12942 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12943 X86ISD::WrapperRIP : X86ISD::Wrapper;
12945 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12946 // global base reg.
12947 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12948 !Subtarget->is64Bit();
12950 OpFlag = X86II::MO_TLVP_PIC_BASE;
12952 OpFlag = X86II::MO_TLVP;
12954 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12955 GA->getValueType(0),
12956 GA->getOffset(), OpFlag);
12957 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12959 // With PIC32, the address is actually $g + Offset.
12961 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12962 DAG.getNode(X86ISD::GlobalBaseReg,
12963 SDLoc(), getPointerTy()),
12966 // Lowering the machine isd will make sure everything is in the right
12968 SDValue Chain = DAG.getEntryNode();
12969 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12970 SDValue Args[] = { Chain, Offset };
12971 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12973 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12974 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12975 MFI->setAdjustsStack(true);
12977 // And our return value (tls address) is in the standard call return value
12979 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12980 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12981 Chain.getValue(1));
12984 if (Subtarget->isTargetKnownWindowsMSVC() ||
12985 Subtarget->isTargetWindowsGNU()) {
12986 // Just use the implicit TLS architecture
12987 // Need to generate someting similar to:
12988 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12990 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12991 // mov rcx, qword [rdx+rcx*8]
12992 // mov eax, .tls$:tlsvar
12993 // [rax+rcx] contains the address
12994 // Windows 64bit: gs:0x58
12995 // Windows 32bit: fs:__tls_array
12998 SDValue Chain = DAG.getEntryNode();
13000 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13001 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13002 // use its literal value of 0x2C.
13003 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13004 ? Type::getInt8PtrTy(*DAG.getContext(),
13006 : Type::getInt32PtrTy(*DAG.getContext(),
13010 Subtarget->is64Bit()
13011 ? DAG.getIntPtrConstant(0x58)
13012 : (Subtarget->isTargetWindowsGNU()
13013 ? DAG.getIntPtrConstant(0x2C)
13014 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13016 SDValue ThreadPointer =
13017 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13018 MachinePointerInfo(Ptr), false, false, false, 0);
13020 // Load the _tls_index variable
13021 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13022 if (Subtarget->is64Bit())
13023 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13024 IDX, MachinePointerInfo(), MVT::i32,
13025 false, false, false, 0);
13027 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13028 false, false, false, 0);
13030 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13032 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13034 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13035 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13036 false, false, false, 0);
13038 // Get the offset of start of .tls section
13039 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13040 GA->getValueType(0),
13041 GA->getOffset(), X86II::MO_SECREL);
13042 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13044 // The address of the thread local variable is the add of the thread
13045 // pointer with the offset of the variable.
13046 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13049 llvm_unreachable("TLS not implemented for this target.");
13052 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13053 /// and take a 2 x i32 value to shift plus a shift amount.
13054 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13055 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13056 MVT VT = Op.getSimpleValueType();
13057 unsigned VTBits = VT.getSizeInBits();
13059 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13060 SDValue ShOpLo = Op.getOperand(0);
13061 SDValue ShOpHi = Op.getOperand(1);
13062 SDValue ShAmt = Op.getOperand(2);
13063 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13064 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13066 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13067 DAG.getConstant(VTBits - 1, MVT::i8));
13068 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13069 DAG.getConstant(VTBits - 1, MVT::i8))
13070 : DAG.getConstant(0, VT);
13072 SDValue Tmp2, Tmp3;
13073 if (Op.getOpcode() == ISD::SHL_PARTS) {
13074 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13075 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13077 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13078 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13081 // If the shift amount is larger or equal than the width of a part we can't
13082 // rely on the results of shld/shrd. Insert a test and select the appropriate
13083 // values for large shift amounts.
13084 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13085 DAG.getConstant(VTBits, MVT::i8));
13086 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13087 AndNode, DAG.getConstant(0, MVT::i8));
13090 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13091 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13092 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13094 if (Op.getOpcode() == ISD::SHL_PARTS) {
13095 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13096 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13098 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13099 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13102 SDValue Ops[2] = { Lo, Hi };
13103 return DAG.getMergeValues(Ops, dl);
13106 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13107 SelectionDAG &DAG) const {
13108 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13110 if (SrcVT.isVector())
13113 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13114 "Unknown SINT_TO_FP to lower!");
13116 // These are really Legal; return the operand so the caller accepts it as
13118 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13120 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13121 Subtarget->is64Bit()) {
13126 unsigned Size = SrcVT.getSizeInBits()/8;
13127 MachineFunction &MF = DAG.getMachineFunction();
13128 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13129 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13130 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13132 MachinePointerInfo::getFixedStack(SSFI),
13134 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13137 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13139 SelectionDAG &DAG) const {
13143 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13145 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13147 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13149 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13151 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13152 MachineMemOperand *MMO;
13154 int SSFI = FI->getIndex();
13156 DAG.getMachineFunction()
13157 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13158 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13160 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13161 StackSlot = StackSlot.getOperand(1);
13163 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13164 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13166 Tys, Ops, SrcVT, MMO);
13169 Chain = Result.getValue(1);
13170 SDValue InFlag = Result.getValue(2);
13172 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13173 // shouldn't be necessary except that RFP cannot be live across
13174 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13175 MachineFunction &MF = DAG.getMachineFunction();
13176 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13177 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13178 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13179 Tys = DAG.getVTList(MVT::Other);
13181 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13183 MachineMemOperand *MMO =
13184 DAG.getMachineFunction()
13185 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13186 MachineMemOperand::MOStore, SSFISize, SSFISize);
13188 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13189 Ops, Op.getValueType(), MMO);
13190 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13191 MachinePointerInfo::getFixedStack(SSFI),
13192 false, false, false, 0);
13198 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13199 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13200 SelectionDAG &DAG) const {
13201 // This algorithm is not obvious. Here it is what we're trying to output:
13204 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13205 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13207 haddpd %xmm0, %xmm0
13209 pshufd $0x4e, %xmm0, %xmm1
13215 LLVMContext *Context = DAG.getContext();
13217 // Build some magic constants.
13218 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13219 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13220 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13222 SmallVector<Constant*,2> CV1;
13224 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13225 APInt(64, 0x4330000000000000ULL))));
13227 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13228 APInt(64, 0x4530000000000000ULL))));
13229 Constant *C1 = ConstantVector::get(CV1);
13230 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13232 // Load the 64-bit value into an XMM register.
13233 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13235 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13236 MachinePointerInfo::getConstantPool(),
13237 false, false, false, 16);
13238 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13239 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13242 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13243 MachinePointerInfo::getConstantPool(),
13244 false, false, false, 16);
13245 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13246 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13249 if (Subtarget->hasSSE3()) {
13250 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13251 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13253 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13254 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13256 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13257 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13261 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13262 DAG.getIntPtrConstant(0));
13265 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13266 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13267 SelectionDAG &DAG) const {
13269 // FP constant to bias correct the final result.
13270 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13273 // Load the 32-bit value into an XMM register.
13274 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13277 // Zero out the upper parts of the register.
13278 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13280 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13281 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13282 DAG.getIntPtrConstant(0));
13284 // Or the load with the bias.
13285 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13286 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13287 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13288 MVT::v2f64, Load)),
13289 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13290 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13291 MVT::v2f64, Bias)));
13292 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13293 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13294 DAG.getIntPtrConstant(0));
13296 // Subtract the bias.
13297 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13299 // Handle final rounding.
13300 EVT DestVT = Op.getValueType();
13302 if (DestVT.bitsLT(MVT::f64))
13303 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13304 DAG.getIntPtrConstant(0));
13305 if (DestVT.bitsGT(MVT::f64))
13306 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13308 // Handle final rounding.
13312 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13313 SelectionDAG &DAG) const {
13314 SDValue N0 = Op.getOperand(0);
13315 MVT SVT = N0.getSimpleValueType();
13318 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13319 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13320 "Custom UINT_TO_FP is not supported!");
13322 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13323 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13324 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13327 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13328 SelectionDAG &DAG) const {
13329 SDValue N0 = Op.getOperand(0);
13332 if (Op.getValueType().isVector())
13333 return lowerUINT_TO_FP_vec(Op, DAG);
13335 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13336 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13337 // the optimization here.
13338 if (DAG.SignBitIsZero(N0))
13339 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13341 MVT SrcVT = N0.getSimpleValueType();
13342 MVT DstVT = Op.getSimpleValueType();
13343 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13344 return LowerUINT_TO_FP_i64(Op, DAG);
13345 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13346 return LowerUINT_TO_FP_i32(Op, DAG);
13347 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13350 // Make a 64-bit buffer, and use it to build an FILD.
13351 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13352 if (SrcVT == MVT::i32) {
13353 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13354 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13355 getPointerTy(), StackSlot, WordOff);
13356 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13357 StackSlot, MachinePointerInfo(),
13359 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13360 OffsetSlot, MachinePointerInfo(),
13362 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13366 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13367 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13368 StackSlot, MachinePointerInfo(),
13370 // For i64 source, we need to add the appropriate power of 2 if the input
13371 // was negative. This is the same as the optimization in
13372 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13373 // we must be careful to do the computation in x87 extended precision, not
13374 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13375 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13376 MachineMemOperand *MMO =
13377 DAG.getMachineFunction()
13378 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13379 MachineMemOperand::MOLoad, 8, 8);
13381 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13382 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13383 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13386 APInt FF(32, 0x5F800000ULL);
13388 // Check whether the sign bit is set.
13389 SDValue SignSet = DAG.getSetCC(dl,
13390 getSetCCResultType(*DAG.getContext(), MVT::i64),
13391 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13394 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13395 SDValue FudgePtr = DAG.getConstantPool(
13396 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13399 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13400 SDValue Zero = DAG.getIntPtrConstant(0);
13401 SDValue Four = DAG.getIntPtrConstant(4);
13402 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13404 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13406 // Load the value out, extending it from f32 to f80.
13407 // FIXME: Avoid the extend by constructing the right constant pool?
13408 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13409 FudgePtr, MachinePointerInfo::getConstantPool(),
13410 MVT::f32, false, false, false, 4);
13411 // Extend everything to 80 bits to force it to be done on x87.
13412 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13413 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13416 std::pair<SDValue,SDValue>
13417 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13418 bool IsSigned, bool IsReplace) const {
13421 EVT DstTy = Op.getValueType();
13423 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13424 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13428 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13429 DstTy.getSimpleVT() >= MVT::i16 &&
13430 "Unknown FP_TO_INT to lower!");
13432 // These are really Legal.
13433 if (DstTy == MVT::i32 &&
13434 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13435 return std::make_pair(SDValue(), SDValue());
13436 if (Subtarget->is64Bit() &&
13437 DstTy == MVT::i64 &&
13438 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13439 return std::make_pair(SDValue(), SDValue());
13441 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13442 // stack slot, or into the FTOL runtime function.
13443 MachineFunction &MF = DAG.getMachineFunction();
13444 unsigned MemSize = DstTy.getSizeInBits()/8;
13445 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13446 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13449 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13450 Opc = X86ISD::WIN_FTOL;
13452 switch (DstTy.getSimpleVT().SimpleTy) {
13453 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13454 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13455 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13456 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13459 SDValue Chain = DAG.getEntryNode();
13460 SDValue Value = Op.getOperand(0);
13461 EVT TheVT = Op.getOperand(0).getValueType();
13462 // FIXME This causes a redundant load/store if the SSE-class value is already
13463 // in memory, such as if it is on the callstack.
13464 if (isScalarFPTypeInSSEReg(TheVT)) {
13465 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13466 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13467 MachinePointerInfo::getFixedStack(SSFI),
13469 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13471 Chain, StackSlot, DAG.getValueType(TheVT)
13474 MachineMemOperand *MMO =
13475 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13476 MachineMemOperand::MOLoad, MemSize, MemSize);
13477 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13478 Chain = Value.getValue(1);
13479 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13480 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13483 MachineMemOperand *MMO =
13484 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13485 MachineMemOperand::MOStore, MemSize, MemSize);
13487 if (Opc != X86ISD::WIN_FTOL) {
13488 // Build the FP_TO_INT*_IN_MEM
13489 SDValue Ops[] = { Chain, Value, StackSlot };
13490 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13492 return std::make_pair(FIST, StackSlot);
13494 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13495 DAG.getVTList(MVT::Other, MVT::Glue),
13497 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13498 MVT::i32, ftol.getValue(1));
13499 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13500 MVT::i32, eax.getValue(2));
13501 SDValue Ops[] = { eax, edx };
13502 SDValue pair = IsReplace
13503 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13504 : DAG.getMergeValues(Ops, DL);
13505 return std::make_pair(pair, SDValue());
13509 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13510 const X86Subtarget *Subtarget) {
13511 MVT VT = Op->getSimpleValueType(0);
13512 SDValue In = Op->getOperand(0);
13513 MVT InVT = In.getSimpleValueType();
13516 // Optimize vectors in AVX mode:
13519 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13520 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13521 // Concat upper and lower parts.
13524 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13525 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13526 // Concat upper and lower parts.
13529 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13530 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13531 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13534 if (Subtarget->hasInt256())
13535 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13537 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13538 SDValue Undef = DAG.getUNDEF(InVT);
13539 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13540 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13541 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13543 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13544 VT.getVectorNumElements()/2);
13546 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13547 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13549 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13552 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13553 SelectionDAG &DAG) {
13554 MVT VT = Op->getSimpleValueType(0);
13555 SDValue In = Op->getOperand(0);
13556 MVT InVT = In.getSimpleValueType();
13558 unsigned int NumElts = VT.getVectorNumElements();
13559 if (NumElts != 8 && NumElts != 16)
13562 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13563 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13565 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13567 // Now we have only mask extension
13568 assert(InVT.getVectorElementType() == MVT::i1);
13569 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13570 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13571 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13572 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13573 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13574 MachinePointerInfo::getConstantPool(),
13575 false, false, false, Alignment);
13577 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13578 if (VT.is512BitVector())
13580 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13583 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13584 SelectionDAG &DAG) {
13585 if (Subtarget->hasFp256()) {
13586 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13594 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13595 SelectionDAG &DAG) {
13597 MVT VT = Op.getSimpleValueType();
13598 SDValue In = Op.getOperand(0);
13599 MVT SVT = In.getSimpleValueType();
13601 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13602 return LowerZERO_EXTEND_AVX512(Op, DAG);
13604 if (Subtarget->hasFp256()) {
13605 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13610 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13611 VT.getVectorNumElements() != SVT.getVectorNumElements());
13615 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13617 MVT VT = Op.getSimpleValueType();
13618 SDValue In = Op.getOperand(0);
13619 MVT InVT = In.getSimpleValueType();
13621 if (VT == MVT::i1) {
13622 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13623 "Invalid scalar TRUNCATE operation");
13624 if (InVT.getSizeInBits() >= 32)
13626 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13627 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13629 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13630 "Invalid TRUNCATE operation");
13632 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13633 if (VT.getVectorElementType().getSizeInBits() >=8)
13634 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13636 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13637 unsigned NumElts = InVT.getVectorNumElements();
13638 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13639 if (InVT.getSizeInBits() < 512) {
13640 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13641 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13645 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13646 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13647 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13648 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13649 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13650 MachinePointerInfo::getConstantPool(),
13651 false, false, false, Alignment);
13652 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13653 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13654 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13657 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13658 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13659 if (Subtarget->hasInt256()) {
13660 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13661 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13662 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13664 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13665 DAG.getIntPtrConstant(0));
13668 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13669 DAG.getIntPtrConstant(0));
13670 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13671 DAG.getIntPtrConstant(2));
13672 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13673 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13674 static const int ShufMask[] = {0, 2, 4, 6};
13675 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13678 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13679 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13680 if (Subtarget->hasInt256()) {
13681 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13683 SmallVector<SDValue,32> pshufbMask;
13684 for (unsigned i = 0; i < 2; ++i) {
13685 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13686 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13687 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13688 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13689 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13690 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13691 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13692 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13693 for (unsigned j = 0; j < 8; ++j)
13694 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13696 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13697 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13698 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13700 static const int ShufMask[] = {0, 2, -1, -1};
13701 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13703 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13704 DAG.getIntPtrConstant(0));
13705 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13708 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13709 DAG.getIntPtrConstant(0));
13711 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13712 DAG.getIntPtrConstant(4));
13714 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13715 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13717 // The PSHUFB mask:
13718 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13719 -1, -1, -1, -1, -1, -1, -1, -1};
13721 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13722 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13723 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13725 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13726 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13728 // The MOVLHPS Mask:
13729 static const int ShufMask2[] = {0, 1, 4, 5};
13730 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13731 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13734 // Handle truncation of V256 to V128 using shuffles.
13735 if (!VT.is128BitVector() || !InVT.is256BitVector())
13738 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13740 unsigned NumElems = VT.getVectorNumElements();
13741 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13743 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13744 // Prepare truncation shuffle mask
13745 for (unsigned i = 0; i != NumElems; ++i)
13746 MaskVec[i] = i * 2;
13747 SDValue V = DAG.getVectorShuffle(NVT, DL,
13748 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13749 DAG.getUNDEF(NVT), &MaskVec[0]);
13750 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13751 DAG.getIntPtrConstant(0));
13754 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13755 SelectionDAG &DAG) const {
13756 assert(!Op.getSimpleValueType().isVector());
13758 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13759 /*IsSigned=*/ true, /*IsReplace=*/ false);
13760 SDValue FIST = Vals.first, StackSlot = Vals.second;
13761 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13762 if (!FIST.getNode()) return Op;
13764 if (StackSlot.getNode())
13765 // Load the result.
13766 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13767 FIST, StackSlot, MachinePointerInfo(),
13768 false, false, false, 0);
13770 // The node is the result.
13774 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13775 SelectionDAG &DAG) const {
13776 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13777 /*IsSigned=*/ false, /*IsReplace=*/ false);
13778 SDValue FIST = Vals.first, StackSlot = Vals.second;
13779 assert(FIST.getNode() && "Unexpected failure");
13781 if (StackSlot.getNode())
13782 // Load the result.
13783 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13784 FIST, StackSlot, MachinePointerInfo(),
13785 false, false, false, 0);
13787 // The node is the result.
13791 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13793 MVT VT = Op.getSimpleValueType();
13794 SDValue In = Op.getOperand(0);
13795 MVT SVT = In.getSimpleValueType();
13797 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13799 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13800 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13801 In, DAG.getUNDEF(SVT)));
13804 /// The only differences between FABS and FNEG are the mask and the logic op.
13805 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13806 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13807 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13808 "Wrong opcode for lowering FABS or FNEG.");
13810 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13812 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13813 // into an FNABS. We'll lower the FABS after that if it is still in use.
13815 for (SDNode *User : Op->uses())
13816 if (User->getOpcode() == ISD::FNEG)
13819 SDValue Op0 = Op.getOperand(0);
13820 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13823 MVT VT = Op.getSimpleValueType();
13824 // Assume scalar op for initialization; update for vector if needed.
13825 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13826 // generate a 16-byte vector constant and logic op even for the scalar case.
13827 // Using a 16-byte mask allows folding the load of the mask with
13828 // the logic op, so it can save (~4 bytes) on code size.
13830 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13831 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13832 // decide if we should generate a 16-byte constant mask when we only need 4 or
13833 // 8 bytes for the scalar case.
13834 if (VT.isVector()) {
13835 EltVT = VT.getVectorElementType();
13836 NumElts = VT.getVectorNumElements();
13839 unsigned EltBits = EltVT.getSizeInBits();
13840 LLVMContext *Context = DAG.getContext();
13841 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13843 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13844 Constant *C = ConstantInt::get(*Context, MaskElt);
13845 C = ConstantVector::getSplat(NumElts, C);
13846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13847 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13848 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13849 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13850 MachinePointerInfo::getConstantPool(),
13851 false, false, false, Alignment);
13853 if (VT.isVector()) {
13854 // For a vector, cast operands to a vector type, perform the logic op,
13855 // and cast the result back to the original value type.
13856 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13857 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13858 SDValue Operand = IsFNABS ?
13859 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13860 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13861 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13862 return DAG.getNode(ISD::BITCAST, dl, VT,
13863 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13866 // If not vector, then scalar.
13867 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13868 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13869 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13872 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13874 LLVMContext *Context = DAG.getContext();
13875 SDValue Op0 = Op.getOperand(0);
13876 SDValue Op1 = Op.getOperand(1);
13878 MVT VT = Op.getSimpleValueType();
13879 MVT SrcVT = Op1.getSimpleValueType();
13881 // If second operand is smaller, extend it first.
13882 if (SrcVT.bitsLT(VT)) {
13883 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13886 // And if it is bigger, shrink it first.
13887 if (SrcVT.bitsGT(VT)) {
13888 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13892 // At this point the operands and the result should have the same
13893 // type, and that won't be f80 since that is not custom lowered.
13895 // First get the sign bit of second operand.
13896 SmallVector<Constant*,4> CV;
13897 if (SrcVT == MVT::f64) {
13898 const fltSemantics &Sem = APFloat::IEEEdouble;
13899 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13900 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13902 const fltSemantics &Sem = APFloat::IEEEsingle;
13903 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13904 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13905 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13906 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13908 Constant *C = ConstantVector::get(CV);
13909 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13910 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13911 MachinePointerInfo::getConstantPool(),
13912 false, false, false, 16);
13913 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13915 // Shift sign bit right or left if the two operands have different types.
13916 if (SrcVT.bitsGT(VT)) {
13917 // Op0 is MVT::f32, Op1 is MVT::f64.
13918 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13919 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13920 DAG.getConstant(32, MVT::i32));
13921 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13922 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13923 DAG.getIntPtrConstant(0));
13926 // Clear first operand sign bit.
13928 if (VT == MVT::f64) {
13929 const fltSemantics &Sem = APFloat::IEEEdouble;
13930 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13931 APInt(64, ~(1ULL << 63)))));
13932 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13934 const fltSemantics &Sem = APFloat::IEEEsingle;
13935 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13936 APInt(32, ~(1U << 31)))));
13937 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13938 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13939 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13941 C = ConstantVector::get(CV);
13942 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13943 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13944 MachinePointerInfo::getConstantPool(),
13945 false, false, false, 16);
13946 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13948 // Or the value with the sign bit.
13949 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13952 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13953 SDValue N0 = Op.getOperand(0);
13955 MVT VT = Op.getSimpleValueType();
13957 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13958 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13959 DAG.getConstant(1, VT));
13960 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13963 // Check whether an OR'd tree is PTEST-able.
13964 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13965 SelectionDAG &DAG) {
13966 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13968 if (!Subtarget->hasSSE41())
13971 if (!Op->hasOneUse())
13974 SDNode *N = Op.getNode();
13977 SmallVector<SDValue, 8> Opnds;
13978 DenseMap<SDValue, unsigned> VecInMap;
13979 SmallVector<SDValue, 8> VecIns;
13980 EVT VT = MVT::Other;
13982 // Recognize a special case where a vector is casted into wide integer to
13984 Opnds.push_back(N->getOperand(0));
13985 Opnds.push_back(N->getOperand(1));
13987 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13988 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13989 // BFS traverse all OR'd operands.
13990 if (I->getOpcode() == ISD::OR) {
13991 Opnds.push_back(I->getOperand(0));
13992 Opnds.push_back(I->getOperand(1));
13993 // Re-evaluate the number of nodes to be traversed.
13994 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13998 // Quit if a non-EXTRACT_VECTOR_ELT
13999 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14002 // Quit if without a constant index.
14003 SDValue Idx = I->getOperand(1);
14004 if (!isa<ConstantSDNode>(Idx))
14007 SDValue ExtractedFromVec = I->getOperand(0);
14008 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14009 if (M == VecInMap.end()) {
14010 VT = ExtractedFromVec.getValueType();
14011 // Quit if not 128/256-bit vector.
14012 if (!VT.is128BitVector() && !VT.is256BitVector())
14014 // Quit if not the same type.
14015 if (VecInMap.begin() != VecInMap.end() &&
14016 VT != VecInMap.begin()->first.getValueType())
14018 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14019 VecIns.push_back(ExtractedFromVec);
14021 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14024 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14025 "Not extracted from 128-/256-bit vector.");
14027 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14029 for (DenseMap<SDValue, unsigned>::const_iterator
14030 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14031 // Quit if not all elements are used.
14032 if (I->second != FullMask)
14036 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14038 // Cast all vectors into TestVT for PTEST.
14039 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14040 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14042 // If more than one full vectors are evaluated, OR them first before PTEST.
14043 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14044 // Each iteration will OR 2 nodes and append the result until there is only
14045 // 1 node left, i.e. the final OR'd value of all vectors.
14046 SDValue LHS = VecIns[Slot];
14047 SDValue RHS = VecIns[Slot + 1];
14048 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14051 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14052 VecIns.back(), VecIns.back());
14055 /// \brief return true if \c Op has a use that doesn't just read flags.
14056 static bool hasNonFlagsUse(SDValue Op) {
14057 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14059 SDNode *User = *UI;
14060 unsigned UOpNo = UI.getOperandNo();
14061 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14062 // Look pass truncate.
14063 UOpNo = User->use_begin().getOperandNo();
14064 User = *User->use_begin();
14067 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14068 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14074 /// Emit nodes that will be selected as "test Op0,Op0", or something
14076 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14077 SelectionDAG &DAG) const {
14078 if (Op.getValueType() == MVT::i1)
14079 // KORTEST instruction should be selected
14080 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14081 DAG.getConstant(0, Op.getValueType()));
14083 // CF and OF aren't always set the way we want. Determine which
14084 // of these we need.
14085 bool NeedCF = false;
14086 bool NeedOF = false;
14089 case X86::COND_A: case X86::COND_AE:
14090 case X86::COND_B: case X86::COND_BE:
14093 case X86::COND_G: case X86::COND_GE:
14094 case X86::COND_L: case X86::COND_LE:
14095 case X86::COND_O: case X86::COND_NO: {
14096 // Check if we really need to set the
14097 // Overflow flag. If NoSignedWrap is present
14098 // that is not actually needed.
14099 switch (Op->getOpcode()) {
14104 const BinaryWithFlagsSDNode *BinNode =
14105 cast<BinaryWithFlagsSDNode>(Op.getNode());
14106 if (BinNode->hasNoSignedWrap())
14116 // See if we can use the EFLAGS value from the operand instead of
14117 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14118 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14119 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14120 // Emit a CMP with 0, which is the TEST pattern.
14121 //if (Op.getValueType() == MVT::i1)
14122 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14123 // DAG.getConstant(0, MVT::i1));
14124 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14125 DAG.getConstant(0, Op.getValueType()));
14127 unsigned Opcode = 0;
14128 unsigned NumOperands = 0;
14130 // Truncate operations may prevent the merge of the SETCC instruction
14131 // and the arithmetic instruction before it. Attempt to truncate the operands
14132 // of the arithmetic instruction and use a reduced bit-width instruction.
14133 bool NeedTruncation = false;
14134 SDValue ArithOp = Op;
14135 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14136 SDValue Arith = Op->getOperand(0);
14137 // Both the trunc and the arithmetic op need to have one user each.
14138 if (Arith->hasOneUse())
14139 switch (Arith.getOpcode()) {
14146 NeedTruncation = true;
14152 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14153 // which may be the result of a CAST. We use the variable 'Op', which is the
14154 // non-casted variable when we check for possible users.
14155 switch (ArithOp.getOpcode()) {
14157 // Due to an isel shortcoming, be conservative if this add is likely to be
14158 // selected as part of a load-modify-store instruction. When the root node
14159 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14160 // uses of other nodes in the match, such as the ADD in this case. This
14161 // leads to the ADD being left around and reselected, with the result being
14162 // two adds in the output. Alas, even if none our users are stores, that
14163 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14164 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14165 // climbing the DAG back to the root, and it doesn't seem to be worth the
14167 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14168 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14169 if (UI->getOpcode() != ISD::CopyToReg &&
14170 UI->getOpcode() != ISD::SETCC &&
14171 UI->getOpcode() != ISD::STORE)
14174 if (ConstantSDNode *C =
14175 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14176 // An add of one will be selected as an INC.
14177 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14178 Opcode = X86ISD::INC;
14183 // An add of negative one (subtract of one) will be selected as a DEC.
14184 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14185 Opcode = X86ISD::DEC;
14191 // Otherwise use a regular EFLAGS-setting add.
14192 Opcode = X86ISD::ADD;
14197 // If we have a constant logical shift that's only used in a comparison
14198 // against zero turn it into an equivalent AND. This allows turning it into
14199 // a TEST instruction later.
14200 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14201 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14202 EVT VT = Op.getValueType();
14203 unsigned BitWidth = VT.getSizeInBits();
14204 unsigned ShAmt = Op->getConstantOperandVal(1);
14205 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14207 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14208 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14209 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14210 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14212 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14213 DAG.getConstant(Mask, VT));
14214 DAG.ReplaceAllUsesWith(Op, New);
14220 // If the primary and result isn't used, don't bother using X86ISD::AND,
14221 // because a TEST instruction will be better.
14222 if (!hasNonFlagsUse(Op))
14228 // Due to the ISEL shortcoming noted above, be conservative if this op is
14229 // likely to be selected as part of a load-modify-store instruction.
14230 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14231 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14232 if (UI->getOpcode() == ISD::STORE)
14235 // Otherwise use a regular EFLAGS-setting instruction.
14236 switch (ArithOp.getOpcode()) {
14237 default: llvm_unreachable("unexpected operator!");
14238 case ISD::SUB: Opcode = X86ISD::SUB; break;
14239 case ISD::XOR: Opcode = X86ISD::XOR; break;
14240 case ISD::AND: Opcode = X86ISD::AND; break;
14242 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14243 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14244 if (EFLAGS.getNode())
14247 Opcode = X86ISD::OR;
14261 return SDValue(Op.getNode(), 1);
14267 // If we found that truncation is beneficial, perform the truncation and
14269 if (NeedTruncation) {
14270 EVT VT = Op.getValueType();
14271 SDValue WideVal = Op->getOperand(0);
14272 EVT WideVT = WideVal.getValueType();
14273 unsigned ConvertedOp = 0;
14274 // Use a target machine opcode to prevent further DAGCombine
14275 // optimizations that may separate the arithmetic operations
14276 // from the setcc node.
14277 switch (WideVal.getOpcode()) {
14279 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14280 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14281 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14282 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14283 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14287 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14288 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14289 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14290 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14291 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14297 // Emit a CMP with 0, which is the TEST pattern.
14298 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14299 DAG.getConstant(0, Op.getValueType()));
14301 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14302 SmallVector<SDValue, 4> Ops;
14303 for (unsigned i = 0; i != NumOperands; ++i)
14304 Ops.push_back(Op.getOperand(i));
14306 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14307 DAG.ReplaceAllUsesWith(Op, New);
14308 return SDValue(New.getNode(), 1);
14311 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14313 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14314 SDLoc dl, SelectionDAG &DAG) const {
14315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14316 if (C->getAPIntValue() == 0)
14317 return EmitTest(Op0, X86CC, dl, DAG);
14319 if (Op0.getValueType() == MVT::i1)
14320 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14323 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14324 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14325 // Do the comparison at i32 if it's smaller, besides the Atom case.
14326 // This avoids subregister aliasing issues. Keep the smaller reference
14327 // if we're optimizing for size, however, as that'll allow better folding
14328 // of memory operations.
14329 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14330 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14331 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14332 !Subtarget->isAtom()) {
14333 unsigned ExtendOp =
14334 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14335 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14336 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14338 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14339 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14340 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14342 return SDValue(Sub.getNode(), 1);
14344 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14347 /// Convert a comparison if required by the subtarget.
14348 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14349 SelectionDAG &DAG) const {
14350 // If the subtarget does not support the FUCOMI instruction, floating-point
14351 // comparisons have to be converted.
14352 if (Subtarget->hasCMov() ||
14353 Cmp.getOpcode() != X86ISD::CMP ||
14354 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14355 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14358 // The instruction selector will select an FUCOM instruction instead of
14359 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14360 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14361 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14363 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14364 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14365 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14366 DAG.getConstant(8, MVT::i8));
14367 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14368 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14371 static bool isAllOnes(SDValue V) {
14372 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14373 return C && C->isAllOnesValue();
14376 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14377 /// if it's possible.
14378 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14379 SDLoc dl, SelectionDAG &DAG) const {
14380 SDValue Op0 = And.getOperand(0);
14381 SDValue Op1 = And.getOperand(1);
14382 if (Op0.getOpcode() == ISD::TRUNCATE)
14383 Op0 = Op0.getOperand(0);
14384 if (Op1.getOpcode() == ISD::TRUNCATE)
14385 Op1 = Op1.getOperand(0);
14388 if (Op1.getOpcode() == ISD::SHL)
14389 std::swap(Op0, Op1);
14390 if (Op0.getOpcode() == ISD::SHL) {
14391 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14392 if (And00C->getZExtValue() == 1) {
14393 // If we looked past a truncate, check that it's only truncating away
14395 unsigned BitWidth = Op0.getValueSizeInBits();
14396 unsigned AndBitWidth = And.getValueSizeInBits();
14397 if (BitWidth > AndBitWidth) {
14399 DAG.computeKnownBits(Op0, Zeros, Ones);
14400 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14404 RHS = Op0.getOperand(1);
14406 } else if (Op1.getOpcode() == ISD::Constant) {
14407 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14408 uint64_t AndRHSVal = AndRHS->getZExtValue();
14409 SDValue AndLHS = Op0;
14411 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14412 LHS = AndLHS.getOperand(0);
14413 RHS = AndLHS.getOperand(1);
14416 // Use BT if the immediate can't be encoded in a TEST instruction.
14417 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14419 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14423 if (LHS.getNode()) {
14424 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14425 // instruction. Since the shift amount is in-range-or-undefined, we know
14426 // that doing a bittest on the i32 value is ok. We extend to i32 because
14427 // the encoding for the i16 version is larger than the i32 version.
14428 // Also promote i16 to i32 for performance / code size reason.
14429 if (LHS.getValueType() == MVT::i8 ||
14430 LHS.getValueType() == MVT::i16)
14431 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14433 // If the operand types disagree, extend the shift amount to match. Since
14434 // BT ignores high bits (like shifts) we can use anyextend.
14435 if (LHS.getValueType() != RHS.getValueType())
14436 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14438 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14439 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14440 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14441 DAG.getConstant(Cond, MVT::i8), BT);
14447 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14449 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14454 // SSE Condition code mapping:
14463 switch (SetCCOpcode) {
14464 default: llvm_unreachable("Unexpected SETCC condition");
14466 case ISD::SETEQ: SSECC = 0; break;
14468 case ISD::SETGT: Swap = true; // Fallthrough
14470 case ISD::SETOLT: SSECC = 1; break;
14472 case ISD::SETGE: Swap = true; // Fallthrough
14474 case ISD::SETOLE: SSECC = 2; break;
14475 case ISD::SETUO: SSECC = 3; break;
14477 case ISD::SETNE: SSECC = 4; break;
14478 case ISD::SETULE: Swap = true; // Fallthrough
14479 case ISD::SETUGE: SSECC = 5; break;
14480 case ISD::SETULT: Swap = true; // Fallthrough
14481 case ISD::SETUGT: SSECC = 6; break;
14482 case ISD::SETO: SSECC = 7; break;
14484 case ISD::SETONE: SSECC = 8; break;
14487 std::swap(Op0, Op1);
14492 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14493 // ones, and then concatenate the result back.
14494 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14495 MVT VT = Op.getSimpleValueType();
14497 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14498 "Unsupported value type for operation");
14500 unsigned NumElems = VT.getVectorNumElements();
14502 SDValue CC = Op.getOperand(2);
14504 // Extract the LHS vectors
14505 SDValue LHS = Op.getOperand(0);
14506 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14507 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14509 // Extract the RHS vectors
14510 SDValue RHS = Op.getOperand(1);
14511 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14512 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14514 // Issue the operation on the smaller types and concatenate the result back
14515 MVT EltVT = VT.getVectorElementType();
14516 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14518 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14519 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14522 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14523 const X86Subtarget *Subtarget) {
14524 SDValue Op0 = Op.getOperand(0);
14525 SDValue Op1 = Op.getOperand(1);
14526 SDValue CC = Op.getOperand(2);
14527 MVT VT = Op.getSimpleValueType();
14530 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14531 Op.getValueType().getScalarType() == MVT::i1 &&
14532 "Cannot set masked compare for this operation");
14534 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14536 bool Unsigned = false;
14539 switch (SetCCOpcode) {
14540 default: llvm_unreachable("Unexpected SETCC condition");
14541 case ISD::SETNE: SSECC = 4; break;
14542 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14543 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14544 case ISD::SETLT: Swap = true; //fall-through
14545 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14546 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14547 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14548 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14549 case ISD::SETULE: Unsigned = true; //fall-through
14550 case ISD::SETLE: SSECC = 2; break;
14554 std::swap(Op0, Op1);
14556 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14557 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14558 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14559 DAG.getConstant(SSECC, MVT::i8));
14562 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14563 /// operand \p Op1. If non-trivial (for example because it's not constant)
14564 /// return an empty value.
14565 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14567 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14571 MVT VT = Op1.getSimpleValueType();
14572 MVT EVT = VT.getVectorElementType();
14573 unsigned n = VT.getVectorNumElements();
14574 SmallVector<SDValue, 8> ULTOp1;
14576 for (unsigned i = 0; i < n; ++i) {
14577 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14578 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14581 // Avoid underflow.
14582 APInt Val = Elt->getAPIntValue();
14586 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14589 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14592 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14593 SelectionDAG &DAG) {
14594 SDValue Op0 = Op.getOperand(0);
14595 SDValue Op1 = Op.getOperand(1);
14596 SDValue CC = Op.getOperand(2);
14597 MVT VT = Op.getSimpleValueType();
14598 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14599 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14604 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14605 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14608 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14609 unsigned Opc = X86ISD::CMPP;
14610 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14611 assert(VT.getVectorNumElements() <= 16);
14612 Opc = X86ISD::CMPM;
14614 // In the two special cases we can't handle, emit two comparisons.
14617 unsigned CombineOpc;
14618 if (SetCCOpcode == ISD::SETUEQ) {
14619 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14621 assert(SetCCOpcode == ISD::SETONE);
14622 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14625 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14626 DAG.getConstant(CC0, MVT::i8));
14627 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14628 DAG.getConstant(CC1, MVT::i8));
14629 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14631 // Handle all other FP comparisons here.
14632 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14633 DAG.getConstant(SSECC, MVT::i8));
14636 // Break 256-bit integer vector compare into smaller ones.
14637 if (VT.is256BitVector() && !Subtarget->hasInt256())
14638 return Lower256IntVSETCC(Op, DAG);
14640 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14641 EVT OpVT = Op1.getValueType();
14642 if (Subtarget->hasAVX512()) {
14643 if (Op1.getValueType().is512BitVector() ||
14644 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14645 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14646 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14648 // In AVX-512 architecture setcc returns mask with i1 elements,
14649 // But there is no compare instruction for i8 and i16 elements in KNL.
14650 // We are not talking about 512-bit operands in this case, these
14651 // types are illegal.
14653 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14654 OpVT.getVectorElementType().getSizeInBits() >= 8))
14655 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14656 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14659 // We are handling one of the integer comparisons here. Since SSE only has
14660 // GT and EQ comparisons for integer, swapping operands and multiple
14661 // operations may be required for some comparisons.
14663 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14664 bool Subus = false;
14666 switch (SetCCOpcode) {
14667 default: llvm_unreachable("Unexpected SETCC condition");
14668 case ISD::SETNE: Invert = true;
14669 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14670 case ISD::SETLT: Swap = true;
14671 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14672 case ISD::SETGE: Swap = true;
14673 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14674 Invert = true; break;
14675 case ISD::SETULT: Swap = true;
14676 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14677 FlipSigns = true; break;
14678 case ISD::SETUGE: Swap = true;
14679 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14680 FlipSigns = true; Invert = true; break;
14683 // Special case: Use min/max operations for SETULE/SETUGE
14684 MVT VET = VT.getVectorElementType();
14686 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14687 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14690 switch (SetCCOpcode) {
14692 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14693 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14696 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14699 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14700 if (!MinMax && hasSubus) {
14701 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14703 // t = psubus Op0, Op1
14704 // pcmpeq t, <0..0>
14705 switch (SetCCOpcode) {
14707 case ISD::SETULT: {
14708 // If the comparison is against a constant we can turn this into a
14709 // setule. With psubus, setule does not require a swap. This is
14710 // beneficial because the constant in the register is no longer
14711 // destructed as the destination so it can be hoisted out of a loop.
14712 // Only do this pre-AVX since vpcmp* is no longer destructive.
14713 if (Subtarget->hasAVX())
14715 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14716 if (ULEOp1.getNode()) {
14718 Subus = true; Invert = false; Swap = false;
14722 // Psubus is better than flip-sign because it requires no inversion.
14723 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14724 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14728 Opc = X86ISD::SUBUS;
14734 std::swap(Op0, Op1);
14736 // Check that the operation in question is available (most are plain SSE2,
14737 // but PCMPGTQ and PCMPEQQ have different requirements).
14738 if (VT == MVT::v2i64) {
14739 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14740 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14742 // First cast everything to the right type.
14743 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14744 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14746 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14747 // bits of the inputs before performing those operations. The lower
14748 // compare is always unsigned.
14751 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14753 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14754 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14755 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14756 Sign, Zero, Sign, Zero);
14758 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14759 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14761 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14762 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14763 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14765 // Create masks for only the low parts/high parts of the 64 bit integers.
14766 static const int MaskHi[] = { 1, 1, 3, 3 };
14767 static const int MaskLo[] = { 0, 0, 2, 2 };
14768 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14769 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14770 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14772 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14773 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14776 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14778 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14781 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14782 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14783 // pcmpeqd + pshufd + pand.
14784 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14786 // First cast everything to the right type.
14787 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14788 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14791 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14793 // Make sure the lower and upper halves are both all-ones.
14794 static const int Mask[] = { 1, 0, 3, 2 };
14795 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14796 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14799 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14801 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14805 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14806 // bits of the inputs before performing those operations.
14808 EVT EltVT = VT.getVectorElementType();
14809 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14810 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14811 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14814 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14816 // If the logical-not of the result is required, perform that now.
14818 Result = DAG.getNOT(dl, Result, VT);
14821 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14824 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14825 getZeroVector(VT, Subtarget, DAG, dl));
14830 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14832 MVT VT = Op.getSimpleValueType();
14834 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14836 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14837 && "SetCC type must be 8-bit or 1-bit integer");
14838 SDValue Op0 = Op.getOperand(0);
14839 SDValue Op1 = Op.getOperand(1);
14841 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14843 // Optimize to BT if possible.
14844 // Lower (X & (1 << N)) == 0 to BT(X, N).
14845 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14846 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14847 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14848 Op1.getOpcode() == ISD::Constant &&
14849 cast<ConstantSDNode>(Op1)->isNullValue() &&
14850 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14851 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14852 if (NewSetCC.getNode())
14856 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14858 if (Op1.getOpcode() == ISD::Constant &&
14859 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14860 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14861 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14863 // If the input is a setcc, then reuse the input setcc or use a new one with
14864 // the inverted condition.
14865 if (Op0.getOpcode() == X86ISD::SETCC) {
14866 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14867 bool Invert = (CC == ISD::SETNE) ^
14868 cast<ConstantSDNode>(Op1)->isNullValue();
14872 CCode = X86::GetOppositeBranchCondition(CCode);
14873 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14874 DAG.getConstant(CCode, MVT::i8),
14875 Op0.getOperand(1));
14877 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14881 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14882 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14883 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14885 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14886 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14889 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14890 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14891 if (X86CC == X86::COND_INVALID)
14894 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14895 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14896 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14897 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14899 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14903 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14904 static bool isX86LogicalCmp(SDValue Op) {
14905 unsigned Opc = Op.getNode()->getOpcode();
14906 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14907 Opc == X86ISD::SAHF)
14909 if (Op.getResNo() == 1 &&
14910 (Opc == X86ISD::ADD ||
14911 Opc == X86ISD::SUB ||
14912 Opc == X86ISD::ADC ||
14913 Opc == X86ISD::SBB ||
14914 Opc == X86ISD::SMUL ||
14915 Opc == X86ISD::UMUL ||
14916 Opc == X86ISD::INC ||
14917 Opc == X86ISD::DEC ||
14918 Opc == X86ISD::OR ||
14919 Opc == X86ISD::XOR ||
14920 Opc == X86ISD::AND))
14923 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14929 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14930 if (V.getOpcode() != ISD::TRUNCATE)
14933 SDValue VOp0 = V.getOperand(0);
14934 unsigned InBits = VOp0.getValueSizeInBits();
14935 unsigned Bits = V.getValueSizeInBits();
14936 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14939 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14940 bool addTest = true;
14941 SDValue Cond = Op.getOperand(0);
14942 SDValue Op1 = Op.getOperand(1);
14943 SDValue Op2 = Op.getOperand(2);
14945 EVT VT = Op1.getValueType();
14948 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14949 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14950 // sequence later on.
14951 if (Cond.getOpcode() == ISD::SETCC &&
14952 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14953 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14954 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14955 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14956 int SSECC = translateX86FSETCC(
14957 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14960 if (Subtarget->hasAVX512()) {
14961 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14962 DAG.getConstant(SSECC, MVT::i8));
14963 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14965 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14966 DAG.getConstant(SSECC, MVT::i8));
14967 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14968 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14969 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14973 if (Cond.getOpcode() == ISD::SETCC) {
14974 SDValue NewCond = LowerSETCC(Cond, DAG);
14975 if (NewCond.getNode())
14979 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14980 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14981 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14982 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14983 if (Cond.getOpcode() == X86ISD::SETCC &&
14984 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14985 isZero(Cond.getOperand(1).getOperand(1))) {
14986 SDValue Cmp = Cond.getOperand(1);
14988 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14990 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14991 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14992 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14994 SDValue CmpOp0 = Cmp.getOperand(0);
14995 // Apply further optimizations for special cases
14996 // (select (x != 0), -1, 0) -> neg & sbb
14997 // (select (x == 0), 0, -1) -> neg & sbb
14998 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14999 if (YC->isNullValue() &&
15000 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15001 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15002 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15003 DAG.getConstant(0, CmpOp0.getValueType()),
15005 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15006 DAG.getConstant(X86::COND_B, MVT::i8),
15007 SDValue(Neg.getNode(), 1));
15011 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15012 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15013 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15015 SDValue Res = // Res = 0 or -1.
15016 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15017 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15019 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15020 Res = DAG.getNOT(DL, Res, Res.getValueType());
15022 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15023 if (!N2C || !N2C->isNullValue())
15024 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15029 // Look past (and (setcc_carry (cmp ...)), 1).
15030 if (Cond.getOpcode() == ISD::AND &&
15031 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15032 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15033 if (C && C->getAPIntValue() == 1)
15034 Cond = Cond.getOperand(0);
15037 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15038 // setting operand in place of the X86ISD::SETCC.
15039 unsigned CondOpcode = Cond.getOpcode();
15040 if (CondOpcode == X86ISD::SETCC ||
15041 CondOpcode == X86ISD::SETCC_CARRY) {
15042 CC = Cond.getOperand(0);
15044 SDValue Cmp = Cond.getOperand(1);
15045 unsigned Opc = Cmp.getOpcode();
15046 MVT VT = Op.getSimpleValueType();
15048 bool IllegalFPCMov = false;
15049 if (VT.isFloatingPoint() && !VT.isVector() &&
15050 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15051 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15053 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15054 Opc == X86ISD::BT) { // FIXME
15058 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15059 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15060 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15061 Cond.getOperand(0).getValueType() != MVT::i8)) {
15062 SDValue LHS = Cond.getOperand(0);
15063 SDValue RHS = Cond.getOperand(1);
15064 unsigned X86Opcode;
15067 switch (CondOpcode) {
15068 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15069 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15070 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15071 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15072 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15073 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15074 default: llvm_unreachable("unexpected overflowing operator");
15076 if (CondOpcode == ISD::UMULO)
15077 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15080 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15082 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15084 if (CondOpcode == ISD::UMULO)
15085 Cond = X86Op.getValue(2);
15087 Cond = X86Op.getValue(1);
15089 CC = DAG.getConstant(X86Cond, MVT::i8);
15094 // Look pass the truncate if the high bits are known zero.
15095 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15096 Cond = Cond.getOperand(0);
15098 // We know the result of AND is compared against zero. Try to match
15100 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15101 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15102 if (NewSetCC.getNode()) {
15103 CC = NewSetCC.getOperand(0);
15104 Cond = NewSetCC.getOperand(1);
15111 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15112 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15115 // a < b ? -1 : 0 -> RES = ~setcc_carry
15116 // a < b ? 0 : -1 -> RES = setcc_carry
15117 // a >= b ? -1 : 0 -> RES = setcc_carry
15118 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15119 if (Cond.getOpcode() == X86ISD::SUB) {
15120 Cond = ConvertCmpIfNecessary(Cond, DAG);
15121 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15123 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15124 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15125 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15126 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15127 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15128 return DAG.getNOT(DL, Res, Res.getValueType());
15133 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15134 // widen the cmov and push the truncate through. This avoids introducing a new
15135 // branch during isel and doesn't add any extensions.
15136 if (Op.getValueType() == MVT::i8 &&
15137 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15138 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15139 if (T1.getValueType() == T2.getValueType() &&
15140 // Blacklist CopyFromReg to avoid partial register stalls.
15141 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15142 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15143 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15144 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15148 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15149 // condition is true.
15150 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15151 SDValue Ops[] = { Op2, Op1, CC, Cond };
15152 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15155 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15156 SelectionDAG &DAG) {
15157 MVT VT = Op->getSimpleValueType(0);
15158 SDValue In = Op->getOperand(0);
15159 MVT InVT = In.getSimpleValueType();
15160 MVT VTElt = VT.getVectorElementType();
15161 MVT InVTElt = InVT.getVectorElementType();
15165 if ((InVTElt == MVT::i1) &&
15166 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15167 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15169 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15170 VTElt.getSizeInBits() <= 16)) ||
15172 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15173 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15175 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15176 VTElt.getSizeInBits() >= 32))))
15177 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15179 unsigned int NumElts = VT.getVectorNumElements();
15181 if (NumElts != 8 && NumElts != 16)
15184 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15185 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15187 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15188 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15190 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15191 Constant *C = ConstantInt::get(*DAG.getContext(),
15192 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15194 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15195 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15196 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15197 MachinePointerInfo::getConstantPool(),
15198 false, false, false, Alignment);
15199 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15200 if (VT.is512BitVector())
15202 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15205 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15206 SelectionDAG &DAG) {
15207 MVT VT = Op->getSimpleValueType(0);
15208 SDValue In = Op->getOperand(0);
15209 MVT InVT = In.getSimpleValueType();
15212 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15213 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15215 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15216 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15217 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15220 if (Subtarget->hasInt256())
15221 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15223 // Optimize vectors in AVX mode
15224 // Sign extend v8i16 to v8i32 and
15227 // Divide input vector into two parts
15228 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15229 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15230 // concat the vectors to original VT
15232 unsigned NumElems = InVT.getVectorNumElements();
15233 SDValue Undef = DAG.getUNDEF(InVT);
15235 SmallVector<int,8> ShufMask1(NumElems, -1);
15236 for (unsigned i = 0; i != NumElems/2; ++i)
15239 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15241 SmallVector<int,8> ShufMask2(NumElems, -1);
15242 for (unsigned i = 0; i != NumElems/2; ++i)
15243 ShufMask2[i] = i + NumElems/2;
15245 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15247 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15248 VT.getVectorNumElements()/2);
15250 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15251 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15253 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15256 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15257 // may emit an illegal shuffle but the expansion is still better than scalar
15258 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15259 // we'll emit a shuffle and a arithmetic shift.
15260 // TODO: It is possible to support ZExt by zeroing the undef values during
15261 // the shuffle phase or after the shuffle.
15262 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15263 SelectionDAG &DAG) {
15264 MVT RegVT = Op.getSimpleValueType();
15265 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15266 assert(RegVT.isInteger() &&
15267 "We only custom lower integer vector sext loads.");
15269 // Nothing useful we can do without SSE2 shuffles.
15270 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15272 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15274 EVT MemVT = Ld->getMemoryVT();
15275 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15276 unsigned RegSz = RegVT.getSizeInBits();
15278 ISD::LoadExtType Ext = Ld->getExtensionType();
15280 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15281 && "Only anyext and sext are currently implemented.");
15282 assert(MemVT != RegVT && "Cannot extend to the same type");
15283 assert(MemVT.isVector() && "Must load a vector from memory");
15285 unsigned NumElems = RegVT.getVectorNumElements();
15286 unsigned MemSz = MemVT.getSizeInBits();
15287 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15289 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15290 // The only way in which we have a legal 256-bit vector result but not the
15291 // integer 256-bit operations needed to directly lower a sextload is if we
15292 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15293 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15294 // correctly legalized. We do this late to allow the canonical form of
15295 // sextload to persist throughout the rest of the DAG combiner -- it wants
15296 // to fold together any extensions it can, and so will fuse a sign_extend
15297 // of an sextload into a sextload targeting a wider value.
15299 if (MemSz == 128) {
15300 // Just switch this to a normal load.
15301 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15302 "it must be a legal 128-bit vector "
15304 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15305 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15306 Ld->isInvariant(), Ld->getAlignment());
15308 assert(MemSz < 128 &&
15309 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15310 // Do an sext load to a 128-bit vector type. We want to use the same
15311 // number of elements, but elements half as wide. This will end up being
15312 // recursively lowered by this routine, but will succeed as we definitely
15313 // have all the necessary features if we're using AVX1.
15315 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15316 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15318 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15319 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15320 Ld->isNonTemporal(), Ld->isInvariant(),
15321 Ld->getAlignment());
15324 // Replace chain users with the new chain.
15325 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15326 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15328 // Finally, do a normal sign-extend to the desired register.
15329 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15332 // All sizes must be a power of two.
15333 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15334 "Non-power-of-two elements are not custom lowered!");
15336 // Attempt to load the original value using scalar loads.
15337 // Find the largest scalar type that divides the total loaded size.
15338 MVT SclrLoadTy = MVT::i8;
15339 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15340 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15341 MVT Tp = (MVT::SimpleValueType)tp;
15342 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15347 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15348 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15350 SclrLoadTy = MVT::f64;
15352 // Calculate the number of scalar loads that we need to perform
15353 // in order to load our vector from memory.
15354 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15356 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15357 "Can only lower sext loads with a single scalar load!");
15359 unsigned loadRegZize = RegSz;
15360 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15363 // Represent our vector as a sequence of elements which are the
15364 // largest scalar that we can load.
15365 EVT LoadUnitVecVT = EVT::getVectorVT(
15366 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15368 // Represent the data using the same element type that is stored in
15369 // memory. In practice, we ''widen'' MemVT.
15371 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15372 loadRegZize / MemVT.getScalarType().getSizeInBits());
15374 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15375 "Invalid vector type");
15377 // We can't shuffle using an illegal type.
15378 assert(TLI.isTypeLegal(WideVecVT) &&
15379 "We only lower types that form legal widened vector types");
15381 SmallVector<SDValue, 8> Chains;
15382 SDValue Ptr = Ld->getBasePtr();
15383 SDValue Increment =
15384 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15385 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15387 for (unsigned i = 0; i < NumLoads; ++i) {
15388 // Perform a single load.
15389 SDValue ScalarLoad =
15390 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15391 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15392 Ld->getAlignment());
15393 Chains.push_back(ScalarLoad.getValue(1));
15394 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15395 // another round of DAGCombining.
15397 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15399 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15400 ScalarLoad, DAG.getIntPtrConstant(i));
15402 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15405 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15407 // Bitcast the loaded value to a vector of the original element type, in
15408 // the size of the target vector type.
15409 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15410 unsigned SizeRatio = RegSz / MemSz;
15412 if (Ext == ISD::SEXTLOAD) {
15413 // If we have SSE4.1, we can directly emit a VSEXT node.
15414 if (Subtarget->hasSSE41()) {
15415 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15416 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15420 // Otherwise we'll shuffle the small elements in the high bits of the
15421 // larger type and perform an arithmetic shift. If the shift is not legal
15422 // it's better to scalarize.
15423 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15424 "We can't implement a sext load without an arithmetic right shift!");
15426 // Redistribute the loaded elements into the different locations.
15427 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15428 for (unsigned i = 0; i != NumElems; ++i)
15429 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15431 SDValue Shuff = DAG.getVectorShuffle(
15432 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15434 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15436 // Build the arithmetic shift.
15437 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15438 MemVT.getVectorElementType().getSizeInBits();
15440 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15442 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15446 // Redistribute the loaded elements into the different locations.
15447 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15448 for (unsigned i = 0; i != NumElems; ++i)
15449 ShuffleVec[i * SizeRatio] = i;
15451 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15452 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15454 // Bitcast to the requested type.
15455 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15456 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15460 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15461 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15462 // from the AND / OR.
15463 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15464 Opc = Op.getOpcode();
15465 if (Opc != ISD::OR && Opc != ISD::AND)
15467 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15468 Op.getOperand(0).hasOneUse() &&
15469 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15470 Op.getOperand(1).hasOneUse());
15473 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15474 // 1 and that the SETCC node has a single use.
15475 static bool isXor1OfSetCC(SDValue Op) {
15476 if (Op.getOpcode() != ISD::XOR)
15478 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15479 if (N1C && N1C->getAPIntValue() == 1) {
15480 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15481 Op.getOperand(0).hasOneUse();
15486 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15487 bool addTest = true;
15488 SDValue Chain = Op.getOperand(0);
15489 SDValue Cond = Op.getOperand(1);
15490 SDValue Dest = Op.getOperand(2);
15493 bool Inverted = false;
15495 if (Cond.getOpcode() == ISD::SETCC) {
15496 // Check for setcc([su]{add,sub,mul}o == 0).
15497 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15498 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15499 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15500 Cond.getOperand(0).getResNo() == 1 &&
15501 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15502 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15503 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15504 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15505 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15506 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15508 Cond = Cond.getOperand(0);
15510 SDValue NewCond = LowerSETCC(Cond, DAG);
15511 if (NewCond.getNode())
15516 // FIXME: LowerXALUO doesn't handle these!!
15517 else if (Cond.getOpcode() == X86ISD::ADD ||
15518 Cond.getOpcode() == X86ISD::SUB ||
15519 Cond.getOpcode() == X86ISD::SMUL ||
15520 Cond.getOpcode() == X86ISD::UMUL)
15521 Cond = LowerXALUO(Cond, DAG);
15524 // Look pass (and (setcc_carry (cmp ...)), 1).
15525 if (Cond.getOpcode() == ISD::AND &&
15526 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15527 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15528 if (C && C->getAPIntValue() == 1)
15529 Cond = Cond.getOperand(0);
15532 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15533 // setting operand in place of the X86ISD::SETCC.
15534 unsigned CondOpcode = Cond.getOpcode();
15535 if (CondOpcode == X86ISD::SETCC ||
15536 CondOpcode == X86ISD::SETCC_CARRY) {
15537 CC = Cond.getOperand(0);
15539 SDValue Cmp = Cond.getOperand(1);
15540 unsigned Opc = Cmp.getOpcode();
15541 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15542 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15546 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15550 // These can only come from an arithmetic instruction with overflow,
15551 // e.g. SADDO, UADDO.
15552 Cond = Cond.getNode()->getOperand(1);
15558 CondOpcode = Cond.getOpcode();
15559 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15560 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15561 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15562 Cond.getOperand(0).getValueType() != MVT::i8)) {
15563 SDValue LHS = Cond.getOperand(0);
15564 SDValue RHS = Cond.getOperand(1);
15565 unsigned X86Opcode;
15568 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15569 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15571 switch (CondOpcode) {
15572 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15574 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15576 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15579 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15580 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15584 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15587 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15588 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15589 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15590 default: llvm_unreachable("unexpected overflowing operator");
15593 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15594 if (CondOpcode == ISD::UMULO)
15595 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15598 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15600 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15602 if (CondOpcode == ISD::UMULO)
15603 Cond = X86Op.getValue(2);
15605 Cond = X86Op.getValue(1);
15607 CC = DAG.getConstant(X86Cond, MVT::i8);
15611 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15612 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15613 if (CondOpc == ISD::OR) {
15614 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15615 // two branches instead of an explicit OR instruction with a
15617 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15618 isX86LogicalCmp(Cmp)) {
15619 CC = Cond.getOperand(0).getOperand(0);
15620 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15621 Chain, Dest, CC, Cmp);
15622 CC = Cond.getOperand(1).getOperand(0);
15626 } else { // ISD::AND
15627 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15628 // two branches instead of an explicit AND instruction with a
15629 // separate test. However, we only do this if this block doesn't
15630 // have a fall-through edge, because this requires an explicit
15631 // jmp when the condition is false.
15632 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15633 isX86LogicalCmp(Cmp) &&
15634 Op.getNode()->hasOneUse()) {
15635 X86::CondCode CCode =
15636 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15637 CCode = X86::GetOppositeBranchCondition(CCode);
15638 CC = DAG.getConstant(CCode, MVT::i8);
15639 SDNode *User = *Op.getNode()->use_begin();
15640 // Look for an unconditional branch following this conditional branch.
15641 // We need this because we need to reverse the successors in order
15642 // to implement FCMP_OEQ.
15643 if (User->getOpcode() == ISD::BR) {
15644 SDValue FalseBB = User->getOperand(1);
15646 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15647 assert(NewBR == User);
15651 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15652 Chain, Dest, CC, Cmp);
15653 X86::CondCode CCode =
15654 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15655 CCode = X86::GetOppositeBranchCondition(CCode);
15656 CC = DAG.getConstant(CCode, MVT::i8);
15662 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15663 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15664 // It should be transformed during dag combiner except when the condition
15665 // is set by a arithmetics with overflow node.
15666 X86::CondCode CCode =
15667 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15668 CCode = X86::GetOppositeBranchCondition(CCode);
15669 CC = DAG.getConstant(CCode, MVT::i8);
15670 Cond = Cond.getOperand(0).getOperand(1);
15672 } else if (Cond.getOpcode() == ISD::SETCC &&
15673 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15674 // For FCMP_OEQ, we can emit
15675 // two branches instead of an explicit AND instruction with a
15676 // separate test. However, we only do this if this block doesn't
15677 // have a fall-through edge, because this requires an explicit
15678 // jmp when the condition is false.
15679 if (Op.getNode()->hasOneUse()) {
15680 SDNode *User = *Op.getNode()->use_begin();
15681 // Look for an unconditional branch following this conditional branch.
15682 // We need this because we need to reverse the successors in order
15683 // to implement FCMP_OEQ.
15684 if (User->getOpcode() == ISD::BR) {
15685 SDValue FalseBB = User->getOperand(1);
15687 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15688 assert(NewBR == User);
15692 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15693 Cond.getOperand(0), Cond.getOperand(1));
15694 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15695 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15696 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15697 Chain, Dest, CC, Cmp);
15698 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15703 } else if (Cond.getOpcode() == ISD::SETCC &&
15704 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15705 // For FCMP_UNE, we can emit
15706 // two branches instead of an explicit AND instruction with a
15707 // separate test. However, we only do this if this block doesn't
15708 // have a fall-through edge, because this requires an explicit
15709 // jmp when the condition is false.
15710 if (Op.getNode()->hasOneUse()) {
15711 SDNode *User = *Op.getNode()->use_begin();
15712 // Look for an unconditional branch following this conditional branch.
15713 // We need this because we need to reverse the successors in order
15714 // to implement FCMP_UNE.
15715 if (User->getOpcode() == ISD::BR) {
15716 SDValue FalseBB = User->getOperand(1);
15718 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15719 assert(NewBR == User);
15722 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15723 Cond.getOperand(0), Cond.getOperand(1));
15724 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15725 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15726 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15727 Chain, Dest, CC, Cmp);
15728 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15738 // Look pass the truncate if the high bits are known zero.
15739 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15740 Cond = Cond.getOperand(0);
15742 // We know the result of AND is compared against zero. Try to match
15744 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15745 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15746 if (NewSetCC.getNode()) {
15747 CC = NewSetCC.getOperand(0);
15748 Cond = NewSetCC.getOperand(1);
15755 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15756 CC = DAG.getConstant(X86Cond, MVT::i8);
15757 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15759 Cond = ConvertCmpIfNecessary(Cond, DAG);
15760 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15761 Chain, Dest, CC, Cond);
15764 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15765 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15766 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15767 // that the guard pages used by the OS virtual memory manager are allocated in
15768 // correct sequence.
15770 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15771 SelectionDAG &DAG) const {
15772 MachineFunction &MF = DAG.getMachineFunction();
15773 bool SplitStack = MF.shouldSplitStack();
15774 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15779 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15780 SDNode* Node = Op.getNode();
15782 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15783 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15784 " not tell us which reg is the stack pointer!");
15785 EVT VT = Node->getValueType(0);
15786 SDValue Tmp1 = SDValue(Node, 0);
15787 SDValue Tmp2 = SDValue(Node, 1);
15788 SDValue Tmp3 = Node->getOperand(2);
15789 SDValue Chain = Tmp1.getOperand(0);
15791 // Chain the dynamic stack allocation so that it doesn't modify the stack
15792 // pointer when other instructions are using the stack.
15793 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15796 SDValue Size = Tmp2.getOperand(1);
15797 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15798 Chain = SP.getValue(1);
15799 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15800 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15801 unsigned StackAlign = TFI.getStackAlignment();
15802 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15803 if (Align > StackAlign)
15804 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15805 DAG.getConstant(-(uint64_t)Align, VT));
15806 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15808 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15809 DAG.getIntPtrConstant(0, true), SDValue(),
15812 SDValue Ops[2] = { Tmp1, Tmp2 };
15813 return DAG.getMergeValues(Ops, dl);
15817 SDValue Chain = Op.getOperand(0);
15818 SDValue Size = Op.getOperand(1);
15819 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15820 EVT VT = Op.getNode()->getValueType(0);
15822 bool Is64Bit = Subtarget->is64Bit();
15823 EVT SPTy = getPointerTy();
15826 MachineRegisterInfo &MRI = MF.getRegInfo();
15829 // The 64 bit implementation of segmented stacks needs to clobber both r10
15830 // r11. This makes it impossible to use it along with nested parameters.
15831 const Function *F = MF.getFunction();
15833 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15835 if (I->hasNestAttr())
15836 report_fatal_error("Cannot use segmented stacks with functions that "
15837 "have nested arguments.");
15840 const TargetRegisterClass *AddrRegClass =
15841 getRegClassFor(getPointerTy());
15842 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15843 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15844 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15845 DAG.getRegister(Vreg, SPTy));
15846 SDValue Ops1[2] = { Value, Chain };
15847 return DAG.getMergeValues(Ops1, dl);
15850 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15852 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15853 Flag = Chain.getValue(1);
15854 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15856 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15858 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15859 DAG.getSubtarget().getRegisterInfo());
15860 unsigned SPReg = RegInfo->getStackRegister();
15861 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15862 Chain = SP.getValue(1);
15865 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15866 DAG.getConstant(-(uint64_t)Align, VT));
15867 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15870 SDValue Ops1[2] = { SP, Chain };
15871 return DAG.getMergeValues(Ops1, dl);
15875 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15876 MachineFunction &MF = DAG.getMachineFunction();
15877 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15879 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15882 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15883 // vastart just stores the address of the VarArgsFrameIndex slot into the
15884 // memory location argument.
15885 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15887 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15888 MachinePointerInfo(SV), false, false, 0);
15892 // gp_offset (0 - 6 * 8)
15893 // fp_offset (48 - 48 + 8 * 16)
15894 // overflow_arg_area (point to parameters coming in memory).
15896 SmallVector<SDValue, 8> MemOps;
15897 SDValue FIN = Op.getOperand(1);
15899 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15900 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15902 FIN, MachinePointerInfo(SV), false, false, 0);
15903 MemOps.push_back(Store);
15906 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15907 FIN, DAG.getIntPtrConstant(4));
15908 Store = DAG.getStore(Op.getOperand(0), DL,
15909 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15911 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15912 MemOps.push_back(Store);
15914 // Store ptr to overflow_arg_area
15915 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15916 FIN, DAG.getIntPtrConstant(4));
15917 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15919 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15920 MachinePointerInfo(SV, 8),
15922 MemOps.push_back(Store);
15924 // Store ptr to reg_save_area.
15925 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15926 FIN, DAG.getIntPtrConstant(8));
15927 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15929 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15930 MachinePointerInfo(SV, 16), false, false, 0);
15931 MemOps.push_back(Store);
15932 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15935 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15936 assert(Subtarget->is64Bit() &&
15937 "LowerVAARG only handles 64-bit va_arg!");
15938 assert((Subtarget->isTargetLinux() ||
15939 Subtarget->isTargetDarwin()) &&
15940 "Unhandled target in LowerVAARG");
15941 assert(Op.getNode()->getNumOperands() == 4);
15942 SDValue Chain = Op.getOperand(0);
15943 SDValue SrcPtr = Op.getOperand(1);
15944 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15945 unsigned Align = Op.getConstantOperandVal(3);
15948 EVT ArgVT = Op.getNode()->getValueType(0);
15949 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15950 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15953 // Decide which area this value should be read from.
15954 // TODO: Implement the AMD64 ABI in its entirety. This simple
15955 // selection mechanism works only for the basic types.
15956 if (ArgVT == MVT::f80) {
15957 llvm_unreachable("va_arg for f80 not yet implemented");
15958 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15959 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15960 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15961 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15963 llvm_unreachable("Unhandled argument type in LowerVAARG");
15966 if (ArgMode == 2) {
15967 // Sanity Check: Make sure using fp_offset makes sense.
15968 assert(!DAG.getTarget().Options.UseSoftFloat &&
15969 !(DAG.getMachineFunction()
15970 .getFunction()->getAttributes()
15971 .hasAttribute(AttributeSet::FunctionIndex,
15972 Attribute::NoImplicitFloat)) &&
15973 Subtarget->hasSSE1());
15976 // Insert VAARG_64 node into the DAG
15977 // VAARG_64 returns two values: Variable Argument Address, Chain
15978 SmallVector<SDValue, 11> InstOps;
15979 InstOps.push_back(Chain);
15980 InstOps.push_back(SrcPtr);
15981 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15982 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15983 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15984 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15985 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15986 VTs, InstOps, MVT::i64,
15987 MachinePointerInfo(SV),
15989 /*Volatile=*/false,
15991 /*WriteMem=*/true);
15992 Chain = VAARG.getValue(1);
15994 // Load the next argument and return it
15995 return DAG.getLoad(ArgVT, dl,
15998 MachinePointerInfo(),
15999 false, false, false, 0);
16002 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16003 SelectionDAG &DAG) {
16004 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16005 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16006 SDValue Chain = Op.getOperand(0);
16007 SDValue DstPtr = Op.getOperand(1);
16008 SDValue SrcPtr = Op.getOperand(2);
16009 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16010 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16013 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16014 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16016 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16019 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16020 // amount is a constant. Takes immediate version of shift as input.
16021 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16022 SDValue SrcOp, uint64_t ShiftAmt,
16023 SelectionDAG &DAG) {
16024 MVT ElementType = VT.getVectorElementType();
16026 // Fold this packed shift into its first operand if ShiftAmt is 0.
16030 // Check for ShiftAmt >= element width
16031 if (ShiftAmt >= ElementType.getSizeInBits()) {
16032 if (Opc == X86ISD::VSRAI)
16033 ShiftAmt = ElementType.getSizeInBits() - 1;
16035 return DAG.getConstant(0, VT);
16038 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16039 && "Unknown target vector shift-by-constant node");
16041 // Fold this packed vector shift into a build vector if SrcOp is a
16042 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16043 if (VT == SrcOp.getSimpleValueType() &&
16044 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16045 SmallVector<SDValue, 8> Elts;
16046 unsigned NumElts = SrcOp->getNumOperands();
16047 ConstantSDNode *ND;
16050 default: llvm_unreachable(nullptr);
16051 case X86ISD::VSHLI:
16052 for (unsigned i=0; i!=NumElts; ++i) {
16053 SDValue CurrentOp = SrcOp->getOperand(i);
16054 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16055 Elts.push_back(CurrentOp);
16058 ND = cast<ConstantSDNode>(CurrentOp);
16059 const APInt &C = ND->getAPIntValue();
16060 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16063 case X86ISD::VSRLI:
16064 for (unsigned i=0; i!=NumElts; ++i) {
16065 SDValue CurrentOp = SrcOp->getOperand(i);
16066 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16067 Elts.push_back(CurrentOp);
16070 ND = cast<ConstantSDNode>(CurrentOp);
16071 const APInt &C = ND->getAPIntValue();
16072 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16075 case X86ISD::VSRAI:
16076 for (unsigned i=0; i!=NumElts; ++i) {
16077 SDValue CurrentOp = SrcOp->getOperand(i);
16078 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16079 Elts.push_back(CurrentOp);
16082 ND = cast<ConstantSDNode>(CurrentOp);
16083 const APInt &C = ND->getAPIntValue();
16084 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16089 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16092 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16095 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16096 // may or may not be a constant. Takes immediate version of shift as input.
16097 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16098 SDValue SrcOp, SDValue ShAmt,
16099 SelectionDAG &DAG) {
16100 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16102 // Catch shift-by-constant.
16103 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16104 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16105 CShAmt->getZExtValue(), DAG);
16107 // Change opcode to non-immediate version
16109 default: llvm_unreachable("Unknown target vector shift node");
16110 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16111 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16112 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16115 // Need to build a vector containing shift amount
16116 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16119 ShOps[1] = DAG.getConstant(0, MVT::i32);
16120 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16121 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16123 // The return type has to be a 128-bit type with the same element
16124 // type as the input type.
16125 MVT EltVT = VT.getVectorElementType();
16126 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16128 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16129 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16132 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16133 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16134 /// necessary casting for \p Mask when lowering masking intrinsics.
16135 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16136 SDValue PreservedSrc, SelectionDAG &DAG) {
16137 EVT VT = Op.getValueType();
16138 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16139 MVT::i1, VT.getVectorNumElements());
16140 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16141 Mask.getValueType().getSizeInBits());
16144 assert(MaskVT.isSimple() && "invalid mask type");
16146 if (isAllOnes(Mask))
16149 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16150 // are extracted by EXTRACT_SUBVECTOR.
16151 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16152 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16153 DAG.getIntPtrConstant(0));
16155 switch (Op.getOpcode()) {
16157 case X86ISD::PCMPEQM:
16158 case X86ISD::PCMPGTM:
16160 case X86ISD::CMPMU:
16161 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16164 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16167 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16169 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16170 case Intrinsic::x86_fma_vfmadd_ps:
16171 case Intrinsic::x86_fma_vfmadd_pd:
16172 case Intrinsic::x86_fma_vfmadd_ps_256:
16173 case Intrinsic::x86_fma_vfmadd_pd_256:
16174 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16175 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16176 return X86ISD::FMADD;
16177 case Intrinsic::x86_fma_vfmsub_ps:
16178 case Intrinsic::x86_fma_vfmsub_pd:
16179 case Intrinsic::x86_fma_vfmsub_ps_256:
16180 case Intrinsic::x86_fma_vfmsub_pd_256:
16181 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16182 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16183 return X86ISD::FMSUB;
16184 case Intrinsic::x86_fma_vfnmadd_ps:
16185 case Intrinsic::x86_fma_vfnmadd_pd:
16186 case Intrinsic::x86_fma_vfnmadd_ps_256:
16187 case Intrinsic::x86_fma_vfnmadd_pd_256:
16188 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16189 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16190 return X86ISD::FNMADD;
16191 case Intrinsic::x86_fma_vfnmsub_ps:
16192 case Intrinsic::x86_fma_vfnmsub_pd:
16193 case Intrinsic::x86_fma_vfnmsub_ps_256:
16194 case Intrinsic::x86_fma_vfnmsub_pd_256:
16195 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16196 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16197 return X86ISD::FNMSUB;
16198 case Intrinsic::x86_fma_vfmaddsub_ps:
16199 case Intrinsic::x86_fma_vfmaddsub_pd:
16200 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16201 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16202 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16203 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16204 return X86ISD::FMADDSUB;
16205 case Intrinsic::x86_fma_vfmsubadd_ps:
16206 case Intrinsic::x86_fma_vfmsubadd_pd:
16207 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16208 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16209 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16210 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16211 return X86ISD::FMSUBADD;
16215 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16217 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16219 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16221 switch(IntrData->Type) {
16222 case INTR_TYPE_1OP:
16223 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16224 case INTR_TYPE_2OP:
16225 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16227 case INTR_TYPE_3OP:
16228 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16229 Op.getOperand(2), Op.getOperand(3));
16231 case CMP_MASK_CC: {
16232 // Comparison intrinsics with masks.
16233 // Example of transformation:
16234 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16235 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16237 // (v8i1 (insert_subvector undef,
16238 // (v2i1 (and (PCMPEQM %a, %b),
16239 // (extract_subvector
16240 // (v8i1 (bitcast %mask)), 0))), 0))))
16241 EVT VT = Op.getOperand(1).getValueType();
16242 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16243 VT.getVectorNumElements());
16244 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16245 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16246 Mask.getValueType().getSizeInBits());
16248 if (IntrData->Type == CMP_MASK_CC) {
16249 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16250 Op.getOperand(2), Op.getOperand(3));
16252 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16253 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16256 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16257 DAG.getTargetConstant(0, MaskVT), DAG);
16258 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16259 DAG.getUNDEF(BitcastVT), CmpMask,
16260 DAG.getIntPtrConstant(0));
16261 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16263 case COMI: { // Comparison intrinsics
16264 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16265 SDValue LHS = Op.getOperand(1);
16266 SDValue RHS = Op.getOperand(2);
16267 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16268 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16269 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16270 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16271 DAG.getConstant(X86CC, MVT::i8), Cond);
16272 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16275 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16276 Op.getOperand(1), Op.getOperand(2), DAG);
16283 default: return SDValue(); // Don't custom lower most intrinsics.
16285 // Arithmetic intrinsics.
16286 case Intrinsic::x86_sse2_pmulu_dq:
16287 case Intrinsic::x86_avx2_pmulu_dq:
16288 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16289 Op.getOperand(1), Op.getOperand(2));
16291 case Intrinsic::x86_sse41_pmuldq:
16292 case Intrinsic::x86_avx2_pmul_dq:
16293 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16294 Op.getOperand(1), Op.getOperand(2));
16296 case Intrinsic::x86_sse2_pmulhu_w:
16297 case Intrinsic::x86_avx2_pmulhu_w:
16298 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16299 Op.getOperand(1), Op.getOperand(2));
16301 case Intrinsic::x86_sse2_pmulh_w:
16302 case Intrinsic::x86_avx2_pmulh_w:
16303 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16304 Op.getOperand(1), Op.getOperand(2));
16306 // SSE/SSE2/AVX floating point max/min intrinsics.
16307 case Intrinsic::x86_sse_max_ps:
16308 case Intrinsic::x86_sse2_max_pd:
16309 case Intrinsic::x86_avx_max_ps_256:
16310 case Intrinsic::x86_avx_max_pd_256:
16311 case Intrinsic::x86_sse_min_ps:
16312 case Intrinsic::x86_sse2_min_pd:
16313 case Intrinsic::x86_avx_min_ps_256:
16314 case Intrinsic::x86_avx_min_pd_256: {
16317 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16318 case Intrinsic::x86_sse_max_ps:
16319 case Intrinsic::x86_sse2_max_pd:
16320 case Intrinsic::x86_avx_max_ps_256:
16321 case Intrinsic::x86_avx_max_pd_256:
16322 Opcode = X86ISD::FMAX;
16324 case Intrinsic::x86_sse_min_ps:
16325 case Intrinsic::x86_sse2_min_pd:
16326 case Intrinsic::x86_avx_min_ps_256:
16327 case Intrinsic::x86_avx_min_pd_256:
16328 Opcode = X86ISD::FMIN;
16331 return DAG.getNode(Opcode, dl, Op.getValueType(),
16332 Op.getOperand(1), Op.getOperand(2));
16335 // AVX2 variable shift intrinsics
16336 case Intrinsic::x86_avx2_psllv_d:
16337 case Intrinsic::x86_avx2_psllv_q:
16338 case Intrinsic::x86_avx2_psllv_d_256:
16339 case Intrinsic::x86_avx2_psllv_q_256:
16340 case Intrinsic::x86_avx2_psrlv_d:
16341 case Intrinsic::x86_avx2_psrlv_q:
16342 case Intrinsic::x86_avx2_psrlv_d_256:
16343 case Intrinsic::x86_avx2_psrlv_q_256:
16344 case Intrinsic::x86_avx2_psrav_d:
16345 case Intrinsic::x86_avx2_psrav_d_256: {
16348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16349 case Intrinsic::x86_avx2_psllv_d:
16350 case Intrinsic::x86_avx2_psllv_q:
16351 case Intrinsic::x86_avx2_psllv_d_256:
16352 case Intrinsic::x86_avx2_psllv_q_256:
16355 case Intrinsic::x86_avx2_psrlv_d:
16356 case Intrinsic::x86_avx2_psrlv_q:
16357 case Intrinsic::x86_avx2_psrlv_d_256:
16358 case Intrinsic::x86_avx2_psrlv_q_256:
16361 case Intrinsic::x86_avx2_psrav_d:
16362 case Intrinsic::x86_avx2_psrav_d_256:
16366 return DAG.getNode(Opcode, dl, Op.getValueType(),
16367 Op.getOperand(1), Op.getOperand(2));
16370 case Intrinsic::x86_sse2_packssdw_128:
16371 case Intrinsic::x86_sse2_packsswb_128:
16372 case Intrinsic::x86_avx2_packssdw:
16373 case Intrinsic::x86_avx2_packsswb:
16374 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16375 Op.getOperand(1), Op.getOperand(2));
16377 case Intrinsic::x86_sse2_packuswb_128:
16378 case Intrinsic::x86_sse41_packusdw:
16379 case Intrinsic::x86_avx2_packuswb:
16380 case Intrinsic::x86_avx2_packusdw:
16381 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16382 Op.getOperand(1), Op.getOperand(2));
16384 case Intrinsic::x86_ssse3_pshuf_b_128:
16385 case Intrinsic::x86_avx2_pshuf_b:
16386 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16387 Op.getOperand(1), Op.getOperand(2));
16389 case Intrinsic::x86_sse2_pshuf_d:
16390 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16391 Op.getOperand(1), Op.getOperand(2));
16393 case Intrinsic::x86_sse2_pshufl_w:
16394 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16395 Op.getOperand(1), Op.getOperand(2));
16397 case Intrinsic::x86_sse2_pshufh_w:
16398 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16399 Op.getOperand(1), Op.getOperand(2));
16401 case Intrinsic::x86_ssse3_psign_b_128:
16402 case Intrinsic::x86_ssse3_psign_w_128:
16403 case Intrinsic::x86_ssse3_psign_d_128:
16404 case Intrinsic::x86_avx2_psign_b:
16405 case Intrinsic::x86_avx2_psign_w:
16406 case Intrinsic::x86_avx2_psign_d:
16407 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16408 Op.getOperand(1), Op.getOperand(2));
16410 case Intrinsic::x86_avx2_permd:
16411 case Intrinsic::x86_avx2_permps:
16412 // Operands intentionally swapped. Mask is last operand to intrinsic,
16413 // but second operand for node/instruction.
16414 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16415 Op.getOperand(2), Op.getOperand(1));
16417 case Intrinsic::x86_avx512_mask_valign_q_512:
16418 case Intrinsic::x86_avx512_mask_valign_d_512:
16419 // Vector source operands are swapped.
16420 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16421 Op.getValueType(), Op.getOperand(2),
16424 Op.getOperand(5), Op.getOperand(4), DAG);
16426 // ptest and testp intrinsics. The intrinsic these come from are designed to
16427 // return an integer value, not just an instruction so lower it to the ptest
16428 // or testp pattern and a setcc for the result.
16429 case Intrinsic::x86_sse41_ptestz:
16430 case Intrinsic::x86_sse41_ptestc:
16431 case Intrinsic::x86_sse41_ptestnzc:
16432 case Intrinsic::x86_avx_ptestz_256:
16433 case Intrinsic::x86_avx_ptestc_256:
16434 case Intrinsic::x86_avx_ptestnzc_256:
16435 case Intrinsic::x86_avx_vtestz_ps:
16436 case Intrinsic::x86_avx_vtestc_ps:
16437 case Intrinsic::x86_avx_vtestnzc_ps:
16438 case Intrinsic::x86_avx_vtestz_pd:
16439 case Intrinsic::x86_avx_vtestc_pd:
16440 case Intrinsic::x86_avx_vtestnzc_pd:
16441 case Intrinsic::x86_avx_vtestz_ps_256:
16442 case Intrinsic::x86_avx_vtestc_ps_256:
16443 case Intrinsic::x86_avx_vtestnzc_ps_256:
16444 case Intrinsic::x86_avx_vtestz_pd_256:
16445 case Intrinsic::x86_avx_vtestc_pd_256:
16446 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16447 bool IsTestPacked = false;
16450 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16451 case Intrinsic::x86_avx_vtestz_ps:
16452 case Intrinsic::x86_avx_vtestz_pd:
16453 case Intrinsic::x86_avx_vtestz_ps_256:
16454 case Intrinsic::x86_avx_vtestz_pd_256:
16455 IsTestPacked = true; // Fallthrough
16456 case Intrinsic::x86_sse41_ptestz:
16457 case Intrinsic::x86_avx_ptestz_256:
16459 X86CC = X86::COND_E;
16461 case Intrinsic::x86_avx_vtestc_ps:
16462 case Intrinsic::x86_avx_vtestc_pd:
16463 case Intrinsic::x86_avx_vtestc_ps_256:
16464 case Intrinsic::x86_avx_vtestc_pd_256:
16465 IsTestPacked = true; // Fallthrough
16466 case Intrinsic::x86_sse41_ptestc:
16467 case Intrinsic::x86_avx_ptestc_256:
16469 X86CC = X86::COND_B;
16471 case Intrinsic::x86_avx_vtestnzc_ps:
16472 case Intrinsic::x86_avx_vtestnzc_pd:
16473 case Intrinsic::x86_avx_vtestnzc_ps_256:
16474 case Intrinsic::x86_avx_vtestnzc_pd_256:
16475 IsTestPacked = true; // Fallthrough
16476 case Intrinsic::x86_sse41_ptestnzc:
16477 case Intrinsic::x86_avx_ptestnzc_256:
16479 X86CC = X86::COND_A;
16483 SDValue LHS = Op.getOperand(1);
16484 SDValue RHS = Op.getOperand(2);
16485 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16486 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16487 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16488 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16489 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16491 case Intrinsic::x86_avx512_kortestz_w:
16492 case Intrinsic::x86_avx512_kortestc_w: {
16493 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16494 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16495 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16496 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16497 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16498 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16499 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16502 case Intrinsic::x86_sse42_pcmpistria128:
16503 case Intrinsic::x86_sse42_pcmpestria128:
16504 case Intrinsic::x86_sse42_pcmpistric128:
16505 case Intrinsic::x86_sse42_pcmpestric128:
16506 case Intrinsic::x86_sse42_pcmpistrio128:
16507 case Intrinsic::x86_sse42_pcmpestrio128:
16508 case Intrinsic::x86_sse42_pcmpistris128:
16509 case Intrinsic::x86_sse42_pcmpestris128:
16510 case Intrinsic::x86_sse42_pcmpistriz128:
16511 case Intrinsic::x86_sse42_pcmpestriz128: {
16515 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16516 case Intrinsic::x86_sse42_pcmpistria128:
16517 Opcode = X86ISD::PCMPISTRI;
16518 X86CC = X86::COND_A;
16520 case Intrinsic::x86_sse42_pcmpestria128:
16521 Opcode = X86ISD::PCMPESTRI;
16522 X86CC = X86::COND_A;
16524 case Intrinsic::x86_sse42_pcmpistric128:
16525 Opcode = X86ISD::PCMPISTRI;
16526 X86CC = X86::COND_B;
16528 case Intrinsic::x86_sse42_pcmpestric128:
16529 Opcode = X86ISD::PCMPESTRI;
16530 X86CC = X86::COND_B;
16532 case Intrinsic::x86_sse42_pcmpistrio128:
16533 Opcode = X86ISD::PCMPISTRI;
16534 X86CC = X86::COND_O;
16536 case Intrinsic::x86_sse42_pcmpestrio128:
16537 Opcode = X86ISD::PCMPESTRI;
16538 X86CC = X86::COND_O;
16540 case Intrinsic::x86_sse42_pcmpistris128:
16541 Opcode = X86ISD::PCMPISTRI;
16542 X86CC = X86::COND_S;
16544 case Intrinsic::x86_sse42_pcmpestris128:
16545 Opcode = X86ISD::PCMPESTRI;
16546 X86CC = X86::COND_S;
16548 case Intrinsic::x86_sse42_pcmpistriz128:
16549 Opcode = X86ISD::PCMPISTRI;
16550 X86CC = X86::COND_E;
16552 case Intrinsic::x86_sse42_pcmpestriz128:
16553 Opcode = X86ISD::PCMPESTRI;
16554 X86CC = X86::COND_E;
16557 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16558 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16559 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16560 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16561 DAG.getConstant(X86CC, MVT::i8),
16562 SDValue(PCMP.getNode(), 1));
16563 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16566 case Intrinsic::x86_sse42_pcmpistri128:
16567 case Intrinsic::x86_sse42_pcmpestri128: {
16569 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16570 Opcode = X86ISD::PCMPISTRI;
16572 Opcode = X86ISD::PCMPESTRI;
16574 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16575 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16576 return DAG.getNode(Opcode, dl, VTs, NewOps);
16579 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16580 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16581 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16582 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16583 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16584 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16585 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16586 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16587 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16588 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16589 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16590 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16591 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16592 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16593 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16594 dl, Op.getValueType(),
16598 Op.getOperand(4), Op.getOperand(1), DAG);
16603 case Intrinsic::x86_fma_vfmadd_ps:
16604 case Intrinsic::x86_fma_vfmadd_pd:
16605 case Intrinsic::x86_fma_vfmsub_ps:
16606 case Intrinsic::x86_fma_vfmsub_pd:
16607 case Intrinsic::x86_fma_vfnmadd_ps:
16608 case Intrinsic::x86_fma_vfnmadd_pd:
16609 case Intrinsic::x86_fma_vfnmsub_ps:
16610 case Intrinsic::x86_fma_vfnmsub_pd:
16611 case Intrinsic::x86_fma_vfmaddsub_ps:
16612 case Intrinsic::x86_fma_vfmaddsub_pd:
16613 case Intrinsic::x86_fma_vfmsubadd_ps:
16614 case Intrinsic::x86_fma_vfmsubadd_pd:
16615 case Intrinsic::x86_fma_vfmadd_ps_256:
16616 case Intrinsic::x86_fma_vfmadd_pd_256:
16617 case Intrinsic::x86_fma_vfmsub_ps_256:
16618 case Intrinsic::x86_fma_vfmsub_pd_256:
16619 case Intrinsic::x86_fma_vfnmadd_ps_256:
16620 case Intrinsic::x86_fma_vfnmadd_pd_256:
16621 case Intrinsic::x86_fma_vfnmsub_ps_256:
16622 case Intrinsic::x86_fma_vfnmsub_pd_256:
16623 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16624 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16625 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16626 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16627 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16628 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16632 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16633 SDValue Src, SDValue Mask, SDValue Base,
16634 SDValue Index, SDValue ScaleOp, SDValue Chain,
16635 const X86Subtarget * Subtarget) {
16637 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16638 assert(C && "Invalid scale type");
16639 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16640 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16641 Index.getSimpleValueType().getVectorNumElements());
16643 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16645 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16647 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16648 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16649 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16650 SDValue Segment = DAG.getRegister(0, MVT::i32);
16651 if (Src.getOpcode() == ISD::UNDEF)
16652 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16653 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16654 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16655 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16656 return DAG.getMergeValues(RetOps, dl);
16659 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16660 SDValue Src, SDValue Mask, SDValue Base,
16661 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16663 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16664 assert(C && "Invalid scale type");
16665 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16666 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16667 SDValue Segment = DAG.getRegister(0, MVT::i32);
16668 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16669 Index.getSimpleValueType().getVectorNumElements());
16671 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16673 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16675 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16676 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16677 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16678 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16679 return SDValue(Res, 1);
16682 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16683 SDValue Mask, SDValue Base, SDValue Index,
16684 SDValue ScaleOp, SDValue Chain) {
16686 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16687 assert(C && "Invalid scale type");
16688 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16689 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16690 SDValue Segment = DAG.getRegister(0, MVT::i32);
16692 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16694 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16696 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16698 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16699 //SDVTList VTs = DAG.getVTList(MVT::Other);
16700 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16701 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16702 return SDValue(Res, 0);
16705 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16706 // read performance monitor counters (x86_rdpmc).
16707 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16708 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16709 SmallVectorImpl<SDValue> &Results) {
16710 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16711 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16714 // The ECX register is used to select the index of the performance counter
16716 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16718 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16720 // Reads the content of a 64-bit performance counter and returns it in the
16721 // registers EDX:EAX.
16722 if (Subtarget->is64Bit()) {
16723 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16724 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16727 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16728 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16731 Chain = HI.getValue(1);
16733 if (Subtarget->is64Bit()) {
16734 // The EAX register is loaded with the low-order 32 bits. The EDX register
16735 // is loaded with the supported high-order bits of the counter.
16736 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16737 DAG.getConstant(32, MVT::i8));
16738 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16739 Results.push_back(Chain);
16743 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16744 SDValue Ops[] = { LO, HI };
16745 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16746 Results.push_back(Pair);
16747 Results.push_back(Chain);
16750 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16751 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16752 // also used to custom lower READCYCLECOUNTER nodes.
16753 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16754 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16755 SmallVectorImpl<SDValue> &Results) {
16756 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16757 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16760 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16761 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16762 // and the EAX register is loaded with the low-order 32 bits.
16763 if (Subtarget->is64Bit()) {
16764 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16765 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16768 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16769 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16772 SDValue Chain = HI.getValue(1);
16774 if (Opcode == X86ISD::RDTSCP_DAG) {
16775 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16777 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16778 // the ECX register. Add 'ecx' explicitly to the chain.
16779 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16781 // Explicitly store the content of ECX at the location passed in input
16782 // to the 'rdtscp' intrinsic.
16783 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16784 MachinePointerInfo(), false, false, 0);
16787 if (Subtarget->is64Bit()) {
16788 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16789 // the EAX register is loaded with the low-order 32 bits.
16790 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16791 DAG.getConstant(32, MVT::i8));
16792 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16793 Results.push_back(Chain);
16797 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16798 SDValue Ops[] = { LO, HI };
16799 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16800 Results.push_back(Pair);
16801 Results.push_back(Chain);
16804 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16805 SelectionDAG &DAG) {
16806 SmallVector<SDValue, 2> Results;
16808 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16810 return DAG.getMergeValues(Results, DL);
16814 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16815 SelectionDAG &DAG) {
16816 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16818 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16823 switch(IntrData->Type) {
16825 llvm_unreachable("Unknown Intrinsic Type");
16829 // Emit the node with the right value type.
16830 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16831 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16833 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16834 // Otherwise return the value from Rand, which is always 0, casted to i32.
16835 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16836 DAG.getConstant(1, Op->getValueType(1)),
16837 DAG.getConstant(X86::COND_B, MVT::i32),
16838 SDValue(Result.getNode(), 1) };
16839 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16840 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16843 // Return { result, isValid, chain }.
16844 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16845 SDValue(Result.getNode(), 2));
16848 //gather(v1, mask, index, base, scale);
16849 SDValue Chain = Op.getOperand(0);
16850 SDValue Src = Op.getOperand(2);
16851 SDValue Base = Op.getOperand(3);
16852 SDValue Index = Op.getOperand(4);
16853 SDValue Mask = Op.getOperand(5);
16854 SDValue Scale = Op.getOperand(6);
16855 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16859 //scatter(base, mask, index, v1, scale);
16860 SDValue Chain = Op.getOperand(0);
16861 SDValue Base = Op.getOperand(2);
16862 SDValue Mask = Op.getOperand(3);
16863 SDValue Index = Op.getOperand(4);
16864 SDValue Src = Op.getOperand(5);
16865 SDValue Scale = Op.getOperand(6);
16866 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16869 SDValue Hint = Op.getOperand(6);
16871 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16872 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16873 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16874 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16875 SDValue Chain = Op.getOperand(0);
16876 SDValue Mask = Op.getOperand(2);
16877 SDValue Index = Op.getOperand(3);
16878 SDValue Base = Op.getOperand(4);
16879 SDValue Scale = Op.getOperand(5);
16880 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16882 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16884 SmallVector<SDValue, 2> Results;
16885 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16886 return DAG.getMergeValues(Results, dl);
16888 // Read Performance Monitoring Counters.
16890 SmallVector<SDValue, 2> Results;
16891 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16892 return DAG.getMergeValues(Results, dl);
16894 // XTEST intrinsics.
16896 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16897 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16898 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16899 DAG.getConstant(X86::COND_NE, MVT::i8),
16901 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16902 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16903 Ret, SDValue(InTrans.getNode(), 1));
16907 SmallVector<SDValue, 2> Results;
16908 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16909 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16910 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16911 DAG.getConstant(-1, MVT::i8));
16912 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16913 Op.getOperand(4), GenCF.getValue(1));
16914 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16915 Op.getOperand(5), MachinePointerInfo(),
16917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16918 DAG.getConstant(X86::COND_B, MVT::i8),
16920 Results.push_back(SetCC);
16921 Results.push_back(Store);
16922 return DAG.getMergeValues(Results, dl);
16927 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16928 SelectionDAG &DAG) const {
16929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16930 MFI->setReturnAddressIsTaken(true);
16932 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16935 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16937 EVT PtrVT = getPointerTy();
16940 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16941 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16942 DAG.getSubtarget().getRegisterInfo());
16943 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16944 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16945 DAG.getNode(ISD::ADD, dl, PtrVT,
16946 FrameAddr, Offset),
16947 MachinePointerInfo(), false, false, false, 0);
16950 // Just load the return address.
16951 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16952 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16953 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16956 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16957 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16958 MFI->setFrameAddressIsTaken(true);
16960 EVT VT = Op.getValueType();
16961 SDLoc dl(Op); // FIXME probably not meaningful
16962 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16963 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16964 DAG.getSubtarget().getRegisterInfo());
16965 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16966 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16967 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16968 "Invalid Frame Register!");
16969 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16971 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16972 MachinePointerInfo(),
16973 false, false, false, 0);
16977 // FIXME? Maybe this could be a TableGen attribute on some registers and
16978 // this table could be generated automatically from RegInfo.
16979 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16981 unsigned Reg = StringSwitch<unsigned>(RegName)
16982 .Case("esp", X86::ESP)
16983 .Case("rsp", X86::RSP)
16987 report_fatal_error("Invalid register name global variable");
16990 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16991 SelectionDAG &DAG) const {
16992 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16993 DAG.getSubtarget().getRegisterInfo());
16994 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16997 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16998 SDValue Chain = Op.getOperand(0);
16999 SDValue Offset = Op.getOperand(1);
17000 SDValue Handler = Op.getOperand(2);
17003 EVT PtrVT = getPointerTy();
17004 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17005 DAG.getSubtarget().getRegisterInfo());
17006 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17007 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17008 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17009 "Invalid Frame Register!");
17010 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17011 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17013 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17014 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17015 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17016 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17018 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17020 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17021 DAG.getRegister(StoreAddrReg, PtrVT));
17024 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17025 SelectionDAG &DAG) const {
17027 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17028 DAG.getVTList(MVT::i32, MVT::Other),
17029 Op.getOperand(0), Op.getOperand(1));
17032 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17033 SelectionDAG &DAG) const {
17035 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17036 Op.getOperand(0), Op.getOperand(1));
17039 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17040 return Op.getOperand(0);
17043 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17044 SelectionDAG &DAG) const {
17045 SDValue Root = Op.getOperand(0);
17046 SDValue Trmp = Op.getOperand(1); // trampoline
17047 SDValue FPtr = Op.getOperand(2); // nested function
17048 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17051 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17052 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17054 if (Subtarget->is64Bit()) {
17055 SDValue OutChains[6];
17057 // Large code-model.
17058 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17059 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17061 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17062 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17064 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17066 // Load the pointer to the nested function into R11.
17067 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17068 SDValue Addr = Trmp;
17069 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17070 Addr, MachinePointerInfo(TrmpAddr),
17073 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17074 DAG.getConstant(2, MVT::i64));
17075 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17076 MachinePointerInfo(TrmpAddr, 2),
17079 // Load the 'nest' parameter value into R10.
17080 // R10 is specified in X86CallingConv.td
17081 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17083 DAG.getConstant(10, MVT::i64));
17084 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17085 Addr, MachinePointerInfo(TrmpAddr, 10),
17088 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17089 DAG.getConstant(12, MVT::i64));
17090 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17091 MachinePointerInfo(TrmpAddr, 12),
17094 // Jump to the nested function.
17095 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17096 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17097 DAG.getConstant(20, MVT::i64));
17098 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17099 Addr, MachinePointerInfo(TrmpAddr, 20),
17102 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17104 DAG.getConstant(22, MVT::i64));
17105 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17106 MachinePointerInfo(TrmpAddr, 22),
17109 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17111 const Function *Func =
17112 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17113 CallingConv::ID CC = Func->getCallingConv();
17118 llvm_unreachable("Unsupported calling convention");
17119 case CallingConv::C:
17120 case CallingConv::X86_StdCall: {
17121 // Pass 'nest' parameter in ECX.
17122 // Must be kept in sync with X86CallingConv.td
17123 NestReg = X86::ECX;
17125 // Check that ECX wasn't needed by an 'inreg' parameter.
17126 FunctionType *FTy = Func->getFunctionType();
17127 const AttributeSet &Attrs = Func->getAttributes();
17129 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17130 unsigned InRegCount = 0;
17133 for (FunctionType::param_iterator I = FTy->param_begin(),
17134 E = FTy->param_end(); I != E; ++I, ++Idx)
17135 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17136 // FIXME: should only count parameters that are lowered to integers.
17137 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17139 if (InRegCount > 2) {
17140 report_fatal_error("Nest register in use - reduce number of inreg"
17146 case CallingConv::X86_FastCall:
17147 case CallingConv::X86_ThisCall:
17148 case CallingConv::Fast:
17149 // Pass 'nest' parameter in EAX.
17150 // Must be kept in sync with X86CallingConv.td
17151 NestReg = X86::EAX;
17155 SDValue OutChains[4];
17156 SDValue Addr, Disp;
17158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17159 DAG.getConstant(10, MVT::i32));
17160 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17162 // This is storing the opcode for MOV32ri.
17163 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17164 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17165 OutChains[0] = DAG.getStore(Root, dl,
17166 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17167 Trmp, MachinePointerInfo(TrmpAddr),
17170 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17171 DAG.getConstant(1, MVT::i32));
17172 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17173 MachinePointerInfo(TrmpAddr, 1),
17176 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17178 DAG.getConstant(5, MVT::i32));
17179 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17180 MachinePointerInfo(TrmpAddr, 5),
17183 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17184 DAG.getConstant(6, MVT::i32));
17185 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17186 MachinePointerInfo(TrmpAddr, 6),
17189 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17193 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17194 SelectionDAG &DAG) const {
17196 The rounding mode is in bits 11:10 of FPSR, and has the following
17198 00 Round to nearest
17203 FLT_ROUNDS, on the other hand, expects the following:
17210 To perform the conversion, we do:
17211 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17214 MachineFunction &MF = DAG.getMachineFunction();
17215 const TargetMachine &TM = MF.getTarget();
17216 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17217 unsigned StackAlignment = TFI.getStackAlignment();
17218 MVT VT = Op.getSimpleValueType();
17221 // Save FP Control Word to stack slot
17222 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17223 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17225 MachineMemOperand *MMO =
17226 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17227 MachineMemOperand::MOStore, 2, 2);
17229 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17230 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17231 DAG.getVTList(MVT::Other),
17232 Ops, MVT::i16, MMO);
17234 // Load FP Control Word from stack slot
17235 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17236 MachinePointerInfo(), false, false, false, 0);
17238 // Transform as necessary
17240 DAG.getNode(ISD::SRL, DL, MVT::i16,
17241 DAG.getNode(ISD::AND, DL, MVT::i16,
17242 CWD, DAG.getConstant(0x800, MVT::i16)),
17243 DAG.getConstant(11, MVT::i8));
17245 DAG.getNode(ISD::SRL, DL, MVT::i16,
17246 DAG.getNode(ISD::AND, DL, MVT::i16,
17247 CWD, DAG.getConstant(0x400, MVT::i16)),
17248 DAG.getConstant(9, MVT::i8));
17251 DAG.getNode(ISD::AND, DL, MVT::i16,
17252 DAG.getNode(ISD::ADD, DL, MVT::i16,
17253 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17254 DAG.getConstant(1, MVT::i16)),
17255 DAG.getConstant(3, MVT::i16));
17257 return DAG.getNode((VT.getSizeInBits() < 16 ?
17258 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17261 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17262 MVT VT = Op.getSimpleValueType();
17264 unsigned NumBits = VT.getSizeInBits();
17267 Op = Op.getOperand(0);
17268 if (VT == MVT::i8) {
17269 // Zero extend to i32 since there is not an i8 bsr.
17271 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17274 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17275 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17276 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17278 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17281 DAG.getConstant(NumBits+NumBits-1, OpVT),
17282 DAG.getConstant(X86::COND_E, MVT::i8),
17285 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17287 // Finally xor with NumBits-1.
17288 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17291 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17295 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17296 MVT VT = Op.getSimpleValueType();
17298 unsigned NumBits = VT.getSizeInBits();
17301 Op = Op.getOperand(0);
17302 if (VT == MVT::i8) {
17303 // Zero extend to i32 since there is not an i8 bsr.
17305 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17308 // Issue a bsr (scan bits in reverse).
17309 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17310 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17312 // And xor with NumBits-1.
17313 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17316 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17320 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17321 MVT VT = Op.getSimpleValueType();
17322 unsigned NumBits = VT.getSizeInBits();
17324 Op = Op.getOperand(0);
17326 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17327 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17328 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17330 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17333 DAG.getConstant(NumBits, VT),
17334 DAG.getConstant(X86::COND_E, MVT::i8),
17337 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17340 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17341 // ones, and then concatenate the result back.
17342 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17343 MVT VT = Op.getSimpleValueType();
17345 assert(VT.is256BitVector() && VT.isInteger() &&
17346 "Unsupported value type for operation");
17348 unsigned NumElems = VT.getVectorNumElements();
17351 // Extract the LHS vectors
17352 SDValue LHS = Op.getOperand(0);
17353 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17354 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17356 // Extract the RHS vectors
17357 SDValue RHS = Op.getOperand(1);
17358 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17359 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17361 MVT EltVT = VT.getVectorElementType();
17362 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17364 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17365 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17366 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17369 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17370 assert(Op.getSimpleValueType().is256BitVector() &&
17371 Op.getSimpleValueType().isInteger() &&
17372 "Only handle AVX 256-bit vector integer operation");
17373 return Lower256IntArith(Op, DAG);
17376 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17377 assert(Op.getSimpleValueType().is256BitVector() &&
17378 Op.getSimpleValueType().isInteger() &&
17379 "Only handle AVX 256-bit vector integer operation");
17380 return Lower256IntArith(Op, DAG);
17383 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17384 SelectionDAG &DAG) {
17386 MVT VT = Op.getSimpleValueType();
17388 // Decompose 256-bit ops into smaller 128-bit ops.
17389 if (VT.is256BitVector() && !Subtarget->hasInt256())
17390 return Lower256IntArith(Op, DAG);
17392 SDValue A = Op.getOperand(0);
17393 SDValue B = Op.getOperand(1);
17395 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17396 if (VT == MVT::v4i32) {
17397 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17398 "Should not custom lower when pmuldq is available!");
17400 // Extract the odd parts.
17401 static const int UnpackMask[] = { 1, -1, 3, -1 };
17402 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17403 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17405 // Multiply the even parts.
17406 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17407 // Now multiply odd parts.
17408 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17410 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17411 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17413 // Merge the two vectors back together with a shuffle. This expands into 2
17415 static const int ShufMask[] = { 0, 4, 2, 6 };
17416 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17419 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17420 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17422 // Ahi = psrlqi(a, 32);
17423 // Bhi = psrlqi(b, 32);
17425 // AloBlo = pmuludq(a, b);
17426 // AloBhi = pmuludq(a, Bhi);
17427 // AhiBlo = pmuludq(Ahi, b);
17429 // AloBhi = psllqi(AloBhi, 32);
17430 // AhiBlo = psllqi(AhiBlo, 32);
17431 // return AloBlo + AloBhi + AhiBlo;
17433 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17434 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17436 // Bit cast to 32-bit vectors for MULUDQ
17437 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17438 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17439 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17440 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17441 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17442 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17444 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17445 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17446 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17448 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17449 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17451 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17452 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17455 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17456 assert(Subtarget->isTargetWin64() && "Unexpected target");
17457 EVT VT = Op.getValueType();
17458 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17459 "Unexpected return type for lowering");
17463 switch (Op->getOpcode()) {
17464 default: llvm_unreachable("Unexpected request for libcall!");
17465 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17466 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17467 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17468 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17469 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17470 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17474 SDValue InChain = DAG.getEntryNode();
17476 TargetLowering::ArgListTy Args;
17477 TargetLowering::ArgListEntry Entry;
17478 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17479 EVT ArgVT = Op->getOperand(i).getValueType();
17480 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17481 "Unexpected argument type for lowering");
17482 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17483 Entry.Node = StackPtr;
17484 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17486 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17487 Entry.Ty = PointerType::get(ArgTy,0);
17488 Entry.isSExt = false;
17489 Entry.isZExt = false;
17490 Args.push_back(Entry);
17493 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17496 TargetLowering::CallLoweringInfo CLI(DAG);
17497 CLI.setDebugLoc(dl).setChain(InChain)
17498 .setCallee(getLibcallCallingConv(LC),
17499 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17500 Callee, std::move(Args), 0)
17501 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17503 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17504 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17507 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17508 SelectionDAG &DAG) {
17509 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17510 EVT VT = Op0.getValueType();
17513 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17514 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17516 // PMULxD operations multiply each even value (starting at 0) of LHS with
17517 // the related value of RHS and produce a widen result.
17518 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17519 // => <2 x i64> <ae|cg>
17521 // In other word, to have all the results, we need to perform two PMULxD:
17522 // 1. one with the even values.
17523 // 2. one with the odd values.
17524 // To achieve #2, with need to place the odd values at an even position.
17526 // Place the odd value at an even position (basically, shift all values 1
17527 // step to the left):
17528 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17529 // <a|b|c|d> => <b|undef|d|undef>
17530 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17531 // <e|f|g|h> => <f|undef|h|undef>
17532 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17534 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17536 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17537 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17539 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17540 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17541 // => <2 x i64> <ae|cg>
17542 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17543 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17544 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17545 // => <2 x i64> <bf|dh>
17546 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17547 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17549 // Shuffle it back into the right order.
17550 SDValue Highs, Lows;
17551 if (VT == MVT::v8i32) {
17552 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17553 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17554 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17555 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17557 const int HighMask[] = {1, 5, 3, 7};
17558 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17559 const int LowMask[] = {0, 4, 2, 6};
17560 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17563 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17564 // unsigned multiply.
17565 if (IsSigned && !Subtarget->hasSSE41()) {
17567 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17568 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17569 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17570 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17571 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17573 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17574 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17577 // The first result of MUL_LOHI is actually the low value, followed by the
17579 SDValue Ops[] = {Lows, Highs};
17580 return DAG.getMergeValues(Ops, dl);
17583 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17584 const X86Subtarget *Subtarget) {
17585 MVT VT = Op.getSimpleValueType();
17587 SDValue R = Op.getOperand(0);
17588 SDValue Amt = Op.getOperand(1);
17590 // Optimize shl/srl/sra with constant shift amount.
17591 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17592 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17593 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17595 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17596 (Subtarget->hasInt256() &&
17597 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17598 (Subtarget->hasAVX512() &&
17599 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17600 if (Op.getOpcode() == ISD::SHL)
17601 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17603 if (Op.getOpcode() == ISD::SRL)
17604 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17606 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17607 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17611 if (VT == MVT::v16i8) {
17612 if (Op.getOpcode() == ISD::SHL) {
17613 // Make a large shift.
17614 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17615 MVT::v8i16, R, ShiftAmt,
17617 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17618 // Zero out the rightmost bits.
17619 SmallVector<SDValue, 16> V(16,
17620 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17622 return DAG.getNode(ISD::AND, dl, VT, SHL,
17623 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17625 if (Op.getOpcode() == ISD::SRL) {
17626 // Make a large shift.
17627 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17628 MVT::v8i16, R, ShiftAmt,
17630 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17631 // Zero out the leftmost bits.
17632 SmallVector<SDValue, 16> V(16,
17633 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17635 return DAG.getNode(ISD::AND, dl, VT, SRL,
17636 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17638 if (Op.getOpcode() == ISD::SRA) {
17639 if (ShiftAmt == 7) {
17640 // R s>> 7 === R s< 0
17641 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17642 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17645 // R s>> a === ((R u>> a) ^ m) - m
17646 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17647 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17649 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17650 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17651 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17654 llvm_unreachable("Unknown shift opcode.");
17657 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17658 if (Op.getOpcode() == ISD::SHL) {
17659 // Make a large shift.
17660 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17661 MVT::v16i16, R, ShiftAmt,
17663 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17664 // Zero out the rightmost bits.
17665 SmallVector<SDValue, 32> V(32,
17666 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17668 return DAG.getNode(ISD::AND, dl, VT, SHL,
17669 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17671 if (Op.getOpcode() == ISD::SRL) {
17672 // Make a large shift.
17673 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17674 MVT::v16i16, R, ShiftAmt,
17676 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17677 // Zero out the leftmost bits.
17678 SmallVector<SDValue, 32> V(32,
17679 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17681 return DAG.getNode(ISD::AND, dl, VT, SRL,
17682 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17684 if (Op.getOpcode() == ISD::SRA) {
17685 if (ShiftAmt == 7) {
17686 // R s>> 7 === R s< 0
17687 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17688 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17691 // R s>> a === ((R u>> a) ^ m) - m
17692 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17693 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17695 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17696 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17697 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17700 llvm_unreachable("Unknown shift opcode.");
17705 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17706 if (!Subtarget->is64Bit() &&
17707 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17708 Amt.getOpcode() == ISD::BITCAST &&
17709 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17710 Amt = Amt.getOperand(0);
17711 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17712 VT.getVectorNumElements();
17713 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17714 uint64_t ShiftAmt = 0;
17715 for (unsigned i = 0; i != Ratio; ++i) {
17716 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17720 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17722 // Check remaining shift amounts.
17723 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17724 uint64_t ShAmt = 0;
17725 for (unsigned j = 0; j != Ratio; ++j) {
17726 ConstantSDNode *C =
17727 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17731 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17733 if (ShAmt != ShiftAmt)
17736 switch (Op.getOpcode()) {
17738 llvm_unreachable("Unknown shift opcode!");
17740 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17743 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17746 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17754 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17755 const X86Subtarget* Subtarget) {
17756 MVT VT = Op.getSimpleValueType();
17758 SDValue R = Op.getOperand(0);
17759 SDValue Amt = Op.getOperand(1);
17761 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17762 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17763 (Subtarget->hasInt256() &&
17764 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17765 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17766 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17768 EVT EltVT = VT.getVectorElementType();
17770 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17771 unsigned NumElts = VT.getVectorNumElements();
17773 for (i = 0; i != NumElts; ++i) {
17774 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17778 for (j = i; j != NumElts; ++j) {
17779 SDValue Arg = Amt.getOperand(j);
17780 if (Arg.getOpcode() == ISD::UNDEF) continue;
17781 if (Arg != Amt.getOperand(i))
17784 if (i != NumElts && j == NumElts)
17785 BaseShAmt = Amt.getOperand(i);
17787 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17788 Amt = Amt.getOperand(0);
17789 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17790 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17791 SDValue InVec = Amt.getOperand(0);
17792 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17793 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17795 for (; i != NumElts; ++i) {
17796 SDValue Arg = InVec.getOperand(i);
17797 if (Arg.getOpcode() == ISD::UNDEF) continue;
17801 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17802 if (ConstantSDNode *C =
17803 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17804 unsigned SplatIdx =
17805 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17806 if (C->getZExtValue() == SplatIdx)
17807 BaseShAmt = InVec.getOperand(1);
17810 if (!BaseShAmt.getNode())
17811 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17812 DAG.getIntPtrConstant(0));
17816 if (BaseShAmt.getNode()) {
17817 if (EltVT.bitsGT(MVT::i32))
17818 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17819 else if (EltVT.bitsLT(MVT::i32))
17820 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17822 switch (Op.getOpcode()) {
17824 llvm_unreachable("Unknown shift opcode!");
17826 switch (VT.SimpleTy) {
17827 default: return SDValue();
17836 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17839 switch (VT.SimpleTy) {
17840 default: return SDValue();
17847 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17850 switch (VT.SimpleTy) {
17851 default: return SDValue();
17860 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17866 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17867 if (!Subtarget->is64Bit() &&
17868 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17869 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17870 Amt.getOpcode() == ISD::BITCAST &&
17871 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17872 Amt = Amt.getOperand(0);
17873 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17874 VT.getVectorNumElements();
17875 std::vector<SDValue> Vals(Ratio);
17876 for (unsigned i = 0; i != Ratio; ++i)
17877 Vals[i] = Amt.getOperand(i);
17878 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17879 for (unsigned j = 0; j != Ratio; ++j)
17880 if (Vals[j] != Amt.getOperand(i + j))
17883 switch (Op.getOpcode()) {
17885 llvm_unreachable("Unknown shift opcode!");
17887 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17889 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17891 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17898 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17899 SelectionDAG &DAG) {
17900 MVT VT = Op.getSimpleValueType();
17902 SDValue R = Op.getOperand(0);
17903 SDValue Amt = Op.getOperand(1);
17906 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17907 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17909 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17913 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17917 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17919 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17920 if (Subtarget->hasInt256()) {
17921 if (Op.getOpcode() == ISD::SRL &&
17922 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17923 VT == MVT::v4i64 || VT == MVT::v8i32))
17925 if (Op.getOpcode() == ISD::SHL &&
17926 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17927 VT == MVT::v4i64 || VT == MVT::v8i32))
17929 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17933 // If possible, lower this packed shift into a vector multiply instead of
17934 // expanding it into a sequence of scalar shifts.
17935 // Do this only if the vector shift count is a constant build_vector.
17936 if (Op.getOpcode() == ISD::SHL &&
17937 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17938 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17939 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17940 SmallVector<SDValue, 8> Elts;
17941 EVT SVT = VT.getScalarType();
17942 unsigned SVTBits = SVT.getSizeInBits();
17943 const APInt &One = APInt(SVTBits, 1);
17944 unsigned NumElems = VT.getVectorNumElements();
17946 for (unsigned i=0; i !=NumElems; ++i) {
17947 SDValue Op = Amt->getOperand(i);
17948 if (Op->getOpcode() == ISD::UNDEF) {
17949 Elts.push_back(Op);
17953 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17954 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17955 uint64_t ShAmt = C.getZExtValue();
17956 if (ShAmt >= SVTBits) {
17957 Elts.push_back(DAG.getUNDEF(SVT));
17960 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17962 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17963 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17966 // Lower SHL with variable shift amount.
17967 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17968 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17970 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17971 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17972 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17973 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17976 // If possible, lower this shift as a sequence of two shifts by
17977 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17979 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17981 // Could be rewritten as:
17982 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17984 // The advantage is that the two shifts from the example would be
17985 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17986 // the vector shift into four scalar shifts plus four pairs of vector
17988 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17989 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17990 unsigned TargetOpcode = X86ISD::MOVSS;
17991 bool CanBeSimplified;
17992 // The splat value for the first packed shift (the 'X' from the example).
17993 SDValue Amt1 = Amt->getOperand(0);
17994 // The splat value for the second packed shift (the 'Y' from the example).
17995 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17996 Amt->getOperand(2);
17998 // See if it is possible to replace this node with a sequence of
17999 // two shifts followed by a MOVSS/MOVSD
18000 if (VT == MVT::v4i32) {
18001 // Check if it is legal to use a MOVSS.
18002 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18003 Amt2 == Amt->getOperand(3);
18004 if (!CanBeSimplified) {
18005 // Otherwise, check if we can still simplify this node using a MOVSD.
18006 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18007 Amt->getOperand(2) == Amt->getOperand(3);
18008 TargetOpcode = X86ISD::MOVSD;
18009 Amt2 = Amt->getOperand(2);
18012 // Do similar checks for the case where the machine value type
18014 CanBeSimplified = Amt1 == Amt->getOperand(1);
18015 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18016 CanBeSimplified = Amt2 == Amt->getOperand(i);
18018 if (!CanBeSimplified) {
18019 TargetOpcode = X86ISD::MOVSD;
18020 CanBeSimplified = true;
18021 Amt2 = Amt->getOperand(4);
18022 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18023 CanBeSimplified = Amt1 == Amt->getOperand(i);
18024 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18025 CanBeSimplified = Amt2 == Amt->getOperand(j);
18029 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18030 isa<ConstantSDNode>(Amt2)) {
18031 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18032 EVT CastVT = MVT::v4i32;
18034 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18035 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18037 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18038 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18039 if (TargetOpcode == X86ISD::MOVSD)
18040 CastVT = MVT::v2i64;
18041 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18042 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18043 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18045 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18049 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18050 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18053 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18054 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18056 // Turn 'a' into a mask suitable for VSELECT
18057 SDValue VSelM = DAG.getConstant(0x80, VT);
18058 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18059 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18061 SDValue CM1 = DAG.getConstant(0x0f, VT);
18062 SDValue CM2 = DAG.getConstant(0x3f, VT);
18064 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18065 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18066 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18067 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18068 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18071 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18072 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18073 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18075 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18076 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18077 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18078 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18079 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18082 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18083 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18084 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18086 // return VSELECT(r, r+r, a);
18087 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18088 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18092 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18093 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18094 // solution better.
18095 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18096 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18098 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18099 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18100 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18101 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18102 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18105 // Decompose 256-bit shifts into smaller 128-bit shifts.
18106 if (VT.is256BitVector()) {
18107 unsigned NumElems = VT.getVectorNumElements();
18108 MVT EltVT = VT.getVectorElementType();
18109 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18111 // Extract the two vectors
18112 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18113 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18115 // Recreate the shift amount vectors
18116 SDValue Amt1, Amt2;
18117 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18118 // Constant shift amount
18119 SmallVector<SDValue, 4> Amt1Csts;
18120 SmallVector<SDValue, 4> Amt2Csts;
18121 for (unsigned i = 0; i != NumElems/2; ++i)
18122 Amt1Csts.push_back(Amt->getOperand(i));
18123 for (unsigned i = NumElems/2; i != NumElems; ++i)
18124 Amt2Csts.push_back(Amt->getOperand(i));
18126 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18127 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18129 // Variable shift amount
18130 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18131 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18134 // Issue new vector shifts for the smaller types
18135 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18136 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18138 // Concatenate the result back
18139 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18145 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18146 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18147 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18148 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18149 // has only one use.
18150 SDNode *N = Op.getNode();
18151 SDValue LHS = N->getOperand(0);
18152 SDValue RHS = N->getOperand(1);
18153 unsigned BaseOp = 0;
18156 switch (Op.getOpcode()) {
18157 default: llvm_unreachable("Unknown ovf instruction!");
18159 // A subtract of one will be selected as a INC. Note that INC doesn't
18160 // set CF, so we can't do this for UADDO.
18161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18163 BaseOp = X86ISD::INC;
18164 Cond = X86::COND_O;
18167 BaseOp = X86ISD::ADD;
18168 Cond = X86::COND_O;
18171 BaseOp = X86ISD::ADD;
18172 Cond = X86::COND_B;
18175 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18176 // set CF, so we can't do this for USUBO.
18177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18179 BaseOp = X86ISD::DEC;
18180 Cond = X86::COND_O;
18183 BaseOp = X86ISD::SUB;
18184 Cond = X86::COND_O;
18187 BaseOp = X86ISD::SUB;
18188 Cond = X86::COND_B;
18191 BaseOp = X86ISD::SMUL;
18192 Cond = X86::COND_O;
18194 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18195 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18197 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18200 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18201 DAG.getConstant(X86::COND_O, MVT::i32),
18202 SDValue(Sum.getNode(), 2));
18204 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18208 // Also sets EFLAGS.
18209 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18210 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18213 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18214 DAG.getConstant(Cond, MVT::i32),
18215 SDValue(Sum.getNode(), 1));
18217 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18220 // Sign extension of the low part of vector elements. This may be used either
18221 // when sign extend instructions are not available or if the vector element
18222 // sizes already match the sign-extended size. If the vector elements are in
18223 // their pre-extended size and sign extend instructions are available, that will
18224 // be handled by LowerSIGN_EXTEND.
18225 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18226 SelectionDAG &DAG) const {
18228 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18229 MVT VT = Op.getSimpleValueType();
18231 if (!Subtarget->hasSSE2() || !VT.isVector())
18234 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18235 ExtraVT.getScalarType().getSizeInBits();
18237 switch (VT.SimpleTy) {
18238 default: return SDValue();
18241 if (!Subtarget->hasFp256())
18243 if (!Subtarget->hasInt256()) {
18244 // needs to be split
18245 unsigned NumElems = VT.getVectorNumElements();
18247 // Extract the LHS vectors
18248 SDValue LHS = Op.getOperand(0);
18249 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18250 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18252 MVT EltVT = VT.getVectorElementType();
18253 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18255 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18256 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18257 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18259 SDValue Extra = DAG.getValueType(ExtraVT);
18261 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18262 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18264 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18269 SDValue Op0 = Op.getOperand(0);
18271 // This is a sign extension of some low part of vector elements without
18272 // changing the size of the vector elements themselves:
18273 // Shift-Left + Shift-Right-Algebraic.
18274 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18276 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18282 /// Returns true if the operand type is exactly twice the native width, and
18283 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18284 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18285 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18286 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18287 const X86Subtarget &Subtarget =
18288 getTargetMachine().getSubtarget<X86Subtarget>();
18289 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18292 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18293 else if (OpWidth == 128)
18294 return Subtarget.hasCmpxchg16b();
18299 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18300 return needsCmpXchgNb(SI->getValueOperand()->getType());
18303 // Note: this turns large loads into lock cmpxchg8b/16b.
18304 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18305 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18306 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18307 return needsCmpXchgNb(PTy->getElementType());
18310 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18311 const X86Subtarget &Subtarget =
18312 getTargetMachine().getSubtarget<X86Subtarget>();
18313 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18314 const Type *MemType = AI->getType();
18316 // If the operand is too big, we must see if cmpxchg8/16b is available
18317 // and default to library calls otherwise.
18318 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18319 return needsCmpXchgNb(MemType);
18321 AtomicRMWInst::BinOp Op = AI->getOperation();
18324 llvm_unreachable("Unknown atomic operation");
18325 case AtomicRMWInst::Xchg:
18326 case AtomicRMWInst::Add:
18327 case AtomicRMWInst::Sub:
18328 // It's better to use xadd, xsub or xchg for these in all cases.
18330 case AtomicRMWInst::Or:
18331 case AtomicRMWInst::And:
18332 case AtomicRMWInst::Xor:
18333 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18334 // prefix to a normal instruction for these operations.
18335 return !AI->use_empty();
18336 case AtomicRMWInst::Nand:
18337 case AtomicRMWInst::Max:
18338 case AtomicRMWInst::Min:
18339 case AtomicRMWInst::UMax:
18340 case AtomicRMWInst::UMin:
18341 // These always require a non-trivial set of data operations on x86. We must
18342 // use a cmpxchg loop.
18347 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18348 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18349 // no-sse2). There isn't any reason to disable it if the target processor
18351 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18355 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18356 const X86Subtarget &Subtarget =
18357 getTargetMachine().getSubtarget<X86Subtarget>();
18358 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18359 const Type *MemType = AI->getType();
18360 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18361 // there is no benefit in turning such RMWs into loads, and it is actually
18362 // harmful as it introduces a mfence.
18363 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18366 auto Builder = IRBuilder<>(AI);
18367 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18368 auto SynchScope = AI->getSynchScope();
18369 // We must restrict the ordering to avoid generating loads with Release or
18370 // ReleaseAcquire orderings.
18371 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18372 auto Ptr = AI->getPointerOperand();
18374 // Before the load we need a fence. Here is an example lifted from
18375 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18378 // x.store(1, relaxed);
18379 // r1 = y.fetch_add(0, release);
18381 // y.fetch_add(42, acquire);
18382 // r2 = x.load(relaxed);
18383 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18384 // lowered to just a load without a fence. A mfence flushes the store buffer,
18385 // making the optimization clearly correct.
18386 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18387 // otherwise, we might be able to be more agressive on relaxed idempotent
18388 // rmw. In practice, they do not look useful, so we don't try to be
18389 // especially clever.
18390 if (SynchScope == SingleThread) {
18391 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18392 // the IR level, so we must wrap it in an intrinsic.
18394 } else if (hasMFENCE(Subtarget)) {
18395 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18396 Intrinsic::x86_sse2_mfence);
18397 Builder.CreateCall(MFence);
18399 // FIXME: it might make sense to use a locked operation here but on a
18400 // different cache-line to prevent cache-line bouncing. In practice it
18401 // is probably a small win, and x86 processors without mfence are rare
18402 // enough that we do not bother.
18406 // Finally we can emit the atomic load.
18407 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18408 AI->getType()->getPrimitiveSizeInBits());
18409 Loaded->setAtomic(Order, SynchScope);
18410 AI->replaceAllUsesWith(Loaded);
18411 AI->eraseFromParent();
18415 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18416 SelectionDAG &DAG) {
18418 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18419 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18420 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18421 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18423 // The only fence that needs an instruction is a sequentially-consistent
18424 // cross-thread fence.
18425 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18426 if (hasMFENCE(*Subtarget))
18427 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18429 SDValue Chain = Op.getOperand(0);
18430 SDValue Zero = DAG.getConstant(0, MVT::i32);
18432 DAG.getRegister(X86::ESP, MVT::i32), // Base
18433 DAG.getTargetConstant(1, MVT::i8), // Scale
18434 DAG.getRegister(0, MVT::i32), // Index
18435 DAG.getTargetConstant(0, MVT::i32), // Disp
18436 DAG.getRegister(0, MVT::i32), // Segment.
18440 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18441 return SDValue(Res, 0);
18444 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18445 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18448 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18449 SelectionDAG &DAG) {
18450 MVT T = Op.getSimpleValueType();
18454 switch(T.SimpleTy) {
18455 default: llvm_unreachable("Invalid value type!");
18456 case MVT::i8: Reg = X86::AL; size = 1; break;
18457 case MVT::i16: Reg = X86::AX; size = 2; break;
18458 case MVT::i32: Reg = X86::EAX; size = 4; break;
18460 assert(Subtarget->is64Bit() && "Node not type legal!");
18461 Reg = X86::RAX; size = 8;
18464 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18465 Op.getOperand(2), SDValue());
18466 SDValue Ops[] = { cpIn.getValue(0),
18469 DAG.getTargetConstant(size, MVT::i8),
18470 cpIn.getValue(1) };
18471 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18472 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18473 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18477 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18478 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18479 MVT::i32, cpOut.getValue(2));
18480 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18481 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18483 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18484 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18485 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18489 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18490 SelectionDAG &DAG) {
18491 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18492 MVT DstVT = Op.getSimpleValueType();
18494 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18495 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18496 if (DstVT != MVT::f64)
18497 // This conversion needs to be expanded.
18500 SDValue InVec = Op->getOperand(0);
18502 unsigned NumElts = SrcVT.getVectorNumElements();
18503 EVT SVT = SrcVT.getVectorElementType();
18505 // Widen the vector in input in the case of MVT::v2i32.
18506 // Example: from MVT::v2i32 to MVT::v4i32.
18507 SmallVector<SDValue, 16> Elts;
18508 for (unsigned i = 0, e = NumElts; i != e; ++i)
18509 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18510 DAG.getIntPtrConstant(i)));
18512 // Explicitly mark the extra elements as Undef.
18513 SDValue Undef = DAG.getUNDEF(SVT);
18514 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18515 Elts.push_back(Undef);
18517 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18518 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18519 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18520 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18521 DAG.getIntPtrConstant(0));
18524 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18525 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18526 assert((DstVT == MVT::i64 ||
18527 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18528 "Unexpected custom BITCAST");
18529 // i64 <=> MMX conversions are Legal.
18530 if (SrcVT==MVT::i64 && DstVT.isVector())
18532 if (DstVT==MVT::i64 && SrcVT.isVector())
18534 // MMX <=> MMX conversions are Legal.
18535 if (SrcVT.isVector() && DstVT.isVector())
18537 // All other conversions need to be expanded.
18541 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18542 SDNode *Node = Op.getNode();
18544 EVT T = Node->getValueType(0);
18545 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18546 DAG.getConstant(0, T), Node->getOperand(2));
18547 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18548 cast<AtomicSDNode>(Node)->getMemoryVT(),
18549 Node->getOperand(0),
18550 Node->getOperand(1), negOp,
18551 cast<AtomicSDNode>(Node)->getMemOperand(),
18552 cast<AtomicSDNode>(Node)->getOrdering(),
18553 cast<AtomicSDNode>(Node)->getSynchScope());
18556 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18557 SDNode *Node = Op.getNode();
18559 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18561 // Convert seq_cst store -> xchg
18562 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18563 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18564 // (The only way to get a 16-byte store is cmpxchg16b)
18565 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18566 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18567 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18568 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18569 cast<AtomicSDNode>(Node)->getMemoryVT(),
18570 Node->getOperand(0),
18571 Node->getOperand(1), Node->getOperand(2),
18572 cast<AtomicSDNode>(Node)->getMemOperand(),
18573 cast<AtomicSDNode>(Node)->getOrdering(),
18574 cast<AtomicSDNode>(Node)->getSynchScope());
18575 return Swap.getValue(1);
18577 // Other atomic stores have a simple pattern.
18581 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18582 EVT VT = Op.getNode()->getSimpleValueType(0);
18584 // Let legalize expand this if it isn't a legal type yet.
18585 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18588 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18591 bool ExtraOp = false;
18592 switch (Op.getOpcode()) {
18593 default: llvm_unreachable("Invalid code");
18594 case ISD::ADDC: Opc = X86ISD::ADD; break;
18595 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18596 case ISD::SUBC: Opc = X86ISD::SUB; break;
18597 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18601 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18603 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18604 Op.getOperand(1), Op.getOperand(2));
18607 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18608 SelectionDAG &DAG) {
18609 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18611 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18612 // which returns the values as { float, float } (in XMM0) or
18613 // { double, double } (which is returned in XMM0, XMM1).
18615 SDValue Arg = Op.getOperand(0);
18616 EVT ArgVT = Arg.getValueType();
18617 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18619 TargetLowering::ArgListTy Args;
18620 TargetLowering::ArgListEntry Entry;
18624 Entry.isSExt = false;
18625 Entry.isZExt = false;
18626 Args.push_back(Entry);
18628 bool isF64 = ArgVT == MVT::f64;
18629 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18630 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18631 // the results are returned via SRet in memory.
18632 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18634 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18636 Type *RetTy = isF64
18637 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18638 : (Type*)VectorType::get(ArgTy, 4);
18640 TargetLowering::CallLoweringInfo CLI(DAG);
18641 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18642 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18644 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18647 // Returned in xmm0 and xmm1.
18648 return CallResult.first;
18650 // Returned in bits 0:31 and 32:64 xmm0.
18651 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18652 CallResult.first, DAG.getIntPtrConstant(0));
18653 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18654 CallResult.first, DAG.getIntPtrConstant(1));
18655 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18656 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18659 /// LowerOperation - Provide custom lowering hooks for some operations.
18661 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18662 switch (Op.getOpcode()) {
18663 default: llvm_unreachable("Should not custom lower this!");
18664 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18665 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18666 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18667 return LowerCMP_SWAP(Op, Subtarget, DAG);
18668 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18669 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18670 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18671 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18672 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18673 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18674 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18675 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18676 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18677 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18678 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18679 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18680 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18681 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18682 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18683 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18684 case ISD::SHL_PARTS:
18685 case ISD::SRA_PARTS:
18686 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18687 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18688 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18689 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18690 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18691 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18692 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18693 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18694 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18695 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18696 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18698 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18699 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18700 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18701 case ISD::SETCC: return LowerSETCC(Op, DAG);
18702 case ISD::SELECT: return LowerSELECT(Op, DAG);
18703 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18704 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18705 case ISD::VASTART: return LowerVASTART(Op, DAG);
18706 case ISD::VAARG: return LowerVAARG(Op, DAG);
18707 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18708 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18709 case ISD::INTRINSIC_VOID:
18710 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18711 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18712 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18713 case ISD::FRAME_TO_ARGS_OFFSET:
18714 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18715 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18716 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18717 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18718 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18719 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18720 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18721 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18722 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18723 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18724 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18725 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18726 case ISD::UMUL_LOHI:
18727 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18730 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18736 case ISD::UMULO: return LowerXALUO(Op, DAG);
18737 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18738 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18742 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18743 case ISD::ADD: return LowerADD(Op, DAG);
18744 case ISD::SUB: return LowerSUB(Op, DAG);
18745 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18749 /// ReplaceNodeResults - Replace a node with an illegal result type
18750 /// with a new node built out of custom code.
18751 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18752 SmallVectorImpl<SDValue>&Results,
18753 SelectionDAG &DAG) const {
18755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18756 switch (N->getOpcode()) {
18758 llvm_unreachable("Do not know how to custom type legalize this operation!");
18759 case ISD::SIGN_EXTEND_INREG:
18764 // We don't want to expand or promote these.
18771 case ISD::UDIVREM: {
18772 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18773 Results.push_back(V);
18776 case ISD::FP_TO_SINT:
18777 case ISD::FP_TO_UINT: {
18778 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18780 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18783 std::pair<SDValue,SDValue> Vals =
18784 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18785 SDValue FIST = Vals.first, StackSlot = Vals.second;
18786 if (FIST.getNode()) {
18787 EVT VT = N->getValueType(0);
18788 // Return a load from the stack slot.
18789 if (StackSlot.getNode())
18790 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18791 MachinePointerInfo(),
18792 false, false, false, 0));
18794 Results.push_back(FIST);
18798 case ISD::UINT_TO_FP: {
18799 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18800 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18801 N->getValueType(0) != MVT::v2f32)
18803 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18805 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18807 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18808 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18809 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18810 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18811 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18812 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18815 case ISD::FP_ROUND: {
18816 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18818 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18819 Results.push_back(V);
18822 case ISD::INTRINSIC_W_CHAIN: {
18823 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18825 default : llvm_unreachable("Do not know how to custom type "
18826 "legalize this intrinsic operation!");
18827 case Intrinsic::x86_rdtsc:
18828 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18830 case Intrinsic::x86_rdtscp:
18831 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18833 case Intrinsic::x86_rdpmc:
18834 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18837 case ISD::READCYCLECOUNTER: {
18838 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18841 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18842 EVT T = N->getValueType(0);
18843 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18844 bool Regs64bit = T == MVT::i128;
18845 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18846 SDValue cpInL, cpInH;
18847 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18848 DAG.getConstant(0, HalfT));
18849 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18850 DAG.getConstant(1, HalfT));
18851 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18852 Regs64bit ? X86::RAX : X86::EAX,
18854 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18855 Regs64bit ? X86::RDX : X86::EDX,
18856 cpInH, cpInL.getValue(1));
18857 SDValue swapInL, swapInH;
18858 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18859 DAG.getConstant(0, HalfT));
18860 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18861 DAG.getConstant(1, HalfT));
18862 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18863 Regs64bit ? X86::RBX : X86::EBX,
18864 swapInL, cpInH.getValue(1));
18865 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18866 Regs64bit ? X86::RCX : X86::ECX,
18867 swapInH, swapInL.getValue(1));
18868 SDValue Ops[] = { swapInH.getValue(0),
18870 swapInH.getValue(1) };
18871 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18872 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18873 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18874 X86ISD::LCMPXCHG8_DAG;
18875 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18876 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18877 Regs64bit ? X86::RAX : X86::EAX,
18878 HalfT, Result.getValue(1));
18879 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18880 Regs64bit ? X86::RDX : X86::EDX,
18881 HalfT, cpOutL.getValue(2));
18882 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18884 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18885 MVT::i32, cpOutH.getValue(2));
18887 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18888 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18889 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18891 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18892 Results.push_back(Success);
18893 Results.push_back(EFLAGS.getValue(1));
18896 case ISD::ATOMIC_SWAP:
18897 case ISD::ATOMIC_LOAD_ADD:
18898 case ISD::ATOMIC_LOAD_SUB:
18899 case ISD::ATOMIC_LOAD_AND:
18900 case ISD::ATOMIC_LOAD_OR:
18901 case ISD::ATOMIC_LOAD_XOR:
18902 case ISD::ATOMIC_LOAD_NAND:
18903 case ISD::ATOMIC_LOAD_MIN:
18904 case ISD::ATOMIC_LOAD_MAX:
18905 case ISD::ATOMIC_LOAD_UMIN:
18906 case ISD::ATOMIC_LOAD_UMAX:
18907 case ISD::ATOMIC_LOAD: {
18908 // Delegate to generic TypeLegalization. Situations we can really handle
18909 // should have already been dealt with by AtomicExpandPass.cpp.
18912 case ISD::BITCAST: {
18913 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18914 EVT DstVT = N->getValueType(0);
18915 EVT SrcVT = N->getOperand(0)->getValueType(0);
18917 if (SrcVT != MVT::f64 ||
18918 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18921 unsigned NumElts = DstVT.getVectorNumElements();
18922 EVT SVT = DstVT.getVectorElementType();
18923 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18924 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18925 MVT::v2f64, N->getOperand(0));
18926 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18928 if (ExperimentalVectorWideningLegalization) {
18929 // If we are legalizing vectors by widening, we already have the desired
18930 // legal vector type, just return it.
18931 Results.push_back(ToVecInt);
18935 SmallVector<SDValue, 8> Elts;
18936 for (unsigned i = 0, e = NumElts; i != e; ++i)
18937 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18938 ToVecInt, DAG.getIntPtrConstant(i)));
18940 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18945 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18947 default: return nullptr;
18948 case X86ISD::BSF: return "X86ISD::BSF";
18949 case X86ISD::BSR: return "X86ISD::BSR";
18950 case X86ISD::SHLD: return "X86ISD::SHLD";
18951 case X86ISD::SHRD: return "X86ISD::SHRD";
18952 case X86ISD::FAND: return "X86ISD::FAND";
18953 case X86ISD::FANDN: return "X86ISD::FANDN";
18954 case X86ISD::FOR: return "X86ISD::FOR";
18955 case X86ISD::FXOR: return "X86ISD::FXOR";
18956 case X86ISD::FSRL: return "X86ISD::FSRL";
18957 case X86ISD::FILD: return "X86ISD::FILD";
18958 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18959 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18960 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18961 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18962 case X86ISD::FLD: return "X86ISD::FLD";
18963 case X86ISD::FST: return "X86ISD::FST";
18964 case X86ISD::CALL: return "X86ISD::CALL";
18965 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18966 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18967 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18968 case X86ISD::BT: return "X86ISD::BT";
18969 case X86ISD::CMP: return "X86ISD::CMP";
18970 case X86ISD::COMI: return "X86ISD::COMI";
18971 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18972 case X86ISD::CMPM: return "X86ISD::CMPM";
18973 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18974 case X86ISD::SETCC: return "X86ISD::SETCC";
18975 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18976 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18977 case X86ISD::CMOV: return "X86ISD::CMOV";
18978 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18979 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18980 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18981 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18982 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18983 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18984 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18985 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18986 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18987 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18988 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18989 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18990 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18991 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18992 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18993 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18994 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18995 case X86ISD::HADD: return "X86ISD::HADD";
18996 case X86ISD::HSUB: return "X86ISD::HSUB";
18997 case X86ISD::FHADD: return "X86ISD::FHADD";
18998 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18999 case X86ISD::UMAX: return "X86ISD::UMAX";
19000 case X86ISD::UMIN: return "X86ISD::UMIN";
19001 case X86ISD::SMAX: return "X86ISD::SMAX";
19002 case X86ISD::SMIN: return "X86ISD::SMIN";
19003 case X86ISD::FMAX: return "X86ISD::FMAX";
19004 case X86ISD::FMIN: return "X86ISD::FMIN";
19005 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19006 case X86ISD::FMINC: return "X86ISD::FMINC";
19007 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19008 case X86ISD::FRCP: return "X86ISD::FRCP";
19009 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19010 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19011 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19012 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19013 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19014 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19015 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19016 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19017 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19018 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19019 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19020 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19021 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19022 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19023 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19024 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19025 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19026 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19027 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19028 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19029 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19030 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19031 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19032 case X86ISD::VSHL: return "X86ISD::VSHL";
19033 case X86ISD::VSRL: return "X86ISD::VSRL";
19034 case X86ISD::VSRA: return "X86ISD::VSRA";
19035 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19036 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19037 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19038 case X86ISD::CMPP: return "X86ISD::CMPP";
19039 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19040 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19041 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19042 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19043 case X86ISD::ADD: return "X86ISD::ADD";
19044 case X86ISD::SUB: return "X86ISD::SUB";
19045 case X86ISD::ADC: return "X86ISD::ADC";
19046 case X86ISD::SBB: return "X86ISD::SBB";
19047 case X86ISD::SMUL: return "X86ISD::SMUL";
19048 case X86ISD::UMUL: return "X86ISD::UMUL";
19049 case X86ISD::INC: return "X86ISD::INC";
19050 case X86ISD::DEC: return "X86ISD::DEC";
19051 case X86ISD::OR: return "X86ISD::OR";
19052 case X86ISD::XOR: return "X86ISD::XOR";
19053 case X86ISD::AND: return "X86ISD::AND";
19054 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19055 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19056 case X86ISD::PTEST: return "X86ISD::PTEST";
19057 case X86ISD::TESTP: return "X86ISD::TESTP";
19058 case X86ISD::TESTM: return "X86ISD::TESTM";
19059 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19060 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19061 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19062 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19063 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19064 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19065 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19066 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19067 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19068 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19069 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19070 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19071 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19072 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19073 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19074 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19075 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19076 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19077 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19078 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19079 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19080 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19081 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19082 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19083 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19084 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19085 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19086 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19087 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19088 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19089 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19090 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19091 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19092 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19093 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19094 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19095 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19096 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19097 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19098 case X86ISD::SAHF: return "X86ISD::SAHF";
19099 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19100 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19101 case X86ISD::FMADD: return "X86ISD::FMADD";
19102 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19103 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19104 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19105 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19106 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19107 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19108 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19109 case X86ISD::XTEST: return "X86ISD::XTEST";
19113 // isLegalAddressingMode - Return true if the addressing mode represented
19114 // by AM is legal for this target, for a load/store of the specified type.
19115 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19117 // X86 supports extremely general addressing modes.
19118 CodeModel::Model M = getTargetMachine().getCodeModel();
19119 Reloc::Model R = getTargetMachine().getRelocationModel();
19121 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19122 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19127 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19129 // If a reference to this global requires an extra load, we can't fold it.
19130 if (isGlobalStubReference(GVFlags))
19133 // If BaseGV requires a register for the PIC base, we cannot also have a
19134 // BaseReg specified.
19135 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19138 // If lower 4G is not available, then we must use rip-relative addressing.
19139 if ((M != CodeModel::Small || R != Reloc::Static) &&
19140 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19144 switch (AM.Scale) {
19150 // These scales always work.
19155 // These scales are formed with basereg+scalereg. Only accept if there is
19160 default: // Other stuff never works.
19167 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19168 unsigned Bits = Ty->getScalarSizeInBits();
19170 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19171 // particularly cheaper than those without.
19175 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19176 // variable shifts just as cheap as scalar ones.
19177 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19180 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19181 // fully general vector.
19185 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19186 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19188 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19189 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19190 return NumBits1 > NumBits2;
19193 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19194 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19197 if (!isTypeLegal(EVT::getEVT(Ty1)))
19200 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19202 // Assuming the caller doesn't have a zeroext or signext return parameter,
19203 // truncation all the way down to i1 is valid.
19207 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19208 return isInt<32>(Imm);
19211 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19212 // Can also use sub to handle negated immediates.
19213 return isInt<32>(Imm);
19216 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19217 if (!VT1.isInteger() || !VT2.isInteger())
19219 unsigned NumBits1 = VT1.getSizeInBits();
19220 unsigned NumBits2 = VT2.getSizeInBits();
19221 return NumBits1 > NumBits2;
19224 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19225 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19226 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19229 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19230 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19231 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19234 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19235 EVT VT1 = Val.getValueType();
19236 if (isZExtFree(VT1, VT2))
19239 if (Val.getOpcode() != ISD::LOAD)
19242 if (!VT1.isSimple() || !VT1.isInteger() ||
19243 !VT2.isSimple() || !VT2.isInteger())
19246 switch (VT1.getSimpleVT().SimpleTy) {
19251 // X86 has 8, 16, and 32-bit zero-extending loads.
19259 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19260 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19263 VT = VT.getScalarType();
19265 if (!VT.isSimple())
19268 switch (VT.getSimpleVT().SimpleTy) {
19279 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19280 // i16 instructions are longer (0x66 prefix) and potentially slower.
19281 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19284 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19285 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19286 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19287 /// are assumed to be legal.
19289 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19291 if (!VT.isSimple())
19294 MVT SVT = VT.getSimpleVT();
19296 // Very little shuffling can be done for 64-bit vectors right now.
19297 if (VT.getSizeInBits() == 64)
19300 // If this is a single-input shuffle with no 128 bit lane crossings we can
19301 // lower it into pshufb.
19302 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19303 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19304 bool isLegal = true;
19305 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19306 if (M[I] >= (int)SVT.getVectorNumElements() ||
19307 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19316 // FIXME: blends, shifts.
19317 return (SVT.getVectorNumElements() == 2 ||
19318 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19319 isMOVLMask(M, SVT) ||
19320 isMOVHLPSMask(M, SVT) ||
19321 isSHUFPMask(M, SVT) ||
19322 isPSHUFDMask(M, SVT) ||
19323 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19324 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19325 isPALIGNRMask(M, SVT, Subtarget) ||
19326 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19327 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19328 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19329 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19330 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19334 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19336 if (!VT.isSimple())
19339 MVT SVT = VT.getSimpleVT();
19340 unsigned NumElts = SVT.getVectorNumElements();
19341 // FIXME: This collection of masks seems suspect.
19344 if (NumElts == 4 && SVT.is128BitVector()) {
19345 return (isMOVLMask(Mask, SVT) ||
19346 isCommutedMOVLMask(Mask, SVT, true) ||
19347 isSHUFPMask(Mask, SVT) ||
19348 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19353 //===----------------------------------------------------------------------===//
19354 // X86 Scheduler Hooks
19355 //===----------------------------------------------------------------------===//
19357 /// Utility function to emit xbegin specifying the start of an RTM region.
19358 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19359 const TargetInstrInfo *TII) {
19360 DebugLoc DL = MI->getDebugLoc();
19362 const BasicBlock *BB = MBB->getBasicBlock();
19363 MachineFunction::iterator I = MBB;
19366 // For the v = xbegin(), we generate
19377 MachineBasicBlock *thisMBB = MBB;
19378 MachineFunction *MF = MBB->getParent();
19379 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19380 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19381 MF->insert(I, mainMBB);
19382 MF->insert(I, sinkMBB);
19384 // Transfer the remainder of BB and its successor edges to sinkMBB.
19385 sinkMBB->splice(sinkMBB->begin(), MBB,
19386 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19387 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19391 // # fallthrough to mainMBB
19392 // # abortion to sinkMBB
19393 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19394 thisMBB->addSuccessor(mainMBB);
19395 thisMBB->addSuccessor(sinkMBB);
19399 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19400 mainMBB->addSuccessor(sinkMBB);
19403 // EAX is live into the sinkMBB
19404 sinkMBB->addLiveIn(X86::EAX);
19405 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19406 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19409 MI->eraseFromParent();
19413 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19414 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19415 // in the .td file.
19416 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19417 const TargetInstrInfo *TII) {
19419 switch (MI->getOpcode()) {
19420 default: llvm_unreachable("illegal opcode!");
19421 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19422 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19423 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19424 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19425 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19426 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19427 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19428 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19431 DebugLoc dl = MI->getDebugLoc();
19432 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19434 unsigned NumArgs = MI->getNumOperands();
19435 for (unsigned i = 1; i < NumArgs; ++i) {
19436 MachineOperand &Op = MI->getOperand(i);
19437 if (!(Op.isReg() && Op.isImplicit()))
19438 MIB.addOperand(Op);
19440 if (MI->hasOneMemOperand())
19441 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19443 BuildMI(*BB, MI, dl,
19444 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19445 .addReg(X86::XMM0);
19447 MI->eraseFromParent();
19451 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19452 // defs in an instruction pattern
19453 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19454 const TargetInstrInfo *TII) {
19456 switch (MI->getOpcode()) {
19457 default: llvm_unreachable("illegal opcode!");
19458 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19459 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19460 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19461 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19462 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19463 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19464 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19465 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19468 DebugLoc dl = MI->getDebugLoc();
19469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19471 unsigned NumArgs = MI->getNumOperands(); // remove the results
19472 for (unsigned i = 1; i < NumArgs; ++i) {
19473 MachineOperand &Op = MI->getOperand(i);
19474 if (!(Op.isReg() && Op.isImplicit()))
19475 MIB.addOperand(Op);
19477 if (MI->hasOneMemOperand())
19478 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19480 BuildMI(*BB, MI, dl,
19481 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19484 MI->eraseFromParent();
19488 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19489 const TargetInstrInfo *TII,
19490 const X86Subtarget* Subtarget) {
19491 DebugLoc dl = MI->getDebugLoc();
19493 // Address into RAX/EAX, other two args into ECX, EDX.
19494 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19495 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19496 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19497 for (int i = 0; i < X86::AddrNumOperands; ++i)
19498 MIB.addOperand(MI->getOperand(i));
19500 unsigned ValOps = X86::AddrNumOperands;
19501 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19502 .addReg(MI->getOperand(ValOps).getReg());
19503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19504 .addReg(MI->getOperand(ValOps+1).getReg());
19506 // The instruction doesn't actually take any operands though.
19507 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19509 MI->eraseFromParent(); // The pseudo is gone now.
19513 MachineBasicBlock *
19514 X86TargetLowering::EmitVAARG64WithCustomInserter(
19516 MachineBasicBlock *MBB) const {
19517 // Emit va_arg instruction on X86-64.
19519 // Operands to this pseudo-instruction:
19520 // 0 ) Output : destination address (reg)
19521 // 1-5) Input : va_list address (addr, i64mem)
19522 // 6 ) ArgSize : Size (in bytes) of vararg type
19523 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19524 // 8 ) Align : Alignment of type
19525 // 9 ) EFLAGS (implicit-def)
19527 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19528 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19530 unsigned DestReg = MI->getOperand(0).getReg();
19531 MachineOperand &Base = MI->getOperand(1);
19532 MachineOperand &Scale = MI->getOperand(2);
19533 MachineOperand &Index = MI->getOperand(3);
19534 MachineOperand &Disp = MI->getOperand(4);
19535 MachineOperand &Segment = MI->getOperand(5);
19536 unsigned ArgSize = MI->getOperand(6).getImm();
19537 unsigned ArgMode = MI->getOperand(7).getImm();
19538 unsigned Align = MI->getOperand(8).getImm();
19540 // Memory Reference
19541 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19542 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19543 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19545 // Machine Information
19546 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19547 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19548 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19549 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19550 DebugLoc DL = MI->getDebugLoc();
19552 // struct va_list {
19555 // i64 overflow_area (address)
19556 // i64 reg_save_area (address)
19558 // sizeof(va_list) = 24
19559 // alignment(va_list) = 8
19561 unsigned TotalNumIntRegs = 6;
19562 unsigned TotalNumXMMRegs = 8;
19563 bool UseGPOffset = (ArgMode == 1);
19564 bool UseFPOffset = (ArgMode == 2);
19565 unsigned MaxOffset = TotalNumIntRegs * 8 +
19566 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19568 /* Align ArgSize to a multiple of 8 */
19569 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19570 bool NeedsAlign = (Align > 8);
19572 MachineBasicBlock *thisMBB = MBB;
19573 MachineBasicBlock *overflowMBB;
19574 MachineBasicBlock *offsetMBB;
19575 MachineBasicBlock *endMBB;
19577 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19578 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19579 unsigned OffsetReg = 0;
19581 if (!UseGPOffset && !UseFPOffset) {
19582 // If we only pull from the overflow region, we don't create a branch.
19583 // We don't need to alter control flow.
19584 OffsetDestReg = 0; // unused
19585 OverflowDestReg = DestReg;
19587 offsetMBB = nullptr;
19588 overflowMBB = thisMBB;
19591 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19592 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19593 // If not, pull from overflow_area. (branch to overflowMBB)
19598 // offsetMBB overflowMBB
19603 // Registers for the PHI in endMBB
19604 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19605 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19607 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19608 MachineFunction *MF = MBB->getParent();
19609 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19610 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19611 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19613 MachineFunction::iterator MBBIter = MBB;
19616 // Insert the new basic blocks
19617 MF->insert(MBBIter, offsetMBB);
19618 MF->insert(MBBIter, overflowMBB);
19619 MF->insert(MBBIter, endMBB);
19621 // Transfer the remainder of MBB and its successor edges to endMBB.
19622 endMBB->splice(endMBB->begin(), thisMBB,
19623 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19624 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19626 // Make offsetMBB and overflowMBB successors of thisMBB
19627 thisMBB->addSuccessor(offsetMBB);
19628 thisMBB->addSuccessor(overflowMBB);
19630 // endMBB is a successor of both offsetMBB and overflowMBB
19631 offsetMBB->addSuccessor(endMBB);
19632 overflowMBB->addSuccessor(endMBB);
19634 // Load the offset value into a register
19635 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19636 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19640 .addDisp(Disp, UseFPOffset ? 4 : 0)
19641 .addOperand(Segment)
19642 .setMemRefs(MMOBegin, MMOEnd);
19644 // Check if there is enough room left to pull this argument.
19645 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19647 .addImm(MaxOffset + 8 - ArgSizeA8);
19649 // Branch to "overflowMBB" if offset >= max
19650 // Fall through to "offsetMBB" otherwise
19651 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19652 .addMBB(overflowMBB);
19655 // In offsetMBB, emit code to use the reg_save_area.
19657 assert(OffsetReg != 0);
19659 // Read the reg_save_area address.
19660 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19661 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19666 .addOperand(Segment)
19667 .setMemRefs(MMOBegin, MMOEnd);
19669 // Zero-extend the offset
19670 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19671 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19674 .addImm(X86::sub_32bit);
19676 // Add the offset to the reg_save_area to get the final address.
19677 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19678 .addReg(OffsetReg64)
19679 .addReg(RegSaveReg);
19681 // Compute the offset for the next argument
19682 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19683 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19685 .addImm(UseFPOffset ? 16 : 8);
19687 // Store it back into the va_list.
19688 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19692 .addDisp(Disp, UseFPOffset ? 4 : 0)
19693 .addOperand(Segment)
19694 .addReg(NextOffsetReg)
19695 .setMemRefs(MMOBegin, MMOEnd);
19698 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19703 // Emit code to use overflow area
19706 // Load the overflow_area address into a register.
19707 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19708 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19713 .addOperand(Segment)
19714 .setMemRefs(MMOBegin, MMOEnd);
19716 // If we need to align it, do so. Otherwise, just copy the address
19717 // to OverflowDestReg.
19719 // Align the overflow address
19720 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19721 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19723 // aligned_addr = (addr + (align-1)) & ~(align-1)
19724 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19725 .addReg(OverflowAddrReg)
19728 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19730 .addImm(~(uint64_t)(Align-1));
19732 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19733 .addReg(OverflowAddrReg);
19736 // Compute the next overflow address after this argument.
19737 // (the overflow address should be kept 8-byte aligned)
19738 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19739 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19740 .addReg(OverflowDestReg)
19741 .addImm(ArgSizeA8);
19743 // Store the new overflow address.
19744 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19749 .addOperand(Segment)
19750 .addReg(NextAddrReg)
19751 .setMemRefs(MMOBegin, MMOEnd);
19753 // If we branched, emit the PHI to the front of endMBB.
19755 BuildMI(*endMBB, endMBB->begin(), DL,
19756 TII->get(X86::PHI), DestReg)
19757 .addReg(OffsetDestReg).addMBB(offsetMBB)
19758 .addReg(OverflowDestReg).addMBB(overflowMBB);
19761 // Erase the pseudo instruction
19762 MI->eraseFromParent();
19767 MachineBasicBlock *
19768 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19770 MachineBasicBlock *MBB) const {
19771 // Emit code to save XMM registers to the stack. The ABI says that the
19772 // number of registers to save is given in %al, so it's theoretically
19773 // possible to do an indirect jump trick to avoid saving all of them,
19774 // however this code takes a simpler approach and just executes all
19775 // of the stores if %al is non-zero. It's less code, and it's probably
19776 // easier on the hardware branch predictor, and stores aren't all that
19777 // expensive anyway.
19779 // Create the new basic blocks. One block contains all the XMM stores,
19780 // and one block is the final destination regardless of whether any
19781 // stores were performed.
19782 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19783 MachineFunction *F = MBB->getParent();
19784 MachineFunction::iterator MBBIter = MBB;
19786 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19787 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19788 F->insert(MBBIter, XMMSaveMBB);
19789 F->insert(MBBIter, EndMBB);
19791 // Transfer the remainder of MBB and its successor edges to EndMBB.
19792 EndMBB->splice(EndMBB->begin(), MBB,
19793 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19794 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19796 // The original block will now fall through to the XMM save block.
19797 MBB->addSuccessor(XMMSaveMBB);
19798 // The XMMSaveMBB will fall through to the end block.
19799 XMMSaveMBB->addSuccessor(EndMBB);
19801 // Now add the instructions.
19802 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19803 DebugLoc DL = MI->getDebugLoc();
19805 unsigned CountReg = MI->getOperand(0).getReg();
19806 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19807 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19809 if (!Subtarget->isTargetWin64()) {
19810 // If %al is 0, branch around the XMM save block.
19811 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19812 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19813 MBB->addSuccessor(EndMBB);
19816 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19817 // that was just emitted, but clearly shouldn't be "saved".
19818 assert((MI->getNumOperands() <= 3 ||
19819 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19820 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19821 && "Expected last argument to be EFLAGS");
19822 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19823 // In the XMM save block, save all the XMM argument registers.
19824 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19825 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19826 MachineMemOperand *MMO =
19827 F->getMachineMemOperand(
19828 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19829 MachineMemOperand::MOStore,
19830 /*Size=*/16, /*Align=*/16);
19831 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19832 .addFrameIndex(RegSaveFrameIndex)
19833 .addImm(/*Scale=*/1)
19834 .addReg(/*IndexReg=*/0)
19835 .addImm(/*Disp=*/Offset)
19836 .addReg(/*Segment=*/0)
19837 .addReg(MI->getOperand(i).getReg())
19838 .addMemOperand(MMO);
19841 MI->eraseFromParent(); // The pseudo instruction is gone now.
19846 // The EFLAGS operand of SelectItr might be missing a kill marker
19847 // because there were multiple uses of EFLAGS, and ISel didn't know
19848 // which to mark. Figure out whether SelectItr should have had a
19849 // kill marker, and set it if it should. Returns the correct kill
19851 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19852 MachineBasicBlock* BB,
19853 const TargetRegisterInfo* TRI) {
19854 // Scan forward through BB for a use/def of EFLAGS.
19855 MachineBasicBlock::iterator miI(std::next(SelectItr));
19856 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19857 const MachineInstr& mi = *miI;
19858 if (mi.readsRegister(X86::EFLAGS))
19860 if (mi.definesRegister(X86::EFLAGS))
19861 break; // Should have kill-flag - update below.
19864 // If we hit the end of the block, check whether EFLAGS is live into a
19866 if (miI == BB->end()) {
19867 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19868 sEnd = BB->succ_end();
19869 sItr != sEnd; ++sItr) {
19870 MachineBasicBlock* succ = *sItr;
19871 if (succ->isLiveIn(X86::EFLAGS))
19876 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19877 // out. SelectMI should have a kill flag on EFLAGS.
19878 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19882 MachineBasicBlock *
19883 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19884 MachineBasicBlock *BB) const {
19885 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19886 DebugLoc DL = MI->getDebugLoc();
19888 // To "insert" a SELECT_CC instruction, we actually have to insert the
19889 // diamond control-flow pattern. The incoming instruction knows the
19890 // destination vreg to set, the condition code register to branch on, the
19891 // true/false values to select between, and a branch opcode to use.
19892 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19893 MachineFunction::iterator It = BB;
19899 // cmpTY ccX, r1, r2
19901 // fallthrough --> copy0MBB
19902 MachineBasicBlock *thisMBB = BB;
19903 MachineFunction *F = BB->getParent();
19904 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19905 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19906 F->insert(It, copy0MBB);
19907 F->insert(It, sinkMBB);
19909 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19910 // live into the sink and copy blocks.
19911 const TargetRegisterInfo *TRI =
19912 BB->getParent()->getSubtarget().getRegisterInfo();
19913 if (!MI->killsRegister(X86::EFLAGS) &&
19914 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19915 copy0MBB->addLiveIn(X86::EFLAGS);
19916 sinkMBB->addLiveIn(X86::EFLAGS);
19919 // Transfer the remainder of BB and its successor edges to sinkMBB.
19920 sinkMBB->splice(sinkMBB->begin(), BB,
19921 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19922 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19924 // Add the true and fallthrough blocks as its successors.
19925 BB->addSuccessor(copy0MBB);
19926 BB->addSuccessor(sinkMBB);
19928 // Create the conditional branch instruction.
19930 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19931 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19934 // %FalseValue = ...
19935 // # fallthrough to sinkMBB
19936 copy0MBB->addSuccessor(sinkMBB);
19939 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19941 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19942 TII->get(X86::PHI), MI->getOperand(0).getReg())
19943 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19944 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19946 MI->eraseFromParent(); // The pseudo instruction is gone now.
19950 MachineBasicBlock *
19951 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19952 MachineBasicBlock *BB) const {
19953 MachineFunction *MF = BB->getParent();
19954 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19955 DebugLoc DL = MI->getDebugLoc();
19956 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19958 assert(MF->shouldSplitStack());
19960 const bool Is64Bit = Subtarget->is64Bit();
19961 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19963 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19964 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19967 // ... [Till the alloca]
19968 // If stacklet is not large enough, jump to mallocMBB
19971 // Allocate by subtracting from RSP
19972 // Jump to continueMBB
19975 // Allocate by call to runtime
19979 // [rest of original BB]
19982 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19983 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19984 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19986 MachineRegisterInfo &MRI = MF->getRegInfo();
19987 const TargetRegisterClass *AddrRegClass =
19988 getRegClassFor(getPointerTy());
19990 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19991 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19992 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19993 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19994 sizeVReg = MI->getOperand(1).getReg(),
19995 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19997 MachineFunction::iterator MBBIter = BB;
20000 MF->insert(MBBIter, bumpMBB);
20001 MF->insert(MBBIter, mallocMBB);
20002 MF->insert(MBBIter, continueMBB);
20004 continueMBB->splice(continueMBB->begin(), BB,
20005 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20006 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20008 // Add code to the main basic block to check if the stack limit has been hit,
20009 // and if so, jump to mallocMBB otherwise to bumpMBB.
20010 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20011 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20012 .addReg(tmpSPVReg).addReg(sizeVReg);
20013 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20014 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20015 .addReg(SPLimitVReg);
20016 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20018 // bumpMBB simply decreases the stack pointer, since we know the current
20019 // stacklet has enough space.
20020 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20021 .addReg(SPLimitVReg);
20022 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20023 .addReg(SPLimitVReg);
20024 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20026 // Calls into a routine in libgcc to allocate more space from the heap.
20027 const uint32_t *RegMask = MF->getTarget()
20028 .getSubtargetImpl()
20029 ->getRegisterInfo()
20030 ->getCallPreservedMask(CallingConv::C);
20032 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20034 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20035 .addExternalSymbol("__morestack_allocate_stack_space")
20036 .addRegMask(RegMask)
20037 .addReg(X86::RDI, RegState::Implicit)
20038 .addReg(X86::RAX, RegState::ImplicitDefine);
20039 } else if (Is64Bit) {
20040 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20042 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20043 .addExternalSymbol("__morestack_allocate_stack_space")
20044 .addRegMask(RegMask)
20045 .addReg(X86::EDI, RegState::Implicit)
20046 .addReg(X86::EAX, RegState::ImplicitDefine);
20048 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20050 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20051 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20052 .addExternalSymbol("__morestack_allocate_stack_space")
20053 .addRegMask(RegMask)
20054 .addReg(X86::EAX, RegState::ImplicitDefine);
20058 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20061 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20062 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20063 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20065 // Set up the CFG correctly.
20066 BB->addSuccessor(bumpMBB);
20067 BB->addSuccessor(mallocMBB);
20068 mallocMBB->addSuccessor(continueMBB);
20069 bumpMBB->addSuccessor(continueMBB);
20071 // Take care of the PHI nodes.
20072 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20073 MI->getOperand(0).getReg())
20074 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20075 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20077 // Delete the original pseudo instruction.
20078 MI->eraseFromParent();
20081 return continueMBB;
20084 MachineBasicBlock *
20085 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20086 MachineBasicBlock *BB) const {
20087 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20088 DebugLoc DL = MI->getDebugLoc();
20090 assert(!Subtarget->isTargetMacho());
20092 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20093 // non-trivial part is impdef of ESP.
20095 if (Subtarget->isTargetWin64()) {
20096 if (Subtarget->isTargetCygMing()) {
20097 // ___chkstk(Mingw64):
20098 // Clobbers R10, R11, RAX and EFLAGS.
20100 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20101 .addExternalSymbol("___chkstk")
20102 .addReg(X86::RAX, RegState::Implicit)
20103 .addReg(X86::RSP, RegState::Implicit)
20104 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20105 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20106 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20108 // __chkstk(MSVCRT): does not update stack pointer.
20109 // Clobbers R10, R11 and EFLAGS.
20110 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20111 .addExternalSymbol("__chkstk")
20112 .addReg(X86::RAX, RegState::Implicit)
20113 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20114 // RAX has the offset to be subtracted from RSP.
20115 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20120 const char *StackProbeSymbol =
20121 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20123 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20124 .addExternalSymbol(StackProbeSymbol)
20125 .addReg(X86::EAX, RegState::Implicit)
20126 .addReg(X86::ESP, RegState::Implicit)
20127 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20128 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20129 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20132 MI->eraseFromParent(); // The pseudo instruction is gone now.
20136 MachineBasicBlock *
20137 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20138 MachineBasicBlock *BB) const {
20139 // This is pretty easy. We're taking the value that we received from
20140 // our load from the relocation, sticking it in either RDI (x86-64)
20141 // or EAX and doing an indirect call. The return value will then
20142 // be in the normal return register.
20143 MachineFunction *F = BB->getParent();
20144 const X86InstrInfo *TII =
20145 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20146 DebugLoc DL = MI->getDebugLoc();
20148 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20149 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20151 // Get a register mask for the lowered call.
20152 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20153 // proper register mask.
20154 const uint32_t *RegMask = F->getTarget()
20155 .getSubtargetImpl()
20156 ->getRegisterInfo()
20157 ->getCallPreservedMask(CallingConv::C);
20158 if (Subtarget->is64Bit()) {
20159 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20160 TII->get(X86::MOV64rm), X86::RDI)
20162 .addImm(0).addReg(0)
20163 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20164 MI->getOperand(3).getTargetFlags())
20166 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20167 addDirectMem(MIB, X86::RDI);
20168 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20169 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20170 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20171 TII->get(X86::MOV32rm), X86::EAX)
20173 .addImm(0).addReg(0)
20174 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20175 MI->getOperand(3).getTargetFlags())
20177 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20178 addDirectMem(MIB, X86::EAX);
20179 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20181 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20182 TII->get(X86::MOV32rm), X86::EAX)
20183 .addReg(TII->getGlobalBaseReg(F))
20184 .addImm(0).addReg(0)
20185 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20186 MI->getOperand(3).getTargetFlags())
20188 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20189 addDirectMem(MIB, X86::EAX);
20190 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20193 MI->eraseFromParent(); // The pseudo instruction is gone now.
20197 MachineBasicBlock *
20198 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20199 MachineBasicBlock *MBB) const {
20200 DebugLoc DL = MI->getDebugLoc();
20201 MachineFunction *MF = MBB->getParent();
20202 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20203 MachineRegisterInfo &MRI = MF->getRegInfo();
20205 const BasicBlock *BB = MBB->getBasicBlock();
20206 MachineFunction::iterator I = MBB;
20209 // Memory Reference
20210 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20211 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20214 unsigned MemOpndSlot = 0;
20216 unsigned CurOp = 0;
20218 DstReg = MI->getOperand(CurOp++).getReg();
20219 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20220 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20221 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20222 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20224 MemOpndSlot = CurOp;
20226 MVT PVT = getPointerTy();
20227 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20228 "Invalid Pointer Size!");
20230 // For v = setjmp(buf), we generate
20233 // buf[LabelOffset] = restoreMBB
20234 // SjLjSetup restoreMBB
20240 // v = phi(main, restore)
20245 MachineBasicBlock *thisMBB = MBB;
20246 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20247 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20248 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20249 MF->insert(I, mainMBB);
20250 MF->insert(I, sinkMBB);
20251 MF->push_back(restoreMBB);
20253 MachineInstrBuilder MIB;
20255 // Transfer the remainder of BB and its successor edges to sinkMBB.
20256 sinkMBB->splice(sinkMBB->begin(), MBB,
20257 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20258 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20261 unsigned PtrStoreOpc = 0;
20262 unsigned LabelReg = 0;
20263 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20264 Reloc::Model RM = MF->getTarget().getRelocationModel();
20265 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20266 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20268 // Prepare IP either in reg or imm.
20269 if (!UseImmLabel) {
20270 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20271 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20272 LabelReg = MRI.createVirtualRegister(PtrRC);
20273 if (Subtarget->is64Bit()) {
20274 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20278 .addMBB(restoreMBB)
20281 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20282 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20283 .addReg(XII->getGlobalBaseReg(MF))
20286 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20290 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20292 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20293 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20294 if (i == X86::AddrDisp)
20295 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20297 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20300 MIB.addReg(LabelReg);
20302 MIB.addMBB(restoreMBB);
20303 MIB.setMemRefs(MMOBegin, MMOEnd);
20305 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20306 .addMBB(restoreMBB);
20308 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20309 MF->getSubtarget().getRegisterInfo());
20310 MIB.addRegMask(RegInfo->getNoPreservedMask());
20311 thisMBB->addSuccessor(mainMBB);
20312 thisMBB->addSuccessor(restoreMBB);
20316 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20317 mainMBB->addSuccessor(sinkMBB);
20320 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20321 TII->get(X86::PHI), DstReg)
20322 .addReg(mainDstReg).addMBB(mainMBB)
20323 .addReg(restoreDstReg).addMBB(restoreMBB);
20326 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20327 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20328 restoreMBB->addSuccessor(sinkMBB);
20330 MI->eraseFromParent();
20334 MachineBasicBlock *
20335 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20336 MachineBasicBlock *MBB) const {
20337 DebugLoc DL = MI->getDebugLoc();
20338 MachineFunction *MF = MBB->getParent();
20339 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20340 MachineRegisterInfo &MRI = MF->getRegInfo();
20342 // Memory Reference
20343 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20344 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20346 MVT PVT = getPointerTy();
20347 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20348 "Invalid Pointer Size!");
20350 const TargetRegisterClass *RC =
20351 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20352 unsigned Tmp = MRI.createVirtualRegister(RC);
20353 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20354 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20355 MF->getSubtarget().getRegisterInfo());
20356 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20357 unsigned SP = RegInfo->getStackRegister();
20359 MachineInstrBuilder MIB;
20361 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20362 const int64_t SPOffset = 2 * PVT.getStoreSize();
20364 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20365 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20368 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20369 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20370 MIB.addOperand(MI->getOperand(i));
20371 MIB.setMemRefs(MMOBegin, MMOEnd);
20373 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20374 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20375 if (i == X86::AddrDisp)
20376 MIB.addDisp(MI->getOperand(i), LabelOffset);
20378 MIB.addOperand(MI->getOperand(i));
20380 MIB.setMemRefs(MMOBegin, MMOEnd);
20382 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20383 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20384 if (i == X86::AddrDisp)
20385 MIB.addDisp(MI->getOperand(i), SPOffset);
20387 MIB.addOperand(MI->getOperand(i));
20389 MIB.setMemRefs(MMOBegin, MMOEnd);
20391 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20393 MI->eraseFromParent();
20397 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20398 // accumulator loops. Writing back to the accumulator allows the coalescer
20399 // to remove extra copies in the loop.
20400 MachineBasicBlock *
20401 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20402 MachineBasicBlock *MBB) const {
20403 MachineOperand &AddendOp = MI->getOperand(3);
20405 // Bail out early if the addend isn't a register - we can't switch these.
20406 if (!AddendOp.isReg())
20409 MachineFunction &MF = *MBB->getParent();
20410 MachineRegisterInfo &MRI = MF.getRegInfo();
20412 // Check whether the addend is defined by a PHI:
20413 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20414 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20415 if (!AddendDef.isPHI())
20418 // Look for the following pattern:
20420 // %addend = phi [%entry, 0], [%loop, %result]
20422 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20426 // %addend = phi [%entry, 0], [%loop, %result]
20428 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20430 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20431 assert(AddendDef.getOperand(i).isReg());
20432 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20433 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20434 if (&PHISrcInst == MI) {
20435 // Found a matching instruction.
20436 unsigned NewFMAOpc = 0;
20437 switch (MI->getOpcode()) {
20438 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20439 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20440 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20441 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20442 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20443 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20444 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20445 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20446 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20447 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20448 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20449 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20450 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20451 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20452 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20453 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20454 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20455 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20456 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20457 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20458 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20459 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20460 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20461 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20462 default: llvm_unreachable("Unrecognized FMA variant.");
20465 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20466 MachineInstrBuilder MIB =
20467 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20468 .addOperand(MI->getOperand(0))
20469 .addOperand(MI->getOperand(3))
20470 .addOperand(MI->getOperand(2))
20471 .addOperand(MI->getOperand(1));
20472 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20473 MI->eraseFromParent();
20480 MachineBasicBlock *
20481 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20482 MachineBasicBlock *BB) const {
20483 switch (MI->getOpcode()) {
20484 default: llvm_unreachable("Unexpected instr type to insert");
20485 case X86::TAILJMPd64:
20486 case X86::TAILJMPr64:
20487 case X86::TAILJMPm64:
20488 llvm_unreachable("TAILJMP64 would not be touched here.");
20489 case X86::TCRETURNdi64:
20490 case X86::TCRETURNri64:
20491 case X86::TCRETURNmi64:
20493 case X86::WIN_ALLOCA:
20494 return EmitLoweredWinAlloca(MI, BB);
20495 case X86::SEG_ALLOCA_32:
20496 case X86::SEG_ALLOCA_64:
20497 return EmitLoweredSegAlloca(MI, BB);
20498 case X86::TLSCall_32:
20499 case X86::TLSCall_64:
20500 return EmitLoweredTLSCall(MI, BB);
20501 case X86::CMOV_GR8:
20502 case X86::CMOV_FR32:
20503 case X86::CMOV_FR64:
20504 case X86::CMOV_V4F32:
20505 case X86::CMOV_V2F64:
20506 case X86::CMOV_V2I64:
20507 case X86::CMOV_V8F32:
20508 case X86::CMOV_V4F64:
20509 case X86::CMOV_V4I64:
20510 case X86::CMOV_V16F32:
20511 case X86::CMOV_V8F64:
20512 case X86::CMOV_V8I64:
20513 case X86::CMOV_GR16:
20514 case X86::CMOV_GR32:
20515 case X86::CMOV_RFP32:
20516 case X86::CMOV_RFP64:
20517 case X86::CMOV_RFP80:
20518 return EmitLoweredSelect(MI, BB);
20520 case X86::FP32_TO_INT16_IN_MEM:
20521 case X86::FP32_TO_INT32_IN_MEM:
20522 case X86::FP32_TO_INT64_IN_MEM:
20523 case X86::FP64_TO_INT16_IN_MEM:
20524 case X86::FP64_TO_INT32_IN_MEM:
20525 case X86::FP64_TO_INT64_IN_MEM:
20526 case X86::FP80_TO_INT16_IN_MEM:
20527 case X86::FP80_TO_INT32_IN_MEM:
20528 case X86::FP80_TO_INT64_IN_MEM: {
20529 MachineFunction *F = BB->getParent();
20530 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20531 DebugLoc DL = MI->getDebugLoc();
20533 // Change the floating point control register to use "round towards zero"
20534 // mode when truncating to an integer value.
20535 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20536 addFrameReference(BuildMI(*BB, MI, DL,
20537 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20539 // Load the old value of the high byte of the control word...
20541 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20542 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20545 // Set the high part to be round to zero...
20546 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20549 // Reload the modified control word now...
20550 addFrameReference(BuildMI(*BB, MI, DL,
20551 TII->get(X86::FLDCW16m)), CWFrameIdx);
20553 // Restore the memory image of control word to original value
20554 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20557 // Get the X86 opcode to use.
20559 switch (MI->getOpcode()) {
20560 default: llvm_unreachable("illegal opcode!");
20561 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20562 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20563 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20564 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20565 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20566 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20567 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20568 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20569 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20573 MachineOperand &Op = MI->getOperand(0);
20575 AM.BaseType = X86AddressMode::RegBase;
20576 AM.Base.Reg = Op.getReg();
20578 AM.BaseType = X86AddressMode::FrameIndexBase;
20579 AM.Base.FrameIndex = Op.getIndex();
20581 Op = MI->getOperand(1);
20583 AM.Scale = Op.getImm();
20584 Op = MI->getOperand(2);
20586 AM.IndexReg = Op.getImm();
20587 Op = MI->getOperand(3);
20588 if (Op.isGlobal()) {
20589 AM.GV = Op.getGlobal();
20591 AM.Disp = Op.getImm();
20593 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20594 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20596 // Reload the original control word now.
20597 addFrameReference(BuildMI(*BB, MI, DL,
20598 TII->get(X86::FLDCW16m)), CWFrameIdx);
20600 MI->eraseFromParent(); // The pseudo instruction is gone now.
20603 // String/text processing lowering.
20604 case X86::PCMPISTRM128REG:
20605 case X86::VPCMPISTRM128REG:
20606 case X86::PCMPISTRM128MEM:
20607 case X86::VPCMPISTRM128MEM:
20608 case X86::PCMPESTRM128REG:
20609 case X86::VPCMPESTRM128REG:
20610 case X86::PCMPESTRM128MEM:
20611 case X86::VPCMPESTRM128MEM:
20612 assert(Subtarget->hasSSE42() &&
20613 "Target must have SSE4.2 or AVX features enabled");
20614 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20616 // String/text processing lowering.
20617 case X86::PCMPISTRIREG:
20618 case X86::VPCMPISTRIREG:
20619 case X86::PCMPISTRIMEM:
20620 case X86::VPCMPISTRIMEM:
20621 case X86::PCMPESTRIREG:
20622 case X86::VPCMPESTRIREG:
20623 case X86::PCMPESTRIMEM:
20624 case X86::VPCMPESTRIMEM:
20625 assert(Subtarget->hasSSE42() &&
20626 "Target must have SSE4.2 or AVX features enabled");
20627 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20629 // Thread synchronization.
20631 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20636 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20638 case X86::VASTART_SAVE_XMM_REGS:
20639 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20641 case X86::VAARG_64:
20642 return EmitVAARG64WithCustomInserter(MI, BB);
20644 case X86::EH_SjLj_SetJmp32:
20645 case X86::EH_SjLj_SetJmp64:
20646 return emitEHSjLjSetJmp(MI, BB);
20648 case X86::EH_SjLj_LongJmp32:
20649 case X86::EH_SjLj_LongJmp64:
20650 return emitEHSjLjLongJmp(MI, BB);
20652 case TargetOpcode::STACKMAP:
20653 case TargetOpcode::PATCHPOINT:
20654 return emitPatchPoint(MI, BB);
20656 case X86::VFMADDPDr213r:
20657 case X86::VFMADDPSr213r:
20658 case X86::VFMADDSDr213r:
20659 case X86::VFMADDSSr213r:
20660 case X86::VFMSUBPDr213r:
20661 case X86::VFMSUBPSr213r:
20662 case X86::VFMSUBSDr213r:
20663 case X86::VFMSUBSSr213r:
20664 case X86::VFNMADDPDr213r:
20665 case X86::VFNMADDPSr213r:
20666 case X86::VFNMADDSDr213r:
20667 case X86::VFNMADDSSr213r:
20668 case X86::VFNMSUBPDr213r:
20669 case X86::VFNMSUBPSr213r:
20670 case X86::VFNMSUBSDr213r:
20671 case X86::VFNMSUBSSr213r:
20672 case X86::VFMADDPDr213rY:
20673 case X86::VFMADDPSr213rY:
20674 case X86::VFMSUBPDr213rY:
20675 case X86::VFMSUBPSr213rY:
20676 case X86::VFNMADDPDr213rY:
20677 case X86::VFNMADDPSr213rY:
20678 case X86::VFNMSUBPDr213rY:
20679 case X86::VFNMSUBPSr213rY:
20680 return emitFMA3Instr(MI, BB);
20684 //===----------------------------------------------------------------------===//
20685 // X86 Optimization Hooks
20686 //===----------------------------------------------------------------------===//
20688 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20691 const SelectionDAG &DAG,
20692 unsigned Depth) const {
20693 unsigned BitWidth = KnownZero.getBitWidth();
20694 unsigned Opc = Op.getOpcode();
20695 assert((Opc >= ISD::BUILTIN_OP_END ||
20696 Opc == ISD::INTRINSIC_WO_CHAIN ||
20697 Opc == ISD::INTRINSIC_W_CHAIN ||
20698 Opc == ISD::INTRINSIC_VOID) &&
20699 "Should use MaskedValueIsZero if you don't know whether Op"
20700 " is a target node!");
20702 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20716 // These nodes' second result is a boolean.
20717 if (Op.getResNo() == 0)
20720 case X86ISD::SETCC:
20721 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20723 case ISD::INTRINSIC_WO_CHAIN: {
20724 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20725 unsigned NumLoBits = 0;
20728 case Intrinsic::x86_sse_movmsk_ps:
20729 case Intrinsic::x86_avx_movmsk_ps_256:
20730 case Intrinsic::x86_sse2_movmsk_pd:
20731 case Intrinsic::x86_avx_movmsk_pd_256:
20732 case Intrinsic::x86_mmx_pmovmskb:
20733 case Intrinsic::x86_sse2_pmovmskb_128:
20734 case Intrinsic::x86_avx2_pmovmskb: {
20735 // High bits of movmskp{s|d}, pmovmskb are known zero.
20737 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20738 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20739 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20740 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20741 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20742 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20743 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20744 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20746 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20755 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20757 const SelectionDAG &,
20758 unsigned Depth) const {
20759 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20760 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20761 return Op.getValueType().getScalarType().getSizeInBits();
20767 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20768 /// node is a GlobalAddress + offset.
20769 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20770 const GlobalValue* &GA,
20771 int64_t &Offset) const {
20772 if (N->getOpcode() == X86ISD::Wrapper) {
20773 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20774 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20775 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20779 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20782 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20783 /// same as extracting the high 128-bit part of 256-bit vector and then
20784 /// inserting the result into the low part of a new 256-bit vector
20785 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20786 EVT VT = SVOp->getValueType(0);
20787 unsigned NumElems = VT.getVectorNumElements();
20789 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20790 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20791 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20792 SVOp->getMaskElt(j) >= 0)
20798 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20799 /// same as extracting the low 128-bit part of 256-bit vector and then
20800 /// inserting the result into the high part of a new 256-bit vector
20801 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20802 EVT VT = SVOp->getValueType(0);
20803 unsigned NumElems = VT.getVectorNumElements();
20805 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20806 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20807 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20808 SVOp->getMaskElt(j) >= 0)
20814 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20815 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20816 TargetLowering::DAGCombinerInfo &DCI,
20817 const X86Subtarget* Subtarget) {
20819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20820 SDValue V1 = SVOp->getOperand(0);
20821 SDValue V2 = SVOp->getOperand(1);
20822 EVT VT = SVOp->getValueType(0);
20823 unsigned NumElems = VT.getVectorNumElements();
20825 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20826 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20830 // V UNDEF BUILD_VECTOR UNDEF
20832 // CONCAT_VECTOR CONCAT_VECTOR
20835 // RESULT: V + zero extended
20837 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20838 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20839 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20842 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20845 // To match the shuffle mask, the first half of the mask should
20846 // be exactly the first vector, and all the rest a splat with the
20847 // first element of the second one.
20848 for (unsigned i = 0; i != NumElems/2; ++i)
20849 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20850 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20853 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20854 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20855 if (Ld->hasNUsesOfValue(1, 0)) {
20856 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20857 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20859 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20861 Ld->getPointerInfo(),
20862 Ld->getAlignment(),
20863 false/*isVolatile*/, true/*ReadMem*/,
20864 false/*WriteMem*/);
20866 // Make sure the newly-created LOAD is in the same position as Ld in
20867 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20868 // and update uses of Ld's output chain to use the TokenFactor.
20869 if (Ld->hasAnyUseOfValue(1)) {
20870 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20871 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20872 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20873 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20874 SDValue(ResNode.getNode(), 1));
20877 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20881 // Emit a zeroed vector and insert the desired subvector on its
20883 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20884 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20885 return DCI.CombineTo(N, InsV);
20888 //===--------------------------------------------------------------------===//
20889 // Combine some shuffles into subvector extracts and inserts:
20892 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20893 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20894 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20895 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20896 return DCI.CombineTo(N, InsV);
20899 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20900 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20901 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20902 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20903 return DCI.CombineTo(N, InsV);
20909 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20912 /// This is the leaf of the recursive combinine below. When we have found some
20913 /// chain of single-use x86 shuffle instructions and accumulated the combined
20914 /// shuffle mask represented by them, this will try to pattern match that mask
20915 /// into either a single instruction if there is a special purpose instruction
20916 /// for this operation, or into a PSHUFB instruction which is a fully general
20917 /// instruction but should only be used to replace chains over a certain depth.
20918 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20919 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20920 TargetLowering::DAGCombinerInfo &DCI,
20921 const X86Subtarget *Subtarget) {
20922 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20924 // Find the operand that enters the chain. Note that multiple uses are OK
20925 // here, we're not going to remove the operand we find.
20926 SDValue Input = Op.getOperand(0);
20927 while (Input.getOpcode() == ISD::BITCAST)
20928 Input = Input.getOperand(0);
20930 MVT VT = Input.getSimpleValueType();
20931 MVT RootVT = Root.getSimpleValueType();
20934 // Just remove no-op shuffle masks.
20935 if (Mask.size() == 1) {
20936 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20941 // Use the float domain if the operand type is a floating point type.
20942 bool FloatDomain = VT.isFloatingPoint();
20944 // For floating point shuffles, we don't have free copies in the shuffle
20945 // instructions or the ability to load as part of the instruction, so
20946 // canonicalize their shuffles to UNPCK or MOV variants.
20948 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20949 // vectors because it can have a load folded into it that UNPCK cannot. This
20950 // doesn't preclude something switching to the shorter encoding post-RA.
20952 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20953 bool Lo = Mask.equals(0, 0);
20956 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20957 // is no slower than UNPCKLPD but has the option to fold the input operand
20958 // into even an unaligned memory load.
20959 if (Lo && Subtarget->hasSSE3()) {
20960 Shuffle = X86ISD::MOVDDUP;
20961 ShuffleVT = MVT::v2f64;
20963 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20964 // than the UNPCK variants.
20965 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20966 ShuffleVT = MVT::v4f32;
20968 if (Depth == 1 && Root->getOpcode() == Shuffle)
20969 return false; // Nothing to do!
20970 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20971 DCI.AddToWorklist(Op.getNode());
20972 if (Shuffle == X86ISD::MOVDDUP)
20973 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20975 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20976 DCI.AddToWorklist(Op.getNode());
20977 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20981 if (Subtarget->hasSSE3() &&
20982 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20983 bool Lo = Mask.equals(0, 0, 2, 2);
20984 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20985 MVT ShuffleVT = MVT::v4f32;
20986 if (Depth == 1 && Root->getOpcode() == Shuffle)
20987 return false; // Nothing to do!
20988 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20989 DCI.AddToWorklist(Op.getNode());
20990 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20991 DCI.AddToWorklist(Op.getNode());
20992 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20996 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20997 bool Lo = Mask.equals(0, 0, 1, 1);
20998 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20999 MVT ShuffleVT = MVT::v4f32;
21000 if (Depth == 1 && Root->getOpcode() == Shuffle)
21001 return false; // Nothing to do!
21002 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21003 DCI.AddToWorklist(Op.getNode());
21004 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21005 DCI.AddToWorklist(Op.getNode());
21006 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21012 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21013 // variants as none of these have single-instruction variants that are
21014 // superior to the UNPCK formulation.
21015 if (!FloatDomain &&
21016 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21017 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21018 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21019 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21021 bool Lo = Mask[0] == 0;
21022 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21023 if (Depth == 1 && Root->getOpcode() == Shuffle)
21024 return false; // Nothing to do!
21026 switch (Mask.size()) {
21028 ShuffleVT = MVT::v8i16;
21031 ShuffleVT = MVT::v16i8;
21034 llvm_unreachable("Impossible mask size!");
21036 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21037 DCI.AddToWorklist(Op.getNode());
21038 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21039 DCI.AddToWorklist(Op.getNode());
21040 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21045 // Don't try to re-form single instruction chains under any circumstances now
21046 // that we've done encoding canonicalization for them.
21050 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21051 // can replace them with a single PSHUFB instruction profitably. Intel's
21052 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21053 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21054 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21055 SmallVector<SDValue, 16> PSHUFBMask;
21056 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21057 int Ratio = 16 / Mask.size();
21058 for (unsigned i = 0; i < 16; ++i) {
21059 if (Mask[i / Ratio] == SM_SentinelUndef) {
21060 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21063 int M = Mask[i / Ratio] != SM_SentinelZero
21064 ? Ratio * Mask[i / Ratio] + i % Ratio
21066 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21068 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21069 DCI.AddToWorklist(Op.getNode());
21070 SDValue PSHUFBMaskOp =
21071 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21072 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21073 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21074 DCI.AddToWorklist(Op.getNode());
21075 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21080 // Failed to find any combines.
21084 /// \brief Fully generic combining of x86 shuffle instructions.
21086 /// This should be the last combine run over the x86 shuffle instructions. Once
21087 /// they have been fully optimized, this will recursively consider all chains
21088 /// of single-use shuffle instructions, build a generic model of the cumulative
21089 /// shuffle operation, and check for simpler instructions which implement this
21090 /// operation. We use this primarily for two purposes:
21092 /// 1) Collapse generic shuffles to specialized single instructions when
21093 /// equivalent. In most cases, this is just an encoding size win, but
21094 /// sometimes we will collapse multiple generic shuffles into a single
21095 /// special-purpose shuffle.
21096 /// 2) Look for sequences of shuffle instructions with 3 or more total
21097 /// instructions, and replace them with the slightly more expensive SSSE3
21098 /// PSHUFB instruction if available. We do this as the last combining step
21099 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21100 /// a suitable short sequence of other instructions. The PHUFB will either
21101 /// use a register or have to read from memory and so is slightly (but only
21102 /// slightly) more expensive than the other shuffle instructions.
21104 /// Because this is inherently a quadratic operation (for each shuffle in
21105 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21106 /// This should never be an issue in practice as the shuffle lowering doesn't
21107 /// produce sequences of more than 8 instructions.
21109 /// FIXME: We will currently miss some cases where the redundant shuffling
21110 /// would simplify under the threshold for PSHUFB formation because of
21111 /// combine-ordering. To fix this, we should do the redundant instruction
21112 /// combining in this recursive walk.
21113 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21114 ArrayRef<int> RootMask,
21115 int Depth, bool HasPSHUFB,
21117 TargetLowering::DAGCombinerInfo &DCI,
21118 const X86Subtarget *Subtarget) {
21119 // Bound the depth of our recursive combine because this is ultimately
21120 // quadratic in nature.
21124 // Directly rip through bitcasts to find the underlying operand.
21125 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21126 Op = Op.getOperand(0);
21128 MVT VT = Op.getSimpleValueType();
21129 if (!VT.isVector())
21130 return false; // Bail if we hit a non-vector.
21131 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21132 // version should be added.
21133 if (VT.getSizeInBits() != 128)
21136 assert(Root.getSimpleValueType().isVector() &&
21137 "Shuffles operate on vector types!");
21138 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21139 "Can only combine shuffles of the same vector register size.");
21141 if (!isTargetShuffle(Op.getOpcode()))
21143 SmallVector<int, 16> OpMask;
21145 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21146 // We only can combine unary shuffles which we can decode the mask for.
21147 if (!HaveMask || !IsUnary)
21150 assert(VT.getVectorNumElements() == OpMask.size() &&
21151 "Different mask size from vector size!");
21152 assert(((RootMask.size() > OpMask.size() &&
21153 RootMask.size() % OpMask.size() == 0) ||
21154 (OpMask.size() > RootMask.size() &&
21155 OpMask.size() % RootMask.size() == 0) ||
21156 OpMask.size() == RootMask.size()) &&
21157 "The smaller number of elements must divide the larger.");
21158 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21159 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21160 assert(((RootRatio == 1 && OpRatio == 1) ||
21161 (RootRatio == 1) != (OpRatio == 1)) &&
21162 "Must not have a ratio for both incoming and op masks!");
21164 SmallVector<int, 16> Mask;
21165 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21167 // Merge this shuffle operation's mask into our accumulated mask. Note that
21168 // this shuffle's mask will be the first applied to the input, followed by the
21169 // root mask to get us all the way to the root value arrangement. The reason
21170 // for this order is that we are recursing up the operation chain.
21171 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21172 int RootIdx = i / RootRatio;
21173 if (RootMask[RootIdx] < 0) {
21174 // This is a zero or undef lane, we're done.
21175 Mask.push_back(RootMask[RootIdx]);
21179 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21180 int OpIdx = RootMaskedIdx / OpRatio;
21181 if (OpMask[OpIdx] < 0) {
21182 // The incoming lanes are zero or undef, it doesn't matter which ones we
21184 Mask.push_back(OpMask[OpIdx]);
21188 // Ok, we have non-zero lanes, map them through.
21189 Mask.push_back(OpMask[OpIdx] * OpRatio +
21190 RootMaskedIdx % OpRatio);
21193 // See if we can recurse into the operand to combine more things.
21194 switch (Op.getOpcode()) {
21195 case X86ISD::PSHUFB:
21197 case X86ISD::PSHUFD:
21198 case X86ISD::PSHUFHW:
21199 case X86ISD::PSHUFLW:
21200 if (Op.getOperand(0).hasOneUse() &&
21201 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21202 HasPSHUFB, DAG, DCI, Subtarget))
21206 case X86ISD::UNPCKL:
21207 case X86ISD::UNPCKH:
21208 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21209 // We can't check for single use, we have to check that this shuffle is the only user.
21210 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21211 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21212 HasPSHUFB, DAG, DCI, Subtarget))
21217 // Minor canonicalization of the accumulated shuffle mask to make it easier
21218 // to match below. All this does is detect masks with squential pairs of
21219 // elements, and shrink them to the half-width mask. It does this in a loop
21220 // so it will reduce the size of the mask to the minimal width mask which
21221 // performs an equivalent shuffle.
21222 SmallVector<int, 16> WidenedMask;
21223 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21224 Mask = std::move(WidenedMask);
21225 WidenedMask.clear();
21228 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21232 /// \brief Get the PSHUF-style mask from PSHUF node.
21234 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21235 /// PSHUF-style masks that can be reused with such instructions.
21236 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21237 SmallVector<int, 4> Mask;
21239 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21243 switch (N.getOpcode()) {
21244 case X86ISD::PSHUFD:
21246 case X86ISD::PSHUFLW:
21249 case X86ISD::PSHUFHW:
21250 Mask.erase(Mask.begin(), Mask.begin() + 4);
21251 for (int &M : Mask)
21255 llvm_unreachable("No valid shuffle instruction found!");
21259 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21261 /// We walk up the chain and look for a combinable shuffle, skipping over
21262 /// shuffles that we could hoist this shuffle's transformation past without
21263 /// altering anything.
21265 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21267 TargetLowering::DAGCombinerInfo &DCI) {
21268 assert(N.getOpcode() == X86ISD::PSHUFD &&
21269 "Called with something other than an x86 128-bit half shuffle!");
21272 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21273 // of the shuffles in the chain so that we can form a fresh chain to replace
21275 SmallVector<SDValue, 8> Chain;
21276 SDValue V = N.getOperand(0);
21277 for (; V.hasOneUse(); V = V.getOperand(0)) {
21278 switch (V.getOpcode()) {
21280 return SDValue(); // Nothing combined!
21283 // Skip bitcasts as we always know the type for the target specific
21287 case X86ISD::PSHUFD:
21288 // Found another dword shuffle.
21291 case X86ISD::PSHUFLW:
21292 // Check that the low words (being shuffled) are the identity in the
21293 // dword shuffle, and the high words are self-contained.
21294 if (Mask[0] != 0 || Mask[1] != 1 ||
21295 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21298 Chain.push_back(V);
21301 case X86ISD::PSHUFHW:
21302 // Check that the high words (being shuffled) are the identity in the
21303 // dword shuffle, and the low words are self-contained.
21304 if (Mask[2] != 2 || Mask[3] != 3 ||
21305 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21308 Chain.push_back(V);
21311 case X86ISD::UNPCKL:
21312 case X86ISD::UNPCKH:
21313 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21314 // shuffle into a preceding word shuffle.
21315 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21318 // Search for a half-shuffle which we can combine with.
21319 unsigned CombineOp =
21320 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21321 if (V.getOperand(0) != V.getOperand(1) ||
21322 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21324 Chain.push_back(V);
21325 V = V.getOperand(0);
21327 switch (V.getOpcode()) {
21329 return SDValue(); // Nothing to combine.
21331 case X86ISD::PSHUFLW:
21332 case X86ISD::PSHUFHW:
21333 if (V.getOpcode() == CombineOp)
21336 Chain.push_back(V);
21340 V = V.getOperand(0);
21344 } while (V.hasOneUse());
21347 // Break out of the loop if we break out of the switch.
21351 if (!V.hasOneUse())
21352 // We fell out of the loop without finding a viable combining instruction.
21355 // Merge this node's mask and our incoming mask.
21356 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21357 for (int &M : Mask)
21359 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21360 getV4X86ShuffleImm8ForMask(Mask, DAG));
21362 // Rebuild the chain around this new shuffle.
21363 while (!Chain.empty()) {
21364 SDValue W = Chain.pop_back_val();
21366 if (V.getValueType() != W.getOperand(0).getValueType())
21367 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21369 switch (W.getOpcode()) {
21371 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21373 case X86ISD::UNPCKL:
21374 case X86ISD::UNPCKH:
21375 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21378 case X86ISD::PSHUFD:
21379 case X86ISD::PSHUFLW:
21380 case X86ISD::PSHUFHW:
21381 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21385 if (V.getValueType() != N.getValueType())
21386 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21388 // Return the new chain to replace N.
21392 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21394 /// We walk up the chain, skipping shuffles of the other half and looking
21395 /// through shuffles which switch halves trying to find a shuffle of the same
21396 /// pair of dwords.
21397 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21399 TargetLowering::DAGCombinerInfo &DCI) {
21401 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21402 "Called with something other than an x86 128-bit half shuffle!");
21404 unsigned CombineOpcode = N.getOpcode();
21406 // Walk up a single-use chain looking for a combinable shuffle.
21407 SDValue V = N.getOperand(0);
21408 for (; V.hasOneUse(); V = V.getOperand(0)) {
21409 switch (V.getOpcode()) {
21411 return false; // Nothing combined!
21414 // Skip bitcasts as we always know the type for the target specific
21418 case X86ISD::PSHUFLW:
21419 case X86ISD::PSHUFHW:
21420 if (V.getOpcode() == CombineOpcode)
21423 // Other-half shuffles are no-ops.
21426 // Break out of the loop if we break out of the switch.
21430 if (!V.hasOneUse())
21431 // We fell out of the loop without finding a viable combining instruction.
21434 // Combine away the bottom node as its shuffle will be accumulated into
21435 // a preceding shuffle.
21436 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21438 // Record the old value.
21441 // Merge this node's mask and our incoming mask (adjusted to account for all
21442 // the pshufd instructions encountered).
21443 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21444 for (int &M : Mask)
21446 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21447 getV4X86ShuffleImm8ForMask(Mask, DAG));
21449 // Check that the shuffles didn't cancel each other out. If not, we need to
21450 // combine to the new one.
21452 // Replace the combinable shuffle with the combined one, updating all users
21453 // so that we re-evaluate the chain here.
21454 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21459 /// \brief Try to combine x86 target specific shuffles.
21460 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21461 TargetLowering::DAGCombinerInfo &DCI,
21462 const X86Subtarget *Subtarget) {
21464 MVT VT = N.getSimpleValueType();
21465 SmallVector<int, 4> Mask;
21467 switch (N.getOpcode()) {
21468 case X86ISD::PSHUFD:
21469 case X86ISD::PSHUFLW:
21470 case X86ISD::PSHUFHW:
21471 Mask = getPSHUFShuffleMask(N);
21472 assert(Mask.size() == 4);
21478 // Nuke no-op shuffles that show up after combining.
21479 if (isNoopShuffleMask(Mask))
21480 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21482 // Look for simplifications involving one or two shuffle instructions.
21483 SDValue V = N.getOperand(0);
21484 switch (N.getOpcode()) {
21487 case X86ISD::PSHUFLW:
21488 case X86ISD::PSHUFHW:
21489 assert(VT == MVT::v8i16);
21492 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21493 return SDValue(); // We combined away this shuffle, so we're done.
21495 // See if this reduces to a PSHUFD which is no more expensive and can
21496 // combine with more operations. Note that it has to at least flip the
21497 // dwords as otherwise it would have been removed as a no-op.
21498 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21499 int DMask[] = {0, 1, 2, 3};
21500 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21501 DMask[DOffset + 0] = DOffset + 1;
21502 DMask[DOffset + 1] = DOffset + 0;
21503 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21504 DCI.AddToWorklist(V.getNode());
21505 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21506 getV4X86ShuffleImm8ForMask(DMask, DAG));
21507 DCI.AddToWorklist(V.getNode());
21508 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21511 // Look for shuffle patterns which can be implemented as a single unpack.
21512 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21513 // only works when we have a PSHUFD followed by two half-shuffles.
21514 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21515 (V.getOpcode() == X86ISD::PSHUFLW ||
21516 V.getOpcode() == X86ISD::PSHUFHW) &&
21517 V.getOpcode() != N.getOpcode() &&
21519 SDValue D = V.getOperand(0);
21520 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21521 D = D.getOperand(0);
21522 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21523 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21524 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21525 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21526 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21528 for (int i = 0; i < 4; ++i) {
21529 WordMask[i + NOffset] = Mask[i] + NOffset;
21530 WordMask[i + VOffset] = VMask[i] + VOffset;
21532 // Map the word mask through the DWord mask.
21534 for (int i = 0; i < 8; ++i)
21535 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21536 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21537 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21538 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21539 std::begin(UnpackLoMask)) ||
21540 std::equal(std::begin(MappedMask), std::end(MappedMask),
21541 std::begin(UnpackHiMask))) {
21542 // We can replace all three shuffles with an unpack.
21543 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21544 DCI.AddToWorklist(V.getNode());
21545 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21547 DL, MVT::v8i16, V, V);
21554 case X86ISD::PSHUFD:
21555 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21564 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21566 /// We combine this directly on the abstract vector shuffle nodes so it is
21567 /// easier to generically match. We also insert dummy vector shuffle nodes for
21568 /// the operands which explicitly discard the lanes which are unused by this
21569 /// operation to try to flow through the rest of the combiner the fact that
21570 /// they're unused.
21571 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21573 EVT VT = N->getValueType(0);
21575 // We only handle target-independent shuffles.
21576 // FIXME: It would be easy and harmless to use the target shuffle mask
21577 // extraction tool to support more.
21578 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21581 auto *SVN = cast<ShuffleVectorSDNode>(N);
21582 ArrayRef<int> Mask = SVN->getMask();
21583 SDValue V1 = N->getOperand(0);
21584 SDValue V2 = N->getOperand(1);
21586 // We require the first shuffle operand to be the SUB node, and the second to
21587 // be the ADD node.
21588 // FIXME: We should support the commuted patterns.
21589 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21592 // If there are other uses of these operations we can't fold them.
21593 if (!V1->hasOneUse() || !V2->hasOneUse())
21596 // Ensure that both operations have the same operands. Note that we can
21597 // commute the FADD operands.
21598 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21599 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21600 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21603 // We're looking for blends between FADD and FSUB nodes. We insist on these
21604 // nodes being lined up in a specific expected pattern.
21605 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21606 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21607 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21610 // Only specific types are legal at this point, assert so we notice if and
21611 // when these change.
21612 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21613 VT == MVT::v4f64) &&
21614 "Unknown vector type encountered!");
21616 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21619 /// PerformShuffleCombine - Performs several different shuffle combines.
21620 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21621 TargetLowering::DAGCombinerInfo &DCI,
21622 const X86Subtarget *Subtarget) {
21624 SDValue N0 = N->getOperand(0);
21625 SDValue N1 = N->getOperand(1);
21626 EVT VT = N->getValueType(0);
21628 // Don't create instructions with illegal types after legalize types has run.
21629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21630 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21633 // If we have legalized the vector types, look for blends of FADD and FSUB
21634 // nodes that we can fuse into an ADDSUB node.
21635 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21636 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21639 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21640 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21641 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21642 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21644 // During Type Legalization, when promoting illegal vector types,
21645 // the backend might introduce new shuffle dag nodes and bitcasts.
21647 // This code performs the following transformation:
21648 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21649 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21651 // We do this only if both the bitcast and the BINOP dag nodes have
21652 // one use. Also, perform this transformation only if the new binary
21653 // operation is legal. This is to avoid introducing dag nodes that
21654 // potentially need to be further expanded (or custom lowered) into a
21655 // less optimal sequence of dag nodes.
21656 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21657 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21658 N0.getOpcode() == ISD::BITCAST) {
21659 SDValue BC0 = N0.getOperand(0);
21660 EVT SVT = BC0.getValueType();
21661 unsigned Opcode = BC0.getOpcode();
21662 unsigned NumElts = VT.getVectorNumElements();
21664 if (BC0.hasOneUse() && SVT.isVector() &&
21665 SVT.getVectorNumElements() * 2 == NumElts &&
21666 TLI.isOperationLegal(Opcode, VT)) {
21667 bool CanFold = false;
21679 unsigned SVTNumElts = SVT.getVectorNumElements();
21680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21681 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21682 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21683 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21684 CanFold = SVOp->getMaskElt(i) < 0;
21687 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21688 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21689 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21690 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21695 // Only handle 128 wide vector from here on.
21696 if (!VT.is128BitVector())
21699 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21700 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21701 // consecutive, non-overlapping, and in the right order.
21702 SmallVector<SDValue, 16> Elts;
21703 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21704 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21706 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21710 if (isTargetShuffle(N->getOpcode())) {
21712 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21713 if (Shuffle.getNode())
21716 // Try recursively combining arbitrary sequences of x86 shuffle
21717 // instructions into higher-order shuffles. We do this after combining
21718 // specific PSHUF instruction sequences into their minimal form so that we
21719 // can evaluate how many specialized shuffle instructions are involved in
21720 // a particular chain.
21721 SmallVector<int, 1> NonceMask; // Just a placeholder.
21722 NonceMask.push_back(0);
21723 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21724 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21726 return SDValue(); // This routine will use CombineTo to replace N.
21732 /// PerformTruncateCombine - Converts truncate operation to
21733 /// a sequence of vector shuffle operations.
21734 /// It is possible when we truncate 256-bit vector to 128-bit vector
21735 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21736 TargetLowering::DAGCombinerInfo &DCI,
21737 const X86Subtarget *Subtarget) {
21741 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21742 /// specific shuffle of a load can be folded into a single element load.
21743 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21744 /// shuffles have been customed lowered so we need to handle those here.
21745 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21746 TargetLowering::DAGCombinerInfo &DCI) {
21747 if (DCI.isBeforeLegalizeOps())
21750 SDValue InVec = N->getOperand(0);
21751 SDValue EltNo = N->getOperand(1);
21753 if (!isa<ConstantSDNode>(EltNo))
21756 EVT VT = InVec.getValueType();
21758 if (InVec.getOpcode() == ISD::BITCAST) {
21759 // Don't duplicate a load with other uses.
21760 if (!InVec.hasOneUse())
21762 EVT BCVT = InVec.getOperand(0).getValueType();
21763 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21765 InVec = InVec.getOperand(0);
21768 if (!isTargetShuffle(InVec.getOpcode()))
21771 // Don't duplicate a load with other uses.
21772 if (!InVec.hasOneUse())
21775 SmallVector<int, 16> ShuffleMask;
21777 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21781 // Select the input vector, guarding against out of range extract vector.
21782 unsigned NumElems = VT.getVectorNumElements();
21783 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21784 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21785 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21786 : InVec.getOperand(1);
21788 // If inputs to shuffle are the same for both ops, then allow 2 uses
21789 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21791 if (LdNode.getOpcode() == ISD::BITCAST) {
21792 // Don't duplicate a load with other uses.
21793 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21796 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21797 LdNode = LdNode.getOperand(0);
21800 if (!ISD::isNormalLoad(LdNode.getNode()))
21803 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21805 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21808 EVT EltVT = N->getValueType(0);
21809 // If there's a bitcast before the shuffle, check if the load type and
21810 // alignment is valid.
21811 unsigned Align = LN0->getAlignment();
21812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21813 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21814 EltVT.getTypeForEVT(*DAG.getContext()));
21816 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21819 // All checks match so transform back to vector_shuffle so that DAG combiner
21820 // can finish the job
21823 // Create shuffle node taking into account the case that its a unary shuffle
21824 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21825 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21826 InVec.getOperand(0), Shuffle,
21828 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21829 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21833 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21834 /// generation and convert it from being a bunch of shuffles and extracts
21835 /// to a simple store and scalar loads to extract the elements.
21836 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21837 TargetLowering::DAGCombinerInfo &DCI) {
21838 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21839 if (NewOp.getNode())
21842 SDValue InputVector = N->getOperand(0);
21844 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21845 // from mmx to v2i32 has a single usage.
21846 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21847 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21848 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21849 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21850 N->getValueType(0),
21851 InputVector.getNode()->getOperand(0));
21853 // Only operate on vectors of 4 elements, where the alternative shuffling
21854 // gets to be more expensive.
21855 if (InputVector.getValueType() != MVT::v4i32)
21858 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21859 // single use which is a sign-extend or zero-extend, and all elements are
21861 SmallVector<SDNode *, 4> Uses;
21862 unsigned ExtractedElements = 0;
21863 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21864 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21865 if (UI.getUse().getResNo() != InputVector.getResNo())
21868 SDNode *Extract = *UI;
21869 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21872 if (Extract->getValueType(0) != MVT::i32)
21874 if (!Extract->hasOneUse())
21876 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21877 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21879 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21882 // Record which element was extracted.
21883 ExtractedElements |=
21884 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21886 Uses.push_back(Extract);
21889 // If not all the elements were used, this may not be worthwhile.
21890 if (ExtractedElements != 15)
21893 // Ok, we've now decided to do the transformation.
21894 SDLoc dl(InputVector);
21896 // Store the value to a temporary stack slot.
21897 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21898 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21899 MachinePointerInfo(), false, false, 0);
21901 // Replace each use (extract) with a load of the appropriate element.
21902 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21903 UE = Uses.end(); UI != UE; ++UI) {
21904 SDNode *Extract = *UI;
21906 // cOMpute the element's address.
21907 SDValue Idx = Extract->getOperand(1);
21909 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21910 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21911 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21912 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21914 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21915 StackPtr, OffsetVal);
21917 // Load the scalar.
21918 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21919 ScalarAddr, MachinePointerInfo(),
21920 false, false, false, 0);
21922 // Replace the exact with the load.
21923 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21926 // The replacement was made in place; don't return anything.
21930 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21931 static std::pair<unsigned, bool>
21932 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21933 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21934 if (!VT.isVector())
21935 return std::make_pair(0, false);
21937 bool NeedSplit = false;
21938 switch (VT.getSimpleVT().SimpleTy) {
21939 default: return std::make_pair(0, false);
21943 if (!Subtarget->hasAVX2())
21945 if (!Subtarget->hasAVX())
21946 return std::make_pair(0, false);
21951 if (!Subtarget->hasSSE2())
21952 return std::make_pair(0, false);
21955 // SSE2 has only a small subset of the operations.
21956 bool hasUnsigned = Subtarget->hasSSE41() ||
21957 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21958 bool hasSigned = Subtarget->hasSSE41() ||
21959 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21961 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21964 // Check for x CC y ? x : y.
21965 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21966 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21971 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21974 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21977 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21980 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21982 // Check for x CC y ? y : x -- a min/max with reversed arms.
21983 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21984 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21989 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21992 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21995 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21998 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22002 return std::make_pair(Opc, NeedSplit);
22006 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22007 const X86Subtarget *Subtarget) {
22009 SDValue Cond = N->getOperand(0);
22010 SDValue LHS = N->getOperand(1);
22011 SDValue RHS = N->getOperand(2);
22013 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22014 SDValue CondSrc = Cond->getOperand(0);
22015 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22016 Cond = CondSrc->getOperand(0);
22019 MVT VT = N->getSimpleValueType(0);
22020 MVT EltVT = VT.getVectorElementType();
22021 unsigned NumElems = VT.getVectorNumElements();
22022 // There is no blend with immediate in AVX-512.
22023 if (VT.is512BitVector())
22026 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22028 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22031 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22034 // A vselect where all conditions and data are constants can be optimized into
22035 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22036 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22037 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22040 unsigned MaskValue = 0;
22041 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22044 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22045 for (unsigned i = 0; i < NumElems; ++i) {
22046 // Be sure we emit undef where we can.
22047 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22048 ShuffleMask[i] = -1;
22050 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22053 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22056 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22058 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22059 TargetLowering::DAGCombinerInfo &DCI,
22060 const X86Subtarget *Subtarget) {
22062 SDValue Cond = N->getOperand(0);
22063 // Get the LHS/RHS of the select.
22064 SDValue LHS = N->getOperand(1);
22065 SDValue RHS = N->getOperand(2);
22066 EVT VT = LHS.getValueType();
22067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22069 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22070 // instructions match the semantics of the common C idiom x<y?x:y but not
22071 // x<=y?x:y, because of how they handle negative zero (which can be
22072 // ignored in unsafe-math mode).
22073 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22074 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22075 (Subtarget->hasSSE2() ||
22076 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22077 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22079 unsigned Opcode = 0;
22080 // Check for x CC y ? x : y.
22081 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22082 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22086 // Converting this to a min would handle NaNs incorrectly, and swapping
22087 // the operands would cause it to handle comparisons between positive
22088 // and negative zero incorrectly.
22089 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22090 if (!DAG.getTarget().Options.UnsafeFPMath &&
22091 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22093 std::swap(LHS, RHS);
22095 Opcode = X86ISD::FMIN;
22098 // Converting this to a min would handle comparisons between positive
22099 // and negative zero incorrectly.
22100 if (!DAG.getTarget().Options.UnsafeFPMath &&
22101 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22103 Opcode = X86ISD::FMIN;
22106 // Converting this to a min would handle both negative zeros and NaNs
22107 // incorrectly, but we can swap the operands to fix both.
22108 std::swap(LHS, RHS);
22112 Opcode = X86ISD::FMIN;
22116 // Converting this to a max would handle comparisons between positive
22117 // and negative zero incorrectly.
22118 if (!DAG.getTarget().Options.UnsafeFPMath &&
22119 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22121 Opcode = X86ISD::FMAX;
22124 // Converting this to a max would handle NaNs incorrectly, and swapping
22125 // the operands would cause it to handle comparisons between positive
22126 // and negative zero incorrectly.
22127 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22128 if (!DAG.getTarget().Options.UnsafeFPMath &&
22129 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22131 std::swap(LHS, RHS);
22133 Opcode = X86ISD::FMAX;
22136 // Converting this to a max would handle both negative zeros and NaNs
22137 // incorrectly, but we can swap the operands to fix both.
22138 std::swap(LHS, RHS);
22142 Opcode = X86ISD::FMAX;
22145 // Check for x CC y ? y : x -- a min/max with reversed arms.
22146 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22147 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22151 // Converting this to a min would handle comparisons between positive
22152 // and negative zero incorrectly, and swapping the operands would
22153 // cause it to handle NaNs incorrectly.
22154 if (!DAG.getTarget().Options.UnsafeFPMath &&
22155 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22156 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22158 std::swap(LHS, RHS);
22160 Opcode = X86ISD::FMIN;
22163 // Converting this to a min would handle NaNs incorrectly.
22164 if (!DAG.getTarget().Options.UnsafeFPMath &&
22165 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22167 Opcode = X86ISD::FMIN;
22170 // Converting this to a min would handle both negative zeros and NaNs
22171 // incorrectly, but we can swap the operands to fix both.
22172 std::swap(LHS, RHS);
22176 Opcode = X86ISD::FMIN;
22180 // Converting this to a max would handle NaNs incorrectly.
22181 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22183 Opcode = X86ISD::FMAX;
22186 // Converting this to a max would handle comparisons between positive
22187 // and negative zero incorrectly, and swapping the operands would
22188 // cause it to handle NaNs incorrectly.
22189 if (!DAG.getTarget().Options.UnsafeFPMath &&
22190 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22191 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22193 std::swap(LHS, RHS);
22195 Opcode = X86ISD::FMAX;
22198 // Converting this to a max would handle both negative zeros and NaNs
22199 // incorrectly, but we can swap the operands to fix both.
22200 std::swap(LHS, RHS);
22204 Opcode = X86ISD::FMAX;
22210 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22213 EVT CondVT = Cond.getValueType();
22214 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22215 CondVT.getVectorElementType() == MVT::i1) {
22216 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22217 // lowering on KNL. In this case we convert it to
22218 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22219 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22220 // Since SKX these selects have a proper lowering.
22221 EVT OpVT = LHS.getValueType();
22222 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22223 (OpVT.getVectorElementType() == MVT::i8 ||
22224 OpVT.getVectorElementType() == MVT::i16) &&
22225 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22226 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22227 DCI.AddToWorklist(Cond.getNode());
22228 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22231 // If this is a select between two integer constants, try to do some
22233 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22234 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22235 // Don't do this for crazy integer types.
22236 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22237 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22238 // so that TrueC (the true value) is larger than FalseC.
22239 bool NeedsCondInvert = false;
22241 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22242 // Efficiently invertible.
22243 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22244 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22245 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22246 NeedsCondInvert = true;
22247 std::swap(TrueC, FalseC);
22250 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22251 if (FalseC->getAPIntValue() == 0 &&
22252 TrueC->getAPIntValue().isPowerOf2()) {
22253 if (NeedsCondInvert) // Invert the condition if needed.
22254 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22255 DAG.getConstant(1, Cond.getValueType()));
22257 // Zero extend the condition if needed.
22258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22260 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22261 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22262 DAG.getConstant(ShAmt, MVT::i8));
22265 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22266 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22267 if (NeedsCondInvert) // Invert the condition if needed.
22268 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22269 DAG.getConstant(1, Cond.getValueType()));
22271 // Zero extend the condition if needed.
22272 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22273 FalseC->getValueType(0), Cond);
22274 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22275 SDValue(FalseC, 0));
22278 // Optimize cases that will turn into an LEA instruction. This requires
22279 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22280 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22281 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22282 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22284 bool isFastMultiplier = false;
22286 switch ((unsigned char)Diff) {
22288 case 1: // result = add base, cond
22289 case 2: // result = lea base( , cond*2)
22290 case 3: // result = lea base(cond, cond*2)
22291 case 4: // result = lea base( , cond*4)
22292 case 5: // result = lea base(cond, cond*4)
22293 case 8: // result = lea base( , cond*8)
22294 case 9: // result = lea base(cond, cond*8)
22295 isFastMultiplier = true;
22300 if (isFastMultiplier) {
22301 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22302 if (NeedsCondInvert) // Invert the condition if needed.
22303 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22304 DAG.getConstant(1, Cond.getValueType()));
22306 // Zero extend the condition if needed.
22307 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22309 // Scale the condition by the difference.
22311 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22312 DAG.getConstant(Diff, Cond.getValueType()));
22314 // Add the base if non-zero.
22315 if (FalseC->getAPIntValue() != 0)
22316 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22317 SDValue(FalseC, 0));
22324 // Canonicalize max and min:
22325 // (x > y) ? x : y -> (x >= y) ? x : y
22326 // (x < y) ? x : y -> (x <= y) ? x : y
22327 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22328 // the need for an extra compare
22329 // against zero. e.g.
22330 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22332 // testl %edi, %edi
22334 // cmovgl %edi, %eax
22338 // cmovsl %eax, %edi
22339 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22340 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22341 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22342 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22347 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22348 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22349 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22350 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22355 // Early exit check
22356 if (!TLI.isTypeLegal(VT))
22359 // Match VSELECTs into subs with unsigned saturation.
22360 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22361 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22362 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22363 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22364 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22366 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22367 // left side invert the predicate to simplify logic below.
22369 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22371 CC = ISD::getSetCCInverse(CC, true);
22372 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22376 if (Other.getNode() && Other->getNumOperands() == 2 &&
22377 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22378 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22379 SDValue CondRHS = Cond->getOperand(1);
22381 // Look for a general sub with unsigned saturation first.
22382 // x >= y ? x-y : 0 --> subus x, y
22383 // x > y ? x-y : 0 --> subus x, y
22384 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22385 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22386 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22388 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22389 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22390 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22391 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22392 // If the RHS is a constant we have to reverse the const
22393 // canonicalization.
22394 // x > C-1 ? x+-C : 0 --> subus x, C
22395 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22396 CondRHSConst->getAPIntValue() ==
22397 (-OpRHSConst->getAPIntValue() - 1))
22398 return DAG.getNode(
22399 X86ISD::SUBUS, DL, VT, OpLHS,
22400 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22402 // Another special case: If C was a sign bit, the sub has been
22403 // canonicalized into a xor.
22404 // FIXME: Would it be better to use computeKnownBits to determine
22405 // whether it's safe to decanonicalize the xor?
22406 // x s< 0 ? x^C : 0 --> subus x, C
22407 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22408 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22409 OpRHSConst->getAPIntValue().isSignBit())
22410 // Note that we have to rebuild the RHS constant here to ensure we
22411 // don't rely on particular values of undef lanes.
22412 return DAG.getNode(
22413 X86ISD::SUBUS, DL, VT, OpLHS,
22414 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22419 // Try to match a min/max vector operation.
22420 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22421 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22422 unsigned Opc = ret.first;
22423 bool NeedSplit = ret.second;
22425 if (Opc && NeedSplit) {
22426 unsigned NumElems = VT.getVectorNumElements();
22427 // Extract the LHS vectors
22428 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22429 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22431 // Extract the RHS vectors
22432 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22433 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22435 // Create min/max for each subvector
22436 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22437 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22439 // Merge the result
22440 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22442 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22445 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22446 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22447 // Check if SETCC has already been promoted
22448 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22449 // Check that condition value type matches vselect operand type
22452 assert(Cond.getValueType().isVector() &&
22453 "vector select expects a vector selector!");
22455 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22456 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22458 if (!TValIsAllOnes && !FValIsAllZeros) {
22459 // Try invert the condition if true value is not all 1s and false value
22461 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22462 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22464 if (TValIsAllZeros || FValIsAllOnes) {
22465 SDValue CC = Cond.getOperand(2);
22466 ISD::CondCode NewCC =
22467 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22468 Cond.getOperand(0).getValueType().isInteger());
22469 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22470 std::swap(LHS, RHS);
22471 TValIsAllOnes = FValIsAllOnes;
22472 FValIsAllZeros = TValIsAllZeros;
22476 if (TValIsAllOnes || FValIsAllZeros) {
22479 if (TValIsAllOnes && FValIsAllZeros)
22481 else if (TValIsAllOnes)
22482 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22483 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22484 else if (FValIsAllZeros)
22485 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22486 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22488 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22492 // Try to fold this VSELECT into a MOVSS/MOVSD
22493 if (N->getOpcode() == ISD::VSELECT &&
22494 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22495 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22496 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22497 bool CanFold = false;
22498 unsigned NumElems = Cond.getNumOperands();
22502 if (isZero(Cond.getOperand(0))) {
22505 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22506 // fold (vselect <0,-1> -> (movsd A, B)
22507 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22508 CanFold = isAllOnes(Cond.getOperand(i));
22509 } else if (isAllOnes(Cond.getOperand(0))) {
22513 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22514 // fold (vselect <-1,0> -> (movsd B, A)
22515 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22516 CanFold = isZero(Cond.getOperand(i));
22520 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22521 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22522 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22525 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22526 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22527 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22528 // (v2i64 (bitcast B)))))
22530 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22531 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22532 // (v2f64 (bitcast B)))))
22534 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22535 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22536 // (v2i64 (bitcast A)))))
22538 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22539 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22540 // (v2f64 (bitcast A)))))
22542 CanFold = (isZero(Cond.getOperand(0)) &&
22543 isZero(Cond.getOperand(1)) &&
22544 isAllOnes(Cond.getOperand(2)) &&
22545 isAllOnes(Cond.getOperand(3)));
22547 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22548 isAllOnes(Cond.getOperand(1)) &&
22549 isZero(Cond.getOperand(2)) &&
22550 isZero(Cond.getOperand(3))) {
22552 std::swap(LHS, RHS);
22556 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22557 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22558 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22559 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22561 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22567 // If we know that this node is legal then we know that it is going to be
22568 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22569 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22570 // to simplify previous instructions.
22571 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22572 !DCI.isBeforeLegalize() &&
22573 // We explicitly check against v8i16 and v16i16 because, although
22574 // they're marked as Custom, they might only be legal when Cond is a
22575 // build_vector of constants. This will be taken care in a later
22577 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22578 VT != MVT::v8i16)) {
22579 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22581 // Don't optimize vector selects that map to mask-registers.
22585 // Check all uses of that condition operand to check whether it will be
22586 // consumed by non-BLEND instructions, which may depend on all bits are set
22588 for (SDNode::use_iterator I = Cond->use_begin(),
22589 E = Cond->use_end(); I != E; ++I)
22590 if (I->getOpcode() != ISD::VSELECT)
22591 // TODO: Add other opcodes eventually lowered into BLEND.
22594 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22595 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22597 APInt KnownZero, KnownOne;
22598 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22599 DCI.isBeforeLegalizeOps());
22600 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22601 (TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22603 // Don't optimize vector of constants. Those are handled by
22604 // the generic code and all the bits must be properly set for
22605 // the generic optimizer.
22606 !ISD::isBuildVectorOfConstantSDNodes(TLO.New.getNode())))
22607 DCI.CommitTargetLoweringOpt(TLO);
22610 // We should generate an X86ISD::BLENDI from a vselect if its argument
22611 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22612 // constants. This specific pattern gets generated when we split a
22613 // selector for a 512 bit vector in a machine without AVX512 (but with
22614 // 256-bit vectors), during legalization:
22616 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22618 // Iff we find this pattern and the build_vectors are built from
22619 // constants, we translate the vselect into a shuffle_vector that we
22620 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22621 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22622 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22623 if (Shuffle.getNode())
22630 // Check whether a boolean test is testing a boolean value generated by
22631 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22634 // Simplify the following patterns:
22635 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22636 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22637 // to (Op EFLAGS Cond)
22639 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22640 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22641 // to (Op EFLAGS !Cond)
22643 // where Op could be BRCOND or CMOV.
22645 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22646 // Quit if not CMP and SUB with its value result used.
22647 if (Cmp.getOpcode() != X86ISD::CMP &&
22648 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22651 // Quit if not used as a boolean value.
22652 if (CC != X86::COND_E && CC != X86::COND_NE)
22655 // Check CMP operands. One of them should be 0 or 1 and the other should be
22656 // an SetCC or extended from it.
22657 SDValue Op1 = Cmp.getOperand(0);
22658 SDValue Op2 = Cmp.getOperand(1);
22661 const ConstantSDNode* C = nullptr;
22662 bool needOppositeCond = (CC == X86::COND_E);
22663 bool checkAgainstTrue = false; // Is it a comparison against 1?
22665 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22667 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22669 else // Quit if all operands are not constants.
22672 if (C->getZExtValue() == 1) {
22673 needOppositeCond = !needOppositeCond;
22674 checkAgainstTrue = true;
22675 } else if (C->getZExtValue() != 0)
22676 // Quit if the constant is neither 0 or 1.
22679 bool truncatedToBoolWithAnd = false;
22680 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22681 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22682 SetCC.getOpcode() == ISD::TRUNCATE ||
22683 SetCC.getOpcode() == ISD::AND) {
22684 if (SetCC.getOpcode() == ISD::AND) {
22686 ConstantSDNode *CS;
22687 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22688 CS->getZExtValue() == 1)
22690 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22691 CS->getZExtValue() == 1)
22695 SetCC = SetCC.getOperand(OpIdx);
22696 truncatedToBoolWithAnd = true;
22698 SetCC = SetCC.getOperand(0);
22701 switch (SetCC.getOpcode()) {
22702 case X86ISD::SETCC_CARRY:
22703 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22704 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22705 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22706 // truncated to i1 using 'and'.
22707 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22709 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22710 "Invalid use of SETCC_CARRY!");
22712 case X86ISD::SETCC:
22713 // Set the condition code or opposite one if necessary.
22714 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22715 if (needOppositeCond)
22716 CC = X86::GetOppositeBranchCondition(CC);
22717 return SetCC.getOperand(1);
22718 case X86ISD::CMOV: {
22719 // Check whether false/true value has canonical one, i.e. 0 or 1.
22720 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22721 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22722 // Quit if true value is not a constant.
22725 // Quit if false value is not a constant.
22727 SDValue Op = SetCC.getOperand(0);
22728 // Skip 'zext' or 'trunc' node.
22729 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22730 Op.getOpcode() == ISD::TRUNCATE)
22731 Op = Op.getOperand(0);
22732 // A special case for rdrand/rdseed, where 0 is set if false cond is
22734 if ((Op.getOpcode() != X86ISD::RDRAND &&
22735 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22738 // Quit if false value is not the constant 0 or 1.
22739 bool FValIsFalse = true;
22740 if (FVal && FVal->getZExtValue() != 0) {
22741 if (FVal->getZExtValue() != 1)
22743 // If FVal is 1, opposite cond is needed.
22744 needOppositeCond = !needOppositeCond;
22745 FValIsFalse = false;
22747 // Quit if TVal is not the constant opposite of FVal.
22748 if (FValIsFalse && TVal->getZExtValue() != 1)
22750 if (!FValIsFalse && TVal->getZExtValue() != 0)
22752 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22753 if (needOppositeCond)
22754 CC = X86::GetOppositeBranchCondition(CC);
22755 return SetCC.getOperand(3);
22762 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22763 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22764 TargetLowering::DAGCombinerInfo &DCI,
22765 const X86Subtarget *Subtarget) {
22768 // If the flag operand isn't dead, don't touch this CMOV.
22769 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22772 SDValue FalseOp = N->getOperand(0);
22773 SDValue TrueOp = N->getOperand(1);
22774 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22775 SDValue Cond = N->getOperand(3);
22777 if (CC == X86::COND_E || CC == X86::COND_NE) {
22778 switch (Cond.getOpcode()) {
22782 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22783 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22784 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22790 Flags = checkBoolTestSetCCCombine(Cond, CC);
22791 if (Flags.getNode() &&
22792 // Extra check as FCMOV only supports a subset of X86 cond.
22793 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22794 SDValue Ops[] = { FalseOp, TrueOp,
22795 DAG.getConstant(CC, MVT::i8), Flags };
22796 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22799 // If this is a select between two integer constants, try to do some
22800 // optimizations. Note that the operands are ordered the opposite of SELECT
22802 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22803 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22804 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22805 // larger than FalseC (the false value).
22806 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22807 CC = X86::GetOppositeBranchCondition(CC);
22808 std::swap(TrueC, FalseC);
22809 std::swap(TrueOp, FalseOp);
22812 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22813 // This is efficient for any integer data type (including i8/i16) and
22815 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22816 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22817 DAG.getConstant(CC, MVT::i8), Cond);
22819 // Zero extend the condition if needed.
22820 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22822 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22823 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22824 DAG.getConstant(ShAmt, MVT::i8));
22825 if (N->getNumValues() == 2) // Dead flag value?
22826 return DCI.CombineTo(N, Cond, SDValue());
22830 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22831 // for any integer data type, including i8/i16.
22832 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22833 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22834 DAG.getConstant(CC, MVT::i8), Cond);
22836 // Zero extend the condition if needed.
22837 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22838 FalseC->getValueType(0), Cond);
22839 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22840 SDValue(FalseC, 0));
22842 if (N->getNumValues() == 2) // Dead flag value?
22843 return DCI.CombineTo(N, Cond, SDValue());
22847 // Optimize cases that will turn into an LEA instruction. This requires
22848 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22849 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22850 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22851 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22853 bool isFastMultiplier = false;
22855 switch ((unsigned char)Diff) {
22857 case 1: // result = add base, cond
22858 case 2: // result = lea base( , cond*2)
22859 case 3: // result = lea base(cond, cond*2)
22860 case 4: // result = lea base( , cond*4)
22861 case 5: // result = lea base(cond, cond*4)
22862 case 8: // result = lea base( , cond*8)
22863 case 9: // result = lea base(cond, cond*8)
22864 isFastMultiplier = true;
22869 if (isFastMultiplier) {
22870 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22871 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22872 DAG.getConstant(CC, MVT::i8), Cond);
22873 // Zero extend the condition if needed.
22874 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22876 // Scale the condition by the difference.
22878 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22879 DAG.getConstant(Diff, Cond.getValueType()));
22881 // Add the base if non-zero.
22882 if (FalseC->getAPIntValue() != 0)
22883 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22884 SDValue(FalseC, 0));
22885 if (N->getNumValues() == 2) // Dead flag value?
22886 return DCI.CombineTo(N, Cond, SDValue());
22893 // Handle these cases:
22894 // (select (x != c), e, c) -> select (x != c), e, x),
22895 // (select (x == c), c, e) -> select (x == c), x, e)
22896 // where the c is an integer constant, and the "select" is the combination
22897 // of CMOV and CMP.
22899 // The rationale for this change is that the conditional-move from a constant
22900 // needs two instructions, however, conditional-move from a register needs
22901 // only one instruction.
22903 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22904 // some instruction-combining opportunities. This opt needs to be
22905 // postponed as late as possible.
22907 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22908 // the DCI.xxxx conditions are provided to postpone the optimization as
22909 // late as possible.
22911 ConstantSDNode *CmpAgainst = nullptr;
22912 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22913 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22914 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22916 if (CC == X86::COND_NE &&
22917 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22918 CC = X86::GetOppositeBranchCondition(CC);
22919 std::swap(TrueOp, FalseOp);
22922 if (CC == X86::COND_E &&
22923 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22924 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22925 DAG.getConstant(CC, MVT::i8), Cond };
22926 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22934 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22935 const X86Subtarget *Subtarget) {
22936 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22938 default: return SDValue();
22939 // SSE/AVX/AVX2 blend intrinsics.
22940 case Intrinsic::x86_avx2_pblendvb:
22941 case Intrinsic::x86_avx2_pblendw:
22942 case Intrinsic::x86_avx2_pblendd_128:
22943 case Intrinsic::x86_avx2_pblendd_256:
22944 // Don't try to simplify this intrinsic if we don't have AVX2.
22945 if (!Subtarget->hasAVX2())
22948 case Intrinsic::x86_avx_blend_pd_256:
22949 case Intrinsic::x86_avx_blend_ps_256:
22950 case Intrinsic::x86_avx_blendv_pd_256:
22951 case Intrinsic::x86_avx_blendv_ps_256:
22952 // Don't try to simplify this intrinsic if we don't have AVX.
22953 if (!Subtarget->hasAVX())
22956 case Intrinsic::x86_sse41_pblendw:
22957 case Intrinsic::x86_sse41_blendpd:
22958 case Intrinsic::x86_sse41_blendps:
22959 case Intrinsic::x86_sse41_blendvps:
22960 case Intrinsic::x86_sse41_blendvpd:
22961 case Intrinsic::x86_sse41_pblendvb: {
22962 SDValue Op0 = N->getOperand(1);
22963 SDValue Op1 = N->getOperand(2);
22964 SDValue Mask = N->getOperand(3);
22966 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22967 if (!Subtarget->hasSSE41())
22970 // fold (blend A, A, Mask) -> A
22973 // fold (blend A, B, allZeros) -> A
22974 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22976 // fold (blend A, B, allOnes) -> B
22977 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22980 // Simplify the case where the mask is a constant i32 value.
22981 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22982 if (C->isNullValue())
22984 if (C->isAllOnesValue())
22991 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22992 case Intrinsic::x86_sse2_psrai_w:
22993 case Intrinsic::x86_sse2_psrai_d:
22994 case Intrinsic::x86_avx2_psrai_w:
22995 case Intrinsic::x86_avx2_psrai_d:
22996 case Intrinsic::x86_sse2_psra_w:
22997 case Intrinsic::x86_sse2_psra_d:
22998 case Intrinsic::x86_avx2_psra_w:
22999 case Intrinsic::x86_avx2_psra_d: {
23000 SDValue Op0 = N->getOperand(1);
23001 SDValue Op1 = N->getOperand(2);
23002 EVT VT = Op0.getValueType();
23003 assert(VT.isVector() && "Expected a vector type!");
23005 if (isa<BuildVectorSDNode>(Op1))
23006 Op1 = Op1.getOperand(0);
23008 if (!isa<ConstantSDNode>(Op1))
23011 EVT SVT = VT.getVectorElementType();
23012 unsigned SVTBits = SVT.getSizeInBits();
23014 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23015 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23016 uint64_t ShAmt = C.getZExtValue();
23018 // Don't try to convert this shift into a ISD::SRA if the shift
23019 // count is bigger than or equal to the element size.
23020 if (ShAmt >= SVTBits)
23023 // Trivial case: if the shift count is zero, then fold this
23024 // into the first operand.
23028 // Replace this packed shift intrinsic with a target independent
23030 SDValue Splat = DAG.getConstant(C, VT);
23031 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23036 /// PerformMulCombine - Optimize a single multiply with constant into two
23037 /// in order to implement it with two cheaper instructions, e.g.
23038 /// LEA + SHL, LEA + LEA.
23039 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23040 TargetLowering::DAGCombinerInfo &DCI) {
23041 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23044 EVT VT = N->getValueType(0);
23045 if (VT != MVT::i64)
23048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23051 uint64_t MulAmt = C->getZExtValue();
23052 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23055 uint64_t MulAmt1 = 0;
23056 uint64_t MulAmt2 = 0;
23057 if ((MulAmt % 9) == 0) {
23059 MulAmt2 = MulAmt / 9;
23060 } else if ((MulAmt % 5) == 0) {
23062 MulAmt2 = MulAmt / 5;
23063 } else if ((MulAmt % 3) == 0) {
23065 MulAmt2 = MulAmt / 3;
23068 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23071 if (isPowerOf2_64(MulAmt2) &&
23072 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23073 // If second multiplifer is pow2, issue it first. We want the multiply by
23074 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23076 std::swap(MulAmt1, MulAmt2);
23079 if (isPowerOf2_64(MulAmt1))
23080 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23081 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23083 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23084 DAG.getConstant(MulAmt1, VT));
23086 if (isPowerOf2_64(MulAmt2))
23087 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23088 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23090 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23091 DAG.getConstant(MulAmt2, VT));
23093 // Do not add new nodes to DAG combiner worklist.
23094 DCI.CombineTo(N, NewMul, false);
23099 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23100 SDValue N0 = N->getOperand(0);
23101 SDValue N1 = N->getOperand(1);
23102 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23103 EVT VT = N0.getValueType();
23105 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23106 // since the result of setcc_c is all zero's or all ones.
23107 if (VT.isInteger() && !VT.isVector() &&
23108 N1C && N0.getOpcode() == ISD::AND &&
23109 N0.getOperand(1).getOpcode() == ISD::Constant) {
23110 SDValue N00 = N0.getOperand(0);
23111 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23112 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23113 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23114 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23115 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23116 APInt ShAmt = N1C->getAPIntValue();
23117 Mask = Mask.shl(ShAmt);
23119 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23120 N00, DAG.getConstant(Mask, VT));
23124 // Hardware support for vector shifts is sparse which makes us scalarize the
23125 // vector operations in many cases. Also, on sandybridge ADD is faster than
23127 // (shl V, 1) -> add V,V
23128 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23129 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23130 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23131 // We shift all of the values by one. In many cases we do not have
23132 // hardware support for this operation. This is better expressed as an ADD
23134 if (N1SplatC->getZExtValue() == 1)
23135 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23141 /// \brief Returns a vector of 0s if the node in input is a vector logical
23142 /// shift by a constant amount which is known to be bigger than or equal
23143 /// to the vector element size in bits.
23144 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23145 const X86Subtarget *Subtarget) {
23146 EVT VT = N->getValueType(0);
23148 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23149 (!Subtarget->hasInt256() ||
23150 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23153 SDValue Amt = N->getOperand(1);
23155 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23156 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23157 APInt ShiftAmt = AmtSplat->getAPIntValue();
23158 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23160 // SSE2/AVX2 logical shifts always return a vector of 0s
23161 // if the shift amount is bigger than or equal to
23162 // the element size. The constant shift amount will be
23163 // encoded as a 8-bit immediate.
23164 if (ShiftAmt.trunc(8).uge(MaxAmount))
23165 return getZeroVector(VT, Subtarget, DAG, DL);
23171 /// PerformShiftCombine - Combine shifts.
23172 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23173 TargetLowering::DAGCombinerInfo &DCI,
23174 const X86Subtarget *Subtarget) {
23175 if (N->getOpcode() == ISD::SHL) {
23176 SDValue V = PerformSHLCombine(N, DAG);
23177 if (V.getNode()) return V;
23180 if (N->getOpcode() != ISD::SRA) {
23181 // Try to fold this logical shift into a zero vector.
23182 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23183 if (V.getNode()) return V;
23189 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23190 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23191 // and friends. Likewise for OR -> CMPNEQSS.
23192 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23193 TargetLowering::DAGCombinerInfo &DCI,
23194 const X86Subtarget *Subtarget) {
23197 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23198 // we're requiring SSE2 for both.
23199 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23200 SDValue N0 = N->getOperand(0);
23201 SDValue N1 = N->getOperand(1);
23202 SDValue CMP0 = N0->getOperand(1);
23203 SDValue CMP1 = N1->getOperand(1);
23206 // The SETCCs should both refer to the same CMP.
23207 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23210 SDValue CMP00 = CMP0->getOperand(0);
23211 SDValue CMP01 = CMP0->getOperand(1);
23212 EVT VT = CMP00.getValueType();
23214 if (VT == MVT::f32 || VT == MVT::f64) {
23215 bool ExpectingFlags = false;
23216 // Check for any users that want flags:
23217 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23218 !ExpectingFlags && UI != UE; ++UI)
23219 switch (UI->getOpcode()) {
23224 ExpectingFlags = true;
23226 case ISD::CopyToReg:
23227 case ISD::SIGN_EXTEND:
23228 case ISD::ZERO_EXTEND:
23229 case ISD::ANY_EXTEND:
23233 if (!ExpectingFlags) {
23234 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23235 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23237 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23238 X86::CondCode tmp = cc0;
23243 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23244 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23245 // FIXME: need symbolic constants for these magic numbers.
23246 // See X86ATTInstPrinter.cpp:printSSECC().
23247 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23248 if (Subtarget->hasAVX512()) {
23249 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23250 CMP01, DAG.getConstant(x86cc, MVT::i8));
23251 if (N->getValueType(0) != MVT::i1)
23252 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23256 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23257 CMP00.getValueType(), CMP00, CMP01,
23258 DAG.getConstant(x86cc, MVT::i8));
23260 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23261 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23263 if (is64BitFP && !Subtarget->is64Bit()) {
23264 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23265 // 64-bit integer, since that's not a legal type. Since
23266 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23267 // bits, but can do this little dance to extract the lowest 32 bits
23268 // and work with those going forward.
23269 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23271 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23273 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23274 Vector32, DAG.getIntPtrConstant(0));
23278 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23279 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23280 DAG.getConstant(1, IntVT));
23281 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23282 return OneBitOfTruth;
23290 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23291 /// so it can be folded inside ANDNP.
23292 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23293 EVT VT = N->getValueType(0);
23295 // Match direct AllOnes for 128 and 256-bit vectors
23296 if (ISD::isBuildVectorAllOnes(N))
23299 // Look through a bit convert.
23300 if (N->getOpcode() == ISD::BITCAST)
23301 N = N->getOperand(0).getNode();
23303 // Sometimes the operand may come from a insert_subvector building a 256-bit
23305 if (VT.is256BitVector() &&
23306 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23307 SDValue V1 = N->getOperand(0);
23308 SDValue V2 = N->getOperand(1);
23310 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23311 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23312 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23313 ISD::isBuildVectorAllOnes(V2.getNode()))
23320 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23321 // register. In most cases we actually compare or select YMM-sized registers
23322 // and mixing the two types creates horrible code. This method optimizes
23323 // some of the transition sequences.
23324 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23325 TargetLowering::DAGCombinerInfo &DCI,
23326 const X86Subtarget *Subtarget) {
23327 EVT VT = N->getValueType(0);
23328 if (!VT.is256BitVector())
23331 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23332 N->getOpcode() == ISD::ZERO_EXTEND ||
23333 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23335 SDValue Narrow = N->getOperand(0);
23336 EVT NarrowVT = Narrow->getValueType(0);
23337 if (!NarrowVT.is128BitVector())
23340 if (Narrow->getOpcode() != ISD::XOR &&
23341 Narrow->getOpcode() != ISD::AND &&
23342 Narrow->getOpcode() != ISD::OR)
23345 SDValue N0 = Narrow->getOperand(0);
23346 SDValue N1 = Narrow->getOperand(1);
23349 // The Left side has to be a trunc.
23350 if (N0.getOpcode() != ISD::TRUNCATE)
23353 // The type of the truncated inputs.
23354 EVT WideVT = N0->getOperand(0)->getValueType(0);
23358 // The right side has to be a 'trunc' or a constant vector.
23359 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23360 ConstantSDNode *RHSConstSplat = nullptr;
23361 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23362 RHSConstSplat = RHSBV->getConstantSplatNode();
23363 if (!RHSTrunc && !RHSConstSplat)
23366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23368 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23371 // Set N0 and N1 to hold the inputs to the new wide operation.
23372 N0 = N0->getOperand(0);
23373 if (RHSConstSplat) {
23374 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23375 SDValue(RHSConstSplat, 0));
23376 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23377 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23378 } else if (RHSTrunc) {
23379 N1 = N1->getOperand(0);
23382 // Generate the wide operation.
23383 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23384 unsigned Opcode = N->getOpcode();
23386 case ISD::ANY_EXTEND:
23388 case ISD::ZERO_EXTEND: {
23389 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23390 APInt Mask = APInt::getAllOnesValue(InBits);
23391 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23392 return DAG.getNode(ISD::AND, DL, VT,
23393 Op, DAG.getConstant(Mask, VT));
23395 case ISD::SIGN_EXTEND:
23396 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23397 Op, DAG.getValueType(NarrowVT));
23399 llvm_unreachable("Unexpected opcode");
23403 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23404 TargetLowering::DAGCombinerInfo &DCI,
23405 const X86Subtarget *Subtarget) {
23406 EVT VT = N->getValueType(0);
23407 if (DCI.isBeforeLegalizeOps())
23410 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23414 // Create BEXTR instructions
23415 // BEXTR is ((X >> imm) & (2**size-1))
23416 if (VT == MVT::i32 || VT == MVT::i64) {
23417 SDValue N0 = N->getOperand(0);
23418 SDValue N1 = N->getOperand(1);
23421 // Check for BEXTR.
23422 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23423 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23424 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23425 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23426 if (MaskNode && ShiftNode) {
23427 uint64_t Mask = MaskNode->getZExtValue();
23428 uint64_t Shift = ShiftNode->getZExtValue();
23429 if (isMask_64(Mask)) {
23430 uint64_t MaskSize = CountPopulation_64(Mask);
23431 if (Shift + MaskSize <= VT.getSizeInBits())
23432 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23433 DAG.getConstant(Shift | (MaskSize << 8), VT));
23441 // Want to form ANDNP nodes:
23442 // 1) In the hopes of then easily combining them with OR and AND nodes
23443 // to form PBLEND/PSIGN.
23444 // 2) To match ANDN packed intrinsics
23445 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23448 SDValue N0 = N->getOperand(0);
23449 SDValue N1 = N->getOperand(1);
23452 // Check LHS for vnot
23453 if (N0.getOpcode() == ISD::XOR &&
23454 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23455 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23456 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23458 // Check RHS for vnot
23459 if (N1.getOpcode() == ISD::XOR &&
23460 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23461 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23462 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23467 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23468 TargetLowering::DAGCombinerInfo &DCI,
23469 const X86Subtarget *Subtarget) {
23470 if (DCI.isBeforeLegalizeOps())
23473 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23477 SDValue N0 = N->getOperand(0);
23478 SDValue N1 = N->getOperand(1);
23479 EVT VT = N->getValueType(0);
23481 // look for psign/blend
23482 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23483 if (!Subtarget->hasSSSE3() ||
23484 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23487 // Canonicalize pandn to RHS
23488 if (N0.getOpcode() == X86ISD::ANDNP)
23490 // or (and (m, y), (pandn m, x))
23491 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23492 SDValue Mask = N1.getOperand(0);
23493 SDValue X = N1.getOperand(1);
23495 if (N0.getOperand(0) == Mask)
23496 Y = N0.getOperand(1);
23497 if (N0.getOperand(1) == Mask)
23498 Y = N0.getOperand(0);
23500 // Check to see if the mask appeared in both the AND and ANDNP and
23504 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23505 // Look through mask bitcast.
23506 if (Mask.getOpcode() == ISD::BITCAST)
23507 Mask = Mask.getOperand(0);
23508 if (X.getOpcode() == ISD::BITCAST)
23509 X = X.getOperand(0);
23510 if (Y.getOpcode() == ISD::BITCAST)
23511 Y = Y.getOperand(0);
23513 EVT MaskVT = Mask.getValueType();
23515 // Validate that the Mask operand is a vector sra node.
23516 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23517 // there is no psrai.b
23518 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23519 unsigned SraAmt = ~0;
23520 if (Mask.getOpcode() == ISD::SRA) {
23521 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23522 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23523 SraAmt = AmtConst->getZExtValue();
23524 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23525 SDValue SraC = Mask.getOperand(1);
23526 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23528 if ((SraAmt + 1) != EltBits)
23533 // Now we know we at least have a plendvb with the mask val. See if
23534 // we can form a psignb/w/d.
23535 // psign = x.type == y.type == mask.type && y = sub(0, x);
23536 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23537 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23538 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23539 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23540 "Unsupported VT for PSIGN");
23541 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23542 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23544 // PBLENDVB only available on SSE 4.1
23545 if (!Subtarget->hasSSE41())
23548 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23550 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23551 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23552 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23553 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23554 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23558 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23561 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23562 MachineFunction &MF = DAG.getMachineFunction();
23563 bool OptForSize = MF.getFunction()->getAttributes().
23564 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23566 // SHLD/SHRD instructions have lower register pressure, but on some
23567 // platforms they have higher latency than the equivalent
23568 // series of shifts/or that would otherwise be generated.
23569 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23570 // have higher latencies and we are not optimizing for size.
23571 if (!OptForSize && Subtarget->isSHLDSlow())
23574 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23576 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23578 if (!N0.hasOneUse() || !N1.hasOneUse())
23581 SDValue ShAmt0 = N0.getOperand(1);
23582 if (ShAmt0.getValueType() != MVT::i8)
23584 SDValue ShAmt1 = N1.getOperand(1);
23585 if (ShAmt1.getValueType() != MVT::i8)
23587 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23588 ShAmt0 = ShAmt0.getOperand(0);
23589 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23590 ShAmt1 = ShAmt1.getOperand(0);
23593 unsigned Opc = X86ISD::SHLD;
23594 SDValue Op0 = N0.getOperand(0);
23595 SDValue Op1 = N1.getOperand(0);
23596 if (ShAmt0.getOpcode() == ISD::SUB) {
23597 Opc = X86ISD::SHRD;
23598 std::swap(Op0, Op1);
23599 std::swap(ShAmt0, ShAmt1);
23602 unsigned Bits = VT.getSizeInBits();
23603 if (ShAmt1.getOpcode() == ISD::SUB) {
23604 SDValue Sum = ShAmt1.getOperand(0);
23605 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23606 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23607 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23608 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23609 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23610 return DAG.getNode(Opc, DL, VT,
23612 DAG.getNode(ISD::TRUNCATE, DL,
23615 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23616 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23618 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23619 return DAG.getNode(Opc, DL, VT,
23620 N0.getOperand(0), N1.getOperand(0),
23621 DAG.getNode(ISD::TRUNCATE, DL,
23628 // Generate NEG and CMOV for integer abs.
23629 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23630 EVT VT = N->getValueType(0);
23632 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23633 // 8-bit integer abs to NEG and CMOV.
23634 if (VT.isInteger() && VT.getSizeInBits() == 8)
23637 SDValue N0 = N->getOperand(0);
23638 SDValue N1 = N->getOperand(1);
23641 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23642 // and change it to SUB and CMOV.
23643 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23644 N0.getOpcode() == ISD::ADD &&
23645 N0.getOperand(1) == N1 &&
23646 N1.getOpcode() == ISD::SRA &&
23647 N1.getOperand(0) == N0.getOperand(0))
23648 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23649 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23650 // Generate SUB & CMOV.
23651 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23652 DAG.getConstant(0, VT), N0.getOperand(0));
23654 SDValue Ops[] = { N0.getOperand(0), Neg,
23655 DAG.getConstant(X86::COND_GE, MVT::i8),
23656 SDValue(Neg.getNode(), 1) };
23657 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23662 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23663 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23664 TargetLowering::DAGCombinerInfo &DCI,
23665 const X86Subtarget *Subtarget) {
23666 if (DCI.isBeforeLegalizeOps())
23669 if (Subtarget->hasCMov()) {
23670 SDValue RV = performIntegerAbsCombine(N, DAG);
23678 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23679 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23680 TargetLowering::DAGCombinerInfo &DCI,
23681 const X86Subtarget *Subtarget) {
23682 LoadSDNode *Ld = cast<LoadSDNode>(N);
23683 EVT RegVT = Ld->getValueType(0);
23684 EVT MemVT = Ld->getMemoryVT();
23686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23688 // On Sandybridge unaligned 256bit loads are inefficient.
23689 ISD::LoadExtType Ext = Ld->getExtensionType();
23690 unsigned Alignment = Ld->getAlignment();
23691 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23692 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23693 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23694 unsigned NumElems = RegVT.getVectorNumElements();
23698 SDValue Ptr = Ld->getBasePtr();
23699 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23701 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23703 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23704 Ld->getPointerInfo(), Ld->isVolatile(),
23705 Ld->isNonTemporal(), Ld->isInvariant(),
23707 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23708 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23709 Ld->getPointerInfo(), Ld->isVolatile(),
23710 Ld->isNonTemporal(), Ld->isInvariant(),
23711 std::min(16U, Alignment));
23712 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23714 Load2.getValue(1));
23716 SDValue NewVec = DAG.getUNDEF(RegVT);
23717 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23718 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23719 return DCI.CombineTo(N, NewVec, TF, true);
23725 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23726 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23727 const X86Subtarget *Subtarget) {
23728 StoreSDNode *St = cast<StoreSDNode>(N);
23729 EVT VT = St->getValue().getValueType();
23730 EVT StVT = St->getMemoryVT();
23732 SDValue StoredVal = St->getOperand(1);
23733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23735 // If we are saving a concatenation of two XMM registers, perform two stores.
23736 // On Sandy Bridge, 256-bit memory operations are executed by two
23737 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23738 // memory operation.
23739 unsigned Alignment = St->getAlignment();
23740 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23741 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23742 StVT == VT && !IsAligned) {
23743 unsigned NumElems = VT.getVectorNumElements();
23747 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23748 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23750 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23751 SDValue Ptr0 = St->getBasePtr();
23752 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23754 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23755 St->getPointerInfo(), St->isVolatile(),
23756 St->isNonTemporal(), Alignment);
23757 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23758 St->getPointerInfo(), St->isVolatile(),
23759 St->isNonTemporal(),
23760 std::min(16U, Alignment));
23761 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23764 // Optimize trunc store (of multiple scalars) to shuffle and store.
23765 // First, pack all of the elements in one place. Next, store to memory
23766 // in fewer chunks.
23767 if (St->isTruncatingStore() && VT.isVector()) {
23768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23769 unsigned NumElems = VT.getVectorNumElements();
23770 assert(StVT != VT && "Cannot truncate to the same type");
23771 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23772 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23774 // From, To sizes and ElemCount must be pow of two
23775 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23776 // We are going to use the original vector elt for storing.
23777 // Accumulated smaller vector elements must be a multiple of the store size.
23778 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23780 unsigned SizeRatio = FromSz / ToSz;
23782 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23784 // Create a type on which we perform the shuffle
23785 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23786 StVT.getScalarType(), NumElems*SizeRatio);
23788 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23790 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23791 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23792 for (unsigned i = 0; i != NumElems; ++i)
23793 ShuffleVec[i] = i * SizeRatio;
23795 // Can't shuffle using an illegal type.
23796 if (!TLI.isTypeLegal(WideVecVT))
23799 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23800 DAG.getUNDEF(WideVecVT),
23802 // At this point all of the data is stored at the bottom of the
23803 // register. We now need to save it to mem.
23805 // Find the largest store unit
23806 MVT StoreType = MVT::i8;
23807 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23808 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23809 MVT Tp = (MVT::SimpleValueType)tp;
23810 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23814 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23815 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23816 (64 <= NumElems * ToSz))
23817 StoreType = MVT::f64;
23819 // Bitcast the original vector into a vector of store-size units
23820 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23821 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23822 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23823 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23824 SmallVector<SDValue, 8> Chains;
23825 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23826 TLI.getPointerTy());
23827 SDValue Ptr = St->getBasePtr();
23829 // Perform one or more big stores into memory.
23830 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23831 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23832 StoreType, ShuffWide,
23833 DAG.getIntPtrConstant(i));
23834 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23835 St->getPointerInfo(), St->isVolatile(),
23836 St->isNonTemporal(), St->getAlignment());
23837 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23838 Chains.push_back(Ch);
23841 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23844 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23845 // the FP state in cases where an emms may be missing.
23846 // A preferable solution to the general problem is to figure out the right
23847 // places to insert EMMS. This qualifies as a quick hack.
23849 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23850 if (VT.getSizeInBits() != 64)
23853 const Function *F = DAG.getMachineFunction().getFunction();
23854 bool NoImplicitFloatOps = F->getAttributes().
23855 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23856 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23857 && Subtarget->hasSSE2();
23858 if ((VT.isVector() ||
23859 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23860 isa<LoadSDNode>(St->getValue()) &&
23861 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23862 St->getChain().hasOneUse() && !St->isVolatile()) {
23863 SDNode* LdVal = St->getValue().getNode();
23864 LoadSDNode *Ld = nullptr;
23865 int TokenFactorIndex = -1;
23866 SmallVector<SDValue, 8> Ops;
23867 SDNode* ChainVal = St->getChain().getNode();
23868 // Must be a store of a load. We currently handle two cases: the load
23869 // is a direct child, and it's under an intervening TokenFactor. It is
23870 // possible to dig deeper under nested TokenFactors.
23871 if (ChainVal == LdVal)
23872 Ld = cast<LoadSDNode>(St->getChain());
23873 else if (St->getValue().hasOneUse() &&
23874 ChainVal->getOpcode() == ISD::TokenFactor) {
23875 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23876 if (ChainVal->getOperand(i).getNode() == LdVal) {
23877 TokenFactorIndex = i;
23878 Ld = cast<LoadSDNode>(St->getValue());
23880 Ops.push_back(ChainVal->getOperand(i));
23884 if (!Ld || !ISD::isNormalLoad(Ld))
23887 // If this is not the MMX case, i.e. we are just turning i64 load/store
23888 // into f64 load/store, avoid the transformation if there are multiple
23889 // uses of the loaded value.
23890 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23895 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23896 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23898 if (Subtarget->is64Bit() || F64IsLegal) {
23899 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23900 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23901 Ld->getPointerInfo(), Ld->isVolatile(),
23902 Ld->isNonTemporal(), Ld->isInvariant(),
23903 Ld->getAlignment());
23904 SDValue NewChain = NewLd.getValue(1);
23905 if (TokenFactorIndex != -1) {
23906 Ops.push_back(NewChain);
23907 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23909 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23910 St->getPointerInfo(),
23911 St->isVolatile(), St->isNonTemporal(),
23912 St->getAlignment());
23915 // Otherwise, lower to two pairs of 32-bit loads / stores.
23916 SDValue LoAddr = Ld->getBasePtr();
23917 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23918 DAG.getConstant(4, MVT::i32));
23920 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23921 Ld->getPointerInfo(),
23922 Ld->isVolatile(), Ld->isNonTemporal(),
23923 Ld->isInvariant(), Ld->getAlignment());
23924 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23925 Ld->getPointerInfo().getWithOffset(4),
23926 Ld->isVolatile(), Ld->isNonTemporal(),
23928 MinAlign(Ld->getAlignment(), 4));
23930 SDValue NewChain = LoLd.getValue(1);
23931 if (TokenFactorIndex != -1) {
23932 Ops.push_back(LoLd);
23933 Ops.push_back(HiLd);
23934 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23937 LoAddr = St->getBasePtr();
23938 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23939 DAG.getConstant(4, MVT::i32));
23941 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23942 St->getPointerInfo(),
23943 St->isVolatile(), St->isNonTemporal(),
23944 St->getAlignment());
23945 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23946 St->getPointerInfo().getWithOffset(4),
23948 St->isNonTemporal(),
23949 MinAlign(St->getAlignment(), 4));
23950 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23955 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23956 /// and return the operands for the horizontal operation in LHS and RHS. A
23957 /// horizontal operation performs the binary operation on successive elements
23958 /// of its first operand, then on successive elements of its second operand,
23959 /// returning the resulting values in a vector. For example, if
23960 /// A = < float a0, float a1, float a2, float a3 >
23962 /// B = < float b0, float b1, float b2, float b3 >
23963 /// then the result of doing a horizontal operation on A and B is
23964 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23965 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23966 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23967 /// set to A, RHS to B, and the routine returns 'true'.
23968 /// Note that the binary operation should have the property that if one of the
23969 /// operands is UNDEF then the result is UNDEF.
23970 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23971 // Look for the following pattern: if
23972 // A = < float a0, float a1, float a2, float a3 >
23973 // B = < float b0, float b1, float b2, float b3 >
23975 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23976 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23977 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23978 // which is A horizontal-op B.
23980 // At least one of the operands should be a vector shuffle.
23981 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23982 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23985 MVT VT = LHS.getSimpleValueType();
23987 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23988 "Unsupported vector type for horizontal add/sub");
23990 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23991 // operate independently on 128-bit lanes.
23992 unsigned NumElts = VT.getVectorNumElements();
23993 unsigned NumLanes = VT.getSizeInBits()/128;
23994 unsigned NumLaneElts = NumElts / NumLanes;
23995 assert((NumLaneElts % 2 == 0) &&
23996 "Vector type should have an even number of elements in each lane");
23997 unsigned HalfLaneElts = NumLaneElts/2;
23999 // View LHS in the form
24000 // LHS = VECTOR_SHUFFLE A, B, LMask
24001 // If LHS is not a shuffle then pretend it is the shuffle
24002 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24003 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24006 SmallVector<int, 16> LMask(NumElts);
24007 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24008 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24009 A = LHS.getOperand(0);
24010 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24011 B = LHS.getOperand(1);
24012 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24013 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24015 if (LHS.getOpcode() != ISD::UNDEF)
24017 for (unsigned i = 0; i != NumElts; ++i)
24021 // Likewise, view RHS in the form
24022 // RHS = VECTOR_SHUFFLE C, D, RMask
24024 SmallVector<int, 16> RMask(NumElts);
24025 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24026 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24027 C = RHS.getOperand(0);
24028 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24029 D = RHS.getOperand(1);
24030 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24031 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24033 if (RHS.getOpcode() != ISD::UNDEF)
24035 for (unsigned i = 0; i != NumElts; ++i)
24039 // Check that the shuffles are both shuffling the same vectors.
24040 if (!(A == C && B == D) && !(A == D && B == C))
24043 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24044 if (!A.getNode() && !B.getNode())
24047 // If A and B occur in reverse order in RHS, then "swap" them (which means
24048 // rewriting the mask).
24050 CommuteVectorShuffleMask(RMask, NumElts);
24052 // At this point LHS and RHS are equivalent to
24053 // LHS = VECTOR_SHUFFLE A, B, LMask
24054 // RHS = VECTOR_SHUFFLE A, B, RMask
24055 // Check that the masks correspond to performing a horizontal operation.
24056 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24057 for (unsigned i = 0; i != NumLaneElts; ++i) {
24058 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24060 // Ignore any UNDEF components.
24061 if (LIdx < 0 || RIdx < 0 ||
24062 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24063 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24066 // Check that successive elements are being operated on. If not, this is
24067 // not a horizontal operation.
24068 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24069 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24070 if (!(LIdx == Index && RIdx == Index + 1) &&
24071 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24076 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24077 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24081 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24082 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24083 const X86Subtarget *Subtarget) {
24084 EVT VT = N->getValueType(0);
24085 SDValue LHS = N->getOperand(0);
24086 SDValue RHS = N->getOperand(1);
24088 // Try to synthesize horizontal adds from adds of shuffles.
24089 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24090 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24091 isHorizontalBinOp(LHS, RHS, true))
24092 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24096 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24097 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24098 const X86Subtarget *Subtarget) {
24099 EVT VT = N->getValueType(0);
24100 SDValue LHS = N->getOperand(0);
24101 SDValue RHS = N->getOperand(1);
24103 // Try to synthesize horizontal subs from subs of shuffles.
24104 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24105 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24106 isHorizontalBinOp(LHS, RHS, false))
24107 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24111 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24112 /// X86ISD::FXOR nodes.
24113 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24114 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24115 // F[X]OR(0.0, x) -> x
24116 // F[X]OR(x, 0.0) -> x
24117 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24118 if (C->getValueAPF().isPosZero())
24119 return N->getOperand(1);
24120 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24121 if (C->getValueAPF().isPosZero())
24122 return N->getOperand(0);
24126 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24127 /// X86ISD::FMAX nodes.
24128 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24129 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24131 // Only perform optimizations if UnsafeMath is used.
24132 if (!DAG.getTarget().Options.UnsafeFPMath)
24135 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24136 // into FMINC and FMAXC, which are Commutative operations.
24137 unsigned NewOp = 0;
24138 switch (N->getOpcode()) {
24139 default: llvm_unreachable("unknown opcode");
24140 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24141 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24144 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24145 N->getOperand(0), N->getOperand(1));
24148 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24149 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24150 // FAND(0.0, x) -> 0.0
24151 // FAND(x, 0.0) -> 0.0
24152 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24153 if (C->getValueAPF().isPosZero())
24154 return N->getOperand(0);
24155 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24156 if (C->getValueAPF().isPosZero())
24157 return N->getOperand(1);
24161 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24162 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24163 // FANDN(x, 0.0) -> 0.0
24164 // FANDN(0.0, x) -> x
24165 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24166 if (C->getValueAPF().isPosZero())
24167 return N->getOperand(1);
24168 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24169 if (C->getValueAPF().isPosZero())
24170 return N->getOperand(1);
24174 static SDValue PerformBTCombine(SDNode *N,
24176 TargetLowering::DAGCombinerInfo &DCI) {
24177 // BT ignores high bits in the bit index operand.
24178 SDValue Op1 = N->getOperand(1);
24179 if (Op1.hasOneUse()) {
24180 unsigned BitWidth = Op1.getValueSizeInBits();
24181 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24182 APInt KnownZero, KnownOne;
24183 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24184 !DCI.isBeforeLegalizeOps());
24185 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24186 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24187 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24188 DCI.CommitTargetLoweringOpt(TLO);
24193 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24194 SDValue Op = N->getOperand(0);
24195 if (Op.getOpcode() == ISD::BITCAST)
24196 Op = Op.getOperand(0);
24197 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24198 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24199 VT.getVectorElementType().getSizeInBits() ==
24200 OpVT.getVectorElementType().getSizeInBits()) {
24201 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24206 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24207 const X86Subtarget *Subtarget) {
24208 EVT VT = N->getValueType(0);
24209 if (!VT.isVector())
24212 SDValue N0 = N->getOperand(0);
24213 SDValue N1 = N->getOperand(1);
24214 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24217 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24218 // both SSE and AVX2 since there is no sign-extended shift right
24219 // operation on a vector with 64-bit elements.
24220 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24221 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24222 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24223 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24224 SDValue N00 = N0.getOperand(0);
24226 // EXTLOAD has a better solution on AVX2,
24227 // it may be replaced with X86ISD::VSEXT node.
24228 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24229 if (!ISD::isNormalLoad(N00.getNode()))
24232 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24233 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24235 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24241 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24242 TargetLowering::DAGCombinerInfo &DCI,
24243 const X86Subtarget *Subtarget) {
24244 if (!DCI.isBeforeLegalizeOps())
24247 if (!Subtarget->hasFp256())
24250 EVT VT = N->getValueType(0);
24251 if (VT.isVector() && VT.getSizeInBits() == 256) {
24252 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24260 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24261 const X86Subtarget* Subtarget) {
24263 EVT VT = N->getValueType(0);
24265 // Let legalize expand this if it isn't a legal type yet.
24266 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24269 EVT ScalarVT = VT.getScalarType();
24270 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24271 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24274 SDValue A = N->getOperand(0);
24275 SDValue B = N->getOperand(1);
24276 SDValue C = N->getOperand(2);
24278 bool NegA = (A.getOpcode() == ISD::FNEG);
24279 bool NegB = (B.getOpcode() == ISD::FNEG);
24280 bool NegC = (C.getOpcode() == ISD::FNEG);
24282 // Negative multiplication when NegA xor NegB
24283 bool NegMul = (NegA != NegB);
24285 A = A.getOperand(0);
24287 B = B.getOperand(0);
24289 C = C.getOperand(0);
24293 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24295 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24297 return DAG.getNode(Opcode, dl, VT, A, B, C);
24300 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24301 TargetLowering::DAGCombinerInfo &DCI,
24302 const X86Subtarget *Subtarget) {
24303 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24304 // (and (i32 x86isd::setcc_carry), 1)
24305 // This eliminates the zext. This transformation is necessary because
24306 // ISD::SETCC is always legalized to i8.
24308 SDValue N0 = N->getOperand(0);
24309 EVT VT = N->getValueType(0);
24311 if (N0.getOpcode() == ISD::AND &&
24313 N0.getOperand(0).hasOneUse()) {
24314 SDValue N00 = N0.getOperand(0);
24315 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24316 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24317 if (!C || C->getZExtValue() != 1)
24319 return DAG.getNode(ISD::AND, dl, VT,
24320 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24321 N00.getOperand(0), N00.getOperand(1)),
24322 DAG.getConstant(1, VT));
24326 if (N0.getOpcode() == ISD::TRUNCATE &&
24328 N0.getOperand(0).hasOneUse()) {
24329 SDValue N00 = N0.getOperand(0);
24330 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24331 return DAG.getNode(ISD::AND, dl, VT,
24332 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24333 N00.getOperand(0), N00.getOperand(1)),
24334 DAG.getConstant(1, VT));
24337 if (VT.is256BitVector()) {
24338 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24346 // Optimize x == -y --> x+y == 0
24347 // x != -y --> x+y != 0
24348 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24349 const X86Subtarget* Subtarget) {
24350 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24351 SDValue LHS = N->getOperand(0);
24352 SDValue RHS = N->getOperand(1);
24353 EVT VT = N->getValueType(0);
24356 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24358 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24359 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24360 LHS.getValueType(), RHS, LHS.getOperand(1));
24361 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24362 addV, DAG.getConstant(0, addV.getValueType()), CC);
24364 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24365 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24366 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24367 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24368 RHS.getValueType(), LHS, RHS.getOperand(1));
24369 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24370 addV, DAG.getConstant(0, addV.getValueType()), CC);
24373 if (VT.getScalarType() == MVT::i1) {
24374 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24375 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24376 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24377 if (!IsSEXT0 && !IsVZero0)
24379 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24380 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24381 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24383 if (!IsSEXT1 && !IsVZero1)
24386 if (IsSEXT0 && IsVZero1) {
24387 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24388 if (CC == ISD::SETEQ)
24389 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24390 return LHS.getOperand(0);
24392 if (IsSEXT1 && IsVZero0) {
24393 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24394 if (CC == ISD::SETEQ)
24395 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24396 return RHS.getOperand(0);
24403 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24404 const X86Subtarget *Subtarget) {
24406 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24407 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24408 "X86insertps is only defined for v4x32");
24410 SDValue Ld = N->getOperand(1);
24411 if (MayFoldLoad(Ld)) {
24412 // Extract the countS bits from the immediate so we can get the proper
24413 // address when narrowing the vector load to a specific element.
24414 // When the second source op is a memory address, interps doesn't use
24415 // countS and just gets an f32 from that address.
24416 unsigned DestIndex =
24417 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24418 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24422 // Create this as a scalar to vector to match the instruction pattern.
24423 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24424 // countS bits are ignored when loading from memory on insertps, which
24425 // means we don't need to explicitly set them to 0.
24426 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24427 LoadScalarToVector, N->getOperand(2));
24430 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24431 // as "sbb reg,reg", since it can be extended without zext and produces
24432 // an all-ones bit which is more useful than 0/1 in some cases.
24433 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24436 return DAG.getNode(ISD::AND, DL, VT,
24437 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24438 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24439 DAG.getConstant(1, VT));
24440 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24441 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24442 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24443 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24446 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24447 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24448 TargetLowering::DAGCombinerInfo &DCI,
24449 const X86Subtarget *Subtarget) {
24451 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24452 SDValue EFLAGS = N->getOperand(1);
24454 if (CC == X86::COND_A) {
24455 // Try to convert COND_A into COND_B in an attempt to facilitate
24456 // materializing "setb reg".
24458 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24459 // cannot take an immediate as its first operand.
24461 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24462 EFLAGS.getValueType().isInteger() &&
24463 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24464 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24465 EFLAGS.getNode()->getVTList(),
24466 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24467 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24468 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24472 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24473 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24475 if (CC == X86::COND_B)
24476 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24480 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24481 if (Flags.getNode()) {
24482 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24483 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24489 // Optimize branch condition evaluation.
24491 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24492 TargetLowering::DAGCombinerInfo &DCI,
24493 const X86Subtarget *Subtarget) {
24495 SDValue Chain = N->getOperand(0);
24496 SDValue Dest = N->getOperand(1);
24497 SDValue EFLAGS = N->getOperand(3);
24498 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24502 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24503 if (Flags.getNode()) {
24504 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24505 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24512 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24513 SelectionDAG &DAG) {
24514 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24515 // optimize away operation when it's from a constant.
24517 // The general transformation is:
24518 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24519 // AND(VECTOR_CMP(x,y), constant2)
24520 // constant2 = UNARYOP(constant)
24522 // Early exit if this isn't a vector operation, the operand of the
24523 // unary operation isn't a bitwise AND, or if the sizes of the operations
24524 // aren't the same.
24525 EVT VT = N->getValueType(0);
24526 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24527 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24528 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24531 // Now check that the other operand of the AND is a constant. We could
24532 // make the transformation for non-constant splats as well, but it's unclear
24533 // that would be a benefit as it would not eliminate any operations, just
24534 // perform one more step in scalar code before moving to the vector unit.
24535 if (BuildVectorSDNode *BV =
24536 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24537 // Bail out if the vector isn't a constant.
24538 if (!BV->isConstant())
24541 // Everything checks out. Build up the new and improved node.
24543 EVT IntVT = BV->getValueType(0);
24544 // Create a new constant of the appropriate type for the transformed
24546 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24547 // The AND node needs bitcasts to/from an integer vector type around it.
24548 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24549 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24550 N->getOperand(0)->getOperand(0), MaskConst);
24551 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24558 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24559 const X86TargetLowering *XTLI) {
24560 // First try to optimize away the conversion entirely when it's
24561 // conditionally from a constant. Vectors only.
24562 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24563 if (Res != SDValue())
24566 // Now move on to more general possibilities.
24567 SDValue Op0 = N->getOperand(0);
24568 EVT InVT = Op0->getValueType(0);
24570 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24571 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24573 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24574 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24575 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24578 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24579 // a 32-bit target where SSE doesn't support i64->FP operations.
24580 if (Op0.getOpcode() == ISD::LOAD) {
24581 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24582 EVT VT = Ld->getValueType(0);
24583 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24584 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24585 !XTLI->getSubtarget()->is64Bit() &&
24587 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24588 Ld->getChain(), Op0, DAG);
24589 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24596 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24597 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24598 X86TargetLowering::DAGCombinerInfo &DCI) {
24599 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24600 // the result is either zero or one (depending on the input carry bit).
24601 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24602 if (X86::isZeroNode(N->getOperand(0)) &&
24603 X86::isZeroNode(N->getOperand(1)) &&
24604 // We don't have a good way to replace an EFLAGS use, so only do this when
24606 SDValue(N, 1).use_empty()) {
24608 EVT VT = N->getValueType(0);
24609 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24610 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24611 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24612 DAG.getConstant(X86::COND_B,MVT::i8),
24614 DAG.getConstant(1, VT));
24615 return DCI.CombineTo(N, Res1, CarryOut);
24621 // fold (add Y, (sete X, 0)) -> adc 0, Y
24622 // (add Y, (setne X, 0)) -> sbb -1, Y
24623 // (sub (sete X, 0), Y) -> sbb 0, Y
24624 // (sub (setne X, 0), Y) -> adc -1, Y
24625 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24628 // Look through ZExts.
24629 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24630 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24633 SDValue SetCC = Ext.getOperand(0);
24634 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24637 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24638 if (CC != X86::COND_E && CC != X86::COND_NE)
24641 SDValue Cmp = SetCC.getOperand(1);
24642 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24643 !X86::isZeroNode(Cmp.getOperand(1)) ||
24644 !Cmp.getOperand(0).getValueType().isInteger())
24647 SDValue CmpOp0 = Cmp.getOperand(0);
24648 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24649 DAG.getConstant(1, CmpOp0.getValueType()));
24651 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24652 if (CC == X86::COND_NE)
24653 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24654 DL, OtherVal.getValueType(), OtherVal,
24655 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24656 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24657 DL, OtherVal.getValueType(), OtherVal,
24658 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24661 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24662 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24663 const X86Subtarget *Subtarget) {
24664 EVT VT = N->getValueType(0);
24665 SDValue Op0 = N->getOperand(0);
24666 SDValue Op1 = N->getOperand(1);
24668 // Try to synthesize horizontal adds from adds of shuffles.
24669 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24670 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24671 isHorizontalBinOp(Op0, Op1, true))
24672 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24674 return OptimizeConditionalInDecrement(N, DAG);
24677 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24678 const X86Subtarget *Subtarget) {
24679 SDValue Op0 = N->getOperand(0);
24680 SDValue Op1 = N->getOperand(1);
24682 // X86 can't encode an immediate LHS of a sub. See if we can push the
24683 // negation into a preceding instruction.
24684 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24685 // If the RHS of the sub is a XOR with one use and a constant, invert the
24686 // immediate. Then add one to the LHS of the sub so we can turn
24687 // X-Y -> X+~Y+1, saving one register.
24688 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24689 isa<ConstantSDNode>(Op1.getOperand(1))) {
24690 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24691 EVT VT = Op0.getValueType();
24692 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24694 DAG.getConstant(~XorC, VT));
24695 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24696 DAG.getConstant(C->getAPIntValue()+1, VT));
24700 // Try to synthesize horizontal adds from adds of shuffles.
24701 EVT VT = N->getValueType(0);
24702 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24703 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24704 isHorizontalBinOp(Op0, Op1, true))
24705 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24707 return OptimizeConditionalInDecrement(N, DAG);
24710 /// performVZEXTCombine - Performs build vector combines
24711 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24712 TargetLowering::DAGCombinerInfo &DCI,
24713 const X86Subtarget *Subtarget) {
24715 MVT VT = N->getSimpleValueType(0);
24716 SDValue Op = N->getOperand(0);
24717 MVT OpVT = Op.getSimpleValueType();
24718 MVT OpEltVT = OpVT.getVectorElementType();
24719 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24721 // (vzext (bitcast (vzext (x)) -> (vzext x)
24723 while (V.getOpcode() == ISD::BITCAST)
24724 V = V.getOperand(0);
24726 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24727 MVT InnerVT = V.getSimpleValueType();
24728 MVT InnerEltVT = InnerVT.getVectorElementType();
24730 // If the element sizes match exactly, we can just do one larger vzext. This
24731 // is always an exact type match as vzext operates on integer types.
24732 if (OpEltVT == InnerEltVT) {
24733 assert(OpVT == InnerVT && "Types must match for vzext!");
24734 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24737 // The only other way we can combine them is if only a single element of the
24738 // inner vzext is used in the input to the outer vzext.
24739 if (InnerEltVT.getSizeInBits() < InputBits)
24742 // In this case, the inner vzext is completely dead because we're going to
24743 // only look at bits inside of the low element. Just do the outer vzext on
24744 // a bitcast of the input to the inner.
24745 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24746 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24749 // Check if we can bypass extracting and re-inserting an element of an input
24750 // vector. Essentialy:
24751 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24752 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24753 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24754 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24755 SDValue ExtractedV = V.getOperand(0);
24756 SDValue OrigV = ExtractedV.getOperand(0);
24757 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24758 if (ExtractIdx->getZExtValue() == 0) {
24759 MVT OrigVT = OrigV.getSimpleValueType();
24760 // Extract a subvector if necessary...
24761 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24762 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24763 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24764 OrigVT.getVectorNumElements() / Ratio);
24765 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24766 DAG.getIntPtrConstant(0));
24768 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24769 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24776 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24777 DAGCombinerInfo &DCI) const {
24778 SelectionDAG &DAG = DCI.DAG;
24779 switch (N->getOpcode()) {
24781 case ISD::EXTRACT_VECTOR_ELT:
24782 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24784 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24785 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24786 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24787 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24788 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24789 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24792 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24793 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24794 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24795 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24796 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24797 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24798 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24799 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24800 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24802 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24804 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24805 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24806 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24807 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24808 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24809 case ISD::ANY_EXTEND:
24810 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24811 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24812 case ISD::SIGN_EXTEND_INREG:
24813 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24814 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24815 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24816 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24817 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24818 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24819 case X86ISD::SHUFP: // Handle all target specific shuffles
24820 case X86ISD::PALIGNR:
24821 case X86ISD::UNPCKH:
24822 case X86ISD::UNPCKL:
24823 case X86ISD::MOVHLPS:
24824 case X86ISD::MOVLHPS:
24825 case X86ISD::PSHUFB:
24826 case X86ISD::PSHUFD:
24827 case X86ISD::PSHUFHW:
24828 case X86ISD::PSHUFLW:
24829 case X86ISD::MOVSS:
24830 case X86ISD::MOVSD:
24831 case X86ISD::VPERMILPI:
24832 case X86ISD::VPERM2X128:
24833 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24834 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24835 case ISD::INTRINSIC_WO_CHAIN:
24836 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24837 case X86ISD::INSERTPS:
24838 return PerformINSERTPSCombine(N, DAG, Subtarget);
24839 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24845 /// isTypeDesirableForOp - Return true if the target has native support for
24846 /// the specified value type and it is 'desirable' to use the type for the
24847 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24848 /// instruction encodings are longer and some i16 instructions are slow.
24849 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24850 if (!isTypeLegal(VT))
24852 if (VT != MVT::i16)
24859 case ISD::SIGN_EXTEND:
24860 case ISD::ZERO_EXTEND:
24861 case ISD::ANY_EXTEND:
24874 /// IsDesirableToPromoteOp - This method query the target whether it is
24875 /// beneficial for dag combiner to promote the specified node. If true, it
24876 /// should return the desired promotion type by reference.
24877 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24878 EVT VT = Op.getValueType();
24879 if (VT != MVT::i16)
24882 bool Promote = false;
24883 bool Commute = false;
24884 switch (Op.getOpcode()) {
24887 LoadSDNode *LD = cast<LoadSDNode>(Op);
24888 // If the non-extending load has a single use and it's not live out, then it
24889 // might be folded.
24890 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24891 Op.hasOneUse()*/) {
24892 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24893 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24894 // The only case where we'd want to promote LOAD (rather then it being
24895 // promoted as an operand is when it's only use is liveout.
24896 if (UI->getOpcode() != ISD::CopyToReg)
24903 case ISD::SIGN_EXTEND:
24904 case ISD::ZERO_EXTEND:
24905 case ISD::ANY_EXTEND:
24910 SDValue N0 = Op.getOperand(0);
24911 // Look out for (store (shl (load), x)).
24912 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24925 SDValue N0 = Op.getOperand(0);
24926 SDValue N1 = Op.getOperand(1);
24927 if (!Commute && MayFoldLoad(N1))
24929 // Avoid disabling potential load folding opportunities.
24930 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24932 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24942 //===----------------------------------------------------------------------===//
24943 // X86 Inline Assembly Support
24944 //===----------------------------------------------------------------------===//
24947 // Helper to match a string separated by whitespace.
24948 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24949 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24951 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24952 StringRef piece(*args[i]);
24953 if (!s.startswith(piece)) // Check if the piece matches.
24956 s = s.substr(piece.size());
24957 StringRef::size_type pos = s.find_first_not_of(" \t");
24958 if (pos == 0) // We matched a prefix.
24966 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24969 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24971 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24972 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24973 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24974 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24976 if (AsmPieces.size() == 3)
24978 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24985 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24986 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24988 std::string AsmStr = IA->getAsmString();
24990 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24991 if (!Ty || Ty->getBitWidth() % 16 != 0)
24994 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24995 SmallVector<StringRef, 4> AsmPieces;
24996 SplitString(AsmStr, AsmPieces, ";\n");
24998 switch (AsmPieces.size()) {
24999 default: return false;
25001 // FIXME: this should verify that we are targeting a 486 or better. If not,
25002 // we will turn this bswap into something that will be lowered to logical
25003 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25004 // lower so don't worry about this.
25006 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25007 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25008 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25009 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25010 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25011 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25012 // No need to check constraints, nothing other than the equivalent of
25013 // "=r,0" would be valid here.
25014 return IntrinsicLowering::LowerToByteSwap(CI);
25017 // rorw $$8, ${0:w} --> llvm.bswap.i16
25018 if (CI->getType()->isIntegerTy(16) &&
25019 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25020 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25021 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25023 const std::string &ConstraintsStr = IA->getConstraintString();
25024 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25025 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25026 if (clobbersFlagRegisters(AsmPieces))
25027 return IntrinsicLowering::LowerToByteSwap(CI);
25031 if (CI->getType()->isIntegerTy(32) &&
25032 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25033 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25034 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25035 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25037 const std::string &ConstraintsStr = IA->getConstraintString();
25038 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25039 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25040 if (clobbersFlagRegisters(AsmPieces))
25041 return IntrinsicLowering::LowerToByteSwap(CI);
25044 if (CI->getType()->isIntegerTy(64)) {
25045 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25046 if (Constraints.size() >= 2 &&
25047 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25048 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25049 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25050 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25051 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25052 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25053 return IntrinsicLowering::LowerToByteSwap(CI);
25061 /// getConstraintType - Given a constraint letter, return the type of
25062 /// constraint it is for this target.
25063 X86TargetLowering::ConstraintType
25064 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25065 if (Constraint.size() == 1) {
25066 switch (Constraint[0]) {
25077 return C_RegisterClass;
25101 return TargetLowering::getConstraintType(Constraint);
25104 /// Examine constraint type and operand type and determine a weight value.
25105 /// This object must already have been set up with the operand type
25106 /// and the current alternative constraint selected.
25107 TargetLowering::ConstraintWeight
25108 X86TargetLowering::getSingleConstraintMatchWeight(
25109 AsmOperandInfo &info, const char *constraint) const {
25110 ConstraintWeight weight = CW_Invalid;
25111 Value *CallOperandVal = info.CallOperandVal;
25112 // If we don't have a value, we can't do a match,
25113 // but allow it at the lowest weight.
25114 if (!CallOperandVal)
25116 Type *type = CallOperandVal->getType();
25117 // Look at the constraint type.
25118 switch (*constraint) {
25120 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25131 if (CallOperandVal->getType()->isIntegerTy())
25132 weight = CW_SpecificReg;
25137 if (type->isFloatingPointTy())
25138 weight = CW_SpecificReg;
25141 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25142 weight = CW_SpecificReg;
25146 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25147 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25148 weight = CW_Register;
25151 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25152 if (C->getZExtValue() <= 31)
25153 weight = CW_Constant;
25157 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25158 if (C->getZExtValue() <= 63)
25159 weight = CW_Constant;
25163 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25164 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25165 weight = CW_Constant;
25169 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25170 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25171 weight = CW_Constant;
25175 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25176 if (C->getZExtValue() <= 3)
25177 weight = CW_Constant;
25181 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25182 if (C->getZExtValue() <= 0xff)
25183 weight = CW_Constant;
25188 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25189 weight = CW_Constant;
25193 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25194 if ((C->getSExtValue() >= -0x80000000LL) &&
25195 (C->getSExtValue() <= 0x7fffffffLL))
25196 weight = CW_Constant;
25200 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25201 if (C->getZExtValue() <= 0xffffffff)
25202 weight = CW_Constant;
25209 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25210 /// with another that has more specific requirements based on the type of the
25211 /// corresponding operand.
25212 const char *X86TargetLowering::
25213 LowerXConstraint(EVT ConstraintVT) const {
25214 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25215 // 'f' like normal targets.
25216 if (ConstraintVT.isFloatingPoint()) {
25217 if (Subtarget->hasSSE2())
25219 if (Subtarget->hasSSE1())
25223 return TargetLowering::LowerXConstraint(ConstraintVT);
25226 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25227 /// vector. If it is invalid, don't add anything to Ops.
25228 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25229 std::string &Constraint,
25230 std::vector<SDValue>&Ops,
25231 SelectionDAG &DAG) const {
25234 // Only support length 1 constraints for now.
25235 if (Constraint.length() > 1) return;
25237 char ConstraintLetter = Constraint[0];
25238 switch (ConstraintLetter) {
25241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25242 if (C->getZExtValue() <= 31) {
25243 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25250 if (C->getZExtValue() <= 63) {
25251 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25258 if (isInt<8>(C->getSExtValue())) {
25259 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25265 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25266 if (C->getZExtValue() <= 255) {
25267 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25273 // 32-bit signed value
25274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25275 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25276 C->getSExtValue())) {
25277 // Widen to 64 bits here to get it sign extended.
25278 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25281 // FIXME gcc accepts some relocatable values here too, but only in certain
25282 // memory models; it's complicated.
25287 // 32-bit unsigned value
25288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25289 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25290 C->getZExtValue())) {
25291 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25295 // FIXME gcc accepts some relocatable values here too, but only in certain
25296 // memory models; it's complicated.
25300 // Literal immediates are always ok.
25301 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25302 // Widen to 64 bits here to get it sign extended.
25303 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25307 // In any sort of PIC mode addresses need to be computed at runtime by
25308 // adding in a register or some sort of table lookup. These can't
25309 // be used as immediates.
25310 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25313 // If we are in non-pic codegen mode, we allow the address of a global (with
25314 // an optional displacement) to be used with 'i'.
25315 GlobalAddressSDNode *GA = nullptr;
25316 int64_t Offset = 0;
25318 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25320 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25321 Offset += GA->getOffset();
25323 } else if (Op.getOpcode() == ISD::ADD) {
25324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25325 Offset += C->getZExtValue();
25326 Op = Op.getOperand(0);
25329 } else if (Op.getOpcode() == ISD::SUB) {
25330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25331 Offset += -C->getZExtValue();
25332 Op = Op.getOperand(0);
25337 // Otherwise, this isn't something we can handle, reject it.
25341 const GlobalValue *GV = GA->getGlobal();
25342 // If we require an extra load to get this address, as in PIC mode, we
25343 // can't accept it.
25344 if (isGlobalStubReference(
25345 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25348 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25349 GA->getValueType(0), Offset);
25354 if (Result.getNode()) {
25355 Ops.push_back(Result);
25358 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25361 std::pair<unsigned, const TargetRegisterClass*>
25362 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25364 // First, see if this is a constraint that directly corresponds to an LLVM
25366 if (Constraint.size() == 1) {
25367 // GCC Constraint Letters
25368 switch (Constraint[0]) {
25370 // TODO: Slight differences here in allocation order and leaving
25371 // RIP in the class. Do they matter any more here than they do
25372 // in the normal allocation?
25373 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25374 if (Subtarget->is64Bit()) {
25375 if (VT == MVT::i32 || VT == MVT::f32)
25376 return std::make_pair(0U, &X86::GR32RegClass);
25377 if (VT == MVT::i16)
25378 return std::make_pair(0U, &X86::GR16RegClass);
25379 if (VT == MVT::i8 || VT == MVT::i1)
25380 return std::make_pair(0U, &X86::GR8RegClass);
25381 if (VT == MVT::i64 || VT == MVT::f64)
25382 return std::make_pair(0U, &X86::GR64RegClass);
25385 // 32-bit fallthrough
25386 case 'Q': // Q_REGS
25387 if (VT == MVT::i32 || VT == MVT::f32)
25388 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25389 if (VT == MVT::i16)
25390 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25391 if (VT == MVT::i8 || VT == MVT::i1)
25392 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25393 if (VT == MVT::i64)
25394 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25396 case 'r': // GENERAL_REGS
25397 case 'l': // INDEX_REGS
25398 if (VT == MVT::i8 || VT == MVT::i1)
25399 return std::make_pair(0U, &X86::GR8RegClass);
25400 if (VT == MVT::i16)
25401 return std::make_pair(0U, &X86::GR16RegClass);
25402 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25403 return std::make_pair(0U, &X86::GR32RegClass);
25404 return std::make_pair(0U, &X86::GR64RegClass);
25405 case 'R': // LEGACY_REGS
25406 if (VT == MVT::i8 || VT == MVT::i1)
25407 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25408 if (VT == MVT::i16)
25409 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25410 if (VT == MVT::i32 || !Subtarget->is64Bit())
25411 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25412 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25413 case 'f': // FP Stack registers.
25414 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25415 // value to the correct fpstack register class.
25416 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25417 return std::make_pair(0U, &X86::RFP32RegClass);
25418 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25419 return std::make_pair(0U, &X86::RFP64RegClass);
25420 return std::make_pair(0U, &X86::RFP80RegClass);
25421 case 'y': // MMX_REGS if MMX allowed.
25422 if (!Subtarget->hasMMX()) break;
25423 return std::make_pair(0U, &X86::VR64RegClass);
25424 case 'Y': // SSE_REGS if SSE2 allowed
25425 if (!Subtarget->hasSSE2()) break;
25427 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25428 if (!Subtarget->hasSSE1()) break;
25430 switch (VT.SimpleTy) {
25432 // Scalar SSE types.
25435 return std::make_pair(0U, &X86::FR32RegClass);
25438 return std::make_pair(0U, &X86::FR64RegClass);
25446 return std::make_pair(0U, &X86::VR128RegClass);
25454 return std::make_pair(0U, &X86::VR256RegClass);
25459 return std::make_pair(0U, &X86::VR512RegClass);
25465 // Use the default implementation in TargetLowering to convert the register
25466 // constraint into a member of a register class.
25467 std::pair<unsigned, const TargetRegisterClass*> Res;
25468 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25470 // Not found as a standard register?
25472 // Map st(0) -> st(7) -> ST0
25473 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25474 tolower(Constraint[1]) == 's' &&
25475 tolower(Constraint[2]) == 't' &&
25476 Constraint[3] == '(' &&
25477 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25478 Constraint[5] == ')' &&
25479 Constraint[6] == '}') {
25481 Res.first = X86::FP0+Constraint[4]-'0';
25482 Res.second = &X86::RFP80RegClass;
25486 // GCC allows "st(0)" to be called just plain "st".
25487 if (StringRef("{st}").equals_lower(Constraint)) {
25488 Res.first = X86::FP0;
25489 Res.second = &X86::RFP80RegClass;
25494 if (StringRef("{flags}").equals_lower(Constraint)) {
25495 Res.first = X86::EFLAGS;
25496 Res.second = &X86::CCRRegClass;
25500 // 'A' means EAX + EDX.
25501 if (Constraint == "A") {
25502 Res.first = X86::EAX;
25503 Res.second = &X86::GR32_ADRegClass;
25509 // Otherwise, check to see if this is a register class of the wrong value
25510 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25511 // turn into {ax},{dx}.
25512 if (Res.second->hasType(VT))
25513 return Res; // Correct type already, nothing to do.
25515 // All of the single-register GCC register classes map their values onto
25516 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25517 // really want an 8-bit or 32-bit register, map to the appropriate register
25518 // class and return the appropriate register.
25519 if (Res.second == &X86::GR16RegClass) {
25520 if (VT == MVT::i8 || VT == MVT::i1) {
25521 unsigned DestReg = 0;
25522 switch (Res.first) {
25524 case X86::AX: DestReg = X86::AL; break;
25525 case X86::DX: DestReg = X86::DL; break;
25526 case X86::CX: DestReg = X86::CL; break;
25527 case X86::BX: DestReg = X86::BL; break;
25530 Res.first = DestReg;
25531 Res.second = &X86::GR8RegClass;
25533 } else if (VT == MVT::i32 || VT == MVT::f32) {
25534 unsigned DestReg = 0;
25535 switch (Res.first) {
25537 case X86::AX: DestReg = X86::EAX; break;
25538 case X86::DX: DestReg = X86::EDX; break;
25539 case X86::CX: DestReg = X86::ECX; break;
25540 case X86::BX: DestReg = X86::EBX; break;
25541 case X86::SI: DestReg = X86::ESI; break;
25542 case X86::DI: DestReg = X86::EDI; break;
25543 case X86::BP: DestReg = X86::EBP; break;
25544 case X86::SP: DestReg = X86::ESP; break;
25547 Res.first = DestReg;
25548 Res.second = &X86::GR32RegClass;
25550 } else if (VT == MVT::i64 || VT == MVT::f64) {
25551 unsigned DestReg = 0;
25552 switch (Res.first) {
25554 case X86::AX: DestReg = X86::RAX; break;
25555 case X86::DX: DestReg = X86::RDX; break;
25556 case X86::CX: DestReg = X86::RCX; break;
25557 case X86::BX: DestReg = X86::RBX; break;
25558 case X86::SI: DestReg = X86::RSI; break;
25559 case X86::DI: DestReg = X86::RDI; break;
25560 case X86::BP: DestReg = X86::RBP; break;
25561 case X86::SP: DestReg = X86::RSP; break;
25564 Res.first = DestReg;
25565 Res.second = &X86::GR64RegClass;
25568 } else if (Res.second == &X86::FR32RegClass ||
25569 Res.second == &X86::FR64RegClass ||
25570 Res.second == &X86::VR128RegClass ||
25571 Res.second == &X86::VR256RegClass ||
25572 Res.second == &X86::FR32XRegClass ||
25573 Res.second == &X86::FR64XRegClass ||
25574 Res.second == &X86::VR128XRegClass ||
25575 Res.second == &X86::VR256XRegClass ||
25576 Res.second == &X86::VR512RegClass) {
25577 // Handle references to XMM physical registers that got mapped into the
25578 // wrong class. This can happen with constraints like {xmm0} where the
25579 // target independent register mapper will just pick the first match it can
25580 // find, ignoring the required type.
25582 if (VT == MVT::f32 || VT == MVT::i32)
25583 Res.second = &X86::FR32RegClass;
25584 else if (VT == MVT::f64 || VT == MVT::i64)
25585 Res.second = &X86::FR64RegClass;
25586 else if (X86::VR128RegClass.hasType(VT))
25587 Res.second = &X86::VR128RegClass;
25588 else if (X86::VR256RegClass.hasType(VT))
25589 Res.second = &X86::VR256RegClass;
25590 else if (X86::VR512RegClass.hasType(VT))
25591 Res.second = &X86::VR512RegClass;
25597 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25599 // Scaling factors are not free at all.
25600 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25601 // will take 2 allocations in the out of order engine instead of 1
25602 // for plain addressing mode, i.e. inst (reg1).
25604 // vaddps (%rsi,%drx), %ymm0, %ymm1
25605 // Requires two allocations (one for the load, one for the computation)
25607 // vaddps (%rsi), %ymm0, %ymm1
25608 // Requires just 1 allocation, i.e., freeing allocations for other operations
25609 // and having less micro operations to execute.
25611 // For some X86 architectures, this is even worse because for instance for
25612 // stores, the complex addressing mode forces the instruction to use the
25613 // "load" ports instead of the dedicated "store" port.
25614 // E.g., on Haswell:
25615 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25616 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25617 if (isLegalAddressingMode(AM, Ty))
25618 // Scale represents reg2 * scale, thus account for 1
25619 // as soon as we use a second register.
25620 return AM.Scale != 0;
25624 bool X86TargetLowering::isTargetFTOL() const {
25625 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();