1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
991 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
992 MVT VT = (MVT::SimpleValueType)i;
993 // Do not attempt to custom lower non-power-of-2 vectors
994 if (!isPowerOf2_32(VT.getVectorNumElements()))
996 // Do not attempt to custom lower non-128-bit vectors
997 if (!VT.is128BitVector())
999 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1004 // We support custom legalizing of sext and anyext loads for specific
1005 // memory vector types which we can load as a scalar (or sequence of
1006 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1007 // loads these must work with a single scalar load.
1008 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1009 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1010 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1011 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1012 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1013 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1018 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1019 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1020 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1021 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1025 if (Subtarget->is64Bit()) {
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1030 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1031 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1032 MVT VT = (MVT::SimpleValueType)i;
1034 // Do not attempt to promote non-128-bit vectors
1035 if (!VT.is128BitVector())
1038 setOperationAction(ISD::AND, VT, Promote);
1039 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1040 setOperationAction(ISD::OR, VT, Promote);
1041 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1042 setOperationAction(ISD::XOR, VT, Promote);
1043 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1044 setOperationAction(ISD::LOAD, VT, Promote);
1045 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1046 setOperationAction(ISD::SELECT, VT, Promote);
1047 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1050 // Custom lower v2i64 and v2f64 selects.
1051 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1052 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1053 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1056 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1059 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1060 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1061 // As there is no 64-bit GPR available, we need build a special custom
1062 // sequence to convert from v2i32 to v2f32.
1063 if (!Subtarget->is64Bit())
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1066 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1067 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1069 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1071 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1072 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1073 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1076 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1077 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1078 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1079 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1080 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1081 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1088 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1089 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1090 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1091 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1099 // FIXME: Do we need to handle scalar-to-vector here?
1100 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1102 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1103 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1104 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1107 // There is no BLENDI for byte vectors. We don't need to custom lower
1108 // some vselects for now.
1109 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1111 // SSE41 brings specific instructions for doing vector sign extend even in
1112 // cases where we don't have SRA.
1113 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1114 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1115 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1117 // i8 and i16 vectors are custom because the source register and source
1118 // source memory operand types are not the same width. f32 vectors are
1119 // custom since the immediate controlling the insert encodes additional
1121 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1122 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1131 // FIXME: these should be Legal, but that's only for the case where
1132 // the index is constant. For now custom expand to deal with that.
1133 if (Subtarget->is64Bit()) {
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1139 if (Subtarget->hasSSE2()) {
1140 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1141 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1143 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1149 // In the customized shift lowering, the legal cases in AVX2 will be
1151 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1152 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1154 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1160 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1161 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1162 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1163 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1164 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1168 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1169 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1170 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1172 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1174 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1175 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1183 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1185 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1196 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1198 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1199 // even though v8i16 is a legal type.
1200 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1201 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1202 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1204 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1205 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1206 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1211 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1213 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1227 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1228 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1231 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1247 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1249 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1250 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1252 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1253 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1254 setOperationAction(ISD::FMA, MVT::f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::f64, Legal);
1258 if (Subtarget->hasInt256()) {
1259 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1260 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1261 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1262 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1264 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1265 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1266 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1267 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1269 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1270 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1271 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1272 // Don't lower v32i8 because there is no 128-bit byte mul
1274 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1276 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1277 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1279 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1283 // when we have a 256bit-wide blend with immediate.
1284 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1286 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1287 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1288 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1289 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1291 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1292 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1293 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1294 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1296 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1297 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1298 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1299 // Don't lower v32i8 because there is no 128-bit byte mul
1302 // In the customized shift lowering, the legal cases in AVX2 will be
1304 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1312 // Custom lower several nodes for 256-bit types.
1313 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1315 MVT VT = (MVT::SimpleValueType)i;
1317 // Extract subvector is special because the value type
1318 // (result) is 128-bit but the source is 256-bit wide.
1319 if (VT.is128BitVector()) {
1320 if (VT.getScalarSizeInBits() >= 32) {
1321 setOperationAction(ISD::MLOAD, VT, Custom);
1322 setOperationAction(ISD::MSTORE, VT, Custom);
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 if (VT.getScalarSizeInBits() >= 32) {
1331 setOperationAction(ISD::MLOAD, VT, Legal);
1332 setOperationAction(ISD::MSTORE, VT, Legal);
1334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1336 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1339 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1340 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1343 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1344 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1345 MVT VT = (MVT::SimpleValueType)i;
1347 // Do not attempt to promote non-256-bit vectors
1348 if (!VT.is256BitVector())
1351 setOperationAction(ISD::AND, VT, Promote);
1352 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1353 setOperationAction(ISD::OR, VT, Promote);
1354 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1355 setOperationAction(ISD::XOR, VT, Promote);
1356 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1357 setOperationAction(ISD::LOAD, VT, Promote);
1358 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1359 setOperationAction(ISD::SELECT, VT, Promote);
1360 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1365 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1366 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1371 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1372 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1374 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1376 setOperationAction(ISD::XOR, MVT::i1, Legal);
1377 setOperationAction(ISD::OR, MVT::i1, Legal);
1378 setOperationAction(ISD::AND, MVT::i1, Legal);
1379 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1386 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1393 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1399 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1406 if (Subtarget->is64Bit()) {
1407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1427 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1448 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1449 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1451 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1456 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1458 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1463 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1464 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1466 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1467 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1469 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1471 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1477 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1480 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1481 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1482 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1483 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1484 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1485 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1487 if (Subtarget->hasCDI()) {
1488 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1489 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1492 // Custom lower several nodes.
1493 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1494 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1495 MVT VT = (MVT::SimpleValueType)i;
1497 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1498 // Extract subvector is special because the value type
1499 // (result) is 256/128-bit but the source is 512-bit wide.
1500 if (VT.is128BitVector() || VT.is256BitVector()) {
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1502 if ( EltSize >= 32) {
1503 setOperationAction(ISD::MLOAD, VT, Legal);
1504 setOperationAction(ISD::MSTORE, VT, Legal);
1507 if (VT.getVectorElementType() == MVT::i1)
1508 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1510 // Do not attempt to custom lower other non-512-bit vectors
1511 if (!VT.is512BitVector())
1514 if ( EltSize >= 32) {
1515 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1516 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1517 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1518 setOperationAction(ISD::VSELECT, VT, Legal);
1519 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1521 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1522 setOperationAction(ISD::MLOAD, VT, Legal);
1523 setOperationAction(ISD::MSTORE, VT, Legal);
1526 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1527 MVT VT = (MVT::SimpleValueType)i;
1529 // Do not attempt to promote non-256-bit vectors.
1530 if (!VT.is512BitVector())
1533 setOperationAction(ISD::SELECT, VT, Promote);
1534 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1538 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1539 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1540 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1542 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1543 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1545 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1546 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1547 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1548 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1550 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1551 const MVT VT = (MVT::SimpleValueType)i;
1553 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1555 // Do not attempt to promote non-256-bit vectors.
1556 if (!VT.is512BitVector())
1560 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1561 setOperationAction(ISD::VSELECT, VT, Legal);
1566 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1567 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1568 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1570 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1572 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1575 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1576 // of this type with custom code.
1577 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1578 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1579 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1583 // We want to custom lower some of our intrinsics.
1584 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1585 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1586 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1587 if (!Subtarget->is64Bit())
1588 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1590 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1591 // handle type legalization for these operations here.
1593 // FIXME: We really should do custom legalization for addition and
1594 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1595 // than generic legalization for 64-bit multiplication-with-overflow, though.
1596 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1597 // Add/Sub/Mul with overflow operations are custom lowered.
1599 setOperationAction(ISD::SADDO, VT, Custom);
1600 setOperationAction(ISD::UADDO, VT, Custom);
1601 setOperationAction(ISD::SSUBO, VT, Custom);
1602 setOperationAction(ISD::USUBO, VT, Custom);
1603 setOperationAction(ISD::SMULO, VT, Custom);
1604 setOperationAction(ISD::UMULO, VT, Custom);
1608 if (!Subtarget->is64Bit()) {
1609 // These libcalls are not available in 32-bit.
1610 setLibcallName(RTLIB::SHL_I128, nullptr);
1611 setLibcallName(RTLIB::SRL_I128, nullptr);
1612 setLibcallName(RTLIB::SRA_I128, nullptr);
1615 // Combine sin / cos into one node or libcall if possible.
1616 if (Subtarget->hasSinCos()) {
1617 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1618 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1619 if (Subtarget->isTargetDarwin()) {
1620 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1621 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1622 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1623 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1627 if (Subtarget->isTargetWin64()) {
1628 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1629 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1630 setOperationAction(ISD::SREM, MVT::i128, Custom);
1631 setOperationAction(ISD::UREM, MVT::i128, Custom);
1632 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1633 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1636 // We have target-specific dag combine patterns for the following nodes:
1637 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1638 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1639 setTargetDAGCombine(ISD::VSELECT);
1640 setTargetDAGCombine(ISD::SELECT);
1641 setTargetDAGCombine(ISD::SHL);
1642 setTargetDAGCombine(ISD::SRA);
1643 setTargetDAGCombine(ISD::SRL);
1644 setTargetDAGCombine(ISD::OR);
1645 setTargetDAGCombine(ISD::AND);
1646 setTargetDAGCombine(ISD::ADD);
1647 setTargetDAGCombine(ISD::FADD);
1648 setTargetDAGCombine(ISD::FSUB);
1649 setTargetDAGCombine(ISD::FMA);
1650 setTargetDAGCombine(ISD::SUB);
1651 setTargetDAGCombine(ISD::LOAD);
1652 setTargetDAGCombine(ISD::STORE);
1653 setTargetDAGCombine(ISD::ZERO_EXTEND);
1654 setTargetDAGCombine(ISD::ANY_EXTEND);
1655 setTargetDAGCombine(ISD::SIGN_EXTEND);
1656 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1657 setTargetDAGCombine(ISD::TRUNCATE);
1658 setTargetDAGCombine(ISD::SINT_TO_FP);
1659 setTargetDAGCombine(ISD::SETCC);
1660 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1661 setTargetDAGCombine(ISD::BUILD_VECTOR);
1662 if (Subtarget->is64Bit())
1663 setTargetDAGCombine(ISD::MUL);
1664 setTargetDAGCombine(ISD::XOR);
1666 computeRegisterProperties();
1668 // On Darwin, -Os means optimize for size without hurting performance,
1669 // do not reduce the limit.
1670 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1671 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1672 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1673 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1674 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1675 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1676 setPrefLoopAlignment(4); // 2^4 bytes.
1678 // Predictable cmov don't hurt on atom because it's in-order.
1679 PredictableSelectIsExpensive = !Subtarget->isAtom();
1681 setPrefFunctionAlignment(4); // 2^4 bytes.
1683 verifyIntrinsicTables();
1686 // This has so far only been implemented for 64-bit MachO.
1687 bool X86TargetLowering::useLoadStackGuardNode() const {
1688 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1691 TargetLoweringBase::LegalizeTypeAction
1692 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1693 if (ExperimentalVectorWideningLegalization &&
1694 VT.getVectorNumElements() != 1 &&
1695 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1696 return TypeWidenVector;
1698 return TargetLoweringBase::getPreferredVectorAction(VT);
1701 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1703 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1705 const unsigned NumElts = VT.getVectorNumElements();
1706 const EVT EltVT = VT.getVectorElementType();
1707 if (VT.is512BitVector()) {
1708 if (Subtarget->hasAVX512())
1709 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1710 EltVT == MVT::f32 || EltVT == MVT::f64)
1712 case 8: return MVT::v8i1;
1713 case 16: return MVT::v16i1;
1715 if (Subtarget->hasBWI())
1716 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1718 case 32: return MVT::v32i1;
1719 case 64: return MVT::v64i1;
1723 if (VT.is256BitVector() || VT.is128BitVector()) {
1724 if (Subtarget->hasVLX())
1725 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1726 EltVT == MVT::f32 || EltVT == MVT::f64)
1728 case 2: return MVT::v2i1;
1729 case 4: return MVT::v4i1;
1730 case 8: return MVT::v8i1;
1732 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1733 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1735 case 8: return MVT::v8i1;
1736 case 16: return MVT::v16i1;
1737 case 32: return MVT::v32i1;
1741 return VT.changeVectorElementTypeToInteger();
1744 /// Helper for getByValTypeAlignment to determine
1745 /// the desired ByVal argument alignment.
1746 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1749 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1750 if (VTy->getBitWidth() == 128)
1752 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1753 unsigned EltAlign = 0;
1754 getMaxByValAlign(ATy->getElementType(), EltAlign);
1755 if (EltAlign > MaxAlign)
1756 MaxAlign = EltAlign;
1757 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1758 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1759 unsigned EltAlign = 0;
1760 getMaxByValAlign(STy->getElementType(i), EltAlign);
1761 if (EltAlign > MaxAlign)
1762 MaxAlign = EltAlign;
1769 /// Return the desired alignment for ByVal aggregate
1770 /// function arguments in the caller parameter area. For X86, aggregates
1771 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1772 /// are at 4-byte boundaries.
1773 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1774 if (Subtarget->is64Bit()) {
1775 // Max of 8 and alignment of type.
1776 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1783 if (Subtarget->hasSSE1())
1784 getMaxByValAlign(Ty, Align);
1788 /// Returns the target specific optimal type for load
1789 /// and store operations as a result of memset, memcpy, and memmove
1790 /// lowering. If DstAlign is zero that means it's safe to destination
1791 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1792 /// means there isn't a need to check it against alignment requirement,
1793 /// probably because the source does not need to be loaded. If 'IsMemset' is
1794 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1795 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1796 /// source is constant so it does not need to be loaded.
1797 /// It returns EVT::Other if the type should be determined using generic
1798 /// target-independent logic.
1800 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1801 unsigned DstAlign, unsigned SrcAlign,
1802 bool IsMemset, bool ZeroMemset,
1804 MachineFunction &MF) const {
1805 const Function *F = MF.getFunction();
1806 if ((!IsMemset || ZeroMemset) &&
1807 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1808 Attribute::NoImplicitFloat)) {
1810 (Subtarget->isUnalignedMemAccessFast() ||
1811 ((DstAlign == 0 || DstAlign >= 16) &&
1812 (SrcAlign == 0 || SrcAlign >= 16)))) {
1814 if (Subtarget->hasInt256())
1816 if (Subtarget->hasFp256())
1819 if (Subtarget->hasSSE2())
1821 if (Subtarget->hasSSE1())
1823 } else if (!MemcpyStrSrc && Size >= 8 &&
1824 !Subtarget->is64Bit() &&
1825 Subtarget->hasSSE2()) {
1826 // Do not use f64 to lower memcpy if source is string constant. It's
1827 // better to use i32 to avoid the loads.
1831 if (Subtarget->is64Bit() && Size >= 8)
1836 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1838 return X86ScalarSSEf32;
1839 else if (VT == MVT::f64)
1840 return X86ScalarSSEf64;
1845 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1850 *Fast = Subtarget->isUnalignedMemAccessFast();
1854 /// Return the entry encoding for a jump table in the
1855 /// current function. The returned value is a member of the
1856 /// MachineJumpTableInfo::JTEntryKind enum.
1857 unsigned X86TargetLowering::getJumpTableEncoding() const {
1858 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1860 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1861 Subtarget->isPICStyleGOT())
1862 return MachineJumpTableInfo::EK_Custom32;
1864 // Otherwise, use the normal jump table encoding heuristics.
1865 return TargetLowering::getJumpTableEncoding();
1869 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1870 const MachineBasicBlock *MBB,
1871 unsigned uid,MCContext &Ctx) const{
1872 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1873 Subtarget->isPICStyleGOT());
1874 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1876 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1877 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1880 /// Returns relocation base for the given PIC jumptable.
1881 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1882 SelectionDAG &DAG) const {
1883 if (!Subtarget->is64Bit())
1884 // This doesn't have SDLoc associated with it, but is not really the
1885 // same as a Register.
1886 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1890 /// This returns the relocation base for the given PIC jumptable,
1891 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1892 const MCExpr *X86TargetLowering::
1893 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1894 MCContext &Ctx) const {
1895 // X86-64 uses RIP relative addressing based on the jump table label.
1896 if (Subtarget->isPICStyleRIPRel())
1897 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1899 // Otherwise, the reference is relative to the PIC base.
1900 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1903 // FIXME: Why this routine is here? Move to RegInfo!
1904 std::pair<const TargetRegisterClass*, uint8_t>
1905 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1906 const TargetRegisterClass *RRC = nullptr;
1908 switch (VT.SimpleTy) {
1910 return TargetLowering::findRepresentativeClass(VT);
1911 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1912 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1915 RRC = &X86::VR64RegClass;
1917 case MVT::f32: case MVT::f64:
1918 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1919 case MVT::v4f32: case MVT::v2f64:
1920 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1922 RRC = &X86::VR128RegClass;
1925 return std::make_pair(RRC, Cost);
1928 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1929 unsigned &Offset) const {
1930 if (!Subtarget->isTargetLinux())
1933 if (Subtarget->is64Bit()) {
1934 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1936 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1948 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1949 unsigned DestAS) const {
1950 assert(SrcAS != DestAS && "Expected different address spaces!");
1952 return SrcAS < 256 && DestAS < 256;
1955 //===----------------------------------------------------------------------===//
1956 // Return Value Calling Convention Implementation
1957 //===----------------------------------------------------------------------===//
1959 #include "X86GenCallingConv.inc"
1962 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1963 MachineFunction &MF, bool isVarArg,
1964 const SmallVectorImpl<ISD::OutputArg> &Outs,
1965 LLVMContext &Context) const {
1966 SmallVector<CCValAssign, 16> RVLocs;
1967 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1968 return CCInfo.CheckReturn(Outs, RetCC_X86);
1971 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1972 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1977 X86TargetLowering::LowerReturn(SDValue Chain,
1978 CallingConv::ID CallConv, bool isVarArg,
1979 const SmallVectorImpl<ISD::OutputArg> &Outs,
1980 const SmallVectorImpl<SDValue> &OutVals,
1981 SDLoc dl, SelectionDAG &DAG) const {
1982 MachineFunction &MF = DAG.getMachineFunction();
1983 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1985 SmallVector<CCValAssign, 16> RVLocs;
1986 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1987 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1990 SmallVector<SDValue, 6> RetOps;
1991 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1992 // Operand #1 = Bytes To Pop
1993 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1996 // Copy the result values into the output registers.
1997 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1998 CCValAssign &VA = RVLocs[i];
1999 assert(VA.isRegLoc() && "Can only return in registers!");
2000 SDValue ValToCopy = OutVals[i];
2001 EVT ValVT = ValToCopy.getValueType();
2003 // Promote values to the appropriate types.
2004 if (VA.getLocInfo() == CCValAssign::SExt)
2005 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::ZExt)
2007 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::AExt)
2009 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2010 else if (VA.getLocInfo() == CCValAssign::BCvt)
2011 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2013 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2014 "Unexpected FP-extend for return value.");
2016 // If this is x86-64, and we disabled SSE, we can't return FP values,
2017 // or SSE or MMX vectors.
2018 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2019 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2020 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2021 report_fatal_error("SSE register return with SSE disabled");
2023 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2024 // llvm-gcc has never done it right and no one has noticed, so this
2025 // should be OK for now.
2026 if (ValVT == MVT::f64 &&
2027 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2028 report_fatal_error("SSE2 register return with SSE2 disabled");
2030 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2031 // the RET instruction and handled by the FP Stackifier.
2032 if (VA.getLocReg() == X86::FP0 ||
2033 VA.getLocReg() == X86::FP1) {
2034 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2035 // change the value to the FP stack register class.
2036 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2037 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2038 RetOps.push_back(ValToCopy);
2039 // Don't emit a copytoreg.
2043 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2044 // which is returned in RAX / RDX.
2045 if (Subtarget->is64Bit()) {
2046 if (ValVT == MVT::x86mmx) {
2047 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2049 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2051 // If we don't have SSE2 available, convert to v4f32 so the generated
2052 // register is legal.
2053 if (!Subtarget->hasSSE2())
2054 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2059 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2060 Flag = Chain.getValue(1);
2061 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2064 // The x86-64 ABIs require that for returning structs by value we copy
2065 // the sret argument into %rax/%eax (depending on ABI) for the return.
2066 // Win32 requires us to put the sret argument to %eax as well.
2067 // We saved the argument into a virtual register in the entry block,
2068 // so now we copy the value out and into %rax/%eax.
2069 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2070 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2071 MachineFunction &MF = DAG.getMachineFunction();
2072 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2073 unsigned Reg = FuncInfo->getSRetReturnReg();
2075 "SRetReturnReg should have been set in LowerFormalArguments().");
2076 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2079 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2080 X86::RAX : X86::EAX;
2081 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2082 Flag = Chain.getValue(1);
2084 // RAX/EAX now acts like a return value.
2085 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2088 RetOps[0] = Chain; // Update chain.
2090 // Add the flag if we have it.
2092 RetOps.push_back(Flag);
2094 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2097 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2098 if (N->getNumValues() != 1)
2100 if (!N->hasNUsesOfValue(1, 0))
2103 SDValue TCChain = Chain;
2104 SDNode *Copy = *N->use_begin();
2105 if (Copy->getOpcode() == ISD::CopyToReg) {
2106 // If the copy has a glue operand, we conservatively assume it isn't safe to
2107 // perform a tail call.
2108 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2110 TCChain = Copy->getOperand(0);
2111 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2114 bool HasRet = false;
2115 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2117 if (UI->getOpcode() != X86ISD::RET_FLAG)
2119 // If we are returning more than one value, we can definitely
2120 // not make a tail call see PR19530
2121 if (UI->getNumOperands() > 4)
2123 if (UI->getNumOperands() == 4 &&
2124 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2137 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2138 ISD::NodeType ExtendKind) const {
2140 // TODO: Is this also valid on 32-bit?
2141 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2142 ReturnMVT = MVT::i8;
2144 ReturnMVT = MVT::i32;
2146 EVT MinVT = getRegisterType(Context, ReturnMVT);
2147 return VT.bitsLT(MinVT) ? MinVT : VT;
2150 /// Lower the result values of a call into the
2151 /// appropriate copies out of appropriate physical registers.
2154 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2155 CallingConv::ID CallConv, bool isVarArg,
2156 const SmallVectorImpl<ISD::InputArg> &Ins,
2157 SDLoc dl, SelectionDAG &DAG,
2158 SmallVectorImpl<SDValue> &InVals) const {
2160 // Assign locations to each value returned by this call.
2161 SmallVector<CCValAssign, 16> RVLocs;
2162 bool Is64Bit = Subtarget->is64Bit();
2163 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2165 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2167 // Copy all of the result registers out of their specified physreg.
2168 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2169 CCValAssign &VA = RVLocs[i];
2170 EVT CopyVT = VA.getValVT();
2172 // If this is x86-64, and we disabled SSE, we can't return FP values
2173 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2174 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2175 report_fatal_error("SSE register return with SSE disabled");
2178 // If we prefer to use the value in xmm registers, copy it out as f80 and
2179 // use a truncate to move it from fp stack reg to xmm reg.
2180 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2181 isScalarFPTypeInSSEReg(VA.getValVT()))
2184 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2185 CopyVT, InFlag).getValue(1);
2186 SDValue Val = Chain.getValue(0);
2188 if (CopyVT != VA.getValVT())
2189 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2190 // This truncation won't change the value.
2191 DAG.getIntPtrConstant(1));
2193 InFlag = Chain.getValue(2);
2194 InVals.push_back(Val);
2200 //===----------------------------------------------------------------------===//
2201 // C & StdCall & Fast Calling Convention implementation
2202 //===----------------------------------------------------------------------===//
2203 // StdCall calling convention seems to be standard for many Windows' API
2204 // routines and around. It differs from C calling convention just a little:
2205 // callee should clean up the stack, not caller. Symbols should be also
2206 // decorated in some fancy way :) It doesn't support any vector arguments.
2207 // For info on fast calling convention see Fast Calling Convention (tail call)
2208 // implementation LowerX86_32FastCCCallTo.
2210 /// CallIsStructReturn - Determines whether a call uses struct return
2212 enum StructReturnType {
2217 static StructReturnType
2218 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2220 return NotStructReturn;
2222 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2223 if (!Flags.isSRet())
2224 return NotStructReturn;
2225 if (Flags.isInReg())
2226 return RegStructReturn;
2227 return StackStructReturn;
2230 /// Determines whether a function uses struct return semantics.
2231 static StructReturnType
2232 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2234 return NotStructReturn;
2236 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2237 if (!Flags.isSRet())
2238 return NotStructReturn;
2239 if (Flags.isInReg())
2240 return RegStructReturn;
2241 return StackStructReturn;
2244 /// Make a copy of an aggregate at address specified by "Src" to address
2245 /// "Dst" with size and alignment information specified by the specific
2246 /// parameter attribute. The copy will be passed as a byval function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset >= 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3867 /// operand - by default will match for first operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3869 bool TestSecondOperand = false) {
3870 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3871 VT != MVT::v2f64 && VT != MVT::v2i64)
3874 unsigned NumElems = VT.getVectorNumElements();
3875 unsigned Lo = TestSecondOperand ? NumElems : 0;
3876 unsigned Hi = Lo + NumElems;
3878 for (unsigned i = 0; i < NumElems; ++i)
3879 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3885 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3886 /// is suitable for input to PSHUFHW.
3887 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3888 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 4; i != 8; ++i)
3897 if (!isUndefOrInRange(Mask[i], 4, 8))
3900 if (VT == MVT::v16i16) {
3901 // Lower quadword copied in order or undef.
3902 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3905 // Upper quadword shuffled.
3906 for (unsigned i = 12; i != 16; ++i)
3907 if (!isUndefOrInRange(Mask[i], 12, 16))
3914 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3915 /// is suitable for input to PSHUFLW.
3916 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3917 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 0; i != 4; ++i)
3926 if (!isUndefOrInRange(Mask[i], 0, 4))
3929 if (VT == MVT::v16i16) {
3930 // Upper quadword copied in order.
3931 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3934 // Lower quadword shuffled.
3935 for (unsigned i = 8; i != 12; ++i)
3936 if (!isUndefOrInRange(Mask[i], 8, 12))
3943 /// \brief Return true if the mask specifies a shuffle of elements that is
3944 /// suitable for input to intralane (palignr) or interlane (valign) vector
3946 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3947 unsigned NumElts = VT.getVectorNumElements();
3948 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3949 unsigned NumLaneElts = NumElts/NumLanes;
3951 // Do not handle 64-bit element shuffles with palignr.
3952 if (NumLaneElts == 2)
3955 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3957 for (i = 0; i != NumLaneElts; ++i) {
3962 // Lane is all undef, go to next lane
3963 if (i == NumLaneElts)
3966 int Start = Mask[i+l];
3968 // Make sure its in this lane in one of the sources
3969 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3970 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3973 // If not lane 0, then we must match lane 0
3974 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3977 // Correct second source to be contiguous with first source
3978 if (Start >= (int)NumElts)
3979 Start -= NumElts - NumLaneElts;
3981 // Make sure we're shifting in the right direction.
3982 if (Start <= (int)(i+l))
3987 // Check the rest of the elements to see if they are consecutive.
3988 for (++i; i != NumLaneElts; ++i) {
3989 int Idx = Mask[i+l];
3991 // Make sure its in this lane
3992 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3993 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3996 // If not lane 0, then we must match lane 0
3997 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4000 if (Idx >= (int)NumElts)
4001 Idx -= NumElts - NumLaneElts;
4003 if (!isUndefOrEqual(Idx, Start+i))
4012 /// \brief Return true if the node specifies a shuffle of elements that is
4013 /// suitable for input to PALIGNR.
4014 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4015 const X86Subtarget *Subtarget) {
4016 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4017 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4018 VT.is512BitVector())
4019 // FIXME: Add AVX512BW.
4022 return isAlignrMask(Mask, VT, false);
4025 /// \brief Return true if the node specifies a shuffle of elements that is
4026 /// suitable for input to VALIGN.
4027 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4028 const X86Subtarget *Subtarget) {
4029 // FIXME: Add AVX512VL.
4030 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4032 return isAlignrMask(Mask, VT, true);
4035 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4036 /// the two vector operands have swapped position.
4037 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4038 unsigned NumElems) {
4039 for (unsigned i = 0; i != NumElems; ++i) {
4043 else if (idx < (int)NumElems)
4044 Mask[i] = idx + NumElems;
4046 Mask[i] = idx - NumElems;
4050 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4051 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4052 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4053 /// reverse of what x86 shuffles want.
4054 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4056 unsigned NumElems = VT.getVectorNumElements();
4057 unsigned NumLanes = VT.getSizeInBits()/128;
4058 unsigned NumLaneElems = NumElems/NumLanes;
4060 if (NumLaneElems != 2 && NumLaneElems != 4)
4063 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4064 bool symetricMaskRequired =
4065 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4067 // VSHUFPSY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4072 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4074 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4075 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4077 // VSHUFPDY divides the resulting vector into 4 chunks.
4078 // The sources are also splitted into 4 chunks, and each destination
4079 // chunk must come from a different source chunk.
4081 // SRC1 => X3 X2 X1 X0
4082 // SRC2 => Y3 Y2 Y1 Y0
4084 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4086 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4087 unsigned HalfLaneElems = NumLaneElems/2;
4088 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4089 for (unsigned i = 0; i != NumLaneElems; ++i) {
4090 int Idx = Mask[i+l];
4091 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4092 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4094 // For VSHUFPSY, the mask of the second half must be the same as the
4095 // first but with the appropriate offsets. This works in the same way as
4096 // VPERMILPS works with masks.
4097 if (!symetricMaskRequired || Idx < 0)
4099 if (MaskVal[i] < 0) {
4100 MaskVal[i] = Idx - l;
4103 if ((signed)(Idx - l) != MaskVal[i])
4111 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4112 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4113 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4114 if (!VT.is128BitVector())
4117 unsigned NumElems = VT.getVectorNumElements();
4122 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4123 return isUndefOrEqual(Mask[0], 6) &&
4124 isUndefOrEqual(Mask[1], 7) &&
4125 isUndefOrEqual(Mask[2], 2) &&
4126 isUndefOrEqual(Mask[3], 3);
4129 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4130 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4132 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4133 if (!VT.is128BitVector())
4136 unsigned NumElems = VT.getVectorNumElements();
4141 return isUndefOrEqual(Mask[0], 2) &&
4142 isUndefOrEqual(Mask[1], 3) &&
4143 isUndefOrEqual(Mask[2], 2) &&
4144 isUndefOrEqual(Mask[3], 3);
4147 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4148 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4149 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4150 if (!VT.is128BitVector())
4153 unsigned NumElems = VT.getVectorNumElements();
4155 if (NumElems != 2 && NumElems != 4)
4158 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4159 if (!isUndefOrEqual(Mask[i], i + NumElems))
4162 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4163 if (!isUndefOrEqual(Mask[i], i))
4169 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4170 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4171 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4172 if (!VT.is128BitVector())
4175 unsigned NumElems = VT.getVectorNumElements();
4177 if (NumElems != 2 && NumElems != 4)
4180 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4181 if (!isUndefOrEqual(Mask[i], i))
4184 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4185 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4191 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4192 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4193 /// i. e: If all but one element come from the same vector.
4194 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4195 // TODO: Deal with AVX's VINSERTPS
4196 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4199 unsigned CorrectPosV1 = 0;
4200 unsigned CorrectPosV2 = 0;
4201 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4202 if (Mask[i] == -1) {
4210 else if (Mask[i] == i + 4)
4214 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4215 // We have 3 elements (undefs count as elements from any vector) from one
4216 // vector, and one from another.
4223 // Some special combinations that can be optimized.
4226 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4227 SelectionDAG &DAG) {
4228 MVT VT = SVOp->getSimpleValueType(0);
4231 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4234 ArrayRef<int> Mask = SVOp->getMask();
4236 // These are the special masks that may be optimized.
4237 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4238 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4239 bool MatchEvenMask = true;
4240 bool MatchOddMask = true;
4241 for (int i=0; i<8; ++i) {
4242 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4243 MatchEvenMask = false;
4244 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4245 MatchOddMask = false;
4248 if (!MatchEvenMask && !MatchOddMask)
4251 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4253 SDValue Op0 = SVOp->getOperand(0);
4254 SDValue Op1 = SVOp->getOperand(1);
4256 if (MatchEvenMask) {
4257 // Shift the second operand right to 32 bits.
4258 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4259 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4261 // Shift the first operand left to 32 bits.
4262 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4263 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4265 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4266 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4269 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4270 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4271 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4272 bool HasInt256, bool V2IsSplat = false) {
4274 assert(VT.getSizeInBits() >= 128 &&
4275 "Unsupported vector type for unpckl");
4277 unsigned NumElts = VT.getVectorNumElements();
4278 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4279 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4282 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4283 "Unsupported vector type for unpckh");
4285 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4286 unsigned NumLanes = VT.getSizeInBits()/128;
4287 unsigned NumLaneElts = NumElts/NumLanes;
4289 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4290 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4291 int BitI = Mask[l+i];
4292 int BitI1 = Mask[l+i+1];
4293 if (!isUndefOrEqual(BitI, j))
4296 if (!isUndefOrEqual(BitI1, NumElts))
4299 if (!isUndefOrEqual(BitI1, j + NumElts))
4308 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4309 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4310 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4311 bool HasInt256, bool V2IsSplat = false) {
4312 assert(VT.getSizeInBits() >= 128 &&
4313 "Unsupported vector type for unpckh");
4315 unsigned NumElts = VT.getVectorNumElements();
4316 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4317 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4320 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4321 "Unsupported vector type for unpckh");
4323 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4324 unsigned NumLanes = VT.getSizeInBits()/128;
4325 unsigned NumLaneElts = NumElts/NumLanes;
4327 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4328 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4329 int BitI = Mask[l+i];
4330 int BitI1 = Mask[l+i+1];
4331 if (!isUndefOrEqual(BitI, j))
4334 if (isUndefOrEqual(BitI1, NumElts))
4337 if (!isUndefOrEqual(BitI1, j+NumElts))
4345 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4346 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4348 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4349 unsigned NumElts = VT.getVectorNumElements();
4350 bool Is256BitVec = VT.is256BitVector();
4352 if (VT.is512BitVector())
4354 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4355 "Unsupported vector type for unpckh");
4357 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4358 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4361 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4362 // FIXME: Need a better way to get rid of this, there's no latency difference
4363 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4364 // the former later. We should also remove the "_undef" special mask.
4365 if (NumElts == 4 && Is256BitVec)
4368 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4369 // independently on 128-bit lanes.
4370 unsigned NumLanes = VT.getSizeInBits()/128;
4371 unsigned NumLaneElts = NumElts/NumLanes;
4373 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4374 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4375 int BitI = Mask[l+i];
4376 int BitI1 = Mask[l+i+1];
4378 if (!isUndefOrEqual(BitI, j))
4380 if (!isUndefOrEqual(BitI1, j))
4388 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4389 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4391 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4392 unsigned NumElts = VT.getVectorNumElements();
4394 if (VT.is512BitVector())
4397 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4398 "Unsupported vector type for unpckh");
4400 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4401 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4404 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4405 // independently on 128-bit lanes.
4406 unsigned NumLanes = VT.getSizeInBits()/128;
4407 unsigned NumLaneElts = NumElts/NumLanes;
4409 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4410 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4411 int BitI = Mask[l+i];
4412 int BitI1 = Mask[l+i+1];
4413 if (!isUndefOrEqual(BitI, j))
4415 if (!isUndefOrEqual(BitI1, j))
4422 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4423 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4424 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4425 if (!VT.is512BitVector())
4428 unsigned NumElts = VT.getVectorNumElements();
4429 unsigned HalfSize = NumElts/2;
4430 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4431 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4436 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4437 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4445 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4446 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4447 /// MOVSD, and MOVD, i.e. setting the lowest element.
4448 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4449 if (VT.getVectorElementType().getSizeInBits() < 32)
4451 if (!VT.is128BitVector())
4454 unsigned NumElts = VT.getVectorNumElements();
4456 if (!isUndefOrEqual(Mask[0], NumElts))
4459 for (unsigned i = 1; i != NumElts; ++i)
4460 if (!isUndefOrEqual(Mask[i], i))
4466 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4467 /// as permutations between 128-bit chunks or halves. As an example: this
4469 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4470 /// The first half comes from the second half of V1 and the second half from the
4471 /// the second half of V2.
4472 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4473 if (!HasFp256 || !VT.is256BitVector())
4476 // The shuffle result is divided into half A and half B. In total the two
4477 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4478 // B must come from C, D, E or F.
4479 unsigned HalfSize = VT.getVectorNumElements()/2;
4480 bool MatchA = false, MatchB = false;
4482 // Check if A comes from one of C, D, E, F.
4483 for (unsigned Half = 0; Half != 4; ++Half) {
4484 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4490 // Check if B comes from one of C, D, E, F.
4491 for (unsigned Half = 0; Half != 4; ++Half) {
4492 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4498 return MatchA && MatchB;
4501 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4502 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4503 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4504 MVT VT = SVOp->getSimpleValueType(0);
4506 unsigned HalfSize = VT.getVectorNumElements()/2;
4508 unsigned FstHalf = 0, SndHalf = 0;
4509 for (unsigned i = 0; i < HalfSize; ++i) {
4510 if (SVOp->getMaskElt(i) > 0) {
4511 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4515 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4516 if (SVOp->getMaskElt(i) > 0) {
4517 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4522 return (FstHalf | (SndHalf << 4));
4525 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4526 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4527 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4531 unsigned NumElts = VT.getVectorNumElements();
4533 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4534 for (unsigned i = 0; i != NumElts; ++i) {
4537 Imm8 |= Mask[i] << (i*2);
4542 unsigned LaneSize = 4;
4543 SmallVector<int, 4> MaskVal(LaneSize, -1);
4545 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4546 for (unsigned i = 0; i != LaneSize; ++i) {
4547 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4551 if (MaskVal[i] < 0) {
4552 MaskVal[i] = Mask[i+l] - l;
4553 Imm8 |= MaskVal[i] << (i*2);
4556 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4563 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4564 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4565 /// Note that VPERMIL mask matching is different depending whether theunderlying
4566 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4567 /// to the same elements of the low, but to the higher half of the source.
4568 /// In VPERMILPD the two lanes could be shuffled independently of each other
4569 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4570 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4571 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4572 if (VT.getSizeInBits() < 256 || EltSize < 32)
4574 bool symetricMaskRequired = (EltSize == 32);
4575 unsigned NumElts = VT.getVectorNumElements();
4577 unsigned NumLanes = VT.getSizeInBits()/128;
4578 unsigned LaneSize = NumElts/NumLanes;
4579 // 2 or 4 elements in one lane
4581 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4582 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4583 for (unsigned i = 0; i != LaneSize; ++i) {
4584 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4586 if (symetricMaskRequired) {
4587 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4588 ExpectedMaskVal[i] = Mask[i+l] - l;
4591 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4599 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4600 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4601 /// element of vector 2 and the other elements to come from vector 1 in order.
4602 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4603 bool V2IsSplat = false, bool V2IsUndef = false) {
4604 if (!VT.is128BitVector())
4607 unsigned NumOps = VT.getVectorNumElements();
4608 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4611 if (!isUndefOrEqual(Mask[0], 0))
4614 for (unsigned i = 1; i != NumOps; ++i)
4615 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4616 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4617 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4623 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4624 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4625 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4626 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4627 const X86Subtarget *Subtarget) {
4628 if (!Subtarget->hasSSE3())
4631 unsigned NumElems = VT.getVectorNumElements();
4633 if ((VT.is128BitVector() && NumElems != 4) ||
4634 (VT.is256BitVector() && NumElems != 8) ||
4635 (VT.is512BitVector() && NumElems != 16))
4638 // "i+1" is the value the indexed mask element must have
4639 for (unsigned i = 0; i != NumElems; i += 2)
4640 if (!isUndefOrEqual(Mask[i], i+1) ||
4641 !isUndefOrEqual(Mask[i+1], i+1))
4647 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4648 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4649 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4650 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4651 const X86Subtarget *Subtarget) {
4652 if (!Subtarget->hasSSE3())
4655 unsigned NumElems = VT.getVectorNumElements();
4657 if ((VT.is128BitVector() && NumElems != 4) ||
4658 (VT.is256BitVector() && NumElems != 8) ||
4659 (VT.is512BitVector() && NumElems != 16))
4662 // "i" is the value the indexed mask element must have
4663 for (unsigned i = 0; i != NumElems; i += 2)
4664 if (!isUndefOrEqual(Mask[i], i) ||
4665 !isUndefOrEqual(Mask[i+1], i))
4671 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4672 /// specifies a shuffle of elements that is suitable for input to 256-bit
4673 /// version of MOVDDUP.
4674 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4675 if (!HasFp256 || !VT.is256BitVector())
4678 unsigned NumElts = VT.getVectorNumElements();
4682 for (unsigned i = 0; i != NumElts/2; ++i)
4683 if (!isUndefOrEqual(Mask[i], 0))
4685 for (unsigned i = NumElts/2; i != NumElts; ++i)
4686 if (!isUndefOrEqual(Mask[i], NumElts/2))
4691 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4692 /// specifies a shuffle of elements that is suitable for input to 128-bit
4693 /// version of MOVDDUP.
4694 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4695 if (!VT.is128BitVector())
4698 unsigned e = VT.getVectorNumElements() / 2;
4699 for (unsigned i = 0; i != e; ++i)
4700 if (!isUndefOrEqual(Mask[i], i))
4702 for (unsigned i = 0; i != e; ++i)
4703 if (!isUndefOrEqual(Mask[e+i], i))
4708 /// isVEXTRACTIndex - Return true if the specified
4709 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4710 /// suitable for instruction that extract 128 or 256 bit vectors
4711 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4712 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4713 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4716 // The index should be aligned on a vecWidth-bit boundary.
4718 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4720 MVT VT = N->getSimpleValueType(0);
4721 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4722 bool Result = (Index * ElSize) % vecWidth == 0;
4727 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4728 /// operand specifies a subvector insert that is suitable for input to
4729 /// insertion of 128 or 256-bit subvectors
4730 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4731 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4732 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4734 // The index should be aligned on a vecWidth-bit boundary.
4736 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4738 MVT VT = N->getSimpleValueType(0);
4739 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4740 bool Result = (Index * ElSize) % vecWidth == 0;
4745 bool X86::isVINSERT128Index(SDNode *N) {
4746 return isVINSERTIndex(N, 128);
4749 bool X86::isVINSERT256Index(SDNode *N) {
4750 return isVINSERTIndex(N, 256);
4753 bool X86::isVEXTRACT128Index(SDNode *N) {
4754 return isVEXTRACTIndex(N, 128);
4757 bool X86::isVEXTRACT256Index(SDNode *N) {
4758 return isVEXTRACTIndex(N, 256);
4761 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4762 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4763 /// Handles 128-bit and 256-bit.
4764 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4765 MVT VT = N->getSimpleValueType(0);
4767 assert((VT.getSizeInBits() >= 128) &&
4768 "Unsupported vector type for PSHUF/SHUFP");
4770 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4771 // independently on 128-bit lanes.
4772 unsigned NumElts = VT.getVectorNumElements();
4773 unsigned NumLanes = VT.getSizeInBits()/128;
4774 unsigned NumLaneElts = NumElts/NumLanes;
4776 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4777 "Only supports 2, 4 or 8 elements per lane");
4779 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4781 for (unsigned i = 0; i != NumElts; ++i) {
4782 int Elt = N->getMaskElt(i);
4783 if (Elt < 0) continue;
4784 Elt &= NumLaneElts - 1;
4785 unsigned ShAmt = (i << Shift) % 8;
4786 Mask |= Elt << ShAmt;
4792 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4793 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4794 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4795 MVT VT = N->getSimpleValueType(0);
4797 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4798 "Unsupported vector type for PSHUFHW");
4800 unsigned NumElts = VT.getVectorNumElements();
4803 for (unsigned l = 0; l != NumElts; l += 8) {
4804 // 8 nodes per lane, but we only care about the last 4.
4805 for (unsigned i = 0; i < 4; ++i) {
4806 int Elt = N->getMaskElt(l+i+4);
4807 if (Elt < 0) continue;
4808 Elt &= 0x3; // only 2-bits.
4809 Mask |= Elt << (i * 2);
4816 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4817 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4818 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4819 MVT VT = N->getSimpleValueType(0);
4821 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4822 "Unsupported vector type for PSHUFHW");
4824 unsigned NumElts = VT.getVectorNumElements();
4827 for (unsigned l = 0; l != NumElts; l += 8) {
4828 // 8 nodes per lane, but we only care about the first 4.
4829 for (unsigned i = 0; i < 4; ++i) {
4830 int Elt = N->getMaskElt(l+i);
4831 if (Elt < 0) continue;
4832 Elt &= 0x3; // only 2-bits
4833 Mask |= Elt << (i * 2);
4840 /// \brief Return the appropriate immediate to shuffle the specified
4841 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4842 /// VALIGN (if Interlane is true) instructions.
4843 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4845 MVT VT = SVOp->getSimpleValueType(0);
4846 unsigned EltSize = InterLane ? 1 :
4847 VT.getVectorElementType().getSizeInBits() >> 3;
4849 unsigned NumElts = VT.getVectorNumElements();
4850 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4851 unsigned NumLaneElts = NumElts/NumLanes;
4855 for (i = 0; i != NumElts; ++i) {
4856 Val = SVOp->getMaskElt(i);
4860 if (Val >= (int)NumElts)
4861 Val -= NumElts - NumLaneElts;
4863 assert(Val - i > 0 && "PALIGNR imm should be positive");
4864 return (Val - i) * EltSize;
4867 /// \brief Return the appropriate immediate to shuffle the specified
4868 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4869 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4870 return getShuffleAlignrImmediate(SVOp, false);
4873 /// \brief Return the appropriate immediate to shuffle the specified
4874 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4875 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4876 return getShuffleAlignrImmediate(SVOp, true);
4880 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4881 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4882 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4883 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4886 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4888 MVT VecVT = N->getOperand(0).getSimpleValueType();
4889 MVT ElVT = VecVT.getVectorElementType();
4891 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4892 return Index / NumElemsPerChunk;
4895 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4896 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4897 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4898 llvm_unreachable("Illegal insert subvector for VINSERT");
4901 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4903 MVT VecVT = N->getSimpleValueType(0);
4904 MVT ElVT = VecVT.getVectorElementType();
4906 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4907 return Index / NumElemsPerChunk;
4910 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4911 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4912 /// and VINSERTI128 instructions.
4913 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4914 return getExtractVEXTRACTImmediate(N, 128);
4917 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4918 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4919 /// and VINSERTI64x4 instructions.
4920 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4921 return getExtractVEXTRACTImmediate(N, 256);
4924 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4925 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4926 /// and VINSERTI128 instructions.
4927 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4928 return getInsertVINSERTImmediate(N, 128);
4931 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4932 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4933 /// and VINSERTI64x4 instructions.
4934 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4935 return getInsertVINSERTImmediate(N, 256);
4938 /// isZero - Returns true if Elt is a constant integer zero
4939 static bool isZero(SDValue V) {
4940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4941 return C && C->isNullValue();
4944 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4946 bool X86::isZeroNode(SDValue Elt) {
4949 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4950 return CFP->getValueAPF().isPosZero();
4954 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4955 /// match movhlps. The lower half elements should come from upper half of
4956 /// V1 (and in order), and the upper half elements should come from the upper
4957 /// half of V2 (and in order).
4958 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4959 if (!VT.is128BitVector())
4961 if (VT.getVectorNumElements() != 4)
4963 for (unsigned i = 0, e = 2; i != e; ++i)
4964 if (!isUndefOrEqual(Mask[i], i+2))
4966 for (unsigned i = 2; i != 4; ++i)
4967 if (!isUndefOrEqual(Mask[i], i+4))
4972 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4973 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4975 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4976 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4978 N = N->getOperand(0).getNode();
4979 if (!ISD::isNON_EXTLoad(N))
4982 *LD = cast<LoadSDNode>(N);
4986 // Test whether the given value is a vector value which will be legalized
4988 static bool WillBeConstantPoolLoad(SDNode *N) {
4989 if (N->getOpcode() != ISD::BUILD_VECTOR)
4992 // Check for any non-constant elements.
4993 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4994 switch (N->getOperand(i).getNode()->getOpcode()) {
4996 case ISD::ConstantFP:
5003 // Vectors of all-zeros and all-ones are materialized with special
5004 // instructions rather than being loaded.
5005 return !ISD::isBuildVectorAllZeros(N) &&
5006 !ISD::isBuildVectorAllOnes(N);
5009 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5010 /// match movlp{s|d}. The lower half elements should come from lower half of
5011 /// V1 (and in order), and the upper half elements should come from the upper
5012 /// half of V2 (and in order). And since V1 will become the source of the
5013 /// MOVLP, it must be either a vector load or a scalar load to vector.
5014 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5015 ArrayRef<int> Mask, MVT VT) {
5016 if (!VT.is128BitVector())
5019 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5021 // Is V2 is a vector load, don't do this transformation. We will try to use
5022 // load folding shufps op.
5023 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5026 unsigned NumElems = VT.getVectorNumElements();
5028 if (NumElems != 2 && NumElems != 4)
5030 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5031 if (!isUndefOrEqual(Mask[i], i))
5033 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5034 if (!isUndefOrEqual(Mask[i], i+NumElems))
5039 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5040 /// to an zero vector.
5041 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5042 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5043 SDValue V1 = N->getOperand(0);
5044 SDValue V2 = N->getOperand(1);
5045 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5046 for (unsigned i = 0; i != NumElems; ++i) {
5047 int Idx = N->getMaskElt(i);
5048 if (Idx >= (int)NumElems) {
5049 unsigned Opc = V2.getOpcode();
5050 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5052 if (Opc != ISD::BUILD_VECTOR ||
5053 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5055 } else if (Idx >= 0) {
5056 unsigned Opc = V1.getOpcode();
5057 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5059 if (Opc != ISD::BUILD_VECTOR ||
5060 !X86::isZeroNode(V1.getOperand(Idx)))
5067 /// getZeroVector - Returns a vector of specified type with all zero elements.
5069 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5070 SelectionDAG &DAG, SDLoc dl) {
5071 assert(VT.isVector() && "Expected a vector type");
5073 // Always build SSE zero vectors as <4 x i32> bitcasted
5074 // to their dest type. This ensures they get CSE'd.
5076 if (VT.is128BitVector()) { // SSE
5077 if (Subtarget->hasSSE2()) { // SSE2
5078 SDValue Cst = DAG.getConstant(0, MVT::i32);
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5081 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5082 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5084 } else if (VT.is256BitVector()) { // AVX
5085 if (Subtarget->hasInt256()) { // AVX2
5086 SDValue Cst = DAG.getConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5088 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5090 // 256-bit logic and arithmetic instructions in AVX are all
5091 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5092 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5093 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5094 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5096 } else if (VT.is512BitVector()) { // AVX-512
5097 SDValue Cst = DAG.getConstant(0, MVT::i32);
5098 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5099 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5100 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5101 } else if (VT.getScalarType() == MVT::i1) {
5102 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5103 SDValue Cst = DAG.getConstant(0, MVT::i1);
5104 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5105 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5107 llvm_unreachable("Unexpected vector type");
5109 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5112 /// getOnesVector - Returns a vector of specified type with all bits set.
5113 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5114 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5115 /// Then bitcast to their original type, ensuring they get CSE'd.
5116 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5118 assert(VT.isVector() && "Expected a vector type");
5120 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5122 if (VT.is256BitVector()) {
5123 if (HasInt256) { // AVX2
5124 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5125 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5128 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5130 } else if (VT.is128BitVector()) {
5131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5133 llvm_unreachable("Unexpected vector type");
5135 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5138 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5139 /// that point to V2 points to its first element.
5140 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5141 for (unsigned i = 0; i != NumElems; ++i) {
5142 if (Mask[i] > (int)NumElems) {
5148 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5149 /// operation of specified width.
5150 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 Mask.push_back(NumElems);
5155 for (unsigned i = 1; i != NumElems; ++i)
5157 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5160 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5161 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5163 unsigned NumElems = VT.getVectorNumElements();
5164 SmallVector<int, 8> Mask;
5165 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5167 Mask.push_back(i + NumElems);
5169 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5172 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5173 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5175 unsigned NumElems = VT.getVectorNumElements();
5176 SmallVector<int, 8> Mask;
5177 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5178 Mask.push_back(i + Half);
5179 Mask.push_back(i + NumElems + Half);
5181 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5184 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5185 // a generic shuffle instruction because the target has no such instructions.
5186 // Generate shuffles which repeat i16 and i8 several times until they can be
5187 // represented by v4f32 and then be manipulated by target suported shuffles.
5188 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5189 MVT VT = V.getSimpleValueType();
5190 int NumElems = VT.getVectorNumElements();
5193 while (NumElems > 4) {
5194 if (EltNo < NumElems/2) {
5195 V = getUnpackl(DAG, dl, VT, V, V);
5197 V = getUnpackh(DAG, dl, VT, V, V);
5198 EltNo -= NumElems/2;
5205 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5206 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5207 MVT VT = V.getSimpleValueType();
5210 if (VT.is128BitVector()) {
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5212 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5213 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5215 } else if (VT.is256BitVector()) {
5216 // To use VPERMILPS to splat scalars, the second half of indicies must
5217 // refer to the higher part, which is a duplication of the lower one,
5218 // because VPERMILPS can only handle in-lane permutations.
5219 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5220 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5222 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5223 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5226 llvm_unreachable("Vector size not supported");
5228 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5231 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5232 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5233 MVT SrcVT = SV->getSimpleValueType(0);
5234 SDValue V1 = SV->getOperand(0);
5237 int EltNo = SV->getSplatIndex();
5238 int NumElems = SrcVT.getVectorNumElements();
5239 bool Is256BitVec = SrcVT.is256BitVector();
5241 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5242 "Unknown how to promote splat for type");
5244 // Extract the 128-bit part containing the splat element and update
5245 // the splat element index when it refers to the higher register.
5247 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5248 if (EltNo >= NumElems/2)
5249 EltNo -= NumElems/2;
5252 // All i16 and i8 vector types can't be used directly by a generic shuffle
5253 // instruction because the target has no such instruction. Generate shuffles
5254 // which repeat i16 and i8 several times until they fit in i32, and then can
5255 // be manipulated by target suported shuffles.
5256 MVT EltVT = SrcVT.getVectorElementType();
5257 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5258 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5260 // Recreate the 256-bit vector and place the same 128-bit vector
5261 // into the low and high part. This is necessary because we want
5262 // to use VPERM* to shuffle the vectors
5264 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5267 return getLegalSplat(DAG, V1, EltNo);
5270 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5271 /// vector of zero or undef vector. This produces a shuffle where the low
5272 /// element of V2 is swizzled into the zero/undef vector, landing at element
5273 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5274 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5276 const X86Subtarget *Subtarget,
5277 SelectionDAG &DAG) {
5278 MVT VT = V2.getSimpleValueType();
5280 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5281 unsigned NumElems = VT.getVectorNumElements();
5282 SmallVector<int, 16> MaskVec;
5283 for (unsigned i = 0; i != NumElems; ++i)
5284 // If this is the insertion idx, put the low elt of V2 here.
5285 MaskVec.push_back(i == Idx ? NumElems : i);
5286 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5289 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5290 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5291 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5292 /// shuffles which use a single input multiple times, and in those cases it will
5293 /// adjust the mask to only have indices within that single input.
5294 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5295 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5296 unsigned NumElems = VT.getVectorNumElements();
5300 bool IsFakeUnary = false;
5301 switch(N->getOpcode()) {
5302 case X86ISD::BLENDI:
5303 ImmN = N->getOperand(N->getNumOperands()-1);
5304 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5307 ImmN = N->getOperand(N->getNumOperands()-1);
5308 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKH:
5312 DecodeUNPCKHMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::UNPCKL:
5316 DecodeUNPCKLMask(VT, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVHLPS:
5320 DecodeMOVHLPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::MOVLHPS:
5324 DecodeMOVLHPSMask(NumElems, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::PALIGNR:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 case X86ISD::PSHUFD:
5332 case X86ISD::VPERMILPI:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFHW:
5338 ImmN = N->getOperand(N->getNumOperands()-1);
5339 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFLW:
5343 ImmN = N->getOperand(N->getNumOperands()-1);
5344 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5347 case X86ISD::PSHUFB: {
5349 SDValue MaskNode = N->getOperand(1);
5350 while (MaskNode->getOpcode() == ISD::BITCAST)
5351 MaskNode = MaskNode->getOperand(0);
5353 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5354 // If we have a build-vector, then things are easy.
5355 EVT VT = MaskNode.getValueType();
5356 assert(VT.isVector() &&
5357 "Can't produce a non-vector with a build_vector!");
5358 if (!VT.isInteger())
5361 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5363 SmallVector<uint64_t, 32> RawMask;
5364 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5365 SDValue Op = MaskNode->getOperand(i);
5366 if (Op->getOpcode() == ISD::UNDEF) {
5367 RawMask.push_back((uint64_t)SM_SentinelUndef);
5370 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5373 APInt MaskElement = CN->getAPIntValue();
5375 // We now have to decode the element which could be any integer size and
5376 // extract each byte of it.
5377 for (int j = 0; j < NumBytesPerElement; ++j) {
5378 // Note that this is x86 and so always little endian: the low byte is
5379 // the first byte of the mask.
5380 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5381 MaskElement = MaskElement.lshr(8);
5384 DecodePSHUFBMask(RawMask, Mask);
5388 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5392 SDValue Ptr = MaskLoad->getBasePtr();
5393 if (Ptr->getOpcode() == X86ISD::Wrapper)
5394 Ptr = Ptr->getOperand(0);
5396 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5397 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5400 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5401 // FIXME: Support AVX-512 here.
5402 Type *Ty = C->getType();
5403 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5404 Ty->getVectorNumElements() != 32))
5407 DecodePSHUFBMask(C, Mask);
5413 case X86ISD::VPERMI:
5414 ImmN = N->getOperand(N->getNumOperands()-1);
5415 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5419 case X86ISD::MOVSD: {
5420 // The index 0 always comes from the first element of the second source,
5421 // this is why MOVSS and MOVSD are used in the first place. The other
5422 // elements come from the other positions of the first source vector
5423 Mask.push_back(NumElems);
5424 for (unsigned i = 1; i != NumElems; ++i) {
5429 case X86ISD::VPERM2X128:
5430 ImmN = N->getOperand(N->getNumOperands()-1);
5431 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5432 if (Mask.empty()) return false;
5434 case X86ISD::MOVSLDUP:
5435 DecodeMOVSLDUPMask(VT, Mask);
5437 case X86ISD::MOVSHDUP:
5438 DecodeMOVSHDUPMask(VT, Mask);
5440 case X86ISD::MOVDDUP:
5441 case X86ISD::MOVLHPD:
5442 case X86ISD::MOVLPD:
5443 case X86ISD::MOVLPS:
5444 // Not yet implemented
5446 default: llvm_unreachable("unknown target shuffle node");
5449 // If we have a fake unary shuffle, the shuffle mask is spread across two
5450 // inputs that are actually the same node. Re-map the mask to always point
5451 // into the first input.
5454 if (M >= (int)Mask.size())
5460 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5461 /// element of the result of the vector shuffle.
5462 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5465 return SDValue(); // Limit search depth.
5467 SDValue V = SDValue(N, 0);
5468 EVT VT = V.getValueType();
5469 unsigned Opcode = V.getOpcode();
5471 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5472 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5473 int Elt = SV->getMaskElt(Index);
5476 return DAG.getUNDEF(VT.getVectorElementType());
5478 unsigned NumElems = VT.getVectorNumElements();
5479 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5480 : SV->getOperand(1);
5481 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5484 // Recurse into target specific vector shuffles to find scalars.
5485 if (isTargetShuffle(Opcode)) {
5486 MVT ShufVT = V.getSimpleValueType();
5487 unsigned NumElems = ShufVT.getVectorNumElements();
5488 SmallVector<int, 16> ShuffleMask;
5491 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5494 int Elt = ShuffleMask[Index];
5496 return DAG.getUNDEF(ShufVT.getVectorElementType());
5498 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5500 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5504 // Actual nodes that may contain scalar elements
5505 if (Opcode == ISD::BITCAST) {
5506 V = V.getOperand(0);
5507 EVT SrcVT = V.getValueType();
5508 unsigned NumElems = VT.getVectorNumElements();
5510 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5514 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5515 return (Index == 0) ? V.getOperand(0)
5516 : DAG.getUNDEF(VT.getVectorElementType());
5518 if (V.getOpcode() == ISD::BUILD_VECTOR)
5519 return V.getOperand(Index);
5524 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5525 /// shuffle operation which come from a consecutively from a zero. The
5526 /// search can start in two different directions, from left or right.
5527 /// We count undefs as zeros until PreferredNum is reached.
5528 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5529 unsigned NumElems, bool ZerosFromLeft,
5531 unsigned PreferredNum = -1U) {
5532 unsigned NumZeros = 0;
5533 for (unsigned i = 0; i != NumElems; ++i) {
5534 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5535 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5539 if (X86::isZeroNode(Elt))
5541 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5542 NumZeros = std::min(NumZeros + 1, PreferredNum);
5550 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5551 /// correspond consecutively to elements from one of the vector operands,
5552 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5554 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5555 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5556 unsigned NumElems, unsigned &OpNum) {
5557 bool SeenV1 = false;
5558 bool SeenV2 = false;
5560 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5561 int Idx = SVOp->getMaskElt(i);
5562 // Ignore undef indicies
5566 if (Idx < (int)NumElems)
5571 // Only accept consecutive elements from the same vector
5572 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5576 OpNum = SeenV1 ? 0 : 1;
5580 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5581 /// logical left shift of a vector.
5582 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5583 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5585 SVOp->getSimpleValueType(0).getVectorNumElements();
5586 unsigned NumZeros = getNumOfConsecutiveZeros(
5587 SVOp, NumElems, false /* check zeros from right */, DAG,
5588 SVOp->getMaskElt(0));
5594 // Considering the elements in the mask that are not consecutive zeros,
5595 // check if they consecutively come from only one of the source vectors.
5597 // V1 = {X, A, B, C} 0
5599 // vector_shuffle V1, V2 <1, 2, 3, X>
5601 if (!isShuffleMaskConsecutive(SVOp,
5602 0, // Mask Start Index
5603 NumElems-NumZeros, // Mask End Index(exclusive)
5604 NumZeros, // Where to start looking in the src vector
5605 NumElems, // Number of elements in vector
5606 OpSrc)) // Which source operand ?
5611 ShVal = SVOp->getOperand(OpSrc);
5615 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5616 /// logical left shift of a vector.
5617 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5618 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5620 SVOp->getSimpleValueType(0).getVectorNumElements();
5621 unsigned NumZeros = getNumOfConsecutiveZeros(
5622 SVOp, NumElems, true /* check zeros from left */, DAG,
5623 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5629 // Considering the elements in the mask that are not consecutive zeros,
5630 // check if they consecutively come from only one of the source vectors.
5632 // 0 { A, B, X, X } = V2
5634 // vector_shuffle V1, V2 <X, X, 4, 5>
5636 if (!isShuffleMaskConsecutive(SVOp,
5637 NumZeros, // Mask Start Index
5638 NumElems, // Mask End Index(exclusive)
5639 0, // Where to start looking in the src vector
5640 NumElems, // Number of elements in vector
5641 OpSrc)) // Which source operand ?
5646 ShVal = SVOp->getOperand(OpSrc);
5650 /// isVectorShift - Returns true if the shuffle can be implemented as a
5651 /// logical left or right shift of a vector.
5652 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5653 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5654 // Although the logic below support any bitwidth size, there are no
5655 // shift instructions which handle more than 128-bit vectors.
5656 if (!SVOp->getSimpleValueType(0).is128BitVector())
5659 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5660 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5666 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5668 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5669 unsigned NumNonZero, unsigned NumZero,
5671 const X86Subtarget* Subtarget,
5672 const TargetLowering &TLI) {
5679 for (unsigned i = 0; i < 16; ++i) {
5680 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5681 if (ThisIsNonZero && First) {
5683 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5685 V = DAG.getUNDEF(MVT::v8i16);
5690 SDValue ThisElt, LastElt;
5691 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5692 if (LastIsNonZero) {
5693 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5694 MVT::i16, Op.getOperand(i-1));
5696 if (ThisIsNonZero) {
5697 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5698 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5699 ThisElt, DAG.getConstant(8, MVT::i8));
5701 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5705 if (ThisElt.getNode())
5706 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5707 DAG.getIntPtrConstant(i/2));
5711 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5714 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5716 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5717 unsigned NumNonZero, unsigned NumZero,
5719 const X86Subtarget* Subtarget,
5720 const TargetLowering &TLI) {
5727 for (unsigned i = 0; i < 8; ++i) {
5728 bool isNonZero = (NonZeros & (1 << i)) != 0;
5732 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5734 V = DAG.getUNDEF(MVT::v8i16);
5737 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5738 MVT::v8i16, V, Op.getOperand(i),
5739 DAG.getIntPtrConstant(i));
5746 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5747 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5748 const X86Subtarget *Subtarget,
5749 const TargetLowering &TLI) {
5750 // Find all zeroable elements.
5752 for (int i=0; i < 4; ++i) {
5753 SDValue Elt = Op->getOperand(i);
5754 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5756 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5757 [](bool M) { return !M; }) > 1 &&
5758 "We expect at least two non-zero elements!");
5760 // We only know how to deal with build_vector nodes where elements are either
5761 // zeroable or extract_vector_elt with constant index.
5762 SDValue FirstNonZero;
5763 unsigned FirstNonZeroIdx;
5764 for (unsigned i=0; i < 4; ++i) {
5767 SDValue Elt = Op->getOperand(i);
5768 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5769 !isa<ConstantSDNode>(Elt.getOperand(1)))
5771 // Make sure that this node is extracting from a 128-bit vector.
5772 MVT VT = Elt.getOperand(0).getSimpleValueType();
5773 if (!VT.is128BitVector())
5775 if (!FirstNonZero.getNode()) {
5777 FirstNonZeroIdx = i;
5781 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5782 SDValue V1 = FirstNonZero.getOperand(0);
5783 MVT VT = V1.getSimpleValueType();
5785 // See if this build_vector can be lowered as a blend with zero.
5787 unsigned EltMaskIdx, EltIdx;
5789 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5790 if (Zeroable[EltIdx]) {
5791 // The zero vector will be on the right hand side.
5792 Mask[EltIdx] = EltIdx+4;
5796 Elt = Op->getOperand(EltIdx);
5797 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5798 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5799 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5801 Mask[EltIdx] = EltIdx;
5805 // Let the shuffle legalizer deal with blend operations.
5806 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5807 if (V1.getSimpleValueType() != VT)
5808 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5809 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5812 // See if we can lower this build_vector to a INSERTPS.
5813 if (!Subtarget->hasSSE41())
5816 SDValue V2 = Elt.getOperand(0);
5817 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5820 bool CanFold = true;
5821 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5825 SDValue Current = Op->getOperand(i);
5826 SDValue SrcVector = Current->getOperand(0);
5829 CanFold = SrcVector == V1 &&
5830 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5836 assert(V1.getNode() && "Expected at least two non-zero elements!");
5837 if (V1.getSimpleValueType() != MVT::v4f32)
5838 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5839 if (V2.getSimpleValueType() != MVT::v4f32)
5840 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5842 // Ok, we can emit an INSERTPS instruction.
5844 for (int i = 0; i < 4; ++i)
5848 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5849 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5850 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5851 DAG.getIntPtrConstant(InsertPSMask));
5852 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5855 /// getVShift - Return a vector logical shift node.
5857 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5858 unsigned NumBits, SelectionDAG &DAG,
5859 const TargetLowering &TLI, SDLoc dl) {
5860 assert(VT.is128BitVector() && "Unknown type for VShift");
5861 EVT ShVT = MVT::v2i64;
5862 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5863 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5864 return DAG.getNode(ISD::BITCAST, dl, VT,
5865 DAG.getNode(Opc, dl, ShVT, SrcOp,
5866 DAG.getConstant(NumBits,
5867 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5871 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5873 // Check if the scalar load can be widened into a vector load. And if
5874 // the address is "base + cst" see if the cst can be "absorbed" into
5875 // the shuffle mask.
5876 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5877 SDValue Ptr = LD->getBasePtr();
5878 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5880 EVT PVT = LD->getValueType(0);
5881 if (PVT != MVT::i32 && PVT != MVT::f32)
5886 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5887 FI = FINode->getIndex();
5889 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5890 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5891 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5892 Offset = Ptr.getConstantOperandVal(1);
5893 Ptr = Ptr.getOperand(0);
5898 // FIXME: 256-bit vector instructions don't require a strict alignment,
5899 // improve this code to support it better.
5900 unsigned RequiredAlign = VT.getSizeInBits()/8;
5901 SDValue Chain = LD->getChain();
5902 // Make sure the stack object alignment is at least 16 or 32.
5903 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5904 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5905 if (MFI->isFixedObjectIndex(FI)) {
5906 // Can't change the alignment. FIXME: It's possible to compute
5907 // the exact stack offset and reference FI + adjust offset instead.
5908 // If someone *really* cares about this. That's the way to implement it.
5911 MFI->setObjectAlignment(FI, RequiredAlign);
5915 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5916 // Ptr + (Offset & ~15).
5919 if ((Offset % RequiredAlign) & 3)
5921 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5923 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5924 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5926 int EltNo = (Offset - StartOffset) >> 2;
5927 unsigned NumElems = VT.getVectorNumElements();
5929 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5930 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5931 LD->getPointerInfo().getWithOffset(StartOffset),
5932 false, false, false, 0);
5934 SmallVector<int, 8> Mask;
5935 for (unsigned i = 0; i != NumElems; ++i)
5936 Mask.push_back(EltNo);
5938 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5944 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5945 /// vector of type 'VT', see if the elements can be replaced by a single large
5946 /// load which has the same value as a build_vector whose operands are 'elts'.
5948 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5950 /// FIXME: we'd also like to handle the case where the last elements are zero
5951 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5952 /// There's even a handy isZeroNode for that purpose.
5953 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5954 SDLoc &DL, SelectionDAG &DAG,
5955 bool isAfterLegalize) {
5956 EVT EltVT = VT.getVectorElementType();
5957 unsigned NumElems = Elts.size();
5959 LoadSDNode *LDBase = nullptr;
5960 unsigned LastLoadedElt = -1U;
5962 // For each element in the initializer, see if we've found a load or an undef.
5963 // If we don't find an initial load element, or later load elements are
5964 // non-consecutive, bail out.
5965 for (unsigned i = 0; i < NumElems; ++i) {
5966 SDValue Elt = Elts[i];
5968 if (!Elt.getNode() ||
5969 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5972 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5974 LDBase = cast<LoadSDNode>(Elt.getNode());
5978 if (Elt.getOpcode() == ISD::UNDEF)
5981 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5982 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5987 // If we have found an entire vector of loads and undefs, then return a large
5988 // load of the entire vector width starting at the base pointer. If we found
5989 // consecutive loads for the low half, generate a vzext_load node.
5990 if (LastLoadedElt == NumElems - 1) {
5992 if (isAfterLegalize &&
5993 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5996 SDValue NewLd = SDValue();
5998 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5999 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6000 LDBase->getPointerInfo(),
6001 LDBase->isVolatile(), LDBase->isNonTemporal(),
6002 LDBase->isInvariant(), 0);
6003 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6004 LDBase->getPointerInfo(),
6005 LDBase->isVolatile(), LDBase->isNonTemporal(),
6006 LDBase->isInvariant(), LDBase->getAlignment());
6008 if (LDBase->hasAnyUseOfValue(1)) {
6009 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6011 SDValue(NewLd.getNode(), 1));
6012 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6013 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6014 SDValue(NewLd.getNode(), 1));
6020 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6021 //of a v4i32 / v4f32. It's probably worth generalizing.
6022 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6023 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6024 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6025 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6027 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6028 LDBase->getPointerInfo(),
6029 LDBase->getAlignment(),
6030 false/*isVolatile*/, true/*ReadMem*/,
6033 // Make sure the newly-created LOAD is in the same position as LDBase in
6034 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6035 // update uses of LDBase's output chain to use the TokenFactor.
6036 if (LDBase->hasAnyUseOfValue(1)) {
6037 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6038 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6039 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6040 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6041 SDValue(ResNode.getNode(), 1));
6044 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6049 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6050 /// to generate a splat value for the following cases:
6051 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6052 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6053 /// a scalar load, or a constant.
6054 /// The VBROADCAST node is returned when a pattern is found,
6055 /// or SDValue() otherwise.
6056 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6057 SelectionDAG &DAG) {
6058 // VBROADCAST requires AVX.
6059 // TODO: Splats could be generated for non-AVX CPUs using SSE
6060 // instructions, but there's less potential gain for only 128-bit vectors.
6061 if (!Subtarget->hasAVX())
6064 MVT VT = Op.getSimpleValueType();
6067 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6068 "Unsupported vector type for broadcast.");
6073 switch (Op.getOpcode()) {
6075 // Unknown pattern found.
6078 case ISD::BUILD_VECTOR: {
6079 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6080 BitVector UndefElements;
6081 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6083 // We need a splat of a single value to use broadcast, and it doesn't
6084 // make any sense if the value is only in one element of the vector.
6085 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6089 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6090 Ld.getOpcode() == ISD::ConstantFP);
6092 // Make sure that all of the users of a non-constant load are from the
6093 // BUILD_VECTOR node.
6094 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6099 case ISD::VECTOR_SHUFFLE: {
6100 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6102 // Shuffles must have a splat mask where the first element is
6104 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6107 SDValue Sc = Op.getOperand(0);
6108 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6109 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6111 if (!Subtarget->hasInt256())
6114 // Use the register form of the broadcast instruction available on AVX2.
6115 if (VT.getSizeInBits() >= 256)
6116 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6117 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6120 Ld = Sc.getOperand(0);
6121 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6122 Ld.getOpcode() == ISD::ConstantFP);
6124 // The scalar_to_vector node and the suspected
6125 // load node must have exactly one user.
6126 // Constants may have multiple users.
6128 // AVX-512 has register version of the broadcast
6129 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6130 Ld.getValueType().getSizeInBits() >= 32;
6131 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6138 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6139 bool IsGE256 = (VT.getSizeInBits() >= 256);
6141 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6142 // instruction to save 8 or more bytes of constant pool data.
6143 // TODO: If multiple splats are generated to load the same constant,
6144 // it may be detrimental to overall size. There needs to be a way to detect
6145 // that condition to know if this is truly a size win.
6146 const Function *F = DAG.getMachineFunction().getFunction();
6147 bool OptForSize = F->getAttributes().
6148 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6150 // Handle broadcasting a single constant scalar from the constant pool
6152 // On Sandybridge (no AVX2), it is still better to load a constant vector
6153 // from the constant pool and not to broadcast it from a scalar.
6154 // But override that restriction when optimizing for size.
6155 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6156 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6157 EVT CVT = Ld.getValueType();
6158 assert(!CVT.isVector() && "Must not broadcast a vector type");
6160 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6161 // For size optimization, also splat v2f64 and v2i64, and for size opt
6162 // with AVX2, also splat i8 and i16.
6163 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6164 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6165 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6166 const Constant *C = nullptr;
6167 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6168 C = CI->getConstantIntValue();
6169 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6170 C = CF->getConstantFPValue();
6172 assert(C && "Invalid constant type");
6174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6175 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6176 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6177 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6178 MachinePointerInfo::getConstantPool(),
6179 false, false, false, Alignment);
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6185 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6187 // Handle AVX2 in-register broadcasts.
6188 if (!IsLoad && Subtarget->hasInt256() &&
6189 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6190 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6192 // The scalar source must be a normal load.
6196 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6197 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6199 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6200 // double since there is no vbroadcastsd xmm
6201 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6202 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6203 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6206 // Unsupported broadcast.
6210 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6211 /// underlying vector and index.
6213 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6215 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6217 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6218 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6221 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6223 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6225 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6226 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6229 // In this case the vector is the extract_subvector expression and the index
6230 // is 2, as specified by the shuffle.
6231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6232 SDValue ShuffleVec = SVOp->getOperand(0);
6233 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6234 assert(ShuffleVecVT.getVectorElementType() ==
6235 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6237 int ShuffleIdx = SVOp->getMaskElt(Idx);
6238 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6239 ExtractedFromVec = ShuffleVec;
6245 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6246 MVT VT = Op.getSimpleValueType();
6248 // Skip if insert_vec_elt is not supported.
6249 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6250 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6254 unsigned NumElems = Op.getNumOperands();
6258 SmallVector<unsigned, 4> InsertIndices;
6259 SmallVector<int, 8> Mask(NumElems, -1);
6261 for (unsigned i = 0; i != NumElems; ++i) {
6262 unsigned Opc = Op.getOperand(i).getOpcode();
6264 if (Opc == ISD::UNDEF)
6267 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6268 // Quit if more than 1 elements need inserting.
6269 if (InsertIndices.size() > 1)
6272 InsertIndices.push_back(i);
6276 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6277 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6278 // Quit if non-constant index.
6279 if (!isa<ConstantSDNode>(ExtIdx))
6281 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6283 // Quit if extracted from vector of different type.
6284 if (ExtractedFromVec.getValueType() != VT)
6287 if (!VecIn1.getNode())
6288 VecIn1 = ExtractedFromVec;
6289 else if (VecIn1 != ExtractedFromVec) {
6290 if (!VecIn2.getNode())
6291 VecIn2 = ExtractedFromVec;
6292 else if (VecIn2 != ExtractedFromVec)
6293 // Quit if more than 2 vectors to shuffle
6297 if (ExtractedFromVec == VecIn1)
6299 else if (ExtractedFromVec == VecIn2)
6300 Mask[i] = Idx + NumElems;
6303 if (!VecIn1.getNode())
6306 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6307 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6308 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6309 unsigned Idx = InsertIndices[i];
6310 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6311 DAG.getIntPtrConstant(Idx));
6317 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6319 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6321 MVT VT = Op.getSimpleValueType();
6322 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6323 "Unexpected type in LowerBUILD_VECTORvXi1!");
6326 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6327 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6328 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6329 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6332 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6333 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6334 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6335 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6338 bool AllContants = true;
6339 uint64_t Immediate = 0;
6340 int NonConstIdx = -1;
6341 bool IsSplat = true;
6342 unsigned NumNonConsts = 0;
6343 unsigned NumConsts = 0;
6344 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6345 SDValue In = Op.getOperand(idx);
6346 if (In.getOpcode() == ISD::UNDEF)
6348 if (!isa<ConstantSDNode>(In)) {
6349 AllContants = false;
6354 if (cast<ConstantSDNode>(In)->getZExtValue())
6355 Immediate |= (1ULL << idx);
6357 if (In != Op.getOperand(0))
6362 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6363 DAG.getConstant(Immediate, MVT::i16));
6364 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6365 DAG.getIntPtrConstant(0));
6368 if (NumNonConsts == 1 && NonConstIdx != 0) {
6371 SDValue VecAsImm = DAG.getConstant(Immediate,
6372 MVT::getIntegerVT(VT.getSizeInBits()));
6373 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6376 DstVec = DAG.getUNDEF(VT);
6377 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6378 Op.getOperand(NonConstIdx),
6379 DAG.getIntPtrConstant(NonConstIdx));
6381 if (!IsSplat && (NonConstIdx != 0))
6382 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6383 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6386 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6387 DAG.getConstant(-1, SelectVT),
6388 DAG.getConstant(0, SelectVT));
6390 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6391 DAG.getConstant((Immediate | 1), SelectVT),
6392 DAG.getConstant(Immediate, SelectVT));
6393 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6396 /// \brief Return true if \p N implements a horizontal binop and return the
6397 /// operands for the horizontal binop into V0 and V1.
6399 /// This is a helper function of PerformBUILD_VECTORCombine.
6400 /// This function checks that the build_vector \p N in input implements a
6401 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6402 /// operation to match.
6403 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6404 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6405 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6408 /// This function only analyzes elements of \p N whose indices are
6409 /// in range [BaseIdx, LastIdx).
6410 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6412 unsigned BaseIdx, unsigned LastIdx,
6413 SDValue &V0, SDValue &V1) {
6414 EVT VT = N->getValueType(0);
6416 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6417 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6418 "Invalid Vector in input!");
6420 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6421 bool CanFold = true;
6422 unsigned ExpectedVExtractIdx = BaseIdx;
6423 unsigned NumElts = LastIdx - BaseIdx;
6424 V0 = DAG.getUNDEF(VT);
6425 V1 = DAG.getUNDEF(VT);
6427 // Check if N implements a horizontal binop.
6428 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6429 SDValue Op = N->getOperand(i + BaseIdx);
6432 if (Op->getOpcode() == ISD::UNDEF) {
6433 // Update the expected vector extract index.
6434 if (i * 2 == NumElts)
6435 ExpectedVExtractIdx = BaseIdx;
6436 ExpectedVExtractIdx += 2;
6440 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6445 SDValue Op0 = Op.getOperand(0);
6446 SDValue Op1 = Op.getOperand(1);
6448 // Try to match the following pattern:
6449 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6450 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6451 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6452 Op0.getOperand(0) == Op1.getOperand(0) &&
6453 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6454 isa<ConstantSDNode>(Op1.getOperand(1)));
6458 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6459 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6461 if (i * 2 < NumElts) {
6462 if (V0.getOpcode() == ISD::UNDEF)
6463 V0 = Op0.getOperand(0);
6465 if (V1.getOpcode() == ISD::UNDEF)
6466 V1 = Op0.getOperand(0);
6467 if (i * 2 == NumElts)
6468 ExpectedVExtractIdx = BaseIdx;
6471 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6472 if (I0 == ExpectedVExtractIdx)
6473 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6474 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6475 // Try to match the following dag sequence:
6476 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6477 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6481 ExpectedVExtractIdx += 2;
6487 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6488 /// a concat_vector.
6490 /// This is a helper function of PerformBUILD_VECTORCombine.
6491 /// This function expects two 256-bit vectors called V0 and V1.
6492 /// At first, each vector is split into two separate 128-bit vectors.
6493 /// Then, the resulting 128-bit vectors are used to implement two
6494 /// horizontal binary operations.
6496 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6498 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6499 /// the two new horizontal binop.
6500 /// When Mode is set, the first horizontal binop dag node would take as input
6501 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6502 /// horizontal binop dag node would take as input the lower 128-bit of V1
6503 /// and the upper 128-bit of V1.
6505 /// HADD V0_LO, V0_HI
6506 /// HADD V1_LO, V1_HI
6508 /// Otherwise, the first horizontal binop dag node takes as input the lower
6509 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6510 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6512 /// HADD V0_LO, V1_LO
6513 /// HADD V0_HI, V1_HI
6515 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6516 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6517 /// the upper 128-bits of the result.
6518 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6519 SDLoc DL, SelectionDAG &DAG,
6520 unsigned X86Opcode, bool Mode,
6521 bool isUndefLO, bool isUndefHI) {
6522 EVT VT = V0.getValueType();
6523 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6524 "Invalid nodes in input!");
6526 unsigned NumElts = VT.getVectorNumElements();
6527 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6528 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6529 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6530 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6531 EVT NewVT = V0_LO.getValueType();
6533 SDValue LO = DAG.getUNDEF(NewVT);
6534 SDValue HI = DAG.getUNDEF(NewVT);
6537 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6538 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6539 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6540 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6541 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6543 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6544 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6545 V1_LO->getOpcode() != ISD::UNDEF))
6546 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6548 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6549 V1_HI->getOpcode() != ISD::UNDEF))
6550 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6553 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6556 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6557 /// sequence of 'vadd + vsub + blendi'.
6558 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6559 const X86Subtarget *Subtarget) {
6561 EVT VT = BV->getValueType(0);
6562 unsigned NumElts = VT.getVectorNumElements();
6563 SDValue InVec0 = DAG.getUNDEF(VT);
6564 SDValue InVec1 = DAG.getUNDEF(VT);
6566 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6567 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6569 // Odd-numbered elements in the input build vector are obtained from
6570 // adding two integer/float elements.
6571 // Even-numbered elements in the input build vector are obtained from
6572 // subtracting two integer/float elements.
6573 unsigned ExpectedOpcode = ISD::FSUB;
6574 unsigned NextExpectedOpcode = ISD::FADD;
6575 bool AddFound = false;
6576 bool SubFound = false;
6578 for (unsigned i = 0, e = NumElts; i != e; i++) {
6579 SDValue Op = BV->getOperand(i);
6581 // Skip 'undef' values.
6582 unsigned Opcode = Op.getOpcode();
6583 if (Opcode == ISD::UNDEF) {
6584 std::swap(ExpectedOpcode, NextExpectedOpcode);
6588 // Early exit if we found an unexpected opcode.
6589 if (Opcode != ExpectedOpcode)
6592 SDValue Op0 = Op.getOperand(0);
6593 SDValue Op1 = Op.getOperand(1);
6595 // Try to match the following pattern:
6596 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6597 // Early exit if we cannot match that sequence.
6598 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6599 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6600 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6601 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6602 Op0.getOperand(1) != Op1.getOperand(1))
6605 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6609 // We found a valid add/sub node. Update the information accordingly.
6615 // Update InVec0 and InVec1.
6616 if (InVec0.getOpcode() == ISD::UNDEF)
6617 InVec0 = Op0.getOperand(0);
6618 if (InVec1.getOpcode() == ISD::UNDEF)
6619 InVec1 = Op1.getOperand(0);
6621 // Make sure that operands in input to each add/sub node always
6622 // come from a same pair of vectors.
6623 if (InVec0 != Op0.getOperand(0)) {
6624 if (ExpectedOpcode == ISD::FSUB)
6627 // FADD is commutable. Try to commute the operands
6628 // and then test again.
6629 std::swap(Op0, Op1);
6630 if (InVec0 != Op0.getOperand(0))
6634 if (InVec1 != Op1.getOperand(0))
6637 // Update the pair of expected opcodes.
6638 std::swap(ExpectedOpcode, NextExpectedOpcode);
6641 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6642 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6643 InVec1.getOpcode() != ISD::UNDEF)
6644 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6649 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6650 const X86Subtarget *Subtarget) {
6652 EVT VT = N->getValueType(0);
6653 unsigned NumElts = VT.getVectorNumElements();
6654 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6655 SDValue InVec0, InVec1;
6657 // Try to match an ADDSUB.
6658 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6659 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6660 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6661 if (Value.getNode())
6665 // Try to match horizontal ADD/SUB.
6666 unsigned NumUndefsLO = 0;
6667 unsigned NumUndefsHI = 0;
6668 unsigned Half = NumElts/2;
6670 // Count the number of UNDEF operands in the build_vector in input.
6671 for (unsigned i = 0, e = Half; i != e; ++i)
6672 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6675 for (unsigned i = Half, e = NumElts; i != e; ++i)
6676 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6679 // Early exit if this is either a build_vector of all UNDEFs or all the
6680 // operands but one are UNDEF.
6681 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6684 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6685 // Try to match an SSE3 float HADD/HSUB.
6686 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6687 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6689 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6690 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6691 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6692 // Try to match an SSSE3 integer HADD/HSUB.
6693 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6694 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6696 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6697 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6700 if (!Subtarget->hasAVX())
6703 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6704 // Try to match an AVX horizontal add/sub of packed single/double
6705 // precision floating point values from 256-bit vectors.
6706 SDValue InVec2, InVec3;
6707 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6708 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6709 ((InVec0.getOpcode() == ISD::UNDEF ||
6710 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6711 ((InVec1.getOpcode() == ISD::UNDEF ||
6712 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6713 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6715 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6716 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6717 ((InVec0.getOpcode() == ISD::UNDEF ||
6718 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6719 ((InVec1.getOpcode() == ISD::UNDEF ||
6720 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6721 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6722 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6723 // Try to match an AVX2 horizontal add/sub of signed integers.
6724 SDValue InVec2, InVec3;
6726 bool CanFold = true;
6728 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6729 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6730 ((InVec0.getOpcode() == ISD::UNDEF ||
6731 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6732 ((InVec1.getOpcode() == ISD::UNDEF ||
6733 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6734 X86Opcode = X86ISD::HADD;
6735 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6736 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6737 ((InVec0.getOpcode() == ISD::UNDEF ||
6738 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6739 ((InVec1.getOpcode() == ISD::UNDEF ||
6740 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6741 X86Opcode = X86ISD::HSUB;
6746 // Fold this build_vector into a single horizontal add/sub.
6747 // Do this only if the target has AVX2.
6748 if (Subtarget->hasAVX2())
6749 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6751 // Do not try to expand this build_vector into a pair of horizontal
6752 // add/sub if we can emit a pair of scalar add/sub.
6753 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6756 // Convert this build_vector into a pair of horizontal binop followed by
6758 bool isUndefLO = NumUndefsLO == Half;
6759 bool isUndefHI = NumUndefsHI == Half;
6760 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6761 isUndefLO, isUndefHI);
6765 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6766 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6768 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6769 X86Opcode = X86ISD::HADD;
6770 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6771 X86Opcode = X86ISD::HSUB;
6772 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6773 X86Opcode = X86ISD::FHADD;
6774 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6775 X86Opcode = X86ISD::FHSUB;
6779 // Don't try to expand this build_vector into a pair of horizontal add/sub
6780 // if we can simply emit a pair of scalar add/sub.
6781 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6784 // Convert this build_vector into two horizontal add/sub followed by
6786 bool isUndefLO = NumUndefsLO == Half;
6787 bool isUndefHI = NumUndefsHI == Half;
6788 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6789 isUndefLO, isUndefHI);
6796 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6799 MVT VT = Op.getSimpleValueType();
6800 MVT ExtVT = VT.getVectorElementType();
6801 unsigned NumElems = Op.getNumOperands();
6803 // Generate vectors for predicate vectors.
6804 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6805 return LowerBUILD_VECTORvXi1(Op, DAG);
6807 // Vectors containing all zeros can be matched by pxor and xorps later
6808 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6809 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6810 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6811 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6814 return getZeroVector(VT, Subtarget, DAG, dl);
6817 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6818 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6819 // vpcmpeqd on 256-bit vectors.
6820 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6821 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6824 if (!VT.is512BitVector())
6825 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6828 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6829 if (Broadcast.getNode())
6832 unsigned EVTBits = ExtVT.getSizeInBits();
6834 unsigned NumZero = 0;
6835 unsigned NumNonZero = 0;
6836 unsigned NonZeros = 0;
6837 bool IsAllConstants = true;
6838 SmallSet<SDValue, 8> Values;
6839 for (unsigned i = 0; i < NumElems; ++i) {
6840 SDValue Elt = Op.getOperand(i);
6841 if (Elt.getOpcode() == ISD::UNDEF)
6844 if (Elt.getOpcode() != ISD::Constant &&
6845 Elt.getOpcode() != ISD::ConstantFP)
6846 IsAllConstants = false;
6847 if (X86::isZeroNode(Elt))
6850 NonZeros |= (1 << i);
6855 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6856 if (NumNonZero == 0)
6857 return DAG.getUNDEF(VT);
6859 // Special case for single non-zero, non-undef, element.
6860 if (NumNonZero == 1) {
6861 unsigned Idx = countTrailingZeros(NonZeros);
6862 SDValue Item = Op.getOperand(Idx);
6864 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6865 // the value are obviously zero, truncate the value to i32 and do the
6866 // insertion that way. Only do this if the value is non-constant or if the
6867 // value is a constant being inserted into element 0. It is cheaper to do
6868 // a constant pool load than it is to do a movd + shuffle.
6869 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6870 (!IsAllConstants || Idx == 0)) {
6871 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6873 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6874 EVT VecVT = MVT::v4i32;
6875 unsigned VecElts = 4;
6877 // Truncate the value (which may itself be a constant) to i32, and
6878 // convert it to a vector with movd (S2V+shuffle to zero extend).
6879 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6882 // If using the new shuffle lowering, just directly insert this.
6883 if (ExperimentalVectorShuffleLowering)
6885 ISD::BITCAST, dl, VT,
6886 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6888 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6890 // Now we have our 32-bit value zero extended in the low element of
6891 // a vector. If Idx != 0, swizzle it into place.
6893 SmallVector<int, 4> Mask;
6894 Mask.push_back(Idx);
6895 for (unsigned i = 1; i != VecElts; ++i)
6897 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6900 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6904 // If we have a constant or non-constant insertion into the low element of
6905 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6906 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6907 // depending on what the source datatype is.
6910 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6912 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6913 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6914 if (VT.is256BitVector() || VT.is512BitVector()) {
6915 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6916 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6917 Item, DAG.getIntPtrConstant(0));
6919 assert(VT.is128BitVector() && "Expected an SSE value type!");
6920 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6921 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6922 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6925 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6926 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6927 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6928 if (VT.is256BitVector()) {
6929 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6930 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6932 assert(VT.is128BitVector() && "Expected an SSE value type!");
6933 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6935 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6939 // Is it a vector logical left shift?
6940 if (NumElems == 2 && Idx == 1 &&
6941 X86::isZeroNode(Op.getOperand(0)) &&
6942 !X86::isZeroNode(Op.getOperand(1))) {
6943 unsigned NumBits = VT.getSizeInBits();
6944 return getVShift(true, VT,
6945 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6946 VT, Op.getOperand(1)),
6947 NumBits/2, DAG, *this, dl);
6950 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6953 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6954 // is a non-constant being inserted into an element other than the low one,
6955 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6956 // movd/movss) to move this into the low element, then shuffle it into
6958 if (EVTBits == 32) {
6959 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6961 // If using the new shuffle lowering, just directly insert this.
6962 if (ExperimentalVectorShuffleLowering)
6963 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6965 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6966 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6967 SmallVector<int, 8> MaskVec;
6968 for (unsigned i = 0; i != NumElems; ++i)
6969 MaskVec.push_back(i == Idx ? 0 : 1);
6970 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6974 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6975 if (Values.size() == 1) {
6976 if (EVTBits == 32) {
6977 // Instead of a shuffle like this:
6978 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6979 // Check if it's possible to issue this instead.
6980 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6981 unsigned Idx = countTrailingZeros(NonZeros);
6982 SDValue Item = Op.getOperand(Idx);
6983 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6984 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6989 // A vector full of immediates; various special cases are already
6990 // handled, so this is best done with a single constant-pool load.
6994 // For AVX-length vectors, see if we can use a vector load to get all of the
6995 // elements, otherwise build the individual 128-bit pieces and use
6996 // shuffles to put them in place.
6997 if (VT.is256BitVector() || VT.is512BitVector()) {
6998 SmallVector<SDValue, 64> V;
6999 for (unsigned i = 0; i != NumElems; ++i)
7000 V.push_back(Op.getOperand(i));
7002 // Check for a build vector of consecutive loads.
7003 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7006 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7008 // Build both the lower and upper subvector.
7009 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7010 makeArrayRef(&V[0], NumElems/2));
7011 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7012 makeArrayRef(&V[NumElems / 2], NumElems/2));
7014 // Recreate the wider vector with the lower and upper part.
7015 if (VT.is256BitVector())
7016 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7017 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7020 // Let legalizer expand 2-wide build_vectors.
7021 if (EVTBits == 64) {
7022 if (NumNonZero == 1) {
7023 // One half is zero or undef.
7024 unsigned Idx = countTrailingZeros(NonZeros);
7025 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7026 Op.getOperand(Idx));
7027 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7032 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7033 if (EVTBits == 8 && NumElems == 16) {
7034 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7036 if (V.getNode()) return V;
7039 if (EVTBits == 16 && NumElems == 8) {
7040 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7042 if (V.getNode()) return V;
7045 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7046 if (EVTBits == 32 && NumElems == 4) {
7047 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7052 // If element VT is == 32 bits, turn it into a number of shuffles.
7053 SmallVector<SDValue, 8> V(NumElems);
7054 if (NumElems == 4 && NumZero > 0) {
7055 for (unsigned i = 0; i < 4; ++i) {
7056 bool isZero = !(NonZeros & (1 << i));
7058 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7060 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7063 for (unsigned i = 0; i < 2; ++i) {
7064 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7067 V[i] = V[i*2]; // Must be a zero vector.
7070 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7073 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7076 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7081 bool Reverse1 = (NonZeros & 0x3) == 2;
7082 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7086 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7087 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7089 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7092 if (Values.size() > 1 && VT.is128BitVector()) {
7093 // Check for a build vector of consecutive loads.
7094 for (unsigned i = 0; i < NumElems; ++i)
7095 V[i] = Op.getOperand(i);
7097 // Check for elements which are consecutive loads.
7098 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7102 // Check for a build vector from mostly shuffle plus few inserting.
7103 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7107 // For SSE 4.1, use insertps to put the high elements into the low element.
7108 if (getSubtarget()->hasSSE41()) {
7110 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7111 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7113 Result = DAG.getUNDEF(VT);
7115 for (unsigned i = 1; i < NumElems; ++i) {
7116 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7117 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7118 Op.getOperand(i), DAG.getIntPtrConstant(i));
7123 // Otherwise, expand into a number of unpckl*, start by extending each of
7124 // our (non-undef) elements to the full vector width with the element in the
7125 // bottom slot of the vector (which generates no code for SSE).
7126 for (unsigned i = 0; i < NumElems; ++i) {
7127 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7128 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7130 V[i] = DAG.getUNDEF(VT);
7133 // Next, we iteratively mix elements, e.g. for v4f32:
7134 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7135 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7136 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7137 unsigned EltStride = NumElems >> 1;
7138 while (EltStride != 0) {
7139 for (unsigned i = 0; i < EltStride; ++i) {
7140 // If V[i+EltStride] is undef and this is the first round of mixing,
7141 // then it is safe to just drop this shuffle: V[i] is already in the
7142 // right place, the one element (since it's the first round) being
7143 // inserted as undef can be dropped. This isn't safe for successive
7144 // rounds because they will permute elements within both vectors.
7145 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7146 EltStride == NumElems/2)
7149 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7158 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7159 // to create 256-bit vectors from two other 128-bit ones.
7160 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7162 MVT ResVT = Op.getSimpleValueType();
7164 assert((ResVT.is256BitVector() ||
7165 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7167 SDValue V1 = Op.getOperand(0);
7168 SDValue V2 = Op.getOperand(1);
7169 unsigned NumElems = ResVT.getVectorNumElements();
7170 if(ResVT.is256BitVector())
7171 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7173 if (Op.getNumOperands() == 4) {
7174 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7175 ResVT.getVectorNumElements()/2);
7176 SDValue V3 = Op.getOperand(2);
7177 SDValue V4 = Op.getOperand(3);
7178 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7179 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7181 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7184 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7185 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7186 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7187 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7188 Op.getNumOperands() == 4)));
7190 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7191 // from two other 128-bit ones.
7193 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7194 return LowerAVXCONCAT_VECTORS(Op, DAG);
7198 //===----------------------------------------------------------------------===//
7199 // Vector shuffle lowering
7201 // This is an experimental code path for lowering vector shuffles on x86. It is
7202 // designed to handle arbitrary vector shuffles and blends, gracefully
7203 // degrading performance as necessary. It works hard to recognize idiomatic
7204 // shuffles and lower them to optimal instruction patterns without leaving
7205 // a framework that allows reasonably efficient handling of all vector shuffle
7207 //===----------------------------------------------------------------------===//
7209 /// \brief Tiny helper function to identify a no-op mask.
7211 /// This is a somewhat boring predicate function. It checks whether the mask
7212 /// array input, which is assumed to be a single-input shuffle mask of the kind
7213 /// used by the X86 shuffle instructions (not a fully general
7214 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7215 /// in-place shuffle are 'no-op's.
7216 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7217 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7218 if (Mask[i] != -1 && Mask[i] != i)
7223 /// \brief Helper function to classify a mask as a single-input mask.
7225 /// This isn't a generic single-input test because in the vector shuffle
7226 /// lowering we canonicalize single inputs to be the first input operand. This
7227 /// means we can more quickly test for a single input by only checking whether
7228 /// an input from the second operand exists. We also assume that the size of
7229 /// mask corresponds to the size of the input vectors which isn't true in the
7230 /// fully general case.
7231 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7233 if (M >= (int)Mask.size())
7238 /// \brief Test whether there are elements crossing 128-bit lanes in this
7241 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7242 /// and we routinely test for these.
7243 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7244 int LaneSize = 128 / VT.getScalarSizeInBits();
7245 int Size = Mask.size();
7246 for (int i = 0; i < Size; ++i)
7247 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7252 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7254 /// This checks a shuffle mask to see if it is performing the same
7255 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7256 /// that it is also not lane-crossing. It may however involve a blend from the
7257 /// same lane of a second vector.
7259 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7260 /// non-trivial to compute in the face of undef lanes. The representation is
7261 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7262 /// entries from both V1 and V2 inputs to the wider mask.
7264 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7265 SmallVectorImpl<int> &RepeatedMask) {
7266 int LaneSize = 128 / VT.getScalarSizeInBits();
7267 RepeatedMask.resize(LaneSize, -1);
7268 int Size = Mask.size();
7269 for (int i = 0; i < Size; ++i) {
7272 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7273 // This entry crosses lanes, so there is no way to model this shuffle.
7276 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7277 if (RepeatedMask[i % LaneSize] == -1)
7278 // This is the first non-undef entry in this slot of a 128-bit lane.
7279 RepeatedMask[i % LaneSize] =
7280 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7281 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7282 // Found a mismatch with the repeated mask.
7288 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7289 // 2013 will allow us to use it as a non-type template parameter.
7292 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7294 /// See its documentation for details.
7295 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7296 if (Mask.size() != Args.size())
7298 for (int i = 0, e = Mask.size(); i < e; ++i) {
7299 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7300 if (Mask[i] != -1 && Mask[i] != *Args[i])
7308 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7311 /// This is a fast way to test a shuffle mask against a fixed pattern:
7313 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7315 /// It returns true if the mask is exactly as wide as the argument list, and
7316 /// each element of the mask is either -1 (signifying undef) or the value given
7317 /// in the argument.
7318 static const VariadicFunction1<
7319 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7321 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7323 /// This helper function produces an 8-bit shuffle immediate corresponding to
7324 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7325 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7328 /// NB: We rely heavily on "undef" masks preserving the input lane.
7329 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7330 SelectionDAG &DAG) {
7331 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7332 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7333 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7334 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7335 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7338 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7339 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7340 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7341 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7342 return DAG.getConstant(Imm, MVT::i8);
7345 /// \brief Try to emit a blend instruction for a shuffle.
7347 /// This doesn't do any checks for the availability of instructions for blending
7348 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7349 /// be matched in the backend with the type given. What it does check for is
7350 /// that the shuffle mask is in fact a blend.
7351 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7352 SDValue V2, ArrayRef<int> Mask,
7353 const X86Subtarget *Subtarget,
7354 SelectionDAG &DAG) {
7356 unsigned BlendMask = 0;
7357 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7358 if (Mask[i] >= Size) {
7359 if (Mask[i] != i + Size)
7360 return SDValue(); // Shuffled V2 input!
7361 BlendMask |= 1u << i;
7364 if (Mask[i] >= 0 && Mask[i] != i)
7365 return SDValue(); // Shuffled V1 input!
7367 switch (VT.SimpleTy) {
7372 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7373 DAG.getConstant(BlendMask, MVT::i8));
7377 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7381 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7382 // that instruction.
7383 if (Subtarget->hasAVX2()) {
7384 // Scale the blend by the number of 32-bit dwords per element.
7385 int Scale = VT.getScalarSizeInBits() / 32;
7387 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7388 if (Mask[i] >= Size)
7389 for (int j = 0; j < Scale; ++j)
7390 BlendMask |= 1u << (i * Scale + j);
7392 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7393 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7394 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7395 return DAG.getNode(ISD::BITCAST, DL, VT,
7396 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7397 DAG.getConstant(BlendMask, MVT::i8)));
7401 // For integer shuffles we need to expand the mask and cast the inputs to
7402 // v8i16s prior to blending.
7403 int Scale = 8 / VT.getVectorNumElements();
7405 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7406 if (Mask[i] >= Size)
7407 for (int j = 0; j < Scale; ++j)
7408 BlendMask |= 1u << (i * Scale + j);
7410 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7411 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7412 return DAG.getNode(ISD::BITCAST, DL, VT,
7413 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7414 DAG.getConstant(BlendMask, MVT::i8)));
7418 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7419 SmallVector<int, 8> RepeatedMask;
7420 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7421 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7422 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7424 for (int i = 0; i < 8; ++i)
7425 if (RepeatedMask[i] >= 16)
7426 BlendMask |= 1u << i;
7427 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7428 DAG.getConstant(BlendMask, MVT::i8));
7433 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7434 // Scale the blend by the number of bytes per element.
7435 int Scale = VT.getScalarSizeInBits() / 8;
7436 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7438 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7439 // mix of LLVM's code generator and the x86 backend. We tell the code
7440 // generator that boolean values in the elements of an x86 vector register
7441 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7442 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7443 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7444 // of the element (the remaining are ignored) and 0 in that high bit would
7445 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7446 // the LLVM model for boolean values in vector elements gets the relevant
7447 // bit set, it is set backwards and over constrained relative to x86's
7449 SDValue VSELECTMask[32];
7450 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7451 for (int j = 0; j < Scale; ++j)
7452 VSELECTMask[Scale * i + j] =
7453 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7454 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7456 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7457 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7459 ISD::BITCAST, DL, VT,
7460 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7461 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7466 llvm_unreachable("Not a supported integer vector type!");
7470 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7471 /// unblended shuffles followed by an unshuffled blend.
7473 /// This matches the extremely common pattern for handling combined
7474 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7476 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7480 SelectionDAG &DAG) {
7481 // Shuffle the input elements into the desired positions in V1 and V2 and
7482 // blend them together.
7483 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7484 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7485 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7486 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7487 if (Mask[i] >= 0 && Mask[i] < Size) {
7488 V1Mask[i] = Mask[i];
7490 } else if (Mask[i] >= Size) {
7491 V2Mask[i] = Mask[i] - Size;
7492 BlendMask[i] = i + Size;
7495 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7496 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7497 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7500 /// \brief Try to lower a vector shuffle as a byte rotation.
7502 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7503 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7504 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7505 /// try to generically lower a vector shuffle through such an pattern. It
7506 /// does not check for the profitability of lowering either as PALIGNR or
7507 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7508 /// This matches shuffle vectors that look like:
7510 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7512 /// Essentially it concatenates V1 and V2, shifts right by some number of
7513 /// elements, and takes the low elements as the result. Note that while this is
7514 /// specified as a *right shift* because x86 is little-endian, it is a *left
7515 /// rotate* of the vector lanes.
7517 /// Note that this only handles 128-bit vector widths currently.
7518 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7521 const X86Subtarget *Subtarget,
7522 SelectionDAG &DAG) {
7523 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7525 // We need to detect various ways of spelling a rotation:
7526 // [11, 12, 13, 14, 15, 0, 1, 2]
7527 // [-1, 12, 13, 14, -1, -1, 1, -1]
7528 // [-1, -1, -1, -1, -1, -1, 1, 2]
7529 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7530 // [-1, 4, 5, 6, -1, -1, 9, -1]
7531 // [-1, 4, 5, 6, -1, -1, -1, -1]
7534 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7537 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7539 // Based on the mod-Size value of this mask element determine where
7540 // a rotated vector would have started.
7541 int StartIdx = i - (Mask[i] % Size);
7543 // The identity rotation isn't interesting, stop.
7546 // If we found the tail of a vector the rotation must be the missing
7547 // front. If we found the head of a vector, it must be how much of the head.
7548 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7551 Rotation = CandidateRotation;
7552 else if (Rotation != CandidateRotation)
7553 // The rotations don't match, so we can't match this mask.
7556 // Compute which value this mask is pointing at.
7557 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7559 // Compute which of the two target values this index should be assigned to.
7560 // This reflects whether the high elements are remaining or the low elements
7562 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7564 // Either set up this value if we've not encountered it before, or check
7565 // that it remains consistent.
7568 else if (TargetV != MaskV)
7569 // This may be a rotation, but it pulls from the inputs in some
7570 // unsupported interleaving.
7574 // Check that we successfully analyzed the mask, and normalize the results.
7575 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7576 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7582 assert(VT.getSizeInBits() == 128 &&
7583 "Rotate-based lowering only supports 128-bit lowering!");
7584 assert(Mask.size() <= 16 &&
7585 "Can shuffle at most 16 bytes in a 128-bit vector!");
7587 // The actual rotate instruction rotates bytes, so we need to scale the
7588 // rotation based on how many bytes are in the vector.
7589 int Scale = 16 / Mask.size();
7591 // SSSE3 targets can use the palignr instruction
7592 if (Subtarget->hasSSSE3()) {
7593 // Cast the inputs to v16i8 to match PALIGNR.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7597 return DAG.getNode(ISD::BITCAST, DL, VT,
7598 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7599 DAG.getConstant(Rotation * Scale, MVT::i8)));
7602 // Default SSE2 implementation
7603 int LoByteShift = 16 - Rotation * Scale;
7604 int HiByteShift = Rotation * Scale;
7606 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7607 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7608 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7610 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7611 DAG.getConstant(8 * LoByteShift, MVT::i8));
7612 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7613 DAG.getConstant(8 * HiByteShift, MVT::i8));
7614 return DAG.getNode(ISD::BITCAST, DL, VT,
7615 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7618 /// \brief Compute whether each element of a shuffle is zeroable.
7620 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7621 /// Either it is an undef element in the shuffle mask, the element of the input
7622 /// referenced is undef, or the element of the input referenced is known to be
7623 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7624 /// as many lanes with this technique as possible to simplify the remaining
7626 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7627 SDValue V1, SDValue V2) {
7628 SmallBitVector Zeroable(Mask.size(), false);
7630 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7631 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7633 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7635 // Handle the easy cases.
7636 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7641 // If this is an index into a build_vector node, dig out the input value and
7643 SDValue V = M < Size ? V1 : V2;
7644 if (V.getOpcode() != ISD::BUILD_VECTOR)
7647 SDValue Input = V.getOperand(M % Size);
7648 // The UNDEF opcode check really should be dead code here, but not quite
7649 // worth asserting on (it isn't invalid, just unexpected).
7650 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7657 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7659 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7660 /// byte-shift instructions. The mask must consist of a shifted sequential
7661 /// shuffle from one of the input vectors and zeroable elements for the
7662 /// remaining 'shifted in' elements.
7664 /// Note that this only handles 128-bit vector widths currently.
7665 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7666 SDValue V2, ArrayRef<int> Mask,
7667 SelectionDAG &DAG) {
7668 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7670 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7672 int Size = Mask.size();
7673 int Scale = 16 / Size;
7675 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7676 ArrayRef<int> Mask) {
7677 for (int i = StartIndex; i < EndIndex; i++) {
7680 if (i + Base != Mask[i] - MaskOffset)
7686 for (int Shift = 1; Shift < Size; Shift++) {
7687 int ByteShift = Shift * Scale;
7689 // PSRLDQ : (little-endian) right byte shift
7690 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7691 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7692 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7693 bool ZeroableRight = true;
7694 for (int i = Size - Shift; i < Size; i++) {
7695 ZeroableRight &= Zeroable[i];
7698 if (ZeroableRight) {
7699 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7700 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7702 if (ValidShiftRight1 || ValidShiftRight2) {
7703 // Cast the inputs to v2i64 to match PSRLDQ.
7704 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7705 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7706 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7707 DAG.getConstant(ByteShift * 8, MVT::i8));
7708 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7712 // PSLLDQ : (little-endian) left byte shift
7713 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7714 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7715 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7716 bool ZeroableLeft = true;
7717 for (int i = 0; i < Shift; i++) {
7718 ZeroableLeft &= Zeroable[i];
7722 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7723 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7725 if (ValidShiftLeft1 || ValidShiftLeft2) {
7726 // Cast the inputs to v2i64 to match PSLLDQ.
7727 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7728 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7729 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7730 DAG.getConstant(ByteShift * 8, MVT::i8));
7731 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7739 /// \brief Lower a vector shuffle as a zero or any extension.
7741 /// Given a specific number of elements, element bit width, and extension
7742 /// stride, produce either a zero or any extension based on the available
7743 /// features of the subtarget.
7744 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7745 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7746 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7747 assert(Scale > 1 && "Need a scale to extend.");
7748 int EltBits = VT.getSizeInBits() / NumElements;
7749 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7750 "Only 8, 16, and 32 bit elements can be extended.");
7751 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7753 // Found a valid zext mask! Try various lowering strategies based on the
7754 // input type and available ISA extensions.
7755 if (Subtarget->hasSSE41()) {
7756 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7757 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7758 NumElements / Scale);
7759 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7760 return DAG.getNode(ISD::BITCAST, DL, VT,
7761 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7764 // For any extends we can cheat for larger element sizes and use shuffle
7765 // instructions that can fold with a load and/or copy.
7766 if (AnyExt && EltBits == 32) {
7767 int PSHUFDMask[4] = {0, -1, 1, -1};
7769 ISD::BITCAST, DL, VT,
7770 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7771 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7772 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7774 if (AnyExt && EltBits == 16 && Scale > 2) {
7775 int PSHUFDMask[4] = {0, -1, 0, -1};
7776 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7777 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7778 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7779 int PSHUFHWMask[4] = {1, -1, -1, -1};
7781 ISD::BITCAST, DL, VT,
7782 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7783 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7784 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7787 // If this would require more than 2 unpack instructions to expand, use
7788 // pshufb when available. We can only use more than 2 unpack instructions
7789 // when zero extending i8 elements which also makes it easier to use pshufb.
7790 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7791 assert(NumElements == 16 && "Unexpected byte vector width!");
7792 SDValue PSHUFBMask[16];
7793 for (int i = 0; i < 16; ++i)
7795 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7796 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7797 return DAG.getNode(ISD::BITCAST, DL, VT,
7798 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7799 DAG.getNode(ISD::BUILD_VECTOR, DL,
7800 MVT::v16i8, PSHUFBMask)));
7803 // Otherwise emit a sequence of unpacks.
7805 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7806 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7807 : getZeroVector(InputVT, Subtarget, DAG, DL);
7808 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7809 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7813 } while (Scale > 1);
7814 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7817 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7819 /// This routine will try to do everything in its power to cleverly lower
7820 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7821 /// check for the profitability of this lowering, it tries to aggressively
7822 /// match this pattern. It will use all of the micro-architectural details it
7823 /// can to emit an efficient lowering. It handles both blends with all-zero
7824 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7825 /// masking out later).
7827 /// The reason we have dedicated lowering for zext-style shuffles is that they
7828 /// are both incredibly common and often quite performance sensitive.
7829 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7830 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7831 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7832 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7834 int Bits = VT.getSizeInBits();
7835 int NumElements = Mask.size();
7837 // Define a helper function to check a particular ext-scale and lower to it if
7839 auto Lower = [&](int Scale) -> SDValue {
7842 for (int i = 0; i < NumElements; ++i) {
7844 continue; // Valid anywhere but doesn't tell us anything.
7845 if (i % Scale != 0) {
7846 // Each of the extend elements needs to be zeroable.
7850 // We no lorger are in the anyext case.
7855 // Each of the base elements needs to be consecutive indices into the
7856 // same input vector.
7857 SDValue V = Mask[i] < NumElements ? V1 : V2;
7860 else if (InputV != V)
7861 return SDValue(); // Flip-flopping inputs.
7863 if (Mask[i] % NumElements != i / Scale)
7864 return SDValue(); // Non-consecutive strided elemenst.
7867 // If we fail to find an input, we have a zero-shuffle which should always
7868 // have already been handled.
7869 // FIXME: Maybe handle this here in case during blending we end up with one?
7873 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7874 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7877 // The widest scale possible for extending is to a 64-bit integer.
7878 assert(Bits % 64 == 0 &&
7879 "The number of bits in a vector must be divisible by 64 on x86!");
7880 int NumExtElements = Bits / 64;
7882 // Each iteration, try extending the elements half as much, but into twice as
7884 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7885 assert(NumElements % NumExtElements == 0 &&
7886 "The input vector size must be divisble by the extended size.");
7887 if (SDValue V = Lower(NumElements / NumExtElements))
7891 // No viable ext lowering found.
7895 /// \brief Try to get a scalar value for a specific element of a vector.
7897 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7898 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7899 SelectionDAG &DAG) {
7900 MVT VT = V.getSimpleValueType();
7901 MVT EltVT = VT.getVectorElementType();
7902 while (V.getOpcode() == ISD::BITCAST)
7903 V = V.getOperand(0);
7904 // If the bitcasts shift the element size, we can't extract an equivalent
7906 MVT NewVT = V.getSimpleValueType();
7907 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7910 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7911 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7912 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7917 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7919 /// This is particularly important because the set of instructions varies
7920 /// significantly based on whether the operand is a load or not.
7921 static bool isShuffleFoldableLoad(SDValue V) {
7922 while (V.getOpcode() == ISD::BITCAST)
7923 V = V.getOperand(0);
7925 return ISD::isNON_EXTLoad(V.getNode());
7928 /// \brief Try to lower insertion of a single element into a zero vector.
7930 /// This is a common pattern that we have especially efficient patterns to lower
7931 /// across all subtarget feature sets.
7932 static SDValue lowerVectorShuffleAsElementInsertion(
7933 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7934 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7935 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7937 MVT EltVT = VT.getVectorElementType();
7939 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7940 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7942 bool IsV1Zeroable = true;
7943 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7944 if (i != V2Index && !Zeroable[i]) {
7945 IsV1Zeroable = false;
7949 // Check for a single input from a SCALAR_TO_VECTOR node.
7950 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7951 // all the smarts here sunk into that routine. However, the current
7952 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7953 // vector shuffle lowering is dead.
7954 if (SDValue V2S = getScalarValueForVectorElement(
7955 V2, Mask[V2Index] - Mask.size(), DAG)) {
7956 // We need to zext the scalar if it is smaller than an i32.
7957 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7958 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7959 // Using zext to expand a narrow element won't work for non-zero
7964 // Zero-extend directly to i32.
7966 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7968 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7969 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7970 EltVT == MVT::i16) {
7971 // Either not inserting from the low element of the input or the input
7972 // element size is too small to use VZEXT_MOVL to clear the high bits.
7976 if (!IsV1Zeroable) {
7977 // If V1 can't be treated as a zero vector we have fewer options to lower
7978 // this. We can't support integer vectors or non-zero targets cheaply, and
7979 // the V1 elements can't be permuted in any way.
7980 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7981 if (!VT.isFloatingPoint() || V2Index != 0)
7983 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7984 V1Mask[V2Index] = -1;
7985 if (!isNoopShuffleMask(V1Mask))
7987 // This is essentially a special case blend operation, but if we have
7988 // general purpose blend operations, they are always faster. Bail and let
7989 // the rest of the lowering handle these as blends.
7990 if (Subtarget->hasSSE41())
7993 // Otherwise, use MOVSD or MOVSS.
7994 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7995 "Only two types of floating point element types to handle!");
7996 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8000 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8002 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8005 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8006 // the desired position. Otherwise it is more efficient to do a vector
8007 // shift left. We know that we can do a vector shift left because all
8008 // the inputs are zero.
8009 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8010 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8011 V2Shuffle[V2Index] = 0;
8012 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8014 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8016 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8018 V2Index * EltVT.getSizeInBits(),
8019 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8020 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8026 /// \brief Try to lower broadcast of a single element.
8028 /// For convenience, this code also bundles all of the subtarget feature set
8029 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8030 /// a convenient way to factor it out.
8031 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8033 const X86Subtarget *Subtarget,
8034 SelectionDAG &DAG) {
8035 if (!Subtarget->hasAVX())
8037 if (VT.isInteger() && !Subtarget->hasAVX2())
8040 // Check that the mask is a broadcast.
8041 int BroadcastIdx = -1;
8043 if (M >= 0 && BroadcastIdx == -1)
8045 else if (M >= 0 && M != BroadcastIdx)
8048 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8049 "a sorted mask where the broadcast "
8052 // Go up the chain of (vector) values to try and find a scalar load that
8053 // we can combine with the broadcast.
8055 switch (V.getOpcode()) {
8056 case ISD::CONCAT_VECTORS: {
8057 int OperandSize = Mask.size() / V.getNumOperands();
8058 V = V.getOperand(BroadcastIdx / OperandSize);
8059 BroadcastIdx %= OperandSize;
8063 case ISD::INSERT_SUBVECTOR: {
8064 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8065 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8069 int BeginIdx = (int)ConstantIdx->getZExtValue();
8071 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8072 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8073 BroadcastIdx -= BeginIdx;
8084 // Check if this is a broadcast of a scalar. We special case lowering
8085 // for scalars so that we can more effectively fold with loads.
8086 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8087 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8088 V = V.getOperand(BroadcastIdx);
8090 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8092 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8094 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8095 // We can't broadcast from a vector register w/o AVX2, and we can only
8096 // broadcast from the zero-element of a vector register.
8100 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8103 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8105 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8106 /// support for floating point shuffles but not integer shuffles. These
8107 /// instructions will incur a domain crossing penalty on some chips though so
8108 /// it is better to avoid lowering through this for integer vectors where
8110 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8111 const X86Subtarget *Subtarget,
8112 SelectionDAG &DAG) {
8114 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8115 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8116 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8117 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8118 ArrayRef<int> Mask = SVOp->getMask();
8119 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8121 if (isSingleInputShuffleMask(Mask)) {
8122 // Straight shuffle of a single input vector. Simulate this by using the
8123 // single input as both of the "inputs" to this instruction..
8124 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8126 if (Subtarget->hasAVX()) {
8127 // If we have AVX, we can use VPERMILPS which will allow folding a load
8128 // into the shuffle.
8129 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8130 DAG.getConstant(SHUFPDMask, MVT::i8));
8133 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8134 DAG.getConstant(SHUFPDMask, MVT::i8));
8136 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8137 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8139 // Use dedicated unpack instructions for masks that match their pattern.
8140 if (isShuffleEquivalent(Mask, 0, 2))
8141 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8142 if (isShuffleEquivalent(Mask, 1, 3))
8143 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8145 // If we have a single input, insert that into V1 if we can do so cheaply.
8146 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8147 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8148 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8150 // Try inverting the insertion since for v2 masks it is easy to do and we
8151 // can't reliably sort the mask one way or the other.
8152 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8153 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8154 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8155 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8159 // Try to use one of the special instruction patterns to handle two common
8160 // blend patterns if a zero-blend above didn't work.
8161 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8162 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8163 // We can either use a special instruction to load over the low double or
8164 // to move just the low double.
8166 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8168 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8170 if (Subtarget->hasSSE41())
8171 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8175 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8176 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8177 DAG.getConstant(SHUFPDMask, MVT::i8));
8180 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8182 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8183 /// the integer unit to minimize domain crossing penalties. However, for blends
8184 /// it falls back to the floating point shuffle operation with appropriate bit
8186 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8187 const X86Subtarget *Subtarget,
8188 SelectionDAG &DAG) {
8190 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8191 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8192 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8193 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8194 ArrayRef<int> Mask = SVOp->getMask();
8195 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8197 if (isSingleInputShuffleMask(Mask)) {
8198 // Check for being able to broadcast a single element.
8199 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8200 Mask, Subtarget, DAG))
8203 // Straight shuffle of a single input vector. For everything from SSE2
8204 // onward this has a single fast instruction with no scary immediates.
8205 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8206 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8207 int WidenedMask[4] = {
8208 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8209 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8211 ISD::BITCAST, DL, MVT::v2i64,
8212 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8213 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8216 // Try to use byte shift instructions.
8217 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8218 DL, MVT::v2i64, V1, V2, Mask, DAG))
8221 // If we have a single input from V2 insert that into V1 if we can do so
8223 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8224 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8225 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8227 // Try inverting the insertion since for v2 masks it is easy to do and we
8228 // can't reliably sort the mask one way or the other.
8229 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8230 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8231 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8232 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8236 // Use dedicated unpack instructions for masks that match their pattern.
8237 if (isShuffleEquivalent(Mask, 0, 2))
8238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8239 if (isShuffleEquivalent(Mask, 1, 3))
8240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8242 if (Subtarget->hasSSE41())
8243 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8247 // Try to use byte rotation instructions.
8248 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8249 if (Subtarget->hasSSSE3())
8250 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8251 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8254 // We implement this with SHUFPD which is pretty lame because it will likely
8255 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8256 // However, all the alternatives are still more cycles and newer chips don't
8257 // have this problem. It would be really nice if x86 had better shuffles here.
8258 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8259 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8260 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8261 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8264 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8266 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8267 /// It makes no assumptions about whether this is the *best* lowering, it simply
8269 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8270 ArrayRef<int> Mask, SDValue V1,
8271 SDValue V2, SelectionDAG &DAG) {
8272 SDValue LowV = V1, HighV = V2;
8273 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8276 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8278 if (NumV2Elements == 1) {
8280 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8283 // Compute the index adjacent to V2Index and in the same half by toggling
8285 int V2AdjIndex = V2Index ^ 1;
8287 if (Mask[V2AdjIndex] == -1) {
8288 // Handles all the cases where we have a single V2 element and an undef.
8289 // This will only ever happen in the high lanes because we commute the
8290 // vector otherwise.
8292 std::swap(LowV, HighV);
8293 NewMask[V2Index] -= 4;
8295 // Handle the case where the V2 element ends up adjacent to a V1 element.
8296 // To make this work, blend them together as the first step.
8297 int V1Index = V2AdjIndex;
8298 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8299 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8300 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8302 // Now proceed to reconstruct the final blend as we have the necessary
8303 // high or low half formed.
8310 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8311 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8313 } else if (NumV2Elements == 2) {
8314 if (Mask[0] < 4 && Mask[1] < 4) {
8315 // Handle the easy case where we have V1 in the low lanes and V2 in the
8319 } else if (Mask[2] < 4 && Mask[3] < 4) {
8320 // We also handle the reversed case because this utility may get called
8321 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8322 // arrange things in the right direction.
8328 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8329 // trying to place elements directly, just blend them and set up the final
8330 // shuffle to place them.
8332 // The first two blend mask elements are for V1, the second two are for
8334 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8335 Mask[2] < 4 ? Mask[2] : Mask[3],
8336 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8337 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8338 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8339 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8341 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8344 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8345 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8346 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8347 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8350 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8351 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8354 /// \brief Lower 4-lane 32-bit floating point shuffles.
8356 /// Uses instructions exclusively from the floating point unit to minimize
8357 /// domain crossing penalties, as these are sufficient to implement all v4f32
8359 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8360 const X86Subtarget *Subtarget,
8361 SelectionDAG &DAG) {
8363 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8364 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8365 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8367 ArrayRef<int> Mask = SVOp->getMask();
8368 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8371 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8373 if (NumV2Elements == 0) {
8374 // Check for being able to broadcast a single element.
8375 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8376 Mask, Subtarget, DAG))
8379 if (Subtarget->hasAVX()) {
8380 // If we have AVX, we can use VPERMILPS which will allow folding a load
8381 // into the shuffle.
8382 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8383 getV4X86ShuffleImm8ForMask(Mask, DAG));
8386 // Otherwise, use a straight shuffle of a single input vector. We pass the
8387 // input vector to both operands to simulate this with a SHUFPS.
8388 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8389 getV4X86ShuffleImm8ForMask(Mask, DAG));
8392 // Use dedicated unpack instructions for masks that match their pattern.
8393 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8394 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8395 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8396 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8398 // There are special ways we can lower some single-element blends. However, we
8399 // have custom ways we can lower more complex single-element blends below that
8400 // we defer to if both this and BLENDPS fail to match, so restrict this to
8401 // when the V2 input is targeting element 0 of the mask -- that is the fast
8403 if (NumV2Elements == 1 && Mask[0] >= 4)
8404 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8405 Mask, Subtarget, DAG))
8408 if (Subtarget->hasSSE41())
8409 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8413 // Check for whether we can use INSERTPS to perform the blend. We only use
8414 // INSERTPS when the V1 elements are already in the correct locations
8415 // because otherwise we can just always use two SHUFPS instructions which
8416 // are much smaller to encode than a SHUFPS and an INSERTPS.
8417 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8419 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8422 // When using INSERTPS we can zero any lane of the destination. Collect
8423 // the zero inputs into a mask and drop them from the lanes of V1 which
8424 // actually need to be present as inputs to the INSERTPS.
8425 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8427 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8428 bool InsertNeedsShuffle = false;
8430 for (int i = 0; i < 4; ++i)
8434 } else if (Mask[i] != i) {
8435 InsertNeedsShuffle = true;
8440 // We don't want to use INSERTPS or other insertion techniques if it will
8441 // require shuffling anyways.
8442 if (!InsertNeedsShuffle) {
8443 // If all of V1 is zeroable, replace it with undef.
8444 if ((ZMask | 1 << V2Index) == 0xF)
8445 V1 = DAG.getUNDEF(MVT::v4f32);
8447 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8448 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8450 // Insert the V2 element into the desired position.
8451 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8452 DAG.getConstant(InsertPSMask, MVT::i8));
8456 // Otherwise fall back to a SHUFPS lowering strategy.
8457 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8460 /// \brief Lower 4-lane i32 vector shuffles.
8462 /// We try to handle these with integer-domain shuffles where we can, but for
8463 /// blends we use the floating point domain blend instructions.
8464 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8465 const X86Subtarget *Subtarget,
8466 SelectionDAG &DAG) {
8468 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8469 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8470 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8472 ArrayRef<int> Mask = SVOp->getMask();
8473 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8475 // Whenever we can lower this as a zext, that instruction is strictly faster
8476 // than any alternative. It also allows us to fold memory operands into the
8477 // shuffle in many cases.
8478 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8479 Mask, Subtarget, DAG))
8483 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8485 if (NumV2Elements == 0) {
8486 // Check for being able to broadcast a single element.
8487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8488 Mask, Subtarget, DAG))
8491 // Straight shuffle of a single input vector. For everything from SSE2
8492 // onward this has a single fast instruction with no scary immediates.
8493 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8494 // but we aren't actually going to use the UNPCK instruction because doing
8495 // so prevents folding a load into this instruction or making a copy.
8496 const int UnpackLoMask[] = {0, 0, 1, 1};
8497 const int UnpackHiMask[] = {2, 2, 3, 3};
8498 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8499 Mask = UnpackLoMask;
8500 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8501 Mask = UnpackHiMask;
8503 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8504 getV4X86ShuffleImm8ForMask(Mask, DAG));
8507 // Try to use byte shift instructions.
8508 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8509 DL, MVT::v4i32, V1, V2, Mask, DAG))
8512 // There are special ways we can lower some single-element blends.
8513 if (NumV2Elements == 1)
8514 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8515 Mask, Subtarget, DAG))
8518 // Use dedicated unpack instructions for masks that match their pattern.
8519 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8520 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8521 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8522 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8524 if (Subtarget->hasSSE41())
8525 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8529 // Try to use byte rotation instructions.
8530 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8531 if (Subtarget->hasSSSE3())
8532 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8533 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8536 // We implement this with SHUFPS because it can blend from two vectors.
8537 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8538 // up the inputs, bypassing domain shift penalties that we would encur if we
8539 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8541 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8542 DAG.getVectorShuffle(
8544 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8545 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8548 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8549 /// shuffle lowering, and the most complex part.
8551 /// The lowering strategy is to try to form pairs of input lanes which are
8552 /// targeted at the same half of the final vector, and then use a dword shuffle
8553 /// to place them onto the right half, and finally unpack the paired lanes into
8554 /// their final position.
8556 /// The exact breakdown of how to form these dword pairs and align them on the
8557 /// correct sides is really tricky. See the comments within the function for
8558 /// more of the details.
8559 static SDValue lowerV8I16SingleInputVectorShuffle(
8560 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8561 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8562 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8563 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8564 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8566 SmallVector<int, 4> LoInputs;
8567 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8568 [](int M) { return M >= 0; });
8569 std::sort(LoInputs.begin(), LoInputs.end());
8570 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8571 SmallVector<int, 4> HiInputs;
8572 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8573 [](int M) { return M >= 0; });
8574 std::sort(HiInputs.begin(), HiInputs.end());
8575 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8577 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8578 int NumHToL = LoInputs.size() - NumLToL;
8580 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8581 int NumHToH = HiInputs.size() - NumLToH;
8582 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8583 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8584 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8585 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8587 // Check for being able to broadcast a single element.
8588 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8589 Mask, Subtarget, DAG))
8592 // Try to use byte shift instructions.
8593 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8594 DL, MVT::v8i16, V, V, Mask, DAG))
8597 // Use dedicated unpack instructions for masks that match their pattern.
8598 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8599 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8600 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8601 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8603 // Try to use byte rotation instructions.
8604 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8605 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8608 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8609 // such inputs we can swap two of the dwords across the half mark and end up
8610 // with <=2 inputs to each half in each half. Once there, we can fall through
8611 // to the generic code below. For example:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8616 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8617 // and an existing 2-into-2 on the other half. In this case we may have to
8618 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8619 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8620 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8621 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8622 // half than the one we target for fixing) will be fixed when we re-enter this
8623 // path. We will also combine away any sequence of PSHUFD instructions that
8624 // result into a single instruction. Here is an example of the tricky case:
8626 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8627 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8629 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8631 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8632 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8634 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8635 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8637 // The result is fine to be handled by the generic logic.
8638 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8639 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8640 int AOffset, int BOffset) {
8641 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8642 "Must call this with A having 3 or 1 inputs from the A half.");
8643 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8644 "Must call this with B having 1 or 3 inputs from the B half.");
8645 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8646 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8648 // Compute the index of dword with only one word among the three inputs in
8649 // a half by taking the sum of the half with three inputs and subtracting
8650 // the sum of the actual three inputs. The difference is the remaining
8653 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8654 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8655 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8656 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8657 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8658 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8659 int TripleNonInputIdx =
8660 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8661 TripleDWord = TripleNonInputIdx / 2;
8663 // We use xor with one to compute the adjacent DWord to whichever one the
8665 OneInputDWord = (OneInput / 2) ^ 1;
8667 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8668 // and BToA inputs. If there is also such a problem with the BToB and AToB
8669 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8670 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8671 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8672 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8673 // Compute how many inputs will be flipped by swapping these DWords. We
8675 // to balance this to ensure we don't form a 3-1 shuffle in the other
8677 int NumFlippedAToBInputs =
8678 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8679 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8680 int NumFlippedBToBInputs =
8681 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8682 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8683 if ((NumFlippedAToBInputs == 1 &&
8684 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8685 (NumFlippedBToBInputs == 1 &&
8686 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8687 // We choose whether to fix the A half or B half based on whether that
8688 // half has zero flipped inputs. At zero, we may not be able to fix it
8689 // with that half. We also bias towards fixing the B half because that
8690 // will more commonly be the high half, and we have to bias one way.
8691 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8692 ArrayRef<int> Inputs) {
8693 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8694 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8695 PinnedIdx ^ 1) != Inputs.end();
8696 // Determine whether the free index is in the flipped dword or the
8697 // unflipped dword based on where the pinned index is. We use this bit
8698 // in an xor to conditionally select the adjacent dword.
8699 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8700 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8701 FixFreeIdx) != Inputs.end();
8702 if (IsFixIdxInput == IsFixFreeIdxInput)
8704 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8705 FixFreeIdx) != Inputs.end();
8706 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8707 "We need to be changing the number of flipped inputs!");
8708 int PSHUFHalfMask[] = {0, 1, 2, 3};
8709 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8710 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8712 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8715 if (M != -1 && M == FixIdx)
8717 else if (M != -1 && M == FixFreeIdx)
8720 if (NumFlippedBToBInputs != 0) {
8722 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8723 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8725 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8727 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8728 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8733 int PSHUFDMask[] = {0, 1, 2, 3};
8734 PSHUFDMask[ADWord] = BDWord;
8735 PSHUFDMask[BDWord] = ADWord;
8736 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8737 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8738 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8739 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8741 // Adjust the mask to match the new locations of A and B.
8743 if (M != -1 && M/2 == ADWord)
8744 M = 2 * BDWord + M % 2;
8745 else if (M != -1 && M/2 == BDWord)
8746 M = 2 * ADWord + M % 2;
8748 // Recurse back into this routine to re-compute state now that this isn't
8749 // a 3 and 1 problem.
8750 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8753 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8754 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8755 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8756 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8758 // At this point there are at most two inputs to the low and high halves from
8759 // each half. That means the inputs can always be grouped into dwords and
8760 // those dwords can then be moved to the correct half with a dword shuffle.
8761 // We use at most one low and one high word shuffle to collect these paired
8762 // inputs into dwords, and finally a dword shuffle to place them.
8763 int PSHUFLMask[4] = {-1, -1, -1, -1};
8764 int PSHUFHMask[4] = {-1, -1, -1, -1};
8765 int PSHUFDMask[4] = {-1, -1, -1, -1};
8767 // First fix the masks for all the inputs that are staying in their
8768 // original halves. This will then dictate the targets of the cross-half
8770 auto fixInPlaceInputs =
8771 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8772 MutableArrayRef<int> SourceHalfMask,
8773 MutableArrayRef<int> HalfMask, int HalfOffset) {
8774 if (InPlaceInputs.empty())
8776 if (InPlaceInputs.size() == 1) {
8777 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8778 InPlaceInputs[0] - HalfOffset;
8779 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8782 if (IncomingInputs.empty()) {
8783 // Just fix all of the in place inputs.
8784 for (int Input : InPlaceInputs) {
8785 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8786 PSHUFDMask[Input / 2] = Input / 2;
8791 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8792 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8793 InPlaceInputs[0] - HalfOffset;
8794 // Put the second input next to the first so that they are packed into
8795 // a dword. We find the adjacent index by toggling the low bit.
8796 int AdjIndex = InPlaceInputs[0] ^ 1;
8797 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8798 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8799 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8801 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8802 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8804 // Now gather the cross-half inputs and place them into a free dword of
8805 // their target half.
8806 // FIXME: This operation could almost certainly be simplified dramatically to
8807 // look more like the 3-1 fixing operation.
8808 auto moveInputsToRightHalf = [&PSHUFDMask](
8809 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8810 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8811 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8813 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8814 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8816 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8818 int LowWord = Word & ~1;
8819 int HighWord = Word | 1;
8820 return isWordClobbered(SourceHalfMask, LowWord) ||
8821 isWordClobbered(SourceHalfMask, HighWord);
8824 if (IncomingInputs.empty())
8827 if (ExistingInputs.empty()) {
8828 // Map any dwords with inputs from them into the right half.
8829 for (int Input : IncomingInputs) {
8830 // If the source half mask maps over the inputs, turn those into
8831 // swaps and use the swapped lane.
8832 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8833 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8834 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8835 Input - SourceOffset;
8836 // We have to swap the uses in our half mask in one sweep.
8837 for (int &M : HalfMask)
8838 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8840 else if (M == Input)
8841 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8843 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8844 Input - SourceOffset &&
8845 "Previous placement doesn't match!");
8847 // Note that this correctly re-maps both when we do a swap and when
8848 // we observe the other side of the swap above. We rely on that to
8849 // avoid swapping the members of the input list directly.
8850 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8853 // Map the input's dword into the correct half.
8854 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8855 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8857 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8859 "Previous placement doesn't match!");
8862 // And just directly shift any other-half mask elements to be same-half
8863 // as we will have mirrored the dword containing the element into the
8864 // same position within that half.
8865 for (int &M : HalfMask)
8866 if (M >= SourceOffset && M < SourceOffset + 4) {
8867 M = M - SourceOffset + DestOffset;
8868 assert(M >= 0 && "This should never wrap below zero!");
8873 // Ensure we have the input in a viable dword of its current half. This
8874 // is particularly tricky because the original position may be clobbered
8875 // by inputs being moved and *staying* in that half.
8876 if (IncomingInputs.size() == 1) {
8877 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8878 int InputFixed = std::find(std::begin(SourceHalfMask),
8879 std::end(SourceHalfMask), -1) -
8880 std::begin(SourceHalfMask) + SourceOffset;
8881 SourceHalfMask[InputFixed - SourceOffset] =
8882 IncomingInputs[0] - SourceOffset;
8883 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8885 IncomingInputs[0] = InputFixed;
8887 } else if (IncomingInputs.size() == 2) {
8888 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8889 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8890 // We have two non-adjacent or clobbered inputs we need to extract from
8891 // the source half. To do this, we need to map them into some adjacent
8892 // dword slot in the source mask.
8893 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8894 IncomingInputs[1] - SourceOffset};
8896 // If there is a free slot in the source half mask adjacent to one of
8897 // the inputs, place the other input in it. We use (Index XOR 1) to
8898 // compute an adjacent index.
8899 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8900 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8901 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8902 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8903 InputsFixed[1] = InputsFixed[0] ^ 1;
8904 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8905 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8906 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8907 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8908 InputsFixed[0] = InputsFixed[1] ^ 1;
8909 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8910 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8911 // The two inputs are in the same DWord but it is clobbered and the
8912 // adjacent DWord isn't used at all. Move both inputs to the free
8914 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8915 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8916 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8917 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8919 // The only way we hit this point is if there is no clobbering
8920 // (because there are no off-half inputs to this half) and there is no
8921 // free slot adjacent to one of the inputs. In this case, we have to
8922 // swap an input with a non-input.
8923 for (int i = 0; i < 4; ++i)
8924 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8925 "We can't handle any clobbers here!");
8926 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8927 "Cannot have adjacent inputs here!");
8929 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8930 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8932 // We also have to update the final source mask in this case because
8933 // it may need to undo the above swap.
8934 for (int &M : FinalSourceHalfMask)
8935 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8936 M = InputsFixed[1] + SourceOffset;
8937 else if (M == InputsFixed[1] + SourceOffset)
8938 M = (InputsFixed[0] ^ 1) + SourceOffset;
8940 InputsFixed[1] = InputsFixed[0] ^ 1;
8943 // Point everything at the fixed inputs.
8944 for (int &M : HalfMask)
8945 if (M == IncomingInputs[0])
8946 M = InputsFixed[0] + SourceOffset;
8947 else if (M == IncomingInputs[1])
8948 M = InputsFixed[1] + SourceOffset;
8950 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8951 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8954 llvm_unreachable("Unhandled input size!");
8957 // Now hoist the DWord down to the right half.
8958 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8959 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8960 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8961 for (int &M : HalfMask)
8962 for (int Input : IncomingInputs)
8964 M = FreeDWord * 2 + Input % 2;
8966 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8967 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8968 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8969 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8971 // Now enact all the shuffles we've computed to move the inputs into their
8973 if (!isNoopShuffleMask(PSHUFLMask))
8974 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8975 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8976 if (!isNoopShuffleMask(PSHUFHMask))
8977 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8978 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8979 if (!isNoopShuffleMask(PSHUFDMask))
8980 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8981 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8982 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8983 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8985 // At this point, each half should contain all its inputs, and we can then
8986 // just shuffle them into their final position.
8987 assert(std::count_if(LoMask.begin(), LoMask.end(),
8988 [](int M) { return M >= 4; }) == 0 &&
8989 "Failed to lift all the high half inputs to the low mask!");
8990 assert(std::count_if(HiMask.begin(), HiMask.end(),
8991 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8992 "Failed to lift all the low half inputs to the high mask!");
8994 // Do a half shuffle for the low mask.
8995 if (!isNoopShuffleMask(LoMask))
8996 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8997 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8999 // Do a half shuffle with the high mask after shifting its values down.
9000 for (int &M : HiMask)
9003 if (!isNoopShuffleMask(HiMask))
9004 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9005 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9010 /// \brief Detect whether the mask pattern should be lowered through
9013 /// This essentially tests whether viewing the mask as an interleaving of two
9014 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9015 /// lowering it through interleaving is a significantly better strategy.
9016 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9017 int NumEvenInputs[2] = {0, 0};
9018 int NumOddInputs[2] = {0, 0};
9019 int NumLoInputs[2] = {0, 0};
9020 int NumHiInputs[2] = {0, 0};
9021 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9025 int InputIdx = Mask[i] >= Size;
9028 ++NumLoInputs[InputIdx];
9030 ++NumHiInputs[InputIdx];
9033 ++NumEvenInputs[InputIdx];
9035 ++NumOddInputs[InputIdx];
9038 // The minimum number of cross-input results for both the interleaved and
9039 // split cases. If interleaving results in fewer cross-input results, return
9041 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9042 NumEvenInputs[0] + NumOddInputs[1]);
9043 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9044 NumLoInputs[0] + NumHiInputs[1]);
9045 return InterleavedCrosses < SplitCrosses;
9048 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9050 /// This strategy only works when the inputs from each vector fit into a single
9051 /// half of that vector, and generally there are not so many inputs as to leave
9052 /// the in-place shuffles required highly constrained (and thus expensive). It
9053 /// shifts all the inputs into a single side of both input vectors and then
9054 /// uses an unpack to interleave these inputs in a single vector. At that
9055 /// point, we will fall back on the generic single input shuffle lowering.
9056 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9058 MutableArrayRef<int> Mask,
9059 const X86Subtarget *Subtarget,
9060 SelectionDAG &DAG) {
9061 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9062 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9063 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9064 for (int i = 0; i < 8; ++i)
9065 if (Mask[i] >= 0 && Mask[i] < 4)
9066 LoV1Inputs.push_back(i);
9067 else if (Mask[i] >= 4 && Mask[i] < 8)
9068 HiV1Inputs.push_back(i);
9069 else if (Mask[i] >= 8 && Mask[i] < 12)
9070 LoV2Inputs.push_back(i);
9071 else if (Mask[i] >= 12)
9072 HiV2Inputs.push_back(i);
9074 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9075 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9078 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9079 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9080 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9082 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9083 HiV1Inputs.size() + HiV2Inputs.size();
9085 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9086 ArrayRef<int> HiInputs, bool MoveToLo,
9088 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9089 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9090 if (BadInputs.empty())
9093 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9094 int MoveOffset = MoveToLo ? 0 : 4;
9096 if (GoodInputs.empty()) {
9097 for (int BadInput : BadInputs) {
9098 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9099 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9102 if (GoodInputs.size() == 2) {
9103 // If the low inputs are spread across two dwords, pack them into
9105 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9106 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9107 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9108 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9110 // Otherwise pin the good inputs.
9111 for (int GoodInput : GoodInputs)
9112 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9115 if (BadInputs.size() == 2) {
9116 // If we have two bad inputs then there may be either one or two good
9117 // inputs fixed in place. Find a fixed input, and then find the *other*
9118 // two adjacent indices by using modular arithmetic.
9120 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9121 [](int M) { return M >= 0; }) -
9122 std::begin(MoveMask);
9124 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9125 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9126 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9127 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9128 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9129 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9130 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9132 assert(BadInputs.size() == 1 && "All sizes handled");
9133 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9134 std::end(MoveMask), -1) -
9135 std::begin(MoveMask);
9136 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9137 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9141 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9144 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9146 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9149 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9150 // cross-half traffic in the final shuffle.
9152 // Munge the mask to be a single-input mask after the unpack merges the
9156 M = 2 * (M % 4) + (M / 8);
9158 return DAG.getVectorShuffle(
9159 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9160 DL, MVT::v8i16, V1, V2),
9161 DAG.getUNDEF(MVT::v8i16), Mask);
9164 /// \brief Generic lowering of 8-lane i16 shuffles.
9166 /// This handles both single-input shuffles and combined shuffle/blends with
9167 /// two inputs. The single input shuffles are immediately delegated to
9168 /// a dedicated lowering routine.
9170 /// The blends are lowered in one of three fundamental ways. If there are few
9171 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9172 /// of the input is significantly cheaper when lowered as an interleaving of
9173 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9174 /// halves of the inputs separately (making them have relatively few inputs)
9175 /// and then concatenate them.
9176 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9177 const X86Subtarget *Subtarget,
9178 SelectionDAG &DAG) {
9180 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9181 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9182 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9184 ArrayRef<int> OrigMask = SVOp->getMask();
9185 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9186 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9187 MutableArrayRef<int> Mask(MaskStorage);
9189 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9191 // Whenever we can lower this as a zext, that instruction is strictly faster
9192 // than any alternative.
9193 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9194 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9197 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9198 auto isV2 = [](int M) { return M >= 8; };
9200 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9201 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9203 if (NumV2Inputs == 0)
9204 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9206 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9207 "to be V1-input shuffles.");
9209 // Try to use byte shift instructions.
9210 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9211 DL, MVT::v8i16, V1, V2, Mask, DAG))
9214 // There are special ways we can lower some single-element blends.
9215 if (NumV2Inputs == 1)
9216 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9217 Mask, Subtarget, DAG))
9220 // Use dedicated unpack instructions for masks that match their pattern.
9221 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9222 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9223 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9224 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9226 if (Subtarget->hasSSE41())
9227 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9231 // Try to use byte rotation instructions.
9232 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9233 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9236 if (NumV1Inputs + NumV2Inputs <= 4)
9237 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9239 // Check whether an interleaving lowering is likely to be more efficient.
9240 // This isn't perfect but it is a strong heuristic that tends to work well on
9241 // the kinds of shuffles that show up in practice.
9243 // FIXME: Handle 1x, 2x, and 4x interleaving.
9244 if (shouldLowerAsInterleaving(Mask)) {
9245 // FIXME: Figure out whether we should pack these into the low or high
9248 int EMask[8], OMask[8];
9249 for (int i = 0; i < 4; ++i) {
9250 EMask[i] = Mask[2*i];
9251 OMask[i] = Mask[2*i + 1];
9256 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9257 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9259 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9262 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9263 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9265 for (int i = 0; i < 4; ++i) {
9266 LoBlendMask[i] = Mask[i];
9267 HiBlendMask[i] = Mask[i + 4];
9270 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9271 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9272 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9273 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9275 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9276 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9279 /// \brief Check whether a compaction lowering can be done by dropping even
9280 /// elements and compute how many times even elements must be dropped.
9282 /// This handles shuffles which take every Nth element where N is a power of
9283 /// two. Example shuffle masks:
9285 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9286 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9287 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9288 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9289 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9290 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9292 /// Any of these lanes can of course be undef.
9294 /// This routine only supports N <= 3.
9295 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9298 /// \returns N above, or the number of times even elements must be dropped if
9299 /// there is such a number. Otherwise returns zero.
9300 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9301 // Figure out whether we're looping over two inputs or just one.
9302 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9304 // The modulus for the shuffle vector entries is based on whether this is
9305 // a single input or not.
9306 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9307 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9308 "We should only be called with masks with a power-of-2 size!");
9310 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9312 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9313 // and 2^3 simultaneously. This is because we may have ambiguity with
9314 // partially undef inputs.
9315 bool ViableForN[3] = {true, true, true};
9317 for (int i = 0, e = Mask.size(); i < e; ++i) {
9318 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9323 bool IsAnyViable = false;
9324 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9325 if (ViableForN[j]) {
9328 // The shuffle mask must be equal to (i * 2^N) % M.
9329 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9332 ViableForN[j] = false;
9334 // Early exit if we exhaust the possible powers of two.
9339 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9343 // Return 0 as there is no viable power of two.
9347 /// \brief Generic lowering of v16i8 shuffles.
9349 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9350 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9351 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9352 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9354 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9355 const X86Subtarget *Subtarget,
9356 SelectionDAG &DAG) {
9358 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9359 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9360 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9361 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9362 ArrayRef<int> OrigMask = SVOp->getMask();
9363 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9365 // Try to use byte shift instructions.
9366 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9367 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9370 // Try to use byte rotation instructions.
9371 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9372 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9375 // Try to use a zext lowering.
9376 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9377 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9380 int MaskStorage[16] = {
9381 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9382 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9383 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9384 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9385 MutableArrayRef<int> Mask(MaskStorage);
9386 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9387 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9390 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9392 // For single-input shuffles, there are some nicer lowering tricks we can use.
9393 if (NumV2Elements == 0) {
9394 // Check for being able to broadcast a single element.
9395 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9396 Mask, Subtarget, DAG))
9399 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9400 // Notably, this handles splat and partial-splat shuffles more efficiently.
9401 // However, it only makes sense if the pre-duplication shuffle simplifies
9402 // things significantly. Currently, this means we need to be able to
9403 // express the pre-duplication shuffle as an i16 shuffle.
9405 // FIXME: We should check for other patterns which can be widened into an
9406 // i16 shuffle as well.
9407 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9408 for (int i = 0; i < 16; i += 2)
9409 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9414 auto tryToWidenViaDuplication = [&]() -> SDValue {
9415 if (!canWidenViaDuplication(Mask))
9417 SmallVector<int, 4> LoInputs;
9418 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9419 [](int M) { return M >= 0 && M < 8; });
9420 std::sort(LoInputs.begin(), LoInputs.end());
9421 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9423 SmallVector<int, 4> HiInputs;
9424 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9425 [](int M) { return M >= 8; });
9426 std::sort(HiInputs.begin(), HiInputs.end());
9427 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9430 bool TargetLo = LoInputs.size() >= HiInputs.size();
9431 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9432 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9434 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9435 SmallDenseMap<int, int, 8> LaneMap;
9436 for (int I : InPlaceInputs) {
9437 PreDupI16Shuffle[I/2] = I/2;
9440 int j = TargetLo ? 0 : 4, je = j + 4;
9441 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9442 // Check if j is already a shuffle of this input. This happens when
9443 // there are two adjacent bytes after we move the low one.
9444 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9445 // If we haven't yet mapped the input, search for a slot into which
9447 while (j < je && PreDupI16Shuffle[j] != -1)
9451 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9454 // Map this input with the i16 shuffle.
9455 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9458 // Update the lane map based on the mapping we ended up with.
9459 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9462 ISD::BITCAST, DL, MVT::v16i8,
9463 DAG.getVectorShuffle(MVT::v8i16, DL,
9464 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9465 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9467 // Unpack the bytes to form the i16s that will be shuffled into place.
9468 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9469 MVT::v16i8, V1, V1);
9471 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9472 for (int i = 0; i < 16; ++i)
9473 if (Mask[i] != -1) {
9474 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9475 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9476 if (PostDupI16Shuffle[i / 2] == -1)
9477 PostDupI16Shuffle[i / 2] = MappedMask;
9479 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9480 "Conflicting entrties in the original shuffle!");
9483 ISD::BITCAST, DL, MVT::v16i8,
9484 DAG.getVectorShuffle(MVT::v8i16, DL,
9485 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9486 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9488 if (SDValue V = tryToWidenViaDuplication())
9492 // Check whether an interleaving lowering is likely to be more efficient.
9493 // This isn't perfect but it is a strong heuristic that tends to work well on
9494 // the kinds of shuffles that show up in practice.
9496 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9497 if (shouldLowerAsInterleaving(Mask)) {
9498 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9499 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9501 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9502 return (M >= 8 && M < 16) || M >= 24;
9504 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9505 -1, -1, -1, -1, -1, -1, -1, -1};
9506 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9507 -1, -1, -1, -1, -1, -1, -1, -1};
9508 bool UnpackLo = NumLoHalf >= NumHiHalf;
9509 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9510 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9511 for (int i = 0; i < 8; ++i) {
9512 TargetEMask[i] = Mask[2 * i];
9513 TargetOMask[i] = Mask[2 * i + 1];
9516 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9517 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9519 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9520 MVT::v16i8, Evens, Odds);
9523 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9524 // with PSHUFB. It is important to do this before we attempt to generate any
9525 // blends but after all of the single-input lowerings. If the single input
9526 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9527 // want to preserve that and we can DAG combine any longer sequences into
9528 // a PSHUFB in the end. But once we start blending from multiple inputs,
9529 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9530 // and there are *very* few patterns that would actually be faster than the
9531 // PSHUFB approach because of its ability to zero lanes.
9533 // FIXME: The only exceptions to the above are blends which are exact
9534 // interleavings with direct instructions supporting them. We currently don't
9535 // handle those well here.
9536 if (Subtarget->hasSSSE3()) {
9539 for (int i = 0; i < 16; ++i)
9540 if (Mask[i] == -1) {
9541 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9543 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9545 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9547 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9548 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9549 if (isSingleInputShuffleMask(Mask))
9550 return V1; // Single inputs are easy.
9552 // Otherwise, blend the two.
9553 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9554 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9555 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9558 // There are special ways we can lower some single-element blends.
9559 if (NumV2Elements == 1)
9560 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9561 Mask, Subtarget, DAG))
9564 // Check whether a compaction lowering can be done. This handles shuffles
9565 // which take every Nth element for some even N. See the helper function for
9568 // We special case these as they can be particularly efficiently handled with
9569 // the PACKUSB instruction on x86 and they show up in common patterns of
9570 // rearranging bytes to truncate wide elements.
9571 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9572 // NumEvenDrops is the power of two stride of the elements. Another way of
9573 // thinking about it is that we need to drop the even elements this many
9574 // times to get the original input.
9575 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9577 // First we need to zero all the dropped bytes.
9578 assert(NumEvenDrops <= 3 &&
9579 "No support for dropping even elements more than 3 times.");
9580 // We use the mask type to pick which bytes are preserved based on how many
9581 // elements are dropped.
9582 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9583 SDValue ByteClearMask =
9584 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9585 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9586 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9588 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9590 // Now pack things back together.
9591 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9592 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9593 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9594 for (int i = 1; i < NumEvenDrops; ++i) {
9595 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9596 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9602 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9603 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9604 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9605 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9607 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9608 MutableArrayRef<int> V1HalfBlendMask,
9609 MutableArrayRef<int> V2HalfBlendMask) {
9610 for (int i = 0; i < 8; ++i)
9611 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9612 V1HalfBlendMask[i] = HalfMask[i];
9614 } else if (HalfMask[i] >= 16) {
9615 V2HalfBlendMask[i] = HalfMask[i] - 16;
9616 HalfMask[i] = i + 8;
9619 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9620 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9622 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9624 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9625 MutableArrayRef<int> HiBlendMask) {
9627 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9628 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9630 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9631 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9632 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9633 [](int M) { return M >= 0 && M % 2 == 1; })) {
9634 // Use a mask to drop the high bytes.
9635 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9636 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9637 DAG.getConstant(0x00FF, MVT::v8i16));
9639 // This will be a single vector shuffle instead of a blend so nuke V2.
9640 V2 = DAG.getUNDEF(MVT::v8i16);
9642 // Squash the masks to point directly into V1.
9643 for (int &M : LoBlendMask)
9646 for (int &M : HiBlendMask)
9650 // Otherwise just unpack the low half of V into V1 and the high half into
9651 // V2 so that we can blend them as i16s.
9652 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9653 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9654 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9655 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9658 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9659 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9660 return std::make_pair(BlendedLo, BlendedHi);
9662 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9663 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9664 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9666 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9667 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9669 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9672 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9674 /// This routine breaks down the specific type of 128-bit shuffle and
9675 /// dispatches to the lowering routines accordingly.
9676 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9677 MVT VT, const X86Subtarget *Subtarget,
9678 SelectionDAG &DAG) {
9679 switch (VT.SimpleTy) {
9681 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9683 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9685 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9691 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9694 llvm_unreachable("Unimplemented!");
9698 /// \brief Helper function to test whether a shuffle mask could be
9699 /// simplified by widening the elements being shuffled.
9701 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9702 /// leaves it in an unspecified state.
9704 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9705 /// shuffle masks. The latter have the special property of a '-2' representing
9706 /// a zero-ed lane of a vector.
9707 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9708 SmallVectorImpl<int> &WidenedMask) {
9709 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9710 // If both elements are undef, its trivial.
9711 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9712 WidenedMask.push_back(SM_SentinelUndef);
9716 // Check for an undef mask and a mask value properly aligned to fit with
9717 // a pair of values. If we find such a case, use the non-undef mask's value.
9718 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9719 WidenedMask.push_back(Mask[i + 1] / 2);
9722 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9723 WidenedMask.push_back(Mask[i] / 2);
9727 // When zeroing, we need to spread the zeroing across both lanes to widen.
9728 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9729 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9730 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9731 WidenedMask.push_back(SM_SentinelZero);
9737 // Finally check if the two mask values are adjacent and aligned with
9739 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9740 WidenedMask.push_back(Mask[i] / 2);
9744 // Otherwise we can't safely widen the elements used in this shuffle.
9747 assert(WidenedMask.size() == Mask.size() / 2 &&
9748 "Incorrect size of mask after widening the elements!");
9753 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9755 /// This routine just extracts two subvectors, shuffles them independently, and
9756 /// then concatenates them back together. This should work effectively with all
9757 /// AVX vector shuffle types.
9758 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9759 SDValue V2, ArrayRef<int> Mask,
9760 SelectionDAG &DAG) {
9761 assert(VT.getSizeInBits() >= 256 &&
9762 "Only for 256-bit or wider vector shuffles!");
9763 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9764 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9766 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9767 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9769 int NumElements = VT.getVectorNumElements();
9770 int SplitNumElements = NumElements / 2;
9771 MVT ScalarVT = VT.getScalarType();
9772 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9774 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9775 DAG.getIntPtrConstant(0));
9776 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9777 DAG.getIntPtrConstant(SplitNumElements));
9778 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9779 DAG.getIntPtrConstant(0));
9780 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9781 DAG.getIntPtrConstant(SplitNumElements));
9783 // Now create two 4-way blends of these half-width vectors.
9784 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9785 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9786 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9787 for (int i = 0; i < SplitNumElements; ++i) {
9788 int M = HalfMask[i];
9789 if (M >= NumElements) {
9790 if (M >= NumElements + SplitNumElements)
9794 V2BlendMask.push_back(M - NumElements);
9795 V1BlendMask.push_back(-1);
9796 BlendMask.push_back(SplitNumElements + i);
9797 } else if (M >= 0) {
9798 if (M >= SplitNumElements)
9802 V2BlendMask.push_back(-1);
9803 V1BlendMask.push_back(M);
9804 BlendMask.push_back(i);
9806 V2BlendMask.push_back(-1);
9807 V1BlendMask.push_back(-1);
9808 BlendMask.push_back(-1);
9812 // Because the lowering happens after all combining takes place, we need to
9813 // manually combine these blend masks as much as possible so that we create
9814 // a minimal number of high-level vector shuffle nodes.
9816 // First try just blending the halves of V1 or V2.
9817 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9818 return DAG.getUNDEF(SplitVT);
9819 if (!UseLoV2 && !UseHiV2)
9820 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9821 if (!UseLoV1 && !UseHiV1)
9822 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9824 SDValue V1Blend, V2Blend;
9825 if (UseLoV1 && UseHiV1) {
9827 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9829 // We only use half of V1 so map the usage down into the final blend mask.
9830 V1Blend = UseLoV1 ? LoV1 : HiV1;
9831 for (int i = 0; i < SplitNumElements; ++i)
9832 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9833 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9835 if (UseLoV2 && UseHiV2) {
9837 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9839 // We only use half of V2 so map the usage down into the final blend mask.
9840 V2Blend = UseLoV2 ? LoV2 : HiV2;
9841 for (int i = 0; i < SplitNumElements; ++i)
9842 if (BlendMask[i] >= SplitNumElements)
9843 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9845 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9847 SDValue Lo = HalfBlend(LoMask);
9848 SDValue Hi = HalfBlend(HiMask);
9849 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9852 /// \brief Either split a vector in halves or decompose the shuffles and the
9855 /// This is provided as a good fallback for many lowerings of non-single-input
9856 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9857 /// between splitting the shuffle into 128-bit components and stitching those
9858 /// back together vs. extracting the single-input shuffles and blending those
9860 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9861 SDValue V2, ArrayRef<int> Mask,
9862 SelectionDAG &DAG) {
9863 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9864 "lower single-input shuffles as it "
9865 "could then recurse on itself.");
9866 int Size = Mask.size();
9868 // If this can be modeled as a broadcast of two elements followed by a blend,
9869 // prefer that lowering. This is especially important because broadcasts can
9870 // often fold with memory operands.
9871 auto DoBothBroadcast = [&] {
9872 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9875 if (V2BroadcastIdx == -1)
9876 V2BroadcastIdx = M - Size;
9877 else if (M - Size != V2BroadcastIdx)
9879 } else if (M >= 0) {
9880 if (V1BroadcastIdx == -1)
9882 else if (M != V1BroadcastIdx)
9887 if (DoBothBroadcast())
9888 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9891 // If the inputs all stem from a single 128-bit lane of each input, then we
9892 // split them rather than blending because the split will decompose to
9893 // unusually few instructions.
9894 int LaneCount = VT.getSizeInBits() / 128;
9895 int LaneSize = Size / LaneCount;
9896 SmallBitVector LaneInputs[2];
9897 LaneInputs[0].resize(LaneCount, false);
9898 LaneInputs[1].resize(LaneCount, false);
9899 for (int i = 0; i < Size; ++i)
9901 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9902 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9903 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9905 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9906 // that the decomposed single-input shuffles don't end up here.
9907 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9910 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9911 /// a permutation and blend of those lanes.
9913 /// This essentially blends the out-of-lane inputs to each lane into the lane
9914 /// from a permuted copy of the vector. This lowering strategy results in four
9915 /// instructions in the worst case for a single-input cross lane shuffle which
9916 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9917 /// of. Special cases for each particular shuffle pattern should be handled
9918 /// prior to trying this lowering.
9919 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9920 SDValue V1, SDValue V2,
9922 SelectionDAG &DAG) {
9923 // FIXME: This should probably be generalized for 512-bit vectors as well.
9924 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9925 int LaneSize = Mask.size() / 2;
9927 // If there are only inputs from one 128-bit lane, splitting will in fact be
9928 // less expensive. The flags track wether the given lane contains an element
9929 // that crosses to another lane.
9930 bool LaneCrossing[2] = {false, false};
9931 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9932 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9933 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9934 if (!LaneCrossing[0] || !LaneCrossing[1])
9935 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9937 if (isSingleInputShuffleMask(Mask)) {
9938 SmallVector<int, 32> FlippedBlendMask;
9939 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9940 FlippedBlendMask.push_back(
9941 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9943 : Mask[i] % LaneSize +
9944 (i / LaneSize) * LaneSize + Size));
9946 // Flip the vector, and blend the results which should now be in-lane. The
9947 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9948 // 5 for the high source. The value 3 selects the high half of source 2 and
9949 // the value 2 selects the low half of source 2. We only use source 2 to
9950 // allow folding it into a memory operand.
9951 unsigned PERMMask = 3 | 2 << 4;
9952 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9953 V1, DAG.getConstant(PERMMask, MVT::i8));
9954 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9957 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9958 // will be handled by the above logic and a blend of the results, much like
9959 // other patterns in AVX.
9960 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9963 /// \brief Handle lowering 2-lane 128-bit shuffles.
9964 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9965 SDValue V2, ArrayRef<int> Mask,
9966 const X86Subtarget *Subtarget,
9967 SelectionDAG &DAG) {
9968 // Blends are faster and handle all the non-lane-crossing cases.
9969 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9973 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9974 VT.getVectorNumElements() / 2);
9975 // Check for patterns which can be matched with a single insert of a 128-bit
9977 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9978 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9979 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9980 DAG.getIntPtrConstant(0));
9981 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9982 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9983 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9985 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9986 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9987 DAG.getIntPtrConstant(0));
9988 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9989 DAG.getIntPtrConstant(2));
9990 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9993 // Otherwise form a 128-bit permutation.
9994 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9995 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9996 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9997 DAG.getConstant(PermMask, MVT::i8));
10000 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10001 /// shuffling each lane.
10003 /// This will only succeed when the result of fixing the 128-bit lanes results
10004 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10005 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10006 /// the lane crosses early and then use simpler shuffles within each lane.
10008 /// FIXME: It might be worthwhile at some point to support this without
10009 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10010 /// in x86 only floating point has interesting non-repeating shuffles, and even
10011 /// those are still *marginally* more expensive.
10012 static SDValue lowerVectorShuffleByMerging128BitLanes(
10013 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10014 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10015 assert(!isSingleInputShuffleMask(Mask) &&
10016 "This is only useful with multiple inputs.");
10018 int Size = Mask.size();
10019 int LaneSize = 128 / VT.getScalarSizeInBits();
10020 int NumLanes = Size / LaneSize;
10021 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10023 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10024 // check whether the in-128-bit lane shuffles share a repeating pattern.
10025 SmallVector<int, 4> Lanes;
10026 Lanes.resize(NumLanes, -1);
10027 SmallVector<int, 4> InLaneMask;
10028 InLaneMask.resize(LaneSize, -1);
10029 for (int i = 0; i < Size; ++i) {
10033 int j = i / LaneSize;
10035 if (Lanes[j] < 0) {
10036 // First entry we've seen for this lane.
10037 Lanes[j] = Mask[i] / LaneSize;
10038 } else if (Lanes[j] != Mask[i] / LaneSize) {
10039 // This doesn't match the lane selected previously!
10043 // Check that within each lane we have a consistent shuffle mask.
10044 int k = i % LaneSize;
10045 if (InLaneMask[k] < 0) {
10046 InLaneMask[k] = Mask[i] % LaneSize;
10047 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10048 // This doesn't fit a repeating in-lane mask.
10053 // First shuffle the lanes into place.
10054 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10055 VT.getSizeInBits() / 64);
10056 SmallVector<int, 8> LaneMask;
10057 LaneMask.resize(NumLanes * 2, -1);
10058 for (int i = 0; i < NumLanes; ++i)
10059 if (Lanes[i] >= 0) {
10060 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10061 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10064 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10065 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10066 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10068 // Cast it back to the type we actually want.
10069 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10071 // Now do a simple shuffle that isn't lane crossing.
10072 SmallVector<int, 8> NewMask;
10073 NewMask.resize(Size, -1);
10074 for (int i = 0; i < Size; ++i)
10076 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10077 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10078 "Must not introduce lane crosses at this point!");
10080 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10083 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10086 /// This returns true if the elements from a particular input are already in the
10087 /// slot required by the given mask and require no permutation.
10088 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10089 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10090 int Size = Mask.size();
10091 for (int i = 0; i < Size; ++i)
10092 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10098 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10100 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10101 /// isn't available.
10102 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10103 const X86Subtarget *Subtarget,
10104 SelectionDAG &DAG) {
10106 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10107 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10109 ArrayRef<int> Mask = SVOp->getMask();
10110 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10112 SmallVector<int, 4> WidenedMask;
10113 if (canWidenShuffleElements(Mask, WidenedMask))
10114 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10117 if (isSingleInputShuffleMask(Mask)) {
10118 // Check for being able to broadcast a single element.
10119 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10120 Mask, Subtarget, DAG))
10123 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10124 // Non-half-crossing single input shuffles can be lowerid with an
10125 // interleaved permutation.
10126 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10127 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10128 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10129 DAG.getConstant(VPERMILPMask, MVT::i8));
10132 // With AVX2 we have direct support for this permutation.
10133 if (Subtarget->hasAVX2())
10134 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10135 getV4X86ShuffleImm8ForMask(Mask, DAG));
10137 // Otherwise, fall back.
10138 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10142 // X86 has dedicated unpack instructions that can handle specific blend
10143 // operations: UNPCKH and UNPCKL.
10144 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10145 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10146 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10147 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10149 // If we have a single input to the zero element, insert that into V1 if we
10150 // can do so cheaply.
10151 int NumV2Elements =
10152 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10153 if (NumV2Elements == 1 && Mask[0] >= 4)
10154 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10155 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10162 // Check if the blend happens to exactly fit that of SHUFPD.
10163 if ((Mask[0] == -1 || Mask[0] < 2) &&
10164 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10165 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10166 (Mask[3] == -1 || Mask[3] >= 6)) {
10167 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10168 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10169 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10170 DAG.getConstant(SHUFPDMask, MVT::i8));
10172 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10173 (Mask[1] == -1 || Mask[1] < 2) &&
10174 (Mask[2] == -1 || Mask[2] >= 6) &&
10175 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10176 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10177 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10178 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10179 DAG.getConstant(SHUFPDMask, MVT::i8));
10182 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10183 // shuffle. However, if we have AVX2 and either inputs are already in place,
10184 // we will be able to shuffle even across lanes the other input in a single
10185 // instruction so skip this pattern.
10186 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10187 isShuffleMaskInputInPlace(1, Mask))))
10188 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10189 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10192 // If we have AVX2 then we always want to lower with a blend because an v4 we
10193 // can fully permute the elements.
10194 if (Subtarget->hasAVX2())
10195 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10198 // Otherwise fall back on generic lowering.
10199 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10202 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10204 /// This routine is only called when we have AVX2 and thus a reasonable
10205 /// instruction set for v4i64 shuffling..
10206 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10207 const X86Subtarget *Subtarget,
10208 SelectionDAG &DAG) {
10210 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10211 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10212 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10213 ArrayRef<int> Mask = SVOp->getMask();
10214 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10215 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10217 SmallVector<int, 4> WidenedMask;
10218 if (canWidenShuffleElements(Mask, WidenedMask))
10219 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10222 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10226 // Check for being able to broadcast a single element.
10227 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10228 Mask, Subtarget, DAG))
10231 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10232 // use lower latency instructions that will operate on both 128-bit lanes.
10233 SmallVector<int, 2> RepeatedMask;
10234 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10235 if (isSingleInputShuffleMask(Mask)) {
10236 int PSHUFDMask[] = {-1, -1, -1, -1};
10237 for (int i = 0; i < 2; ++i)
10238 if (RepeatedMask[i] >= 0) {
10239 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10240 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10242 return DAG.getNode(
10243 ISD::BITCAST, DL, MVT::v4i64,
10244 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10245 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10246 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10249 // Use dedicated unpack instructions for masks that match their pattern.
10250 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10251 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10252 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10253 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10256 // AVX2 provides a direct instruction for permuting a single input across
10258 if (isSingleInputShuffleMask(Mask))
10259 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10260 getV4X86ShuffleImm8ForMask(Mask, DAG));
10262 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10263 // shuffle. However, if we have AVX2 and either inputs are already in place,
10264 // we will be able to shuffle even across lanes the other input in a single
10265 // instruction so skip this pattern.
10266 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10267 isShuffleMaskInputInPlace(1, Mask))))
10268 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10269 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10272 // Otherwise fall back on generic blend lowering.
10273 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10277 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10279 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10280 /// isn't available.
10281 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10282 const X86Subtarget *Subtarget,
10283 SelectionDAG &DAG) {
10285 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10286 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10288 ArrayRef<int> Mask = SVOp->getMask();
10289 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10291 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10295 // Check for being able to broadcast a single element.
10296 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10297 Mask, Subtarget, DAG))
10300 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10301 // options to efficiently lower the shuffle.
10302 SmallVector<int, 4> RepeatedMask;
10303 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10304 assert(RepeatedMask.size() == 4 &&
10305 "Repeated masks must be half the mask width!");
10306 if (isSingleInputShuffleMask(Mask))
10307 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10308 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10310 // Use dedicated unpack instructions for masks that match their pattern.
10311 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10312 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10313 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10314 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10316 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10317 // have already handled any direct blends. We also need to squash the
10318 // repeated mask into a simulated v4f32 mask.
10319 for (int i = 0; i < 4; ++i)
10320 if (RepeatedMask[i] >= 8)
10321 RepeatedMask[i] -= 4;
10322 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10325 // If we have a single input shuffle with different shuffle patterns in the
10326 // two 128-bit lanes use the variable mask to VPERMILPS.
10327 if (isSingleInputShuffleMask(Mask)) {
10328 SDValue VPermMask[8];
10329 for (int i = 0; i < 8; ++i)
10330 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10331 : DAG.getConstant(Mask[i], MVT::i32);
10332 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10333 return DAG.getNode(
10334 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10335 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10337 if (Subtarget->hasAVX2())
10338 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10339 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10340 DAG.getNode(ISD::BUILD_VECTOR, DL,
10341 MVT::v8i32, VPermMask)),
10344 // Otherwise, fall back.
10345 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10349 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10351 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10352 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10355 // If we have AVX2 then we always want to lower with a blend because at v8 we
10356 // can fully permute the elements.
10357 if (Subtarget->hasAVX2())
10358 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10361 // Otherwise fall back on generic lowering.
10362 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10365 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10367 /// This routine is only called when we have AVX2 and thus a reasonable
10368 /// instruction set for v8i32 shuffling..
10369 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10370 const X86Subtarget *Subtarget,
10371 SelectionDAG &DAG) {
10373 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10374 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10375 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10376 ArrayRef<int> Mask = SVOp->getMask();
10377 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10378 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10380 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10384 // Check for being able to broadcast a single element.
10385 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10386 Mask, Subtarget, DAG))
10389 // If the shuffle mask is repeated in each 128-bit lane we can use more
10390 // efficient instructions that mirror the shuffles across the two 128-bit
10392 SmallVector<int, 4> RepeatedMask;
10393 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10394 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10395 if (isSingleInputShuffleMask(Mask))
10396 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10397 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10399 // Use dedicated unpack instructions for masks that match their pattern.
10400 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10401 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10402 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10403 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10406 // If the shuffle patterns aren't repeated but it is a single input, directly
10407 // generate a cross-lane VPERMD instruction.
10408 if (isSingleInputShuffleMask(Mask)) {
10409 SDValue VPermMask[8];
10410 for (int i = 0; i < 8; ++i)
10411 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10412 : DAG.getConstant(Mask[i], MVT::i32);
10413 return DAG.getNode(
10414 X86ISD::VPERMV, DL, MVT::v8i32,
10415 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10418 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10420 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10421 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10424 // Otherwise fall back on generic blend lowering.
10425 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10429 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10431 /// This routine is only called when we have AVX2 and thus a reasonable
10432 /// instruction set for v16i16 shuffling..
10433 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10434 const X86Subtarget *Subtarget,
10435 SelectionDAG &DAG) {
10437 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10438 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10439 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10440 ArrayRef<int> Mask = SVOp->getMask();
10441 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10442 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10444 // Check for being able to broadcast a single element.
10445 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10446 Mask, Subtarget, DAG))
10449 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10453 // Use dedicated unpack instructions for masks that match their pattern.
10454 if (isShuffleEquivalent(Mask,
10455 // First 128-bit lane:
10456 0, 16, 1, 17, 2, 18, 3, 19,
10457 // Second 128-bit lane:
10458 8, 24, 9, 25, 10, 26, 11, 27))
10459 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10460 if (isShuffleEquivalent(Mask,
10461 // First 128-bit lane:
10462 4, 20, 5, 21, 6, 22, 7, 23,
10463 // Second 128-bit lane:
10464 12, 28, 13, 29, 14, 30, 15, 31))
10465 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10467 if (isSingleInputShuffleMask(Mask)) {
10468 // There are no generalized cross-lane shuffle operations available on i16
10470 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10471 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10474 SDValue PSHUFBMask[32];
10475 for (int i = 0; i < 16; ++i) {
10476 if (Mask[i] == -1) {
10477 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10481 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10482 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10483 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10484 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10486 return DAG.getNode(
10487 ISD::BITCAST, DL, MVT::v16i16,
10489 X86ISD::PSHUFB, DL, MVT::v32i8,
10490 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10491 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10494 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10496 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10497 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10500 // Otherwise fall back on generic lowering.
10501 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10504 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10506 /// This routine is only called when we have AVX2 and thus a reasonable
10507 /// instruction set for v32i8 shuffling..
10508 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10509 const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10512 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10513 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10515 ArrayRef<int> Mask = SVOp->getMask();
10516 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10517 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10519 // Check for being able to broadcast a single element.
10520 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10521 Mask, Subtarget, DAG))
10524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10528 // Use dedicated unpack instructions for masks that match their pattern.
10529 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10531 if (isShuffleEquivalent(
10533 // First 128-bit lane:
10534 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10535 // Second 128-bit lane:
10536 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10537 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10538 if (isShuffleEquivalent(
10540 // First 128-bit lane:
10541 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10542 // Second 128-bit lane:
10543 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10544 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10546 if (isSingleInputShuffleMask(Mask)) {
10547 // There are no generalized cross-lane shuffle operations available on i8
10549 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10550 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10553 SDValue PSHUFBMask[32];
10554 for (int i = 0; i < 32; ++i)
10557 ? DAG.getUNDEF(MVT::i8)
10558 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10560 return DAG.getNode(
10561 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10562 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10565 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10567 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10568 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10571 // Otherwise fall back on generic lowering.
10572 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10575 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10577 /// This routine either breaks down the specific type of a 256-bit x86 vector
10578 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10579 /// together based on the available instructions.
10580 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10581 MVT VT, const X86Subtarget *Subtarget,
10582 SelectionDAG &DAG) {
10584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10585 ArrayRef<int> Mask = SVOp->getMask();
10587 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10588 // check for those subtargets here and avoid much of the subtarget querying in
10589 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10590 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10591 // floating point types there eventually, just immediately cast everything to
10592 // a float and operate entirely in that domain.
10593 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10594 int ElementBits = VT.getScalarSizeInBits();
10595 if (ElementBits < 32)
10596 // No floating point type available, decompose into 128-bit vectors.
10597 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10599 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10600 VT.getVectorNumElements());
10601 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10602 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10603 return DAG.getNode(ISD::BITCAST, DL, VT,
10604 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10607 switch (VT.SimpleTy) {
10609 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10611 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10613 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10615 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10619 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10622 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10626 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10627 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10628 const X86Subtarget *Subtarget,
10629 SelectionDAG &DAG) {
10631 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10632 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10634 ArrayRef<int> Mask = SVOp->getMask();
10635 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10637 // FIXME: Implement direct support for this type!
10638 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10641 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10642 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10643 const X86Subtarget *Subtarget,
10644 SelectionDAG &DAG) {
10646 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10647 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10649 ArrayRef<int> Mask = SVOp->getMask();
10650 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10652 // FIXME: Implement direct support for this type!
10653 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10656 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10657 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10658 const X86Subtarget *Subtarget,
10659 SelectionDAG &DAG) {
10661 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10662 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10664 ArrayRef<int> Mask = SVOp->getMask();
10665 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10667 // FIXME: Implement direct support for this type!
10668 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10671 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10672 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10673 const X86Subtarget *Subtarget,
10674 SelectionDAG &DAG) {
10676 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10677 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10679 ArrayRef<int> Mask = SVOp->getMask();
10680 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10682 // FIXME: Implement direct support for this type!
10683 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10686 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10687 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10688 const X86Subtarget *Subtarget,
10689 SelectionDAG &DAG) {
10691 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10692 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10693 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10694 ArrayRef<int> Mask = SVOp->getMask();
10695 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10696 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10698 // FIXME: Implement direct support for this type!
10699 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10702 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10703 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10704 const X86Subtarget *Subtarget,
10705 SelectionDAG &DAG) {
10707 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10708 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10710 ArrayRef<int> Mask = SVOp->getMask();
10711 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10712 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10714 // FIXME: Implement direct support for this type!
10715 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10718 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10720 /// This routine either breaks down the specific type of a 512-bit x86 vector
10721 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10722 /// together based on the available instructions.
10723 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10724 MVT VT, const X86Subtarget *Subtarget,
10725 SelectionDAG &DAG) {
10727 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10728 ArrayRef<int> Mask = SVOp->getMask();
10729 assert(Subtarget->hasAVX512() &&
10730 "Cannot lower 512-bit vectors w/ basic ISA!");
10732 // Check for being able to broadcast a single element.
10733 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10734 Mask, Subtarget, DAG))
10737 // Dispatch to each element type for lowering. If we don't have supprot for
10738 // specific element type shuffles at 512 bits, immediately split them and
10739 // lower them. Each lowering routine of a given type is allowed to assume that
10740 // the requisite ISA extensions for that element type are available.
10741 switch (VT.SimpleTy) {
10743 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10745 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10747 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10749 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 if (Subtarget->hasBWI())
10752 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 if (Subtarget->hasBWI())
10756 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10760 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10763 // Otherwise fall back on splitting.
10764 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10767 /// \brief Top-level lowering for x86 vector shuffles.
10769 /// This handles decomposition, canonicalization, and lowering of all x86
10770 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10771 /// above in helper routines. The canonicalization attempts to widen shuffles
10772 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10773 /// s.t. only one of the two inputs needs to be tested, etc.
10774 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10775 SelectionDAG &DAG) {
10776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10777 ArrayRef<int> Mask = SVOp->getMask();
10778 SDValue V1 = Op.getOperand(0);
10779 SDValue V2 = Op.getOperand(1);
10780 MVT VT = Op.getSimpleValueType();
10781 int NumElements = VT.getVectorNumElements();
10784 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10786 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10787 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10788 if (V1IsUndef && V2IsUndef)
10789 return DAG.getUNDEF(VT);
10791 // When we create a shuffle node we put the UNDEF node to second operand,
10792 // but in some cases the first operand may be transformed to UNDEF.
10793 // In this case we should just commute the node.
10795 return DAG.getCommutedVectorShuffle(*SVOp);
10797 // Check for non-undef masks pointing at an undef vector and make the masks
10798 // undef as well. This makes it easier to match the shuffle based solely on
10802 if (M >= NumElements) {
10803 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10804 for (int &M : NewMask)
10805 if (M >= NumElements)
10807 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10810 // Try to collapse shuffles into using a vector type with fewer elements but
10811 // wider element types. We cap this to not form integers or floating point
10812 // elements wider than 64 bits, but it might be interesting to form i128
10813 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10814 SmallVector<int, 16> WidenedMask;
10815 if (VT.getScalarSizeInBits() < 64 &&
10816 canWidenShuffleElements(Mask, WidenedMask)) {
10817 MVT NewEltVT = VT.isFloatingPoint()
10818 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10819 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10820 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10821 // Make sure that the new vector type is legal. For example, v2f64 isn't
10823 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10824 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10825 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10826 return DAG.getNode(ISD::BITCAST, dl, VT,
10827 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10831 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10832 for (int M : SVOp->getMask())
10834 ++NumUndefElements;
10835 else if (M < NumElements)
10840 // Commute the shuffle as needed such that more elements come from V1 than
10841 // V2. This allows us to match the shuffle pattern strictly on how many
10842 // elements come from V1 without handling the symmetric cases.
10843 if (NumV2Elements > NumV1Elements)
10844 return DAG.getCommutedVectorShuffle(*SVOp);
10846 // When the number of V1 and V2 elements are the same, try to minimize the
10847 // number of uses of V2 in the low half of the vector. When that is tied,
10848 // ensure that the sum of indices for V1 is equal to or lower than the sum
10849 // indices for V2. When those are equal, try to ensure that the number of odd
10850 // indices for V1 is lower than the number of odd indices for V2.
10851 if (NumV1Elements == NumV2Elements) {
10852 int LowV1Elements = 0, LowV2Elements = 0;
10853 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10854 if (M >= NumElements)
10858 if (LowV2Elements > LowV1Elements) {
10859 return DAG.getCommutedVectorShuffle(*SVOp);
10860 } else if (LowV2Elements == LowV1Elements) {
10861 int SumV1Indices = 0, SumV2Indices = 0;
10862 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10863 if (SVOp->getMask()[i] >= NumElements)
10865 else if (SVOp->getMask()[i] >= 0)
10867 if (SumV2Indices < SumV1Indices) {
10868 return DAG.getCommutedVectorShuffle(*SVOp);
10869 } else if (SumV2Indices == SumV1Indices) {
10870 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10871 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10872 if (SVOp->getMask()[i] >= NumElements)
10873 NumV2OddIndices += i % 2;
10874 else if (SVOp->getMask()[i] >= 0)
10875 NumV1OddIndices += i % 2;
10876 if (NumV2OddIndices < NumV1OddIndices)
10877 return DAG.getCommutedVectorShuffle(*SVOp);
10882 // For each vector width, delegate to a specialized lowering routine.
10883 if (VT.getSizeInBits() == 128)
10884 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10886 if (VT.getSizeInBits() == 256)
10887 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10889 // Force AVX-512 vectors to be scalarized for now.
10890 // FIXME: Implement AVX-512 support!
10891 if (VT.getSizeInBits() == 512)
10892 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10894 llvm_unreachable("Unimplemented!");
10898 //===----------------------------------------------------------------------===//
10899 // Legacy vector shuffle lowering
10901 // This code is the legacy code handling vector shuffles until the above
10902 // replaces its functionality and performance.
10903 //===----------------------------------------------------------------------===//
10905 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10906 bool hasInt256, unsigned *MaskOut = nullptr) {
10907 MVT EltVT = VT.getVectorElementType();
10909 // There is no blend with immediate in AVX-512.
10910 if (VT.is512BitVector())
10913 if (!hasSSE41 || EltVT == MVT::i8)
10915 if (!hasInt256 && VT == MVT::v16i16)
10918 unsigned MaskValue = 0;
10919 unsigned NumElems = VT.getVectorNumElements();
10920 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10921 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10922 unsigned NumElemsInLane = NumElems / NumLanes;
10924 // Blend for v16i16 should be symetric for the both lanes.
10925 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10927 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10928 int EltIdx = MaskVals[i];
10930 if ((EltIdx < 0 || EltIdx == (int)i) &&
10931 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10934 if (((unsigned)EltIdx == (i + NumElems)) &&
10935 (SndLaneEltIdx < 0 ||
10936 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10937 MaskValue |= (1 << i);
10943 *MaskOut = MaskValue;
10947 // Try to lower a shuffle node into a simple blend instruction.
10948 // This function assumes isBlendMask returns true for this
10949 // SuffleVectorSDNode
10950 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10951 unsigned MaskValue,
10952 const X86Subtarget *Subtarget,
10953 SelectionDAG &DAG) {
10954 MVT VT = SVOp->getSimpleValueType(0);
10955 MVT EltVT = VT.getVectorElementType();
10956 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10957 Subtarget->hasInt256() && "Trying to lower a "
10958 "VECTOR_SHUFFLE to a Blend but "
10959 "with the wrong mask"));
10960 SDValue V1 = SVOp->getOperand(0);
10961 SDValue V2 = SVOp->getOperand(1);
10963 unsigned NumElems = VT.getVectorNumElements();
10965 // Convert i32 vectors to floating point if it is not AVX2.
10966 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10968 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10969 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10971 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10972 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10975 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10976 DAG.getConstant(MaskValue, MVT::i32));
10977 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10980 /// In vector type \p VT, return true if the element at index \p InputIdx
10981 /// falls on a different 128-bit lane than \p OutputIdx.
10982 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10983 unsigned OutputIdx) {
10984 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10985 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10988 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10989 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10990 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10991 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10993 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10994 SelectionDAG &DAG) {
10995 MVT VT = V1.getSimpleValueType();
10996 assert(VT.is128BitVector() || VT.is256BitVector());
10998 MVT EltVT = VT.getVectorElementType();
10999 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11000 unsigned NumElts = VT.getVectorNumElements();
11002 SmallVector<SDValue, 32> PshufbMask;
11003 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11004 int InputIdx = MaskVals[OutputIdx];
11005 unsigned InputByteIdx;
11007 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11008 InputByteIdx = 0x80;
11010 // Cross lane is not allowed.
11011 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11013 InputByteIdx = InputIdx * EltSizeInBytes;
11014 // Index is an byte offset within the 128-bit lane.
11015 InputByteIdx &= 0xf;
11018 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11019 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11020 if (InputByteIdx != 0x80)
11025 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11027 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11028 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11029 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11032 // v8i16 shuffles - Prefer shuffles in the following order:
11033 // 1. [all] pshuflw, pshufhw, optional move
11034 // 2. [ssse3] 1 x pshufb
11035 // 3. [ssse3] 2 x pshufb + 1 x por
11036 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11038 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11039 SelectionDAG &DAG) {
11040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11041 SDValue V1 = SVOp->getOperand(0);
11042 SDValue V2 = SVOp->getOperand(1);
11044 SmallVector<int, 8> MaskVals;
11046 // Determine if more than 1 of the words in each of the low and high quadwords
11047 // of the result come from the same quadword of one of the two inputs. Undef
11048 // mask values count as coming from any quadword, for better codegen.
11050 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11051 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11052 unsigned LoQuad[] = { 0, 0, 0, 0 };
11053 unsigned HiQuad[] = { 0, 0, 0, 0 };
11054 // Indices of quads used.
11055 std::bitset<4> InputQuads;
11056 for (unsigned i = 0; i < 8; ++i) {
11057 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11058 int EltIdx = SVOp->getMaskElt(i);
11059 MaskVals.push_back(EltIdx);
11067 ++Quad[EltIdx / 4];
11068 InputQuads.set(EltIdx / 4);
11071 int BestLoQuad = -1;
11072 unsigned MaxQuad = 1;
11073 for (unsigned i = 0; i < 4; ++i) {
11074 if (LoQuad[i] > MaxQuad) {
11076 MaxQuad = LoQuad[i];
11080 int BestHiQuad = -1;
11082 for (unsigned i = 0; i < 4; ++i) {
11083 if (HiQuad[i] > MaxQuad) {
11085 MaxQuad = HiQuad[i];
11089 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11090 // of the two input vectors, shuffle them into one input vector so only a
11091 // single pshufb instruction is necessary. If there are more than 2 input
11092 // quads, disable the next transformation since it does not help SSSE3.
11093 bool V1Used = InputQuads[0] || InputQuads[1];
11094 bool V2Used = InputQuads[2] || InputQuads[3];
11095 if (Subtarget->hasSSSE3()) {
11096 if (InputQuads.count() == 2 && V1Used && V2Used) {
11097 BestLoQuad = InputQuads[0] ? 0 : 1;
11098 BestHiQuad = InputQuads[2] ? 2 : 3;
11100 if (InputQuads.count() > 2) {
11106 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11107 // the shuffle mask. If a quad is scored as -1, that means that it contains
11108 // words from all 4 input quadwords.
11110 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11112 BestLoQuad < 0 ? 0 : BestLoQuad,
11113 BestHiQuad < 0 ? 1 : BestHiQuad
11115 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11116 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11117 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11118 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11120 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11121 // source words for the shuffle, to aid later transformations.
11122 bool AllWordsInNewV = true;
11123 bool InOrder[2] = { true, true };
11124 for (unsigned i = 0; i != 8; ++i) {
11125 int idx = MaskVals[i];
11127 InOrder[i/4] = false;
11128 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11130 AllWordsInNewV = false;
11134 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11135 if (AllWordsInNewV) {
11136 for (int i = 0; i != 8; ++i) {
11137 int idx = MaskVals[i];
11140 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11141 if ((idx != i) && idx < 4)
11143 if ((idx != i) && idx > 3)
11152 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11153 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11154 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11155 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11156 unsigned TargetMask = 0;
11157 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11158 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11159 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11160 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11161 getShufflePSHUFLWImmediate(SVOp);
11162 V1 = NewV.getOperand(0);
11163 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11167 // Promote splats to a larger type which usually leads to more efficient code.
11168 // FIXME: Is this true if pshufb is available?
11169 if (SVOp->isSplat())
11170 return PromoteSplat(SVOp, DAG);
11172 // If we have SSSE3, and all words of the result are from 1 input vector,
11173 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11174 // is present, fall back to case 4.
11175 if (Subtarget->hasSSSE3()) {
11176 SmallVector<SDValue,16> pshufbMask;
11178 // If we have elements from both input vectors, set the high bit of the
11179 // shuffle mask element to zero out elements that come from V2 in the V1
11180 // mask, and elements that come from V1 in the V2 mask, so that the two
11181 // results can be OR'd together.
11182 bool TwoInputs = V1Used && V2Used;
11183 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11185 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11187 // Calculate the shuffle mask for the second input, shuffle it, and
11188 // OR it with the first shuffled input.
11189 CommuteVectorShuffleMask(MaskVals, 8);
11190 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11191 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11192 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11195 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11196 // and update MaskVals with new element order.
11197 std::bitset<8> InOrder;
11198 if (BestLoQuad >= 0) {
11199 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11200 for (int i = 0; i != 4; ++i) {
11201 int idx = MaskVals[i];
11204 } else if ((idx / 4) == BestLoQuad) {
11205 MaskV[i] = idx & 3;
11209 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11212 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11214 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11215 NewV.getOperand(0),
11216 getShufflePSHUFLWImmediate(SVOp), DAG);
11220 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11221 // and update MaskVals with the new element order.
11222 if (BestHiQuad >= 0) {
11223 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11224 for (unsigned i = 4; i != 8; ++i) {
11225 int idx = MaskVals[i];
11228 } else if ((idx / 4) == BestHiQuad) {
11229 MaskV[i] = (idx & 3) + 4;
11233 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11236 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11238 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11239 NewV.getOperand(0),
11240 getShufflePSHUFHWImmediate(SVOp), DAG);
11244 // In case BestHi & BestLo were both -1, which means each quadword has a word
11245 // from each of the four input quadwords, calculate the InOrder bitvector now
11246 // before falling through to the insert/extract cleanup.
11247 if (BestLoQuad == -1 && BestHiQuad == -1) {
11249 for (int i = 0; i != 8; ++i)
11250 if (MaskVals[i] < 0 || MaskVals[i] == i)
11254 // The other elements are put in the right place using pextrw and pinsrw.
11255 for (unsigned i = 0; i != 8; ++i) {
11258 int EltIdx = MaskVals[i];
11261 SDValue ExtOp = (EltIdx < 8) ?
11262 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11263 DAG.getIntPtrConstant(EltIdx)) :
11264 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11265 DAG.getIntPtrConstant(EltIdx - 8));
11266 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11267 DAG.getIntPtrConstant(i));
11272 /// \brief v16i16 shuffles
11274 /// FIXME: We only support generation of a single pshufb currently. We can
11275 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11276 /// well (e.g 2 x pshufb + 1 x por).
11278 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11280 SDValue V1 = SVOp->getOperand(0);
11281 SDValue V2 = SVOp->getOperand(1);
11284 if (V2.getOpcode() != ISD::UNDEF)
11287 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11288 return getPSHUFB(MaskVals, V1, dl, DAG);
11291 // v16i8 shuffles - Prefer shuffles in the following order:
11292 // 1. [ssse3] 1 x pshufb
11293 // 2. [ssse3] 2 x pshufb + 1 x por
11294 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11295 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11296 const X86Subtarget* Subtarget,
11297 SelectionDAG &DAG) {
11298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11299 SDValue V1 = SVOp->getOperand(0);
11300 SDValue V2 = SVOp->getOperand(1);
11302 ArrayRef<int> MaskVals = SVOp->getMask();
11304 // Promote splats to a larger type which usually leads to more efficient code.
11305 // FIXME: Is this true if pshufb is available?
11306 if (SVOp->isSplat())
11307 return PromoteSplat(SVOp, DAG);
11309 // If we have SSSE3, case 1 is generated when all result bytes come from
11310 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11311 // present, fall back to case 3.
11313 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11314 if (Subtarget->hasSSSE3()) {
11315 SmallVector<SDValue,16> pshufbMask;
11317 // If all result elements are from one input vector, then only translate
11318 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11320 // Otherwise, we have elements from both input vectors, and must zero out
11321 // elements that come from V2 in the first mask, and V1 in the second mask
11322 // so that we can OR them together.
11323 for (unsigned i = 0; i != 16; ++i) {
11324 int EltIdx = MaskVals[i];
11325 if (EltIdx < 0 || EltIdx >= 16)
11327 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11329 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11330 DAG.getNode(ISD::BUILD_VECTOR, dl,
11331 MVT::v16i8, pshufbMask));
11333 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11334 // the 2nd operand if it's undefined or zero.
11335 if (V2.getOpcode() == ISD::UNDEF ||
11336 ISD::isBuildVectorAllZeros(V2.getNode()))
11339 // Calculate the shuffle mask for the second input, shuffle it, and
11340 // OR it with the first shuffled input.
11341 pshufbMask.clear();
11342 for (unsigned i = 0; i != 16; ++i) {
11343 int EltIdx = MaskVals[i];
11344 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11345 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11347 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11348 DAG.getNode(ISD::BUILD_VECTOR, dl,
11349 MVT::v16i8, pshufbMask));
11350 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11353 // No SSSE3 - Calculate in place words and then fix all out of place words
11354 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11355 // the 16 different words that comprise the two doublequadword input vectors.
11356 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11357 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11359 for (int i = 0; i != 8; ++i) {
11360 int Elt0 = MaskVals[i*2];
11361 int Elt1 = MaskVals[i*2+1];
11363 // This word of the result is all undef, skip it.
11364 if (Elt0 < 0 && Elt1 < 0)
11367 // This word of the result is already in the correct place, skip it.
11368 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11371 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11372 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11375 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11376 // using a single extract together, load it and store it.
11377 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11378 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11379 DAG.getIntPtrConstant(Elt1 / 2));
11380 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11381 DAG.getIntPtrConstant(i));
11385 // If Elt1 is defined, extract it from the appropriate source. If the
11386 // source byte is not also odd, shift the extracted word left 8 bits
11387 // otherwise clear the bottom 8 bits if we need to do an or.
11389 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11390 DAG.getIntPtrConstant(Elt1 / 2));
11391 if ((Elt1 & 1) == 0)
11392 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11394 TLI.getShiftAmountTy(InsElt.getValueType())));
11395 else if (Elt0 >= 0)
11396 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11397 DAG.getConstant(0xFF00, MVT::i16));
11399 // If Elt0 is defined, extract it from the appropriate source. If the
11400 // source byte is not also even, shift the extracted word right 8 bits. If
11401 // Elt1 was also defined, OR the extracted values together before
11402 // inserting them in the result.
11404 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11405 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11406 if ((Elt0 & 1) != 0)
11407 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11409 TLI.getShiftAmountTy(InsElt0.getValueType())));
11410 else if (Elt1 >= 0)
11411 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11412 DAG.getConstant(0x00FF, MVT::i16));
11413 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11416 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11417 DAG.getIntPtrConstant(i));
11419 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11422 // v32i8 shuffles - Translate to VPSHUFB if possible.
11424 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11425 const X86Subtarget *Subtarget,
11426 SelectionDAG &DAG) {
11427 MVT VT = SVOp->getSimpleValueType(0);
11428 SDValue V1 = SVOp->getOperand(0);
11429 SDValue V2 = SVOp->getOperand(1);
11431 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11433 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11434 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11435 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11437 // VPSHUFB may be generated if
11438 // (1) one of input vector is undefined or zeroinitializer.
11439 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11440 // And (2) the mask indexes don't cross the 128-bit lane.
11441 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11442 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11445 if (V1IsAllZero && !V2IsAllZero) {
11446 CommuteVectorShuffleMask(MaskVals, 32);
11449 return getPSHUFB(MaskVals, V1, dl, DAG);
11452 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11453 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11454 /// done when every pair / quad of shuffle mask elements point to elements in
11455 /// the right sequence. e.g.
11456 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11458 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11459 SelectionDAG &DAG) {
11460 MVT VT = SVOp->getSimpleValueType(0);
11462 unsigned NumElems = VT.getVectorNumElements();
11465 switch (VT.SimpleTy) {
11466 default: llvm_unreachable("Unexpected!");
11469 return SDValue(SVOp, 0);
11470 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11471 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11472 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11473 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11474 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11475 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11478 SmallVector<int, 8> MaskVec;
11479 for (unsigned i = 0; i != NumElems; i += Scale) {
11481 for (unsigned j = 0; j != Scale; ++j) {
11482 int EltIdx = SVOp->getMaskElt(i+j);
11486 StartIdx = (EltIdx / Scale);
11487 if (EltIdx != (int)(StartIdx*Scale + j))
11490 MaskVec.push_back(StartIdx);
11493 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11494 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11495 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11498 /// getVZextMovL - Return a zero-extending vector move low node.
11500 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11501 SDValue SrcOp, SelectionDAG &DAG,
11502 const X86Subtarget *Subtarget, SDLoc dl) {
11503 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11504 LoadSDNode *LD = nullptr;
11505 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11506 LD = dyn_cast<LoadSDNode>(SrcOp);
11508 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11510 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11511 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11512 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11513 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11514 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11516 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11517 return DAG.getNode(ISD::BITCAST, dl, VT,
11518 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11519 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11521 SrcOp.getOperand(0)
11527 return DAG.getNode(ISD::BITCAST, dl, VT,
11528 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11529 DAG.getNode(ISD::BITCAST, dl,
11533 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11534 /// which could not be matched by any known target speficic shuffle
11536 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11538 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11539 if (NewOp.getNode())
11542 MVT VT = SVOp->getSimpleValueType(0);
11544 unsigned NumElems = VT.getVectorNumElements();
11545 unsigned NumLaneElems = NumElems / 2;
11548 MVT EltVT = VT.getVectorElementType();
11549 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11552 SmallVector<int, 16> Mask;
11553 for (unsigned l = 0; l < 2; ++l) {
11554 // Build a shuffle mask for the output, discovering on the fly which
11555 // input vectors to use as shuffle operands (recorded in InputUsed).
11556 // If building a suitable shuffle vector proves too hard, then bail
11557 // out with UseBuildVector set.
11558 bool UseBuildVector = false;
11559 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11560 unsigned LaneStart = l * NumLaneElems;
11561 for (unsigned i = 0; i != NumLaneElems; ++i) {
11562 // The mask element. This indexes into the input.
11563 int Idx = SVOp->getMaskElt(i+LaneStart);
11565 // the mask element does not index into any input vector.
11566 Mask.push_back(-1);
11570 // The input vector this mask element indexes into.
11571 int Input = Idx / NumLaneElems;
11573 // Turn the index into an offset from the start of the input vector.
11574 Idx -= Input * NumLaneElems;
11576 // Find or create a shuffle vector operand to hold this input.
11578 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11579 if (InputUsed[OpNo] == Input)
11580 // This input vector is already an operand.
11582 if (InputUsed[OpNo] < 0) {
11583 // Create a new operand for this input vector.
11584 InputUsed[OpNo] = Input;
11589 if (OpNo >= array_lengthof(InputUsed)) {
11590 // More than two input vectors used! Give up on trying to create a
11591 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11592 UseBuildVector = true;
11596 // Add the mask index for the new shuffle vector.
11597 Mask.push_back(Idx + OpNo * NumLaneElems);
11600 if (UseBuildVector) {
11601 SmallVector<SDValue, 16> SVOps;
11602 for (unsigned i = 0; i != NumLaneElems; ++i) {
11603 // The mask element. This indexes into the input.
11604 int Idx = SVOp->getMaskElt(i+LaneStart);
11606 SVOps.push_back(DAG.getUNDEF(EltVT));
11610 // The input vector this mask element indexes into.
11611 int Input = Idx / NumElems;
11613 // Turn the index into an offset from the start of the input vector.
11614 Idx -= Input * NumElems;
11616 // Extract the vector element by hand.
11617 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11618 SVOp->getOperand(Input),
11619 DAG.getIntPtrConstant(Idx)));
11622 // Construct the output using a BUILD_VECTOR.
11623 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11624 } else if (InputUsed[0] < 0) {
11625 // No input vectors were used! The result is undefined.
11626 Output[l] = DAG.getUNDEF(NVT);
11628 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11629 (InputUsed[0] % 2) * NumLaneElems,
11631 // If only one input was used, use an undefined vector for the other.
11632 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11633 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11634 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11635 // At least one input vector was used. Create a new shuffle vector.
11636 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11642 // Concatenate the result back
11643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11646 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11647 /// 4 elements, and match them with several different shuffle types.
11649 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11650 SDValue V1 = SVOp->getOperand(0);
11651 SDValue V2 = SVOp->getOperand(1);
11653 MVT VT = SVOp->getSimpleValueType(0);
11655 assert(VT.is128BitVector() && "Unsupported vector size");
11657 std::pair<int, int> Locs[4];
11658 int Mask1[] = { -1, -1, -1, -1 };
11659 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11661 unsigned NumHi = 0;
11662 unsigned NumLo = 0;
11663 for (unsigned i = 0; i != 4; ++i) {
11664 int Idx = PermMask[i];
11666 Locs[i] = std::make_pair(-1, -1);
11668 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11670 Locs[i] = std::make_pair(0, NumLo);
11671 Mask1[NumLo] = Idx;
11674 Locs[i] = std::make_pair(1, NumHi);
11676 Mask1[2+NumHi] = Idx;
11682 if (NumLo <= 2 && NumHi <= 2) {
11683 // If no more than two elements come from either vector. This can be
11684 // implemented with two shuffles. First shuffle gather the elements.
11685 // The second shuffle, which takes the first shuffle as both of its
11686 // vector operands, put the elements into the right order.
11687 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11689 int Mask2[] = { -1, -1, -1, -1 };
11691 for (unsigned i = 0; i != 4; ++i)
11692 if (Locs[i].first != -1) {
11693 unsigned Idx = (i < 2) ? 0 : 4;
11694 Idx += Locs[i].first * 2 + Locs[i].second;
11698 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11701 if (NumLo == 3 || NumHi == 3) {
11702 // Otherwise, we must have three elements from one vector, call it X, and
11703 // one element from the other, call it Y. First, use a shufps to build an
11704 // intermediate vector with the one element from Y and the element from X
11705 // that will be in the same half in the final destination (the indexes don't
11706 // matter). Then, use a shufps to build the final vector, taking the half
11707 // containing the element from Y from the intermediate, and the other half
11710 // Normalize it so the 3 elements come from V1.
11711 CommuteVectorShuffleMask(PermMask, 4);
11715 // Find the element from V2.
11717 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11718 int Val = PermMask[HiIndex];
11725 Mask1[0] = PermMask[HiIndex];
11727 Mask1[2] = PermMask[HiIndex^1];
11729 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11731 if (HiIndex >= 2) {
11732 Mask1[0] = PermMask[0];
11733 Mask1[1] = PermMask[1];
11734 Mask1[2] = HiIndex & 1 ? 6 : 4;
11735 Mask1[3] = HiIndex & 1 ? 4 : 6;
11736 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11739 Mask1[0] = HiIndex & 1 ? 2 : 0;
11740 Mask1[1] = HiIndex & 1 ? 0 : 2;
11741 Mask1[2] = PermMask[2];
11742 Mask1[3] = PermMask[3];
11747 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11750 // Break it into (shuffle shuffle_hi, shuffle_lo).
11751 int LoMask[] = { -1, -1, -1, -1 };
11752 int HiMask[] = { -1, -1, -1, -1 };
11754 int *MaskPtr = LoMask;
11755 unsigned MaskIdx = 0;
11756 unsigned LoIdx = 0;
11757 unsigned HiIdx = 2;
11758 for (unsigned i = 0; i != 4; ++i) {
11765 int Idx = PermMask[i];
11767 Locs[i] = std::make_pair(-1, -1);
11768 } else if (Idx < 4) {
11769 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11770 MaskPtr[LoIdx] = Idx;
11773 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11774 MaskPtr[HiIdx] = Idx;
11779 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11780 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11781 int MaskOps[] = { -1, -1, -1, -1 };
11782 for (unsigned i = 0; i != 4; ++i)
11783 if (Locs[i].first != -1)
11784 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11785 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11788 static bool MayFoldVectorLoad(SDValue V) {
11789 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11790 V = V.getOperand(0);
11792 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11793 V = V.getOperand(0);
11794 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11795 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11796 // BUILD_VECTOR (load), undef
11797 V = V.getOperand(0);
11799 return MayFoldLoad(V);
11803 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11804 MVT VT = Op.getSimpleValueType();
11806 // Canonizalize to v2f64.
11807 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11808 return DAG.getNode(ISD::BITCAST, dl, VT,
11809 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11814 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11816 SDValue V1 = Op.getOperand(0);
11817 SDValue V2 = Op.getOperand(1);
11818 MVT VT = Op.getSimpleValueType();
11820 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11822 if (HasSSE2 && VT == MVT::v2f64)
11823 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11825 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11826 return DAG.getNode(ISD::BITCAST, dl, VT,
11827 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11828 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11829 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11833 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11834 SDValue V1 = Op.getOperand(0);
11835 SDValue V2 = Op.getOperand(1);
11836 MVT VT = Op.getSimpleValueType();
11838 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11839 "unsupported shuffle type");
11841 if (V2.getOpcode() == ISD::UNDEF)
11845 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11849 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11850 SDValue V1 = Op.getOperand(0);
11851 SDValue V2 = Op.getOperand(1);
11852 MVT VT = Op.getSimpleValueType();
11853 unsigned NumElems = VT.getVectorNumElements();
11855 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11856 // operand of these instructions is only memory, so check if there's a
11857 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11859 bool CanFoldLoad = false;
11861 // Trivial case, when V2 comes from a load.
11862 if (MayFoldVectorLoad(V2))
11863 CanFoldLoad = true;
11865 // When V1 is a load, it can be folded later into a store in isel, example:
11866 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11868 // (MOVLPSmr addr:$src1, VR128:$src2)
11869 // So, recognize this potential and also use MOVLPS or MOVLPD
11870 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11871 CanFoldLoad = true;
11873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11875 if (HasSSE2 && NumElems == 2)
11876 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11879 // If we don't care about the second element, proceed to use movss.
11880 if (SVOp->getMaskElt(1) != -1)
11881 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11884 // movl and movlp will both match v2i64, but v2i64 is never matched by
11885 // movl earlier because we make it strict to avoid messing with the movlp load
11886 // folding logic (see the code above getMOVLP call). Match it here then,
11887 // this is horrible, but will stay like this until we move all shuffle
11888 // matching to x86 specific nodes. Note that for the 1st condition all
11889 // types are matched with movsd.
11891 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11892 // as to remove this logic from here, as much as possible
11893 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11894 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11895 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11898 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11900 // Invert the operand order and use SHUFPS to match it.
11901 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11902 getShuffleSHUFImmediate(SVOp), DAG);
11905 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11906 SelectionDAG &DAG) {
11908 MVT VT = Load->getSimpleValueType(0);
11909 MVT EVT = VT.getVectorElementType();
11910 SDValue Addr = Load->getOperand(1);
11911 SDValue NewAddr = DAG.getNode(
11912 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11913 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11916 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11917 DAG.getMachineFunction().getMachineMemOperand(
11918 Load->getMemOperand(), 0, EVT.getStoreSize()));
11922 // It is only safe to call this function if isINSERTPSMask is true for
11923 // this shufflevector mask.
11924 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11925 SelectionDAG &DAG) {
11926 // Generate an insertps instruction when inserting an f32 from memory onto a
11927 // v4f32 or when copying a member from one v4f32 to another.
11928 // We also use it for transferring i32 from one register to another,
11929 // since it simply copies the same bits.
11930 // If we're transferring an i32 from memory to a specific element in a
11931 // register, we output a generic DAG that will match the PINSRD
11933 MVT VT = SVOp->getSimpleValueType(0);
11934 MVT EVT = VT.getVectorElementType();
11935 SDValue V1 = SVOp->getOperand(0);
11936 SDValue V2 = SVOp->getOperand(1);
11937 auto Mask = SVOp->getMask();
11938 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11939 "unsupported vector type for insertps/pinsrd");
11941 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11942 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11943 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11947 unsigned DestIndex;
11951 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11954 // If we have 1 element from each vector, we have to check if we're
11955 // changing V1's element's place. If so, we're done. Otherwise, we
11956 // should assume we're changing V2's element's place and behave
11958 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11959 assert(DestIndex <= INT32_MAX && "truncated destination index");
11960 if (FromV1 == FromV2 &&
11961 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11965 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11968 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11969 "More than one element from V1 and from V2, or no elements from one "
11970 "of the vectors. This case should not have returned true from "
11975 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11978 // Get an index into the source vector in the range [0,4) (the mask is
11979 // in the range [0,8) because it can address V1 and V2)
11980 unsigned SrcIndex = Mask[DestIndex] % 4;
11981 if (MayFoldLoad(From)) {
11982 // Trivial case, when From comes from a load and is only used by the
11983 // shuffle. Make it use insertps from the vector that we need from that
11986 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11987 if (!NewLoad.getNode())
11990 if (EVT == MVT::f32) {
11991 // Create this as a scalar to vector to match the instruction pattern.
11992 SDValue LoadScalarToVector =
11993 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11994 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11995 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11997 } else { // EVT == MVT::i32
11998 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11999 // instruction, to match the PINSRD instruction, which loads an i32 to a
12000 // certain vector element.
12001 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12002 DAG.getConstant(DestIndex, MVT::i32));
12006 // Vector-element-to-vector
12007 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12008 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12011 // Reduce a vector shuffle to zext.
12012 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12013 SelectionDAG &DAG) {
12014 // PMOVZX is only available from SSE41.
12015 if (!Subtarget->hasSSE41())
12018 MVT VT = Op.getSimpleValueType();
12020 // Only AVX2 support 256-bit vector integer extending.
12021 if (!Subtarget->hasInt256() && VT.is256BitVector())
12024 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12026 SDValue V1 = Op.getOperand(0);
12027 SDValue V2 = Op.getOperand(1);
12028 unsigned NumElems = VT.getVectorNumElements();
12030 // Extending is an unary operation and the element type of the source vector
12031 // won't be equal to or larger than i64.
12032 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12033 VT.getVectorElementType() == MVT::i64)
12036 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12037 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12038 while ((1U << Shift) < NumElems) {
12039 if (SVOp->getMaskElt(1U << Shift) == 1)
12042 // The maximal ratio is 8, i.e. from i8 to i64.
12047 // Check the shuffle mask.
12048 unsigned Mask = (1U << Shift) - 1;
12049 for (unsigned i = 0; i != NumElems; ++i) {
12050 int EltIdx = SVOp->getMaskElt(i);
12051 if ((i & Mask) != 0 && EltIdx != -1)
12053 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12057 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12058 MVT NeVT = MVT::getIntegerVT(NBits);
12059 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12061 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12064 return DAG.getNode(ISD::BITCAST, DL, VT,
12065 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12068 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12069 SelectionDAG &DAG) {
12070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12071 MVT VT = Op.getSimpleValueType();
12073 SDValue V1 = Op.getOperand(0);
12074 SDValue V2 = Op.getOperand(1);
12076 if (isZeroShuffle(SVOp))
12077 return getZeroVector(VT, Subtarget, DAG, dl);
12079 // Handle splat operations
12080 if (SVOp->isSplat()) {
12081 // Use vbroadcast whenever the splat comes from a foldable load
12082 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12083 if (Broadcast.getNode())
12087 // Check integer expanding shuffles.
12088 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12089 if (NewOp.getNode())
12092 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12094 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12095 VT == MVT::v32i8) {
12096 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12097 if (NewOp.getNode())
12098 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12099 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12100 // FIXME: Figure out a cleaner way to do this.
12101 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12102 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12103 if (NewOp.getNode()) {
12104 MVT NewVT = NewOp.getSimpleValueType();
12105 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12106 NewVT, true, false))
12107 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12110 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12111 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12112 if (NewOp.getNode()) {
12113 MVT NewVT = NewOp.getSimpleValueType();
12114 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12115 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12124 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12126 SDValue V1 = Op.getOperand(0);
12127 SDValue V2 = Op.getOperand(1);
12128 MVT VT = Op.getSimpleValueType();
12130 unsigned NumElems = VT.getVectorNumElements();
12131 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12132 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12133 bool V1IsSplat = false;
12134 bool V2IsSplat = false;
12135 bool HasSSE2 = Subtarget->hasSSE2();
12136 bool HasFp256 = Subtarget->hasFp256();
12137 bool HasInt256 = Subtarget->hasInt256();
12138 MachineFunction &MF = DAG.getMachineFunction();
12139 bool OptForSize = MF.getFunction()->getAttributes().
12140 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12142 // Check if we should use the experimental vector shuffle lowering. If so,
12143 // delegate completely to that code path.
12144 if (ExperimentalVectorShuffleLowering)
12145 return lowerVectorShuffle(Op, Subtarget, DAG);
12147 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12149 if (V1IsUndef && V2IsUndef)
12150 return DAG.getUNDEF(VT);
12152 // When we create a shuffle node we put the UNDEF node to second operand,
12153 // but in some cases the first operand may be transformed to UNDEF.
12154 // In this case we should just commute the node.
12156 return DAG.getCommutedVectorShuffle(*SVOp);
12158 // Vector shuffle lowering takes 3 steps:
12160 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12161 // narrowing and commutation of operands should be handled.
12162 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12164 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12165 // so the shuffle can be broken into other shuffles and the legalizer can
12166 // try the lowering again.
12168 // The general idea is that no vector_shuffle operation should be left to
12169 // be matched during isel, all of them must be converted to a target specific
12172 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12173 // narrowing and commutation of operands should be handled. The actual code
12174 // doesn't include all of those, work in progress...
12175 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12176 if (NewOp.getNode())
12179 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12181 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12182 // unpckh_undef). Only use pshufd if speed is more important than size.
12183 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12184 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12185 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12186 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12188 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12189 V2IsUndef && MayFoldVectorLoad(V1))
12190 return getMOVDDup(Op, dl, V1, DAG);
12192 if (isMOVHLPS_v_undef_Mask(M, VT))
12193 return getMOVHighToLow(Op, dl, DAG);
12195 // Use to match splats
12196 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12197 (VT == MVT::v2f64 || VT == MVT::v2i64))
12198 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12200 if (isPSHUFDMask(M, VT)) {
12201 // The actual implementation will match the mask in the if above and then
12202 // during isel it can match several different instructions, not only pshufd
12203 // as its name says, sad but true, emulate the behavior for now...
12204 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12205 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12207 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12209 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12210 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12212 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12213 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12216 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12220 if (isPALIGNRMask(M, VT, Subtarget))
12221 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12222 getShufflePALIGNRImmediate(SVOp),
12225 if (isVALIGNMask(M, VT, Subtarget))
12226 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12227 getShuffleVALIGNImmediate(SVOp),
12230 // Check if this can be converted into a logical shift.
12231 bool isLeft = false;
12232 unsigned ShAmt = 0;
12234 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12235 if (isShift && ShVal.hasOneUse()) {
12236 // If the shifted value has multiple uses, it may be cheaper to use
12237 // v_set0 + movlhps or movhlps, etc.
12238 MVT EltVT = VT.getVectorElementType();
12239 ShAmt *= EltVT.getSizeInBits();
12240 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12243 if (isMOVLMask(M, VT)) {
12244 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12245 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12246 if (!isMOVLPMask(M, VT)) {
12247 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12248 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12250 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12251 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12255 // FIXME: fold these into legal mask.
12256 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12257 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12259 if (isMOVHLPSMask(M, VT))
12260 return getMOVHighToLow(Op, dl, DAG);
12262 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12263 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12265 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12266 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12268 if (isMOVLPMask(M, VT))
12269 return getMOVLP(Op, dl, DAG, HasSSE2);
12271 if (ShouldXformToMOVHLPS(M, VT) ||
12272 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12273 return DAG.getCommutedVectorShuffle(*SVOp);
12276 // No better options. Use a vshldq / vsrldq.
12277 MVT EltVT = VT.getVectorElementType();
12278 ShAmt *= EltVT.getSizeInBits();
12279 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12282 bool Commuted = false;
12283 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12284 // 1,1,1,1 -> v8i16 though.
12285 BitVector UndefElements;
12286 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12287 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12289 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12290 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12293 // Canonicalize the splat or undef, if present, to be on the RHS.
12294 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12295 CommuteVectorShuffleMask(M, NumElems);
12297 std::swap(V1IsSplat, V2IsSplat);
12301 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12302 // Shuffling low element of v1 into undef, just return v1.
12305 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12306 // the instruction selector will not match, so get a canonical MOVL with
12307 // swapped operands to undo the commute.
12308 return getMOVL(DAG, dl, VT, V2, V1);
12311 if (isUNPCKLMask(M, VT, HasInt256))
12312 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12314 if (isUNPCKHMask(M, VT, HasInt256))
12315 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12318 // Normalize mask so all entries that point to V2 points to its first
12319 // element then try to match unpck{h|l} again. If match, return a
12320 // new vector_shuffle with the corrected mask.p
12321 SmallVector<int, 8> NewMask(M.begin(), M.end());
12322 NormalizeMask(NewMask, NumElems);
12323 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12324 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12325 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12326 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12330 // Commute is back and try unpck* again.
12331 // FIXME: this seems wrong.
12332 CommuteVectorShuffleMask(M, NumElems);
12334 std::swap(V1IsSplat, V2IsSplat);
12336 if (isUNPCKLMask(M, VT, HasInt256))
12337 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12339 if (isUNPCKHMask(M, VT, HasInt256))
12340 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12343 // Normalize the node to match x86 shuffle ops if needed
12344 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12345 return DAG.getCommutedVectorShuffle(*SVOp);
12347 // The checks below are all present in isShuffleMaskLegal, but they are
12348 // inlined here right now to enable us to directly emit target specific
12349 // nodes, and remove one by one until they don't return Op anymore.
12351 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12352 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12353 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12354 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12357 if (isPSHUFHWMask(M, VT, HasInt256))
12358 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12359 getShufflePSHUFHWImmediate(SVOp),
12362 if (isPSHUFLWMask(M, VT, HasInt256))
12363 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12364 getShufflePSHUFLWImmediate(SVOp),
12367 unsigned MaskValue;
12368 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12370 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12372 if (isSHUFPMask(M, VT))
12373 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12374 getShuffleSHUFImmediate(SVOp), DAG);
12376 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12377 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12378 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12379 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12381 //===--------------------------------------------------------------------===//
12382 // Generate target specific nodes for 128 or 256-bit shuffles only
12383 // supported in the AVX instruction set.
12386 // Handle VMOVDDUPY permutations
12387 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12388 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12390 // Handle VPERMILPS/D* permutations
12391 if (isVPERMILPMask(M, VT)) {
12392 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12393 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12394 getShuffleSHUFImmediate(SVOp), DAG);
12395 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12396 getShuffleSHUFImmediate(SVOp), DAG);
12400 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12401 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12402 Idx*(NumElems/2), DAG, dl);
12404 // Handle VPERM2F128/VPERM2I128 permutations
12405 if (isVPERM2X128Mask(M, VT, HasFp256))
12406 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12407 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12409 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12410 return getINSERTPS(SVOp, dl, DAG);
12413 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12414 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12416 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12417 VT.is512BitVector()) {
12418 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12419 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12420 SmallVector<SDValue, 16> permclMask;
12421 for (unsigned i = 0; i != NumElems; ++i) {
12422 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12425 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12427 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12428 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12429 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12430 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12431 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12434 //===--------------------------------------------------------------------===//
12435 // Since no target specific shuffle was selected for this generic one,
12436 // lower it into other known shuffles. FIXME: this isn't true yet, but
12437 // this is the plan.
12440 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12441 if (VT == MVT::v8i16) {
12442 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12443 if (NewOp.getNode())
12447 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12448 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12449 if (NewOp.getNode())
12453 if (VT == MVT::v16i8) {
12454 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12455 if (NewOp.getNode())
12459 if (VT == MVT::v32i8) {
12460 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12461 if (NewOp.getNode())
12465 // Handle all 128-bit wide vectors with 4 elements, and match them with
12466 // several different shuffle types.
12467 if (NumElems == 4 && VT.is128BitVector())
12468 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12470 // Handle general 256-bit shuffles
12471 if (VT.is256BitVector())
12472 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12477 // This function assumes its argument is a BUILD_VECTOR of constants or
12478 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12480 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12481 unsigned &MaskValue) {
12483 unsigned NumElems = BuildVector->getNumOperands();
12484 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12485 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12486 unsigned NumElemsInLane = NumElems / NumLanes;
12488 // Blend for v16i16 should be symetric for the both lanes.
12489 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12490 SDValue EltCond = BuildVector->getOperand(i);
12491 SDValue SndLaneEltCond =
12492 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12494 int Lane1Cond = -1, Lane2Cond = -1;
12495 if (isa<ConstantSDNode>(EltCond))
12496 Lane1Cond = !isZero(EltCond);
12497 if (isa<ConstantSDNode>(SndLaneEltCond))
12498 Lane2Cond = !isZero(SndLaneEltCond);
12500 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12501 // Lane1Cond != 0, means we want the first argument.
12502 // Lane1Cond == 0, means we want the second argument.
12503 // The encoding of this argument is 0 for the first argument, 1
12504 // for the second. Therefore, invert the condition.
12505 MaskValue |= !Lane1Cond << i;
12506 else if (Lane1Cond < 0)
12507 MaskValue |= !Lane2Cond << i;
12514 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12516 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12517 SelectionDAG &DAG) {
12518 SDValue Cond = Op.getOperand(0);
12519 SDValue LHS = Op.getOperand(1);
12520 SDValue RHS = Op.getOperand(2);
12522 MVT VT = Op.getSimpleValueType();
12523 MVT EltVT = VT.getVectorElementType();
12524 unsigned NumElems = VT.getVectorNumElements();
12526 // There is no blend with immediate in AVX-512.
12527 if (VT.is512BitVector())
12530 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12532 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12535 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12538 // Check the mask for BLEND and build the value.
12539 unsigned MaskValue = 0;
12540 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12543 // Convert i32 vectors to floating point if it is not AVX2.
12544 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12546 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12547 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12549 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12550 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12553 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12554 DAG.getConstant(MaskValue, MVT::i32));
12555 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12558 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12559 // A vselect where all conditions and data are constants can be optimized into
12560 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12561 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12562 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12563 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12566 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12567 if (BlendOp.getNode())
12570 // Some types for vselect were previously set to Expand, not Legal or
12571 // Custom. Return an empty SDValue so we fall-through to Expand, after
12572 // the Custom lowering phase.
12573 MVT VT = Op.getSimpleValueType();
12574 switch (VT.SimpleTy) {
12579 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12584 // We couldn't create a "Blend with immediate" node.
12585 // This node should still be legal, but we'll have to emit a blendv*
12590 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12591 MVT VT = Op.getSimpleValueType();
12594 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12597 if (VT.getSizeInBits() == 8) {
12598 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12599 Op.getOperand(0), Op.getOperand(1));
12600 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12601 DAG.getValueType(VT));
12602 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12605 if (VT.getSizeInBits() == 16) {
12606 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12607 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12609 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12610 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12611 DAG.getNode(ISD::BITCAST, dl,
12614 Op.getOperand(1)));
12615 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12616 Op.getOperand(0), Op.getOperand(1));
12617 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12618 DAG.getValueType(VT));
12619 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12622 if (VT == MVT::f32) {
12623 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12624 // the result back to FR32 register. It's only worth matching if the
12625 // result has a single use which is a store or a bitcast to i32. And in
12626 // the case of a store, it's not worth it if the index is a constant 0,
12627 // because a MOVSSmr can be used instead, which is smaller and faster.
12628 if (!Op.hasOneUse())
12630 SDNode *User = *Op.getNode()->use_begin();
12631 if ((User->getOpcode() != ISD::STORE ||
12632 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12633 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12634 (User->getOpcode() != ISD::BITCAST ||
12635 User->getValueType(0) != MVT::i32))
12637 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12638 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12641 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12644 if (VT == MVT::i32 || VT == MVT::i64) {
12645 // ExtractPS/pextrq works with constant index.
12646 if (isa<ConstantSDNode>(Op.getOperand(1)))
12652 /// Extract one bit from mask vector, like v16i1 or v8i1.
12653 /// AVX-512 feature.
12655 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12656 SDValue Vec = Op.getOperand(0);
12658 MVT VecVT = Vec.getSimpleValueType();
12659 SDValue Idx = Op.getOperand(1);
12660 MVT EltVT = Op.getSimpleValueType();
12662 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12664 // variable index can't be handled in mask registers,
12665 // extend vector to VR512
12666 if (!isa<ConstantSDNode>(Idx)) {
12667 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12668 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12669 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12670 ExtVT.getVectorElementType(), Ext, Idx);
12671 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12674 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12675 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12676 unsigned MaxSift = rc->getSize()*8 - 1;
12677 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12678 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12679 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12680 DAG.getConstant(MaxSift, MVT::i8));
12681 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12682 DAG.getIntPtrConstant(0));
12686 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12687 SelectionDAG &DAG) const {
12689 SDValue Vec = Op.getOperand(0);
12690 MVT VecVT = Vec.getSimpleValueType();
12691 SDValue Idx = Op.getOperand(1);
12693 if (Op.getSimpleValueType() == MVT::i1)
12694 return ExtractBitFromMaskVector(Op, DAG);
12696 if (!isa<ConstantSDNode>(Idx)) {
12697 if (VecVT.is512BitVector() ||
12698 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12699 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12702 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12703 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12704 MaskEltVT.getSizeInBits());
12706 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12707 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12708 getZeroVector(MaskVT, Subtarget, DAG, dl),
12709 Idx, DAG.getConstant(0, getPointerTy()));
12710 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12711 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12712 Perm, DAG.getConstant(0, getPointerTy()));
12717 // If this is a 256-bit vector result, first extract the 128-bit vector and
12718 // then extract the element from the 128-bit vector.
12719 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12721 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12722 // Get the 128-bit vector.
12723 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12724 MVT EltVT = VecVT.getVectorElementType();
12726 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12728 //if (IdxVal >= NumElems/2)
12729 // IdxVal -= NumElems/2;
12730 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12731 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12732 DAG.getConstant(IdxVal, MVT::i32));
12735 assert(VecVT.is128BitVector() && "Unexpected vector length");
12737 if (Subtarget->hasSSE41()) {
12738 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12743 MVT VT = Op.getSimpleValueType();
12744 // TODO: handle v16i8.
12745 if (VT.getSizeInBits() == 16) {
12746 SDValue Vec = Op.getOperand(0);
12747 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12749 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12750 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12751 DAG.getNode(ISD::BITCAST, dl,
12753 Op.getOperand(1)));
12754 // Transform it so it match pextrw which produces a 32-bit result.
12755 MVT EltVT = MVT::i32;
12756 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12757 Op.getOperand(0), Op.getOperand(1));
12758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12759 DAG.getValueType(VT));
12760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12763 if (VT.getSizeInBits() == 32) {
12764 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12768 // SHUFPS the element to the lowest double word, then movss.
12769 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12770 MVT VVT = Op.getOperand(0).getSimpleValueType();
12771 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12772 DAG.getUNDEF(VVT), Mask);
12773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12774 DAG.getIntPtrConstant(0));
12777 if (VT.getSizeInBits() == 64) {
12778 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12779 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12780 // to match extract_elt for f64.
12781 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12785 // UNPCKHPD the element to the lowest double word, then movsd.
12786 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12787 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12788 int Mask[2] = { 1, -1 };
12789 MVT VVT = Op.getOperand(0).getSimpleValueType();
12790 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12791 DAG.getUNDEF(VVT), Mask);
12792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12793 DAG.getIntPtrConstant(0));
12799 /// Insert one bit to mask vector, like v16i1 or v8i1.
12800 /// AVX-512 feature.
12802 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12804 SDValue Vec = Op.getOperand(0);
12805 SDValue Elt = Op.getOperand(1);
12806 SDValue Idx = Op.getOperand(2);
12807 MVT VecVT = Vec.getSimpleValueType();
12809 if (!isa<ConstantSDNode>(Idx)) {
12810 // Non constant index. Extend source and destination,
12811 // insert element and then truncate the result.
12812 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12813 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12814 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12815 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12816 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12817 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12820 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12821 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12822 if (Vec.getOpcode() == ISD::UNDEF)
12823 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12824 DAG.getConstant(IdxVal, MVT::i8));
12825 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12826 unsigned MaxSift = rc->getSize()*8 - 1;
12827 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12828 DAG.getConstant(MaxSift, MVT::i8));
12829 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12830 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12831 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12834 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12835 SelectionDAG &DAG) const {
12836 MVT VT = Op.getSimpleValueType();
12837 MVT EltVT = VT.getVectorElementType();
12839 if (EltVT == MVT::i1)
12840 return InsertBitToMaskVector(Op, DAG);
12843 SDValue N0 = Op.getOperand(0);
12844 SDValue N1 = Op.getOperand(1);
12845 SDValue N2 = Op.getOperand(2);
12846 if (!isa<ConstantSDNode>(N2))
12848 auto *N2C = cast<ConstantSDNode>(N2);
12849 unsigned IdxVal = N2C->getZExtValue();
12851 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12852 // into that, and then insert the subvector back into the result.
12853 if (VT.is256BitVector() || VT.is512BitVector()) {
12854 // Get the desired 128-bit vector half.
12855 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12857 // Insert the element into the desired half.
12858 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12859 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12861 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12862 DAG.getConstant(IdxIn128, MVT::i32));
12864 // Insert the changed part back to the 256-bit vector
12865 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12867 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12869 if (Subtarget->hasSSE41()) {
12870 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12872 if (VT == MVT::v8i16) {
12873 Opc = X86ISD::PINSRW;
12875 assert(VT == MVT::v16i8);
12876 Opc = X86ISD::PINSRB;
12879 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12881 if (N1.getValueType() != MVT::i32)
12882 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12883 if (N2.getValueType() != MVT::i32)
12884 N2 = DAG.getIntPtrConstant(IdxVal);
12885 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12888 if (EltVT == MVT::f32) {
12889 // Bits [7:6] of the constant are the source select. This will always be
12890 // zero here. The DAG Combiner may combine an extract_elt index into
12892 // bits. For example (insert (extract, 3), 2) could be matched by
12894 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12895 // Bits [5:4] of the constant are the destination select. This is the
12896 // value of the incoming immediate.
12897 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12898 // combine either bitwise AND or insert of float 0.0 to set these bits.
12899 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12900 // Create this as a scalar to vector..
12901 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12902 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12905 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12906 // PINSR* works with constant index.
12911 if (EltVT == MVT::i8)
12914 if (EltVT.getSizeInBits() == 16) {
12915 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12916 // as its second argument.
12917 if (N1.getValueType() != MVT::i32)
12918 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12919 if (N2.getValueType() != MVT::i32)
12920 N2 = DAG.getIntPtrConstant(IdxVal);
12921 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12926 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12928 MVT OpVT = Op.getSimpleValueType();
12930 // If this is a 256-bit vector result, first insert into a 128-bit
12931 // vector and then insert into the 256-bit vector.
12932 if (!OpVT.is128BitVector()) {
12933 // Insert into a 128-bit vector.
12934 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12935 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12936 OpVT.getVectorNumElements() / SizeFactor);
12938 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12940 // Insert the 128-bit vector.
12941 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12944 if (OpVT == MVT::v1i64 &&
12945 Op.getOperand(0).getValueType() == MVT::i64)
12946 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12948 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12949 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12950 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12951 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12954 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12955 // a simple subregister reference or explicit instructions to grab
12956 // upper bits of a vector.
12957 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12958 SelectionDAG &DAG) {
12960 SDValue In = Op.getOperand(0);
12961 SDValue Idx = Op.getOperand(1);
12962 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12963 MVT ResVT = Op.getSimpleValueType();
12964 MVT InVT = In.getSimpleValueType();
12966 if (Subtarget->hasFp256()) {
12967 if (ResVT.is128BitVector() &&
12968 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12969 isa<ConstantSDNode>(Idx)) {
12970 return Extract128BitVector(In, IdxVal, DAG, dl);
12972 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12973 isa<ConstantSDNode>(Idx)) {
12974 return Extract256BitVector(In, IdxVal, DAG, dl);
12980 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12981 // simple superregister reference or explicit instructions to insert
12982 // the upper bits of a vector.
12983 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12984 SelectionDAG &DAG) {
12985 if (Subtarget->hasFp256()) {
12986 SDLoc dl(Op.getNode());
12987 SDValue Vec = Op.getNode()->getOperand(0);
12988 SDValue SubVec = Op.getNode()->getOperand(1);
12989 SDValue Idx = Op.getNode()->getOperand(2);
12991 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12992 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12993 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12994 isa<ConstantSDNode>(Idx)) {
12995 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12996 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12999 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13000 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13001 isa<ConstantSDNode>(Idx)) {
13002 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13003 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13009 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13010 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13011 // one of the above mentioned nodes. It has to be wrapped because otherwise
13012 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13013 // be used to form addressing mode. These wrapped nodes will be selected
13016 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13017 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13019 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13020 // global base reg.
13021 unsigned char OpFlag = 0;
13022 unsigned WrapperKind = X86ISD::Wrapper;
13023 CodeModel::Model M = DAG.getTarget().getCodeModel();
13025 if (Subtarget->isPICStyleRIPRel() &&
13026 (M == CodeModel::Small || M == CodeModel::Kernel))
13027 WrapperKind = X86ISD::WrapperRIP;
13028 else if (Subtarget->isPICStyleGOT())
13029 OpFlag = X86II::MO_GOTOFF;
13030 else if (Subtarget->isPICStyleStubPIC())
13031 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13033 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13034 CP->getAlignment(),
13035 CP->getOffset(), OpFlag);
13037 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13038 // With PIC, the address is actually $g + Offset.
13040 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13041 DAG.getNode(X86ISD::GlobalBaseReg,
13042 SDLoc(), getPointerTy()),
13049 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13050 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13052 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13053 // global base reg.
13054 unsigned char OpFlag = 0;
13055 unsigned WrapperKind = X86ISD::Wrapper;
13056 CodeModel::Model M = DAG.getTarget().getCodeModel();
13058 if (Subtarget->isPICStyleRIPRel() &&
13059 (M == CodeModel::Small || M == CodeModel::Kernel))
13060 WrapperKind = X86ISD::WrapperRIP;
13061 else if (Subtarget->isPICStyleGOT())
13062 OpFlag = X86II::MO_GOTOFF;
13063 else if (Subtarget->isPICStyleStubPIC())
13064 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13066 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13069 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13071 // With PIC, the address is actually $g + Offset.
13073 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13074 DAG.getNode(X86ISD::GlobalBaseReg,
13075 SDLoc(), getPointerTy()),
13082 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13083 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13085 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13086 // global base reg.
13087 unsigned char OpFlag = 0;
13088 unsigned WrapperKind = X86ISD::Wrapper;
13089 CodeModel::Model M = DAG.getTarget().getCodeModel();
13091 if (Subtarget->isPICStyleRIPRel() &&
13092 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13093 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13094 OpFlag = X86II::MO_GOTPCREL;
13095 WrapperKind = X86ISD::WrapperRIP;
13096 } else if (Subtarget->isPICStyleGOT()) {
13097 OpFlag = X86II::MO_GOT;
13098 } else if (Subtarget->isPICStyleStubPIC()) {
13099 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13100 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13101 OpFlag = X86II::MO_DARWIN_NONLAZY;
13104 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13107 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13109 // With PIC, the address is actually $g + Offset.
13110 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13111 !Subtarget->is64Bit()) {
13112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13113 DAG.getNode(X86ISD::GlobalBaseReg,
13114 SDLoc(), getPointerTy()),
13118 // For symbols that require a load from a stub to get the address, emit the
13120 if (isGlobalStubReference(OpFlag))
13121 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13122 MachinePointerInfo::getGOT(), false, false, false, 0);
13128 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13129 // Create the TargetBlockAddressAddress node.
13130 unsigned char OpFlags =
13131 Subtarget->ClassifyBlockAddressReference();
13132 CodeModel::Model M = DAG.getTarget().getCodeModel();
13133 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13134 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13136 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13139 if (Subtarget->isPICStyleRIPRel() &&
13140 (M == CodeModel::Small || M == CodeModel::Kernel))
13141 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13143 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13145 // With PIC, the address is actually $g + Offset.
13146 if (isGlobalRelativeToPICBase(OpFlags)) {
13147 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13148 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13156 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13157 int64_t Offset, SelectionDAG &DAG) const {
13158 // Create the TargetGlobalAddress node, folding in the constant
13159 // offset if it is legal.
13160 unsigned char OpFlags =
13161 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13162 CodeModel::Model M = DAG.getTarget().getCodeModel();
13164 if (OpFlags == X86II::MO_NO_FLAG &&
13165 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13166 // A direct static reference to a global.
13167 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13170 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13173 if (Subtarget->isPICStyleRIPRel() &&
13174 (M == CodeModel::Small || M == CodeModel::Kernel))
13175 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13177 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13179 // With PIC, the address is actually $g + Offset.
13180 if (isGlobalRelativeToPICBase(OpFlags)) {
13181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13182 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13186 // For globals that require a load from a stub to get the address, emit the
13188 if (isGlobalStubReference(OpFlags))
13189 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13190 MachinePointerInfo::getGOT(), false, false, false, 0);
13192 // If there was a non-zero offset that we didn't fold, create an explicit
13193 // addition for it.
13195 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13196 DAG.getConstant(Offset, getPointerTy()));
13202 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13203 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13204 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13205 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13209 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13210 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13211 unsigned char OperandFlags, bool LocalDynamic = false) {
13212 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13213 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13215 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13216 GA->getValueType(0),
13220 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13224 SDValue Ops[] = { Chain, TGA, *InFlag };
13225 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13227 SDValue Ops[] = { Chain, TGA };
13228 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13231 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13232 MFI->setAdjustsStack(true);
13233 MFI->setHasCalls(true);
13235 SDValue Flag = Chain.getValue(1);
13236 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13239 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13241 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13244 SDLoc dl(GA); // ? function entry point might be better
13245 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13246 DAG.getNode(X86ISD::GlobalBaseReg,
13247 SDLoc(), PtrVT), InFlag);
13248 InFlag = Chain.getValue(1);
13250 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13253 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13255 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13257 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13258 X86::RAX, X86II::MO_TLSGD);
13261 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13267 // Get the start address of the TLS block for this module.
13268 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13269 .getInfo<X86MachineFunctionInfo>();
13270 MFI->incNumLocalDynamicTLSAccesses();
13274 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13275 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13278 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13279 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13280 InFlag = Chain.getValue(1);
13281 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13282 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13285 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13289 unsigned char OperandFlags = X86II::MO_DTPOFF;
13290 unsigned WrapperKind = X86ISD::Wrapper;
13291 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13292 GA->getValueType(0),
13293 GA->getOffset(), OperandFlags);
13294 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13296 // Add x@dtpoff with the base.
13297 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13300 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13301 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13302 const EVT PtrVT, TLSModel::Model model,
13303 bool is64Bit, bool isPIC) {
13306 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13307 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13308 is64Bit ? 257 : 256));
13310 SDValue ThreadPointer =
13311 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13312 MachinePointerInfo(Ptr), false, false, false, 0);
13314 unsigned char OperandFlags = 0;
13315 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13317 unsigned WrapperKind = X86ISD::Wrapper;
13318 if (model == TLSModel::LocalExec) {
13319 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13320 } else if (model == TLSModel::InitialExec) {
13322 OperandFlags = X86II::MO_GOTTPOFF;
13323 WrapperKind = X86ISD::WrapperRIP;
13325 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13328 llvm_unreachable("Unexpected model");
13331 // emit "addl x@ntpoff,%eax" (local exec)
13332 // or "addl x@indntpoff,%eax" (initial exec)
13333 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13335 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13336 GA->getOffset(), OperandFlags);
13337 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13339 if (model == TLSModel::InitialExec) {
13340 if (isPIC && !is64Bit) {
13341 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13342 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13346 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13347 MachinePointerInfo::getGOT(), false, false, false, 0);
13350 // The address of the thread local variable is the add of the thread
13351 // pointer with the offset of the variable.
13352 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13356 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13358 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13359 const GlobalValue *GV = GA->getGlobal();
13361 if (Subtarget->isTargetELF()) {
13362 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13365 case TLSModel::GeneralDynamic:
13366 if (Subtarget->is64Bit())
13367 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13368 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13369 case TLSModel::LocalDynamic:
13370 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13371 Subtarget->is64Bit());
13372 case TLSModel::InitialExec:
13373 case TLSModel::LocalExec:
13374 return LowerToTLSExecModel(
13375 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13376 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13378 llvm_unreachable("Unknown TLS model.");
13381 if (Subtarget->isTargetDarwin()) {
13382 // Darwin only has one model of TLS. Lower to that.
13383 unsigned char OpFlag = 0;
13384 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13385 X86ISD::WrapperRIP : X86ISD::Wrapper;
13387 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13388 // global base reg.
13389 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13390 !Subtarget->is64Bit();
13392 OpFlag = X86II::MO_TLVP_PIC_BASE;
13394 OpFlag = X86II::MO_TLVP;
13396 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13397 GA->getValueType(0),
13398 GA->getOffset(), OpFlag);
13399 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13401 // With PIC32, the address is actually $g + Offset.
13403 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13404 DAG.getNode(X86ISD::GlobalBaseReg,
13405 SDLoc(), getPointerTy()),
13408 // Lowering the machine isd will make sure everything is in the right
13410 SDValue Chain = DAG.getEntryNode();
13411 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13412 SDValue Args[] = { Chain, Offset };
13413 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13415 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13416 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13417 MFI->setAdjustsStack(true);
13419 // And our return value (tls address) is in the standard call return value
13421 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13422 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13423 Chain.getValue(1));
13426 if (Subtarget->isTargetKnownWindowsMSVC() ||
13427 Subtarget->isTargetWindowsGNU()) {
13428 // Just use the implicit TLS architecture
13429 // Need to generate someting similar to:
13430 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13432 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13433 // mov rcx, qword [rdx+rcx*8]
13434 // mov eax, .tls$:tlsvar
13435 // [rax+rcx] contains the address
13436 // Windows 64bit: gs:0x58
13437 // Windows 32bit: fs:__tls_array
13440 SDValue Chain = DAG.getEntryNode();
13442 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13443 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13444 // use its literal value of 0x2C.
13445 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13446 ? Type::getInt8PtrTy(*DAG.getContext(),
13448 : Type::getInt32PtrTy(*DAG.getContext(),
13452 Subtarget->is64Bit()
13453 ? DAG.getIntPtrConstant(0x58)
13454 : (Subtarget->isTargetWindowsGNU()
13455 ? DAG.getIntPtrConstant(0x2C)
13456 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13458 SDValue ThreadPointer =
13459 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13460 MachinePointerInfo(Ptr), false, false, false, 0);
13462 // Load the _tls_index variable
13463 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13464 if (Subtarget->is64Bit())
13465 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13466 IDX, MachinePointerInfo(), MVT::i32,
13467 false, false, false, 0);
13469 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13470 false, false, false, 0);
13472 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13474 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13476 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13477 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13478 false, false, false, 0);
13480 // Get the offset of start of .tls section
13481 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13482 GA->getValueType(0),
13483 GA->getOffset(), X86II::MO_SECREL);
13484 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13486 // The address of the thread local variable is the add of the thread
13487 // pointer with the offset of the variable.
13488 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13491 llvm_unreachable("TLS not implemented for this target.");
13494 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13495 /// and take a 2 x i32 value to shift plus a shift amount.
13496 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13497 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13498 MVT VT = Op.getSimpleValueType();
13499 unsigned VTBits = VT.getSizeInBits();
13501 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13502 SDValue ShOpLo = Op.getOperand(0);
13503 SDValue ShOpHi = Op.getOperand(1);
13504 SDValue ShAmt = Op.getOperand(2);
13505 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13506 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13508 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13509 DAG.getConstant(VTBits - 1, MVT::i8));
13510 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13511 DAG.getConstant(VTBits - 1, MVT::i8))
13512 : DAG.getConstant(0, VT);
13514 SDValue Tmp2, Tmp3;
13515 if (Op.getOpcode() == ISD::SHL_PARTS) {
13516 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13517 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13519 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13520 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13523 // If the shift amount is larger or equal than the width of a part we can't
13524 // rely on the results of shld/shrd. Insert a test and select the appropriate
13525 // values for large shift amounts.
13526 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13527 DAG.getConstant(VTBits, MVT::i8));
13528 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13529 AndNode, DAG.getConstant(0, MVT::i8));
13532 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13533 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13534 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13536 if (Op.getOpcode() == ISD::SHL_PARTS) {
13537 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13538 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13540 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13541 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13544 SDValue Ops[2] = { Lo, Hi };
13545 return DAG.getMergeValues(Ops, dl);
13548 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13549 SelectionDAG &DAG) const {
13550 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13553 if (SrcVT.isVector()) {
13554 if (SrcVT.getVectorElementType() == MVT::i1) {
13555 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13556 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13557 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13558 Op.getOperand(0)));
13563 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13564 "Unknown SINT_TO_FP to lower!");
13566 // These are really Legal; return the operand so the caller accepts it as
13568 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13570 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13571 Subtarget->is64Bit()) {
13575 unsigned Size = SrcVT.getSizeInBits()/8;
13576 MachineFunction &MF = DAG.getMachineFunction();
13577 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13578 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13579 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13581 MachinePointerInfo::getFixedStack(SSFI),
13583 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13586 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13588 SelectionDAG &DAG) const {
13592 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13594 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13596 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13598 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13600 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13601 MachineMemOperand *MMO;
13603 int SSFI = FI->getIndex();
13605 DAG.getMachineFunction()
13606 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13607 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13609 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13610 StackSlot = StackSlot.getOperand(1);
13612 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13613 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13615 Tys, Ops, SrcVT, MMO);
13618 Chain = Result.getValue(1);
13619 SDValue InFlag = Result.getValue(2);
13621 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13622 // shouldn't be necessary except that RFP cannot be live across
13623 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13624 MachineFunction &MF = DAG.getMachineFunction();
13625 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13626 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13627 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13628 Tys = DAG.getVTList(MVT::Other);
13630 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13632 MachineMemOperand *MMO =
13633 DAG.getMachineFunction()
13634 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13635 MachineMemOperand::MOStore, SSFISize, SSFISize);
13637 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13638 Ops, Op.getValueType(), MMO);
13639 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13640 MachinePointerInfo::getFixedStack(SSFI),
13641 false, false, false, 0);
13647 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13648 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13649 SelectionDAG &DAG) const {
13650 // This algorithm is not obvious. Here it is what we're trying to output:
13653 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13654 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13656 haddpd %xmm0, %xmm0
13658 pshufd $0x4e, %xmm0, %xmm1
13664 LLVMContext *Context = DAG.getContext();
13666 // Build some magic constants.
13667 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13668 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13669 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13671 SmallVector<Constant*,2> CV1;
13673 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13674 APInt(64, 0x4330000000000000ULL))));
13676 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13677 APInt(64, 0x4530000000000000ULL))));
13678 Constant *C1 = ConstantVector::get(CV1);
13679 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13681 // Load the 64-bit value into an XMM register.
13682 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13684 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13685 MachinePointerInfo::getConstantPool(),
13686 false, false, false, 16);
13687 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13688 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13691 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13692 MachinePointerInfo::getConstantPool(),
13693 false, false, false, 16);
13694 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13695 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13698 if (Subtarget->hasSSE3()) {
13699 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13700 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13702 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13703 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13705 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13706 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13710 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13711 DAG.getIntPtrConstant(0));
13714 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13715 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13716 SelectionDAG &DAG) const {
13718 // FP constant to bias correct the final result.
13719 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13722 // Load the 32-bit value into an XMM register.
13723 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13726 // Zero out the upper parts of the register.
13727 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13729 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13730 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13731 DAG.getIntPtrConstant(0));
13733 // Or the load with the bias.
13734 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13735 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13736 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13737 MVT::v2f64, Load)),
13738 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13739 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13740 MVT::v2f64, Bias)));
13741 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13743 DAG.getIntPtrConstant(0));
13745 // Subtract the bias.
13746 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13748 // Handle final rounding.
13749 EVT DestVT = Op.getValueType();
13751 if (DestVT.bitsLT(MVT::f64))
13752 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13753 DAG.getIntPtrConstant(0));
13754 if (DestVT.bitsGT(MVT::f64))
13755 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13757 // Handle final rounding.
13761 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13762 const X86Subtarget &Subtarget) {
13763 // The algorithm is the following:
13764 // #ifdef __SSE4_1__
13765 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13766 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13767 // (uint4) 0x53000000, 0xaa);
13769 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13770 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13772 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13773 // return (float4) lo + fhi;
13776 SDValue V = Op->getOperand(0);
13777 EVT VecIntVT = V.getValueType();
13778 bool Is128 = VecIntVT == MVT::v4i32;
13779 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13780 // If we convert to something else than the supported type, e.g., to v4f64,
13782 if (VecFloatVT != Op->getValueType(0))
13785 unsigned NumElts = VecIntVT.getVectorNumElements();
13786 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13787 "Unsupported custom type");
13788 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13790 // In the #idef/#else code, we have in common:
13791 // - The vector of constants:
13797 // Create the splat vector for 0x4b000000.
13798 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13799 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13800 CstLow, CstLow, CstLow, CstLow};
13801 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13802 makeArrayRef(&CstLowArray[0], NumElts));
13803 // Create the splat vector for 0x53000000.
13804 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13805 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13806 CstHigh, CstHigh, CstHigh, CstHigh};
13807 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13808 makeArrayRef(&CstHighArray[0], NumElts));
13810 // Create the right shift.
13811 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13812 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13813 CstShift, CstShift, CstShift, CstShift};
13814 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13815 makeArrayRef(&CstShiftArray[0], NumElts));
13816 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13819 if (Subtarget.hasSSE41()) {
13820 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13821 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13822 SDValue VecCstLowBitcast =
13823 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13824 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13825 // Low will be bitcasted right away, so do not bother bitcasting back to its
13827 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13828 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13829 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13830 // (uint4) 0x53000000, 0xaa);
13831 SDValue VecCstHighBitcast =
13832 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13833 SDValue VecShiftBitcast =
13834 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13835 // High will be bitcasted right away, so do not bother bitcasting back to
13836 // its original type.
13837 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13838 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13840 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13841 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13842 CstMask, CstMask, CstMask);
13843 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13844 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13845 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13847 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13848 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13851 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13852 SDValue CstFAdd = DAG.getConstantFP(
13853 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13854 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13855 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13856 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13857 makeArrayRef(&CstFAddArray[0], NumElts));
13859 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13860 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13862 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13863 // return (float4) lo + fhi;
13864 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13865 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13868 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13869 SelectionDAG &DAG) const {
13870 SDValue N0 = Op.getOperand(0);
13871 MVT SVT = N0.getSimpleValueType();
13874 switch (SVT.SimpleTy) {
13876 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13881 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13882 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13883 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13887 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13889 llvm_unreachable(nullptr);
13892 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13893 SelectionDAG &DAG) const {
13894 SDValue N0 = Op.getOperand(0);
13897 if (Op.getValueType().isVector())
13898 return lowerUINT_TO_FP_vec(Op, DAG);
13900 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13901 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13902 // the optimization here.
13903 if (DAG.SignBitIsZero(N0))
13904 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13906 MVT SrcVT = N0.getSimpleValueType();
13907 MVT DstVT = Op.getSimpleValueType();
13908 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13909 return LowerUINT_TO_FP_i64(Op, DAG);
13910 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13911 return LowerUINT_TO_FP_i32(Op, DAG);
13912 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13915 // Make a 64-bit buffer, and use it to build an FILD.
13916 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13917 if (SrcVT == MVT::i32) {
13918 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13919 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13920 getPointerTy(), StackSlot, WordOff);
13921 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13922 StackSlot, MachinePointerInfo(),
13924 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13925 OffsetSlot, MachinePointerInfo(),
13927 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13931 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13932 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13933 StackSlot, MachinePointerInfo(),
13935 // For i64 source, we need to add the appropriate power of 2 if the input
13936 // was negative. This is the same as the optimization in
13937 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13938 // we must be careful to do the computation in x87 extended precision, not
13939 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13940 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13941 MachineMemOperand *MMO =
13942 DAG.getMachineFunction()
13943 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13944 MachineMemOperand::MOLoad, 8, 8);
13946 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13947 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13948 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13951 APInt FF(32, 0x5F800000ULL);
13953 // Check whether the sign bit is set.
13954 SDValue SignSet = DAG.getSetCC(dl,
13955 getSetCCResultType(*DAG.getContext(), MVT::i64),
13956 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13959 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13960 SDValue FudgePtr = DAG.getConstantPool(
13961 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13964 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13965 SDValue Zero = DAG.getIntPtrConstant(0);
13966 SDValue Four = DAG.getIntPtrConstant(4);
13967 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13969 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13971 // Load the value out, extending it from f32 to f80.
13972 // FIXME: Avoid the extend by constructing the right constant pool?
13973 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13974 FudgePtr, MachinePointerInfo::getConstantPool(),
13975 MVT::f32, false, false, false, 4);
13976 // Extend everything to 80 bits to force it to be done on x87.
13977 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13978 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13981 std::pair<SDValue,SDValue>
13982 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13983 bool IsSigned, bool IsReplace) const {
13986 EVT DstTy = Op.getValueType();
13988 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13989 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13993 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13994 DstTy.getSimpleVT() >= MVT::i16 &&
13995 "Unknown FP_TO_INT to lower!");
13997 // These are really Legal.
13998 if (DstTy == MVT::i32 &&
13999 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14000 return std::make_pair(SDValue(), SDValue());
14001 if (Subtarget->is64Bit() &&
14002 DstTy == MVT::i64 &&
14003 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14004 return std::make_pair(SDValue(), SDValue());
14006 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14007 // stack slot, or into the FTOL runtime function.
14008 MachineFunction &MF = DAG.getMachineFunction();
14009 unsigned MemSize = DstTy.getSizeInBits()/8;
14010 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14011 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14014 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14015 Opc = X86ISD::WIN_FTOL;
14017 switch (DstTy.getSimpleVT().SimpleTy) {
14018 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14019 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14020 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14021 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14024 SDValue Chain = DAG.getEntryNode();
14025 SDValue Value = Op.getOperand(0);
14026 EVT TheVT = Op.getOperand(0).getValueType();
14027 // FIXME This causes a redundant load/store if the SSE-class value is already
14028 // in memory, such as if it is on the callstack.
14029 if (isScalarFPTypeInSSEReg(TheVT)) {
14030 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14031 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14032 MachinePointerInfo::getFixedStack(SSFI),
14034 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14036 Chain, StackSlot, DAG.getValueType(TheVT)
14039 MachineMemOperand *MMO =
14040 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14041 MachineMemOperand::MOLoad, MemSize, MemSize);
14042 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14043 Chain = Value.getValue(1);
14044 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14045 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14048 MachineMemOperand *MMO =
14049 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14050 MachineMemOperand::MOStore, MemSize, MemSize);
14052 if (Opc != X86ISD::WIN_FTOL) {
14053 // Build the FP_TO_INT*_IN_MEM
14054 SDValue Ops[] = { Chain, Value, StackSlot };
14055 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14057 return std::make_pair(FIST, StackSlot);
14059 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14060 DAG.getVTList(MVT::Other, MVT::Glue),
14062 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14063 MVT::i32, ftol.getValue(1));
14064 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14065 MVT::i32, eax.getValue(2));
14066 SDValue Ops[] = { eax, edx };
14067 SDValue pair = IsReplace
14068 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14069 : DAG.getMergeValues(Ops, DL);
14070 return std::make_pair(pair, SDValue());
14074 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14075 const X86Subtarget *Subtarget) {
14076 MVT VT = Op->getSimpleValueType(0);
14077 SDValue In = Op->getOperand(0);
14078 MVT InVT = In.getSimpleValueType();
14081 // Optimize vectors in AVX mode:
14084 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14085 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14086 // Concat upper and lower parts.
14089 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14090 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14091 // Concat upper and lower parts.
14094 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14095 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14096 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14099 if (Subtarget->hasInt256())
14100 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14102 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14103 SDValue Undef = DAG.getUNDEF(InVT);
14104 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14105 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14106 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14108 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14109 VT.getVectorNumElements()/2);
14111 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14112 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14114 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14117 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14118 SelectionDAG &DAG) {
14119 MVT VT = Op->getSimpleValueType(0);
14120 SDValue In = Op->getOperand(0);
14121 MVT InVT = In.getSimpleValueType();
14123 unsigned int NumElts = VT.getVectorNumElements();
14124 if (NumElts != 8 && NumElts != 16)
14127 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14128 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14130 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14132 // Now we have only mask extension
14133 assert(InVT.getVectorElementType() == MVT::i1);
14134 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14135 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14136 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14137 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14138 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14139 MachinePointerInfo::getConstantPool(),
14140 false, false, false, Alignment);
14142 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14143 if (VT.is512BitVector())
14145 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14148 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14149 SelectionDAG &DAG) {
14150 if (Subtarget->hasFp256()) {
14151 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14159 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14160 SelectionDAG &DAG) {
14162 MVT VT = Op.getSimpleValueType();
14163 SDValue In = Op.getOperand(0);
14164 MVT SVT = In.getSimpleValueType();
14166 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14167 return LowerZERO_EXTEND_AVX512(Op, DAG);
14169 if (Subtarget->hasFp256()) {
14170 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14175 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14176 VT.getVectorNumElements() != SVT.getVectorNumElements());
14180 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14182 MVT VT = Op.getSimpleValueType();
14183 SDValue In = Op.getOperand(0);
14184 MVT InVT = In.getSimpleValueType();
14186 if (VT == MVT::i1) {
14187 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14188 "Invalid scalar TRUNCATE operation");
14189 if (InVT.getSizeInBits() >= 32)
14191 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14192 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14194 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14195 "Invalid TRUNCATE operation");
14197 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14198 if (VT.getVectorElementType().getSizeInBits() >=8)
14199 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14201 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14202 unsigned NumElts = InVT.getVectorNumElements();
14203 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14204 if (InVT.getSizeInBits() < 512) {
14205 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14206 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14210 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14211 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14212 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14213 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14214 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14215 MachinePointerInfo::getConstantPool(),
14216 false, false, false, Alignment);
14217 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14218 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14219 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14222 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14223 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14224 if (Subtarget->hasInt256()) {
14225 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14226 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14227 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14229 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14230 DAG.getIntPtrConstant(0));
14233 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14234 DAG.getIntPtrConstant(0));
14235 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14236 DAG.getIntPtrConstant(2));
14237 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14238 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14239 static const int ShufMask[] = {0, 2, 4, 6};
14240 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14243 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14244 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14245 if (Subtarget->hasInt256()) {
14246 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14248 SmallVector<SDValue,32> pshufbMask;
14249 for (unsigned i = 0; i < 2; ++i) {
14250 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14251 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14252 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14253 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14254 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14257 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14258 for (unsigned j = 0; j < 8; ++j)
14259 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14261 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14262 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14263 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14265 static const int ShufMask[] = {0, 2, -1, -1};
14266 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14268 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14269 DAG.getIntPtrConstant(0));
14270 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14273 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14274 DAG.getIntPtrConstant(0));
14276 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14277 DAG.getIntPtrConstant(4));
14279 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14280 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14282 // The PSHUFB mask:
14283 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14284 -1, -1, -1, -1, -1, -1, -1, -1};
14286 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14287 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14288 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14290 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14291 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14293 // The MOVLHPS Mask:
14294 static const int ShufMask2[] = {0, 1, 4, 5};
14295 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14296 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14299 // Handle truncation of V256 to V128 using shuffles.
14300 if (!VT.is128BitVector() || !InVT.is256BitVector())
14303 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14305 unsigned NumElems = VT.getVectorNumElements();
14306 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14308 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14309 // Prepare truncation shuffle mask
14310 for (unsigned i = 0; i != NumElems; ++i)
14311 MaskVec[i] = i * 2;
14312 SDValue V = DAG.getVectorShuffle(NVT, DL,
14313 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14314 DAG.getUNDEF(NVT), &MaskVec[0]);
14315 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14316 DAG.getIntPtrConstant(0));
14319 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14320 SelectionDAG &DAG) const {
14321 assert(!Op.getSimpleValueType().isVector());
14323 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14324 /*IsSigned=*/ true, /*IsReplace=*/ false);
14325 SDValue FIST = Vals.first, StackSlot = Vals.second;
14326 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14327 if (!FIST.getNode()) return Op;
14329 if (StackSlot.getNode())
14330 // Load the result.
14331 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14332 FIST, StackSlot, MachinePointerInfo(),
14333 false, false, false, 0);
14335 // The node is the result.
14339 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14340 SelectionDAG &DAG) const {
14341 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14342 /*IsSigned=*/ false, /*IsReplace=*/ false);
14343 SDValue FIST = Vals.first, StackSlot = Vals.second;
14344 assert(FIST.getNode() && "Unexpected failure");
14346 if (StackSlot.getNode())
14347 // Load the result.
14348 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14349 FIST, StackSlot, MachinePointerInfo(),
14350 false, false, false, 0);
14352 // The node is the result.
14356 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14358 MVT VT = Op.getSimpleValueType();
14359 SDValue In = Op.getOperand(0);
14360 MVT SVT = In.getSimpleValueType();
14362 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14364 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14365 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14366 In, DAG.getUNDEF(SVT)));
14369 /// The only differences between FABS and FNEG are the mask and the logic op.
14370 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14371 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14372 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14373 "Wrong opcode for lowering FABS or FNEG.");
14375 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14377 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14378 // into an FNABS. We'll lower the FABS after that if it is still in use.
14380 for (SDNode *User : Op->uses())
14381 if (User->getOpcode() == ISD::FNEG)
14384 SDValue Op0 = Op.getOperand(0);
14385 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14388 MVT VT = Op.getSimpleValueType();
14389 // Assume scalar op for initialization; update for vector if needed.
14390 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14391 // generate a 16-byte vector constant and logic op even for the scalar case.
14392 // Using a 16-byte mask allows folding the load of the mask with
14393 // the logic op, so it can save (~4 bytes) on code size.
14395 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14396 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14397 // decide if we should generate a 16-byte constant mask when we only need 4 or
14398 // 8 bytes for the scalar case.
14399 if (VT.isVector()) {
14400 EltVT = VT.getVectorElementType();
14401 NumElts = VT.getVectorNumElements();
14404 unsigned EltBits = EltVT.getSizeInBits();
14405 LLVMContext *Context = DAG.getContext();
14406 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14408 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14409 Constant *C = ConstantInt::get(*Context, MaskElt);
14410 C = ConstantVector::getSplat(NumElts, C);
14411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14412 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14413 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14414 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14415 MachinePointerInfo::getConstantPool(),
14416 false, false, false, Alignment);
14418 if (VT.isVector()) {
14419 // For a vector, cast operands to a vector type, perform the logic op,
14420 // and cast the result back to the original value type.
14421 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14422 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14423 SDValue Operand = IsFNABS ?
14424 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14425 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14426 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14427 return DAG.getNode(ISD::BITCAST, dl, VT,
14428 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14431 // If not vector, then scalar.
14432 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14433 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14434 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14437 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14439 LLVMContext *Context = DAG.getContext();
14440 SDValue Op0 = Op.getOperand(0);
14441 SDValue Op1 = Op.getOperand(1);
14443 MVT VT = Op.getSimpleValueType();
14444 MVT SrcVT = Op1.getSimpleValueType();
14446 // If second operand is smaller, extend it first.
14447 if (SrcVT.bitsLT(VT)) {
14448 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14451 // And if it is bigger, shrink it first.
14452 if (SrcVT.bitsGT(VT)) {
14453 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14457 // At this point the operands and the result should have the same
14458 // type, and that won't be f80 since that is not custom lowered.
14460 const fltSemantics &Sem =
14461 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14462 const unsigned SizeInBits = VT.getSizeInBits();
14464 SmallVector<Constant *, 4> CV(
14465 VT == MVT::f64 ? 2 : 4,
14466 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14468 // First, clear all bits but the sign bit from the second operand (sign).
14469 CV[0] = ConstantFP::get(*Context,
14470 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14471 Constant *C = ConstantVector::get(CV);
14472 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14473 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14474 MachinePointerInfo::getConstantPool(),
14475 false, false, false, 16);
14476 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14478 // Next, clear the sign bit from the first operand (magnitude).
14479 CV[0] = ConstantFP::get(
14480 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14481 C = ConstantVector::get(CV);
14482 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14483 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14484 MachinePointerInfo::getConstantPool(),
14485 false, false, false, 16);
14486 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14488 // OR the magnitude value with the sign bit.
14489 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14492 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14493 SDValue N0 = Op.getOperand(0);
14495 MVT VT = Op.getSimpleValueType();
14497 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14498 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14499 DAG.getConstant(1, VT));
14500 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14503 // Check whether an OR'd tree is PTEST-able.
14504 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14505 SelectionDAG &DAG) {
14506 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14508 if (!Subtarget->hasSSE41())
14511 if (!Op->hasOneUse())
14514 SDNode *N = Op.getNode();
14517 SmallVector<SDValue, 8> Opnds;
14518 DenseMap<SDValue, unsigned> VecInMap;
14519 SmallVector<SDValue, 8> VecIns;
14520 EVT VT = MVT::Other;
14522 // Recognize a special case where a vector is casted into wide integer to
14524 Opnds.push_back(N->getOperand(0));
14525 Opnds.push_back(N->getOperand(1));
14527 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14528 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14529 // BFS traverse all OR'd operands.
14530 if (I->getOpcode() == ISD::OR) {
14531 Opnds.push_back(I->getOperand(0));
14532 Opnds.push_back(I->getOperand(1));
14533 // Re-evaluate the number of nodes to be traversed.
14534 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14538 // Quit if a non-EXTRACT_VECTOR_ELT
14539 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14542 // Quit if without a constant index.
14543 SDValue Idx = I->getOperand(1);
14544 if (!isa<ConstantSDNode>(Idx))
14547 SDValue ExtractedFromVec = I->getOperand(0);
14548 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14549 if (M == VecInMap.end()) {
14550 VT = ExtractedFromVec.getValueType();
14551 // Quit if not 128/256-bit vector.
14552 if (!VT.is128BitVector() && !VT.is256BitVector())
14554 // Quit if not the same type.
14555 if (VecInMap.begin() != VecInMap.end() &&
14556 VT != VecInMap.begin()->first.getValueType())
14558 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14559 VecIns.push_back(ExtractedFromVec);
14561 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14564 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14565 "Not extracted from 128-/256-bit vector.");
14567 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14569 for (DenseMap<SDValue, unsigned>::const_iterator
14570 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14571 // Quit if not all elements are used.
14572 if (I->second != FullMask)
14576 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14578 // Cast all vectors into TestVT for PTEST.
14579 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14580 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14582 // If more than one full vectors are evaluated, OR them first before PTEST.
14583 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14584 // Each iteration will OR 2 nodes and append the result until there is only
14585 // 1 node left, i.e. the final OR'd value of all vectors.
14586 SDValue LHS = VecIns[Slot];
14587 SDValue RHS = VecIns[Slot + 1];
14588 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14591 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14592 VecIns.back(), VecIns.back());
14595 /// \brief return true if \c Op has a use that doesn't just read flags.
14596 static bool hasNonFlagsUse(SDValue Op) {
14597 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14599 SDNode *User = *UI;
14600 unsigned UOpNo = UI.getOperandNo();
14601 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14602 // Look pass truncate.
14603 UOpNo = User->use_begin().getOperandNo();
14604 User = *User->use_begin();
14607 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14608 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14614 /// Emit nodes that will be selected as "test Op0,Op0", or something
14616 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14617 SelectionDAG &DAG) const {
14618 if (Op.getValueType() == MVT::i1)
14619 // KORTEST instruction should be selected
14620 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14621 DAG.getConstant(0, Op.getValueType()));
14623 // CF and OF aren't always set the way we want. Determine which
14624 // of these we need.
14625 bool NeedCF = false;
14626 bool NeedOF = false;
14629 case X86::COND_A: case X86::COND_AE:
14630 case X86::COND_B: case X86::COND_BE:
14633 case X86::COND_G: case X86::COND_GE:
14634 case X86::COND_L: case X86::COND_LE:
14635 case X86::COND_O: case X86::COND_NO: {
14636 // Check if we really need to set the
14637 // Overflow flag. If NoSignedWrap is present
14638 // that is not actually needed.
14639 switch (Op->getOpcode()) {
14644 const BinaryWithFlagsSDNode *BinNode =
14645 cast<BinaryWithFlagsSDNode>(Op.getNode());
14646 if (BinNode->hasNoSignedWrap())
14656 // See if we can use the EFLAGS value from the operand instead of
14657 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14658 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14659 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14660 // Emit a CMP with 0, which is the TEST pattern.
14661 //if (Op.getValueType() == MVT::i1)
14662 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14663 // DAG.getConstant(0, MVT::i1));
14664 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14665 DAG.getConstant(0, Op.getValueType()));
14667 unsigned Opcode = 0;
14668 unsigned NumOperands = 0;
14670 // Truncate operations may prevent the merge of the SETCC instruction
14671 // and the arithmetic instruction before it. Attempt to truncate the operands
14672 // of the arithmetic instruction and use a reduced bit-width instruction.
14673 bool NeedTruncation = false;
14674 SDValue ArithOp = Op;
14675 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14676 SDValue Arith = Op->getOperand(0);
14677 // Both the trunc and the arithmetic op need to have one user each.
14678 if (Arith->hasOneUse())
14679 switch (Arith.getOpcode()) {
14686 NeedTruncation = true;
14692 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14693 // which may be the result of a CAST. We use the variable 'Op', which is the
14694 // non-casted variable when we check for possible users.
14695 switch (ArithOp.getOpcode()) {
14697 // Due to an isel shortcoming, be conservative if this add is likely to be
14698 // selected as part of a load-modify-store instruction. When the root node
14699 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14700 // uses of other nodes in the match, such as the ADD in this case. This
14701 // leads to the ADD being left around and reselected, with the result being
14702 // two adds in the output. Alas, even if none our users are stores, that
14703 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14704 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14705 // climbing the DAG back to the root, and it doesn't seem to be worth the
14707 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14708 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14709 if (UI->getOpcode() != ISD::CopyToReg &&
14710 UI->getOpcode() != ISD::SETCC &&
14711 UI->getOpcode() != ISD::STORE)
14714 if (ConstantSDNode *C =
14715 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14716 // An add of one will be selected as an INC.
14717 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14718 Opcode = X86ISD::INC;
14723 // An add of negative one (subtract of one) will be selected as a DEC.
14724 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14725 Opcode = X86ISD::DEC;
14731 // Otherwise use a regular EFLAGS-setting add.
14732 Opcode = X86ISD::ADD;
14737 // If we have a constant logical shift that's only used in a comparison
14738 // against zero turn it into an equivalent AND. This allows turning it into
14739 // a TEST instruction later.
14740 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14741 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14742 EVT VT = Op.getValueType();
14743 unsigned BitWidth = VT.getSizeInBits();
14744 unsigned ShAmt = Op->getConstantOperandVal(1);
14745 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14747 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14748 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14749 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14750 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14752 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14753 DAG.getConstant(Mask, VT));
14754 DAG.ReplaceAllUsesWith(Op, New);
14760 // If the primary and result isn't used, don't bother using X86ISD::AND,
14761 // because a TEST instruction will be better.
14762 if (!hasNonFlagsUse(Op))
14768 // Due to the ISEL shortcoming noted above, be conservative if this op is
14769 // likely to be selected as part of a load-modify-store instruction.
14770 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14771 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14772 if (UI->getOpcode() == ISD::STORE)
14775 // Otherwise use a regular EFLAGS-setting instruction.
14776 switch (ArithOp.getOpcode()) {
14777 default: llvm_unreachable("unexpected operator!");
14778 case ISD::SUB: Opcode = X86ISD::SUB; break;
14779 case ISD::XOR: Opcode = X86ISD::XOR; break;
14780 case ISD::AND: Opcode = X86ISD::AND; break;
14782 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14783 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14784 if (EFLAGS.getNode())
14787 Opcode = X86ISD::OR;
14801 return SDValue(Op.getNode(), 1);
14807 // If we found that truncation is beneficial, perform the truncation and
14809 if (NeedTruncation) {
14810 EVT VT = Op.getValueType();
14811 SDValue WideVal = Op->getOperand(0);
14812 EVT WideVT = WideVal.getValueType();
14813 unsigned ConvertedOp = 0;
14814 // Use a target machine opcode to prevent further DAGCombine
14815 // optimizations that may separate the arithmetic operations
14816 // from the setcc node.
14817 switch (WideVal.getOpcode()) {
14819 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14820 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14821 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14822 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14823 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14828 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14829 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14830 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14831 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14837 // Emit a CMP with 0, which is the TEST pattern.
14838 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14839 DAG.getConstant(0, Op.getValueType()));
14841 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14842 SmallVector<SDValue, 4> Ops;
14843 for (unsigned i = 0; i != NumOperands; ++i)
14844 Ops.push_back(Op.getOperand(i));
14846 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14847 DAG.ReplaceAllUsesWith(Op, New);
14848 return SDValue(New.getNode(), 1);
14851 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14853 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14854 SDLoc dl, SelectionDAG &DAG) const {
14855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14856 if (C->getAPIntValue() == 0)
14857 return EmitTest(Op0, X86CC, dl, DAG);
14859 if (Op0.getValueType() == MVT::i1)
14860 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14863 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14864 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14865 // Do the comparison at i32 if it's smaller, besides the Atom case.
14866 // This avoids subregister aliasing issues. Keep the smaller reference
14867 // if we're optimizing for size, however, as that'll allow better folding
14868 // of memory operations.
14869 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14870 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14871 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14872 !Subtarget->isAtom()) {
14873 unsigned ExtendOp =
14874 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14875 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14876 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14878 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14879 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14880 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14882 return SDValue(Sub.getNode(), 1);
14884 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14887 /// Convert a comparison if required by the subtarget.
14888 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14889 SelectionDAG &DAG) const {
14890 // If the subtarget does not support the FUCOMI instruction, floating-point
14891 // comparisons have to be converted.
14892 if (Subtarget->hasCMov() ||
14893 Cmp.getOpcode() != X86ISD::CMP ||
14894 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14895 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14898 // The instruction selector will select an FUCOM instruction instead of
14899 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14900 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14901 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14903 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14904 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14905 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14906 DAG.getConstant(8, MVT::i8));
14907 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14908 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14911 /// The minimum architected relative accuracy is 2^-12. We need one
14912 /// Newton-Raphson step to have a good float result (24 bits of precision).
14913 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14914 DAGCombinerInfo &DCI,
14915 unsigned &RefinementSteps,
14916 bool &UseOneConstNR) const {
14917 // FIXME: We should use instruction latency models to calculate the cost of
14918 // each potential sequence, but this is very hard to do reliably because
14919 // at least Intel's Core* chips have variable timing based on the number of
14920 // significant digits in the divisor and/or sqrt operand.
14921 if (!Subtarget->useSqrtEst())
14924 EVT VT = Op.getValueType();
14926 // SSE1 has rsqrtss and rsqrtps.
14927 // TODO: Add support for AVX512 (v16f32).
14928 // It is likely not profitable to do this for f64 because a double-precision
14929 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14930 // instructions: convert to single, rsqrtss, convert back to double, refine
14931 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14932 // along with FMA, this could be a throughput win.
14933 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14934 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14935 RefinementSteps = 1;
14936 UseOneConstNR = false;
14937 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14942 /// The minimum architected relative accuracy is 2^-12. We need one
14943 /// Newton-Raphson step to have a good float result (24 bits of precision).
14944 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14945 DAGCombinerInfo &DCI,
14946 unsigned &RefinementSteps) const {
14947 // FIXME: We should use instruction latency models to calculate the cost of
14948 // each potential sequence, but this is very hard to do reliably because
14949 // at least Intel's Core* chips have variable timing based on the number of
14950 // significant digits in the divisor.
14951 if (!Subtarget->useReciprocalEst())
14954 EVT VT = Op.getValueType();
14956 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14957 // TODO: Add support for AVX512 (v16f32).
14958 // It is likely not profitable to do this for f64 because a double-precision
14959 // reciprocal estimate with refinement on x86 prior to FMA requires
14960 // 15 instructions: convert to single, rcpss, convert back to double, refine
14961 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14962 // along with FMA, this could be a throughput win.
14963 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14964 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14965 RefinementSteps = ReciprocalEstimateRefinementSteps;
14966 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14971 static bool isAllOnes(SDValue V) {
14972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14973 return C && C->isAllOnesValue();
14976 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14977 /// if it's possible.
14978 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14979 SDLoc dl, SelectionDAG &DAG) const {
14980 SDValue Op0 = And.getOperand(0);
14981 SDValue Op1 = And.getOperand(1);
14982 if (Op0.getOpcode() == ISD::TRUNCATE)
14983 Op0 = Op0.getOperand(0);
14984 if (Op1.getOpcode() == ISD::TRUNCATE)
14985 Op1 = Op1.getOperand(0);
14988 if (Op1.getOpcode() == ISD::SHL)
14989 std::swap(Op0, Op1);
14990 if (Op0.getOpcode() == ISD::SHL) {
14991 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14992 if (And00C->getZExtValue() == 1) {
14993 // If we looked past a truncate, check that it's only truncating away
14995 unsigned BitWidth = Op0.getValueSizeInBits();
14996 unsigned AndBitWidth = And.getValueSizeInBits();
14997 if (BitWidth > AndBitWidth) {
14999 DAG.computeKnownBits(Op0, Zeros, Ones);
15000 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15004 RHS = Op0.getOperand(1);
15006 } else if (Op1.getOpcode() == ISD::Constant) {
15007 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15008 uint64_t AndRHSVal = AndRHS->getZExtValue();
15009 SDValue AndLHS = Op0;
15011 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15012 LHS = AndLHS.getOperand(0);
15013 RHS = AndLHS.getOperand(1);
15016 // Use BT if the immediate can't be encoded in a TEST instruction.
15017 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15019 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15023 if (LHS.getNode()) {
15024 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15025 // instruction. Since the shift amount is in-range-or-undefined, we know
15026 // that doing a bittest on the i32 value is ok. We extend to i32 because
15027 // the encoding for the i16 version is larger than the i32 version.
15028 // Also promote i16 to i32 for performance / code size reason.
15029 if (LHS.getValueType() == MVT::i8 ||
15030 LHS.getValueType() == MVT::i16)
15031 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15033 // If the operand types disagree, extend the shift amount to match. Since
15034 // BT ignores high bits (like shifts) we can use anyextend.
15035 if (LHS.getValueType() != RHS.getValueType())
15036 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15038 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15039 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15040 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15041 DAG.getConstant(Cond, MVT::i8), BT);
15047 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15049 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15054 // SSE Condition code mapping:
15063 switch (SetCCOpcode) {
15064 default: llvm_unreachable("Unexpected SETCC condition");
15066 case ISD::SETEQ: SSECC = 0; break;
15068 case ISD::SETGT: Swap = true; // Fallthrough
15070 case ISD::SETOLT: SSECC = 1; break;
15072 case ISD::SETGE: Swap = true; // Fallthrough
15074 case ISD::SETOLE: SSECC = 2; break;
15075 case ISD::SETUO: SSECC = 3; break;
15077 case ISD::SETNE: SSECC = 4; break;
15078 case ISD::SETULE: Swap = true; // Fallthrough
15079 case ISD::SETUGE: SSECC = 5; break;
15080 case ISD::SETULT: Swap = true; // Fallthrough
15081 case ISD::SETUGT: SSECC = 6; break;
15082 case ISD::SETO: SSECC = 7; break;
15084 case ISD::SETONE: SSECC = 8; break;
15087 std::swap(Op0, Op1);
15092 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15093 // ones, and then concatenate the result back.
15094 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15095 MVT VT = Op.getSimpleValueType();
15097 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15098 "Unsupported value type for operation");
15100 unsigned NumElems = VT.getVectorNumElements();
15102 SDValue CC = Op.getOperand(2);
15104 // Extract the LHS vectors
15105 SDValue LHS = Op.getOperand(0);
15106 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15107 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15109 // Extract the RHS vectors
15110 SDValue RHS = Op.getOperand(1);
15111 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15112 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15114 // Issue the operation on the smaller types and concatenate the result back
15115 MVT EltVT = VT.getVectorElementType();
15116 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15117 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15118 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15119 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15122 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15123 const X86Subtarget *Subtarget) {
15124 SDValue Op0 = Op.getOperand(0);
15125 SDValue Op1 = Op.getOperand(1);
15126 SDValue CC = Op.getOperand(2);
15127 MVT VT = Op.getSimpleValueType();
15130 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15131 Op.getValueType().getScalarType() == MVT::i1 &&
15132 "Cannot set masked compare for this operation");
15134 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15136 bool Unsigned = false;
15139 switch (SetCCOpcode) {
15140 default: llvm_unreachable("Unexpected SETCC condition");
15141 case ISD::SETNE: SSECC = 4; break;
15142 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15143 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15144 case ISD::SETLT: Swap = true; //fall-through
15145 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15146 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15147 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15148 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15149 case ISD::SETULE: Unsigned = true; //fall-through
15150 case ISD::SETLE: SSECC = 2; break;
15154 std::swap(Op0, Op1);
15156 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15157 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15158 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15159 DAG.getConstant(SSECC, MVT::i8));
15162 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15163 /// operand \p Op1. If non-trivial (for example because it's not constant)
15164 /// return an empty value.
15165 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15167 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15171 MVT VT = Op1.getSimpleValueType();
15172 MVT EVT = VT.getVectorElementType();
15173 unsigned n = VT.getVectorNumElements();
15174 SmallVector<SDValue, 8> ULTOp1;
15176 for (unsigned i = 0; i < n; ++i) {
15177 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15178 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15181 // Avoid underflow.
15182 APInt Val = Elt->getAPIntValue();
15186 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15189 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15192 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15193 SelectionDAG &DAG) {
15194 SDValue Op0 = Op.getOperand(0);
15195 SDValue Op1 = Op.getOperand(1);
15196 SDValue CC = Op.getOperand(2);
15197 MVT VT = Op.getSimpleValueType();
15198 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15199 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15204 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15205 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15208 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15209 unsigned Opc = X86ISD::CMPP;
15210 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15211 assert(VT.getVectorNumElements() <= 16);
15212 Opc = X86ISD::CMPM;
15214 // In the two special cases we can't handle, emit two comparisons.
15217 unsigned CombineOpc;
15218 if (SetCCOpcode == ISD::SETUEQ) {
15219 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15221 assert(SetCCOpcode == ISD::SETONE);
15222 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15225 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15226 DAG.getConstant(CC0, MVT::i8));
15227 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15228 DAG.getConstant(CC1, MVT::i8));
15229 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15231 // Handle all other FP comparisons here.
15232 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15233 DAG.getConstant(SSECC, MVT::i8));
15236 // Break 256-bit integer vector compare into smaller ones.
15237 if (VT.is256BitVector() && !Subtarget->hasInt256())
15238 return Lower256IntVSETCC(Op, DAG);
15240 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15241 EVT OpVT = Op1.getValueType();
15242 if (Subtarget->hasAVX512()) {
15243 if (Op1.getValueType().is512BitVector() ||
15244 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15245 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15246 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15248 // In AVX-512 architecture setcc returns mask with i1 elements,
15249 // But there is no compare instruction for i8 and i16 elements in KNL.
15250 // We are not talking about 512-bit operands in this case, these
15251 // types are illegal.
15253 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15254 OpVT.getVectorElementType().getSizeInBits() >= 8))
15255 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15256 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15259 // We are handling one of the integer comparisons here. Since SSE only has
15260 // GT and EQ comparisons for integer, swapping operands and multiple
15261 // operations may be required for some comparisons.
15263 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15264 bool Subus = false;
15266 switch (SetCCOpcode) {
15267 default: llvm_unreachable("Unexpected SETCC condition");
15268 case ISD::SETNE: Invert = true;
15269 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15270 case ISD::SETLT: Swap = true;
15271 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15272 case ISD::SETGE: Swap = true;
15273 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15274 Invert = true; break;
15275 case ISD::SETULT: Swap = true;
15276 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15277 FlipSigns = true; break;
15278 case ISD::SETUGE: Swap = true;
15279 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15280 FlipSigns = true; Invert = true; break;
15283 // Special case: Use min/max operations for SETULE/SETUGE
15284 MVT VET = VT.getVectorElementType();
15286 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15287 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15290 switch (SetCCOpcode) {
15292 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15293 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15296 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15299 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15300 if (!MinMax && hasSubus) {
15301 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15303 // t = psubus Op0, Op1
15304 // pcmpeq t, <0..0>
15305 switch (SetCCOpcode) {
15307 case ISD::SETULT: {
15308 // If the comparison is against a constant we can turn this into a
15309 // setule. With psubus, setule does not require a swap. This is
15310 // beneficial because the constant in the register is no longer
15311 // destructed as the destination so it can be hoisted out of a loop.
15312 // Only do this pre-AVX since vpcmp* is no longer destructive.
15313 if (Subtarget->hasAVX())
15315 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15316 if (ULEOp1.getNode()) {
15318 Subus = true; Invert = false; Swap = false;
15322 // Psubus is better than flip-sign because it requires no inversion.
15323 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15324 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15328 Opc = X86ISD::SUBUS;
15334 std::swap(Op0, Op1);
15336 // Check that the operation in question is available (most are plain SSE2,
15337 // but PCMPGTQ and PCMPEQQ have different requirements).
15338 if (VT == MVT::v2i64) {
15339 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15340 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15342 // First cast everything to the right type.
15343 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15344 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15346 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15347 // bits of the inputs before performing those operations. The lower
15348 // compare is always unsigned.
15351 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15353 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15354 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15355 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15356 Sign, Zero, Sign, Zero);
15358 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15359 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15361 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15362 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15363 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15365 // Create masks for only the low parts/high parts of the 64 bit integers.
15366 static const int MaskHi[] = { 1, 1, 3, 3 };
15367 static const int MaskLo[] = { 0, 0, 2, 2 };
15368 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15369 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15370 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15372 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15373 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15376 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15378 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15381 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15382 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15383 // pcmpeqd + pshufd + pand.
15384 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15386 // First cast everything to the right type.
15387 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15388 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15391 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15393 // Make sure the lower and upper halves are both all-ones.
15394 static const int Mask[] = { 1, 0, 3, 2 };
15395 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15396 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15399 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15401 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15405 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15406 // bits of the inputs before performing those operations.
15408 EVT EltVT = VT.getVectorElementType();
15409 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15410 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15411 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15414 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15416 // If the logical-not of the result is required, perform that now.
15418 Result = DAG.getNOT(dl, Result, VT);
15421 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15424 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15425 getZeroVector(VT, Subtarget, DAG, dl));
15430 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15432 MVT VT = Op.getSimpleValueType();
15434 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15436 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15437 && "SetCC type must be 8-bit or 1-bit integer");
15438 SDValue Op0 = Op.getOperand(0);
15439 SDValue Op1 = Op.getOperand(1);
15441 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15443 // Optimize to BT if possible.
15444 // Lower (X & (1 << N)) == 0 to BT(X, N).
15445 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15446 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15447 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15448 Op1.getOpcode() == ISD::Constant &&
15449 cast<ConstantSDNode>(Op1)->isNullValue() &&
15450 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15451 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15452 if (NewSetCC.getNode()) {
15454 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15459 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15461 if (Op1.getOpcode() == ISD::Constant &&
15462 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15463 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15464 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15466 // If the input is a setcc, then reuse the input setcc or use a new one with
15467 // the inverted condition.
15468 if (Op0.getOpcode() == X86ISD::SETCC) {
15469 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15470 bool Invert = (CC == ISD::SETNE) ^
15471 cast<ConstantSDNode>(Op1)->isNullValue();
15475 CCode = X86::GetOppositeBranchCondition(CCode);
15476 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15477 DAG.getConstant(CCode, MVT::i8),
15478 Op0.getOperand(1));
15480 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15484 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15485 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15486 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15488 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15489 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15492 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15493 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15494 if (X86CC == X86::COND_INVALID)
15497 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15498 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15499 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15500 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15502 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15506 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15507 static bool isX86LogicalCmp(SDValue Op) {
15508 unsigned Opc = Op.getNode()->getOpcode();
15509 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15510 Opc == X86ISD::SAHF)
15512 if (Op.getResNo() == 1 &&
15513 (Opc == X86ISD::ADD ||
15514 Opc == X86ISD::SUB ||
15515 Opc == X86ISD::ADC ||
15516 Opc == X86ISD::SBB ||
15517 Opc == X86ISD::SMUL ||
15518 Opc == X86ISD::UMUL ||
15519 Opc == X86ISD::INC ||
15520 Opc == X86ISD::DEC ||
15521 Opc == X86ISD::OR ||
15522 Opc == X86ISD::XOR ||
15523 Opc == X86ISD::AND))
15526 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15532 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15533 if (V.getOpcode() != ISD::TRUNCATE)
15536 SDValue VOp0 = V.getOperand(0);
15537 unsigned InBits = VOp0.getValueSizeInBits();
15538 unsigned Bits = V.getValueSizeInBits();
15539 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15542 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15543 bool addTest = true;
15544 SDValue Cond = Op.getOperand(0);
15545 SDValue Op1 = Op.getOperand(1);
15546 SDValue Op2 = Op.getOperand(2);
15548 EVT VT = Op1.getValueType();
15551 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15552 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15553 // sequence later on.
15554 if (Cond.getOpcode() == ISD::SETCC &&
15555 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15556 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15557 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15558 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15559 int SSECC = translateX86FSETCC(
15560 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15563 if (Subtarget->hasAVX512()) {
15564 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15565 DAG.getConstant(SSECC, MVT::i8));
15566 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15568 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15569 DAG.getConstant(SSECC, MVT::i8));
15570 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15571 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15572 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15576 if (Cond.getOpcode() == ISD::SETCC) {
15577 SDValue NewCond = LowerSETCC(Cond, DAG);
15578 if (NewCond.getNode())
15582 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15583 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15584 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15585 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15586 if (Cond.getOpcode() == X86ISD::SETCC &&
15587 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15588 isZero(Cond.getOperand(1).getOperand(1))) {
15589 SDValue Cmp = Cond.getOperand(1);
15591 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15593 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15594 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15595 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15597 SDValue CmpOp0 = Cmp.getOperand(0);
15598 // Apply further optimizations for special cases
15599 // (select (x != 0), -1, 0) -> neg & sbb
15600 // (select (x == 0), 0, -1) -> neg & sbb
15601 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15602 if (YC->isNullValue() &&
15603 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15604 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15605 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15606 DAG.getConstant(0, CmpOp0.getValueType()),
15608 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15609 DAG.getConstant(X86::COND_B, MVT::i8),
15610 SDValue(Neg.getNode(), 1));
15614 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15615 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15616 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15618 SDValue Res = // Res = 0 or -1.
15619 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15620 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15622 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15623 Res = DAG.getNOT(DL, Res, Res.getValueType());
15625 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15626 if (!N2C || !N2C->isNullValue())
15627 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15632 // Look past (and (setcc_carry (cmp ...)), 1).
15633 if (Cond.getOpcode() == ISD::AND &&
15634 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15635 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15636 if (C && C->getAPIntValue() == 1)
15637 Cond = Cond.getOperand(0);
15640 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15641 // setting operand in place of the X86ISD::SETCC.
15642 unsigned CondOpcode = Cond.getOpcode();
15643 if (CondOpcode == X86ISD::SETCC ||
15644 CondOpcode == X86ISD::SETCC_CARRY) {
15645 CC = Cond.getOperand(0);
15647 SDValue Cmp = Cond.getOperand(1);
15648 unsigned Opc = Cmp.getOpcode();
15649 MVT VT = Op.getSimpleValueType();
15651 bool IllegalFPCMov = false;
15652 if (VT.isFloatingPoint() && !VT.isVector() &&
15653 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15654 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15656 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15657 Opc == X86ISD::BT) { // FIXME
15661 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15662 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15663 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15664 Cond.getOperand(0).getValueType() != MVT::i8)) {
15665 SDValue LHS = Cond.getOperand(0);
15666 SDValue RHS = Cond.getOperand(1);
15667 unsigned X86Opcode;
15670 switch (CondOpcode) {
15671 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15672 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15673 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15674 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15675 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15676 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15677 default: llvm_unreachable("unexpected overflowing operator");
15679 if (CondOpcode == ISD::UMULO)
15680 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15683 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15685 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15687 if (CondOpcode == ISD::UMULO)
15688 Cond = X86Op.getValue(2);
15690 Cond = X86Op.getValue(1);
15692 CC = DAG.getConstant(X86Cond, MVT::i8);
15697 // Look pass the truncate if the high bits are known zero.
15698 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15699 Cond = Cond.getOperand(0);
15701 // We know the result of AND is compared against zero. Try to match
15703 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15704 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15705 if (NewSetCC.getNode()) {
15706 CC = NewSetCC.getOperand(0);
15707 Cond = NewSetCC.getOperand(1);
15714 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15715 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15718 // a < b ? -1 : 0 -> RES = ~setcc_carry
15719 // a < b ? 0 : -1 -> RES = setcc_carry
15720 // a >= b ? -1 : 0 -> RES = setcc_carry
15721 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15722 if (Cond.getOpcode() == X86ISD::SUB) {
15723 Cond = ConvertCmpIfNecessary(Cond, DAG);
15724 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15726 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15727 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15728 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15729 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15730 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15731 return DAG.getNOT(DL, Res, Res.getValueType());
15736 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15737 // widen the cmov and push the truncate through. This avoids introducing a new
15738 // branch during isel and doesn't add any extensions.
15739 if (Op.getValueType() == MVT::i8 &&
15740 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15741 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15742 if (T1.getValueType() == T2.getValueType() &&
15743 // Blacklist CopyFromReg to avoid partial register stalls.
15744 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15745 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15746 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15747 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15751 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15752 // condition is true.
15753 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15754 SDValue Ops[] = { Op2, Op1, CC, Cond };
15755 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15758 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15759 SelectionDAG &DAG) {
15760 MVT VT = Op->getSimpleValueType(0);
15761 SDValue In = Op->getOperand(0);
15762 MVT InVT = In.getSimpleValueType();
15763 MVT VTElt = VT.getVectorElementType();
15764 MVT InVTElt = InVT.getVectorElementType();
15768 if ((InVTElt == MVT::i1) &&
15769 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15770 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15772 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15773 VTElt.getSizeInBits() <= 16)) ||
15775 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15776 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15778 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15779 VTElt.getSizeInBits() >= 32))))
15780 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15782 unsigned int NumElts = VT.getVectorNumElements();
15784 if (NumElts != 8 && NumElts != 16)
15787 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15788 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15789 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15790 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15794 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15796 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15797 Constant *C = ConstantInt::get(*DAG.getContext(),
15798 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15800 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15801 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15802 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15803 MachinePointerInfo::getConstantPool(),
15804 false, false, false, Alignment);
15805 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15806 if (VT.is512BitVector())
15808 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15811 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15812 SelectionDAG &DAG) {
15813 MVT VT = Op->getSimpleValueType(0);
15814 SDValue In = Op->getOperand(0);
15815 MVT InVT = In.getSimpleValueType();
15818 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15819 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15821 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15822 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15823 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15826 if (Subtarget->hasInt256())
15827 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15829 // Optimize vectors in AVX mode
15830 // Sign extend v8i16 to v8i32 and
15833 // Divide input vector into two parts
15834 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15835 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15836 // concat the vectors to original VT
15838 unsigned NumElems = InVT.getVectorNumElements();
15839 SDValue Undef = DAG.getUNDEF(InVT);
15841 SmallVector<int,8> ShufMask1(NumElems, -1);
15842 for (unsigned i = 0; i != NumElems/2; ++i)
15845 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15847 SmallVector<int,8> ShufMask2(NumElems, -1);
15848 for (unsigned i = 0; i != NumElems/2; ++i)
15849 ShufMask2[i] = i + NumElems/2;
15851 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15853 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15854 VT.getVectorNumElements()/2);
15856 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15857 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15859 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15862 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15863 // may emit an illegal shuffle but the expansion is still better than scalar
15864 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15865 // we'll emit a shuffle and a arithmetic shift.
15866 // TODO: It is possible to support ZExt by zeroing the undef values during
15867 // the shuffle phase or after the shuffle.
15868 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15869 SelectionDAG &DAG) {
15870 MVT RegVT = Op.getSimpleValueType();
15871 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15872 assert(RegVT.isInteger() &&
15873 "We only custom lower integer vector sext loads.");
15875 // Nothing useful we can do without SSE2 shuffles.
15876 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15878 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15880 EVT MemVT = Ld->getMemoryVT();
15881 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15882 unsigned RegSz = RegVT.getSizeInBits();
15884 ISD::LoadExtType Ext = Ld->getExtensionType();
15886 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15887 && "Only anyext and sext are currently implemented.");
15888 assert(MemVT != RegVT && "Cannot extend to the same type");
15889 assert(MemVT.isVector() && "Must load a vector from memory");
15891 unsigned NumElems = RegVT.getVectorNumElements();
15892 unsigned MemSz = MemVT.getSizeInBits();
15893 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15895 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15896 // The only way in which we have a legal 256-bit vector result but not the
15897 // integer 256-bit operations needed to directly lower a sextload is if we
15898 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15899 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15900 // correctly legalized. We do this late to allow the canonical form of
15901 // sextload to persist throughout the rest of the DAG combiner -- it wants
15902 // to fold together any extensions it can, and so will fuse a sign_extend
15903 // of an sextload into a sextload targeting a wider value.
15905 if (MemSz == 128) {
15906 // Just switch this to a normal load.
15907 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15908 "it must be a legal 128-bit vector "
15910 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15911 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15912 Ld->isInvariant(), Ld->getAlignment());
15914 assert(MemSz < 128 &&
15915 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15916 // Do an sext load to a 128-bit vector type. We want to use the same
15917 // number of elements, but elements half as wide. This will end up being
15918 // recursively lowered by this routine, but will succeed as we definitely
15919 // have all the necessary features if we're using AVX1.
15921 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15922 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15924 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15925 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15926 Ld->isNonTemporal(), Ld->isInvariant(),
15927 Ld->getAlignment());
15930 // Replace chain users with the new chain.
15931 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15932 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15934 // Finally, do a normal sign-extend to the desired register.
15935 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15938 // All sizes must be a power of two.
15939 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15940 "Non-power-of-two elements are not custom lowered!");
15942 // Attempt to load the original value using scalar loads.
15943 // Find the largest scalar type that divides the total loaded size.
15944 MVT SclrLoadTy = MVT::i8;
15945 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15946 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15947 MVT Tp = (MVT::SimpleValueType)tp;
15948 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15953 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15954 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15956 SclrLoadTy = MVT::f64;
15958 // Calculate the number of scalar loads that we need to perform
15959 // in order to load our vector from memory.
15960 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15962 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15963 "Can only lower sext loads with a single scalar load!");
15965 unsigned loadRegZize = RegSz;
15966 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15969 // Represent our vector as a sequence of elements which are the
15970 // largest scalar that we can load.
15971 EVT LoadUnitVecVT = EVT::getVectorVT(
15972 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15974 // Represent the data using the same element type that is stored in
15975 // memory. In practice, we ''widen'' MemVT.
15977 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15978 loadRegZize / MemVT.getScalarType().getSizeInBits());
15980 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15981 "Invalid vector type");
15983 // We can't shuffle using an illegal type.
15984 assert(TLI.isTypeLegal(WideVecVT) &&
15985 "We only lower types that form legal widened vector types");
15987 SmallVector<SDValue, 8> Chains;
15988 SDValue Ptr = Ld->getBasePtr();
15989 SDValue Increment =
15990 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15991 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15993 for (unsigned i = 0; i < NumLoads; ++i) {
15994 // Perform a single load.
15995 SDValue ScalarLoad =
15996 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15997 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15998 Ld->getAlignment());
15999 Chains.push_back(ScalarLoad.getValue(1));
16000 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16001 // another round of DAGCombining.
16003 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16005 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16006 ScalarLoad, DAG.getIntPtrConstant(i));
16008 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16011 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16013 // Bitcast the loaded value to a vector of the original element type, in
16014 // the size of the target vector type.
16015 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16016 unsigned SizeRatio = RegSz / MemSz;
16018 if (Ext == ISD::SEXTLOAD) {
16019 // If we have SSE4.1, we can directly emit a VSEXT node.
16020 if (Subtarget->hasSSE41()) {
16021 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16022 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16026 // Otherwise we'll shuffle the small elements in the high bits of the
16027 // larger type and perform an arithmetic shift. If the shift is not legal
16028 // it's better to scalarize.
16029 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16030 "We can't implement a sext load without an arithmetic right shift!");
16032 // Redistribute the loaded elements into the different locations.
16033 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16034 for (unsigned i = 0; i != NumElems; ++i)
16035 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16037 SDValue Shuff = DAG.getVectorShuffle(
16038 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16040 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16042 // Build the arithmetic shift.
16043 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16044 MemVT.getVectorElementType().getSizeInBits();
16046 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16048 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16052 // Redistribute the loaded elements into the different locations.
16053 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16054 for (unsigned i = 0; i != NumElems; ++i)
16055 ShuffleVec[i * SizeRatio] = i;
16057 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16058 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16060 // Bitcast to the requested type.
16061 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16062 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16066 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16067 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16068 // from the AND / OR.
16069 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16070 Opc = Op.getOpcode();
16071 if (Opc != ISD::OR && Opc != ISD::AND)
16073 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16074 Op.getOperand(0).hasOneUse() &&
16075 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16076 Op.getOperand(1).hasOneUse());
16079 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16080 // 1 and that the SETCC node has a single use.
16081 static bool isXor1OfSetCC(SDValue Op) {
16082 if (Op.getOpcode() != ISD::XOR)
16084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16085 if (N1C && N1C->getAPIntValue() == 1) {
16086 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16087 Op.getOperand(0).hasOneUse();
16092 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16093 bool addTest = true;
16094 SDValue Chain = Op.getOperand(0);
16095 SDValue Cond = Op.getOperand(1);
16096 SDValue Dest = Op.getOperand(2);
16099 bool Inverted = false;
16101 if (Cond.getOpcode() == ISD::SETCC) {
16102 // Check for setcc([su]{add,sub,mul}o == 0).
16103 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16104 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16105 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16106 Cond.getOperand(0).getResNo() == 1 &&
16107 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16108 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16109 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16110 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16111 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16112 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16114 Cond = Cond.getOperand(0);
16116 SDValue NewCond = LowerSETCC(Cond, DAG);
16117 if (NewCond.getNode())
16122 // FIXME: LowerXALUO doesn't handle these!!
16123 else if (Cond.getOpcode() == X86ISD::ADD ||
16124 Cond.getOpcode() == X86ISD::SUB ||
16125 Cond.getOpcode() == X86ISD::SMUL ||
16126 Cond.getOpcode() == X86ISD::UMUL)
16127 Cond = LowerXALUO(Cond, DAG);
16130 // Look pass (and (setcc_carry (cmp ...)), 1).
16131 if (Cond.getOpcode() == ISD::AND &&
16132 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16133 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16134 if (C && C->getAPIntValue() == 1)
16135 Cond = Cond.getOperand(0);
16138 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16139 // setting operand in place of the X86ISD::SETCC.
16140 unsigned CondOpcode = Cond.getOpcode();
16141 if (CondOpcode == X86ISD::SETCC ||
16142 CondOpcode == X86ISD::SETCC_CARRY) {
16143 CC = Cond.getOperand(0);
16145 SDValue Cmp = Cond.getOperand(1);
16146 unsigned Opc = Cmp.getOpcode();
16147 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16148 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16152 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16156 // These can only come from an arithmetic instruction with overflow,
16157 // e.g. SADDO, UADDO.
16158 Cond = Cond.getNode()->getOperand(1);
16164 CondOpcode = Cond.getOpcode();
16165 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16166 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16167 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16168 Cond.getOperand(0).getValueType() != MVT::i8)) {
16169 SDValue LHS = Cond.getOperand(0);
16170 SDValue RHS = Cond.getOperand(1);
16171 unsigned X86Opcode;
16174 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16175 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16177 switch (CondOpcode) {
16178 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16180 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16182 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16185 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16186 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16190 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16193 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16194 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16195 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16196 default: llvm_unreachable("unexpected overflowing operator");
16199 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16200 if (CondOpcode == ISD::UMULO)
16201 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16204 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16206 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16208 if (CondOpcode == ISD::UMULO)
16209 Cond = X86Op.getValue(2);
16211 Cond = X86Op.getValue(1);
16213 CC = DAG.getConstant(X86Cond, MVT::i8);
16217 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16218 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16219 if (CondOpc == ISD::OR) {
16220 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16221 // two branches instead of an explicit OR instruction with a
16223 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16224 isX86LogicalCmp(Cmp)) {
16225 CC = Cond.getOperand(0).getOperand(0);
16226 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16227 Chain, Dest, CC, Cmp);
16228 CC = Cond.getOperand(1).getOperand(0);
16232 } else { // ISD::AND
16233 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16234 // two branches instead of an explicit AND instruction with a
16235 // separate test. However, we only do this if this block doesn't
16236 // have a fall-through edge, because this requires an explicit
16237 // jmp when the condition is false.
16238 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16239 isX86LogicalCmp(Cmp) &&
16240 Op.getNode()->hasOneUse()) {
16241 X86::CondCode CCode =
16242 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16243 CCode = X86::GetOppositeBranchCondition(CCode);
16244 CC = DAG.getConstant(CCode, MVT::i8);
16245 SDNode *User = *Op.getNode()->use_begin();
16246 // Look for an unconditional branch following this conditional branch.
16247 // We need this because we need to reverse the successors in order
16248 // to implement FCMP_OEQ.
16249 if (User->getOpcode() == ISD::BR) {
16250 SDValue FalseBB = User->getOperand(1);
16252 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16253 assert(NewBR == User);
16257 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16258 Chain, Dest, CC, Cmp);
16259 X86::CondCode CCode =
16260 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16261 CCode = X86::GetOppositeBranchCondition(CCode);
16262 CC = DAG.getConstant(CCode, MVT::i8);
16268 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16269 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16270 // It should be transformed during dag combiner except when the condition
16271 // is set by a arithmetics with overflow node.
16272 X86::CondCode CCode =
16273 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16274 CCode = X86::GetOppositeBranchCondition(CCode);
16275 CC = DAG.getConstant(CCode, MVT::i8);
16276 Cond = Cond.getOperand(0).getOperand(1);
16278 } else if (Cond.getOpcode() == ISD::SETCC &&
16279 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16280 // For FCMP_OEQ, we can emit
16281 // two branches instead of an explicit AND instruction with a
16282 // separate test. However, we only do this if this block doesn't
16283 // have a fall-through edge, because this requires an explicit
16284 // jmp when the condition is false.
16285 if (Op.getNode()->hasOneUse()) {
16286 SDNode *User = *Op.getNode()->use_begin();
16287 // Look for an unconditional branch following this conditional branch.
16288 // We need this because we need to reverse the successors in order
16289 // to implement FCMP_OEQ.
16290 if (User->getOpcode() == ISD::BR) {
16291 SDValue FalseBB = User->getOperand(1);
16293 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16294 assert(NewBR == User);
16298 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16299 Cond.getOperand(0), Cond.getOperand(1));
16300 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16301 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16302 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16303 Chain, Dest, CC, Cmp);
16304 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16309 } else if (Cond.getOpcode() == ISD::SETCC &&
16310 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16311 // For FCMP_UNE, we can emit
16312 // two branches instead of an explicit AND instruction with a
16313 // separate test. However, we only do this if this block doesn't
16314 // have a fall-through edge, because this requires an explicit
16315 // jmp when the condition is false.
16316 if (Op.getNode()->hasOneUse()) {
16317 SDNode *User = *Op.getNode()->use_begin();
16318 // Look for an unconditional branch following this conditional branch.
16319 // We need this because we need to reverse the successors in order
16320 // to implement FCMP_UNE.
16321 if (User->getOpcode() == ISD::BR) {
16322 SDValue FalseBB = User->getOperand(1);
16324 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16325 assert(NewBR == User);
16328 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16329 Cond.getOperand(0), Cond.getOperand(1));
16330 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16331 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16332 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16333 Chain, Dest, CC, Cmp);
16334 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16344 // Look pass the truncate if the high bits are known zero.
16345 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16346 Cond = Cond.getOperand(0);
16348 // We know the result of AND is compared against zero. Try to match
16350 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16351 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16352 if (NewSetCC.getNode()) {
16353 CC = NewSetCC.getOperand(0);
16354 Cond = NewSetCC.getOperand(1);
16361 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16362 CC = DAG.getConstant(X86Cond, MVT::i8);
16363 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16365 Cond = ConvertCmpIfNecessary(Cond, DAG);
16366 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16367 Chain, Dest, CC, Cond);
16370 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16371 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16372 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16373 // that the guard pages used by the OS virtual memory manager are allocated in
16374 // correct sequence.
16376 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16377 SelectionDAG &DAG) const {
16378 MachineFunction &MF = DAG.getMachineFunction();
16379 bool SplitStack = MF.shouldSplitStack();
16380 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16386 SDNode* Node = Op.getNode();
16388 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16389 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16390 " not tell us which reg is the stack pointer!");
16391 EVT VT = Node->getValueType(0);
16392 SDValue Tmp1 = SDValue(Node, 0);
16393 SDValue Tmp2 = SDValue(Node, 1);
16394 SDValue Tmp3 = Node->getOperand(2);
16395 SDValue Chain = Tmp1.getOperand(0);
16397 // Chain the dynamic stack allocation so that it doesn't modify the stack
16398 // pointer when other instructions are using the stack.
16399 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16402 SDValue Size = Tmp2.getOperand(1);
16403 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16404 Chain = SP.getValue(1);
16405 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16406 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16407 unsigned StackAlign = TFI.getStackAlignment();
16408 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16409 if (Align > StackAlign)
16410 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16411 DAG.getConstant(-(uint64_t)Align, VT));
16412 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16414 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16415 DAG.getIntPtrConstant(0, true), SDValue(),
16418 SDValue Ops[2] = { Tmp1, Tmp2 };
16419 return DAG.getMergeValues(Ops, dl);
16423 SDValue Chain = Op.getOperand(0);
16424 SDValue Size = Op.getOperand(1);
16425 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16426 EVT VT = Op.getNode()->getValueType(0);
16428 bool Is64Bit = Subtarget->is64Bit();
16429 EVT SPTy = getPointerTy();
16432 MachineRegisterInfo &MRI = MF.getRegInfo();
16435 // The 64 bit implementation of segmented stacks needs to clobber both r10
16436 // r11. This makes it impossible to use it along with nested parameters.
16437 const Function *F = MF.getFunction();
16439 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16441 if (I->hasNestAttr())
16442 report_fatal_error("Cannot use segmented stacks with functions that "
16443 "have nested arguments.");
16446 const TargetRegisterClass *AddrRegClass =
16447 getRegClassFor(getPointerTy());
16448 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16449 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16450 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16451 DAG.getRegister(Vreg, SPTy));
16452 SDValue Ops1[2] = { Value, Chain };
16453 return DAG.getMergeValues(Ops1, dl);
16456 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16458 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16459 Flag = Chain.getValue(1);
16460 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16462 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16464 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16465 DAG.getSubtarget().getRegisterInfo());
16466 unsigned SPReg = RegInfo->getStackRegister();
16467 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16468 Chain = SP.getValue(1);
16471 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16472 DAG.getConstant(-(uint64_t)Align, VT));
16473 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16476 SDValue Ops1[2] = { SP, Chain };
16477 return DAG.getMergeValues(Ops1, dl);
16481 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16482 MachineFunction &MF = DAG.getMachineFunction();
16483 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16485 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16488 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16489 // vastart just stores the address of the VarArgsFrameIndex slot into the
16490 // memory location argument.
16491 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16493 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16494 MachinePointerInfo(SV), false, false, 0);
16498 // gp_offset (0 - 6 * 8)
16499 // fp_offset (48 - 48 + 8 * 16)
16500 // overflow_arg_area (point to parameters coming in memory).
16502 SmallVector<SDValue, 8> MemOps;
16503 SDValue FIN = Op.getOperand(1);
16505 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16506 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16508 FIN, MachinePointerInfo(SV), false, false, 0);
16509 MemOps.push_back(Store);
16512 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16513 FIN, DAG.getIntPtrConstant(4));
16514 Store = DAG.getStore(Op.getOperand(0), DL,
16515 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16517 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16518 MemOps.push_back(Store);
16520 // Store ptr to overflow_arg_area
16521 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16522 FIN, DAG.getIntPtrConstant(4));
16523 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16525 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16526 MachinePointerInfo(SV, 8),
16528 MemOps.push_back(Store);
16530 // Store ptr to reg_save_area.
16531 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16532 FIN, DAG.getIntPtrConstant(8));
16533 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16535 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16536 MachinePointerInfo(SV, 16), false, false, 0);
16537 MemOps.push_back(Store);
16538 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16541 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16542 assert(Subtarget->is64Bit() &&
16543 "LowerVAARG only handles 64-bit va_arg!");
16544 assert((Subtarget->isTargetLinux() ||
16545 Subtarget->isTargetDarwin()) &&
16546 "Unhandled target in LowerVAARG");
16547 assert(Op.getNode()->getNumOperands() == 4);
16548 SDValue Chain = Op.getOperand(0);
16549 SDValue SrcPtr = Op.getOperand(1);
16550 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16551 unsigned Align = Op.getConstantOperandVal(3);
16554 EVT ArgVT = Op.getNode()->getValueType(0);
16555 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16556 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16559 // Decide which area this value should be read from.
16560 // TODO: Implement the AMD64 ABI in its entirety. This simple
16561 // selection mechanism works only for the basic types.
16562 if (ArgVT == MVT::f80) {
16563 llvm_unreachable("va_arg for f80 not yet implemented");
16564 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16565 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16566 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16567 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16569 llvm_unreachable("Unhandled argument type in LowerVAARG");
16572 if (ArgMode == 2) {
16573 // Sanity Check: Make sure using fp_offset makes sense.
16574 assert(!DAG.getTarget().Options.UseSoftFloat &&
16575 !(DAG.getMachineFunction()
16576 .getFunction()->getAttributes()
16577 .hasAttribute(AttributeSet::FunctionIndex,
16578 Attribute::NoImplicitFloat)) &&
16579 Subtarget->hasSSE1());
16582 // Insert VAARG_64 node into the DAG
16583 // VAARG_64 returns two values: Variable Argument Address, Chain
16584 SmallVector<SDValue, 11> InstOps;
16585 InstOps.push_back(Chain);
16586 InstOps.push_back(SrcPtr);
16587 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16588 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16589 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16590 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16591 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16592 VTs, InstOps, MVT::i64,
16593 MachinePointerInfo(SV),
16595 /*Volatile=*/false,
16597 /*WriteMem=*/true);
16598 Chain = VAARG.getValue(1);
16600 // Load the next argument and return it
16601 return DAG.getLoad(ArgVT, dl,
16604 MachinePointerInfo(),
16605 false, false, false, 0);
16608 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16609 SelectionDAG &DAG) {
16610 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16611 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16612 SDValue Chain = Op.getOperand(0);
16613 SDValue DstPtr = Op.getOperand(1);
16614 SDValue SrcPtr = Op.getOperand(2);
16615 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16616 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16619 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16620 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16622 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16625 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16626 // amount is a constant. Takes immediate version of shift as input.
16627 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16628 SDValue SrcOp, uint64_t ShiftAmt,
16629 SelectionDAG &DAG) {
16630 MVT ElementType = VT.getVectorElementType();
16632 // Fold this packed shift into its first operand if ShiftAmt is 0.
16636 // Check for ShiftAmt >= element width
16637 if (ShiftAmt >= ElementType.getSizeInBits()) {
16638 if (Opc == X86ISD::VSRAI)
16639 ShiftAmt = ElementType.getSizeInBits() - 1;
16641 return DAG.getConstant(0, VT);
16644 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16645 && "Unknown target vector shift-by-constant node");
16647 // Fold this packed vector shift into a build vector if SrcOp is a
16648 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16649 if (VT == SrcOp.getSimpleValueType() &&
16650 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16651 SmallVector<SDValue, 8> Elts;
16652 unsigned NumElts = SrcOp->getNumOperands();
16653 ConstantSDNode *ND;
16656 default: llvm_unreachable(nullptr);
16657 case X86ISD::VSHLI:
16658 for (unsigned i=0; i!=NumElts; ++i) {
16659 SDValue CurrentOp = SrcOp->getOperand(i);
16660 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16661 Elts.push_back(CurrentOp);
16664 ND = cast<ConstantSDNode>(CurrentOp);
16665 const APInt &C = ND->getAPIntValue();
16666 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16669 case X86ISD::VSRLI:
16670 for (unsigned i=0; i!=NumElts; ++i) {
16671 SDValue CurrentOp = SrcOp->getOperand(i);
16672 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16673 Elts.push_back(CurrentOp);
16676 ND = cast<ConstantSDNode>(CurrentOp);
16677 const APInt &C = ND->getAPIntValue();
16678 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16681 case X86ISD::VSRAI:
16682 for (unsigned i=0; i!=NumElts; ++i) {
16683 SDValue CurrentOp = SrcOp->getOperand(i);
16684 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16685 Elts.push_back(CurrentOp);
16688 ND = cast<ConstantSDNode>(CurrentOp);
16689 const APInt &C = ND->getAPIntValue();
16690 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16695 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16698 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16701 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16702 // may or may not be a constant. Takes immediate version of shift as input.
16703 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16704 SDValue SrcOp, SDValue ShAmt,
16705 SelectionDAG &DAG) {
16706 MVT SVT = ShAmt.getSimpleValueType();
16707 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16709 // Catch shift-by-constant.
16710 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16711 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16712 CShAmt->getZExtValue(), DAG);
16714 // Change opcode to non-immediate version
16716 default: llvm_unreachable("Unknown target vector shift node");
16717 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16718 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16719 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16722 const X86Subtarget &Subtarget =
16723 DAG.getTarget().getSubtarget<X86Subtarget>();
16724 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16725 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16726 // Let the shuffle legalizer expand this shift amount node.
16727 SDValue Op0 = ShAmt.getOperand(0);
16728 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16729 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16731 // Need to build a vector containing shift amount.
16732 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16733 SmallVector<SDValue, 4> ShOps;
16734 ShOps.push_back(ShAmt);
16735 if (SVT == MVT::i32) {
16736 ShOps.push_back(DAG.getConstant(0, SVT));
16737 ShOps.push_back(DAG.getUNDEF(SVT));
16739 ShOps.push_back(DAG.getUNDEF(SVT));
16741 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16742 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16745 // The return type has to be a 128-bit type with the same element
16746 // type as the input type.
16747 MVT EltVT = VT.getVectorElementType();
16748 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16750 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16751 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16754 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16755 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16756 /// necessary casting for \p Mask when lowering masking intrinsics.
16757 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16758 SDValue PreservedSrc,
16759 const X86Subtarget *Subtarget,
16760 SelectionDAG &DAG) {
16761 EVT VT = Op.getValueType();
16762 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16763 MVT::i1, VT.getVectorNumElements());
16764 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16765 Mask.getValueType().getSizeInBits());
16768 assert(MaskVT.isSimple() && "invalid mask type");
16770 if (isAllOnes(Mask))
16773 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16774 // are extracted by EXTRACT_SUBVECTOR.
16775 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16776 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16777 DAG.getIntPtrConstant(0));
16779 switch (Op.getOpcode()) {
16781 case X86ISD::PCMPEQM:
16782 case X86ISD::PCMPGTM:
16784 case X86ISD::CMPMU:
16785 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16787 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16788 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16789 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16792 /// \brief Creates an SDNode for a predicated scalar operation.
16793 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16794 /// The mask is comming as MVT::i8 and it should be truncated
16795 /// to MVT::i1 while lowering masking intrinsics.
16796 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16797 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16798 /// a scalar instruction.
16799 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16800 SDValue PreservedSrc,
16801 const X86Subtarget *Subtarget,
16802 SelectionDAG &DAG) {
16803 if (isAllOnes(Mask))
16806 EVT VT = Op.getValueType();
16808 // The mask should be of type MVT::i1
16809 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16811 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16812 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16813 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16816 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16818 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16819 case Intrinsic::x86_fma_vfmadd_ps:
16820 case Intrinsic::x86_fma_vfmadd_pd:
16821 case Intrinsic::x86_fma_vfmadd_ps_256:
16822 case Intrinsic::x86_fma_vfmadd_pd_256:
16823 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16824 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16825 return X86ISD::FMADD;
16826 case Intrinsic::x86_fma_vfmsub_ps:
16827 case Intrinsic::x86_fma_vfmsub_pd:
16828 case Intrinsic::x86_fma_vfmsub_ps_256:
16829 case Intrinsic::x86_fma_vfmsub_pd_256:
16830 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16831 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16832 return X86ISD::FMSUB;
16833 case Intrinsic::x86_fma_vfnmadd_ps:
16834 case Intrinsic::x86_fma_vfnmadd_pd:
16835 case Intrinsic::x86_fma_vfnmadd_ps_256:
16836 case Intrinsic::x86_fma_vfnmadd_pd_256:
16837 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16838 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16839 return X86ISD::FNMADD;
16840 case Intrinsic::x86_fma_vfnmsub_ps:
16841 case Intrinsic::x86_fma_vfnmsub_pd:
16842 case Intrinsic::x86_fma_vfnmsub_ps_256:
16843 case Intrinsic::x86_fma_vfnmsub_pd_256:
16844 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16845 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16846 return X86ISD::FNMSUB;
16847 case Intrinsic::x86_fma_vfmaddsub_ps:
16848 case Intrinsic::x86_fma_vfmaddsub_pd:
16849 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16850 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16851 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16852 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16853 return X86ISD::FMADDSUB;
16854 case Intrinsic::x86_fma_vfmsubadd_ps:
16855 case Intrinsic::x86_fma_vfmsubadd_pd:
16856 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16857 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16858 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16859 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16860 return X86ISD::FMSUBADD;
16864 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16865 SelectionDAG &DAG) {
16867 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16868 EVT VT = Op.getValueType();
16869 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16871 switch(IntrData->Type) {
16872 case INTR_TYPE_1OP:
16873 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16874 case INTR_TYPE_2OP:
16875 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16877 case INTR_TYPE_3OP:
16878 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16879 Op.getOperand(2), Op.getOperand(3));
16880 case INTR_TYPE_1OP_MASK_RM: {
16881 SDValue Src = Op.getOperand(1);
16882 SDValue Src0 = Op.getOperand(2);
16883 SDValue Mask = Op.getOperand(3);
16884 SDValue RoundingMode = Op.getOperand(4);
16885 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16887 Mask, Src0, Subtarget, DAG);
16889 case INTR_TYPE_SCALAR_MASK_RM: {
16890 SDValue Src1 = Op.getOperand(1);
16891 SDValue Src2 = Op.getOperand(2);
16892 SDValue Src0 = Op.getOperand(3);
16893 SDValue Mask = Op.getOperand(4);
16894 SDValue RoundingMode = Op.getOperand(5);
16895 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16897 Mask, Src0, Subtarget, DAG);
16899 case INTR_TYPE_2OP_MASK: {
16900 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16902 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16905 case CMP_MASK_CC: {
16906 // Comparison intrinsics with masks.
16907 // Example of transformation:
16908 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16909 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16911 // (v8i1 (insert_subvector undef,
16912 // (v2i1 (and (PCMPEQM %a, %b),
16913 // (extract_subvector
16914 // (v8i1 (bitcast %mask)), 0))), 0))))
16915 EVT VT = Op.getOperand(1).getValueType();
16916 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16917 VT.getVectorNumElements());
16918 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16919 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16920 Mask.getValueType().getSizeInBits());
16922 if (IntrData->Type == CMP_MASK_CC) {
16923 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16924 Op.getOperand(2), Op.getOperand(3));
16926 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16927 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16930 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16931 DAG.getTargetConstant(0, MaskVT),
16933 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16934 DAG.getUNDEF(BitcastVT), CmpMask,
16935 DAG.getIntPtrConstant(0));
16936 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16938 case COMI: { // Comparison intrinsics
16939 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16940 SDValue LHS = Op.getOperand(1);
16941 SDValue RHS = Op.getOperand(2);
16942 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16943 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16944 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16945 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16946 DAG.getConstant(X86CC, MVT::i8), Cond);
16947 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16950 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16951 Op.getOperand(1), Op.getOperand(2), DAG);
16953 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16954 Op.getSimpleValueType(),
16956 Op.getOperand(2), DAG),
16957 Op.getOperand(4), Op.getOperand(3), Subtarget,
16959 case COMPRESS_TO_REG: {
16960 SDValue Mask = Op.getOperand(3);
16961 SDValue DataToCompress = Op.getOperand(1);
16962 SDValue PassThru = Op.getOperand(2);
16963 if (isAllOnes(Mask)) // return data as is
16964 return Op.getOperand(1);
16965 EVT VT = Op.getValueType();
16966 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16967 VT.getVectorNumElements());
16968 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16969 Mask.getValueType().getSizeInBits());
16971 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16972 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16973 DAG.getIntPtrConstant(0));
16975 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
16984 default: return SDValue(); // Don't custom lower most intrinsics.
16986 case Intrinsic::x86_avx512_mask_valign_q_512:
16987 case Intrinsic::x86_avx512_mask_valign_d_512:
16988 // Vector source operands are swapped.
16989 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16990 Op.getValueType(), Op.getOperand(2),
16993 Op.getOperand(5), Op.getOperand(4),
16996 // ptest and testp intrinsics. The intrinsic these come from are designed to
16997 // return an integer value, not just an instruction so lower it to the ptest
16998 // or testp pattern and a setcc for the result.
16999 case Intrinsic::x86_sse41_ptestz:
17000 case Intrinsic::x86_sse41_ptestc:
17001 case Intrinsic::x86_sse41_ptestnzc:
17002 case Intrinsic::x86_avx_ptestz_256:
17003 case Intrinsic::x86_avx_ptestc_256:
17004 case Intrinsic::x86_avx_ptestnzc_256:
17005 case Intrinsic::x86_avx_vtestz_ps:
17006 case Intrinsic::x86_avx_vtestc_ps:
17007 case Intrinsic::x86_avx_vtestnzc_ps:
17008 case Intrinsic::x86_avx_vtestz_pd:
17009 case Intrinsic::x86_avx_vtestc_pd:
17010 case Intrinsic::x86_avx_vtestnzc_pd:
17011 case Intrinsic::x86_avx_vtestz_ps_256:
17012 case Intrinsic::x86_avx_vtestc_ps_256:
17013 case Intrinsic::x86_avx_vtestnzc_ps_256:
17014 case Intrinsic::x86_avx_vtestz_pd_256:
17015 case Intrinsic::x86_avx_vtestc_pd_256:
17016 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17017 bool IsTestPacked = false;
17020 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17021 case Intrinsic::x86_avx_vtestz_ps:
17022 case Intrinsic::x86_avx_vtestz_pd:
17023 case Intrinsic::x86_avx_vtestz_ps_256:
17024 case Intrinsic::x86_avx_vtestz_pd_256:
17025 IsTestPacked = true; // Fallthrough
17026 case Intrinsic::x86_sse41_ptestz:
17027 case Intrinsic::x86_avx_ptestz_256:
17029 X86CC = X86::COND_E;
17031 case Intrinsic::x86_avx_vtestc_ps:
17032 case Intrinsic::x86_avx_vtestc_pd:
17033 case Intrinsic::x86_avx_vtestc_ps_256:
17034 case Intrinsic::x86_avx_vtestc_pd_256:
17035 IsTestPacked = true; // Fallthrough
17036 case Intrinsic::x86_sse41_ptestc:
17037 case Intrinsic::x86_avx_ptestc_256:
17039 X86CC = X86::COND_B;
17041 case Intrinsic::x86_avx_vtestnzc_ps:
17042 case Intrinsic::x86_avx_vtestnzc_pd:
17043 case Intrinsic::x86_avx_vtestnzc_ps_256:
17044 case Intrinsic::x86_avx_vtestnzc_pd_256:
17045 IsTestPacked = true; // Fallthrough
17046 case Intrinsic::x86_sse41_ptestnzc:
17047 case Intrinsic::x86_avx_ptestnzc_256:
17049 X86CC = X86::COND_A;
17053 SDValue LHS = Op.getOperand(1);
17054 SDValue RHS = Op.getOperand(2);
17055 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17056 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17057 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17058 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17059 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17061 case Intrinsic::x86_avx512_kortestz_w:
17062 case Intrinsic::x86_avx512_kortestc_w: {
17063 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17064 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17065 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17066 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17067 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17068 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17069 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17072 case Intrinsic::x86_sse42_pcmpistria128:
17073 case Intrinsic::x86_sse42_pcmpestria128:
17074 case Intrinsic::x86_sse42_pcmpistric128:
17075 case Intrinsic::x86_sse42_pcmpestric128:
17076 case Intrinsic::x86_sse42_pcmpistrio128:
17077 case Intrinsic::x86_sse42_pcmpestrio128:
17078 case Intrinsic::x86_sse42_pcmpistris128:
17079 case Intrinsic::x86_sse42_pcmpestris128:
17080 case Intrinsic::x86_sse42_pcmpistriz128:
17081 case Intrinsic::x86_sse42_pcmpestriz128: {
17085 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17086 case Intrinsic::x86_sse42_pcmpistria128:
17087 Opcode = X86ISD::PCMPISTRI;
17088 X86CC = X86::COND_A;
17090 case Intrinsic::x86_sse42_pcmpestria128:
17091 Opcode = X86ISD::PCMPESTRI;
17092 X86CC = X86::COND_A;
17094 case Intrinsic::x86_sse42_pcmpistric128:
17095 Opcode = X86ISD::PCMPISTRI;
17096 X86CC = X86::COND_B;
17098 case Intrinsic::x86_sse42_pcmpestric128:
17099 Opcode = X86ISD::PCMPESTRI;
17100 X86CC = X86::COND_B;
17102 case Intrinsic::x86_sse42_pcmpistrio128:
17103 Opcode = X86ISD::PCMPISTRI;
17104 X86CC = X86::COND_O;
17106 case Intrinsic::x86_sse42_pcmpestrio128:
17107 Opcode = X86ISD::PCMPESTRI;
17108 X86CC = X86::COND_O;
17110 case Intrinsic::x86_sse42_pcmpistris128:
17111 Opcode = X86ISD::PCMPISTRI;
17112 X86CC = X86::COND_S;
17114 case Intrinsic::x86_sse42_pcmpestris128:
17115 Opcode = X86ISD::PCMPESTRI;
17116 X86CC = X86::COND_S;
17118 case Intrinsic::x86_sse42_pcmpistriz128:
17119 Opcode = X86ISD::PCMPISTRI;
17120 X86CC = X86::COND_E;
17122 case Intrinsic::x86_sse42_pcmpestriz128:
17123 Opcode = X86ISD::PCMPESTRI;
17124 X86CC = X86::COND_E;
17127 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17128 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17129 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17130 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17131 DAG.getConstant(X86CC, MVT::i8),
17132 SDValue(PCMP.getNode(), 1));
17133 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17136 case Intrinsic::x86_sse42_pcmpistri128:
17137 case Intrinsic::x86_sse42_pcmpestri128: {
17139 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17140 Opcode = X86ISD::PCMPISTRI;
17142 Opcode = X86ISD::PCMPESTRI;
17144 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17145 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17146 return DAG.getNode(Opcode, dl, VTs, NewOps);
17149 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17150 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17151 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17152 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17153 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17154 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17155 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17156 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17157 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17158 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17159 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17160 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17161 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17162 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17163 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17164 dl, Op.getValueType(),
17168 Op.getOperand(4), Op.getOperand(1),
17174 case Intrinsic::x86_fma_vfmadd_ps:
17175 case Intrinsic::x86_fma_vfmadd_pd:
17176 case Intrinsic::x86_fma_vfmsub_ps:
17177 case Intrinsic::x86_fma_vfmsub_pd:
17178 case Intrinsic::x86_fma_vfnmadd_ps:
17179 case Intrinsic::x86_fma_vfnmadd_pd:
17180 case Intrinsic::x86_fma_vfnmsub_ps:
17181 case Intrinsic::x86_fma_vfnmsub_pd:
17182 case Intrinsic::x86_fma_vfmaddsub_ps:
17183 case Intrinsic::x86_fma_vfmaddsub_pd:
17184 case Intrinsic::x86_fma_vfmsubadd_ps:
17185 case Intrinsic::x86_fma_vfmsubadd_pd:
17186 case Intrinsic::x86_fma_vfmadd_ps_256:
17187 case Intrinsic::x86_fma_vfmadd_pd_256:
17188 case Intrinsic::x86_fma_vfmsub_ps_256:
17189 case Intrinsic::x86_fma_vfmsub_pd_256:
17190 case Intrinsic::x86_fma_vfnmadd_ps_256:
17191 case Intrinsic::x86_fma_vfnmadd_pd_256:
17192 case Intrinsic::x86_fma_vfnmsub_ps_256:
17193 case Intrinsic::x86_fma_vfnmsub_pd_256:
17194 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17195 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17196 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17197 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17198 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17199 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17203 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17204 SDValue Src, SDValue Mask, SDValue Base,
17205 SDValue Index, SDValue ScaleOp, SDValue Chain,
17206 const X86Subtarget * Subtarget) {
17208 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17209 assert(C && "Invalid scale type");
17210 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17211 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17212 Index.getSimpleValueType().getVectorNumElements());
17214 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17216 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17218 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17219 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17220 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17221 SDValue Segment = DAG.getRegister(0, MVT::i32);
17222 if (Src.getOpcode() == ISD::UNDEF)
17223 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17224 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17225 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17226 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17227 return DAG.getMergeValues(RetOps, dl);
17230 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17231 SDValue Src, SDValue Mask, SDValue Base,
17232 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17235 assert(C && "Invalid scale type");
17236 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17237 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17238 SDValue Segment = DAG.getRegister(0, MVT::i32);
17239 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17240 Index.getSimpleValueType().getVectorNumElements());
17242 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17244 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17246 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17247 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17248 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17249 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17250 return SDValue(Res, 1);
17253 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17254 SDValue Mask, SDValue Base, SDValue Index,
17255 SDValue ScaleOp, SDValue Chain) {
17257 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17258 assert(C && "Invalid scale type");
17259 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17260 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17261 SDValue Segment = DAG.getRegister(0, MVT::i32);
17263 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17265 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17267 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17269 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17270 //SDVTList VTs = DAG.getVTList(MVT::Other);
17271 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17272 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17273 return SDValue(Res, 0);
17276 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17277 // read performance monitor counters (x86_rdpmc).
17278 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17279 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17280 SmallVectorImpl<SDValue> &Results) {
17281 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17282 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17285 // The ECX register is used to select the index of the performance counter
17287 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17289 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17291 // Reads the content of a 64-bit performance counter and returns it in the
17292 // registers EDX:EAX.
17293 if (Subtarget->is64Bit()) {
17294 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17295 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17298 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17299 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17302 Chain = HI.getValue(1);
17304 if (Subtarget->is64Bit()) {
17305 // The EAX register is loaded with the low-order 32 bits. The EDX register
17306 // is loaded with the supported high-order bits of the counter.
17307 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17308 DAG.getConstant(32, MVT::i8));
17309 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17310 Results.push_back(Chain);
17314 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17315 SDValue Ops[] = { LO, HI };
17316 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17317 Results.push_back(Pair);
17318 Results.push_back(Chain);
17321 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17322 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17323 // also used to custom lower READCYCLECOUNTER nodes.
17324 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17325 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17326 SmallVectorImpl<SDValue> &Results) {
17327 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17328 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17331 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17332 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17333 // and the EAX register is loaded with the low-order 32 bits.
17334 if (Subtarget->is64Bit()) {
17335 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17336 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17339 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17340 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17343 SDValue Chain = HI.getValue(1);
17345 if (Opcode == X86ISD::RDTSCP_DAG) {
17346 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17348 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17349 // the ECX register. Add 'ecx' explicitly to the chain.
17350 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17352 // Explicitly store the content of ECX at the location passed in input
17353 // to the 'rdtscp' intrinsic.
17354 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17355 MachinePointerInfo(), false, false, 0);
17358 if (Subtarget->is64Bit()) {
17359 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17360 // the EAX register is loaded with the low-order 32 bits.
17361 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17362 DAG.getConstant(32, MVT::i8));
17363 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17364 Results.push_back(Chain);
17368 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17369 SDValue Ops[] = { LO, HI };
17370 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17371 Results.push_back(Pair);
17372 Results.push_back(Chain);
17375 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17376 SelectionDAG &DAG) {
17377 SmallVector<SDValue, 2> Results;
17379 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17381 return DAG.getMergeValues(Results, DL);
17385 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17386 SelectionDAG &DAG) {
17387 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17389 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17394 switch(IntrData->Type) {
17396 llvm_unreachable("Unknown Intrinsic Type");
17400 // Emit the node with the right value type.
17401 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17402 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17404 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17405 // Otherwise return the value from Rand, which is always 0, casted to i32.
17406 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17407 DAG.getConstant(1, Op->getValueType(1)),
17408 DAG.getConstant(X86::COND_B, MVT::i32),
17409 SDValue(Result.getNode(), 1) };
17410 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17411 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17414 // Return { result, isValid, chain }.
17415 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17416 SDValue(Result.getNode(), 2));
17419 //gather(v1, mask, index, base, scale);
17420 SDValue Chain = Op.getOperand(0);
17421 SDValue Src = Op.getOperand(2);
17422 SDValue Base = Op.getOperand(3);
17423 SDValue Index = Op.getOperand(4);
17424 SDValue Mask = Op.getOperand(5);
17425 SDValue Scale = Op.getOperand(6);
17426 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17430 //scatter(base, mask, index, v1, scale);
17431 SDValue Chain = Op.getOperand(0);
17432 SDValue Base = Op.getOperand(2);
17433 SDValue Mask = Op.getOperand(3);
17434 SDValue Index = Op.getOperand(4);
17435 SDValue Src = Op.getOperand(5);
17436 SDValue Scale = Op.getOperand(6);
17437 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17440 SDValue Hint = Op.getOperand(6);
17442 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17443 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17444 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17445 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17446 SDValue Chain = Op.getOperand(0);
17447 SDValue Mask = Op.getOperand(2);
17448 SDValue Index = Op.getOperand(3);
17449 SDValue Base = Op.getOperand(4);
17450 SDValue Scale = Op.getOperand(5);
17451 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17453 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17455 SmallVector<SDValue, 2> Results;
17456 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17457 return DAG.getMergeValues(Results, dl);
17459 // Read Performance Monitoring Counters.
17461 SmallVector<SDValue, 2> Results;
17462 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17463 return DAG.getMergeValues(Results, dl);
17465 // XTEST intrinsics.
17467 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17468 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17469 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17470 DAG.getConstant(X86::COND_NE, MVT::i8),
17472 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17473 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17474 Ret, SDValue(InTrans.getNode(), 1));
17478 SmallVector<SDValue, 2> Results;
17479 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17480 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17481 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17482 DAG.getConstant(-1, MVT::i8));
17483 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17484 Op.getOperand(4), GenCF.getValue(1));
17485 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17486 Op.getOperand(5), MachinePointerInfo(),
17488 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17489 DAG.getConstant(X86::COND_B, MVT::i8),
17491 Results.push_back(SetCC);
17492 Results.push_back(Store);
17493 return DAG.getMergeValues(Results, dl);
17495 case COMPRESS_TO_MEM: {
17497 SDValue Mask = Op.getOperand(4);
17498 SDValue DataToCompress = Op.getOperand(3);
17499 SDValue Addr = Op.getOperand(2);
17500 SDValue Chain = Op.getOperand(0);
17502 if (isAllOnes(Mask)) // return just a store
17503 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17504 MachinePointerInfo(), false, false, 0);
17506 EVT VT = DataToCompress.getValueType();
17507 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17508 VT.getVectorNumElements());
17509 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17510 Mask.getValueType().getSizeInBits());
17511 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17512 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17513 DAG.getIntPtrConstant(0));
17515 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17516 DataToCompress, DAG.getUNDEF(VT));
17517 return DAG.getStore(Chain, dl, Compressed, Addr,
17518 MachinePointerInfo(), false, false, 0);
17523 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17524 SelectionDAG &DAG) const {
17525 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17526 MFI->setReturnAddressIsTaken(true);
17528 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17531 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17533 EVT PtrVT = getPointerTy();
17536 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17537 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17538 DAG.getSubtarget().getRegisterInfo());
17539 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17540 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17541 DAG.getNode(ISD::ADD, dl, PtrVT,
17542 FrameAddr, Offset),
17543 MachinePointerInfo(), false, false, false, 0);
17546 // Just load the return address.
17547 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17548 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17549 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17552 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17553 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17554 MFI->setFrameAddressIsTaken(true);
17556 EVT VT = Op.getValueType();
17557 SDLoc dl(Op); // FIXME probably not meaningful
17558 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17559 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17560 DAG.getSubtarget().getRegisterInfo());
17561 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17562 DAG.getMachineFunction());
17563 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17564 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17565 "Invalid Frame Register!");
17566 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17568 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17569 MachinePointerInfo(),
17570 false, false, false, 0);
17574 // FIXME? Maybe this could be a TableGen attribute on some registers and
17575 // this table could be generated automatically from RegInfo.
17576 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17578 unsigned Reg = StringSwitch<unsigned>(RegName)
17579 .Case("esp", X86::ESP)
17580 .Case("rsp", X86::RSP)
17584 report_fatal_error("Invalid register name global variable");
17587 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17588 SelectionDAG &DAG) const {
17589 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17590 DAG.getSubtarget().getRegisterInfo());
17591 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17594 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17595 SDValue Chain = Op.getOperand(0);
17596 SDValue Offset = Op.getOperand(1);
17597 SDValue Handler = Op.getOperand(2);
17600 EVT PtrVT = getPointerTy();
17601 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17602 DAG.getSubtarget().getRegisterInfo());
17603 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17604 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17605 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17606 "Invalid Frame Register!");
17607 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17608 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17610 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17611 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17612 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17613 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17615 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17617 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17618 DAG.getRegister(StoreAddrReg, PtrVT));
17621 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17622 SelectionDAG &DAG) const {
17624 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17625 DAG.getVTList(MVT::i32, MVT::Other),
17626 Op.getOperand(0), Op.getOperand(1));
17629 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17630 SelectionDAG &DAG) const {
17632 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17633 Op.getOperand(0), Op.getOperand(1));
17636 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17637 return Op.getOperand(0);
17640 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17641 SelectionDAG &DAG) const {
17642 SDValue Root = Op.getOperand(0);
17643 SDValue Trmp = Op.getOperand(1); // trampoline
17644 SDValue FPtr = Op.getOperand(2); // nested function
17645 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17648 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17649 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17651 if (Subtarget->is64Bit()) {
17652 SDValue OutChains[6];
17654 // Large code-model.
17655 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17656 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17658 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17659 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17661 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17663 // Load the pointer to the nested function into R11.
17664 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17665 SDValue Addr = Trmp;
17666 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17667 Addr, MachinePointerInfo(TrmpAddr),
17670 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17671 DAG.getConstant(2, MVT::i64));
17672 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17673 MachinePointerInfo(TrmpAddr, 2),
17676 // Load the 'nest' parameter value into R10.
17677 // R10 is specified in X86CallingConv.td
17678 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17679 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17680 DAG.getConstant(10, MVT::i64));
17681 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17682 Addr, MachinePointerInfo(TrmpAddr, 10),
17685 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17686 DAG.getConstant(12, MVT::i64));
17687 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17688 MachinePointerInfo(TrmpAddr, 12),
17691 // Jump to the nested function.
17692 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17693 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17694 DAG.getConstant(20, MVT::i64));
17695 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17696 Addr, MachinePointerInfo(TrmpAddr, 20),
17699 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17700 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17701 DAG.getConstant(22, MVT::i64));
17702 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17703 MachinePointerInfo(TrmpAddr, 22),
17706 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17708 const Function *Func =
17709 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17710 CallingConv::ID CC = Func->getCallingConv();
17715 llvm_unreachable("Unsupported calling convention");
17716 case CallingConv::C:
17717 case CallingConv::X86_StdCall: {
17718 // Pass 'nest' parameter in ECX.
17719 // Must be kept in sync with X86CallingConv.td
17720 NestReg = X86::ECX;
17722 // Check that ECX wasn't needed by an 'inreg' parameter.
17723 FunctionType *FTy = Func->getFunctionType();
17724 const AttributeSet &Attrs = Func->getAttributes();
17726 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17727 unsigned InRegCount = 0;
17730 for (FunctionType::param_iterator I = FTy->param_begin(),
17731 E = FTy->param_end(); I != E; ++I, ++Idx)
17732 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17733 // FIXME: should only count parameters that are lowered to integers.
17734 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17736 if (InRegCount > 2) {
17737 report_fatal_error("Nest register in use - reduce number of inreg"
17743 case CallingConv::X86_FastCall:
17744 case CallingConv::X86_ThisCall:
17745 case CallingConv::Fast:
17746 // Pass 'nest' parameter in EAX.
17747 // Must be kept in sync with X86CallingConv.td
17748 NestReg = X86::EAX;
17752 SDValue OutChains[4];
17753 SDValue Addr, Disp;
17755 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17756 DAG.getConstant(10, MVT::i32));
17757 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17759 // This is storing the opcode for MOV32ri.
17760 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17761 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17762 OutChains[0] = DAG.getStore(Root, dl,
17763 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17764 Trmp, MachinePointerInfo(TrmpAddr),
17767 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17768 DAG.getConstant(1, MVT::i32));
17769 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17770 MachinePointerInfo(TrmpAddr, 1),
17773 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17774 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17775 DAG.getConstant(5, MVT::i32));
17776 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17777 MachinePointerInfo(TrmpAddr, 5),
17780 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17781 DAG.getConstant(6, MVT::i32));
17782 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17783 MachinePointerInfo(TrmpAddr, 6),
17786 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17790 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17791 SelectionDAG &DAG) const {
17793 The rounding mode is in bits 11:10 of FPSR, and has the following
17795 00 Round to nearest
17800 FLT_ROUNDS, on the other hand, expects the following:
17807 To perform the conversion, we do:
17808 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17811 MachineFunction &MF = DAG.getMachineFunction();
17812 const TargetMachine &TM = MF.getTarget();
17813 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17814 unsigned StackAlignment = TFI.getStackAlignment();
17815 MVT VT = Op.getSimpleValueType();
17818 // Save FP Control Word to stack slot
17819 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17820 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17822 MachineMemOperand *MMO =
17823 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17824 MachineMemOperand::MOStore, 2, 2);
17826 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17827 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17828 DAG.getVTList(MVT::Other),
17829 Ops, MVT::i16, MMO);
17831 // Load FP Control Word from stack slot
17832 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17833 MachinePointerInfo(), false, false, false, 0);
17835 // Transform as necessary
17837 DAG.getNode(ISD::SRL, DL, MVT::i16,
17838 DAG.getNode(ISD::AND, DL, MVT::i16,
17839 CWD, DAG.getConstant(0x800, MVT::i16)),
17840 DAG.getConstant(11, MVT::i8));
17842 DAG.getNode(ISD::SRL, DL, MVT::i16,
17843 DAG.getNode(ISD::AND, DL, MVT::i16,
17844 CWD, DAG.getConstant(0x400, MVT::i16)),
17845 DAG.getConstant(9, MVT::i8));
17848 DAG.getNode(ISD::AND, DL, MVT::i16,
17849 DAG.getNode(ISD::ADD, DL, MVT::i16,
17850 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17851 DAG.getConstant(1, MVT::i16)),
17852 DAG.getConstant(3, MVT::i16));
17854 return DAG.getNode((VT.getSizeInBits() < 16 ?
17855 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17858 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17859 MVT VT = Op.getSimpleValueType();
17861 unsigned NumBits = VT.getSizeInBits();
17864 Op = Op.getOperand(0);
17865 if (VT == MVT::i8) {
17866 // Zero extend to i32 since there is not an i8 bsr.
17868 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17871 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17872 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17873 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17875 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17878 DAG.getConstant(NumBits+NumBits-1, OpVT),
17879 DAG.getConstant(X86::COND_E, MVT::i8),
17882 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17884 // Finally xor with NumBits-1.
17885 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17888 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17892 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17893 MVT VT = Op.getSimpleValueType();
17895 unsigned NumBits = VT.getSizeInBits();
17898 Op = Op.getOperand(0);
17899 if (VT == MVT::i8) {
17900 // Zero extend to i32 since there is not an i8 bsr.
17902 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17905 // Issue a bsr (scan bits in reverse).
17906 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17907 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17909 // And xor with NumBits-1.
17910 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17913 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17917 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17918 MVT VT = Op.getSimpleValueType();
17919 unsigned NumBits = VT.getSizeInBits();
17921 Op = Op.getOperand(0);
17923 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17924 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17925 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17927 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17930 DAG.getConstant(NumBits, VT),
17931 DAG.getConstant(X86::COND_E, MVT::i8),
17934 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17937 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17938 // ones, and then concatenate the result back.
17939 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17940 MVT VT = Op.getSimpleValueType();
17942 assert(VT.is256BitVector() && VT.isInteger() &&
17943 "Unsupported value type for operation");
17945 unsigned NumElems = VT.getVectorNumElements();
17948 // Extract the LHS vectors
17949 SDValue LHS = Op.getOperand(0);
17950 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17951 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17953 // Extract the RHS vectors
17954 SDValue RHS = Op.getOperand(1);
17955 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17956 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17958 MVT EltVT = VT.getVectorElementType();
17959 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17961 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17962 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17963 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17966 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17967 assert(Op.getSimpleValueType().is256BitVector() &&
17968 Op.getSimpleValueType().isInteger() &&
17969 "Only handle AVX 256-bit vector integer operation");
17970 return Lower256IntArith(Op, DAG);
17973 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17974 assert(Op.getSimpleValueType().is256BitVector() &&
17975 Op.getSimpleValueType().isInteger() &&
17976 "Only handle AVX 256-bit vector integer operation");
17977 return Lower256IntArith(Op, DAG);
17980 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17981 SelectionDAG &DAG) {
17983 MVT VT = Op.getSimpleValueType();
17985 // Decompose 256-bit ops into smaller 128-bit ops.
17986 if (VT.is256BitVector() && !Subtarget->hasInt256())
17987 return Lower256IntArith(Op, DAG);
17989 SDValue A = Op.getOperand(0);
17990 SDValue B = Op.getOperand(1);
17992 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17993 if (VT == MVT::v4i32) {
17994 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17995 "Should not custom lower when pmuldq is available!");
17997 // Extract the odd parts.
17998 static const int UnpackMask[] = { 1, -1, 3, -1 };
17999 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18000 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18002 // Multiply the even parts.
18003 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18004 // Now multiply odd parts.
18005 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18007 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18008 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18010 // Merge the two vectors back together with a shuffle. This expands into 2
18012 static const int ShufMask[] = { 0, 4, 2, 6 };
18013 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18016 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18017 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18019 // Ahi = psrlqi(a, 32);
18020 // Bhi = psrlqi(b, 32);
18022 // AloBlo = pmuludq(a, b);
18023 // AloBhi = pmuludq(a, Bhi);
18024 // AhiBlo = pmuludq(Ahi, b);
18026 // AloBhi = psllqi(AloBhi, 32);
18027 // AhiBlo = psllqi(AhiBlo, 32);
18028 // return AloBlo + AloBhi + AhiBlo;
18030 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18031 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18033 // Bit cast to 32-bit vectors for MULUDQ
18034 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18035 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18036 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18037 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18038 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18039 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18041 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18042 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18043 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18045 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18046 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18048 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18049 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18052 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18053 assert(Subtarget->isTargetWin64() && "Unexpected target");
18054 EVT VT = Op.getValueType();
18055 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18056 "Unexpected return type for lowering");
18060 switch (Op->getOpcode()) {
18061 default: llvm_unreachable("Unexpected request for libcall!");
18062 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18063 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18064 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18065 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18066 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18067 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18071 SDValue InChain = DAG.getEntryNode();
18073 TargetLowering::ArgListTy Args;
18074 TargetLowering::ArgListEntry Entry;
18075 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18076 EVT ArgVT = Op->getOperand(i).getValueType();
18077 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18078 "Unexpected argument type for lowering");
18079 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18080 Entry.Node = StackPtr;
18081 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18083 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18084 Entry.Ty = PointerType::get(ArgTy,0);
18085 Entry.isSExt = false;
18086 Entry.isZExt = false;
18087 Args.push_back(Entry);
18090 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18093 TargetLowering::CallLoweringInfo CLI(DAG);
18094 CLI.setDebugLoc(dl).setChain(InChain)
18095 .setCallee(getLibcallCallingConv(LC),
18096 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18097 Callee, std::move(Args), 0)
18098 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18100 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18101 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18104 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18105 SelectionDAG &DAG) {
18106 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18107 EVT VT = Op0.getValueType();
18110 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18111 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18113 // PMULxD operations multiply each even value (starting at 0) of LHS with
18114 // the related value of RHS and produce a widen result.
18115 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18116 // => <2 x i64> <ae|cg>
18118 // In other word, to have all the results, we need to perform two PMULxD:
18119 // 1. one with the even values.
18120 // 2. one with the odd values.
18121 // To achieve #2, with need to place the odd values at an even position.
18123 // Place the odd value at an even position (basically, shift all values 1
18124 // step to the left):
18125 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18126 // <a|b|c|d> => <b|undef|d|undef>
18127 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18128 // <e|f|g|h> => <f|undef|h|undef>
18129 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18131 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18133 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18134 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18136 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18137 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18138 // => <2 x i64> <ae|cg>
18139 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18140 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18141 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18142 // => <2 x i64> <bf|dh>
18143 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18144 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18146 // Shuffle it back into the right order.
18147 SDValue Highs, Lows;
18148 if (VT == MVT::v8i32) {
18149 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18150 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18151 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18152 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18154 const int HighMask[] = {1, 5, 3, 7};
18155 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18156 const int LowMask[] = {0, 4, 2, 6};
18157 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18160 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18161 // unsigned multiply.
18162 if (IsSigned && !Subtarget->hasSSE41()) {
18164 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18165 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18166 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18167 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18168 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18170 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18171 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18174 // The first result of MUL_LOHI is actually the low value, followed by the
18176 SDValue Ops[] = {Lows, Highs};
18177 return DAG.getMergeValues(Ops, dl);
18180 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18181 const X86Subtarget *Subtarget) {
18182 MVT VT = Op.getSimpleValueType();
18184 SDValue R = Op.getOperand(0);
18185 SDValue Amt = Op.getOperand(1);
18187 // Optimize shl/srl/sra with constant shift amount.
18188 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18189 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18190 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18192 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18193 (Subtarget->hasInt256() &&
18194 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18195 (Subtarget->hasAVX512() &&
18196 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18197 if (Op.getOpcode() == ISD::SHL)
18198 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18200 if (Op.getOpcode() == ISD::SRL)
18201 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18203 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18204 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18208 if (VT == MVT::v16i8) {
18209 if (Op.getOpcode() == ISD::SHL) {
18210 // Make a large shift.
18211 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18212 MVT::v8i16, R, ShiftAmt,
18214 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18215 // Zero out the rightmost bits.
18216 SmallVector<SDValue, 16> V(16,
18217 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18219 return DAG.getNode(ISD::AND, dl, VT, SHL,
18220 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18222 if (Op.getOpcode() == ISD::SRL) {
18223 // Make a large shift.
18224 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18225 MVT::v8i16, R, ShiftAmt,
18227 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18228 // Zero out the leftmost bits.
18229 SmallVector<SDValue, 16> V(16,
18230 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18232 return DAG.getNode(ISD::AND, dl, VT, SRL,
18233 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18235 if (Op.getOpcode() == ISD::SRA) {
18236 if (ShiftAmt == 7) {
18237 // R s>> 7 === R s< 0
18238 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18239 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18242 // R s>> a === ((R u>> a) ^ m) - m
18243 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18244 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18246 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18247 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18248 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18251 llvm_unreachable("Unknown shift opcode.");
18254 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18255 if (Op.getOpcode() == ISD::SHL) {
18256 // Make a large shift.
18257 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18258 MVT::v16i16, R, ShiftAmt,
18260 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18261 // Zero out the rightmost bits.
18262 SmallVector<SDValue, 32> V(32,
18263 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18265 return DAG.getNode(ISD::AND, dl, VT, SHL,
18266 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18268 if (Op.getOpcode() == ISD::SRL) {
18269 // Make a large shift.
18270 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18271 MVT::v16i16, R, ShiftAmt,
18273 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18274 // Zero out the leftmost bits.
18275 SmallVector<SDValue, 32> V(32,
18276 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18278 return DAG.getNode(ISD::AND, dl, VT, SRL,
18279 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18281 if (Op.getOpcode() == ISD::SRA) {
18282 if (ShiftAmt == 7) {
18283 // R s>> 7 === R s< 0
18284 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18285 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18288 // R s>> a === ((R u>> a) ^ m) - m
18289 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18290 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18292 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18293 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18294 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18297 llvm_unreachable("Unknown shift opcode.");
18302 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18303 if (!Subtarget->is64Bit() &&
18304 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18305 Amt.getOpcode() == ISD::BITCAST &&
18306 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18307 Amt = Amt.getOperand(0);
18308 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18309 VT.getVectorNumElements();
18310 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18311 uint64_t ShiftAmt = 0;
18312 for (unsigned i = 0; i != Ratio; ++i) {
18313 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18317 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18319 // Check remaining shift amounts.
18320 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18321 uint64_t ShAmt = 0;
18322 for (unsigned j = 0; j != Ratio; ++j) {
18323 ConstantSDNode *C =
18324 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18328 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18330 if (ShAmt != ShiftAmt)
18333 switch (Op.getOpcode()) {
18335 llvm_unreachable("Unknown shift opcode!");
18337 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18340 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18343 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18351 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18352 const X86Subtarget* Subtarget) {
18353 MVT VT = Op.getSimpleValueType();
18355 SDValue R = Op.getOperand(0);
18356 SDValue Amt = Op.getOperand(1);
18358 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18359 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18360 (Subtarget->hasInt256() &&
18361 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18362 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18363 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18365 EVT EltVT = VT.getVectorElementType();
18367 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18368 // Check if this build_vector node is doing a splat.
18369 // If so, then set BaseShAmt equal to the splat value.
18370 BaseShAmt = BV->getSplatValue();
18371 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18372 BaseShAmt = SDValue();
18374 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18375 Amt = Amt.getOperand(0);
18377 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18378 if (SVN && SVN->isSplat()) {
18379 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18380 SDValue InVec = Amt.getOperand(0);
18381 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18382 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18383 "Unexpected shuffle index found!");
18384 BaseShAmt = InVec.getOperand(SplatIdx);
18385 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18386 if (ConstantSDNode *C =
18387 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18388 if (C->getZExtValue() == SplatIdx)
18389 BaseShAmt = InVec.getOperand(1);
18394 // Avoid introducing an extract element from a shuffle.
18395 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18396 DAG.getIntPtrConstant(SplatIdx));
18400 if (BaseShAmt.getNode()) {
18401 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18402 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18403 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18404 else if (EltVT.bitsLT(MVT::i32))
18405 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18407 switch (Op.getOpcode()) {
18409 llvm_unreachable("Unknown shift opcode!");
18411 switch (VT.SimpleTy) {
18412 default: return SDValue();
18421 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18424 switch (VT.SimpleTy) {
18425 default: return SDValue();
18432 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18435 switch (VT.SimpleTy) {
18436 default: return SDValue();
18445 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18451 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18452 if (!Subtarget->is64Bit() &&
18453 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18454 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18455 Amt.getOpcode() == ISD::BITCAST &&
18456 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18457 Amt = Amt.getOperand(0);
18458 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18459 VT.getVectorNumElements();
18460 std::vector<SDValue> Vals(Ratio);
18461 for (unsigned i = 0; i != Ratio; ++i)
18462 Vals[i] = Amt.getOperand(i);
18463 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18464 for (unsigned j = 0; j != Ratio; ++j)
18465 if (Vals[j] != Amt.getOperand(i + j))
18468 switch (Op.getOpcode()) {
18470 llvm_unreachable("Unknown shift opcode!");
18472 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18474 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18476 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18483 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18484 SelectionDAG &DAG) {
18485 MVT VT = Op.getSimpleValueType();
18487 SDValue R = Op.getOperand(0);
18488 SDValue Amt = Op.getOperand(1);
18491 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18492 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18494 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18498 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18502 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18504 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18505 if (Subtarget->hasInt256()) {
18506 if (Op.getOpcode() == ISD::SRL &&
18507 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18508 VT == MVT::v4i64 || VT == MVT::v8i32))
18510 if (Op.getOpcode() == ISD::SHL &&
18511 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18512 VT == MVT::v4i64 || VT == MVT::v8i32))
18514 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18518 // If possible, lower this packed shift into a vector multiply instead of
18519 // expanding it into a sequence of scalar shifts.
18520 // Do this only if the vector shift count is a constant build_vector.
18521 if (Op.getOpcode() == ISD::SHL &&
18522 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18523 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18524 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18525 SmallVector<SDValue, 8> Elts;
18526 EVT SVT = VT.getScalarType();
18527 unsigned SVTBits = SVT.getSizeInBits();
18528 const APInt &One = APInt(SVTBits, 1);
18529 unsigned NumElems = VT.getVectorNumElements();
18531 for (unsigned i=0; i !=NumElems; ++i) {
18532 SDValue Op = Amt->getOperand(i);
18533 if (Op->getOpcode() == ISD::UNDEF) {
18534 Elts.push_back(Op);
18538 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18539 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18540 uint64_t ShAmt = C.getZExtValue();
18541 if (ShAmt >= SVTBits) {
18542 Elts.push_back(DAG.getUNDEF(SVT));
18545 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18547 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18548 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18551 // Lower SHL with variable shift amount.
18552 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18553 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18555 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18556 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18557 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18558 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18561 // If possible, lower this shift as a sequence of two shifts by
18562 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18564 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18566 // Could be rewritten as:
18567 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18569 // The advantage is that the two shifts from the example would be
18570 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18571 // the vector shift into four scalar shifts plus four pairs of vector
18573 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18574 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18575 unsigned TargetOpcode = X86ISD::MOVSS;
18576 bool CanBeSimplified;
18577 // The splat value for the first packed shift (the 'X' from the example).
18578 SDValue Amt1 = Amt->getOperand(0);
18579 // The splat value for the second packed shift (the 'Y' from the example).
18580 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18581 Amt->getOperand(2);
18583 // See if it is possible to replace this node with a sequence of
18584 // two shifts followed by a MOVSS/MOVSD
18585 if (VT == MVT::v4i32) {
18586 // Check if it is legal to use a MOVSS.
18587 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18588 Amt2 == Amt->getOperand(3);
18589 if (!CanBeSimplified) {
18590 // Otherwise, check if we can still simplify this node using a MOVSD.
18591 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18592 Amt->getOperand(2) == Amt->getOperand(3);
18593 TargetOpcode = X86ISD::MOVSD;
18594 Amt2 = Amt->getOperand(2);
18597 // Do similar checks for the case where the machine value type
18599 CanBeSimplified = Amt1 == Amt->getOperand(1);
18600 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18601 CanBeSimplified = Amt2 == Amt->getOperand(i);
18603 if (!CanBeSimplified) {
18604 TargetOpcode = X86ISD::MOVSD;
18605 CanBeSimplified = true;
18606 Amt2 = Amt->getOperand(4);
18607 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18608 CanBeSimplified = Amt1 == Amt->getOperand(i);
18609 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18610 CanBeSimplified = Amt2 == Amt->getOperand(j);
18614 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18615 isa<ConstantSDNode>(Amt2)) {
18616 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18617 EVT CastVT = MVT::v4i32;
18619 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18620 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18622 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18623 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18624 if (TargetOpcode == X86ISD::MOVSD)
18625 CastVT = MVT::v2i64;
18626 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18627 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18628 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18630 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18634 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18635 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18638 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18639 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18641 // Turn 'a' into a mask suitable for VSELECT
18642 SDValue VSelM = DAG.getConstant(0x80, VT);
18643 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18644 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18646 SDValue CM1 = DAG.getConstant(0x0f, VT);
18647 SDValue CM2 = DAG.getConstant(0x3f, VT);
18649 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18650 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18651 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18652 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18653 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18656 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18657 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18658 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18660 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18661 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18662 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18663 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18664 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18667 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18668 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18669 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18671 // return VSELECT(r, r+r, a);
18672 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18673 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18677 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18678 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18679 // solution better.
18680 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18681 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18683 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18684 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18685 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18686 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18687 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18690 // Decompose 256-bit shifts into smaller 128-bit shifts.
18691 if (VT.is256BitVector()) {
18692 unsigned NumElems = VT.getVectorNumElements();
18693 MVT EltVT = VT.getVectorElementType();
18694 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18696 // Extract the two vectors
18697 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18698 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18700 // Recreate the shift amount vectors
18701 SDValue Amt1, Amt2;
18702 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18703 // Constant shift amount
18704 SmallVector<SDValue, 4> Amt1Csts;
18705 SmallVector<SDValue, 4> Amt2Csts;
18706 for (unsigned i = 0; i != NumElems/2; ++i)
18707 Amt1Csts.push_back(Amt->getOperand(i));
18708 for (unsigned i = NumElems/2; i != NumElems; ++i)
18709 Amt2Csts.push_back(Amt->getOperand(i));
18711 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18712 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18714 // Variable shift amount
18715 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18716 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18719 // Issue new vector shifts for the smaller types
18720 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18721 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18723 // Concatenate the result back
18724 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18730 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18731 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18732 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18733 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18734 // has only one use.
18735 SDNode *N = Op.getNode();
18736 SDValue LHS = N->getOperand(0);
18737 SDValue RHS = N->getOperand(1);
18738 unsigned BaseOp = 0;
18741 switch (Op.getOpcode()) {
18742 default: llvm_unreachable("Unknown ovf instruction!");
18744 // A subtract of one will be selected as a INC. Note that INC doesn't
18745 // set CF, so we can't do this for UADDO.
18746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18748 BaseOp = X86ISD::INC;
18749 Cond = X86::COND_O;
18752 BaseOp = X86ISD::ADD;
18753 Cond = X86::COND_O;
18756 BaseOp = X86ISD::ADD;
18757 Cond = X86::COND_B;
18760 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18761 // set CF, so we can't do this for USUBO.
18762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18764 BaseOp = X86ISD::DEC;
18765 Cond = X86::COND_O;
18768 BaseOp = X86ISD::SUB;
18769 Cond = X86::COND_O;
18772 BaseOp = X86ISD::SUB;
18773 Cond = X86::COND_B;
18776 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18777 Cond = X86::COND_O;
18779 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18780 if (N->getValueType(0) == MVT::i8) {
18781 BaseOp = X86ISD::UMUL8;
18782 Cond = X86::COND_O;
18785 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18787 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18790 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18791 DAG.getConstant(X86::COND_O, MVT::i32),
18792 SDValue(Sum.getNode(), 2));
18794 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18798 // Also sets EFLAGS.
18799 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18800 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18803 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18804 DAG.getConstant(Cond, MVT::i32),
18805 SDValue(Sum.getNode(), 1));
18807 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18810 // Sign extension of the low part of vector elements. This may be used either
18811 // when sign extend instructions are not available or if the vector element
18812 // sizes already match the sign-extended size. If the vector elements are in
18813 // their pre-extended size and sign extend instructions are available, that will
18814 // be handled by LowerSIGN_EXTEND.
18815 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18816 SelectionDAG &DAG) const {
18818 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18819 MVT VT = Op.getSimpleValueType();
18821 if (!Subtarget->hasSSE2() || !VT.isVector())
18824 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18825 ExtraVT.getScalarType().getSizeInBits();
18827 switch (VT.SimpleTy) {
18828 default: return SDValue();
18831 if (!Subtarget->hasFp256())
18833 if (!Subtarget->hasInt256()) {
18834 // needs to be split
18835 unsigned NumElems = VT.getVectorNumElements();
18837 // Extract the LHS vectors
18838 SDValue LHS = Op.getOperand(0);
18839 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18840 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18842 MVT EltVT = VT.getVectorElementType();
18843 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18845 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18846 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18847 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18849 SDValue Extra = DAG.getValueType(ExtraVT);
18851 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18852 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18854 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18859 SDValue Op0 = Op.getOperand(0);
18861 // This is a sign extension of some low part of vector elements without
18862 // changing the size of the vector elements themselves:
18863 // Shift-Left + Shift-Right-Algebraic.
18864 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18866 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18872 /// Returns true if the operand type is exactly twice the native width, and
18873 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18874 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18875 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18876 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18877 const X86Subtarget &Subtarget =
18878 getTargetMachine().getSubtarget<X86Subtarget>();
18879 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18882 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18883 else if (OpWidth == 128)
18884 return Subtarget.hasCmpxchg16b();
18889 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18890 return needsCmpXchgNb(SI->getValueOperand()->getType());
18893 // Note: this turns large loads into lock cmpxchg8b/16b.
18894 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18895 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18896 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18897 return needsCmpXchgNb(PTy->getElementType());
18900 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18901 const X86Subtarget &Subtarget =
18902 getTargetMachine().getSubtarget<X86Subtarget>();
18903 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18904 const Type *MemType = AI->getType();
18906 // If the operand is too big, we must see if cmpxchg8/16b is available
18907 // and default to library calls otherwise.
18908 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18909 return needsCmpXchgNb(MemType);
18911 AtomicRMWInst::BinOp Op = AI->getOperation();
18914 llvm_unreachable("Unknown atomic operation");
18915 case AtomicRMWInst::Xchg:
18916 case AtomicRMWInst::Add:
18917 case AtomicRMWInst::Sub:
18918 // It's better to use xadd, xsub or xchg for these in all cases.
18920 case AtomicRMWInst::Or:
18921 case AtomicRMWInst::And:
18922 case AtomicRMWInst::Xor:
18923 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18924 // prefix to a normal instruction for these operations.
18925 return !AI->use_empty();
18926 case AtomicRMWInst::Nand:
18927 case AtomicRMWInst::Max:
18928 case AtomicRMWInst::Min:
18929 case AtomicRMWInst::UMax:
18930 case AtomicRMWInst::UMin:
18931 // These always require a non-trivial set of data operations on x86. We must
18932 // use a cmpxchg loop.
18937 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18938 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18939 // no-sse2). There isn't any reason to disable it if the target processor
18941 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18945 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18946 const X86Subtarget &Subtarget =
18947 getTargetMachine().getSubtarget<X86Subtarget>();
18948 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18949 const Type *MemType = AI->getType();
18950 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18951 // there is no benefit in turning such RMWs into loads, and it is actually
18952 // harmful as it introduces a mfence.
18953 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18956 auto Builder = IRBuilder<>(AI);
18957 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18958 auto SynchScope = AI->getSynchScope();
18959 // We must restrict the ordering to avoid generating loads with Release or
18960 // ReleaseAcquire orderings.
18961 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18962 auto Ptr = AI->getPointerOperand();
18964 // Before the load we need a fence. Here is an example lifted from
18965 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18968 // x.store(1, relaxed);
18969 // r1 = y.fetch_add(0, release);
18971 // y.fetch_add(42, acquire);
18972 // r2 = x.load(relaxed);
18973 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18974 // lowered to just a load without a fence. A mfence flushes the store buffer,
18975 // making the optimization clearly correct.
18976 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18977 // otherwise, we might be able to be more agressive on relaxed idempotent
18978 // rmw. In practice, they do not look useful, so we don't try to be
18979 // especially clever.
18980 if (SynchScope == SingleThread) {
18981 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18982 // the IR level, so we must wrap it in an intrinsic.
18984 } else if (hasMFENCE(Subtarget)) {
18985 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18986 Intrinsic::x86_sse2_mfence);
18987 Builder.CreateCall(MFence);
18989 // FIXME: it might make sense to use a locked operation here but on a
18990 // different cache-line to prevent cache-line bouncing. In practice it
18991 // is probably a small win, and x86 processors without mfence are rare
18992 // enough that we do not bother.
18996 // Finally we can emit the atomic load.
18997 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18998 AI->getType()->getPrimitiveSizeInBits());
18999 Loaded->setAtomic(Order, SynchScope);
19000 AI->replaceAllUsesWith(Loaded);
19001 AI->eraseFromParent();
19005 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19006 SelectionDAG &DAG) {
19008 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19009 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19010 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19011 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19013 // The only fence that needs an instruction is a sequentially-consistent
19014 // cross-thread fence.
19015 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19016 if (hasMFENCE(*Subtarget))
19017 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19019 SDValue Chain = Op.getOperand(0);
19020 SDValue Zero = DAG.getConstant(0, MVT::i32);
19022 DAG.getRegister(X86::ESP, MVT::i32), // Base
19023 DAG.getTargetConstant(1, MVT::i8), // Scale
19024 DAG.getRegister(0, MVT::i32), // Index
19025 DAG.getTargetConstant(0, MVT::i32), // Disp
19026 DAG.getRegister(0, MVT::i32), // Segment.
19030 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19031 return SDValue(Res, 0);
19034 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19035 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19038 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19039 SelectionDAG &DAG) {
19040 MVT T = Op.getSimpleValueType();
19044 switch(T.SimpleTy) {
19045 default: llvm_unreachable("Invalid value type!");
19046 case MVT::i8: Reg = X86::AL; size = 1; break;
19047 case MVT::i16: Reg = X86::AX; size = 2; break;
19048 case MVT::i32: Reg = X86::EAX; size = 4; break;
19050 assert(Subtarget->is64Bit() && "Node not type legal!");
19051 Reg = X86::RAX; size = 8;
19054 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19055 Op.getOperand(2), SDValue());
19056 SDValue Ops[] = { cpIn.getValue(0),
19059 DAG.getTargetConstant(size, MVT::i8),
19060 cpIn.getValue(1) };
19061 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19062 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19063 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19067 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19068 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19069 MVT::i32, cpOut.getValue(2));
19070 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19071 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19073 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19074 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19075 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19079 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19080 SelectionDAG &DAG) {
19081 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19082 MVT DstVT = Op.getSimpleValueType();
19084 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19085 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19086 if (DstVT != MVT::f64)
19087 // This conversion needs to be expanded.
19090 SDValue InVec = Op->getOperand(0);
19092 unsigned NumElts = SrcVT.getVectorNumElements();
19093 EVT SVT = SrcVT.getVectorElementType();
19095 // Widen the vector in input in the case of MVT::v2i32.
19096 // Example: from MVT::v2i32 to MVT::v4i32.
19097 SmallVector<SDValue, 16> Elts;
19098 for (unsigned i = 0, e = NumElts; i != e; ++i)
19099 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19100 DAG.getIntPtrConstant(i)));
19102 // Explicitly mark the extra elements as Undef.
19103 SDValue Undef = DAG.getUNDEF(SVT);
19104 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19105 Elts.push_back(Undef);
19107 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19108 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19109 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19110 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19111 DAG.getIntPtrConstant(0));
19114 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19115 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19116 assert((DstVT == MVT::i64 ||
19117 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19118 "Unexpected custom BITCAST");
19119 // i64 <=> MMX conversions are Legal.
19120 if (SrcVT==MVT::i64 && DstVT.isVector())
19122 if (DstVT==MVT::i64 && SrcVT.isVector())
19124 // MMX <=> MMX conversions are Legal.
19125 if (SrcVT.isVector() && DstVT.isVector())
19127 // All other conversions need to be expanded.
19131 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19132 SDNode *Node = Op.getNode();
19134 EVT T = Node->getValueType(0);
19135 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19136 DAG.getConstant(0, T), Node->getOperand(2));
19137 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19138 cast<AtomicSDNode>(Node)->getMemoryVT(),
19139 Node->getOperand(0),
19140 Node->getOperand(1), negOp,
19141 cast<AtomicSDNode>(Node)->getMemOperand(),
19142 cast<AtomicSDNode>(Node)->getOrdering(),
19143 cast<AtomicSDNode>(Node)->getSynchScope());
19146 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19147 SDNode *Node = Op.getNode();
19149 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19151 // Convert seq_cst store -> xchg
19152 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19153 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19154 // (The only way to get a 16-byte store is cmpxchg16b)
19155 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19156 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19157 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19158 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19159 cast<AtomicSDNode>(Node)->getMemoryVT(),
19160 Node->getOperand(0),
19161 Node->getOperand(1), Node->getOperand(2),
19162 cast<AtomicSDNode>(Node)->getMemOperand(),
19163 cast<AtomicSDNode>(Node)->getOrdering(),
19164 cast<AtomicSDNode>(Node)->getSynchScope());
19165 return Swap.getValue(1);
19167 // Other atomic stores have a simple pattern.
19171 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19172 EVT VT = Op.getNode()->getSimpleValueType(0);
19174 // Let legalize expand this if it isn't a legal type yet.
19175 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19178 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19181 bool ExtraOp = false;
19182 switch (Op.getOpcode()) {
19183 default: llvm_unreachable("Invalid code");
19184 case ISD::ADDC: Opc = X86ISD::ADD; break;
19185 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19186 case ISD::SUBC: Opc = X86ISD::SUB; break;
19187 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19191 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19193 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19194 Op.getOperand(1), Op.getOperand(2));
19197 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19198 SelectionDAG &DAG) {
19199 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19201 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19202 // which returns the values as { float, float } (in XMM0) or
19203 // { double, double } (which is returned in XMM0, XMM1).
19205 SDValue Arg = Op.getOperand(0);
19206 EVT ArgVT = Arg.getValueType();
19207 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19209 TargetLowering::ArgListTy Args;
19210 TargetLowering::ArgListEntry Entry;
19214 Entry.isSExt = false;
19215 Entry.isZExt = false;
19216 Args.push_back(Entry);
19218 bool isF64 = ArgVT == MVT::f64;
19219 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19220 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19221 // the results are returned via SRet in memory.
19222 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19223 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19224 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19226 Type *RetTy = isF64
19227 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19228 : (Type*)VectorType::get(ArgTy, 4);
19230 TargetLowering::CallLoweringInfo CLI(DAG);
19231 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19232 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19234 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19237 // Returned in xmm0 and xmm1.
19238 return CallResult.first;
19240 // Returned in bits 0:31 and 32:64 xmm0.
19241 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19242 CallResult.first, DAG.getIntPtrConstant(0));
19243 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19244 CallResult.first, DAG.getIntPtrConstant(1));
19245 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19246 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19249 /// LowerOperation - Provide custom lowering hooks for some operations.
19251 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19252 switch (Op.getOpcode()) {
19253 default: llvm_unreachable("Should not custom lower this!");
19254 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19255 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19256 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19257 return LowerCMP_SWAP(Op, Subtarget, DAG);
19258 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19259 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19260 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19261 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19262 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19263 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19264 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19265 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19266 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19267 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19268 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19269 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19270 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19271 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19272 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19273 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19274 case ISD::SHL_PARTS:
19275 case ISD::SRA_PARTS:
19276 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19277 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19278 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19279 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19280 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19281 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19282 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19283 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19284 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19285 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19286 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19288 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19289 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19290 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19291 case ISD::SETCC: return LowerSETCC(Op, DAG);
19292 case ISD::SELECT: return LowerSELECT(Op, DAG);
19293 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19294 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19295 case ISD::VASTART: return LowerVASTART(Op, DAG);
19296 case ISD::VAARG: return LowerVAARG(Op, DAG);
19297 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19298 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19299 case ISD::INTRINSIC_VOID:
19300 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19301 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19302 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19303 case ISD::FRAME_TO_ARGS_OFFSET:
19304 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19305 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19306 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19307 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19308 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19309 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19310 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19311 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19312 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19313 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19314 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19315 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19316 case ISD::UMUL_LOHI:
19317 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19320 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19326 case ISD::UMULO: return LowerXALUO(Op, DAG);
19327 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19328 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19332 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19333 case ISD::ADD: return LowerADD(Op, DAG);
19334 case ISD::SUB: return LowerSUB(Op, DAG);
19335 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19339 /// ReplaceNodeResults - Replace a node with an illegal result type
19340 /// with a new node built out of custom code.
19341 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19342 SmallVectorImpl<SDValue>&Results,
19343 SelectionDAG &DAG) const {
19345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19346 switch (N->getOpcode()) {
19348 llvm_unreachable("Do not know how to custom type legalize this operation!");
19349 case ISD::SIGN_EXTEND_INREG:
19354 // We don't want to expand or promote these.
19361 case ISD::UDIVREM: {
19362 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19363 Results.push_back(V);
19366 case ISD::FP_TO_SINT:
19367 case ISD::FP_TO_UINT: {
19368 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19370 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19373 std::pair<SDValue,SDValue> Vals =
19374 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19375 SDValue FIST = Vals.first, StackSlot = Vals.second;
19376 if (FIST.getNode()) {
19377 EVT VT = N->getValueType(0);
19378 // Return a load from the stack slot.
19379 if (StackSlot.getNode())
19380 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19381 MachinePointerInfo(),
19382 false, false, false, 0));
19384 Results.push_back(FIST);
19388 case ISD::UINT_TO_FP: {
19389 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19390 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19391 N->getValueType(0) != MVT::v2f32)
19393 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19395 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19397 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19398 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19399 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19400 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19401 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19402 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19405 case ISD::FP_ROUND: {
19406 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19408 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19409 Results.push_back(V);
19412 case ISD::INTRINSIC_W_CHAIN: {
19413 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19415 default : llvm_unreachable("Do not know how to custom type "
19416 "legalize this intrinsic operation!");
19417 case Intrinsic::x86_rdtsc:
19418 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19420 case Intrinsic::x86_rdtscp:
19421 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19423 case Intrinsic::x86_rdpmc:
19424 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19427 case ISD::READCYCLECOUNTER: {
19428 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19431 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19432 EVT T = N->getValueType(0);
19433 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19434 bool Regs64bit = T == MVT::i128;
19435 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19436 SDValue cpInL, cpInH;
19437 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19438 DAG.getConstant(0, HalfT));
19439 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19440 DAG.getConstant(1, HalfT));
19441 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19442 Regs64bit ? X86::RAX : X86::EAX,
19444 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19445 Regs64bit ? X86::RDX : X86::EDX,
19446 cpInH, cpInL.getValue(1));
19447 SDValue swapInL, swapInH;
19448 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19449 DAG.getConstant(0, HalfT));
19450 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19451 DAG.getConstant(1, HalfT));
19452 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19453 Regs64bit ? X86::RBX : X86::EBX,
19454 swapInL, cpInH.getValue(1));
19455 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19456 Regs64bit ? X86::RCX : X86::ECX,
19457 swapInH, swapInL.getValue(1));
19458 SDValue Ops[] = { swapInH.getValue(0),
19460 swapInH.getValue(1) };
19461 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19462 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19463 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19464 X86ISD::LCMPXCHG8_DAG;
19465 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19466 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19467 Regs64bit ? X86::RAX : X86::EAX,
19468 HalfT, Result.getValue(1));
19469 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19470 Regs64bit ? X86::RDX : X86::EDX,
19471 HalfT, cpOutL.getValue(2));
19472 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19474 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19475 MVT::i32, cpOutH.getValue(2));
19477 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19478 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19479 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19481 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19482 Results.push_back(Success);
19483 Results.push_back(EFLAGS.getValue(1));
19486 case ISD::ATOMIC_SWAP:
19487 case ISD::ATOMIC_LOAD_ADD:
19488 case ISD::ATOMIC_LOAD_SUB:
19489 case ISD::ATOMIC_LOAD_AND:
19490 case ISD::ATOMIC_LOAD_OR:
19491 case ISD::ATOMIC_LOAD_XOR:
19492 case ISD::ATOMIC_LOAD_NAND:
19493 case ISD::ATOMIC_LOAD_MIN:
19494 case ISD::ATOMIC_LOAD_MAX:
19495 case ISD::ATOMIC_LOAD_UMIN:
19496 case ISD::ATOMIC_LOAD_UMAX:
19497 case ISD::ATOMIC_LOAD: {
19498 // Delegate to generic TypeLegalization. Situations we can really handle
19499 // should have already been dealt with by AtomicExpandPass.cpp.
19502 case ISD::BITCAST: {
19503 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19504 EVT DstVT = N->getValueType(0);
19505 EVT SrcVT = N->getOperand(0)->getValueType(0);
19507 if (SrcVT != MVT::f64 ||
19508 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19511 unsigned NumElts = DstVT.getVectorNumElements();
19512 EVT SVT = DstVT.getVectorElementType();
19513 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19514 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19515 MVT::v2f64, N->getOperand(0));
19516 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19518 if (ExperimentalVectorWideningLegalization) {
19519 // If we are legalizing vectors by widening, we already have the desired
19520 // legal vector type, just return it.
19521 Results.push_back(ToVecInt);
19525 SmallVector<SDValue, 8> Elts;
19526 for (unsigned i = 0, e = NumElts; i != e; ++i)
19527 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19528 ToVecInt, DAG.getIntPtrConstant(i)));
19530 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19535 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19537 default: return nullptr;
19538 case X86ISD::BSF: return "X86ISD::BSF";
19539 case X86ISD::BSR: return "X86ISD::BSR";
19540 case X86ISD::SHLD: return "X86ISD::SHLD";
19541 case X86ISD::SHRD: return "X86ISD::SHRD";
19542 case X86ISD::FAND: return "X86ISD::FAND";
19543 case X86ISD::FANDN: return "X86ISD::FANDN";
19544 case X86ISD::FOR: return "X86ISD::FOR";
19545 case X86ISD::FXOR: return "X86ISD::FXOR";
19546 case X86ISD::FSRL: return "X86ISD::FSRL";
19547 case X86ISD::FILD: return "X86ISD::FILD";
19548 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19549 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19550 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19551 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19552 case X86ISD::FLD: return "X86ISD::FLD";
19553 case X86ISD::FST: return "X86ISD::FST";
19554 case X86ISD::CALL: return "X86ISD::CALL";
19555 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19556 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19557 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19558 case X86ISD::BT: return "X86ISD::BT";
19559 case X86ISD::CMP: return "X86ISD::CMP";
19560 case X86ISD::COMI: return "X86ISD::COMI";
19561 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19562 case X86ISD::CMPM: return "X86ISD::CMPM";
19563 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19564 case X86ISD::SETCC: return "X86ISD::SETCC";
19565 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19566 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19567 case X86ISD::CMOV: return "X86ISD::CMOV";
19568 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19569 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19570 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19571 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19572 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19573 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19574 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19575 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19576 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19577 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19578 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19579 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19580 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19581 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19582 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19583 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19584 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19585 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19586 case X86ISD::HADD: return "X86ISD::HADD";
19587 case X86ISD::HSUB: return "X86ISD::HSUB";
19588 case X86ISD::FHADD: return "X86ISD::FHADD";
19589 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19590 case X86ISD::UMAX: return "X86ISD::UMAX";
19591 case X86ISD::UMIN: return "X86ISD::UMIN";
19592 case X86ISD::SMAX: return "X86ISD::SMAX";
19593 case X86ISD::SMIN: return "X86ISD::SMIN";
19594 case X86ISD::FMAX: return "X86ISD::FMAX";
19595 case X86ISD::FMIN: return "X86ISD::FMIN";
19596 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19597 case X86ISD::FMINC: return "X86ISD::FMINC";
19598 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19599 case X86ISD::FRCP: return "X86ISD::FRCP";
19600 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19601 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19602 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19603 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19604 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19605 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19606 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19607 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19608 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19609 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19610 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19611 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19612 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19613 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19614 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19615 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19616 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19617 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19618 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19619 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19620 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19621 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19622 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19623 case X86ISD::VSHL: return "X86ISD::VSHL";
19624 case X86ISD::VSRL: return "X86ISD::VSRL";
19625 case X86ISD::VSRA: return "X86ISD::VSRA";
19626 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19627 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19628 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19629 case X86ISD::CMPP: return "X86ISD::CMPP";
19630 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19631 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19632 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19633 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19634 case X86ISD::ADD: return "X86ISD::ADD";
19635 case X86ISD::SUB: return "X86ISD::SUB";
19636 case X86ISD::ADC: return "X86ISD::ADC";
19637 case X86ISD::SBB: return "X86ISD::SBB";
19638 case X86ISD::SMUL: return "X86ISD::SMUL";
19639 case X86ISD::UMUL: return "X86ISD::UMUL";
19640 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19641 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19642 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19643 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19644 case X86ISD::INC: return "X86ISD::INC";
19645 case X86ISD::DEC: return "X86ISD::DEC";
19646 case X86ISD::OR: return "X86ISD::OR";
19647 case X86ISD::XOR: return "X86ISD::XOR";
19648 case X86ISD::AND: return "X86ISD::AND";
19649 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19650 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19651 case X86ISD::PTEST: return "X86ISD::PTEST";
19652 case X86ISD::TESTP: return "X86ISD::TESTP";
19653 case X86ISD::TESTM: return "X86ISD::TESTM";
19654 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19655 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19656 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19657 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19658 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19659 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19660 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19661 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19662 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19663 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19664 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19665 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19666 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19667 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19668 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19669 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19670 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19671 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19672 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19673 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19674 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19675 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19676 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19677 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19678 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19679 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19680 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19681 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19682 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19683 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19684 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19685 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19686 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19687 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19688 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19689 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19690 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19691 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19692 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19693 case X86ISD::SAHF: return "X86ISD::SAHF";
19694 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19695 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19696 case X86ISD::FMADD: return "X86ISD::FMADD";
19697 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19698 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19699 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19700 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19701 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19702 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19703 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19704 case X86ISD::XTEST: return "X86ISD::XTEST";
19705 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19709 // isLegalAddressingMode - Return true if the addressing mode represented
19710 // by AM is legal for this target, for a load/store of the specified type.
19711 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19713 // X86 supports extremely general addressing modes.
19714 CodeModel::Model M = getTargetMachine().getCodeModel();
19715 Reloc::Model R = getTargetMachine().getRelocationModel();
19717 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19718 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19723 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19725 // If a reference to this global requires an extra load, we can't fold it.
19726 if (isGlobalStubReference(GVFlags))
19729 // If BaseGV requires a register for the PIC base, we cannot also have a
19730 // BaseReg specified.
19731 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19734 // If lower 4G is not available, then we must use rip-relative addressing.
19735 if ((M != CodeModel::Small || R != Reloc::Static) &&
19736 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19740 switch (AM.Scale) {
19746 // These scales always work.
19751 // These scales are formed with basereg+scalereg. Only accept if there is
19756 default: // Other stuff never works.
19763 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19764 unsigned Bits = Ty->getScalarSizeInBits();
19766 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19767 // particularly cheaper than those without.
19771 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19772 // variable shifts just as cheap as scalar ones.
19773 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19776 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19777 // fully general vector.
19781 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19782 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19784 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19785 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19786 return NumBits1 > NumBits2;
19789 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19790 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19793 if (!isTypeLegal(EVT::getEVT(Ty1)))
19796 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19798 // Assuming the caller doesn't have a zeroext or signext return parameter,
19799 // truncation all the way down to i1 is valid.
19803 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19804 return isInt<32>(Imm);
19807 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19808 // Can also use sub to handle negated immediates.
19809 return isInt<32>(Imm);
19812 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19813 if (!VT1.isInteger() || !VT2.isInteger())
19815 unsigned NumBits1 = VT1.getSizeInBits();
19816 unsigned NumBits2 = VT2.getSizeInBits();
19817 return NumBits1 > NumBits2;
19820 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19821 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19822 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19825 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19826 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19827 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19830 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19831 EVT VT1 = Val.getValueType();
19832 if (isZExtFree(VT1, VT2))
19835 if (Val.getOpcode() != ISD::LOAD)
19838 if (!VT1.isSimple() || !VT1.isInteger() ||
19839 !VT2.isSimple() || !VT2.isInteger())
19842 switch (VT1.getSimpleVT().SimpleTy) {
19847 // X86 has 8, 16, and 32-bit zero-extending loads.
19855 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19856 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19859 VT = VT.getScalarType();
19861 if (!VT.isSimple())
19864 switch (VT.getSimpleVT().SimpleTy) {
19875 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19876 // i16 instructions are longer (0x66 prefix) and potentially slower.
19877 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19880 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19881 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19882 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19883 /// are assumed to be legal.
19885 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19887 if (!VT.isSimple())
19890 MVT SVT = VT.getSimpleVT();
19892 // Very little shuffling can be done for 64-bit vectors right now.
19893 if (VT.getSizeInBits() == 64)
19896 // If this is a single-input shuffle with no 128 bit lane crossings we can
19897 // lower it into pshufb.
19898 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19899 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19900 bool isLegal = true;
19901 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19902 if (M[I] >= (int)SVT.getVectorNumElements() ||
19903 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19912 // FIXME: blends, shifts.
19913 return (SVT.getVectorNumElements() == 2 ||
19914 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19915 isMOVLMask(M, SVT) ||
19916 isCommutedMOVLMask(M, SVT) ||
19917 isMOVHLPSMask(M, SVT) ||
19918 isSHUFPMask(M, SVT) ||
19919 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19920 isPSHUFDMask(M, SVT) ||
19921 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19922 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19923 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19924 isPALIGNRMask(M, SVT, Subtarget) ||
19925 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19926 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19927 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19928 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19929 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19930 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19934 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19936 if (!VT.isSimple())
19939 MVT SVT = VT.getSimpleVT();
19940 unsigned NumElts = SVT.getVectorNumElements();
19941 // FIXME: This collection of masks seems suspect.
19944 if (NumElts == 4 && SVT.is128BitVector()) {
19945 return (isMOVLMask(Mask, SVT) ||
19946 isCommutedMOVLMask(Mask, SVT, true) ||
19947 isSHUFPMask(Mask, SVT) ||
19948 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19949 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19950 Subtarget->hasInt256()));
19955 //===----------------------------------------------------------------------===//
19956 // X86 Scheduler Hooks
19957 //===----------------------------------------------------------------------===//
19959 /// Utility function to emit xbegin specifying the start of an RTM region.
19960 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19961 const TargetInstrInfo *TII) {
19962 DebugLoc DL = MI->getDebugLoc();
19964 const BasicBlock *BB = MBB->getBasicBlock();
19965 MachineFunction::iterator I = MBB;
19968 // For the v = xbegin(), we generate
19979 MachineBasicBlock *thisMBB = MBB;
19980 MachineFunction *MF = MBB->getParent();
19981 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19982 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19983 MF->insert(I, mainMBB);
19984 MF->insert(I, sinkMBB);
19986 // Transfer the remainder of BB and its successor edges to sinkMBB.
19987 sinkMBB->splice(sinkMBB->begin(), MBB,
19988 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19989 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19993 // # fallthrough to mainMBB
19994 // # abortion to sinkMBB
19995 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19996 thisMBB->addSuccessor(mainMBB);
19997 thisMBB->addSuccessor(sinkMBB);
20001 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20002 mainMBB->addSuccessor(sinkMBB);
20005 // EAX is live into the sinkMBB
20006 sinkMBB->addLiveIn(X86::EAX);
20007 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20008 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20011 MI->eraseFromParent();
20015 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20016 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20017 // in the .td file.
20018 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20019 const TargetInstrInfo *TII) {
20021 switch (MI->getOpcode()) {
20022 default: llvm_unreachable("illegal opcode!");
20023 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20024 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20025 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20026 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20027 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20028 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20029 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20030 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20033 DebugLoc dl = MI->getDebugLoc();
20034 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20036 unsigned NumArgs = MI->getNumOperands();
20037 for (unsigned i = 1; i < NumArgs; ++i) {
20038 MachineOperand &Op = MI->getOperand(i);
20039 if (!(Op.isReg() && Op.isImplicit()))
20040 MIB.addOperand(Op);
20042 if (MI->hasOneMemOperand())
20043 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20045 BuildMI(*BB, MI, dl,
20046 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20047 .addReg(X86::XMM0);
20049 MI->eraseFromParent();
20053 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20054 // defs in an instruction pattern
20055 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20056 const TargetInstrInfo *TII) {
20058 switch (MI->getOpcode()) {
20059 default: llvm_unreachable("illegal opcode!");
20060 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20061 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20062 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20063 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20064 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20065 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20066 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20067 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20070 DebugLoc dl = MI->getDebugLoc();
20071 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20073 unsigned NumArgs = MI->getNumOperands(); // remove the results
20074 for (unsigned i = 1; i < NumArgs; ++i) {
20075 MachineOperand &Op = MI->getOperand(i);
20076 if (!(Op.isReg() && Op.isImplicit()))
20077 MIB.addOperand(Op);
20079 if (MI->hasOneMemOperand())
20080 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20082 BuildMI(*BB, MI, dl,
20083 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20086 MI->eraseFromParent();
20090 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20091 const TargetInstrInfo *TII,
20092 const X86Subtarget* Subtarget) {
20093 DebugLoc dl = MI->getDebugLoc();
20095 // Address into RAX/EAX, other two args into ECX, EDX.
20096 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20097 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20098 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20099 for (int i = 0; i < X86::AddrNumOperands; ++i)
20100 MIB.addOperand(MI->getOperand(i));
20102 unsigned ValOps = X86::AddrNumOperands;
20103 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20104 .addReg(MI->getOperand(ValOps).getReg());
20105 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20106 .addReg(MI->getOperand(ValOps+1).getReg());
20108 // The instruction doesn't actually take any operands though.
20109 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20111 MI->eraseFromParent(); // The pseudo is gone now.
20115 MachineBasicBlock *
20116 X86TargetLowering::EmitVAARG64WithCustomInserter(
20118 MachineBasicBlock *MBB) const {
20119 // Emit va_arg instruction on X86-64.
20121 // Operands to this pseudo-instruction:
20122 // 0 ) Output : destination address (reg)
20123 // 1-5) Input : va_list address (addr, i64mem)
20124 // 6 ) ArgSize : Size (in bytes) of vararg type
20125 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20126 // 8 ) Align : Alignment of type
20127 // 9 ) EFLAGS (implicit-def)
20129 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20130 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20132 unsigned DestReg = MI->getOperand(0).getReg();
20133 MachineOperand &Base = MI->getOperand(1);
20134 MachineOperand &Scale = MI->getOperand(2);
20135 MachineOperand &Index = MI->getOperand(3);
20136 MachineOperand &Disp = MI->getOperand(4);
20137 MachineOperand &Segment = MI->getOperand(5);
20138 unsigned ArgSize = MI->getOperand(6).getImm();
20139 unsigned ArgMode = MI->getOperand(7).getImm();
20140 unsigned Align = MI->getOperand(8).getImm();
20142 // Memory Reference
20143 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20144 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20145 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20147 // Machine Information
20148 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20149 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20150 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20151 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20152 DebugLoc DL = MI->getDebugLoc();
20154 // struct va_list {
20157 // i64 overflow_area (address)
20158 // i64 reg_save_area (address)
20160 // sizeof(va_list) = 24
20161 // alignment(va_list) = 8
20163 unsigned TotalNumIntRegs = 6;
20164 unsigned TotalNumXMMRegs = 8;
20165 bool UseGPOffset = (ArgMode == 1);
20166 bool UseFPOffset = (ArgMode == 2);
20167 unsigned MaxOffset = TotalNumIntRegs * 8 +
20168 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20170 /* Align ArgSize to a multiple of 8 */
20171 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20172 bool NeedsAlign = (Align > 8);
20174 MachineBasicBlock *thisMBB = MBB;
20175 MachineBasicBlock *overflowMBB;
20176 MachineBasicBlock *offsetMBB;
20177 MachineBasicBlock *endMBB;
20179 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20180 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20181 unsigned OffsetReg = 0;
20183 if (!UseGPOffset && !UseFPOffset) {
20184 // If we only pull from the overflow region, we don't create a branch.
20185 // We don't need to alter control flow.
20186 OffsetDestReg = 0; // unused
20187 OverflowDestReg = DestReg;
20189 offsetMBB = nullptr;
20190 overflowMBB = thisMBB;
20193 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20194 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20195 // If not, pull from overflow_area. (branch to overflowMBB)
20200 // offsetMBB overflowMBB
20205 // Registers for the PHI in endMBB
20206 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20207 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20209 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20210 MachineFunction *MF = MBB->getParent();
20211 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20212 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20213 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20215 MachineFunction::iterator MBBIter = MBB;
20218 // Insert the new basic blocks
20219 MF->insert(MBBIter, offsetMBB);
20220 MF->insert(MBBIter, overflowMBB);
20221 MF->insert(MBBIter, endMBB);
20223 // Transfer the remainder of MBB and its successor edges to endMBB.
20224 endMBB->splice(endMBB->begin(), thisMBB,
20225 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20226 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20228 // Make offsetMBB and overflowMBB successors of thisMBB
20229 thisMBB->addSuccessor(offsetMBB);
20230 thisMBB->addSuccessor(overflowMBB);
20232 // endMBB is a successor of both offsetMBB and overflowMBB
20233 offsetMBB->addSuccessor(endMBB);
20234 overflowMBB->addSuccessor(endMBB);
20236 // Load the offset value into a register
20237 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20238 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20242 .addDisp(Disp, UseFPOffset ? 4 : 0)
20243 .addOperand(Segment)
20244 .setMemRefs(MMOBegin, MMOEnd);
20246 // Check if there is enough room left to pull this argument.
20247 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20249 .addImm(MaxOffset + 8 - ArgSizeA8);
20251 // Branch to "overflowMBB" if offset >= max
20252 // Fall through to "offsetMBB" otherwise
20253 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20254 .addMBB(overflowMBB);
20257 // In offsetMBB, emit code to use the reg_save_area.
20259 assert(OffsetReg != 0);
20261 // Read the reg_save_area address.
20262 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20263 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20268 .addOperand(Segment)
20269 .setMemRefs(MMOBegin, MMOEnd);
20271 // Zero-extend the offset
20272 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20273 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20276 .addImm(X86::sub_32bit);
20278 // Add the offset to the reg_save_area to get the final address.
20279 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20280 .addReg(OffsetReg64)
20281 .addReg(RegSaveReg);
20283 // Compute the offset for the next argument
20284 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20285 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20287 .addImm(UseFPOffset ? 16 : 8);
20289 // Store it back into the va_list.
20290 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20294 .addDisp(Disp, UseFPOffset ? 4 : 0)
20295 .addOperand(Segment)
20296 .addReg(NextOffsetReg)
20297 .setMemRefs(MMOBegin, MMOEnd);
20300 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20305 // Emit code to use overflow area
20308 // Load the overflow_area address into a register.
20309 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20310 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20315 .addOperand(Segment)
20316 .setMemRefs(MMOBegin, MMOEnd);
20318 // If we need to align it, do so. Otherwise, just copy the address
20319 // to OverflowDestReg.
20321 // Align the overflow address
20322 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20323 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20325 // aligned_addr = (addr + (align-1)) & ~(align-1)
20326 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20327 .addReg(OverflowAddrReg)
20330 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20332 .addImm(~(uint64_t)(Align-1));
20334 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20335 .addReg(OverflowAddrReg);
20338 // Compute the next overflow address after this argument.
20339 // (the overflow address should be kept 8-byte aligned)
20340 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20341 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20342 .addReg(OverflowDestReg)
20343 .addImm(ArgSizeA8);
20345 // Store the new overflow address.
20346 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20351 .addOperand(Segment)
20352 .addReg(NextAddrReg)
20353 .setMemRefs(MMOBegin, MMOEnd);
20355 // If we branched, emit the PHI to the front of endMBB.
20357 BuildMI(*endMBB, endMBB->begin(), DL,
20358 TII->get(X86::PHI), DestReg)
20359 .addReg(OffsetDestReg).addMBB(offsetMBB)
20360 .addReg(OverflowDestReg).addMBB(overflowMBB);
20363 // Erase the pseudo instruction
20364 MI->eraseFromParent();
20369 MachineBasicBlock *
20370 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20372 MachineBasicBlock *MBB) const {
20373 // Emit code to save XMM registers to the stack. The ABI says that the
20374 // number of registers to save is given in %al, so it's theoretically
20375 // possible to do an indirect jump trick to avoid saving all of them,
20376 // however this code takes a simpler approach and just executes all
20377 // of the stores if %al is non-zero. It's less code, and it's probably
20378 // easier on the hardware branch predictor, and stores aren't all that
20379 // expensive anyway.
20381 // Create the new basic blocks. One block contains all the XMM stores,
20382 // and one block is the final destination regardless of whether any
20383 // stores were performed.
20384 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20385 MachineFunction *F = MBB->getParent();
20386 MachineFunction::iterator MBBIter = MBB;
20388 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20389 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20390 F->insert(MBBIter, XMMSaveMBB);
20391 F->insert(MBBIter, EndMBB);
20393 // Transfer the remainder of MBB and its successor edges to EndMBB.
20394 EndMBB->splice(EndMBB->begin(), MBB,
20395 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20396 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20398 // The original block will now fall through to the XMM save block.
20399 MBB->addSuccessor(XMMSaveMBB);
20400 // The XMMSaveMBB will fall through to the end block.
20401 XMMSaveMBB->addSuccessor(EndMBB);
20403 // Now add the instructions.
20404 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20405 DebugLoc DL = MI->getDebugLoc();
20407 unsigned CountReg = MI->getOperand(0).getReg();
20408 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20409 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20411 if (!Subtarget->isTargetWin64()) {
20412 // If %al is 0, branch around the XMM save block.
20413 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20414 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20415 MBB->addSuccessor(EndMBB);
20418 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20419 // that was just emitted, but clearly shouldn't be "saved".
20420 assert((MI->getNumOperands() <= 3 ||
20421 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20422 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20423 && "Expected last argument to be EFLAGS");
20424 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20425 // In the XMM save block, save all the XMM argument registers.
20426 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20427 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20428 MachineMemOperand *MMO =
20429 F->getMachineMemOperand(
20430 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20431 MachineMemOperand::MOStore,
20432 /*Size=*/16, /*Align=*/16);
20433 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20434 .addFrameIndex(RegSaveFrameIndex)
20435 .addImm(/*Scale=*/1)
20436 .addReg(/*IndexReg=*/0)
20437 .addImm(/*Disp=*/Offset)
20438 .addReg(/*Segment=*/0)
20439 .addReg(MI->getOperand(i).getReg())
20440 .addMemOperand(MMO);
20443 MI->eraseFromParent(); // The pseudo instruction is gone now.
20448 // The EFLAGS operand of SelectItr might be missing a kill marker
20449 // because there were multiple uses of EFLAGS, and ISel didn't know
20450 // which to mark. Figure out whether SelectItr should have had a
20451 // kill marker, and set it if it should. Returns the correct kill
20453 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20454 MachineBasicBlock* BB,
20455 const TargetRegisterInfo* TRI) {
20456 // Scan forward through BB for a use/def of EFLAGS.
20457 MachineBasicBlock::iterator miI(std::next(SelectItr));
20458 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20459 const MachineInstr& mi = *miI;
20460 if (mi.readsRegister(X86::EFLAGS))
20462 if (mi.definesRegister(X86::EFLAGS))
20463 break; // Should have kill-flag - update below.
20466 // If we hit the end of the block, check whether EFLAGS is live into a
20468 if (miI == BB->end()) {
20469 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20470 sEnd = BB->succ_end();
20471 sItr != sEnd; ++sItr) {
20472 MachineBasicBlock* succ = *sItr;
20473 if (succ->isLiveIn(X86::EFLAGS))
20478 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20479 // out. SelectMI should have a kill flag on EFLAGS.
20480 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20484 MachineBasicBlock *
20485 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20486 MachineBasicBlock *BB) const {
20487 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20488 DebugLoc DL = MI->getDebugLoc();
20490 // To "insert" a SELECT_CC instruction, we actually have to insert the
20491 // diamond control-flow pattern. The incoming instruction knows the
20492 // destination vreg to set, the condition code register to branch on, the
20493 // true/false values to select between, and a branch opcode to use.
20494 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20495 MachineFunction::iterator It = BB;
20501 // cmpTY ccX, r1, r2
20503 // fallthrough --> copy0MBB
20504 MachineBasicBlock *thisMBB = BB;
20505 MachineFunction *F = BB->getParent();
20506 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20507 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20508 F->insert(It, copy0MBB);
20509 F->insert(It, sinkMBB);
20511 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20512 // live into the sink and copy blocks.
20513 const TargetRegisterInfo *TRI =
20514 BB->getParent()->getSubtarget().getRegisterInfo();
20515 if (!MI->killsRegister(X86::EFLAGS) &&
20516 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20517 copy0MBB->addLiveIn(X86::EFLAGS);
20518 sinkMBB->addLiveIn(X86::EFLAGS);
20521 // Transfer the remainder of BB and its successor edges to sinkMBB.
20522 sinkMBB->splice(sinkMBB->begin(), BB,
20523 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20524 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20526 // Add the true and fallthrough blocks as its successors.
20527 BB->addSuccessor(copy0MBB);
20528 BB->addSuccessor(sinkMBB);
20530 // Create the conditional branch instruction.
20532 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20533 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20536 // %FalseValue = ...
20537 // # fallthrough to sinkMBB
20538 copy0MBB->addSuccessor(sinkMBB);
20541 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20543 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20544 TII->get(X86::PHI), MI->getOperand(0).getReg())
20545 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20546 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20548 MI->eraseFromParent(); // The pseudo instruction is gone now.
20552 MachineBasicBlock *
20553 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20554 MachineBasicBlock *BB) const {
20555 MachineFunction *MF = BB->getParent();
20556 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20557 DebugLoc DL = MI->getDebugLoc();
20558 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20560 assert(MF->shouldSplitStack());
20562 const bool Is64Bit = Subtarget->is64Bit();
20563 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20565 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20566 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20569 // ... [Till the alloca]
20570 // If stacklet is not large enough, jump to mallocMBB
20573 // Allocate by subtracting from RSP
20574 // Jump to continueMBB
20577 // Allocate by call to runtime
20581 // [rest of original BB]
20584 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20585 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20586 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20588 MachineRegisterInfo &MRI = MF->getRegInfo();
20589 const TargetRegisterClass *AddrRegClass =
20590 getRegClassFor(getPointerTy());
20592 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20593 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20594 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20595 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20596 sizeVReg = MI->getOperand(1).getReg(),
20597 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20599 MachineFunction::iterator MBBIter = BB;
20602 MF->insert(MBBIter, bumpMBB);
20603 MF->insert(MBBIter, mallocMBB);
20604 MF->insert(MBBIter, continueMBB);
20606 continueMBB->splice(continueMBB->begin(), BB,
20607 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20608 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20610 // Add code to the main basic block to check if the stack limit has been hit,
20611 // and if so, jump to mallocMBB otherwise to bumpMBB.
20612 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20613 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20614 .addReg(tmpSPVReg).addReg(sizeVReg);
20615 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20616 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20617 .addReg(SPLimitVReg);
20618 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20620 // bumpMBB simply decreases the stack pointer, since we know the current
20621 // stacklet has enough space.
20622 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20623 .addReg(SPLimitVReg);
20624 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20625 .addReg(SPLimitVReg);
20626 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20628 // Calls into a routine in libgcc to allocate more space from the heap.
20629 const uint32_t *RegMask = MF->getTarget()
20630 .getSubtargetImpl()
20631 ->getRegisterInfo()
20632 ->getCallPreservedMask(CallingConv::C);
20634 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20636 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20637 .addExternalSymbol("__morestack_allocate_stack_space")
20638 .addRegMask(RegMask)
20639 .addReg(X86::RDI, RegState::Implicit)
20640 .addReg(X86::RAX, RegState::ImplicitDefine);
20641 } else if (Is64Bit) {
20642 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20644 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20645 .addExternalSymbol("__morestack_allocate_stack_space")
20646 .addRegMask(RegMask)
20647 .addReg(X86::EDI, RegState::Implicit)
20648 .addReg(X86::EAX, RegState::ImplicitDefine);
20650 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20652 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20653 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20654 .addExternalSymbol("__morestack_allocate_stack_space")
20655 .addRegMask(RegMask)
20656 .addReg(X86::EAX, RegState::ImplicitDefine);
20660 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20663 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20664 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20665 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20667 // Set up the CFG correctly.
20668 BB->addSuccessor(bumpMBB);
20669 BB->addSuccessor(mallocMBB);
20670 mallocMBB->addSuccessor(continueMBB);
20671 bumpMBB->addSuccessor(continueMBB);
20673 // Take care of the PHI nodes.
20674 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20675 MI->getOperand(0).getReg())
20676 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20677 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20679 // Delete the original pseudo instruction.
20680 MI->eraseFromParent();
20683 return continueMBB;
20686 MachineBasicBlock *
20687 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20688 MachineBasicBlock *BB) const {
20689 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20690 DebugLoc DL = MI->getDebugLoc();
20692 assert(!Subtarget->isTargetMachO());
20694 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20695 // non-trivial part is impdef of ESP.
20697 if (Subtarget->isTargetWin64()) {
20698 if (Subtarget->isTargetCygMing()) {
20699 // ___chkstk(Mingw64):
20700 // Clobbers R10, R11, RAX and EFLAGS.
20702 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20703 .addExternalSymbol("___chkstk")
20704 .addReg(X86::RAX, RegState::Implicit)
20705 .addReg(X86::RSP, RegState::Implicit)
20706 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20707 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20708 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20710 // __chkstk(MSVCRT): does not update stack pointer.
20711 // Clobbers R10, R11 and EFLAGS.
20712 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20713 .addExternalSymbol("__chkstk")
20714 .addReg(X86::RAX, RegState::Implicit)
20715 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20716 // RAX has the offset to be subtracted from RSP.
20717 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20722 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20723 Subtarget->isTargetWindowsItanium())
20727 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20728 .addExternalSymbol(StackProbeSymbol)
20729 .addReg(X86::EAX, RegState::Implicit)
20730 .addReg(X86::ESP, RegState::Implicit)
20731 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20732 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20733 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20736 MI->eraseFromParent(); // The pseudo instruction is gone now.
20740 MachineBasicBlock *
20741 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20742 MachineBasicBlock *BB) const {
20743 // This is pretty easy. We're taking the value that we received from
20744 // our load from the relocation, sticking it in either RDI (x86-64)
20745 // or EAX and doing an indirect call. The return value will then
20746 // be in the normal return register.
20747 MachineFunction *F = BB->getParent();
20748 const X86InstrInfo *TII =
20749 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20750 DebugLoc DL = MI->getDebugLoc();
20752 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20753 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20755 // Get a register mask for the lowered call.
20756 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20757 // proper register mask.
20758 const uint32_t *RegMask = F->getTarget()
20759 .getSubtargetImpl()
20760 ->getRegisterInfo()
20761 ->getCallPreservedMask(CallingConv::C);
20762 if (Subtarget->is64Bit()) {
20763 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20764 TII->get(X86::MOV64rm), X86::RDI)
20766 .addImm(0).addReg(0)
20767 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20768 MI->getOperand(3).getTargetFlags())
20770 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20771 addDirectMem(MIB, X86::RDI);
20772 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20773 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20774 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20775 TII->get(X86::MOV32rm), X86::EAX)
20777 .addImm(0).addReg(0)
20778 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20779 MI->getOperand(3).getTargetFlags())
20781 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20782 addDirectMem(MIB, X86::EAX);
20783 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20785 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20786 TII->get(X86::MOV32rm), X86::EAX)
20787 .addReg(TII->getGlobalBaseReg(F))
20788 .addImm(0).addReg(0)
20789 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20790 MI->getOperand(3).getTargetFlags())
20792 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20793 addDirectMem(MIB, X86::EAX);
20794 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20797 MI->eraseFromParent(); // The pseudo instruction is gone now.
20801 MachineBasicBlock *
20802 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20803 MachineBasicBlock *MBB) const {
20804 DebugLoc DL = MI->getDebugLoc();
20805 MachineFunction *MF = MBB->getParent();
20806 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20807 MachineRegisterInfo &MRI = MF->getRegInfo();
20809 const BasicBlock *BB = MBB->getBasicBlock();
20810 MachineFunction::iterator I = MBB;
20813 // Memory Reference
20814 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20815 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20818 unsigned MemOpndSlot = 0;
20820 unsigned CurOp = 0;
20822 DstReg = MI->getOperand(CurOp++).getReg();
20823 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20824 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20825 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20826 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20828 MemOpndSlot = CurOp;
20830 MVT PVT = getPointerTy();
20831 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20832 "Invalid Pointer Size!");
20834 // For v = setjmp(buf), we generate
20837 // buf[LabelOffset] = restoreMBB
20838 // SjLjSetup restoreMBB
20844 // v = phi(main, restore)
20847 // if base pointer being used, load it from frame
20850 MachineBasicBlock *thisMBB = MBB;
20851 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20852 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20853 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20854 MF->insert(I, mainMBB);
20855 MF->insert(I, sinkMBB);
20856 MF->push_back(restoreMBB);
20858 MachineInstrBuilder MIB;
20860 // Transfer the remainder of BB and its successor edges to sinkMBB.
20861 sinkMBB->splice(sinkMBB->begin(), MBB,
20862 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20863 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20866 unsigned PtrStoreOpc = 0;
20867 unsigned LabelReg = 0;
20868 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20869 Reloc::Model RM = MF->getTarget().getRelocationModel();
20870 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20871 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20873 // Prepare IP either in reg or imm.
20874 if (!UseImmLabel) {
20875 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20876 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20877 LabelReg = MRI.createVirtualRegister(PtrRC);
20878 if (Subtarget->is64Bit()) {
20879 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20883 .addMBB(restoreMBB)
20886 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20887 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20888 .addReg(XII->getGlobalBaseReg(MF))
20891 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20895 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20897 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20898 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20899 if (i == X86::AddrDisp)
20900 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20902 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20905 MIB.addReg(LabelReg);
20907 MIB.addMBB(restoreMBB);
20908 MIB.setMemRefs(MMOBegin, MMOEnd);
20910 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20911 .addMBB(restoreMBB);
20913 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20914 MF->getSubtarget().getRegisterInfo());
20915 MIB.addRegMask(RegInfo->getNoPreservedMask());
20916 thisMBB->addSuccessor(mainMBB);
20917 thisMBB->addSuccessor(restoreMBB);
20921 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20922 mainMBB->addSuccessor(sinkMBB);
20925 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20926 TII->get(X86::PHI), DstReg)
20927 .addReg(mainDstReg).addMBB(mainMBB)
20928 .addReg(restoreDstReg).addMBB(restoreMBB);
20931 if (RegInfo->hasBasePointer(*MF)) {
20932 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
20933 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
20934 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20935 X86FI->setRestoreBasePointer(MF);
20936 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20937 unsigned BasePtr = RegInfo->getBaseRegister();
20938 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20939 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20940 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20941 .setMIFlag(MachineInstr::FrameSetup);
20943 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20944 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20945 restoreMBB->addSuccessor(sinkMBB);
20947 MI->eraseFromParent();
20951 MachineBasicBlock *
20952 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20953 MachineBasicBlock *MBB) const {
20954 DebugLoc DL = MI->getDebugLoc();
20955 MachineFunction *MF = MBB->getParent();
20956 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20957 MachineRegisterInfo &MRI = MF->getRegInfo();
20959 // Memory Reference
20960 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20961 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20963 MVT PVT = getPointerTy();
20964 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20965 "Invalid Pointer Size!");
20967 const TargetRegisterClass *RC =
20968 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20969 unsigned Tmp = MRI.createVirtualRegister(RC);
20970 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20971 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20972 MF->getSubtarget().getRegisterInfo());
20973 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20974 unsigned SP = RegInfo->getStackRegister();
20976 MachineInstrBuilder MIB;
20978 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20979 const int64_t SPOffset = 2 * PVT.getStoreSize();
20981 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20982 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20985 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20986 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20987 MIB.addOperand(MI->getOperand(i));
20988 MIB.setMemRefs(MMOBegin, MMOEnd);
20990 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20991 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20992 if (i == X86::AddrDisp)
20993 MIB.addDisp(MI->getOperand(i), LabelOffset);
20995 MIB.addOperand(MI->getOperand(i));
20997 MIB.setMemRefs(MMOBegin, MMOEnd);
20999 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21000 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21001 if (i == X86::AddrDisp)
21002 MIB.addDisp(MI->getOperand(i), SPOffset);
21004 MIB.addOperand(MI->getOperand(i));
21006 MIB.setMemRefs(MMOBegin, MMOEnd);
21008 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21010 MI->eraseFromParent();
21014 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21015 // accumulator loops. Writing back to the accumulator allows the coalescer
21016 // to remove extra copies in the loop.
21017 MachineBasicBlock *
21018 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21019 MachineBasicBlock *MBB) const {
21020 MachineOperand &AddendOp = MI->getOperand(3);
21022 // Bail out early if the addend isn't a register - we can't switch these.
21023 if (!AddendOp.isReg())
21026 MachineFunction &MF = *MBB->getParent();
21027 MachineRegisterInfo &MRI = MF.getRegInfo();
21029 // Check whether the addend is defined by a PHI:
21030 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21031 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21032 if (!AddendDef.isPHI())
21035 // Look for the following pattern:
21037 // %addend = phi [%entry, 0], [%loop, %result]
21039 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21043 // %addend = phi [%entry, 0], [%loop, %result]
21045 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21047 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21048 assert(AddendDef.getOperand(i).isReg());
21049 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21050 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21051 if (&PHISrcInst == MI) {
21052 // Found a matching instruction.
21053 unsigned NewFMAOpc = 0;
21054 switch (MI->getOpcode()) {
21055 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21056 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21057 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21058 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21059 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21060 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21061 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21062 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21063 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21064 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21065 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21066 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21067 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21068 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21069 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21070 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21071 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21072 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21073 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21074 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21076 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21077 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21078 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21079 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21080 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21081 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21082 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21083 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21084 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21085 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21086 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21087 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21088 default: llvm_unreachable("Unrecognized FMA variant.");
21091 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21092 MachineInstrBuilder MIB =
21093 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21094 .addOperand(MI->getOperand(0))
21095 .addOperand(MI->getOperand(3))
21096 .addOperand(MI->getOperand(2))
21097 .addOperand(MI->getOperand(1));
21098 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21099 MI->eraseFromParent();
21106 MachineBasicBlock *
21107 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21108 MachineBasicBlock *BB) const {
21109 switch (MI->getOpcode()) {
21110 default: llvm_unreachable("Unexpected instr type to insert");
21111 case X86::TAILJMPd64:
21112 case X86::TAILJMPr64:
21113 case X86::TAILJMPm64:
21114 llvm_unreachable("TAILJMP64 would not be touched here.");
21115 case X86::TCRETURNdi64:
21116 case X86::TCRETURNri64:
21117 case X86::TCRETURNmi64:
21119 case X86::WIN_ALLOCA:
21120 return EmitLoweredWinAlloca(MI, BB);
21121 case X86::SEG_ALLOCA_32:
21122 case X86::SEG_ALLOCA_64:
21123 return EmitLoweredSegAlloca(MI, BB);
21124 case X86::TLSCall_32:
21125 case X86::TLSCall_64:
21126 return EmitLoweredTLSCall(MI, BB);
21127 case X86::CMOV_GR8:
21128 case X86::CMOV_FR32:
21129 case X86::CMOV_FR64:
21130 case X86::CMOV_V4F32:
21131 case X86::CMOV_V2F64:
21132 case X86::CMOV_V2I64:
21133 case X86::CMOV_V8F32:
21134 case X86::CMOV_V4F64:
21135 case X86::CMOV_V4I64:
21136 case X86::CMOV_V16F32:
21137 case X86::CMOV_V8F64:
21138 case X86::CMOV_V8I64:
21139 case X86::CMOV_GR16:
21140 case X86::CMOV_GR32:
21141 case X86::CMOV_RFP32:
21142 case X86::CMOV_RFP64:
21143 case X86::CMOV_RFP80:
21144 return EmitLoweredSelect(MI, BB);
21146 case X86::FP32_TO_INT16_IN_MEM:
21147 case X86::FP32_TO_INT32_IN_MEM:
21148 case X86::FP32_TO_INT64_IN_MEM:
21149 case X86::FP64_TO_INT16_IN_MEM:
21150 case X86::FP64_TO_INT32_IN_MEM:
21151 case X86::FP64_TO_INT64_IN_MEM:
21152 case X86::FP80_TO_INT16_IN_MEM:
21153 case X86::FP80_TO_INT32_IN_MEM:
21154 case X86::FP80_TO_INT64_IN_MEM: {
21155 MachineFunction *F = BB->getParent();
21156 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21157 DebugLoc DL = MI->getDebugLoc();
21159 // Change the floating point control register to use "round towards zero"
21160 // mode when truncating to an integer value.
21161 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21162 addFrameReference(BuildMI(*BB, MI, DL,
21163 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21165 // Load the old value of the high byte of the control word...
21167 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21168 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21171 // Set the high part to be round to zero...
21172 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21175 // Reload the modified control word now...
21176 addFrameReference(BuildMI(*BB, MI, DL,
21177 TII->get(X86::FLDCW16m)), CWFrameIdx);
21179 // Restore the memory image of control word to original value
21180 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21183 // Get the X86 opcode to use.
21185 switch (MI->getOpcode()) {
21186 default: llvm_unreachable("illegal opcode!");
21187 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21188 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21189 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21190 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21191 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21192 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21193 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21194 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21195 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21199 MachineOperand &Op = MI->getOperand(0);
21201 AM.BaseType = X86AddressMode::RegBase;
21202 AM.Base.Reg = Op.getReg();
21204 AM.BaseType = X86AddressMode::FrameIndexBase;
21205 AM.Base.FrameIndex = Op.getIndex();
21207 Op = MI->getOperand(1);
21209 AM.Scale = Op.getImm();
21210 Op = MI->getOperand(2);
21212 AM.IndexReg = Op.getImm();
21213 Op = MI->getOperand(3);
21214 if (Op.isGlobal()) {
21215 AM.GV = Op.getGlobal();
21217 AM.Disp = Op.getImm();
21219 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21220 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21222 // Reload the original control word now.
21223 addFrameReference(BuildMI(*BB, MI, DL,
21224 TII->get(X86::FLDCW16m)), CWFrameIdx);
21226 MI->eraseFromParent(); // The pseudo instruction is gone now.
21229 // String/text processing lowering.
21230 case X86::PCMPISTRM128REG:
21231 case X86::VPCMPISTRM128REG:
21232 case X86::PCMPISTRM128MEM:
21233 case X86::VPCMPISTRM128MEM:
21234 case X86::PCMPESTRM128REG:
21235 case X86::VPCMPESTRM128REG:
21236 case X86::PCMPESTRM128MEM:
21237 case X86::VPCMPESTRM128MEM:
21238 assert(Subtarget->hasSSE42() &&
21239 "Target must have SSE4.2 or AVX features enabled");
21240 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21242 // String/text processing lowering.
21243 case X86::PCMPISTRIREG:
21244 case X86::VPCMPISTRIREG:
21245 case X86::PCMPISTRIMEM:
21246 case X86::VPCMPISTRIMEM:
21247 case X86::PCMPESTRIREG:
21248 case X86::VPCMPESTRIREG:
21249 case X86::PCMPESTRIMEM:
21250 case X86::VPCMPESTRIMEM:
21251 assert(Subtarget->hasSSE42() &&
21252 "Target must have SSE4.2 or AVX features enabled");
21253 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21255 // Thread synchronization.
21257 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21262 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21264 case X86::VASTART_SAVE_XMM_REGS:
21265 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21267 case X86::VAARG_64:
21268 return EmitVAARG64WithCustomInserter(MI, BB);
21270 case X86::EH_SjLj_SetJmp32:
21271 case X86::EH_SjLj_SetJmp64:
21272 return emitEHSjLjSetJmp(MI, BB);
21274 case X86::EH_SjLj_LongJmp32:
21275 case X86::EH_SjLj_LongJmp64:
21276 return emitEHSjLjLongJmp(MI, BB);
21278 case TargetOpcode::STATEPOINT:
21279 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21280 // this point in the process. We diverge later.
21281 return emitPatchPoint(MI, BB);
21283 case TargetOpcode::STACKMAP:
21284 case TargetOpcode::PATCHPOINT:
21285 return emitPatchPoint(MI, BB);
21287 case X86::VFMADDPDr213r:
21288 case X86::VFMADDPSr213r:
21289 case X86::VFMADDSDr213r:
21290 case X86::VFMADDSSr213r:
21291 case X86::VFMSUBPDr213r:
21292 case X86::VFMSUBPSr213r:
21293 case X86::VFMSUBSDr213r:
21294 case X86::VFMSUBSSr213r:
21295 case X86::VFNMADDPDr213r:
21296 case X86::VFNMADDPSr213r:
21297 case X86::VFNMADDSDr213r:
21298 case X86::VFNMADDSSr213r:
21299 case X86::VFNMSUBPDr213r:
21300 case X86::VFNMSUBPSr213r:
21301 case X86::VFNMSUBSDr213r:
21302 case X86::VFNMSUBSSr213r:
21303 case X86::VFMADDSUBPDr213r:
21304 case X86::VFMADDSUBPSr213r:
21305 case X86::VFMSUBADDPDr213r:
21306 case X86::VFMSUBADDPSr213r:
21307 case X86::VFMADDPDr213rY:
21308 case X86::VFMADDPSr213rY:
21309 case X86::VFMSUBPDr213rY:
21310 case X86::VFMSUBPSr213rY:
21311 case X86::VFNMADDPDr213rY:
21312 case X86::VFNMADDPSr213rY:
21313 case X86::VFNMSUBPDr213rY:
21314 case X86::VFNMSUBPSr213rY:
21315 case X86::VFMADDSUBPDr213rY:
21316 case X86::VFMADDSUBPSr213rY:
21317 case X86::VFMSUBADDPDr213rY:
21318 case X86::VFMSUBADDPSr213rY:
21319 return emitFMA3Instr(MI, BB);
21323 //===----------------------------------------------------------------------===//
21324 // X86 Optimization Hooks
21325 //===----------------------------------------------------------------------===//
21327 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21330 const SelectionDAG &DAG,
21331 unsigned Depth) const {
21332 unsigned BitWidth = KnownZero.getBitWidth();
21333 unsigned Opc = Op.getOpcode();
21334 assert((Opc >= ISD::BUILTIN_OP_END ||
21335 Opc == ISD::INTRINSIC_WO_CHAIN ||
21336 Opc == ISD::INTRINSIC_W_CHAIN ||
21337 Opc == ISD::INTRINSIC_VOID) &&
21338 "Should use MaskedValueIsZero if you don't know whether Op"
21339 " is a target node!");
21341 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21355 // These nodes' second result is a boolean.
21356 if (Op.getResNo() == 0)
21359 case X86ISD::SETCC:
21360 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21362 case ISD::INTRINSIC_WO_CHAIN: {
21363 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21364 unsigned NumLoBits = 0;
21367 case Intrinsic::x86_sse_movmsk_ps:
21368 case Intrinsic::x86_avx_movmsk_ps_256:
21369 case Intrinsic::x86_sse2_movmsk_pd:
21370 case Intrinsic::x86_avx_movmsk_pd_256:
21371 case Intrinsic::x86_mmx_pmovmskb:
21372 case Intrinsic::x86_sse2_pmovmskb_128:
21373 case Intrinsic::x86_avx2_pmovmskb: {
21374 // High bits of movmskp{s|d}, pmovmskb are known zero.
21376 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21377 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21378 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21379 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21380 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21381 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21382 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21383 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21385 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21394 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21396 const SelectionDAG &,
21397 unsigned Depth) const {
21398 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21399 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21400 return Op.getValueType().getScalarType().getSizeInBits();
21406 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21407 /// node is a GlobalAddress + offset.
21408 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21409 const GlobalValue* &GA,
21410 int64_t &Offset) const {
21411 if (N->getOpcode() == X86ISD::Wrapper) {
21412 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21413 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21414 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21418 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21421 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21422 /// same as extracting the high 128-bit part of 256-bit vector and then
21423 /// inserting the result into the low part of a new 256-bit vector
21424 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21425 EVT VT = SVOp->getValueType(0);
21426 unsigned NumElems = VT.getVectorNumElements();
21428 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21429 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21430 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21431 SVOp->getMaskElt(j) >= 0)
21437 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21438 /// same as extracting the low 128-bit part of 256-bit vector and then
21439 /// inserting the result into the high part of a new 256-bit vector
21440 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21441 EVT VT = SVOp->getValueType(0);
21442 unsigned NumElems = VT.getVectorNumElements();
21444 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21445 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21446 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21447 SVOp->getMaskElt(j) >= 0)
21453 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21454 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21455 TargetLowering::DAGCombinerInfo &DCI,
21456 const X86Subtarget* Subtarget) {
21458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21459 SDValue V1 = SVOp->getOperand(0);
21460 SDValue V2 = SVOp->getOperand(1);
21461 EVT VT = SVOp->getValueType(0);
21462 unsigned NumElems = VT.getVectorNumElements();
21464 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21465 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21469 // V UNDEF BUILD_VECTOR UNDEF
21471 // CONCAT_VECTOR CONCAT_VECTOR
21474 // RESULT: V + zero extended
21476 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21477 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21478 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21481 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21484 // To match the shuffle mask, the first half of the mask should
21485 // be exactly the first vector, and all the rest a splat with the
21486 // first element of the second one.
21487 for (unsigned i = 0; i != NumElems/2; ++i)
21488 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21489 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21492 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21493 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21494 if (Ld->hasNUsesOfValue(1, 0)) {
21495 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21496 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21498 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21500 Ld->getPointerInfo(),
21501 Ld->getAlignment(),
21502 false/*isVolatile*/, true/*ReadMem*/,
21503 false/*WriteMem*/);
21505 // Make sure the newly-created LOAD is in the same position as Ld in
21506 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21507 // and update uses of Ld's output chain to use the TokenFactor.
21508 if (Ld->hasAnyUseOfValue(1)) {
21509 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21510 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21511 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21512 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21513 SDValue(ResNode.getNode(), 1));
21516 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21520 // Emit a zeroed vector and insert the desired subvector on its
21522 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21523 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21524 return DCI.CombineTo(N, InsV);
21527 //===--------------------------------------------------------------------===//
21528 // Combine some shuffles into subvector extracts and inserts:
21531 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21532 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21533 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21534 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21535 return DCI.CombineTo(N, InsV);
21538 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21539 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21540 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21541 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21542 return DCI.CombineTo(N, InsV);
21548 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21551 /// This is the leaf of the recursive combinine below. When we have found some
21552 /// chain of single-use x86 shuffle instructions and accumulated the combined
21553 /// shuffle mask represented by them, this will try to pattern match that mask
21554 /// into either a single instruction if there is a special purpose instruction
21555 /// for this operation, or into a PSHUFB instruction which is a fully general
21556 /// instruction but should only be used to replace chains over a certain depth.
21557 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21558 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21559 TargetLowering::DAGCombinerInfo &DCI,
21560 const X86Subtarget *Subtarget) {
21561 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21563 // Find the operand that enters the chain. Note that multiple uses are OK
21564 // here, we're not going to remove the operand we find.
21565 SDValue Input = Op.getOperand(0);
21566 while (Input.getOpcode() == ISD::BITCAST)
21567 Input = Input.getOperand(0);
21569 MVT VT = Input.getSimpleValueType();
21570 MVT RootVT = Root.getSimpleValueType();
21573 // Just remove no-op shuffle masks.
21574 if (Mask.size() == 1) {
21575 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21580 // Use the float domain if the operand type is a floating point type.
21581 bool FloatDomain = VT.isFloatingPoint();
21583 // For floating point shuffles, we don't have free copies in the shuffle
21584 // instructions or the ability to load as part of the instruction, so
21585 // canonicalize their shuffles to UNPCK or MOV variants.
21587 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21588 // vectors because it can have a load folded into it that UNPCK cannot. This
21589 // doesn't preclude something switching to the shorter encoding post-RA.
21591 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21592 bool Lo = Mask.equals(0, 0);
21595 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21596 // is no slower than UNPCKLPD but has the option to fold the input operand
21597 // into even an unaligned memory load.
21598 if (Lo && Subtarget->hasSSE3()) {
21599 Shuffle = X86ISD::MOVDDUP;
21600 ShuffleVT = MVT::v2f64;
21602 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21603 // than the UNPCK variants.
21604 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21605 ShuffleVT = MVT::v4f32;
21607 if (Depth == 1 && Root->getOpcode() == Shuffle)
21608 return false; // Nothing to do!
21609 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21610 DCI.AddToWorklist(Op.getNode());
21611 if (Shuffle == X86ISD::MOVDDUP)
21612 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21614 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21615 DCI.AddToWorklist(Op.getNode());
21616 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21620 if (Subtarget->hasSSE3() &&
21621 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21622 bool Lo = Mask.equals(0, 0, 2, 2);
21623 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21624 MVT ShuffleVT = MVT::v4f32;
21625 if (Depth == 1 && Root->getOpcode() == Shuffle)
21626 return false; // Nothing to do!
21627 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21628 DCI.AddToWorklist(Op.getNode());
21629 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21630 DCI.AddToWorklist(Op.getNode());
21631 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21635 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21636 bool Lo = Mask.equals(0, 0, 1, 1);
21637 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21638 MVT ShuffleVT = MVT::v4f32;
21639 if (Depth == 1 && Root->getOpcode() == Shuffle)
21640 return false; // Nothing to do!
21641 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21642 DCI.AddToWorklist(Op.getNode());
21643 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21644 DCI.AddToWorklist(Op.getNode());
21645 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21651 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21652 // variants as none of these have single-instruction variants that are
21653 // superior to the UNPCK formulation.
21654 if (!FloatDomain &&
21655 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21656 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21657 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21658 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21660 bool Lo = Mask[0] == 0;
21661 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21662 if (Depth == 1 && Root->getOpcode() == Shuffle)
21663 return false; // Nothing to do!
21665 switch (Mask.size()) {
21667 ShuffleVT = MVT::v8i16;
21670 ShuffleVT = MVT::v16i8;
21673 llvm_unreachable("Impossible mask size!");
21675 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21676 DCI.AddToWorklist(Op.getNode());
21677 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21678 DCI.AddToWorklist(Op.getNode());
21679 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21684 // Don't try to re-form single instruction chains under any circumstances now
21685 // that we've done encoding canonicalization for them.
21689 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21690 // can replace them with a single PSHUFB instruction profitably. Intel's
21691 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21692 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21693 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21694 SmallVector<SDValue, 16> PSHUFBMask;
21695 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21696 int Ratio = 16 / Mask.size();
21697 for (unsigned i = 0; i < 16; ++i) {
21698 if (Mask[i / Ratio] == SM_SentinelUndef) {
21699 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21702 int M = Mask[i / Ratio] != SM_SentinelZero
21703 ? Ratio * Mask[i / Ratio] + i % Ratio
21705 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21707 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21708 DCI.AddToWorklist(Op.getNode());
21709 SDValue PSHUFBMaskOp =
21710 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21711 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21712 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21713 DCI.AddToWorklist(Op.getNode());
21714 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21719 // Failed to find any combines.
21723 /// \brief Fully generic combining of x86 shuffle instructions.
21725 /// This should be the last combine run over the x86 shuffle instructions. Once
21726 /// they have been fully optimized, this will recursively consider all chains
21727 /// of single-use shuffle instructions, build a generic model of the cumulative
21728 /// shuffle operation, and check for simpler instructions which implement this
21729 /// operation. We use this primarily for two purposes:
21731 /// 1) Collapse generic shuffles to specialized single instructions when
21732 /// equivalent. In most cases, this is just an encoding size win, but
21733 /// sometimes we will collapse multiple generic shuffles into a single
21734 /// special-purpose shuffle.
21735 /// 2) Look for sequences of shuffle instructions with 3 or more total
21736 /// instructions, and replace them with the slightly more expensive SSSE3
21737 /// PSHUFB instruction if available. We do this as the last combining step
21738 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21739 /// a suitable short sequence of other instructions. The PHUFB will either
21740 /// use a register or have to read from memory and so is slightly (but only
21741 /// slightly) more expensive than the other shuffle instructions.
21743 /// Because this is inherently a quadratic operation (for each shuffle in
21744 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21745 /// This should never be an issue in practice as the shuffle lowering doesn't
21746 /// produce sequences of more than 8 instructions.
21748 /// FIXME: We will currently miss some cases where the redundant shuffling
21749 /// would simplify under the threshold for PSHUFB formation because of
21750 /// combine-ordering. To fix this, we should do the redundant instruction
21751 /// combining in this recursive walk.
21752 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21753 ArrayRef<int> RootMask,
21754 int Depth, bool HasPSHUFB,
21756 TargetLowering::DAGCombinerInfo &DCI,
21757 const X86Subtarget *Subtarget) {
21758 // Bound the depth of our recursive combine because this is ultimately
21759 // quadratic in nature.
21763 // Directly rip through bitcasts to find the underlying operand.
21764 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21765 Op = Op.getOperand(0);
21767 MVT VT = Op.getSimpleValueType();
21768 if (!VT.isVector())
21769 return false; // Bail if we hit a non-vector.
21770 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21771 // version should be added.
21772 if (VT.getSizeInBits() != 128)
21775 assert(Root.getSimpleValueType().isVector() &&
21776 "Shuffles operate on vector types!");
21777 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21778 "Can only combine shuffles of the same vector register size.");
21780 if (!isTargetShuffle(Op.getOpcode()))
21782 SmallVector<int, 16> OpMask;
21784 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21785 // We only can combine unary shuffles which we can decode the mask for.
21786 if (!HaveMask || !IsUnary)
21789 assert(VT.getVectorNumElements() == OpMask.size() &&
21790 "Different mask size from vector size!");
21791 assert(((RootMask.size() > OpMask.size() &&
21792 RootMask.size() % OpMask.size() == 0) ||
21793 (OpMask.size() > RootMask.size() &&
21794 OpMask.size() % RootMask.size() == 0) ||
21795 OpMask.size() == RootMask.size()) &&
21796 "The smaller number of elements must divide the larger.");
21797 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21798 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21799 assert(((RootRatio == 1 && OpRatio == 1) ||
21800 (RootRatio == 1) != (OpRatio == 1)) &&
21801 "Must not have a ratio for both incoming and op masks!");
21803 SmallVector<int, 16> Mask;
21804 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21806 // Merge this shuffle operation's mask into our accumulated mask. Note that
21807 // this shuffle's mask will be the first applied to the input, followed by the
21808 // root mask to get us all the way to the root value arrangement. The reason
21809 // for this order is that we are recursing up the operation chain.
21810 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21811 int RootIdx = i / RootRatio;
21812 if (RootMask[RootIdx] < 0) {
21813 // This is a zero or undef lane, we're done.
21814 Mask.push_back(RootMask[RootIdx]);
21818 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21819 int OpIdx = RootMaskedIdx / OpRatio;
21820 if (OpMask[OpIdx] < 0) {
21821 // The incoming lanes are zero or undef, it doesn't matter which ones we
21823 Mask.push_back(OpMask[OpIdx]);
21827 // Ok, we have non-zero lanes, map them through.
21828 Mask.push_back(OpMask[OpIdx] * OpRatio +
21829 RootMaskedIdx % OpRatio);
21832 // See if we can recurse into the operand to combine more things.
21833 switch (Op.getOpcode()) {
21834 case X86ISD::PSHUFB:
21836 case X86ISD::PSHUFD:
21837 case X86ISD::PSHUFHW:
21838 case X86ISD::PSHUFLW:
21839 if (Op.getOperand(0).hasOneUse() &&
21840 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21841 HasPSHUFB, DAG, DCI, Subtarget))
21845 case X86ISD::UNPCKL:
21846 case X86ISD::UNPCKH:
21847 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21848 // We can't check for single use, we have to check that this shuffle is the only user.
21849 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21850 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21851 HasPSHUFB, DAG, DCI, Subtarget))
21856 // Minor canonicalization of the accumulated shuffle mask to make it easier
21857 // to match below. All this does is detect masks with squential pairs of
21858 // elements, and shrink them to the half-width mask. It does this in a loop
21859 // so it will reduce the size of the mask to the minimal width mask which
21860 // performs an equivalent shuffle.
21861 SmallVector<int, 16> WidenedMask;
21862 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21863 Mask = std::move(WidenedMask);
21864 WidenedMask.clear();
21867 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21871 /// \brief Get the PSHUF-style mask from PSHUF node.
21873 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21874 /// PSHUF-style masks that can be reused with such instructions.
21875 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21876 SmallVector<int, 4> Mask;
21878 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21882 switch (N.getOpcode()) {
21883 case X86ISD::PSHUFD:
21885 case X86ISD::PSHUFLW:
21888 case X86ISD::PSHUFHW:
21889 Mask.erase(Mask.begin(), Mask.begin() + 4);
21890 for (int &M : Mask)
21894 llvm_unreachable("No valid shuffle instruction found!");
21898 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21900 /// We walk up the chain and look for a combinable shuffle, skipping over
21901 /// shuffles that we could hoist this shuffle's transformation past without
21902 /// altering anything.
21904 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21906 TargetLowering::DAGCombinerInfo &DCI) {
21907 assert(N.getOpcode() == X86ISD::PSHUFD &&
21908 "Called with something other than an x86 128-bit half shuffle!");
21911 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21912 // of the shuffles in the chain so that we can form a fresh chain to replace
21914 SmallVector<SDValue, 8> Chain;
21915 SDValue V = N.getOperand(0);
21916 for (; V.hasOneUse(); V = V.getOperand(0)) {
21917 switch (V.getOpcode()) {
21919 return SDValue(); // Nothing combined!
21922 // Skip bitcasts as we always know the type for the target specific
21926 case X86ISD::PSHUFD:
21927 // Found another dword shuffle.
21930 case X86ISD::PSHUFLW:
21931 // Check that the low words (being shuffled) are the identity in the
21932 // dword shuffle, and the high words are self-contained.
21933 if (Mask[0] != 0 || Mask[1] != 1 ||
21934 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21937 Chain.push_back(V);
21940 case X86ISD::PSHUFHW:
21941 // Check that the high words (being shuffled) are the identity in the
21942 // dword shuffle, and the low words are self-contained.
21943 if (Mask[2] != 2 || Mask[3] != 3 ||
21944 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21947 Chain.push_back(V);
21950 case X86ISD::UNPCKL:
21951 case X86ISD::UNPCKH:
21952 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21953 // shuffle into a preceding word shuffle.
21954 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21957 // Search for a half-shuffle which we can combine with.
21958 unsigned CombineOp =
21959 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21960 if (V.getOperand(0) != V.getOperand(1) ||
21961 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21963 Chain.push_back(V);
21964 V = V.getOperand(0);
21966 switch (V.getOpcode()) {
21968 return SDValue(); // Nothing to combine.
21970 case X86ISD::PSHUFLW:
21971 case X86ISD::PSHUFHW:
21972 if (V.getOpcode() == CombineOp)
21975 Chain.push_back(V);
21979 V = V.getOperand(0);
21983 } while (V.hasOneUse());
21986 // Break out of the loop if we break out of the switch.
21990 if (!V.hasOneUse())
21991 // We fell out of the loop without finding a viable combining instruction.
21994 // Merge this node's mask and our incoming mask.
21995 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21996 for (int &M : Mask)
21998 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21999 getV4X86ShuffleImm8ForMask(Mask, DAG));
22001 // Rebuild the chain around this new shuffle.
22002 while (!Chain.empty()) {
22003 SDValue W = Chain.pop_back_val();
22005 if (V.getValueType() != W.getOperand(0).getValueType())
22006 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22008 switch (W.getOpcode()) {
22010 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22012 case X86ISD::UNPCKL:
22013 case X86ISD::UNPCKH:
22014 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22017 case X86ISD::PSHUFD:
22018 case X86ISD::PSHUFLW:
22019 case X86ISD::PSHUFHW:
22020 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22024 if (V.getValueType() != N.getValueType())
22025 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22027 // Return the new chain to replace N.
22031 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22033 /// We walk up the chain, skipping shuffles of the other half and looking
22034 /// through shuffles which switch halves trying to find a shuffle of the same
22035 /// pair of dwords.
22036 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22038 TargetLowering::DAGCombinerInfo &DCI) {
22040 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22041 "Called with something other than an x86 128-bit half shuffle!");
22043 unsigned CombineOpcode = N.getOpcode();
22045 // Walk up a single-use chain looking for a combinable shuffle.
22046 SDValue V = N.getOperand(0);
22047 for (; V.hasOneUse(); V = V.getOperand(0)) {
22048 switch (V.getOpcode()) {
22050 return false; // Nothing combined!
22053 // Skip bitcasts as we always know the type for the target specific
22057 case X86ISD::PSHUFLW:
22058 case X86ISD::PSHUFHW:
22059 if (V.getOpcode() == CombineOpcode)
22062 // Other-half shuffles are no-ops.
22065 // Break out of the loop if we break out of the switch.
22069 if (!V.hasOneUse())
22070 // We fell out of the loop without finding a viable combining instruction.
22073 // Combine away the bottom node as its shuffle will be accumulated into
22074 // a preceding shuffle.
22075 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22077 // Record the old value.
22080 // Merge this node's mask and our incoming mask (adjusted to account for all
22081 // the pshufd instructions encountered).
22082 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22083 for (int &M : Mask)
22085 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22086 getV4X86ShuffleImm8ForMask(Mask, DAG));
22088 // Check that the shuffles didn't cancel each other out. If not, we need to
22089 // combine to the new one.
22091 // Replace the combinable shuffle with the combined one, updating all users
22092 // so that we re-evaluate the chain here.
22093 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22098 /// \brief Try to combine x86 target specific shuffles.
22099 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22100 TargetLowering::DAGCombinerInfo &DCI,
22101 const X86Subtarget *Subtarget) {
22103 MVT VT = N.getSimpleValueType();
22104 SmallVector<int, 4> Mask;
22106 switch (N.getOpcode()) {
22107 case X86ISD::PSHUFD:
22108 case X86ISD::PSHUFLW:
22109 case X86ISD::PSHUFHW:
22110 Mask = getPSHUFShuffleMask(N);
22111 assert(Mask.size() == 4);
22117 // Nuke no-op shuffles that show up after combining.
22118 if (isNoopShuffleMask(Mask))
22119 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22121 // Look for simplifications involving one or two shuffle instructions.
22122 SDValue V = N.getOperand(0);
22123 switch (N.getOpcode()) {
22126 case X86ISD::PSHUFLW:
22127 case X86ISD::PSHUFHW:
22128 assert(VT == MVT::v8i16);
22131 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22132 return SDValue(); // We combined away this shuffle, so we're done.
22134 // See if this reduces to a PSHUFD which is no more expensive and can
22135 // combine with more operations. Note that it has to at least flip the
22136 // dwords as otherwise it would have been removed as a no-op.
22137 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22138 int DMask[] = {0, 1, 2, 3};
22139 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22140 DMask[DOffset + 0] = DOffset + 1;
22141 DMask[DOffset + 1] = DOffset + 0;
22142 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22143 DCI.AddToWorklist(V.getNode());
22144 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22145 getV4X86ShuffleImm8ForMask(DMask, DAG));
22146 DCI.AddToWorklist(V.getNode());
22147 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22150 // Look for shuffle patterns which can be implemented as a single unpack.
22151 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22152 // only works when we have a PSHUFD followed by two half-shuffles.
22153 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22154 (V.getOpcode() == X86ISD::PSHUFLW ||
22155 V.getOpcode() == X86ISD::PSHUFHW) &&
22156 V.getOpcode() != N.getOpcode() &&
22158 SDValue D = V.getOperand(0);
22159 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22160 D = D.getOperand(0);
22161 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22162 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22163 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22164 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22165 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22167 for (int i = 0; i < 4; ++i) {
22168 WordMask[i + NOffset] = Mask[i] + NOffset;
22169 WordMask[i + VOffset] = VMask[i] + VOffset;
22171 // Map the word mask through the DWord mask.
22173 for (int i = 0; i < 8; ++i)
22174 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22175 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22176 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22177 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22178 std::begin(UnpackLoMask)) ||
22179 std::equal(std::begin(MappedMask), std::end(MappedMask),
22180 std::begin(UnpackHiMask))) {
22181 // We can replace all three shuffles with an unpack.
22182 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22183 DCI.AddToWorklist(V.getNode());
22184 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22186 DL, MVT::v8i16, V, V);
22193 case X86ISD::PSHUFD:
22194 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22203 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22205 /// We combine this directly on the abstract vector shuffle nodes so it is
22206 /// easier to generically match. We also insert dummy vector shuffle nodes for
22207 /// the operands which explicitly discard the lanes which are unused by this
22208 /// operation to try to flow through the rest of the combiner the fact that
22209 /// they're unused.
22210 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22212 EVT VT = N->getValueType(0);
22214 // We only handle target-independent shuffles.
22215 // FIXME: It would be easy and harmless to use the target shuffle mask
22216 // extraction tool to support more.
22217 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22220 auto *SVN = cast<ShuffleVectorSDNode>(N);
22221 ArrayRef<int> Mask = SVN->getMask();
22222 SDValue V1 = N->getOperand(0);
22223 SDValue V2 = N->getOperand(1);
22225 // We require the first shuffle operand to be the SUB node, and the second to
22226 // be the ADD node.
22227 // FIXME: We should support the commuted patterns.
22228 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22231 // If there are other uses of these operations we can't fold them.
22232 if (!V1->hasOneUse() || !V2->hasOneUse())
22235 // Ensure that both operations have the same operands. Note that we can
22236 // commute the FADD operands.
22237 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22238 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22239 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22242 // We're looking for blends between FADD and FSUB nodes. We insist on these
22243 // nodes being lined up in a specific expected pattern.
22244 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22245 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22246 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22249 // Only specific types are legal at this point, assert so we notice if and
22250 // when these change.
22251 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22252 VT == MVT::v4f64) &&
22253 "Unknown vector type encountered!");
22255 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22258 /// PerformShuffleCombine - Performs several different shuffle combines.
22259 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22260 TargetLowering::DAGCombinerInfo &DCI,
22261 const X86Subtarget *Subtarget) {
22263 SDValue N0 = N->getOperand(0);
22264 SDValue N1 = N->getOperand(1);
22265 EVT VT = N->getValueType(0);
22267 // Don't create instructions with illegal types after legalize types has run.
22268 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22269 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22272 // If we have legalized the vector types, look for blends of FADD and FSUB
22273 // nodes that we can fuse into an ADDSUB node.
22274 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22275 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22278 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22279 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22280 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22281 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22283 // During Type Legalization, when promoting illegal vector types,
22284 // the backend might introduce new shuffle dag nodes and bitcasts.
22286 // This code performs the following transformation:
22287 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22288 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22290 // We do this only if both the bitcast and the BINOP dag nodes have
22291 // one use. Also, perform this transformation only if the new binary
22292 // operation is legal. This is to avoid introducing dag nodes that
22293 // potentially need to be further expanded (or custom lowered) into a
22294 // less optimal sequence of dag nodes.
22295 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22296 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22297 N0.getOpcode() == ISD::BITCAST) {
22298 SDValue BC0 = N0.getOperand(0);
22299 EVT SVT = BC0.getValueType();
22300 unsigned Opcode = BC0.getOpcode();
22301 unsigned NumElts = VT.getVectorNumElements();
22303 if (BC0.hasOneUse() && SVT.isVector() &&
22304 SVT.getVectorNumElements() * 2 == NumElts &&
22305 TLI.isOperationLegal(Opcode, VT)) {
22306 bool CanFold = false;
22318 unsigned SVTNumElts = SVT.getVectorNumElements();
22319 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22320 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22321 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22322 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22323 CanFold = SVOp->getMaskElt(i) < 0;
22326 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22327 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22328 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22329 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22334 // Only handle 128 wide vector from here on.
22335 if (!VT.is128BitVector())
22338 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22339 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22340 // consecutive, non-overlapping, and in the right order.
22341 SmallVector<SDValue, 16> Elts;
22342 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22343 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22345 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22349 if (isTargetShuffle(N->getOpcode())) {
22351 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22352 if (Shuffle.getNode())
22355 // Try recursively combining arbitrary sequences of x86 shuffle
22356 // instructions into higher-order shuffles. We do this after combining
22357 // specific PSHUF instruction sequences into their minimal form so that we
22358 // can evaluate how many specialized shuffle instructions are involved in
22359 // a particular chain.
22360 SmallVector<int, 1> NonceMask; // Just a placeholder.
22361 NonceMask.push_back(0);
22362 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22363 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22365 return SDValue(); // This routine will use CombineTo to replace N.
22371 /// PerformTruncateCombine - Converts truncate operation to
22372 /// a sequence of vector shuffle operations.
22373 /// It is possible when we truncate 256-bit vector to 128-bit vector
22374 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22375 TargetLowering::DAGCombinerInfo &DCI,
22376 const X86Subtarget *Subtarget) {
22380 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22381 /// specific shuffle of a load can be folded into a single element load.
22382 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22383 /// shuffles have been custom lowered so we need to handle those here.
22384 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22385 TargetLowering::DAGCombinerInfo &DCI) {
22386 if (DCI.isBeforeLegalizeOps())
22389 SDValue InVec = N->getOperand(0);
22390 SDValue EltNo = N->getOperand(1);
22392 if (!isa<ConstantSDNode>(EltNo))
22395 EVT OriginalVT = InVec.getValueType();
22397 if (InVec.getOpcode() == ISD::BITCAST) {
22398 // Don't duplicate a load with other uses.
22399 if (!InVec.hasOneUse())
22401 EVT BCVT = InVec.getOperand(0).getValueType();
22402 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22404 InVec = InVec.getOperand(0);
22407 EVT CurrentVT = InVec.getValueType();
22409 if (!isTargetShuffle(InVec.getOpcode()))
22412 // Don't duplicate a load with other uses.
22413 if (!InVec.hasOneUse())
22416 SmallVector<int, 16> ShuffleMask;
22418 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22419 ShuffleMask, UnaryShuffle))
22422 // Select the input vector, guarding against out of range extract vector.
22423 unsigned NumElems = CurrentVT.getVectorNumElements();
22424 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22425 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22426 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22427 : InVec.getOperand(1);
22429 // If inputs to shuffle are the same for both ops, then allow 2 uses
22430 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22432 if (LdNode.getOpcode() == ISD::BITCAST) {
22433 // Don't duplicate a load with other uses.
22434 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22437 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22438 LdNode = LdNode.getOperand(0);
22441 if (!ISD::isNormalLoad(LdNode.getNode()))
22444 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22446 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22449 EVT EltVT = N->getValueType(0);
22450 // If there's a bitcast before the shuffle, check if the load type and
22451 // alignment is valid.
22452 unsigned Align = LN0->getAlignment();
22453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22454 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22455 EltVT.getTypeForEVT(*DAG.getContext()));
22457 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22460 // All checks match so transform back to vector_shuffle so that DAG combiner
22461 // can finish the job
22464 // Create shuffle node taking into account the case that its a unary shuffle
22465 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22466 : InVec.getOperand(1);
22467 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22468 InVec.getOperand(0), Shuffle,
22470 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22475 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22476 /// generation and convert it from being a bunch of shuffles and extracts
22477 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22478 /// storing the value and loading scalars back, while for x64 we should
22479 /// use 64-bit extracts and shifts.
22480 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22481 TargetLowering::DAGCombinerInfo &DCI) {
22482 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22483 if (NewOp.getNode())
22486 SDValue InputVector = N->getOperand(0);
22488 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22489 // from mmx to v2i32 has a single usage.
22490 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22491 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22492 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22493 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22494 N->getValueType(0),
22495 InputVector.getNode()->getOperand(0));
22497 // Only operate on vectors of 4 elements, where the alternative shuffling
22498 // gets to be more expensive.
22499 if (InputVector.getValueType() != MVT::v4i32)
22502 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22503 // single use which is a sign-extend or zero-extend, and all elements are
22505 SmallVector<SDNode *, 4> Uses;
22506 unsigned ExtractedElements = 0;
22507 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22508 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22509 if (UI.getUse().getResNo() != InputVector.getResNo())
22512 SDNode *Extract = *UI;
22513 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22516 if (Extract->getValueType(0) != MVT::i32)
22518 if (!Extract->hasOneUse())
22520 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22521 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22523 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22526 // Record which element was extracted.
22527 ExtractedElements |=
22528 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22530 Uses.push_back(Extract);
22533 // If not all the elements were used, this may not be worthwhile.
22534 if (ExtractedElements != 15)
22537 // Ok, we've now decided to do the transformation.
22538 // If 64-bit shifts are legal, use the extract-shift sequence,
22539 // otherwise bounce the vector off the cache.
22540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22542 SDLoc dl(InputVector);
22544 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22545 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22546 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22547 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22548 DAG.getConstant(0, VecIdxTy));
22549 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22550 DAG.getConstant(1, VecIdxTy));
22552 SDValue ShAmt = DAG.getConstant(32,
22553 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22554 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22555 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22556 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22557 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22558 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22559 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22561 // Store the value to a temporary stack slot.
22562 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22563 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22564 MachinePointerInfo(), false, false, 0);
22566 EVT ElementType = InputVector.getValueType().getVectorElementType();
22567 unsigned EltSize = ElementType.getSizeInBits() / 8;
22569 // Replace each use (extract) with a load of the appropriate element.
22570 for (unsigned i = 0; i < 4; ++i) {
22571 uint64_t Offset = EltSize * i;
22572 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22574 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22575 StackPtr, OffsetVal);
22577 // Load the scalar.
22578 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22579 ScalarAddr, MachinePointerInfo(),
22580 false, false, false, 0);
22585 // Replace the extracts
22586 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22587 UE = Uses.end(); UI != UE; ++UI) {
22588 SDNode *Extract = *UI;
22590 SDValue Idx = Extract->getOperand(1);
22591 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22592 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22595 // The replacement was made in place; don't return anything.
22599 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22600 static std::pair<unsigned, bool>
22601 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22602 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22603 if (!VT.isVector())
22604 return std::make_pair(0, false);
22606 bool NeedSplit = false;
22607 switch (VT.getSimpleVT().SimpleTy) {
22608 default: return std::make_pair(0, false);
22611 if (!Subtarget->hasVLX())
22612 return std::make_pair(0, false);
22616 if (!Subtarget->hasBWI())
22617 return std::make_pair(0, false);
22621 if (!Subtarget->hasAVX512())
22622 return std::make_pair(0, false);
22627 if (!Subtarget->hasAVX2())
22629 if (!Subtarget->hasAVX())
22630 return std::make_pair(0, false);
22635 if (!Subtarget->hasSSE2())
22636 return std::make_pair(0, false);
22639 // SSE2 has only a small subset of the operations.
22640 bool hasUnsigned = Subtarget->hasSSE41() ||
22641 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22642 bool hasSigned = Subtarget->hasSSE41() ||
22643 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22645 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22648 // Check for x CC y ? x : y.
22649 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22650 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22655 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22658 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22661 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22664 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22666 // Check for x CC y ? y : x -- a min/max with reversed arms.
22667 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22668 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22673 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22676 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22679 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22682 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22686 return std::make_pair(Opc, NeedSplit);
22690 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22691 const X86Subtarget *Subtarget) {
22693 SDValue Cond = N->getOperand(0);
22694 SDValue LHS = N->getOperand(1);
22695 SDValue RHS = N->getOperand(2);
22697 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22698 SDValue CondSrc = Cond->getOperand(0);
22699 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22700 Cond = CondSrc->getOperand(0);
22703 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22706 // A vselect where all conditions and data are constants can be optimized into
22707 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22708 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22709 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22712 unsigned MaskValue = 0;
22713 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22716 MVT VT = N->getSimpleValueType(0);
22717 unsigned NumElems = VT.getVectorNumElements();
22718 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22719 for (unsigned i = 0; i < NumElems; ++i) {
22720 // Be sure we emit undef where we can.
22721 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22722 ShuffleMask[i] = -1;
22724 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22727 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22728 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22730 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22733 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22735 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22736 TargetLowering::DAGCombinerInfo &DCI,
22737 const X86Subtarget *Subtarget) {
22739 SDValue Cond = N->getOperand(0);
22740 // Get the LHS/RHS of the select.
22741 SDValue LHS = N->getOperand(1);
22742 SDValue RHS = N->getOperand(2);
22743 EVT VT = LHS.getValueType();
22744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22746 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22747 // instructions match the semantics of the common C idiom x<y?x:y but not
22748 // x<=y?x:y, because of how they handle negative zero (which can be
22749 // ignored in unsafe-math mode).
22750 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22751 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22752 (Subtarget->hasSSE2() ||
22753 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22754 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22756 unsigned Opcode = 0;
22757 // Check for x CC y ? x : y.
22758 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22759 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22763 // Converting this to a min would handle NaNs incorrectly, and swapping
22764 // the operands would cause it to handle comparisons between positive
22765 // and negative zero incorrectly.
22766 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22767 if (!DAG.getTarget().Options.UnsafeFPMath &&
22768 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22770 std::swap(LHS, RHS);
22772 Opcode = X86ISD::FMIN;
22775 // Converting this to a min would handle comparisons between positive
22776 // and negative zero incorrectly.
22777 if (!DAG.getTarget().Options.UnsafeFPMath &&
22778 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22780 Opcode = X86ISD::FMIN;
22783 // Converting this to a min would handle both negative zeros and NaNs
22784 // incorrectly, but we can swap the operands to fix both.
22785 std::swap(LHS, RHS);
22789 Opcode = X86ISD::FMIN;
22793 // Converting this to a max would handle comparisons between positive
22794 // and negative zero incorrectly.
22795 if (!DAG.getTarget().Options.UnsafeFPMath &&
22796 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22798 Opcode = X86ISD::FMAX;
22801 // Converting this to a max would handle NaNs incorrectly, and swapping
22802 // the operands would cause it to handle comparisons between positive
22803 // and negative zero incorrectly.
22804 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22805 if (!DAG.getTarget().Options.UnsafeFPMath &&
22806 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22808 std::swap(LHS, RHS);
22810 Opcode = X86ISD::FMAX;
22813 // Converting this to a max would handle both negative zeros and NaNs
22814 // incorrectly, but we can swap the operands to fix both.
22815 std::swap(LHS, RHS);
22819 Opcode = X86ISD::FMAX;
22822 // Check for x CC y ? y : x -- a min/max with reversed arms.
22823 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22824 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22828 // Converting this to a min would handle comparisons between positive
22829 // and negative zero incorrectly, and swapping the operands would
22830 // cause it to handle NaNs incorrectly.
22831 if (!DAG.getTarget().Options.UnsafeFPMath &&
22832 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22833 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22835 std::swap(LHS, RHS);
22837 Opcode = X86ISD::FMIN;
22840 // Converting this to a min would handle NaNs incorrectly.
22841 if (!DAG.getTarget().Options.UnsafeFPMath &&
22842 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22844 Opcode = X86ISD::FMIN;
22847 // Converting this to a min would handle both negative zeros and NaNs
22848 // incorrectly, but we can swap the operands to fix both.
22849 std::swap(LHS, RHS);
22853 Opcode = X86ISD::FMIN;
22857 // Converting this to a max would handle NaNs incorrectly.
22858 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22860 Opcode = X86ISD::FMAX;
22863 // Converting this to a max would handle comparisons between positive
22864 // and negative zero incorrectly, and swapping the operands would
22865 // cause it to handle NaNs incorrectly.
22866 if (!DAG.getTarget().Options.UnsafeFPMath &&
22867 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22868 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22870 std::swap(LHS, RHS);
22872 Opcode = X86ISD::FMAX;
22875 // Converting this to a max would handle both negative zeros and NaNs
22876 // incorrectly, but we can swap the operands to fix both.
22877 std::swap(LHS, RHS);
22881 Opcode = X86ISD::FMAX;
22887 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22890 EVT CondVT = Cond.getValueType();
22891 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22892 CondVT.getVectorElementType() == MVT::i1) {
22893 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22894 // lowering on KNL. In this case we convert it to
22895 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22896 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22897 // Since SKX these selects have a proper lowering.
22898 EVT OpVT = LHS.getValueType();
22899 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22900 (OpVT.getVectorElementType() == MVT::i8 ||
22901 OpVT.getVectorElementType() == MVT::i16) &&
22902 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22903 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22904 DCI.AddToWorklist(Cond.getNode());
22905 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22908 // If this is a select between two integer constants, try to do some
22910 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22911 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22912 // Don't do this for crazy integer types.
22913 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22914 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22915 // so that TrueC (the true value) is larger than FalseC.
22916 bool NeedsCondInvert = false;
22918 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22919 // Efficiently invertible.
22920 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22921 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22922 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22923 NeedsCondInvert = true;
22924 std::swap(TrueC, FalseC);
22927 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22928 if (FalseC->getAPIntValue() == 0 &&
22929 TrueC->getAPIntValue().isPowerOf2()) {
22930 if (NeedsCondInvert) // Invert the condition if needed.
22931 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22932 DAG.getConstant(1, Cond.getValueType()));
22934 // Zero extend the condition if needed.
22935 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22937 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22938 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22939 DAG.getConstant(ShAmt, MVT::i8));
22942 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22943 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22944 if (NeedsCondInvert) // Invert the condition if needed.
22945 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22946 DAG.getConstant(1, Cond.getValueType()));
22948 // Zero extend the condition if needed.
22949 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22950 FalseC->getValueType(0), Cond);
22951 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22952 SDValue(FalseC, 0));
22955 // Optimize cases that will turn into an LEA instruction. This requires
22956 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22957 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22958 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22959 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22961 bool isFastMultiplier = false;
22963 switch ((unsigned char)Diff) {
22965 case 1: // result = add base, cond
22966 case 2: // result = lea base( , cond*2)
22967 case 3: // result = lea base(cond, cond*2)
22968 case 4: // result = lea base( , cond*4)
22969 case 5: // result = lea base(cond, cond*4)
22970 case 8: // result = lea base( , cond*8)
22971 case 9: // result = lea base(cond, cond*8)
22972 isFastMultiplier = true;
22977 if (isFastMultiplier) {
22978 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22979 if (NeedsCondInvert) // Invert the condition if needed.
22980 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22981 DAG.getConstant(1, Cond.getValueType()));
22983 // Zero extend the condition if needed.
22984 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22986 // Scale the condition by the difference.
22988 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22989 DAG.getConstant(Diff, Cond.getValueType()));
22991 // Add the base if non-zero.
22992 if (FalseC->getAPIntValue() != 0)
22993 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22994 SDValue(FalseC, 0));
23001 // Canonicalize max and min:
23002 // (x > y) ? x : y -> (x >= y) ? x : y
23003 // (x < y) ? x : y -> (x <= y) ? x : y
23004 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23005 // the need for an extra compare
23006 // against zero. e.g.
23007 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23009 // testl %edi, %edi
23011 // cmovgl %edi, %eax
23015 // cmovsl %eax, %edi
23016 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23017 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23018 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23019 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23024 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23025 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23026 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23027 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23032 // Early exit check
23033 if (!TLI.isTypeLegal(VT))
23036 // Match VSELECTs into subs with unsigned saturation.
23037 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23038 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23039 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23040 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23041 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23043 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23044 // left side invert the predicate to simplify logic below.
23046 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23048 CC = ISD::getSetCCInverse(CC, true);
23049 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23053 if (Other.getNode() && Other->getNumOperands() == 2 &&
23054 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23055 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23056 SDValue CondRHS = Cond->getOperand(1);
23058 // Look for a general sub with unsigned saturation first.
23059 // x >= y ? x-y : 0 --> subus x, y
23060 // x > y ? x-y : 0 --> subus x, y
23061 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23062 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23063 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23065 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23066 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23067 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23068 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23069 // If the RHS is a constant we have to reverse the const
23070 // canonicalization.
23071 // x > C-1 ? x+-C : 0 --> subus x, C
23072 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23073 CondRHSConst->getAPIntValue() ==
23074 (-OpRHSConst->getAPIntValue() - 1))
23075 return DAG.getNode(
23076 X86ISD::SUBUS, DL, VT, OpLHS,
23077 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23079 // Another special case: If C was a sign bit, the sub has been
23080 // canonicalized into a xor.
23081 // FIXME: Would it be better to use computeKnownBits to determine
23082 // whether it's safe to decanonicalize the xor?
23083 // x s< 0 ? x^C : 0 --> subus x, C
23084 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23085 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23086 OpRHSConst->getAPIntValue().isSignBit())
23087 // Note that we have to rebuild the RHS constant here to ensure we
23088 // don't rely on particular values of undef lanes.
23089 return DAG.getNode(
23090 X86ISD::SUBUS, DL, VT, OpLHS,
23091 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23096 // Try to match a min/max vector operation.
23097 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23098 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23099 unsigned Opc = ret.first;
23100 bool NeedSplit = ret.second;
23102 if (Opc && NeedSplit) {
23103 unsigned NumElems = VT.getVectorNumElements();
23104 // Extract the LHS vectors
23105 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23106 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23108 // Extract the RHS vectors
23109 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23110 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23112 // Create min/max for each subvector
23113 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23114 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23116 // Merge the result
23117 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23119 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23122 // Simplify vector selection if condition value type matches vselect
23124 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23125 assert(Cond.getValueType().isVector() &&
23126 "vector select expects a vector selector!");
23128 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23129 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23131 // Try invert the condition if true value is not all 1s and false value
23133 if (!TValIsAllOnes && !FValIsAllZeros &&
23134 // Check if the selector will be produced by CMPP*/PCMP*
23135 Cond.getOpcode() == ISD::SETCC &&
23136 // Check if SETCC has already been promoted
23137 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23138 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23139 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23141 if (TValIsAllZeros || FValIsAllOnes) {
23142 SDValue CC = Cond.getOperand(2);
23143 ISD::CondCode NewCC =
23144 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23145 Cond.getOperand(0).getValueType().isInteger());
23146 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23147 std::swap(LHS, RHS);
23148 TValIsAllOnes = FValIsAllOnes;
23149 FValIsAllZeros = TValIsAllZeros;
23153 if (TValIsAllOnes || FValIsAllZeros) {
23156 if (TValIsAllOnes && FValIsAllZeros)
23158 else if (TValIsAllOnes)
23159 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23160 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23161 else if (FValIsAllZeros)
23162 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23163 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23165 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23169 // If we know that this node is legal then we know that it is going to be
23170 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23171 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23172 // to simplify previous instructions.
23173 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23174 !DCI.isBeforeLegalize() &&
23175 // We explicitly check against v8i16 and v16i16 because, although
23176 // they're marked as Custom, they might only be legal when Cond is a
23177 // build_vector of constants. This will be taken care in a later
23179 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23180 VT != MVT::v8i16) &&
23181 // Don't optimize vector of constants. Those are handled by
23182 // the generic code and all the bits must be properly set for
23183 // the generic optimizer.
23184 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23185 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23187 // Don't optimize vector selects that map to mask-registers.
23191 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23192 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23194 APInt KnownZero, KnownOne;
23195 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23196 DCI.isBeforeLegalizeOps());
23197 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23198 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23200 // If we changed the computation somewhere in the DAG, this change
23201 // will affect all users of Cond.
23202 // Make sure it is fine and update all the nodes so that we do not
23203 // use the generic VSELECT anymore. Otherwise, we may perform
23204 // wrong optimizations as we messed up with the actual expectation
23205 // for the vector boolean values.
23206 if (Cond != TLO.Old) {
23207 // Check all uses of that condition operand to check whether it will be
23208 // consumed by non-BLEND instructions, which may depend on all bits are
23210 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23212 if (I->getOpcode() != ISD::VSELECT)
23213 // TODO: Add other opcodes eventually lowered into BLEND.
23216 // Update all the users of the condition, before committing the change,
23217 // so that the VSELECT optimizations that expect the correct vector
23218 // boolean value will not be triggered.
23219 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23221 DAG.ReplaceAllUsesOfValueWith(
23223 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23224 Cond, I->getOperand(1), I->getOperand(2)));
23225 DCI.CommitTargetLoweringOpt(TLO);
23228 // At this point, only Cond is changed. Change the condition
23229 // just for N to keep the opportunity to optimize all other
23230 // users their own way.
23231 DAG.ReplaceAllUsesOfValueWith(
23233 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23234 TLO.New, N->getOperand(1), N->getOperand(2)));
23239 // We should generate an X86ISD::BLENDI from a vselect if its argument
23240 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23241 // constants. This specific pattern gets generated when we split a
23242 // selector for a 512 bit vector in a machine without AVX512 (but with
23243 // 256-bit vectors), during legalization:
23245 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23247 // Iff we find this pattern and the build_vectors are built from
23248 // constants, we translate the vselect into a shuffle_vector that we
23249 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23250 if ((N->getOpcode() == ISD::VSELECT ||
23251 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23252 !DCI.isBeforeLegalize()) {
23253 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23254 if (Shuffle.getNode())
23261 // Check whether a boolean test is testing a boolean value generated by
23262 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23265 // Simplify the following patterns:
23266 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23267 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23268 // to (Op EFLAGS Cond)
23270 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23271 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23272 // to (Op EFLAGS !Cond)
23274 // where Op could be BRCOND or CMOV.
23276 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23277 // Quit if not CMP and SUB with its value result used.
23278 if (Cmp.getOpcode() != X86ISD::CMP &&
23279 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23282 // Quit if not used as a boolean value.
23283 if (CC != X86::COND_E && CC != X86::COND_NE)
23286 // Check CMP operands. One of them should be 0 or 1 and the other should be
23287 // an SetCC or extended from it.
23288 SDValue Op1 = Cmp.getOperand(0);
23289 SDValue Op2 = Cmp.getOperand(1);
23292 const ConstantSDNode* C = nullptr;
23293 bool needOppositeCond = (CC == X86::COND_E);
23294 bool checkAgainstTrue = false; // Is it a comparison against 1?
23296 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23298 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23300 else // Quit if all operands are not constants.
23303 if (C->getZExtValue() == 1) {
23304 needOppositeCond = !needOppositeCond;
23305 checkAgainstTrue = true;
23306 } else if (C->getZExtValue() != 0)
23307 // Quit if the constant is neither 0 or 1.
23310 bool truncatedToBoolWithAnd = false;
23311 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23312 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23313 SetCC.getOpcode() == ISD::TRUNCATE ||
23314 SetCC.getOpcode() == ISD::AND) {
23315 if (SetCC.getOpcode() == ISD::AND) {
23317 ConstantSDNode *CS;
23318 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23319 CS->getZExtValue() == 1)
23321 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23322 CS->getZExtValue() == 1)
23326 SetCC = SetCC.getOperand(OpIdx);
23327 truncatedToBoolWithAnd = true;
23329 SetCC = SetCC.getOperand(0);
23332 switch (SetCC.getOpcode()) {
23333 case X86ISD::SETCC_CARRY:
23334 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23335 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23336 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23337 // truncated to i1 using 'and'.
23338 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23340 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23341 "Invalid use of SETCC_CARRY!");
23343 case X86ISD::SETCC:
23344 // Set the condition code or opposite one if necessary.
23345 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23346 if (needOppositeCond)
23347 CC = X86::GetOppositeBranchCondition(CC);
23348 return SetCC.getOperand(1);
23349 case X86ISD::CMOV: {
23350 // Check whether false/true value has canonical one, i.e. 0 or 1.
23351 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23352 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23353 // Quit if true value is not a constant.
23356 // Quit if false value is not a constant.
23358 SDValue Op = SetCC.getOperand(0);
23359 // Skip 'zext' or 'trunc' node.
23360 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23361 Op.getOpcode() == ISD::TRUNCATE)
23362 Op = Op.getOperand(0);
23363 // A special case for rdrand/rdseed, where 0 is set if false cond is
23365 if ((Op.getOpcode() != X86ISD::RDRAND &&
23366 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23369 // Quit if false value is not the constant 0 or 1.
23370 bool FValIsFalse = true;
23371 if (FVal && FVal->getZExtValue() != 0) {
23372 if (FVal->getZExtValue() != 1)
23374 // If FVal is 1, opposite cond is needed.
23375 needOppositeCond = !needOppositeCond;
23376 FValIsFalse = false;
23378 // Quit if TVal is not the constant opposite of FVal.
23379 if (FValIsFalse && TVal->getZExtValue() != 1)
23381 if (!FValIsFalse && TVal->getZExtValue() != 0)
23383 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23384 if (needOppositeCond)
23385 CC = X86::GetOppositeBranchCondition(CC);
23386 return SetCC.getOperand(3);
23393 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23394 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23395 TargetLowering::DAGCombinerInfo &DCI,
23396 const X86Subtarget *Subtarget) {
23399 // If the flag operand isn't dead, don't touch this CMOV.
23400 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23403 SDValue FalseOp = N->getOperand(0);
23404 SDValue TrueOp = N->getOperand(1);
23405 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23406 SDValue Cond = N->getOperand(3);
23408 if (CC == X86::COND_E || CC == X86::COND_NE) {
23409 switch (Cond.getOpcode()) {
23413 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23414 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23415 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23421 Flags = checkBoolTestSetCCCombine(Cond, CC);
23422 if (Flags.getNode() &&
23423 // Extra check as FCMOV only supports a subset of X86 cond.
23424 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23425 SDValue Ops[] = { FalseOp, TrueOp,
23426 DAG.getConstant(CC, MVT::i8), Flags };
23427 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23430 // If this is a select between two integer constants, try to do some
23431 // optimizations. Note that the operands are ordered the opposite of SELECT
23433 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23434 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23435 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23436 // larger than FalseC (the false value).
23437 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23438 CC = X86::GetOppositeBranchCondition(CC);
23439 std::swap(TrueC, FalseC);
23440 std::swap(TrueOp, FalseOp);
23443 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23444 // This is efficient for any integer data type (including i8/i16) and
23446 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23447 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23448 DAG.getConstant(CC, MVT::i8), Cond);
23450 // Zero extend the condition if needed.
23451 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23453 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23454 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23455 DAG.getConstant(ShAmt, MVT::i8));
23456 if (N->getNumValues() == 2) // Dead flag value?
23457 return DCI.CombineTo(N, Cond, SDValue());
23461 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23462 // for any integer data type, including i8/i16.
23463 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23464 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23465 DAG.getConstant(CC, MVT::i8), Cond);
23467 // Zero extend the condition if needed.
23468 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23469 FalseC->getValueType(0), Cond);
23470 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23471 SDValue(FalseC, 0));
23473 if (N->getNumValues() == 2) // Dead flag value?
23474 return DCI.CombineTo(N, Cond, SDValue());
23478 // Optimize cases that will turn into an LEA instruction. This requires
23479 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23480 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23481 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23482 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23484 bool isFastMultiplier = false;
23486 switch ((unsigned char)Diff) {
23488 case 1: // result = add base, cond
23489 case 2: // result = lea base( , cond*2)
23490 case 3: // result = lea base(cond, cond*2)
23491 case 4: // result = lea base( , cond*4)
23492 case 5: // result = lea base(cond, cond*4)
23493 case 8: // result = lea base( , cond*8)
23494 case 9: // result = lea base(cond, cond*8)
23495 isFastMultiplier = true;
23500 if (isFastMultiplier) {
23501 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23502 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23503 DAG.getConstant(CC, MVT::i8), Cond);
23504 // Zero extend the condition if needed.
23505 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23507 // Scale the condition by the difference.
23509 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23510 DAG.getConstant(Diff, Cond.getValueType()));
23512 // Add the base if non-zero.
23513 if (FalseC->getAPIntValue() != 0)
23514 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23515 SDValue(FalseC, 0));
23516 if (N->getNumValues() == 2) // Dead flag value?
23517 return DCI.CombineTo(N, Cond, SDValue());
23524 // Handle these cases:
23525 // (select (x != c), e, c) -> select (x != c), e, x),
23526 // (select (x == c), c, e) -> select (x == c), x, e)
23527 // where the c is an integer constant, and the "select" is the combination
23528 // of CMOV and CMP.
23530 // The rationale for this change is that the conditional-move from a constant
23531 // needs two instructions, however, conditional-move from a register needs
23532 // only one instruction.
23534 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23535 // some instruction-combining opportunities. This opt needs to be
23536 // postponed as late as possible.
23538 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23539 // the DCI.xxxx conditions are provided to postpone the optimization as
23540 // late as possible.
23542 ConstantSDNode *CmpAgainst = nullptr;
23543 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23544 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23545 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23547 if (CC == X86::COND_NE &&
23548 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23549 CC = X86::GetOppositeBranchCondition(CC);
23550 std::swap(TrueOp, FalseOp);
23553 if (CC == X86::COND_E &&
23554 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23555 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23556 DAG.getConstant(CC, MVT::i8), Cond };
23557 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23565 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23566 const X86Subtarget *Subtarget) {
23567 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23569 default: return SDValue();
23570 // SSE/AVX/AVX2 blend intrinsics.
23571 case Intrinsic::x86_avx2_pblendvb:
23572 case Intrinsic::x86_avx2_pblendw:
23573 case Intrinsic::x86_avx2_pblendd_128:
23574 case Intrinsic::x86_avx2_pblendd_256:
23575 // Don't try to simplify this intrinsic if we don't have AVX2.
23576 if (!Subtarget->hasAVX2())
23579 case Intrinsic::x86_avx_blend_pd_256:
23580 case Intrinsic::x86_avx_blend_ps_256:
23581 case Intrinsic::x86_avx_blendv_pd_256:
23582 case Intrinsic::x86_avx_blendv_ps_256:
23583 // Don't try to simplify this intrinsic if we don't have AVX.
23584 if (!Subtarget->hasAVX())
23587 case Intrinsic::x86_sse41_pblendw:
23588 case Intrinsic::x86_sse41_blendpd:
23589 case Intrinsic::x86_sse41_blendps:
23590 case Intrinsic::x86_sse41_blendvps:
23591 case Intrinsic::x86_sse41_blendvpd:
23592 case Intrinsic::x86_sse41_pblendvb: {
23593 SDValue Op0 = N->getOperand(1);
23594 SDValue Op1 = N->getOperand(2);
23595 SDValue Mask = N->getOperand(3);
23597 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23598 if (!Subtarget->hasSSE41())
23601 // fold (blend A, A, Mask) -> A
23604 // fold (blend A, B, allZeros) -> A
23605 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23607 // fold (blend A, B, allOnes) -> B
23608 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23611 // Simplify the case where the mask is a constant i32 value.
23612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23613 if (C->isNullValue())
23615 if (C->isAllOnesValue())
23622 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23623 case Intrinsic::x86_sse2_psrai_w:
23624 case Intrinsic::x86_sse2_psrai_d:
23625 case Intrinsic::x86_avx2_psrai_w:
23626 case Intrinsic::x86_avx2_psrai_d:
23627 case Intrinsic::x86_sse2_psra_w:
23628 case Intrinsic::x86_sse2_psra_d:
23629 case Intrinsic::x86_avx2_psra_w:
23630 case Intrinsic::x86_avx2_psra_d: {
23631 SDValue Op0 = N->getOperand(1);
23632 SDValue Op1 = N->getOperand(2);
23633 EVT VT = Op0.getValueType();
23634 assert(VT.isVector() && "Expected a vector type!");
23636 if (isa<BuildVectorSDNode>(Op1))
23637 Op1 = Op1.getOperand(0);
23639 if (!isa<ConstantSDNode>(Op1))
23642 EVT SVT = VT.getVectorElementType();
23643 unsigned SVTBits = SVT.getSizeInBits();
23645 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23646 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23647 uint64_t ShAmt = C.getZExtValue();
23649 // Don't try to convert this shift into a ISD::SRA if the shift
23650 // count is bigger than or equal to the element size.
23651 if (ShAmt >= SVTBits)
23654 // Trivial case: if the shift count is zero, then fold this
23655 // into the first operand.
23659 // Replace this packed shift intrinsic with a target independent
23661 SDValue Splat = DAG.getConstant(C, VT);
23662 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23667 /// PerformMulCombine - Optimize a single multiply with constant into two
23668 /// in order to implement it with two cheaper instructions, e.g.
23669 /// LEA + SHL, LEA + LEA.
23670 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23671 TargetLowering::DAGCombinerInfo &DCI) {
23672 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23675 EVT VT = N->getValueType(0);
23676 if (VT != MVT::i64)
23679 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23682 uint64_t MulAmt = C->getZExtValue();
23683 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23686 uint64_t MulAmt1 = 0;
23687 uint64_t MulAmt2 = 0;
23688 if ((MulAmt % 9) == 0) {
23690 MulAmt2 = MulAmt / 9;
23691 } else if ((MulAmt % 5) == 0) {
23693 MulAmt2 = MulAmt / 5;
23694 } else if ((MulAmt % 3) == 0) {
23696 MulAmt2 = MulAmt / 3;
23699 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23702 if (isPowerOf2_64(MulAmt2) &&
23703 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23704 // If second multiplifer is pow2, issue it first. We want the multiply by
23705 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23707 std::swap(MulAmt1, MulAmt2);
23710 if (isPowerOf2_64(MulAmt1))
23711 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23712 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23714 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23715 DAG.getConstant(MulAmt1, VT));
23717 if (isPowerOf2_64(MulAmt2))
23718 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23719 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23721 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23722 DAG.getConstant(MulAmt2, VT));
23724 // Do not add new nodes to DAG combiner worklist.
23725 DCI.CombineTo(N, NewMul, false);
23730 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23731 SDValue N0 = N->getOperand(0);
23732 SDValue N1 = N->getOperand(1);
23733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23734 EVT VT = N0.getValueType();
23736 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23737 // since the result of setcc_c is all zero's or all ones.
23738 if (VT.isInteger() && !VT.isVector() &&
23739 N1C && N0.getOpcode() == ISD::AND &&
23740 N0.getOperand(1).getOpcode() == ISD::Constant) {
23741 SDValue N00 = N0.getOperand(0);
23742 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23743 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23744 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23745 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23746 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23747 APInt ShAmt = N1C->getAPIntValue();
23748 Mask = Mask.shl(ShAmt);
23750 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23751 N00, DAG.getConstant(Mask, VT));
23755 // Hardware support for vector shifts is sparse which makes us scalarize the
23756 // vector operations in many cases. Also, on sandybridge ADD is faster than
23758 // (shl V, 1) -> add V,V
23759 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23760 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23761 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23762 // We shift all of the values by one. In many cases we do not have
23763 // hardware support for this operation. This is better expressed as an ADD
23765 if (N1SplatC->getZExtValue() == 1)
23766 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23772 /// \brief Returns a vector of 0s if the node in input is a vector logical
23773 /// shift by a constant amount which is known to be bigger than or equal
23774 /// to the vector element size in bits.
23775 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23776 const X86Subtarget *Subtarget) {
23777 EVT VT = N->getValueType(0);
23779 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23780 (!Subtarget->hasInt256() ||
23781 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23784 SDValue Amt = N->getOperand(1);
23786 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23787 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23788 APInt ShiftAmt = AmtSplat->getAPIntValue();
23789 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23791 // SSE2/AVX2 logical shifts always return a vector of 0s
23792 // if the shift amount is bigger than or equal to
23793 // the element size. The constant shift amount will be
23794 // encoded as a 8-bit immediate.
23795 if (ShiftAmt.trunc(8).uge(MaxAmount))
23796 return getZeroVector(VT, Subtarget, DAG, DL);
23802 /// PerformShiftCombine - Combine shifts.
23803 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23804 TargetLowering::DAGCombinerInfo &DCI,
23805 const X86Subtarget *Subtarget) {
23806 if (N->getOpcode() == ISD::SHL) {
23807 SDValue V = PerformSHLCombine(N, DAG);
23808 if (V.getNode()) return V;
23811 if (N->getOpcode() != ISD::SRA) {
23812 // Try to fold this logical shift into a zero vector.
23813 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23814 if (V.getNode()) return V;
23820 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23821 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23822 // and friends. Likewise for OR -> CMPNEQSS.
23823 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23824 TargetLowering::DAGCombinerInfo &DCI,
23825 const X86Subtarget *Subtarget) {
23828 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23829 // we're requiring SSE2 for both.
23830 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23831 SDValue N0 = N->getOperand(0);
23832 SDValue N1 = N->getOperand(1);
23833 SDValue CMP0 = N0->getOperand(1);
23834 SDValue CMP1 = N1->getOperand(1);
23837 // The SETCCs should both refer to the same CMP.
23838 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23841 SDValue CMP00 = CMP0->getOperand(0);
23842 SDValue CMP01 = CMP0->getOperand(1);
23843 EVT VT = CMP00.getValueType();
23845 if (VT == MVT::f32 || VT == MVT::f64) {
23846 bool ExpectingFlags = false;
23847 // Check for any users that want flags:
23848 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23849 !ExpectingFlags && UI != UE; ++UI)
23850 switch (UI->getOpcode()) {
23855 ExpectingFlags = true;
23857 case ISD::CopyToReg:
23858 case ISD::SIGN_EXTEND:
23859 case ISD::ZERO_EXTEND:
23860 case ISD::ANY_EXTEND:
23864 if (!ExpectingFlags) {
23865 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23866 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23868 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23869 X86::CondCode tmp = cc0;
23874 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23875 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23876 // FIXME: need symbolic constants for these magic numbers.
23877 // See X86ATTInstPrinter.cpp:printSSECC().
23878 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23879 if (Subtarget->hasAVX512()) {
23880 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23881 CMP01, DAG.getConstant(x86cc, MVT::i8));
23882 if (N->getValueType(0) != MVT::i1)
23883 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23887 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23888 CMP00.getValueType(), CMP00, CMP01,
23889 DAG.getConstant(x86cc, MVT::i8));
23891 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23892 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23894 if (is64BitFP && !Subtarget->is64Bit()) {
23895 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23896 // 64-bit integer, since that's not a legal type. Since
23897 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23898 // bits, but can do this little dance to extract the lowest 32 bits
23899 // and work with those going forward.
23900 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23902 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23904 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23905 Vector32, DAG.getIntPtrConstant(0));
23909 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23910 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23911 DAG.getConstant(1, IntVT));
23912 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23913 return OneBitOfTruth;
23921 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23922 /// so it can be folded inside ANDNP.
23923 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23924 EVT VT = N->getValueType(0);
23926 // Match direct AllOnes for 128 and 256-bit vectors
23927 if (ISD::isBuildVectorAllOnes(N))
23930 // Look through a bit convert.
23931 if (N->getOpcode() == ISD::BITCAST)
23932 N = N->getOperand(0).getNode();
23934 // Sometimes the operand may come from a insert_subvector building a 256-bit
23936 if (VT.is256BitVector() &&
23937 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23938 SDValue V1 = N->getOperand(0);
23939 SDValue V2 = N->getOperand(1);
23941 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23942 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23943 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23944 ISD::isBuildVectorAllOnes(V2.getNode()))
23951 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23952 // register. In most cases we actually compare or select YMM-sized registers
23953 // and mixing the two types creates horrible code. This method optimizes
23954 // some of the transition sequences.
23955 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23956 TargetLowering::DAGCombinerInfo &DCI,
23957 const X86Subtarget *Subtarget) {
23958 EVT VT = N->getValueType(0);
23959 if (!VT.is256BitVector())
23962 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23963 N->getOpcode() == ISD::ZERO_EXTEND ||
23964 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23966 SDValue Narrow = N->getOperand(0);
23967 EVT NarrowVT = Narrow->getValueType(0);
23968 if (!NarrowVT.is128BitVector())
23971 if (Narrow->getOpcode() != ISD::XOR &&
23972 Narrow->getOpcode() != ISD::AND &&
23973 Narrow->getOpcode() != ISD::OR)
23976 SDValue N0 = Narrow->getOperand(0);
23977 SDValue N1 = Narrow->getOperand(1);
23980 // The Left side has to be a trunc.
23981 if (N0.getOpcode() != ISD::TRUNCATE)
23984 // The type of the truncated inputs.
23985 EVT WideVT = N0->getOperand(0)->getValueType(0);
23989 // The right side has to be a 'trunc' or a constant vector.
23990 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23991 ConstantSDNode *RHSConstSplat = nullptr;
23992 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23993 RHSConstSplat = RHSBV->getConstantSplatNode();
23994 if (!RHSTrunc && !RHSConstSplat)
23997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23999 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24002 // Set N0 and N1 to hold the inputs to the new wide operation.
24003 N0 = N0->getOperand(0);
24004 if (RHSConstSplat) {
24005 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24006 SDValue(RHSConstSplat, 0));
24007 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24008 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24009 } else if (RHSTrunc) {
24010 N1 = N1->getOperand(0);
24013 // Generate the wide operation.
24014 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24015 unsigned Opcode = N->getOpcode();
24017 case ISD::ANY_EXTEND:
24019 case ISD::ZERO_EXTEND: {
24020 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24021 APInt Mask = APInt::getAllOnesValue(InBits);
24022 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24023 return DAG.getNode(ISD::AND, DL, VT,
24024 Op, DAG.getConstant(Mask, VT));
24026 case ISD::SIGN_EXTEND:
24027 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24028 Op, DAG.getValueType(NarrowVT));
24030 llvm_unreachable("Unexpected opcode");
24034 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24035 TargetLowering::DAGCombinerInfo &DCI,
24036 const X86Subtarget *Subtarget) {
24037 EVT VT = N->getValueType(0);
24038 if (DCI.isBeforeLegalizeOps())
24041 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24045 // Create BEXTR instructions
24046 // BEXTR is ((X >> imm) & (2**size-1))
24047 if (VT == MVT::i32 || VT == MVT::i64) {
24048 SDValue N0 = N->getOperand(0);
24049 SDValue N1 = N->getOperand(1);
24052 // Check for BEXTR.
24053 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24054 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24055 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24056 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24057 if (MaskNode && ShiftNode) {
24058 uint64_t Mask = MaskNode->getZExtValue();
24059 uint64_t Shift = ShiftNode->getZExtValue();
24060 if (isMask_64(Mask)) {
24061 uint64_t MaskSize = CountPopulation_64(Mask);
24062 if (Shift + MaskSize <= VT.getSizeInBits())
24063 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24064 DAG.getConstant(Shift | (MaskSize << 8), VT));
24072 // Want to form ANDNP nodes:
24073 // 1) In the hopes of then easily combining them with OR and AND nodes
24074 // to form PBLEND/PSIGN.
24075 // 2) To match ANDN packed intrinsics
24076 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24079 SDValue N0 = N->getOperand(0);
24080 SDValue N1 = N->getOperand(1);
24083 // Check LHS for vnot
24084 if (N0.getOpcode() == ISD::XOR &&
24085 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24086 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24087 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24089 // Check RHS for vnot
24090 if (N1.getOpcode() == ISD::XOR &&
24091 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24092 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24093 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24098 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24099 TargetLowering::DAGCombinerInfo &DCI,
24100 const X86Subtarget *Subtarget) {
24101 if (DCI.isBeforeLegalizeOps())
24104 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24108 SDValue N0 = N->getOperand(0);
24109 SDValue N1 = N->getOperand(1);
24110 EVT VT = N->getValueType(0);
24112 // look for psign/blend
24113 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24114 if (!Subtarget->hasSSSE3() ||
24115 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24118 // Canonicalize pandn to RHS
24119 if (N0.getOpcode() == X86ISD::ANDNP)
24121 // or (and (m, y), (pandn m, x))
24122 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24123 SDValue Mask = N1.getOperand(0);
24124 SDValue X = N1.getOperand(1);
24126 if (N0.getOperand(0) == Mask)
24127 Y = N0.getOperand(1);
24128 if (N0.getOperand(1) == Mask)
24129 Y = N0.getOperand(0);
24131 // Check to see if the mask appeared in both the AND and ANDNP and
24135 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24136 // Look through mask bitcast.
24137 if (Mask.getOpcode() == ISD::BITCAST)
24138 Mask = Mask.getOperand(0);
24139 if (X.getOpcode() == ISD::BITCAST)
24140 X = X.getOperand(0);
24141 if (Y.getOpcode() == ISD::BITCAST)
24142 Y = Y.getOperand(0);
24144 EVT MaskVT = Mask.getValueType();
24146 // Validate that the Mask operand is a vector sra node.
24147 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24148 // there is no psrai.b
24149 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24150 unsigned SraAmt = ~0;
24151 if (Mask.getOpcode() == ISD::SRA) {
24152 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24153 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24154 SraAmt = AmtConst->getZExtValue();
24155 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24156 SDValue SraC = Mask.getOperand(1);
24157 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24159 if ((SraAmt + 1) != EltBits)
24164 // Now we know we at least have a plendvb with the mask val. See if
24165 // we can form a psignb/w/d.
24166 // psign = x.type == y.type == mask.type && y = sub(0, x);
24167 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24168 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24169 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24170 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24171 "Unsupported VT for PSIGN");
24172 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24173 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24175 // PBLENDVB only available on SSE 4.1
24176 if (!Subtarget->hasSSE41())
24179 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24181 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24182 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24183 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24184 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24185 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24189 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24192 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24193 MachineFunction &MF = DAG.getMachineFunction();
24194 bool OptForSize = MF.getFunction()->getAttributes().
24195 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24197 // SHLD/SHRD instructions have lower register pressure, but on some
24198 // platforms they have higher latency than the equivalent
24199 // series of shifts/or that would otherwise be generated.
24200 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24201 // have higher latencies and we are not optimizing for size.
24202 if (!OptForSize && Subtarget->isSHLDSlow())
24205 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24207 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24209 if (!N0.hasOneUse() || !N1.hasOneUse())
24212 SDValue ShAmt0 = N0.getOperand(1);
24213 if (ShAmt0.getValueType() != MVT::i8)
24215 SDValue ShAmt1 = N1.getOperand(1);
24216 if (ShAmt1.getValueType() != MVT::i8)
24218 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24219 ShAmt0 = ShAmt0.getOperand(0);
24220 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24221 ShAmt1 = ShAmt1.getOperand(0);
24224 unsigned Opc = X86ISD::SHLD;
24225 SDValue Op0 = N0.getOperand(0);
24226 SDValue Op1 = N1.getOperand(0);
24227 if (ShAmt0.getOpcode() == ISD::SUB) {
24228 Opc = X86ISD::SHRD;
24229 std::swap(Op0, Op1);
24230 std::swap(ShAmt0, ShAmt1);
24233 unsigned Bits = VT.getSizeInBits();
24234 if (ShAmt1.getOpcode() == ISD::SUB) {
24235 SDValue Sum = ShAmt1.getOperand(0);
24236 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24237 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24238 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24239 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24240 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24241 return DAG.getNode(Opc, DL, VT,
24243 DAG.getNode(ISD::TRUNCATE, DL,
24246 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24247 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24249 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24250 return DAG.getNode(Opc, DL, VT,
24251 N0.getOperand(0), N1.getOperand(0),
24252 DAG.getNode(ISD::TRUNCATE, DL,
24259 // Generate NEG and CMOV for integer abs.
24260 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24261 EVT VT = N->getValueType(0);
24263 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24264 // 8-bit integer abs to NEG and CMOV.
24265 if (VT.isInteger() && VT.getSizeInBits() == 8)
24268 SDValue N0 = N->getOperand(0);
24269 SDValue N1 = N->getOperand(1);
24272 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24273 // and change it to SUB and CMOV.
24274 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24275 N0.getOpcode() == ISD::ADD &&
24276 N0.getOperand(1) == N1 &&
24277 N1.getOpcode() == ISD::SRA &&
24278 N1.getOperand(0) == N0.getOperand(0))
24279 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24280 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24281 // Generate SUB & CMOV.
24282 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24283 DAG.getConstant(0, VT), N0.getOperand(0));
24285 SDValue Ops[] = { N0.getOperand(0), Neg,
24286 DAG.getConstant(X86::COND_GE, MVT::i8),
24287 SDValue(Neg.getNode(), 1) };
24288 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24293 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24294 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24295 TargetLowering::DAGCombinerInfo &DCI,
24296 const X86Subtarget *Subtarget) {
24297 if (DCI.isBeforeLegalizeOps())
24300 if (Subtarget->hasCMov()) {
24301 SDValue RV = performIntegerAbsCombine(N, DAG);
24309 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24310 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24311 TargetLowering::DAGCombinerInfo &DCI,
24312 const X86Subtarget *Subtarget) {
24313 LoadSDNode *Ld = cast<LoadSDNode>(N);
24314 EVT RegVT = Ld->getValueType(0);
24315 EVT MemVT = Ld->getMemoryVT();
24317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24319 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24320 // into two 16-byte operations.
24321 ISD::LoadExtType Ext = Ld->getExtensionType();
24322 unsigned Alignment = Ld->getAlignment();
24323 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24324 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24325 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24326 unsigned NumElems = RegVT.getVectorNumElements();
24330 SDValue Ptr = Ld->getBasePtr();
24331 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24333 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24335 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24336 Ld->getPointerInfo(), Ld->isVolatile(),
24337 Ld->isNonTemporal(), Ld->isInvariant(),
24339 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24340 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24341 Ld->getPointerInfo(), Ld->isVolatile(),
24342 Ld->isNonTemporal(), Ld->isInvariant(),
24343 std::min(16U, Alignment));
24344 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24346 Load2.getValue(1));
24348 SDValue NewVec = DAG.getUNDEF(RegVT);
24349 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24350 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24351 return DCI.CombineTo(N, NewVec, TF, true);
24357 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24358 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24359 const X86Subtarget *Subtarget) {
24360 StoreSDNode *St = cast<StoreSDNode>(N);
24361 EVT VT = St->getValue().getValueType();
24362 EVT StVT = St->getMemoryVT();
24364 SDValue StoredVal = St->getOperand(1);
24365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24367 // If we are saving a concatenation of two XMM registers and 32-byte stores
24368 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24369 unsigned Alignment = St->getAlignment();
24370 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24371 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24372 StVT == VT && !IsAligned) {
24373 unsigned NumElems = VT.getVectorNumElements();
24377 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24378 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24380 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24381 SDValue Ptr0 = St->getBasePtr();
24382 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24384 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24385 St->getPointerInfo(), St->isVolatile(),
24386 St->isNonTemporal(), Alignment);
24387 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24388 St->getPointerInfo(), St->isVolatile(),
24389 St->isNonTemporal(),
24390 std::min(16U, Alignment));
24391 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24394 // Optimize trunc store (of multiple scalars) to shuffle and store.
24395 // First, pack all of the elements in one place. Next, store to memory
24396 // in fewer chunks.
24397 if (St->isTruncatingStore() && VT.isVector()) {
24398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24399 unsigned NumElems = VT.getVectorNumElements();
24400 assert(StVT != VT && "Cannot truncate to the same type");
24401 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24402 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24404 // From, To sizes and ElemCount must be pow of two
24405 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24406 // We are going to use the original vector elt for storing.
24407 // Accumulated smaller vector elements must be a multiple of the store size.
24408 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24410 unsigned SizeRatio = FromSz / ToSz;
24412 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24414 // Create a type on which we perform the shuffle
24415 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24416 StVT.getScalarType(), NumElems*SizeRatio);
24418 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24420 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24421 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24422 for (unsigned i = 0; i != NumElems; ++i)
24423 ShuffleVec[i] = i * SizeRatio;
24425 // Can't shuffle using an illegal type.
24426 if (!TLI.isTypeLegal(WideVecVT))
24429 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24430 DAG.getUNDEF(WideVecVT),
24432 // At this point all of the data is stored at the bottom of the
24433 // register. We now need to save it to mem.
24435 // Find the largest store unit
24436 MVT StoreType = MVT::i8;
24437 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24438 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24439 MVT Tp = (MVT::SimpleValueType)tp;
24440 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24444 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24445 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24446 (64 <= NumElems * ToSz))
24447 StoreType = MVT::f64;
24449 // Bitcast the original vector into a vector of store-size units
24450 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24451 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24452 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24453 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24454 SmallVector<SDValue, 8> Chains;
24455 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24456 TLI.getPointerTy());
24457 SDValue Ptr = St->getBasePtr();
24459 // Perform one or more big stores into memory.
24460 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24461 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24462 StoreType, ShuffWide,
24463 DAG.getIntPtrConstant(i));
24464 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24465 St->getPointerInfo(), St->isVolatile(),
24466 St->isNonTemporal(), St->getAlignment());
24467 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24468 Chains.push_back(Ch);
24471 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24474 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24475 // the FP state in cases where an emms may be missing.
24476 // A preferable solution to the general problem is to figure out the right
24477 // places to insert EMMS. This qualifies as a quick hack.
24479 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24480 if (VT.getSizeInBits() != 64)
24483 const Function *F = DAG.getMachineFunction().getFunction();
24484 bool NoImplicitFloatOps = F->getAttributes().
24485 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24486 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24487 && Subtarget->hasSSE2();
24488 if ((VT.isVector() ||
24489 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24490 isa<LoadSDNode>(St->getValue()) &&
24491 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24492 St->getChain().hasOneUse() && !St->isVolatile()) {
24493 SDNode* LdVal = St->getValue().getNode();
24494 LoadSDNode *Ld = nullptr;
24495 int TokenFactorIndex = -1;
24496 SmallVector<SDValue, 8> Ops;
24497 SDNode* ChainVal = St->getChain().getNode();
24498 // Must be a store of a load. We currently handle two cases: the load
24499 // is a direct child, and it's under an intervening TokenFactor. It is
24500 // possible to dig deeper under nested TokenFactors.
24501 if (ChainVal == LdVal)
24502 Ld = cast<LoadSDNode>(St->getChain());
24503 else if (St->getValue().hasOneUse() &&
24504 ChainVal->getOpcode() == ISD::TokenFactor) {
24505 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24506 if (ChainVal->getOperand(i).getNode() == LdVal) {
24507 TokenFactorIndex = i;
24508 Ld = cast<LoadSDNode>(St->getValue());
24510 Ops.push_back(ChainVal->getOperand(i));
24514 if (!Ld || !ISD::isNormalLoad(Ld))
24517 // If this is not the MMX case, i.e. we are just turning i64 load/store
24518 // into f64 load/store, avoid the transformation if there are multiple
24519 // uses of the loaded value.
24520 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24525 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24526 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24528 if (Subtarget->is64Bit() || F64IsLegal) {
24529 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24530 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24531 Ld->getPointerInfo(), Ld->isVolatile(),
24532 Ld->isNonTemporal(), Ld->isInvariant(),
24533 Ld->getAlignment());
24534 SDValue NewChain = NewLd.getValue(1);
24535 if (TokenFactorIndex != -1) {
24536 Ops.push_back(NewChain);
24537 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24539 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24540 St->getPointerInfo(),
24541 St->isVolatile(), St->isNonTemporal(),
24542 St->getAlignment());
24545 // Otherwise, lower to two pairs of 32-bit loads / stores.
24546 SDValue LoAddr = Ld->getBasePtr();
24547 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24548 DAG.getConstant(4, MVT::i32));
24550 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24551 Ld->getPointerInfo(),
24552 Ld->isVolatile(), Ld->isNonTemporal(),
24553 Ld->isInvariant(), Ld->getAlignment());
24554 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24555 Ld->getPointerInfo().getWithOffset(4),
24556 Ld->isVolatile(), Ld->isNonTemporal(),
24558 MinAlign(Ld->getAlignment(), 4));
24560 SDValue NewChain = LoLd.getValue(1);
24561 if (TokenFactorIndex != -1) {
24562 Ops.push_back(LoLd);
24563 Ops.push_back(HiLd);
24564 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24567 LoAddr = St->getBasePtr();
24568 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24569 DAG.getConstant(4, MVT::i32));
24571 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24572 St->getPointerInfo(),
24573 St->isVolatile(), St->isNonTemporal(),
24574 St->getAlignment());
24575 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24576 St->getPointerInfo().getWithOffset(4),
24578 St->isNonTemporal(),
24579 MinAlign(St->getAlignment(), 4));
24580 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24585 /// Return 'true' if this vector operation is "horizontal"
24586 /// and return the operands for the horizontal operation in LHS and RHS. A
24587 /// horizontal operation performs the binary operation on successive elements
24588 /// of its first operand, then on successive elements of its second operand,
24589 /// returning the resulting values in a vector. For example, if
24590 /// A = < float a0, float a1, float a2, float a3 >
24592 /// B = < float b0, float b1, float b2, float b3 >
24593 /// then the result of doing a horizontal operation on A and B is
24594 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24595 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24596 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24597 /// set to A, RHS to B, and the routine returns 'true'.
24598 /// Note that the binary operation should have the property that if one of the
24599 /// operands is UNDEF then the result is UNDEF.
24600 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24601 // Look for the following pattern: if
24602 // A = < float a0, float a1, float a2, float a3 >
24603 // B = < float b0, float b1, float b2, float b3 >
24605 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24606 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24607 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24608 // which is A horizontal-op B.
24610 // At least one of the operands should be a vector shuffle.
24611 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24612 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24615 MVT VT = LHS.getSimpleValueType();
24617 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24618 "Unsupported vector type for horizontal add/sub");
24620 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24621 // operate independently on 128-bit lanes.
24622 unsigned NumElts = VT.getVectorNumElements();
24623 unsigned NumLanes = VT.getSizeInBits()/128;
24624 unsigned NumLaneElts = NumElts / NumLanes;
24625 assert((NumLaneElts % 2 == 0) &&
24626 "Vector type should have an even number of elements in each lane");
24627 unsigned HalfLaneElts = NumLaneElts/2;
24629 // View LHS in the form
24630 // LHS = VECTOR_SHUFFLE A, B, LMask
24631 // If LHS is not a shuffle then pretend it is the shuffle
24632 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24633 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24636 SmallVector<int, 16> LMask(NumElts);
24637 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24638 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24639 A = LHS.getOperand(0);
24640 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24641 B = LHS.getOperand(1);
24642 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24643 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24645 if (LHS.getOpcode() != ISD::UNDEF)
24647 for (unsigned i = 0; i != NumElts; ++i)
24651 // Likewise, view RHS in the form
24652 // RHS = VECTOR_SHUFFLE C, D, RMask
24654 SmallVector<int, 16> RMask(NumElts);
24655 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24656 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24657 C = RHS.getOperand(0);
24658 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24659 D = RHS.getOperand(1);
24660 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24661 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24663 if (RHS.getOpcode() != ISD::UNDEF)
24665 for (unsigned i = 0; i != NumElts; ++i)
24669 // Check that the shuffles are both shuffling the same vectors.
24670 if (!(A == C && B == D) && !(A == D && B == C))
24673 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24674 if (!A.getNode() && !B.getNode())
24677 // If A and B occur in reverse order in RHS, then "swap" them (which means
24678 // rewriting the mask).
24680 CommuteVectorShuffleMask(RMask, NumElts);
24682 // At this point LHS and RHS are equivalent to
24683 // LHS = VECTOR_SHUFFLE A, B, LMask
24684 // RHS = VECTOR_SHUFFLE A, B, RMask
24685 // Check that the masks correspond to performing a horizontal operation.
24686 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24687 for (unsigned i = 0; i != NumLaneElts; ++i) {
24688 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24690 // Ignore any UNDEF components.
24691 if (LIdx < 0 || RIdx < 0 ||
24692 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24693 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24696 // Check that successive elements are being operated on. If not, this is
24697 // not a horizontal operation.
24698 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24699 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24700 if (!(LIdx == Index && RIdx == Index + 1) &&
24701 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24706 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24707 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24711 /// Do target-specific dag combines on floating point adds.
24712 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24713 const X86Subtarget *Subtarget) {
24714 EVT VT = N->getValueType(0);
24715 SDValue LHS = N->getOperand(0);
24716 SDValue RHS = N->getOperand(1);
24718 // Try to synthesize horizontal adds from adds of shuffles.
24719 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24720 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24721 isHorizontalBinOp(LHS, RHS, true))
24722 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24726 /// Do target-specific dag combines on floating point subs.
24727 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24728 const X86Subtarget *Subtarget) {
24729 EVT VT = N->getValueType(0);
24730 SDValue LHS = N->getOperand(0);
24731 SDValue RHS = N->getOperand(1);
24733 // Try to synthesize horizontal subs from subs of shuffles.
24734 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24735 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24736 isHorizontalBinOp(LHS, RHS, false))
24737 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24741 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24742 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24743 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24744 // F[X]OR(0.0, x) -> x
24745 // F[X]OR(x, 0.0) -> x
24746 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24747 if (C->getValueAPF().isPosZero())
24748 return N->getOperand(1);
24749 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24750 if (C->getValueAPF().isPosZero())
24751 return N->getOperand(0);
24755 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24756 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24757 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24759 // Only perform optimizations if UnsafeMath is used.
24760 if (!DAG.getTarget().Options.UnsafeFPMath)
24763 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24764 // into FMINC and FMAXC, which are Commutative operations.
24765 unsigned NewOp = 0;
24766 switch (N->getOpcode()) {
24767 default: llvm_unreachable("unknown opcode");
24768 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24769 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24772 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24773 N->getOperand(0), N->getOperand(1));
24776 /// Do target-specific dag combines on X86ISD::FAND nodes.
24777 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24778 // FAND(0.0, x) -> 0.0
24779 // FAND(x, 0.0) -> 0.0
24780 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24781 if (C->getValueAPF().isPosZero())
24782 return N->getOperand(0);
24783 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24784 if (C->getValueAPF().isPosZero())
24785 return N->getOperand(1);
24789 /// Do target-specific dag combines on X86ISD::FANDN nodes
24790 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24791 // FANDN(x, 0.0) -> 0.0
24792 // FANDN(0.0, x) -> x
24793 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24794 if (C->getValueAPF().isPosZero())
24795 return N->getOperand(1);
24796 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24797 if (C->getValueAPF().isPosZero())
24798 return N->getOperand(1);
24802 static SDValue PerformBTCombine(SDNode *N,
24804 TargetLowering::DAGCombinerInfo &DCI) {
24805 // BT ignores high bits in the bit index operand.
24806 SDValue Op1 = N->getOperand(1);
24807 if (Op1.hasOneUse()) {
24808 unsigned BitWidth = Op1.getValueSizeInBits();
24809 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24810 APInt KnownZero, KnownOne;
24811 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24812 !DCI.isBeforeLegalizeOps());
24813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24814 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24815 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24816 DCI.CommitTargetLoweringOpt(TLO);
24821 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24822 SDValue Op = N->getOperand(0);
24823 if (Op.getOpcode() == ISD::BITCAST)
24824 Op = Op.getOperand(0);
24825 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24826 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24827 VT.getVectorElementType().getSizeInBits() ==
24828 OpVT.getVectorElementType().getSizeInBits()) {
24829 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24834 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24835 const X86Subtarget *Subtarget) {
24836 EVT VT = N->getValueType(0);
24837 if (!VT.isVector())
24840 SDValue N0 = N->getOperand(0);
24841 SDValue N1 = N->getOperand(1);
24842 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24845 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24846 // both SSE and AVX2 since there is no sign-extended shift right
24847 // operation on a vector with 64-bit elements.
24848 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24849 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24850 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24851 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24852 SDValue N00 = N0.getOperand(0);
24854 // EXTLOAD has a better solution on AVX2,
24855 // it may be replaced with X86ISD::VSEXT node.
24856 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24857 if (!ISD::isNormalLoad(N00.getNode()))
24860 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24861 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24863 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24869 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24870 TargetLowering::DAGCombinerInfo &DCI,
24871 const X86Subtarget *Subtarget) {
24872 SDValue N0 = N->getOperand(0);
24873 EVT VT = N->getValueType(0);
24875 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24876 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24877 // This exposes the sext to the sdivrem lowering, so that it directly extends
24878 // from AH (which we otherwise need to do contortions to access).
24879 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24880 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24882 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24883 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24884 N0.getOperand(0), N0.getOperand(1));
24885 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24886 return R.getValue(1);
24889 if (!DCI.isBeforeLegalizeOps())
24892 if (!Subtarget->hasFp256())
24895 if (VT.isVector() && VT.getSizeInBits() == 256) {
24896 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24904 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24905 const X86Subtarget* Subtarget) {
24907 EVT VT = N->getValueType(0);
24909 // Let legalize expand this if it isn't a legal type yet.
24910 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24913 EVT ScalarVT = VT.getScalarType();
24914 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24915 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24918 SDValue A = N->getOperand(0);
24919 SDValue B = N->getOperand(1);
24920 SDValue C = N->getOperand(2);
24922 bool NegA = (A.getOpcode() == ISD::FNEG);
24923 bool NegB = (B.getOpcode() == ISD::FNEG);
24924 bool NegC = (C.getOpcode() == ISD::FNEG);
24926 // Negative multiplication when NegA xor NegB
24927 bool NegMul = (NegA != NegB);
24929 A = A.getOperand(0);
24931 B = B.getOperand(0);
24933 C = C.getOperand(0);
24937 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24939 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24941 return DAG.getNode(Opcode, dl, VT, A, B, C);
24944 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24945 TargetLowering::DAGCombinerInfo &DCI,
24946 const X86Subtarget *Subtarget) {
24947 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24948 // (and (i32 x86isd::setcc_carry), 1)
24949 // This eliminates the zext. This transformation is necessary because
24950 // ISD::SETCC is always legalized to i8.
24952 SDValue N0 = N->getOperand(0);
24953 EVT VT = N->getValueType(0);
24955 if (N0.getOpcode() == ISD::AND &&
24957 N0.getOperand(0).hasOneUse()) {
24958 SDValue N00 = N0.getOperand(0);
24959 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24960 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24961 if (!C || C->getZExtValue() != 1)
24963 return DAG.getNode(ISD::AND, dl, VT,
24964 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24965 N00.getOperand(0), N00.getOperand(1)),
24966 DAG.getConstant(1, VT));
24970 if (N0.getOpcode() == ISD::TRUNCATE &&
24972 N0.getOperand(0).hasOneUse()) {
24973 SDValue N00 = N0.getOperand(0);
24974 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24975 return DAG.getNode(ISD::AND, dl, VT,
24976 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24977 N00.getOperand(0), N00.getOperand(1)),
24978 DAG.getConstant(1, VT));
24981 if (VT.is256BitVector()) {
24982 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24987 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24988 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24989 // This exposes the zext to the udivrem lowering, so that it directly extends
24990 // from AH (which we otherwise need to do contortions to access).
24991 if (N0.getOpcode() == ISD::UDIVREM &&
24992 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24993 (VT == MVT::i32 || VT == MVT::i64)) {
24994 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24995 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24996 N0.getOperand(0), N0.getOperand(1));
24997 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24998 return R.getValue(1);
25004 // Optimize x == -y --> x+y == 0
25005 // x != -y --> x+y != 0
25006 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25007 const X86Subtarget* Subtarget) {
25008 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25009 SDValue LHS = N->getOperand(0);
25010 SDValue RHS = N->getOperand(1);
25011 EVT VT = N->getValueType(0);
25014 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25016 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25017 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25018 LHS.getValueType(), RHS, LHS.getOperand(1));
25019 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25020 addV, DAG.getConstant(0, addV.getValueType()), CC);
25022 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25024 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25025 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25026 RHS.getValueType(), LHS, RHS.getOperand(1));
25027 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25028 addV, DAG.getConstant(0, addV.getValueType()), CC);
25031 if (VT.getScalarType() == MVT::i1) {
25032 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25033 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25034 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25035 if (!IsSEXT0 && !IsVZero0)
25037 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25038 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25039 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25041 if (!IsSEXT1 && !IsVZero1)
25044 if (IsSEXT0 && IsVZero1) {
25045 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25046 if (CC == ISD::SETEQ)
25047 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25048 return LHS.getOperand(0);
25050 if (IsSEXT1 && IsVZero0) {
25051 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25052 if (CC == ISD::SETEQ)
25053 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25054 return RHS.getOperand(0);
25061 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25062 const X86Subtarget *Subtarget) {
25064 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25065 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25066 "X86insertps is only defined for v4x32");
25068 SDValue Ld = N->getOperand(1);
25069 if (MayFoldLoad(Ld)) {
25070 // Extract the countS bits from the immediate so we can get the proper
25071 // address when narrowing the vector load to a specific element.
25072 // When the second source op is a memory address, interps doesn't use
25073 // countS and just gets an f32 from that address.
25074 unsigned DestIndex =
25075 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25076 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25080 // Create this as a scalar to vector to match the instruction pattern.
25081 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25082 // countS bits are ignored when loading from memory on insertps, which
25083 // means we don't need to explicitly set them to 0.
25084 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25085 LoadScalarToVector, N->getOperand(2));
25088 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25089 // as "sbb reg,reg", since it can be extended without zext and produces
25090 // an all-ones bit which is more useful than 0/1 in some cases.
25091 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25094 return DAG.getNode(ISD::AND, DL, VT,
25095 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25096 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25097 DAG.getConstant(1, VT));
25098 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25099 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25100 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25101 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25104 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25105 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25106 TargetLowering::DAGCombinerInfo &DCI,
25107 const X86Subtarget *Subtarget) {
25109 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25110 SDValue EFLAGS = N->getOperand(1);
25112 if (CC == X86::COND_A) {
25113 // Try to convert COND_A into COND_B in an attempt to facilitate
25114 // materializing "setb reg".
25116 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25117 // cannot take an immediate as its first operand.
25119 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25120 EFLAGS.getValueType().isInteger() &&
25121 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25122 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25123 EFLAGS.getNode()->getVTList(),
25124 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25125 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25126 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25130 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25131 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25133 if (CC == X86::COND_B)
25134 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25138 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25139 if (Flags.getNode()) {
25140 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25141 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25147 // Optimize branch condition evaluation.
25149 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25150 TargetLowering::DAGCombinerInfo &DCI,
25151 const X86Subtarget *Subtarget) {
25153 SDValue Chain = N->getOperand(0);
25154 SDValue Dest = N->getOperand(1);
25155 SDValue EFLAGS = N->getOperand(3);
25156 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25160 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25161 if (Flags.getNode()) {
25162 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25163 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25170 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25171 SelectionDAG &DAG) {
25172 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25173 // optimize away operation when it's from a constant.
25175 // The general transformation is:
25176 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25177 // AND(VECTOR_CMP(x,y), constant2)
25178 // constant2 = UNARYOP(constant)
25180 // Early exit if this isn't a vector operation, the operand of the
25181 // unary operation isn't a bitwise AND, or if the sizes of the operations
25182 // aren't the same.
25183 EVT VT = N->getValueType(0);
25184 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25185 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25186 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25189 // Now check that the other operand of the AND is a constant. We could
25190 // make the transformation for non-constant splats as well, but it's unclear
25191 // that would be a benefit as it would not eliminate any operations, just
25192 // perform one more step in scalar code before moving to the vector unit.
25193 if (BuildVectorSDNode *BV =
25194 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25195 // Bail out if the vector isn't a constant.
25196 if (!BV->isConstant())
25199 // Everything checks out. Build up the new and improved node.
25201 EVT IntVT = BV->getValueType(0);
25202 // Create a new constant of the appropriate type for the transformed
25204 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25205 // The AND node needs bitcasts to/from an integer vector type around it.
25206 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25207 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25208 N->getOperand(0)->getOperand(0), MaskConst);
25209 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25216 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25217 const X86TargetLowering *XTLI) {
25218 // First try to optimize away the conversion entirely when it's
25219 // conditionally from a constant. Vectors only.
25220 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25221 if (Res != SDValue())
25224 // Now move on to more general possibilities.
25225 SDValue Op0 = N->getOperand(0);
25226 EVT InVT = Op0->getValueType(0);
25228 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25229 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25231 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25232 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25233 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25236 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25237 // a 32-bit target where SSE doesn't support i64->FP operations.
25238 if (Op0.getOpcode() == ISD::LOAD) {
25239 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25240 EVT VT = Ld->getValueType(0);
25241 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25242 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25243 !XTLI->getSubtarget()->is64Bit() &&
25245 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25246 Ld->getChain(), Op0, DAG);
25247 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25254 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25255 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25256 X86TargetLowering::DAGCombinerInfo &DCI) {
25257 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25258 // the result is either zero or one (depending on the input carry bit).
25259 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25260 if (X86::isZeroNode(N->getOperand(0)) &&
25261 X86::isZeroNode(N->getOperand(1)) &&
25262 // We don't have a good way to replace an EFLAGS use, so only do this when
25264 SDValue(N, 1).use_empty()) {
25266 EVT VT = N->getValueType(0);
25267 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25268 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25269 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25270 DAG.getConstant(X86::COND_B,MVT::i8),
25272 DAG.getConstant(1, VT));
25273 return DCI.CombineTo(N, Res1, CarryOut);
25279 // fold (add Y, (sete X, 0)) -> adc 0, Y
25280 // (add Y, (setne X, 0)) -> sbb -1, Y
25281 // (sub (sete X, 0), Y) -> sbb 0, Y
25282 // (sub (setne X, 0), Y) -> adc -1, Y
25283 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25286 // Look through ZExts.
25287 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25288 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25291 SDValue SetCC = Ext.getOperand(0);
25292 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25295 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25296 if (CC != X86::COND_E && CC != X86::COND_NE)
25299 SDValue Cmp = SetCC.getOperand(1);
25300 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25301 !X86::isZeroNode(Cmp.getOperand(1)) ||
25302 !Cmp.getOperand(0).getValueType().isInteger())
25305 SDValue CmpOp0 = Cmp.getOperand(0);
25306 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25307 DAG.getConstant(1, CmpOp0.getValueType()));
25309 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25310 if (CC == X86::COND_NE)
25311 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25312 DL, OtherVal.getValueType(), OtherVal,
25313 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25314 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25315 DL, OtherVal.getValueType(), OtherVal,
25316 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25319 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25320 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25321 const X86Subtarget *Subtarget) {
25322 EVT VT = N->getValueType(0);
25323 SDValue Op0 = N->getOperand(0);
25324 SDValue Op1 = N->getOperand(1);
25326 // Try to synthesize horizontal adds from adds of shuffles.
25327 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25328 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25329 isHorizontalBinOp(Op0, Op1, true))
25330 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25332 return OptimizeConditionalInDecrement(N, DAG);
25335 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25336 const X86Subtarget *Subtarget) {
25337 SDValue Op0 = N->getOperand(0);
25338 SDValue Op1 = N->getOperand(1);
25340 // X86 can't encode an immediate LHS of a sub. See if we can push the
25341 // negation into a preceding instruction.
25342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25343 // If the RHS of the sub is a XOR with one use and a constant, invert the
25344 // immediate. Then add one to the LHS of the sub so we can turn
25345 // X-Y -> X+~Y+1, saving one register.
25346 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25347 isa<ConstantSDNode>(Op1.getOperand(1))) {
25348 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25349 EVT VT = Op0.getValueType();
25350 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25352 DAG.getConstant(~XorC, VT));
25353 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25354 DAG.getConstant(C->getAPIntValue()+1, VT));
25358 // Try to synthesize horizontal adds from adds of shuffles.
25359 EVT VT = N->getValueType(0);
25360 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25361 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25362 isHorizontalBinOp(Op0, Op1, true))
25363 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25365 return OptimizeConditionalInDecrement(N, DAG);
25368 /// performVZEXTCombine - Performs build vector combines
25369 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25370 TargetLowering::DAGCombinerInfo &DCI,
25371 const X86Subtarget *Subtarget) {
25373 MVT VT = N->getSimpleValueType(0);
25374 SDValue Op = N->getOperand(0);
25375 MVT OpVT = Op.getSimpleValueType();
25376 MVT OpEltVT = OpVT.getVectorElementType();
25377 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25379 // (vzext (bitcast (vzext (x)) -> (vzext x)
25381 while (V.getOpcode() == ISD::BITCAST)
25382 V = V.getOperand(0);
25384 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25385 MVT InnerVT = V.getSimpleValueType();
25386 MVT InnerEltVT = InnerVT.getVectorElementType();
25388 // If the element sizes match exactly, we can just do one larger vzext. This
25389 // is always an exact type match as vzext operates on integer types.
25390 if (OpEltVT == InnerEltVT) {
25391 assert(OpVT == InnerVT && "Types must match for vzext!");
25392 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25395 // The only other way we can combine them is if only a single element of the
25396 // inner vzext is used in the input to the outer vzext.
25397 if (InnerEltVT.getSizeInBits() < InputBits)
25400 // In this case, the inner vzext is completely dead because we're going to
25401 // only look at bits inside of the low element. Just do the outer vzext on
25402 // a bitcast of the input to the inner.
25403 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25404 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25407 // Check if we can bypass extracting and re-inserting an element of an input
25408 // vector. Essentialy:
25409 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25410 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25411 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25412 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25413 SDValue ExtractedV = V.getOperand(0);
25414 SDValue OrigV = ExtractedV.getOperand(0);
25415 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25416 if (ExtractIdx->getZExtValue() == 0) {
25417 MVT OrigVT = OrigV.getSimpleValueType();
25418 // Extract a subvector if necessary...
25419 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25420 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25421 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25422 OrigVT.getVectorNumElements() / Ratio);
25423 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25424 DAG.getIntPtrConstant(0));
25426 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25427 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25434 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25435 DAGCombinerInfo &DCI) const {
25436 SelectionDAG &DAG = DCI.DAG;
25437 switch (N->getOpcode()) {
25439 case ISD::EXTRACT_VECTOR_ELT:
25440 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25443 case X86ISD::SHRUNKBLEND:
25444 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25445 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25446 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25447 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25448 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25449 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25452 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25453 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25454 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25455 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25456 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25457 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25458 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25459 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25460 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25462 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25464 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25465 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25466 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25467 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25468 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25469 case ISD::ANY_EXTEND:
25470 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25471 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25472 case ISD::SIGN_EXTEND_INREG:
25473 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25474 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25475 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25476 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25477 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25478 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25479 case X86ISD::SHUFP: // Handle all target specific shuffles
25480 case X86ISD::PALIGNR:
25481 case X86ISD::UNPCKH:
25482 case X86ISD::UNPCKL:
25483 case X86ISD::MOVHLPS:
25484 case X86ISD::MOVLHPS:
25485 case X86ISD::PSHUFB:
25486 case X86ISD::PSHUFD:
25487 case X86ISD::PSHUFHW:
25488 case X86ISD::PSHUFLW:
25489 case X86ISD::MOVSS:
25490 case X86ISD::MOVSD:
25491 case X86ISD::VPERMILPI:
25492 case X86ISD::VPERM2X128:
25493 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25494 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25495 case ISD::INTRINSIC_WO_CHAIN:
25496 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25497 case X86ISD::INSERTPS:
25498 return PerformINSERTPSCombine(N, DAG, Subtarget);
25499 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25505 /// isTypeDesirableForOp - Return true if the target has native support for
25506 /// the specified value type and it is 'desirable' to use the type for the
25507 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25508 /// instruction encodings are longer and some i16 instructions are slow.
25509 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25510 if (!isTypeLegal(VT))
25512 if (VT != MVT::i16)
25519 case ISD::SIGN_EXTEND:
25520 case ISD::ZERO_EXTEND:
25521 case ISD::ANY_EXTEND:
25534 /// IsDesirableToPromoteOp - This method query the target whether it is
25535 /// beneficial for dag combiner to promote the specified node. If true, it
25536 /// should return the desired promotion type by reference.
25537 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25538 EVT VT = Op.getValueType();
25539 if (VT != MVT::i16)
25542 bool Promote = false;
25543 bool Commute = false;
25544 switch (Op.getOpcode()) {
25547 LoadSDNode *LD = cast<LoadSDNode>(Op);
25548 // If the non-extending load has a single use and it's not live out, then it
25549 // might be folded.
25550 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25551 Op.hasOneUse()*/) {
25552 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25553 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25554 // The only case where we'd want to promote LOAD (rather then it being
25555 // promoted as an operand is when it's only use is liveout.
25556 if (UI->getOpcode() != ISD::CopyToReg)
25563 case ISD::SIGN_EXTEND:
25564 case ISD::ZERO_EXTEND:
25565 case ISD::ANY_EXTEND:
25570 SDValue N0 = Op.getOperand(0);
25571 // Look out for (store (shl (load), x)).
25572 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25585 SDValue N0 = Op.getOperand(0);
25586 SDValue N1 = Op.getOperand(1);
25587 if (!Commute && MayFoldLoad(N1))
25589 // Avoid disabling potential load folding opportunities.
25590 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25592 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25602 //===----------------------------------------------------------------------===//
25603 // X86 Inline Assembly Support
25604 //===----------------------------------------------------------------------===//
25607 // Helper to match a string separated by whitespace.
25608 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25609 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25611 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25612 StringRef piece(*args[i]);
25613 if (!s.startswith(piece)) // Check if the piece matches.
25616 s = s.substr(piece.size());
25617 StringRef::size_type pos = s.find_first_not_of(" \t");
25618 if (pos == 0) // We matched a prefix.
25626 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25629 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25631 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25632 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25633 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25634 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25636 if (AsmPieces.size() == 3)
25638 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25645 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25646 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25648 std::string AsmStr = IA->getAsmString();
25650 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25651 if (!Ty || Ty->getBitWidth() % 16 != 0)
25654 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25655 SmallVector<StringRef, 4> AsmPieces;
25656 SplitString(AsmStr, AsmPieces, ";\n");
25658 switch (AsmPieces.size()) {
25659 default: return false;
25661 // FIXME: this should verify that we are targeting a 486 or better. If not,
25662 // we will turn this bswap into something that will be lowered to logical
25663 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25664 // lower so don't worry about this.
25666 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25667 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25668 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25669 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25670 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25671 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25672 // No need to check constraints, nothing other than the equivalent of
25673 // "=r,0" would be valid here.
25674 return IntrinsicLowering::LowerToByteSwap(CI);
25677 // rorw $$8, ${0:w} --> llvm.bswap.i16
25678 if (CI->getType()->isIntegerTy(16) &&
25679 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25680 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25681 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25683 const std::string &ConstraintsStr = IA->getConstraintString();
25684 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25685 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25686 if (clobbersFlagRegisters(AsmPieces))
25687 return IntrinsicLowering::LowerToByteSwap(CI);
25691 if (CI->getType()->isIntegerTy(32) &&
25692 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25693 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25694 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25695 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25697 const std::string &ConstraintsStr = IA->getConstraintString();
25698 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25699 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25700 if (clobbersFlagRegisters(AsmPieces))
25701 return IntrinsicLowering::LowerToByteSwap(CI);
25704 if (CI->getType()->isIntegerTy(64)) {
25705 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25706 if (Constraints.size() >= 2 &&
25707 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25708 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25709 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25710 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25711 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25712 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25713 return IntrinsicLowering::LowerToByteSwap(CI);
25721 /// getConstraintType - Given a constraint letter, return the type of
25722 /// constraint it is for this target.
25723 X86TargetLowering::ConstraintType
25724 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25725 if (Constraint.size() == 1) {
25726 switch (Constraint[0]) {
25737 return C_RegisterClass;
25761 return TargetLowering::getConstraintType(Constraint);
25764 /// Examine constraint type and operand type and determine a weight value.
25765 /// This object must already have been set up with the operand type
25766 /// and the current alternative constraint selected.
25767 TargetLowering::ConstraintWeight
25768 X86TargetLowering::getSingleConstraintMatchWeight(
25769 AsmOperandInfo &info, const char *constraint) const {
25770 ConstraintWeight weight = CW_Invalid;
25771 Value *CallOperandVal = info.CallOperandVal;
25772 // If we don't have a value, we can't do a match,
25773 // but allow it at the lowest weight.
25774 if (!CallOperandVal)
25776 Type *type = CallOperandVal->getType();
25777 // Look at the constraint type.
25778 switch (*constraint) {
25780 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25791 if (CallOperandVal->getType()->isIntegerTy())
25792 weight = CW_SpecificReg;
25797 if (type->isFloatingPointTy())
25798 weight = CW_SpecificReg;
25801 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25802 weight = CW_SpecificReg;
25806 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25807 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25808 weight = CW_Register;
25811 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25812 if (C->getZExtValue() <= 31)
25813 weight = CW_Constant;
25817 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25818 if (C->getZExtValue() <= 63)
25819 weight = CW_Constant;
25823 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25824 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25825 weight = CW_Constant;
25829 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25830 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25831 weight = CW_Constant;
25835 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25836 if (C->getZExtValue() <= 3)
25837 weight = CW_Constant;
25841 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25842 if (C->getZExtValue() <= 0xff)
25843 weight = CW_Constant;
25848 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25849 weight = CW_Constant;
25853 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25854 if ((C->getSExtValue() >= -0x80000000LL) &&
25855 (C->getSExtValue() <= 0x7fffffffLL))
25856 weight = CW_Constant;
25860 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25861 if (C->getZExtValue() <= 0xffffffff)
25862 weight = CW_Constant;
25869 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25870 /// with another that has more specific requirements based on the type of the
25871 /// corresponding operand.
25872 const char *X86TargetLowering::
25873 LowerXConstraint(EVT ConstraintVT) const {
25874 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25875 // 'f' like normal targets.
25876 if (ConstraintVT.isFloatingPoint()) {
25877 if (Subtarget->hasSSE2())
25879 if (Subtarget->hasSSE1())
25883 return TargetLowering::LowerXConstraint(ConstraintVT);
25886 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25887 /// vector. If it is invalid, don't add anything to Ops.
25888 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25889 std::string &Constraint,
25890 std::vector<SDValue>&Ops,
25891 SelectionDAG &DAG) const {
25894 // Only support length 1 constraints for now.
25895 if (Constraint.length() > 1) return;
25897 char ConstraintLetter = Constraint[0];
25898 switch (ConstraintLetter) {
25901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25902 if (C->getZExtValue() <= 31) {
25903 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25909 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25910 if (C->getZExtValue() <= 63) {
25911 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25918 if (isInt<8>(C->getSExtValue())) {
25919 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25926 if (C->getZExtValue() <= 255) {
25927 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25933 // 32-bit signed value
25934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25935 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25936 C->getSExtValue())) {
25937 // Widen to 64 bits here to get it sign extended.
25938 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25941 // FIXME gcc accepts some relocatable values here too, but only in certain
25942 // memory models; it's complicated.
25947 // 32-bit unsigned value
25948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25949 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25950 C->getZExtValue())) {
25951 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25955 // FIXME gcc accepts some relocatable values here too, but only in certain
25956 // memory models; it's complicated.
25960 // Literal immediates are always ok.
25961 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25962 // Widen to 64 bits here to get it sign extended.
25963 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25967 // In any sort of PIC mode addresses need to be computed at runtime by
25968 // adding in a register or some sort of table lookup. These can't
25969 // be used as immediates.
25970 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25973 // If we are in non-pic codegen mode, we allow the address of a global (with
25974 // an optional displacement) to be used with 'i'.
25975 GlobalAddressSDNode *GA = nullptr;
25976 int64_t Offset = 0;
25978 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25980 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25981 Offset += GA->getOffset();
25983 } else if (Op.getOpcode() == ISD::ADD) {
25984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25985 Offset += C->getZExtValue();
25986 Op = Op.getOperand(0);
25989 } else if (Op.getOpcode() == ISD::SUB) {
25990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25991 Offset += -C->getZExtValue();
25992 Op = Op.getOperand(0);
25997 // Otherwise, this isn't something we can handle, reject it.
26001 const GlobalValue *GV = GA->getGlobal();
26002 // If we require an extra load to get this address, as in PIC mode, we
26003 // can't accept it.
26004 if (isGlobalStubReference(
26005 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26008 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26009 GA->getValueType(0), Offset);
26014 if (Result.getNode()) {
26015 Ops.push_back(Result);
26018 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26021 std::pair<unsigned, const TargetRegisterClass*>
26022 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26024 // First, see if this is a constraint that directly corresponds to an LLVM
26026 if (Constraint.size() == 1) {
26027 // GCC Constraint Letters
26028 switch (Constraint[0]) {
26030 // TODO: Slight differences here in allocation order and leaving
26031 // RIP in the class. Do they matter any more here than they do
26032 // in the normal allocation?
26033 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26034 if (Subtarget->is64Bit()) {
26035 if (VT == MVT::i32 || VT == MVT::f32)
26036 return std::make_pair(0U, &X86::GR32RegClass);
26037 if (VT == MVT::i16)
26038 return std::make_pair(0U, &X86::GR16RegClass);
26039 if (VT == MVT::i8 || VT == MVT::i1)
26040 return std::make_pair(0U, &X86::GR8RegClass);
26041 if (VT == MVT::i64 || VT == MVT::f64)
26042 return std::make_pair(0U, &X86::GR64RegClass);
26045 // 32-bit fallthrough
26046 case 'Q': // Q_REGS
26047 if (VT == MVT::i32 || VT == MVT::f32)
26048 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26049 if (VT == MVT::i16)
26050 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26051 if (VT == MVT::i8 || VT == MVT::i1)
26052 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26053 if (VT == MVT::i64)
26054 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26056 case 'r': // GENERAL_REGS
26057 case 'l': // INDEX_REGS
26058 if (VT == MVT::i8 || VT == MVT::i1)
26059 return std::make_pair(0U, &X86::GR8RegClass);
26060 if (VT == MVT::i16)
26061 return std::make_pair(0U, &X86::GR16RegClass);
26062 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26063 return std::make_pair(0U, &X86::GR32RegClass);
26064 return std::make_pair(0U, &X86::GR64RegClass);
26065 case 'R': // LEGACY_REGS
26066 if (VT == MVT::i8 || VT == MVT::i1)
26067 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26068 if (VT == MVT::i16)
26069 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26070 if (VT == MVT::i32 || !Subtarget->is64Bit())
26071 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26072 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26073 case 'f': // FP Stack registers.
26074 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26075 // value to the correct fpstack register class.
26076 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26077 return std::make_pair(0U, &X86::RFP32RegClass);
26078 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26079 return std::make_pair(0U, &X86::RFP64RegClass);
26080 return std::make_pair(0U, &X86::RFP80RegClass);
26081 case 'y': // MMX_REGS if MMX allowed.
26082 if (!Subtarget->hasMMX()) break;
26083 return std::make_pair(0U, &X86::VR64RegClass);
26084 case 'Y': // SSE_REGS if SSE2 allowed
26085 if (!Subtarget->hasSSE2()) break;
26087 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26088 if (!Subtarget->hasSSE1()) break;
26090 switch (VT.SimpleTy) {
26092 // Scalar SSE types.
26095 return std::make_pair(0U, &X86::FR32RegClass);
26098 return std::make_pair(0U, &X86::FR64RegClass);
26106 return std::make_pair(0U, &X86::VR128RegClass);
26114 return std::make_pair(0U, &X86::VR256RegClass);
26119 return std::make_pair(0U, &X86::VR512RegClass);
26125 // Use the default implementation in TargetLowering to convert the register
26126 // constraint into a member of a register class.
26127 std::pair<unsigned, const TargetRegisterClass*> Res;
26128 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26130 // Not found as a standard register?
26132 // Map st(0) -> st(7) -> ST0
26133 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26134 tolower(Constraint[1]) == 's' &&
26135 tolower(Constraint[2]) == 't' &&
26136 Constraint[3] == '(' &&
26137 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26138 Constraint[5] == ')' &&
26139 Constraint[6] == '}') {
26141 Res.first = X86::FP0+Constraint[4]-'0';
26142 Res.second = &X86::RFP80RegClass;
26146 // GCC allows "st(0)" to be called just plain "st".
26147 if (StringRef("{st}").equals_lower(Constraint)) {
26148 Res.first = X86::FP0;
26149 Res.second = &X86::RFP80RegClass;
26154 if (StringRef("{flags}").equals_lower(Constraint)) {
26155 Res.first = X86::EFLAGS;
26156 Res.second = &X86::CCRRegClass;
26160 // 'A' means EAX + EDX.
26161 if (Constraint == "A") {
26162 Res.first = X86::EAX;
26163 Res.second = &X86::GR32_ADRegClass;
26169 // Otherwise, check to see if this is a register class of the wrong value
26170 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26171 // turn into {ax},{dx}.
26172 if (Res.second->hasType(VT))
26173 return Res; // Correct type already, nothing to do.
26175 // All of the single-register GCC register classes map their values onto
26176 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26177 // really want an 8-bit or 32-bit register, map to the appropriate register
26178 // class and return the appropriate register.
26179 if (Res.second == &X86::GR16RegClass) {
26180 if (VT == MVT::i8 || VT == MVT::i1) {
26181 unsigned DestReg = 0;
26182 switch (Res.first) {
26184 case X86::AX: DestReg = X86::AL; break;
26185 case X86::DX: DestReg = X86::DL; break;
26186 case X86::CX: DestReg = X86::CL; break;
26187 case X86::BX: DestReg = X86::BL; break;
26190 Res.first = DestReg;
26191 Res.second = &X86::GR8RegClass;
26193 } else if (VT == MVT::i32 || VT == MVT::f32) {
26194 unsigned DestReg = 0;
26195 switch (Res.first) {
26197 case X86::AX: DestReg = X86::EAX; break;
26198 case X86::DX: DestReg = X86::EDX; break;
26199 case X86::CX: DestReg = X86::ECX; break;
26200 case X86::BX: DestReg = X86::EBX; break;
26201 case X86::SI: DestReg = X86::ESI; break;
26202 case X86::DI: DestReg = X86::EDI; break;
26203 case X86::BP: DestReg = X86::EBP; break;
26204 case X86::SP: DestReg = X86::ESP; break;
26207 Res.first = DestReg;
26208 Res.second = &X86::GR32RegClass;
26210 } else if (VT == MVT::i64 || VT == MVT::f64) {
26211 unsigned DestReg = 0;
26212 switch (Res.first) {
26214 case X86::AX: DestReg = X86::RAX; break;
26215 case X86::DX: DestReg = X86::RDX; break;
26216 case X86::CX: DestReg = X86::RCX; break;
26217 case X86::BX: DestReg = X86::RBX; break;
26218 case X86::SI: DestReg = X86::RSI; break;
26219 case X86::DI: DestReg = X86::RDI; break;
26220 case X86::BP: DestReg = X86::RBP; break;
26221 case X86::SP: DestReg = X86::RSP; break;
26224 Res.first = DestReg;
26225 Res.second = &X86::GR64RegClass;
26228 } else if (Res.second == &X86::FR32RegClass ||
26229 Res.second == &X86::FR64RegClass ||
26230 Res.second == &X86::VR128RegClass ||
26231 Res.second == &X86::VR256RegClass ||
26232 Res.second == &X86::FR32XRegClass ||
26233 Res.second == &X86::FR64XRegClass ||
26234 Res.second == &X86::VR128XRegClass ||
26235 Res.second == &X86::VR256XRegClass ||
26236 Res.second == &X86::VR512RegClass) {
26237 // Handle references to XMM physical registers that got mapped into the
26238 // wrong class. This can happen with constraints like {xmm0} where the
26239 // target independent register mapper will just pick the first match it can
26240 // find, ignoring the required type.
26242 if (VT == MVT::f32 || VT == MVT::i32)
26243 Res.second = &X86::FR32RegClass;
26244 else if (VT == MVT::f64 || VT == MVT::i64)
26245 Res.second = &X86::FR64RegClass;
26246 else if (X86::VR128RegClass.hasType(VT))
26247 Res.second = &X86::VR128RegClass;
26248 else if (X86::VR256RegClass.hasType(VT))
26249 Res.second = &X86::VR256RegClass;
26250 else if (X86::VR512RegClass.hasType(VT))
26251 Res.second = &X86::VR512RegClass;
26257 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26259 // Scaling factors are not free at all.
26260 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26261 // will take 2 allocations in the out of order engine instead of 1
26262 // for plain addressing mode, i.e. inst (reg1).
26264 // vaddps (%rsi,%drx), %ymm0, %ymm1
26265 // Requires two allocations (one for the load, one for the computation)
26267 // vaddps (%rsi), %ymm0, %ymm1
26268 // Requires just 1 allocation, i.e., freeing allocations for other operations
26269 // and having less micro operations to execute.
26271 // For some X86 architectures, this is even worse because for instance for
26272 // stores, the complex addressing mode forces the instruction to use the
26273 // "load" ports instead of the dedicated "store" port.
26274 // E.g., on Haswell:
26275 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26276 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26277 if (isLegalAddressingMode(AM, Ty))
26278 // Scale represents reg2 * scale, thus account for 1
26279 // as soon as we use a second register.
26280 return AM.Scale != 0;
26284 bool X86TargetLowering::isTargetFTOL() const {
26285 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();