1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
122 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
123 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
125 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
128 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
130 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
132 // SSE has no i16 to fp conversion, only i32
133 if (X86ScalarSSEf32) {
134 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
135 // f32 and f64 cases are Legal, f80 case is not
136 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
138 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
142 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
143 // are Legal, f80 is custom lowered.
144 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
145 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
147 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
149 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
152 if (X86ScalarSSEf32) {
153 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
154 // f32 and f64 cases are Legal, f80 case is not
155 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
157 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
161 // Handle FP_TO_UINT by promoting the destination to a larger signed
163 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
164 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
167 if (Subtarget->is64Bit()) {
168 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
169 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
171 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
172 // Expand FP_TO_UINT into a select.
173 // FIXME: We would like to use a Custom expander here eventually to do
174 // the optimal thing for SSE vs. the default expansion in the legalizer.
175 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
177 // With SSE3 we can use fisttpll to convert to a signed i64.
178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
181 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
182 if (!X86ScalarSSEf64) {
183 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
184 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
187 // Scalar integer divide and remainder are lowered to use operations that
188 // produce two results, to match the available instructions. This exposes
189 // the two-result form to trivial CSE, which is able to combine x/y and x%y
190 // into a single instruction.
192 // Scalar integer multiply-high is also lowered to use two-result
193 // operations, to match the available instructions. However, plain multiply
194 // (low) operations are left as Legal, as there are single-result
195 // instructions for this in x86. Using the two-result multiply instructions
196 // when both high and low results are needed must be arranged by dagcombine.
197 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
198 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
199 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
200 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::SREM , MVT::i8 , Expand);
202 setOperationAction(ISD::UREM , MVT::i8 , Expand);
203 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
204 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
205 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
206 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::SREM , MVT::i16 , Expand);
208 setOperationAction(ISD::UREM , MVT::i16 , Expand);
209 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
210 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
211 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
212 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::SREM , MVT::i32 , Expand);
214 setOperationAction(ISD::UREM , MVT::i32 , Expand);
215 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
216 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
217 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
218 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::SREM , MVT::i64 , Expand);
220 setOperationAction(ISD::UREM , MVT::i64 , Expand);
222 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
223 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
224 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
225 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
226 if (Subtarget->is64Bit())
227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
231 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
232 setOperationAction(ISD::FREM , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f64 , Expand);
234 setOperationAction(ISD::FREM , MVT::f80 , Expand);
235 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
237 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
238 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
239 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
241 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
242 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
244 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
245 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
246 if (Subtarget->is64Bit()) {
247 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
248 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
249 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
252 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
253 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
255 // These should be promoted to a larger select which is supported.
256 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
257 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
258 // X86 wants to expand cmov itself.
259 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
260 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
261 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
264 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
267 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
270 if (Subtarget->is64Bit()) {
271 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
274 // X86 ret instruction may pop stack.
275 setOperationAction(ISD::RET , MVT::Other, Custom);
276 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
279 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
280 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
281 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
283 if (Subtarget->is64Bit())
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
286 if (Subtarget->is64Bit()) {
287 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
288 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
289 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
290 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
292 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
293 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
294 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
298 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
302 if (Subtarget->hasSSE1())
303 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
305 if (!Subtarget->hasSSE2())
306 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
308 // Expand certain atomics
309 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
310 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
314 setOperationAction(ISD::ATOMIC_LOAD_SUB_8 , MVT::i8, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
319 if (!Subtarget->is64Bit()) {
320 setOperationAction(ISD::ATOMIC_LOAD_ADD_64, MVT::i64, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_AND_64, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_OR_64, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_XOR_64, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_NAND_64, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_SWAP_64, MVT::i64, Custom);
329 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
330 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
331 // FIXME - use subtarget debug flags
332 if (!Subtarget->isTargetDarwin() &&
333 !Subtarget->isTargetELF() &&
334 !Subtarget->isTargetCygMing()) {
335 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
336 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
339 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
340 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
341 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
342 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
343 if (Subtarget->is64Bit()) {
344 setExceptionPointerRegister(X86::RAX);
345 setExceptionSelectorRegister(X86::RDX);
347 setExceptionPointerRegister(X86::EAX);
348 setExceptionSelectorRegister(X86::EDX);
350 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
353 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
355 setOperationAction(ISD::TRAP, MVT::Other, Legal);
357 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
358 setOperationAction(ISD::VASTART , MVT::Other, Custom);
359 setOperationAction(ISD::VAEND , MVT::Other, Expand);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::VAARG , MVT::Other, Custom);
362 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
364 setOperationAction(ISD::VAARG , MVT::Other, Expand);
365 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
368 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
369 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
372 if (Subtarget->isTargetCygMing())
373 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
375 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
377 if (X86ScalarSSEf64) {
378 // f32 and f64 use SSE.
379 // Set up the FP register classes.
380 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
381 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
383 // Use ANDPD to simulate FABS.
384 setOperationAction(ISD::FABS , MVT::f64, Custom);
385 setOperationAction(ISD::FABS , MVT::f32, Custom);
387 // Use XORP to simulate FNEG.
388 setOperationAction(ISD::FNEG , MVT::f64, Custom);
389 setOperationAction(ISD::FNEG , MVT::f32, Custom);
391 // Use ANDPD and ORPD to simulate FCOPYSIGN.
392 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
393 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
395 // We don't support sin/cos/fmod
396 setOperationAction(ISD::FSIN , MVT::f64, Expand);
397 setOperationAction(ISD::FCOS , MVT::f64, Expand);
398 setOperationAction(ISD::FSIN , MVT::f32, Expand);
399 setOperationAction(ISD::FCOS , MVT::f32, Expand);
401 // Expand FP immediates into loads from the stack, except for the special
403 addLegalFPImmediate(APFloat(+0.0)); // xorpd
404 addLegalFPImmediate(APFloat(+0.0f)); // xorps
406 // Floating truncations from f80 and extensions to f80 go through memory.
407 // If optimizing, we lie about this though and handle it in
408 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
410 setConvertAction(MVT::f32, MVT::f80, Expand);
411 setConvertAction(MVT::f64, MVT::f80, Expand);
412 setConvertAction(MVT::f80, MVT::f32, Expand);
413 setConvertAction(MVT::f80, MVT::f64, Expand);
415 } else if (X86ScalarSSEf32) {
416 // Use SSE for f32, x87 for f64.
417 // Set up the FP register classes.
418 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
419 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
421 // Use ANDPS to simulate FABS.
422 setOperationAction(ISD::FABS , MVT::f32, Custom);
424 // Use XORP to simulate FNEG.
425 setOperationAction(ISD::FNEG , MVT::f32, Custom);
427 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
429 // Use ANDPS and ORPS to simulate FCOPYSIGN.
430 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
431 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
433 // We don't support sin/cos/fmod
434 setOperationAction(ISD::FSIN , MVT::f32, Expand);
435 setOperationAction(ISD::FCOS , MVT::f32, Expand);
437 // Special cases we handle for FP constants.
438 addLegalFPImmediate(APFloat(+0.0f)); // xorps
439 addLegalFPImmediate(APFloat(+0.0)); // FLD0
440 addLegalFPImmediate(APFloat(+1.0)); // FLD1
441 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
442 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
444 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
445 // this though and handle it in InstructionSelectPreprocess so that
446 // dagcombine2 can hack on these.
448 setConvertAction(MVT::f32, MVT::f64, Expand);
449 setConvertAction(MVT::f32, MVT::f80, Expand);
450 setConvertAction(MVT::f80, MVT::f32, Expand);
451 setConvertAction(MVT::f64, MVT::f32, Expand);
452 // And x87->x87 truncations also.
453 setConvertAction(MVT::f80, MVT::f64, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 // f32 and f64 in x87.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
466 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
467 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
471 // Floating truncations go through memory. If optimizing, we lie about
472 // this though and handle it in InstructionSelectPreprocess so that
473 // dagcombine2 can hack on these.
475 setConvertAction(MVT::f80, MVT::f32, Expand);
476 setConvertAction(MVT::f64, MVT::f32, Expand);
477 setConvertAction(MVT::f80, MVT::f64, Expand);
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
489 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
490 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
491 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
494 // Long double always uses X87.
495 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
496 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
500 APFloat TmpFlt(+0.0);
501 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
503 addLegalFPImmediate(TmpFlt); // FLD0
505 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
506 APFloat TmpFlt2(+1.0);
507 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
509 addLegalFPImmediate(TmpFlt2); // FLD1
510 TmpFlt2.changeSign();
511 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
515 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
516 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
519 // Always use a library call for pow.
520 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
521 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
524 setOperationAction(ISD::FLOG, MVT::f80, Expand);
525 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
527 setOperationAction(ISD::FEXP, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
530 // First set operation action for all vector types to either promote
531 // (for widening) or expand (for scalarization). Then we will selectively
532 // turn on ones that can be effectively codegen'd.
533 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
534 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
535 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
550 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
580 if (!DisableMMX && Subtarget->hasMMX()) {
581 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
582 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
587 // FIXME: add MMX packed arithmetics
589 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
590 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
591 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
592 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
594 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
595 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
596 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
597 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
599 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
600 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
602 setOperationAction(ISD::AND, MVT::v8i8, Promote);
603 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
604 setOperationAction(ISD::AND, MVT::v4i16, Promote);
605 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
606 setOperationAction(ISD::AND, MVT::v2i32, Promote);
607 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
608 setOperationAction(ISD::AND, MVT::v1i64, Legal);
610 setOperationAction(ISD::OR, MVT::v8i8, Promote);
611 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
612 setOperationAction(ISD::OR, MVT::v4i16, Promote);
613 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
614 setOperationAction(ISD::OR, MVT::v2i32, Promote);
615 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
616 setOperationAction(ISD::OR, MVT::v1i64, Legal);
618 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
619 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
620 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
621 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
622 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
623 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
624 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
626 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
627 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
628 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
629 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
630 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
631 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
632 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
633 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
634 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
655 if (Subtarget->hasSSE1()) {
656 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
658 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
659 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
660 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
661 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
662 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
663 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
664 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
665 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
667 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
668 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
669 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
672 if (Subtarget->hasSSE2()) {
673 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
674 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
675 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
676 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
677 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
679 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
680 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
681 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
682 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
683 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
684 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
685 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
686 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
687 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
688 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
689 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
690 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
691 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
692 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
693 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
695 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
696 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
697 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
698 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
700 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
701 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
702 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
703 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
704 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
706 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
707 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
708 MVT VT = (MVT::SimpleValueType)i;
709 // Do not attempt to custom lower non-power-of-2 vectors
710 if (!isPowerOf2_32(VT.getVectorNumElements()))
712 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
713 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
716 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
717 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
718 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
719 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
720 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
721 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
722 if (Subtarget->is64Bit()) {
723 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
727 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
728 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
729 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
730 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
731 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
732 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
733 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
734 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
735 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
736 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
737 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
738 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
741 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
743 // Custom lower v2i64 and v2f64 selects.
744 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
745 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
746 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
747 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
751 if (Subtarget->hasSSE41()) {
752 // FIXME: Do we need to handle scalar-to-vector here?
753 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
754 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
756 // i8 and i16 vectors are custom , because the source register and source
757 // source memory operand types are not the same width. f32 vectors are
758 // custom since the immediate controlling the insert encodes additional
760 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
761 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
762 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
763 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
766 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
767 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
768 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
770 if (Subtarget->is64Bit()) {
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
776 if (Subtarget->hasSSE42()) {
777 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
780 // We want to custom lower some of our intrinsics.
781 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
783 // Add/Sub/Mul with overflow operations are custom lowered.
784 setOperationAction(ISD::SADDO, MVT::i32, Custom);
785 setOperationAction(ISD::SADDO, MVT::i64, Custom);
786 setOperationAction(ISD::UADDO, MVT::i32, Custom);
787 setOperationAction(ISD::UADDO, MVT::i64, Custom);
788 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
789 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
790 setOperationAction(ISD::USUBO, MVT::i32, Custom);
791 setOperationAction(ISD::USUBO, MVT::i64, Custom);
792 setOperationAction(ISD::SMULO, MVT::i32, Custom);
793 setOperationAction(ISD::SMULO, MVT::i64, Custom);
794 setOperationAction(ISD::UMULO, MVT::i32, Custom);
795 setOperationAction(ISD::UMULO, MVT::i64, Custom);
797 // We have target-specific dag combine patterns for the following nodes:
798 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
799 setTargetDAGCombine(ISD::BUILD_VECTOR);
800 setTargetDAGCombine(ISD::SELECT);
801 setTargetDAGCombine(ISD::STORE);
803 computeRegisterProperties();
805 // FIXME: These should be based on subtarget info. Plus, the values should
806 // be smaller when we are in optimizing for size mode.
807 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
808 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
809 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
810 allowUnalignedMemoryAccesses = true; // x86 supports it!
811 setPrefLoopAlignment(16);
815 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
820 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
821 /// the desired ByVal argument alignment.
822 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
825 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
826 if (VTy->getBitWidth() == 128)
828 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
829 unsigned EltAlign = 0;
830 getMaxByValAlign(ATy->getElementType(), EltAlign);
831 if (EltAlign > MaxAlign)
833 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
834 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
835 unsigned EltAlign = 0;
836 getMaxByValAlign(STy->getElementType(i), EltAlign);
837 if (EltAlign > MaxAlign)
846 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
847 /// function arguments in the caller parameter area. For X86, aggregates
848 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
849 /// are at 4-byte boundaries.
850 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
851 if (Subtarget->is64Bit()) {
852 // Max of 8 and alignment of type.
853 unsigned TyAlign = TD->getABITypeAlignment(Ty);
860 if (Subtarget->hasSSE1())
861 getMaxByValAlign(Ty, Align);
865 /// getOptimalMemOpType - Returns the target specific optimal type for load
866 /// and store operations as a result of memset, memcpy, and memmove
867 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
870 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
871 bool isSrcConst, bool isSrcStr) const {
872 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
873 // linux. This is because the stack realignment code can't handle certain
874 // cases like PR2962. This should be removed when PR2962 is fixed.
875 if (Subtarget->getStackAlignment() >= 16) {
876 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
878 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
881 if (Subtarget->is64Bit() && Size >= 8)
887 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
889 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
890 SelectionDAG &DAG) const {
891 if (usesGlobalOffsetTable())
892 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
893 if (!Subtarget->isPICStyleRIPRel())
894 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
898 //===----------------------------------------------------------------------===//
899 // Return Value Calling Convention Implementation
900 //===----------------------------------------------------------------------===//
902 #include "X86GenCallingConv.inc"
904 /// LowerRET - Lower an ISD::RET node.
905 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
906 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
908 SmallVector<CCValAssign, 16> RVLocs;
909 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
910 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
911 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
912 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
914 // If this is the first return lowered for this function, add the regs to the
915 // liveout set for the function.
916 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
917 for (unsigned i = 0; i != RVLocs.size(); ++i)
918 if (RVLocs[i].isRegLoc())
919 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
921 SDValue Chain = Op.getOperand(0);
923 // Handle tail call return.
924 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
925 if (Chain.getOpcode() == X86ISD::TAILCALL) {
926 SDValue TailCall = Chain;
927 SDValue TargetAddress = TailCall.getOperand(1);
928 SDValue StackAdjustment = TailCall.getOperand(2);
929 assert(((TargetAddress.getOpcode() == ISD::Register &&
930 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
931 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
932 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
933 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
934 "Expecting an global address, external symbol, or register");
935 assert(StackAdjustment.getOpcode() == ISD::Constant &&
936 "Expecting a const value");
938 SmallVector<SDValue,8> Operands;
939 Operands.push_back(Chain.getOperand(0));
940 Operands.push_back(TargetAddress);
941 Operands.push_back(StackAdjustment);
942 // Copy registers used by the call. Last operand is a flag so it is not
944 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
945 Operands.push_back(Chain.getOperand(i));
947 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
954 SmallVector<SDValue, 6> RetOps;
955 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
956 // Operand #1 = Bytes To Pop
957 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
959 // Copy the result values into the output registers.
960 for (unsigned i = 0; i != RVLocs.size(); ++i) {
961 CCValAssign &VA = RVLocs[i];
962 assert(VA.isRegLoc() && "Can only return in registers!");
963 SDValue ValToCopy = Op.getOperand(i*2+1);
965 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
966 // the RET instruction and handled by the FP Stackifier.
967 if (RVLocs[i].getLocReg() == X86::ST0 ||
968 RVLocs[i].getLocReg() == X86::ST1) {
969 // If this is a copy from an xmm register to ST(0), use an FPExtend to
970 // change the value to the FP stack register class.
971 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
972 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
973 RetOps.push_back(ValToCopy);
974 // Don't emit a copytoreg.
978 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
979 Flag = Chain.getValue(1);
982 // The x86-64 ABI for returning structs by value requires that we copy
983 // the sret argument into %rax for the return. We saved the argument into
984 // a virtual register in the entry block, so now we copy the value out
986 if (Subtarget->is64Bit() &&
987 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
988 MachineFunction &MF = DAG.getMachineFunction();
989 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
990 unsigned Reg = FuncInfo->getSRetReturnReg();
992 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
993 FuncInfo->setSRetReturnReg(Reg);
995 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
997 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
998 Flag = Chain.getValue(1);
1001 RetOps[0] = Chain; // Update chain.
1003 // Add the flag if we have it.
1005 RetOps.push_back(Flag);
1007 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
1011 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1012 /// appropriate copies out of appropriate physical registers. This assumes that
1013 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1014 /// being lowered. The returns a SDNode with the same number of values as the
1016 SDNode *X86TargetLowering::
1017 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1018 unsigned CallingConv, SelectionDAG &DAG) {
1020 // Assign locations to each value returned by this call.
1021 SmallVector<CCValAssign, 16> RVLocs;
1022 bool isVarArg = TheCall->isVarArg();
1023 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1024 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1026 SmallVector<SDValue, 8> ResultVals;
1028 // Copy all of the result registers out of their specified physreg.
1029 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1030 MVT CopyVT = RVLocs[i].getValVT();
1032 // If this is a call to a function that returns an fp value on the floating
1033 // point stack, but where we prefer to use the value in xmm registers, copy
1034 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1035 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1036 RVLocs[i].getLocReg() == X86::ST1) &&
1037 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1041 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1042 CopyVT, InFlag).getValue(1);
1043 SDValue Val = Chain.getValue(0);
1044 InFlag = Chain.getValue(2);
1046 if (CopyVT != RVLocs[i].getValVT()) {
1047 // Round the F80 the right size, which also moves to the appropriate xmm
1049 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1050 // This truncation won't change the value.
1051 DAG.getIntPtrConstant(1));
1054 ResultVals.push_back(Val);
1057 // Merge everything together with a MERGE_VALUES node.
1058 ResultVals.push_back(Chain);
1059 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
1060 ResultVals.size()).getNode();
1064 //===----------------------------------------------------------------------===//
1065 // C & StdCall & Fast Calling Convention implementation
1066 //===----------------------------------------------------------------------===//
1067 // StdCall calling convention seems to be standard for many Windows' API
1068 // routines and around. It differs from C calling convention just a little:
1069 // callee should clean up the stack, not caller. Symbols should be also
1070 // decorated in some fancy way :) It doesn't support any vector arguments.
1071 // For info on fast calling convention see Fast Calling Convention (tail call)
1072 // implementation LowerX86_32FastCCCallTo.
1074 /// AddLiveIn - This helper function adds the specified physical register to the
1075 /// MachineFunction as a live in value. It also creates a corresponding virtual
1076 /// register for it.
1077 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1078 const TargetRegisterClass *RC) {
1079 assert(RC->contains(PReg) && "Not the correct regclass!");
1080 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1081 MF.getRegInfo().addLiveIn(PReg, VReg);
1085 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1087 static bool CallIsStructReturn(CallSDNode *TheCall) {
1088 unsigned NumOps = TheCall->getNumArgs();
1092 return TheCall->getArgFlags(0).isSRet();
1095 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1096 /// return semantics.
1097 static bool ArgsAreStructReturn(SDValue Op) {
1098 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1102 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1105 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1106 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1108 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1112 switch (CallingConv) {
1115 case CallingConv::X86_StdCall:
1116 return !Subtarget->is64Bit();
1117 case CallingConv::X86_FastCall:
1118 return !Subtarget->is64Bit();
1119 case CallingConv::Fast:
1120 return PerformTailCallOpt;
1124 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1125 /// given CallingConvention value.
1126 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1127 if (Subtarget->is64Bit()) {
1128 if (Subtarget->isTargetWin64())
1129 return CC_X86_Win64_C;
1130 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1131 return CC_X86_64_TailCall;
1136 if (CC == CallingConv::X86_FastCall)
1137 return CC_X86_32_FastCall;
1138 else if (CC == CallingConv::Fast)
1139 return CC_X86_32_FastCC;
1144 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1145 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1147 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1148 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1149 if (CC == CallingConv::X86_FastCall)
1151 else if (CC == CallingConv::X86_StdCall)
1157 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1158 /// in a register before calling.
1159 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1160 return !IsTailCall && !Is64Bit &&
1161 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1162 Subtarget->isPICStyleGOT();
1165 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1166 /// address to be loaded in a register.
1168 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1169 return !Is64Bit && IsTailCall &&
1170 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1171 Subtarget->isPICStyleGOT();
1174 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1175 /// by "Src" to address "Dst" with size and alignment information specified by
1176 /// the specific parameter attribute. The copy will be passed as a byval
1177 /// function parameter.
1179 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1180 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1181 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1182 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1183 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1186 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1187 const CCValAssign &VA,
1188 MachineFrameInfo *MFI,
1190 SDValue Root, unsigned i) {
1191 // Create the nodes corresponding to a load from this parameter slot.
1192 ISD::ArgFlagsTy Flags =
1193 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1194 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1195 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1197 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1198 // changed with more analysis.
1199 // In case of tail call optimization mark all arguments mutable. Since they
1200 // could be overwritten by lowering of arguments in case of a tail call.
1201 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1202 VA.getLocMemOffset(), isImmutable);
1203 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1204 if (Flags.isByVal())
1206 return DAG.getLoad(VA.getValVT(), Root, FIN,
1207 PseudoSourceValue::getFixedStack(FI), 0);
1211 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1212 MachineFunction &MF = DAG.getMachineFunction();
1213 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1215 const Function* Fn = MF.getFunction();
1216 if (Fn->hasExternalLinkage() &&
1217 Subtarget->isTargetCygMing() &&
1218 Fn->getName() == "main")
1219 FuncInfo->setForceFramePointer(true);
1221 // Decorate the function name.
1222 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1224 MachineFrameInfo *MFI = MF.getFrameInfo();
1225 SDValue Root = Op.getOperand(0);
1226 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1227 unsigned CC = MF.getFunction()->getCallingConv();
1228 bool Is64Bit = Subtarget->is64Bit();
1229 bool IsWin64 = Subtarget->isTargetWin64();
1231 assert(!(isVarArg && CC == CallingConv::Fast) &&
1232 "Var args not supported with calling convention fastcc");
1234 // Assign locations to all of the incoming arguments.
1235 SmallVector<CCValAssign, 16> ArgLocs;
1236 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1237 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1239 SmallVector<SDValue, 8> ArgValues;
1240 unsigned LastVal = ~0U;
1241 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1242 CCValAssign &VA = ArgLocs[i];
1243 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1245 assert(VA.getValNo() != LastVal &&
1246 "Don't support value assigned to multiple locs yet");
1247 LastVal = VA.getValNo();
1249 if (VA.isRegLoc()) {
1250 MVT RegVT = VA.getLocVT();
1251 TargetRegisterClass *RC;
1252 if (RegVT == MVT::i32)
1253 RC = X86::GR32RegisterClass;
1254 else if (Is64Bit && RegVT == MVT::i64)
1255 RC = X86::GR64RegisterClass;
1256 else if (RegVT == MVT::f32)
1257 RC = X86::FR32RegisterClass;
1258 else if (RegVT == MVT::f64)
1259 RC = X86::FR64RegisterClass;
1260 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1261 RC = X86::VR128RegisterClass;
1262 else if (RegVT.isVector()) {
1263 assert(RegVT.getSizeInBits() == 64);
1265 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1267 // Darwin calling convention passes MMX values in either GPRs or
1268 // XMMs in x86-64. Other targets pass them in memory.
1269 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1270 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1273 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1278 assert(0 && "Unknown argument type!");
1281 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1282 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1284 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1285 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1287 if (VA.getLocInfo() == CCValAssign::SExt)
1288 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1289 DAG.getValueType(VA.getValVT()));
1290 else if (VA.getLocInfo() == CCValAssign::ZExt)
1291 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1292 DAG.getValueType(VA.getValVT()));
1294 if (VA.getLocInfo() != CCValAssign::Full)
1295 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1297 // Handle MMX values passed in GPRs.
1298 if (Is64Bit && RegVT != VA.getLocVT()) {
1299 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1300 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1301 else if (RC == X86::VR128RegisterClass) {
1302 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1303 DAG.getConstant(0, MVT::i64));
1304 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1308 ArgValues.push_back(ArgValue);
1310 assert(VA.isMemLoc());
1311 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1315 // The x86-64 ABI for returning structs by value requires that we copy
1316 // the sret argument into %rax for the return. Save the argument into
1317 // a virtual register so that we can access it from the return points.
1318 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1319 MachineFunction &MF = DAG.getMachineFunction();
1320 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1321 unsigned Reg = FuncInfo->getSRetReturnReg();
1323 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1324 FuncInfo->setSRetReturnReg(Reg);
1326 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1327 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1330 unsigned StackSize = CCInfo.getNextStackOffset();
1331 // align stack specially for tail calls
1332 if (PerformTailCallOpt && CC == CallingConv::Fast)
1333 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1335 // If the function takes variable number of arguments, make a frame index for
1336 // the start of the first vararg value... for expansion of llvm.va_start.
1338 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1339 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1342 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1344 // FIXME: We should really autogenerate these arrays
1345 static const unsigned GPR64ArgRegsWin64[] = {
1346 X86::RCX, X86::RDX, X86::R8, X86::R9
1348 static const unsigned XMMArgRegsWin64[] = {
1349 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1351 static const unsigned GPR64ArgRegs64Bit[] = {
1352 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1354 static const unsigned XMMArgRegs64Bit[] = {
1355 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1356 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1358 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1361 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1362 GPR64ArgRegs = GPR64ArgRegsWin64;
1363 XMMArgRegs = XMMArgRegsWin64;
1365 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1366 GPR64ArgRegs = GPR64ArgRegs64Bit;
1367 XMMArgRegs = XMMArgRegs64Bit;
1369 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1371 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1374 // For X86-64, if there are vararg parameters that are passed via
1375 // registers, then we must store them to their spots on the stack so they
1376 // may be loaded by deferencing the result of va_next.
1377 VarArgsGPOffset = NumIntRegs * 8;
1378 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1379 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1380 TotalNumXMMRegs * 16, 16);
1382 // Store the integer parameter registers.
1383 SmallVector<SDValue, 8> MemOps;
1384 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1385 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1386 DAG.getIntPtrConstant(VarArgsGPOffset));
1387 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1388 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1389 X86::GR64RegisterClass);
1390 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1392 DAG.getStore(Val.getValue(1), Val, FIN,
1393 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1394 MemOps.push_back(Store);
1395 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1396 DAG.getIntPtrConstant(8));
1399 // Now store the XMM (fp + vector) parameter registers.
1400 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1401 DAG.getIntPtrConstant(VarArgsFPOffset));
1402 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1403 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1404 X86::VR128RegisterClass);
1405 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1407 DAG.getStore(Val.getValue(1), Val, FIN,
1408 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1409 MemOps.push_back(Store);
1410 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1411 DAG.getIntPtrConstant(16));
1413 if (!MemOps.empty())
1414 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1415 &MemOps[0], MemOps.size());
1419 ArgValues.push_back(Root);
1421 // Some CCs need callee pop.
1422 if (IsCalleePop(isVarArg, CC)) {
1423 BytesToPopOnReturn = StackSize; // Callee pops everything.
1424 BytesCallerReserves = 0;
1426 BytesToPopOnReturn = 0; // Callee pops nothing.
1427 // If this is an sret function, the return should pop the hidden pointer.
1428 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1429 BytesToPopOnReturn = 4;
1430 BytesCallerReserves = StackSize;
1434 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1435 if (CC == CallingConv::X86_FastCall)
1436 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1439 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1441 // Return the new list of results.
1442 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
1443 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1447 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1448 const SDValue &StackPtr,
1449 const CCValAssign &VA,
1451 SDValue Arg, ISD::ArgFlagsTy Flags) {
1452 unsigned LocMemOffset = VA.getLocMemOffset();
1453 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1454 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1455 if (Flags.isByVal()) {
1456 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1458 return DAG.getStore(Chain, Arg, PtrOff,
1459 PseudoSourceValue::getStack(), LocMemOffset);
1462 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1463 /// optimization is performed and it is required.
1465 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1466 SDValue &OutRetAddr,
1471 if (!IsTailCall || FPDiff==0) return Chain;
1473 // Adjust the Return address stack slot.
1474 MVT VT = getPointerTy();
1475 OutRetAddr = getReturnAddressFrameIndex(DAG);
1476 // Load the "old" Return address.
1477 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1478 return SDValue(OutRetAddr.getNode(), 1);
1481 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1482 /// optimization is performed and it is required (FPDiff!=0).
1484 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1485 SDValue Chain, SDValue RetAddrFrIdx,
1486 bool Is64Bit, int FPDiff) {
1487 // Store the return address to the appropriate stack slot.
1488 if (!FPDiff) return Chain;
1489 // Calculate the new stack slot for the return address.
1490 int SlotSize = Is64Bit ? 8 : 4;
1491 int NewReturnAddrFI =
1492 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1493 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1494 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1495 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1496 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1500 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1501 MachineFunction &MF = DAG.getMachineFunction();
1502 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1503 SDValue Chain = TheCall->getChain();
1504 unsigned CC = TheCall->getCallingConv();
1505 bool isVarArg = TheCall->isVarArg();
1506 bool IsTailCall = TheCall->isTailCall() &&
1507 CC == CallingConv::Fast && PerformTailCallOpt;
1508 SDValue Callee = TheCall->getCallee();
1509 bool Is64Bit = Subtarget->is64Bit();
1510 bool IsStructRet = CallIsStructReturn(TheCall);
1512 assert(!(isVarArg && CC == CallingConv::Fast) &&
1513 "Var args not supported with calling convention fastcc");
1515 // Analyze operands of the call, assigning locations to each operand.
1516 SmallVector<CCValAssign, 16> ArgLocs;
1517 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1518 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1520 // Get a count of how many bytes are to be pushed on the stack.
1521 unsigned NumBytes = CCInfo.getNextStackOffset();
1522 if (PerformTailCallOpt && CC == CallingConv::Fast)
1523 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1527 // Lower arguments at fp - stackoffset + fpdiff.
1528 unsigned NumBytesCallerPushed =
1529 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1530 FPDiff = NumBytesCallerPushed - NumBytes;
1532 // Set the delta of movement of the returnaddr stackslot.
1533 // But only set if delta is greater than previous delta.
1534 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1535 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1538 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1540 SDValue RetAddrFrIdx;
1541 // Load return adress for tail calls.
1542 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1545 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1546 SmallVector<SDValue, 8> MemOpChains;
1549 // Walk the register/memloc assignments, inserting copies/loads. In the case
1550 // of tail call optimization arguments are handle later.
1551 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1552 CCValAssign &VA = ArgLocs[i];
1553 SDValue Arg = TheCall->getArg(i);
1554 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1555 bool isByVal = Flags.isByVal();
1557 // Promote the value if needed.
1558 switch (VA.getLocInfo()) {
1559 default: assert(0 && "Unknown loc info!");
1560 case CCValAssign::Full: break;
1561 case CCValAssign::SExt:
1562 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1564 case CCValAssign::ZExt:
1565 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1567 case CCValAssign::AExt:
1568 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1572 if (VA.isRegLoc()) {
1574 MVT RegVT = VA.getLocVT();
1575 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1576 switch (VA.getLocReg()) {
1579 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1581 // Special case: passing MMX values in GPR registers.
1582 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1585 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1586 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1587 // Special case: passing MMX values in XMM registers.
1588 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1589 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1590 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1591 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1592 getMOVLMask(2, DAG));
1597 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1599 if (!IsTailCall || (IsTailCall && isByVal)) {
1600 assert(VA.isMemLoc());
1601 if (StackPtr.getNode() == 0)
1602 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1604 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1605 Chain, Arg, Flags));
1610 if (!MemOpChains.empty())
1611 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1612 &MemOpChains[0], MemOpChains.size());
1614 // Build a sequence of copy-to-reg nodes chained together with token chain
1615 // and flag operands which copy the outgoing args into registers.
1617 // Tail call byval lowering might overwrite argument registers so in case of
1618 // tail call optimization the copies to registers are lowered later.
1620 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1621 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1623 InFlag = Chain.getValue(1);
1626 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1628 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1629 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1630 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1632 InFlag = Chain.getValue(1);
1634 // If we are tail calling and generating PIC/GOT style code load the address
1635 // of the callee into ecx. The value in ecx is used as target of the tail
1636 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1637 // calls on PIC/GOT architectures. Normally we would just put the address of
1638 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1639 // restored (since ebx is callee saved) before jumping to the target@PLT.
1640 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1641 // Note: The actual moving to ecx is done further down.
1642 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1643 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1644 !G->getGlobal()->hasProtectedVisibility())
1645 Callee = LowerGlobalAddress(Callee, DAG);
1646 else if (isa<ExternalSymbolSDNode>(Callee))
1647 Callee = LowerExternalSymbol(Callee,DAG);
1650 if (Is64Bit && isVarArg) {
1651 // From AMD64 ABI document:
1652 // For calls that may call functions that use varargs or stdargs
1653 // (prototype-less calls or calls to functions containing ellipsis (...) in
1654 // the declaration) %al is used as hidden argument to specify the number
1655 // of SSE registers used. The contents of %al do not need to match exactly
1656 // the number of registers, but must be an ubound on the number of SSE
1657 // registers used and is in the range 0 - 8 inclusive.
1659 // FIXME: Verify this on Win64
1660 // Count the number of XMM registers allocated.
1661 static const unsigned XMMArgRegs[] = {
1662 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1663 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1665 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1667 Chain = DAG.getCopyToReg(Chain, X86::AL,
1668 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1669 InFlag = Chain.getValue(1);
1673 // For tail calls lower the arguments to the 'real' stack slot.
1675 SmallVector<SDValue, 8> MemOpChains2;
1678 // Do not flag preceeding copytoreg stuff together with the following stuff.
1680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1681 CCValAssign &VA = ArgLocs[i];
1682 if (!VA.isRegLoc()) {
1683 assert(VA.isMemLoc());
1684 SDValue Arg = TheCall->getArg(i);
1685 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1686 // Create frame index.
1687 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1688 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1689 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1690 FIN = DAG.getFrameIndex(FI, getPointerTy());
1692 if (Flags.isByVal()) {
1693 // Copy relative to framepointer.
1694 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1695 if (StackPtr.getNode() == 0)
1696 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1697 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1699 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1702 // Store relative to framepointer.
1703 MemOpChains2.push_back(
1704 DAG.getStore(Chain, Arg, FIN,
1705 PseudoSourceValue::getFixedStack(FI), 0));
1710 if (!MemOpChains2.empty())
1711 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1712 &MemOpChains2[0], MemOpChains2.size());
1714 // Copy arguments to their registers.
1715 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1716 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1718 InFlag = Chain.getValue(1);
1722 // Store the return address to the appropriate stack slot.
1723 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1727 // If the callee is a GlobalAddress node (quite common, every direct call is)
1728 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1729 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1730 // We should use extra load for direct calls to dllimported functions in
1732 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1733 getTargetMachine(), true))
1734 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1736 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1737 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1738 } else if (IsTailCall) {
1739 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1741 Chain = DAG.getCopyToReg(Chain,
1742 DAG.getRegister(Opc, getPointerTy()),
1744 Callee = DAG.getRegister(Opc, getPointerTy());
1745 // Add register as live out.
1746 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1749 // Returns a chain & a flag for retval copy to use.
1750 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1751 SmallVector<SDValue, 8> Ops;
1754 Ops.push_back(Chain);
1755 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1756 Ops.push_back(DAG.getIntPtrConstant(0, true));
1757 if (InFlag.getNode())
1758 Ops.push_back(InFlag);
1759 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1760 InFlag = Chain.getValue(1);
1762 // Returns a chain & a flag for retval copy to use.
1763 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1767 Ops.push_back(Chain);
1768 Ops.push_back(Callee);
1771 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1773 // Add argument registers to the end of the list so that they are known live
1775 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1776 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1777 RegsToPass[i].second.getValueType()));
1779 // Add an implicit use GOT pointer in EBX.
1780 if (!IsTailCall && !Is64Bit &&
1781 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1782 Subtarget->isPICStyleGOT())
1783 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1785 // Add an implicit use of AL for x86 vararg functions.
1786 if (Is64Bit && isVarArg)
1787 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1789 if (InFlag.getNode())
1790 Ops.push_back(InFlag);
1793 assert(InFlag.getNode() &&
1794 "Flag must be set. Depend on flag being set in LowerRET");
1795 Chain = DAG.getNode(X86ISD::TAILCALL,
1796 TheCall->getVTList(), &Ops[0], Ops.size());
1798 return SDValue(Chain.getNode(), Op.getResNo());
1801 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1802 InFlag = Chain.getValue(1);
1804 // Create the CALLSEQ_END node.
1805 unsigned NumBytesForCalleeToPush;
1806 if (IsCalleePop(isVarArg, CC))
1807 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1808 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1809 // If this is is a call to a struct-return function, the callee
1810 // pops the hidden struct pointer, so we have to push it back.
1811 // This is common for Darwin/X86, Linux & Mingw32 targets.
1812 NumBytesForCalleeToPush = 4;
1814 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1816 // Returns a flag for retval copy to use.
1817 Chain = DAG.getCALLSEQ_END(Chain,
1818 DAG.getIntPtrConstant(NumBytes, true),
1819 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1822 InFlag = Chain.getValue(1);
1824 // Handle result values, copying them out of physregs into vregs that we
1826 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1831 //===----------------------------------------------------------------------===//
1832 // Fast Calling Convention (tail call) implementation
1833 //===----------------------------------------------------------------------===//
1835 // Like std call, callee cleans arguments, convention except that ECX is
1836 // reserved for storing the tail called function address. Only 2 registers are
1837 // free for argument passing (inreg). Tail call optimization is performed
1839 // * tailcallopt is enabled
1840 // * caller/callee are fastcc
1841 // On X86_64 architecture with GOT-style position independent code only local
1842 // (within module) calls are supported at the moment.
1843 // To keep the stack aligned according to platform abi the function
1844 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1845 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1846 // If a tail called function callee has more arguments than the caller the
1847 // caller needs to make sure that there is room to move the RETADDR to. This is
1848 // achieved by reserving an area the size of the argument delta right after the
1849 // original REtADDR, but before the saved framepointer or the spilled registers
1850 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1862 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1863 /// for a 16 byte align requirement.
1864 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1865 SelectionDAG& DAG) {
1866 MachineFunction &MF = DAG.getMachineFunction();
1867 const TargetMachine &TM = MF.getTarget();
1868 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1869 unsigned StackAlignment = TFI.getStackAlignment();
1870 uint64_t AlignMask = StackAlignment - 1;
1871 int64_t Offset = StackSize;
1872 uint64_t SlotSize = TD->getPointerSize();
1873 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1874 // Number smaller than 12 so just add the difference.
1875 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1877 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1878 Offset = ((~AlignMask) & Offset) + StackAlignment +
1879 (StackAlignment-SlotSize);
1884 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1885 /// following the call is a return. A function is eligible if caller/callee
1886 /// calling conventions match, currently only fastcc supports tail calls, and
1887 /// the function CALL is immediatly followed by a RET.
1888 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1890 SelectionDAG& DAG) const {
1891 if (!PerformTailCallOpt)
1894 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1895 MachineFunction &MF = DAG.getMachineFunction();
1896 unsigned CallerCC = MF.getFunction()->getCallingConv();
1897 unsigned CalleeCC= TheCall->getCallingConv();
1898 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1899 SDValue Callee = TheCall->getCallee();
1900 // On x86/32Bit PIC/GOT tail calls are supported.
1901 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1902 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1905 // Can only do local tail calls (in same module, hidden or protected) on
1906 // x86_64 PIC/GOT at the moment.
1907 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1908 return G->getGlobal()->hasHiddenVisibility()
1909 || G->getGlobal()->hasProtectedVisibility();
1917 X86TargetLowering::createFastISel(MachineFunction &mf,
1918 MachineModuleInfo *mmo,
1919 DenseMap<const Value *, unsigned> &vm,
1920 DenseMap<const BasicBlock *,
1921 MachineBasicBlock *> &bm,
1922 DenseMap<const AllocaInst *, int> &am
1924 , SmallSet<Instruction*, 8> &cil
1927 return X86::createFastISel(mf, mmo, vm, bm, am
1935 //===----------------------------------------------------------------------===//
1936 // Other Lowering Hooks
1937 //===----------------------------------------------------------------------===//
1940 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1941 MachineFunction &MF = DAG.getMachineFunction();
1942 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1943 int ReturnAddrIndex = FuncInfo->getRAIndex();
1944 uint64_t SlotSize = TD->getPointerSize();
1946 if (ReturnAddrIndex == 0) {
1947 // Set up a frame object for the return address.
1948 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1949 FuncInfo->setRAIndex(ReturnAddrIndex);
1952 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1956 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1957 /// specific condition code. It returns a false if it cannot do a direct
1958 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1960 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1961 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1962 SelectionDAG &DAG) {
1963 X86CC = X86::COND_INVALID;
1965 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1966 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1967 // X > -1 -> X == 0, jump !sign.
1968 RHS = DAG.getConstant(0, RHS.getValueType());
1969 X86CC = X86::COND_NS;
1971 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1972 // X < 0 -> X == 0, jump on sign.
1973 X86CC = X86::COND_S;
1975 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1977 RHS = DAG.getConstant(0, RHS.getValueType());
1978 X86CC = X86::COND_LE;
1983 switch (SetCCOpcode) {
1985 case ISD::SETEQ: X86CC = X86::COND_E; break;
1986 case ISD::SETGT: X86CC = X86::COND_G; break;
1987 case ISD::SETGE: X86CC = X86::COND_GE; break;
1988 case ISD::SETLT: X86CC = X86::COND_L; break;
1989 case ISD::SETLE: X86CC = X86::COND_LE; break;
1990 case ISD::SETNE: X86CC = X86::COND_NE; break;
1991 case ISD::SETULT: X86CC = X86::COND_B; break;
1992 case ISD::SETUGT: X86CC = X86::COND_A; break;
1993 case ISD::SETULE: X86CC = X86::COND_BE; break;
1994 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1997 // First determine if it is required or is profitable to flip the operands.
1999 // If LHS is a foldable load, but RHS is not, flip the condition.
2000 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2001 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2002 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2003 std::swap(LHS, RHS);
2006 switch (SetCCOpcode) {
2012 std::swap(LHS, RHS);
2016 // On a floating point condition, the flags are set as follows:
2018 // 0 | 0 | 0 | X > Y
2019 // 0 | 0 | 1 | X < Y
2020 // 1 | 0 | 0 | X == Y
2021 // 1 | 1 | 1 | unordered
2022 switch (SetCCOpcode) {
2026 X86CC = X86::COND_E;
2028 case ISD::SETOLT: // flipped
2031 X86CC = X86::COND_A;
2033 case ISD::SETOLE: // flipped
2036 X86CC = X86::COND_AE;
2038 case ISD::SETUGT: // flipped
2041 X86CC = X86::COND_B;
2043 case ISD::SETUGE: // flipped
2046 X86CC = X86::COND_BE;
2050 X86CC = X86::COND_NE;
2053 X86CC = X86::COND_P;
2056 X86CC = X86::COND_NP;
2061 return X86CC != X86::COND_INVALID;
2064 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2065 /// code. Current x86 isa includes the following FP cmov instructions:
2066 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2067 static bool hasFPCMov(unsigned X86CC) {
2083 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2084 /// true if Op is undef or if its value falls within the specified range (L, H].
2085 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2086 if (Op.getOpcode() == ISD::UNDEF)
2089 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2090 return (Val >= Low && Val < Hi);
2093 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2094 /// true if Op is undef or if its value equal to the specified value.
2095 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2096 if (Op.getOpcode() == ISD::UNDEF)
2098 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2101 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2102 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2103 bool X86::isPSHUFDMask(SDNode *N) {
2104 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2106 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2109 // Check if the value doesn't reference the second vector.
2110 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2111 SDValue Arg = N->getOperand(i);
2112 if (Arg.getOpcode() == ISD::UNDEF) continue;
2113 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2114 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2121 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2122 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2123 bool X86::isPSHUFHWMask(SDNode *N) {
2124 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2126 if (N->getNumOperands() != 8)
2129 // Lower quadword copied in order.
2130 for (unsigned i = 0; i != 4; ++i) {
2131 SDValue Arg = N->getOperand(i);
2132 if (Arg.getOpcode() == ISD::UNDEF) continue;
2133 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2134 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2138 // Upper quadword shuffled.
2139 for (unsigned i = 4; i != 8; ++i) {
2140 SDValue Arg = N->getOperand(i);
2141 if (Arg.getOpcode() == ISD::UNDEF) continue;
2142 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2143 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2144 if (Val < 4 || Val > 7)
2151 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2152 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2153 bool X86::isPSHUFLWMask(SDNode *N) {
2154 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2156 if (N->getNumOperands() != 8)
2159 // Upper quadword copied in order.
2160 for (unsigned i = 4; i != 8; ++i)
2161 if (!isUndefOrEqual(N->getOperand(i), i))
2164 // Lower quadword shuffled.
2165 for (unsigned i = 0; i != 4; ++i)
2166 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2172 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2173 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2174 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2175 if (NumElems != 2 && NumElems != 4) return false;
2177 unsigned Half = NumElems / 2;
2178 for (unsigned i = 0; i < Half; ++i)
2179 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2181 for (unsigned i = Half; i < NumElems; ++i)
2182 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2188 bool X86::isSHUFPMask(SDNode *N) {
2189 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2190 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2193 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2194 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2195 /// half elements to come from vector 1 (which would equal the dest.) and
2196 /// the upper half to come from vector 2.
2197 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2198 if (NumOps != 2 && NumOps != 4) return false;
2200 unsigned Half = NumOps / 2;
2201 for (unsigned i = 0; i < Half; ++i)
2202 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2204 for (unsigned i = Half; i < NumOps; ++i)
2205 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2210 static bool isCommutedSHUFP(SDNode *N) {
2211 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2212 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2215 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2216 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2217 bool X86::isMOVHLPSMask(SDNode *N) {
2218 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2220 if (N->getNumOperands() != 4)
2223 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2224 return isUndefOrEqual(N->getOperand(0), 6) &&
2225 isUndefOrEqual(N->getOperand(1), 7) &&
2226 isUndefOrEqual(N->getOperand(2), 2) &&
2227 isUndefOrEqual(N->getOperand(3), 3);
2230 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2231 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2233 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2234 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2236 if (N->getNumOperands() != 4)
2239 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2240 return isUndefOrEqual(N->getOperand(0), 2) &&
2241 isUndefOrEqual(N->getOperand(1), 3) &&
2242 isUndefOrEqual(N->getOperand(2), 2) &&
2243 isUndefOrEqual(N->getOperand(3), 3);
2246 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2247 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2248 bool X86::isMOVLPMask(SDNode *N) {
2249 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2251 unsigned NumElems = N->getNumOperands();
2252 if (NumElems != 2 && NumElems != 4)
2255 for (unsigned i = 0; i < NumElems/2; ++i)
2256 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2259 for (unsigned i = NumElems/2; i < NumElems; ++i)
2260 if (!isUndefOrEqual(N->getOperand(i), i))
2266 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2267 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2269 bool X86::isMOVHPMask(SDNode *N) {
2270 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2272 unsigned NumElems = N->getNumOperands();
2273 if (NumElems != 2 && NumElems != 4)
2276 for (unsigned i = 0; i < NumElems/2; ++i)
2277 if (!isUndefOrEqual(N->getOperand(i), i))
2280 for (unsigned i = 0; i < NumElems/2; ++i) {
2281 SDValue Arg = N->getOperand(i + NumElems/2);
2282 if (!isUndefOrEqual(Arg, i + NumElems))
2289 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2290 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2291 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2292 bool V2IsSplat = false) {
2293 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2296 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2297 SDValue BitI = Elts[i];
2298 SDValue BitI1 = Elts[i+1];
2299 if (!isUndefOrEqual(BitI, j))
2302 if (isUndefOrEqual(BitI1, NumElts))
2305 if (!isUndefOrEqual(BitI1, j + NumElts))
2313 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2314 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2315 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2318 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2319 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2320 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2321 bool V2IsSplat = false) {
2322 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2325 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2326 SDValue BitI = Elts[i];
2327 SDValue BitI1 = Elts[i+1];
2328 if (!isUndefOrEqual(BitI, j + NumElts/2))
2331 if (isUndefOrEqual(BitI1, NumElts))
2334 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2342 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2343 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2344 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2347 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2348 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2350 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2351 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2353 unsigned NumElems = N->getNumOperands();
2354 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2357 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2358 SDValue BitI = N->getOperand(i);
2359 SDValue BitI1 = N->getOperand(i+1);
2361 if (!isUndefOrEqual(BitI, j))
2363 if (!isUndefOrEqual(BitI1, j))
2370 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2371 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2373 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2374 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2376 unsigned NumElems = N->getNumOperands();
2377 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2380 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2381 SDValue BitI = N->getOperand(i);
2382 SDValue BitI1 = N->getOperand(i + 1);
2384 if (!isUndefOrEqual(BitI, j))
2386 if (!isUndefOrEqual(BitI1, j))
2393 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2394 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2395 /// MOVSD, and MOVD, i.e. setting the lowest element.
2396 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2397 if (NumElts != 2 && NumElts != 4)
2400 if (!isUndefOrEqual(Elts[0], NumElts))
2403 for (unsigned i = 1; i < NumElts; ++i) {
2404 if (!isUndefOrEqual(Elts[i], i))
2411 bool X86::isMOVLMask(SDNode *N) {
2412 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2413 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2416 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2417 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2418 /// element of vector 2 and the other elements to come from vector 1 in order.
2419 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2420 bool V2IsSplat = false,
2421 bool V2IsUndef = false) {
2422 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2425 if (!isUndefOrEqual(Ops[0], 0))
2428 for (unsigned i = 1; i < NumOps; ++i) {
2429 SDValue Arg = Ops[i];
2430 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2431 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2432 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2439 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2440 bool V2IsUndef = false) {
2441 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2442 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2443 V2IsSplat, V2IsUndef);
2446 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2447 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2448 bool X86::isMOVSHDUPMask(SDNode *N) {
2449 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2451 if (N->getNumOperands() != 4)
2454 // Expect 1, 1, 3, 3
2455 for (unsigned i = 0; i < 2; ++i) {
2456 SDValue Arg = N->getOperand(i);
2457 if (Arg.getOpcode() == ISD::UNDEF) continue;
2458 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2459 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2460 if (Val != 1) return false;
2464 for (unsigned i = 2; i < 4; ++i) {
2465 SDValue Arg = N->getOperand(i);
2466 if (Arg.getOpcode() == ISD::UNDEF) continue;
2467 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2468 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2469 if (Val != 3) return false;
2473 // Don't use movshdup if it can be done with a shufps.
2477 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2478 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2479 bool X86::isMOVSLDUPMask(SDNode *N) {
2480 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2482 if (N->getNumOperands() != 4)
2485 // Expect 0, 0, 2, 2
2486 for (unsigned i = 0; i < 2; ++i) {
2487 SDValue Arg = N->getOperand(i);
2488 if (Arg.getOpcode() == ISD::UNDEF) continue;
2489 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2490 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2491 if (Val != 0) return false;
2495 for (unsigned i = 2; i < 4; ++i) {
2496 SDValue Arg = N->getOperand(i);
2497 if (Arg.getOpcode() == ISD::UNDEF) continue;
2498 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2499 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2500 if (Val != 2) return false;
2504 // Don't use movshdup if it can be done with a shufps.
2508 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2509 /// specifies a identity operation on the LHS or RHS.
2510 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2511 unsigned NumElems = N->getNumOperands();
2512 for (unsigned i = 0; i < NumElems; ++i)
2513 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2518 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2519 /// a splat of a single element.
2520 static bool isSplatMask(SDNode *N) {
2521 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2523 // This is a splat operation if each element of the permute is the same, and
2524 // if the value doesn't reference the second vector.
2525 unsigned NumElems = N->getNumOperands();
2526 SDValue ElementBase;
2528 for (; i != NumElems; ++i) {
2529 SDValue Elt = N->getOperand(i);
2530 if (isa<ConstantSDNode>(Elt)) {
2536 if (!ElementBase.getNode())
2539 for (; i != NumElems; ++i) {
2540 SDValue Arg = N->getOperand(i);
2541 if (Arg.getOpcode() == ISD::UNDEF) continue;
2542 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2543 if (Arg != ElementBase) return false;
2546 // Make sure it is a splat of the first vector operand.
2547 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2550 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2551 /// a splat of a single element and it's a 2 or 4 element mask.
2552 bool X86::isSplatMask(SDNode *N) {
2553 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2555 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2556 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2558 return ::isSplatMask(N);
2561 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2562 /// specifies a splat of zero element.
2563 bool X86::isSplatLoMask(SDNode *N) {
2564 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2566 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2567 if (!isUndefOrEqual(N->getOperand(i), 0))
2572 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2573 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2574 bool X86::isMOVDDUPMask(SDNode *N) {
2575 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2577 unsigned e = N->getNumOperands() / 2;
2578 for (unsigned i = 0; i < e; ++i)
2579 if (!isUndefOrEqual(N->getOperand(i), i))
2581 for (unsigned i = 0; i < e; ++i)
2582 if (!isUndefOrEqual(N->getOperand(e+i), i))
2587 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2588 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2590 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2591 unsigned NumOperands = N->getNumOperands();
2592 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2594 for (unsigned i = 0; i < NumOperands; ++i) {
2596 SDValue Arg = N->getOperand(NumOperands-i-1);
2597 if (Arg.getOpcode() != ISD::UNDEF)
2598 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2599 if (Val >= NumOperands) Val -= NumOperands;
2601 if (i != NumOperands - 1)
2608 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2609 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2611 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2613 // 8 nodes, but we only care about the last 4.
2614 for (unsigned i = 7; i >= 4; --i) {
2616 SDValue Arg = N->getOperand(i);
2617 if (Arg.getOpcode() != ISD::UNDEF)
2618 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2627 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2628 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2630 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2632 // 8 nodes, but we only care about the first 4.
2633 for (int i = 3; i >= 0; --i) {
2635 SDValue Arg = N->getOperand(i);
2636 if (Arg.getOpcode() != ISD::UNDEF)
2637 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2646 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2647 /// specifies a 8 element shuffle that can be broken into a pair of
2648 /// PSHUFHW and PSHUFLW.
2649 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2650 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2652 if (N->getNumOperands() != 8)
2655 // Lower quadword shuffled.
2656 for (unsigned i = 0; i != 4; ++i) {
2657 SDValue Arg = N->getOperand(i);
2658 if (Arg.getOpcode() == ISD::UNDEF) continue;
2659 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2660 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2665 // Upper quadword shuffled.
2666 for (unsigned i = 4; i != 8; ++i) {
2667 SDValue Arg = N->getOperand(i);
2668 if (Arg.getOpcode() == ISD::UNDEF) continue;
2669 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2670 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2671 if (Val < 4 || Val > 7)
2678 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2679 /// values in ther permute mask.
2680 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2681 SDValue &V2, SDValue &Mask,
2682 SelectionDAG &DAG) {
2683 MVT VT = Op.getValueType();
2684 MVT MaskVT = Mask.getValueType();
2685 MVT EltVT = MaskVT.getVectorElementType();
2686 unsigned NumElems = Mask.getNumOperands();
2687 SmallVector<SDValue, 8> MaskVec;
2689 for (unsigned i = 0; i != NumElems; ++i) {
2690 SDValue Arg = Mask.getOperand(i);
2691 if (Arg.getOpcode() == ISD::UNDEF) {
2692 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2695 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2696 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2698 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2700 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2704 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2705 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2708 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2709 /// the two vector operands have swapped position.
2711 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2712 MVT MaskVT = Mask.getValueType();
2713 MVT EltVT = MaskVT.getVectorElementType();
2714 unsigned NumElems = Mask.getNumOperands();
2715 SmallVector<SDValue, 8> MaskVec;
2716 for (unsigned i = 0; i != NumElems; ++i) {
2717 SDValue Arg = Mask.getOperand(i);
2718 if (Arg.getOpcode() == ISD::UNDEF) {
2719 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2722 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2723 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2725 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2727 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2729 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2733 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2734 /// match movhlps. The lower half elements should come from upper half of
2735 /// V1 (and in order), and the upper half elements should come from the upper
2736 /// half of V2 (and in order).
2737 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2738 unsigned NumElems = Mask->getNumOperands();
2741 for (unsigned i = 0, e = 2; i != e; ++i)
2742 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2744 for (unsigned i = 2; i != 4; ++i)
2745 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2750 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2751 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2753 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2754 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2756 N = N->getOperand(0).getNode();
2757 if (!ISD::isNON_EXTLoad(N))
2760 *LD = cast<LoadSDNode>(N);
2764 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2765 /// match movlp{s|d}. The lower half elements should come from lower half of
2766 /// V1 (and in order), and the upper half elements should come from the upper
2767 /// half of V2 (and in order). And since V1 will become the source of the
2768 /// MOVLP, it must be either a vector load or a scalar load to vector.
2769 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2770 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2772 // Is V2 is a vector load, don't do this transformation. We will try to use
2773 // load folding shufps op.
2774 if (ISD::isNON_EXTLoad(V2))
2777 unsigned NumElems = Mask->getNumOperands();
2778 if (NumElems != 2 && NumElems != 4)
2780 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2781 if (!isUndefOrEqual(Mask->getOperand(i), i))
2783 for (unsigned i = NumElems/2; i != NumElems; ++i)
2784 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2789 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2791 static bool isSplatVector(SDNode *N) {
2792 if (N->getOpcode() != ISD::BUILD_VECTOR)
2795 SDValue SplatValue = N->getOperand(0);
2796 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2797 if (N->getOperand(i) != SplatValue)
2802 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2804 static bool isUndefShuffle(SDNode *N) {
2805 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2808 SDValue V1 = N->getOperand(0);
2809 SDValue V2 = N->getOperand(1);
2810 SDValue Mask = N->getOperand(2);
2811 unsigned NumElems = Mask.getNumOperands();
2812 for (unsigned i = 0; i != NumElems; ++i) {
2813 SDValue Arg = Mask.getOperand(i);
2814 if (Arg.getOpcode() != ISD::UNDEF) {
2815 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2816 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2818 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2825 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2827 static inline bool isZeroNode(SDValue Elt) {
2828 return ((isa<ConstantSDNode>(Elt) &&
2829 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2830 (isa<ConstantFPSDNode>(Elt) &&
2831 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2834 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2835 /// to an zero vector.
2836 static bool isZeroShuffle(SDNode *N) {
2837 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2840 SDValue V1 = N->getOperand(0);
2841 SDValue V2 = N->getOperand(1);
2842 SDValue Mask = N->getOperand(2);
2843 unsigned NumElems = Mask.getNumOperands();
2844 for (unsigned i = 0; i != NumElems; ++i) {
2845 SDValue Arg = Mask.getOperand(i);
2846 if (Arg.getOpcode() == ISD::UNDEF)
2849 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2850 if (Idx < NumElems) {
2851 unsigned Opc = V1.getNode()->getOpcode();
2852 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2854 if (Opc != ISD::BUILD_VECTOR ||
2855 !isZeroNode(V1.getNode()->getOperand(Idx)))
2857 } else if (Idx >= NumElems) {
2858 unsigned Opc = V2.getNode()->getOpcode();
2859 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2861 if (Opc != ISD::BUILD_VECTOR ||
2862 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2869 /// getZeroVector - Returns a vector of specified type with all zero elements.
2871 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2872 assert(VT.isVector() && "Expected a vector type");
2874 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2875 // type. This ensures they get CSE'd.
2877 if (VT.getSizeInBits() == 64) { // MMX
2878 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2879 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2880 } else if (HasSSE2) { // SSE2
2881 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2882 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2884 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2885 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2887 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2890 /// getOnesVector - Returns a vector of specified type with all bits set.
2892 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2893 assert(VT.isVector() && "Expected a vector type");
2895 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2896 // type. This ensures they get CSE'd.
2897 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2899 if (VT.getSizeInBits() == 64) // MMX
2900 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2902 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2903 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2907 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2908 /// that point to V2 points to its first element.
2909 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2910 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2912 bool Changed = false;
2913 SmallVector<SDValue, 8> MaskVec;
2914 unsigned NumElems = Mask.getNumOperands();
2915 for (unsigned i = 0; i != NumElems; ++i) {
2916 SDValue Arg = Mask.getOperand(i);
2917 if (Arg.getOpcode() != ISD::UNDEF) {
2918 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2919 if (Val > NumElems) {
2920 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2924 MaskVec.push_back(Arg);
2928 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2929 &MaskVec[0], MaskVec.size());
2933 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2934 /// operation of specified width.
2935 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2936 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2937 MVT BaseVT = MaskVT.getVectorElementType();
2939 SmallVector<SDValue, 8> MaskVec;
2940 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2941 for (unsigned i = 1; i != NumElems; ++i)
2942 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2943 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2946 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2947 /// of specified width.
2948 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2949 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2950 MVT BaseVT = MaskVT.getVectorElementType();
2951 SmallVector<SDValue, 8> MaskVec;
2952 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2953 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2954 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2956 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2959 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2960 /// of specified width.
2961 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2962 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2963 MVT BaseVT = MaskVT.getVectorElementType();
2964 unsigned Half = NumElems/2;
2965 SmallVector<SDValue, 8> MaskVec;
2966 for (unsigned i = 0; i != Half; ++i) {
2967 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2968 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2970 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2973 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2974 /// element #0 of a vector with the specified index, leaving the rest of the
2975 /// elements in place.
2976 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2977 SelectionDAG &DAG) {
2978 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2979 MVT BaseVT = MaskVT.getVectorElementType();
2980 SmallVector<SDValue, 8> MaskVec;
2981 // Element #0 of the result gets the elt we are replacing.
2982 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2983 for (unsigned i = 1; i != NumElems; ++i)
2984 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2985 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2988 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2989 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2990 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2991 MVT VT = Op.getValueType();
2994 SDValue V1 = Op.getOperand(0);
2995 SDValue Mask = Op.getOperand(2);
2996 unsigned NumElems = Mask.getNumOperands();
2997 // Special handling of v4f32 -> v4i32.
2998 if (VT != MVT::v4f32) {
2999 Mask = getUnpacklMask(NumElems, DAG);
3000 while (NumElems > 4) {
3001 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
3004 Mask = getZeroVector(MVT::v4i32, true, DAG);
3007 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3008 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3009 DAG.getNode(ISD::UNDEF, PVT), Mask);
3010 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3013 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3014 /// load that's promoted to vector, or a load bitcasted.
3015 static bool isVectorLoad(SDValue Op) {
3016 assert(Op.getValueType().isVector() && "Expected a vector type");
3017 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3018 Op.getOpcode() == ISD::BIT_CONVERT) {
3019 return isa<LoadSDNode>(Op.getOperand(0));
3021 return isa<LoadSDNode>(Op);
3025 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3027 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3028 SelectionDAG &DAG, bool HasSSE3) {
3029 // If we have sse3 and shuffle has more than one use or input is a load, then
3030 // use movddup. Otherwise, use movlhps.
3031 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3032 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3033 MVT VT = Op.getValueType();
3036 unsigned NumElems = PVT.getVectorNumElements();
3037 if (NumElems == 2) {
3038 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3039 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3041 assert(NumElems == 4);
3042 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3043 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3044 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3047 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3048 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3049 DAG.getNode(ISD::UNDEF, PVT), Mask);
3050 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3053 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3054 /// vector of zero or undef vector. This produces a shuffle where the low
3055 /// element of V2 is swizzled into the zero/undef vector, landing at element
3056 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3057 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3058 bool isZero, bool HasSSE2,
3059 SelectionDAG &DAG) {
3060 MVT VT = V2.getValueType();
3062 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3063 unsigned NumElems = V2.getValueType().getVectorNumElements();
3064 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3065 MVT EVT = MaskVT.getVectorElementType();
3066 SmallVector<SDValue, 16> MaskVec;
3067 for (unsigned i = 0; i != NumElems; ++i)
3068 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3069 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3071 MaskVec.push_back(DAG.getConstant(i, EVT));
3072 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3073 &MaskVec[0], MaskVec.size());
3074 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3077 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3078 /// a shuffle that is zero.
3080 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3081 unsigned NumElems, bool Low,
3082 SelectionDAG &DAG) {
3083 unsigned NumZeros = 0;
3084 for (unsigned i = 0; i < NumElems; ++i) {
3085 unsigned Index = Low ? i : NumElems-i-1;
3086 SDValue Idx = Mask.getOperand(Index);
3087 if (Idx.getOpcode() == ISD::UNDEF) {
3091 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3092 if (Elt.getNode() && isZeroNode(Elt))
3100 /// isVectorShift - Returns true if the shuffle can be implemented as a
3101 /// logical left or right shift of a vector.
3102 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3103 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3104 unsigned NumElems = Mask.getNumOperands();
3107 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3110 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3115 bool SeenV1 = false;
3116 bool SeenV2 = false;
3117 for (unsigned i = NumZeros; i < NumElems; ++i) {
3118 unsigned Val = isLeft ? (i - NumZeros) : i;
3119 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3120 if (Idx.getOpcode() == ISD::UNDEF)
3122 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3123 if (Index < NumElems)
3132 if (SeenV1 && SeenV2)
3135 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3141 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3143 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3144 unsigned NumNonZero, unsigned NumZero,
3145 SelectionDAG &DAG, TargetLowering &TLI) {
3151 for (unsigned i = 0; i < 16; ++i) {
3152 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3153 if (ThisIsNonZero && First) {
3155 V = getZeroVector(MVT::v8i16, true, DAG);
3157 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3162 SDValue ThisElt(0, 0), LastElt(0, 0);
3163 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3164 if (LastIsNonZero) {
3165 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3167 if (ThisIsNonZero) {
3168 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3169 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3170 ThisElt, DAG.getConstant(8, MVT::i8));
3172 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3176 if (ThisElt.getNode())
3177 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3178 DAG.getIntPtrConstant(i/2));
3182 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3185 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3187 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3188 unsigned NumNonZero, unsigned NumZero,
3189 SelectionDAG &DAG, TargetLowering &TLI) {
3195 for (unsigned i = 0; i < 8; ++i) {
3196 bool isNonZero = (NonZeros & (1 << i)) != 0;
3200 V = getZeroVector(MVT::v8i16, true, DAG);
3202 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3205 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3206 DAG.getIntPtrConstant(i));
3213 /// getVShift - Return a vector logical shift node.
3215 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3216 unsigned NumBits, SelectionDAG &DAG,
3217 const TargetLowering &TLI) {
3218 bool isMMX = VT.getSizeInBits() == 64;
3219 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3220 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3221 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3222 return DAG.getNode(ISD::BIT_CONVERT, VT,
3223 DAG.getNode(Opc, ShVT, SrcOp,
3224 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3228 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3229 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3230 if (ISD::isBuildVectorAllZeros(Op.getNode())
3231 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3232 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3233 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3234 // eliminated on x86-32 hosts.
3235 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3238 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3239 return getOnesVector(Op.getValueType(), DAG);
3240 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3243 MVT VT = Op.getValueType();
3244 MVT EVT = VT.getVectorElementType();
3245 unsigned EVTBits = EVT.getSizeInBits();
3247 unsigned NumElems = Op.getNumOperands();
3248 unsigned NumZero = 0;
3249 unsigned NumNonZero = 0;
3250 unsigned NonZeros = 0;
3251 bool IsAllConstants = true;
3252 SmallSet<SDValue, 8> Values;
3253 for (unsigned i = 0; i < NumElems; ++i) {
3254 SDValue Elt = Op.getOperand(i);
3255 if (Elt.getOpcode() == ISD::UNDEF)
3258 if (Elt.getOpcode() != ISD::Constant &&
3259 Elt.getOpcode() != ISD::ConstantFP)
3260 IsAllConstants = false;
3261 if (isZeroNode(Elt))
3264 NonZeros |= (1 << i);
3269 if (NumNonZero == 0) {
3270 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3271 return DAG.getNode(ISD::UNDEF, VT);
3274 // Special case for single non-zero, non-undef, element.
3275 if (NumNonZero == 1 && NumElems <= 4) {
3276 unsigned Idx = CountTrailingZeros_32(NonZeros);
3277 SDValue Item = Op.getOperand(Idx);
3279 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3280 // the value are obviously zero, truncate the value to i32 and do the
3281 // insertion that way. Only do this if the value is non-constant or if the
3282 // value is a constant being inserted into element 0. It is cheaper to do
3283 // a constant pool load than it is to do a movd + shuffle.
3284 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3285 (!IsAllConstants || Idx == 0)) {
3286 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3287 // Handle MMX and SSE both.
3288 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3289 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3291 // Truncate the value (which may itself be a constant) to i32, and
3292 // convert it to a vector with movd (S2V+shuffle to zero extend).
3293 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3294 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3295 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3296 Subtarget->hasSSE2(), DAG);
3298 // Now we have our 32-bit value zero extended in the low element of
3299 // a vector. If Idx != 0, swizzle it into place.
3302 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3303 getSwapEltZeroMask(VecElts, Idx, DAG)
3305 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3307 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3311 // If we have a constant or non-constant insertion into the low element of
3312 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3313 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3314 // depending on what the source datatype is. Because we can only get here
3315 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3317 // Don't do this for i64 values on x86-32.
3318 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3319 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3320 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3321 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3322 Subtarget->hasSSE2(), DAG);
3325 // Is it a vector logical left shift?
3326 if (NumElems == 2 && Idx == 1 &&
3327 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3328 unsigned NumBits = VT.getSizeInBits();
3329 return getVShift(true, VT,
3330 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3331 NumBits/2, DAG, *this);
3334 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3337 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3338 // is a non-constant being inserted into an element other than the low one,
3339 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3340 // movd/movss) to move this into the low element, then shuffle it into
3342 if (EVTBits == 32) {
3343 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3345 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3346 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3347 Subtarget->hasSSE2(), DAG);
3348 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3349 MVT MaskEVT = MaskVT.getVectorElementType();
3350 SmallVector<SDValue, 8> MaskVec;
3351 for (unsigned i = 0; i < NumElems; i++)
3352 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3353 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3354 &MaskVec[0], MaskVec.size());
3355 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3356 DAG.getNode(ISD::UNDEF, VT), Mask);
3360 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3361 if (Values.size() == 1)
3364 // A vector full of immediates; various special cases are already
3365 // handled, so this is best done with a single constant-pool load.
3369 // Let legalizer expand 2-wide build_vectors.
3370 if (EVTBits == 64) {
3371 if (NumNonZero == 1) {
3372 // One half is zero or undef.
3373 unsigned Idx = CountTrailingZeros_32(NonZeros);
3374 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3375 Op.getOperand(Idx));
3376 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3377 Subtarget->hasSSE2(), DAG);
3382 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3383 if (EVTBits == 8 && NumElems == 16) {
3384 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3386 if (V.getNode()) return V;
3389 if (EVTBits == 16 && NumElems == 8) {
3390 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3392 if (V.getNode()) return V;
3395 // If element VT is == 32 bits, turn it into a number of shuffles.
3396 SmallVector<SDValue, 8> V;
3398 if (NumElems == 4 && NumZero > 0) {
3399 for (unsigned i = 0; i < 4; ++i) {
3400 bool isZero = !(NonZeros & (1 << i));
3402 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3404 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3407 for (unsigned i = 0; i < 2; ++i) {
3408 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3411 V[i] = V[i*2]; // Must be a zero vector.
3414 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3415 getMOVLMask(NumElems, DAG));
3418 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3419 getMOVLMask(NumElems, DAG));
3422 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3423 getUnpacklMask(NumElems, DAG));
3428 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3429 MVT EVT = MaskVT.getVectorElementType();
3430 SmallVector<SDValue, 8> MaskVec;
3431 bool Reverse = (NonZeros & 0x3) == 2;
3432 for (unsigned i = 0; i < 2; ++i)
3434 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3436 MaskVec.push_back(DAG.getConstant(i, EVT));
3437 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3438 for (unsigned i = 0; i < 2; ++i)
3440 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3442 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3443 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3444 &MaskVec[0], MaskVec.size());
3445 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3448 if (Values.size() > 2) {
3449 // Expand into a number of unpckl*.
3451 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3452 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3453 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3454 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3455 for (unsigned i = 0; i < NumElems; ++i)
3456 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3458 while (NumElems != 0) {
3459 for (unsigned i = 0; i < NumElems; ++i)
3460 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3471 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3472 SDValue PermMask, SelectionDAG &DAG,
3473 TargetLowering &TLI) {
3475 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3476 MVT MaskEVT = MaskVT.getVectorElementType();
3477 MVT PtrVT = TLI.getPointerTy();
3478 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3479 PermMask.getNode()->op_end());
3481 // First record which half of which vector the low elements come from.
3482 SmallVector<unsigned, 4> LowQuad(4);
3483 for (unsigned i = 0; i < 4; ++i) {
3484 SDValue Elt = MaskElts[i];
3485 if (Elt.getOpcode() == ISD::UNDEF)
3487 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3488 int QuadIdx = EltIdx / 4;
3492 int BestLowQuad = -1;
3493 unsigned MaxQuad = 1;
3494 for (unsigned i = 0; i < 4; ++i) {
3495 if (LowQuad[i] > MaxQuad) {
3497 MaxQuad = LowQuad[i];
3501 // Record which half of which vector the high elements come from.
3502 SmallVector<unsigned, 4> HighQuad(4);
3503 for (unsigned i = 4; i < 8; ++i) {
3504 SDValue Elt = MaskElts[i];
3505 if (Elt.getOpcode() == ISD::UNDEF)
3507 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3508 int QuadIdx = EltIdx / 4;
3509 ++HighQuad[QuadIdx];
3512 int BestHighQuad = -1;
3514 for (unsigned i = 0; i < 4; ++i) {
3515 if (HighQuad[i] > MaxQuad) {
3517 MaxQuad = HighQuad[i];
3521 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3522 if (BestLowQuad != -1 || BestHighQuad != -1) {
3523 // First sort the 4 chunks in order using shufpd.
3524 SmallVector<SDValue, 8> MaskVec;
3526 if (BestLowQuad != -1)
3527 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3529 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3531 if (BestHighQuad != -1)
3532 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3534 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3536 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3537 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3538 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3539 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3540 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3542 // Now sort high and low parts separately.
3543 BitVector InOrder(8);
3544 if (BestLowQuad != -1) {
3545 // Sort lower half in order using PSHUFLW.
3547 bool AnyOutOrder = false;
3549 for (unsigned i = 0; i != 4; ++i) {
3550 SDValue Elt = MaskElts[i];
3551 if (Elt.getOpcode() == ISD::UNDEF) {
3552 MaskVec.push_back(Elt);
3555 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3559 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3561 // If this element is in the right place after this shuffle, then
3563 if ((int)(EltIdx / 4) == BestLowQuad)
3568 for (unsigned i = 4; i != 8; ++i)
3569 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3570 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3571 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3575 if (BestHighQuad != -1) {
3576 // Sort high half in order using PSHUFHW if possible.
3579 for (unsigned i = 0; i != 4; ++i)
3580 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3582 bool AnyOutOrder = false;
3583 for (unsigned i = 4; i != 8; ++i) {
3584 SDValue Elt = MaskElts[i];
3585 if (Elt.getOpcode() == ISD::UNDEF) {
3586 MaskVec.push_back(Elt);
3589 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3593 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3595 // If this element is in the right place after this shuffle, then
3597 if ((int)(EltIdx / 4) == BestHighQuad)
3603 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3604 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3608 // The other elements are put in the right place using pextrw and pinsrw.
3609 for (unsigned i = 0; i != 8; ++i) {
3612 SDValue Elt = MaskElts[i];
3613 if (Elt.getOpcode() == ISD::UNDEF)
3615 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3616 SDValue ExtOp = (EltIdx < 8)
3617 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3618 DAG.getConstant(EltIdx, PtrVT))
3619 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3620 DAG.getConstant(EltIdx - 8, PtrVT));
3621 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3622 DAG.getConstant(i, PtrVT));
3628 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3629 // few as possible. First, let's find out how many elements are already in the
3631 unsigned V1InOrder = 0;
3632 unsigned V1FromV1 = 0;
3633 unsigned V2InOrder = 0;
3634 unsigned V2FromV2 = 0;
3635 SmallVector<SDValue, 8> V1Elts;
3636 SmallVector<SDValue, 8> V2Elts;
3637 for (unsigned i = 0; i < 8; ++i) {
3638 SDValue Elt = MaskElts[i];
3639 if (Elt.getOpcode() == ISD::UNDEF) {
3640 V1Elts.push_back(Elt);
3641 V2Elts.push_back(Elt);
3646 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3648 V1Elts.push_back(Elt);
3649 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3651 } else if (EltIdx == i+8) {
3652 V1Elts.push_back(Elt);
3653 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3655 } else if (EltIdx < 8) {
3656 V1Elts.push_back(Elt);
3659 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3664 if (V2InOrder > V1InOrder) {
3665 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3667 std::swap(V1Elts, V2Elts);
3668 std::swap(V1FromV1, V2FromV2);
3671 if ((V1FromV1 + V1InOrder) != 8) {
3672 // Some elements are from V2.
3674 // If there are elements that are from V1 but out of place,
3675 // then first sort them in place
3676 SmallVector<SDValue, 8> MaskVec;
3677 for (unsigned i = 0; i < 8; ++i) {
3678 SDValue Elt = V1Elts[i];
3679 if (Elt.getOpcode() == ISD::UNDEF) {
3680 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3683 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3685 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3687 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3689 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3690 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3694 for (unsigned i = 0; i < 8; ++i) {
3695 SDValue Elt = V1Elts[i];
3696 if (Elt.getOpcode() == ISD::UNDEF)
3698 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3701 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3702 DAG.getConstant(EltIdx - 8, PtrVT));
3703 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3704 DAG.getConstant(i, PtrVT));
3708 // All elements are from V1.
3710 for (unsigned i = 0; i < 8; ++i) {
3711 SDValue Elt = V1Elts[i];
3712 if (Elt.getOpcode() == ISD::UNDEF)
3714 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3715 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3716 DAG.getConstant(EltIdx, PtrVT));
3717 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3718 DAG.getConstant(i, PtrVT));
3724 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3725 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3726 /// done when every pair / quad of shuffle mask elements point to elements in
3727 /// the right sequence. e.g.
3728 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3730 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3732 SDValue PermMask, SelectionDAG &DAG,
3733 TargetLowering &TLI) {
3734 unsigned NumElems = PermMask.getNumOperands();
3735 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3736 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3737 MVT MaskEltVT = MaskVT.getVectorElementType();
3739 switch (VT.getSimpleVT()) {
3740 default: assert(false && "Unexpected!");
3741 case MVT::v4f32: NewVT = MVT::v2f64; break;
3742 case MVT::v4i32: NewVT = MVT::v2i64; break;
3743 case MVT::v8i16: NewVT = MVT::v4i32; break;
3744 case MVT::v16i8: NewVT = MVT::v4i32; break;
3747 if (NewWidth == 2) {
3753 unsigned Scale = NumElems / NewWidth;
3754 SmallVector<SDValue, 8> MaskVec;
3755 for (unsigned i = 0; i < NumElems; i += Scale) {
3756 unsigned StartIdx = ~0U;
3757 for (unsigned j = 0; j < Scale; ++j) {
3758 SDValue Elt = PermMask.getOperand(i+j);
3759 if (Elt.getOpcode() == ISD::UNDEF)
3761 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3762 if (StartIdx == ~0U)
3763 StartIdx = EltIdx - (EltIdx % Scale);
3764 if (EltIdx != StartIdx + j)
3767 if (StartIdx == ~0U)
3768 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3770 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3773 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3774 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3775 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3776 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3777 &MaskVec[0], MaskVec.size()));
3780 /// getVZextMovL - Return a zero-extending vector move low node.
3782 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3783 SDValue SrcOp, SelectionDAG &DAG,
3784 const X86Subtarget *Subtarget) {
3785 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3786 LoadSDNode *LD = NULL;
3787 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3788 LD = dyn_cast<LoadSDNode>(SrcOp);
3790 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3792 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3793 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3794 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3795 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3796 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3798 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3799 return DAG.getNode(ISD::BIT_CONVERT, VT,
3800 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3801 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3808 return DAG.getNode(ISD::BIT_CONVERT, VT,
3809 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3810 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3813 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3816 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3817 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3818 MVT MaskVT = PermMask.getValueType();
3819 MVT MaskEVT = MaskVT.getVectorElementType();
3820 SmallVector<std::pair<int, int>, 8> Locs;
3822 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3825 for (unsigned i = 0; i != 4; ++i) {
3826 SDValue Elt = PermMask.getOperand(i);
3827 if (Elt.getOpcode() == ISD::UNDEF) {
3828 Locs[i] = std::make_pair(-1, -1);
3830 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3831 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3833 Locs[i] = std::make_pair(0, NumLo);
3837 Locs[i] = std::make_pair(1, NumHi);
3839 Mask1[2+NumHi] = Elt;
3845 if (NumLo <= 2 && NumHi <= 2) {
3846 // If no more than two elements come from either vector. This can be
3847 // implemented with two shuffles. First shuffle gather the elements.
3848 // The second shuffle, which takes the first shuffle as both of its
3849 // vector operands, put the elements into the right order.
3850 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3851 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3852 &Mask1[0], Mask1.size()));
3854 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3855 for (unsigned i = 0; i != 4; ++i) {
3856 if (Locs[i].first == -1)
3859 unsigned Idx = (i < 2) ? 0 : 4;
3860 Idx += Locs[i].first * 2 + Locs[i].second;
3861 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3865 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3866 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3867 &Mask2[0], Mask2.size()));
3868 } else if (NumLo == 3 || NumHi == 3) {
3869 // Otherwise, we must have three elements from one vector, call it X, and
3870 // one element from the other, call it Y. First, use a shufps to build an
3871 // intermediate vector with the one element from Y and the element from X
3872 // that will be in the same half in the final destination (the indexes don't
3873 // matter). Then, use a shufps to build the final vector, taking the half
3874 // containing the element from Y from the intermediate, and the other half
3877 // Normalize it so the 3 elements come from V1.
3878 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3882 // Find the element from V2.
3884 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3885 SDValue Elt = PermMask.getOperand(HiIndex);
3886 if (Elt.getOpcode() == ISD::UNDEF)
3888 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3893 Mask1[0] = PermMask.getOperand(HiIndex);
3894 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3895 Mask1[2] = PermMask.getOperand(HiIndex^1);
3896 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3897 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3898 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3901 Mask1[0] = PermMask.getOperand(0);
3902 Mask1[1] = PermMask.getOperand(1);
3903 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3904 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3905 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3906 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3908 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3909 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3910 Mask1[2] = PermMask.getOperand(2);
3911 Mask1[3] = PermMask.getOperand(3);
3912 if (Mask1[2].getOpcode() != ISD::UNDEF)
3914 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3916 if (Mask1[3].getOpcode() != ISD::UNDEF)
3918 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3920 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3921 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3925 // Break it into (shuffle shuffle_hi, shuffle_lo).
3927 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3928 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3929 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3930 unsigned MaskIdx = 0;
3933 for (unsigned i = 0; i != 4; ++i) {
3940 SDValue Elt = PermMask.getOperand(i);
3941 if (Elt.getOpcode() == ISD::UNDEF) {
3942 Locs[i] = std::make_pair(-1, -1);
3943 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3944 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3945 (*MaskPtr)[LoIdx] = Elt;
3948 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3949 (*MaskPtr)[HiIdx] = Elt;
3954 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3955 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3956 &LoMask[0], LoMask.size()));
3957 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3958 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3959 &HiMask[0], HiMask.size()));
3960 SmallVector<SDValue, 8> MaskOps;
3961 for (unsigned i = 0; i != 4; ++i) {
3962 if (Locs[i].first == -1) {
3963 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3965 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3966 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3969 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3970 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3971 &MaskOps[0], MaskOps.size()));
3975 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3976 SDValue V1 = Op.getOperand(0);
3977 SDValue V2 = Op.getOperand(1);
3978 SDValue PermMask = Op.getOperand(2);
3979 MVT VT = Op.getValueType();
3980 unsigned NumElems = PermMask.getNumOperands();
3981 bool isMMX = VT.getSizeInBits() == 64;
3982 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3983 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3984 bool V1IsSplat = false;
3985 bool V2IsSplat = false;
3987 if (isUndefShuffle(Op.getNode()))
3988 return DAG.getNode(ISD::UNDEF, VT);
3990 if (isZeroShuffle(Op.getNode()))
3991 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3993 if (isIdentityMask(PermMask.getNode()))
3995 else if (isIdentityMask(PermMask.getNode(), true))
3998 // Canonicalize movddup shuffles.
3999 if (V2IsUndef && Subtarget->hasSSE2() &&
4000 VT.getSizeInBits() == 128 &&
4001 X86::isMOVDDUPMask(PermMask.getNode()))
4002 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4004 if (isSplatMask(PermMask.getNode())) {
4005 if (isMMX || NumElems < 4) return Op;
4006 // Promote it to a v4{if}32 splat.
4007 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4010 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4012 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4013 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
4014 if (NewOp.getNode())
4015 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
4016 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4017 // FIXME: Figure out a cleaner way to do this.
4018 // Try to make use of movq to zero out the top part.
4019 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4020 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4022 if (NewOp.getNode()) {
4023 SDValue NewV1 = NewOp.getOperand(0);
4024 SDValue NewV2 = NewOp.getOperand(1);
4025 SDValue NewMask = NewOp.getOperand(2);
4026 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4027 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4028 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4031 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4032 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4034 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4035 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4040 // Check if this can be converted into a logical shift.
4041 bool isLeft = false;
4044 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4045 if (isShift && ShVal.hasOneUse()) {
4046 // If the shifted value has multiple uses, it may be cheaper to use
4047 // v_set0 + movlhps or movhlps, etc.
4048 MVT EVT = VT.getVectorElementType();
4049 ShAmt *= EVT.getSizeInBits();
4050 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4053 if (X86::isMOVLMask(PermMask.getNode())) {
4056 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4057 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4062 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4063 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4064 X86::isMOVHLPSMask(PermMask.getNode()) ||
4065 X86::isMOVHPMask(PermMask.getNode()) ||
4066 X86::isMOVLPMask(PermMask.getNode())))
4069 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4070 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4071 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4074 // No better options. Use a vshl / vsrl.
4075 MVT EVT = VT.getVectorElementType();
4076 ShAmt *= EVT.getSizeInBits();
4077 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4080 bool Commuted = false;
4081 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4082 // 1,1,1,1 -> v8i16 though.
4083 V1IsSplat = isSplatVector(V1.getNode());
4084 V2IsSplat = isSplatVector(V2.getNode());
4086 // Canonicalize the splat or undef, if present, to be on the RHS.
4087 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4088 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4089 std::swap(V1IsSplat, V2IsSplat);
4090 std::swap(V1IsUndef, V2IsUndef);
4094 // FIXME: Figure out a cleaner way to do this.
4095 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4096 if (V2IsUndef) return V1;
4097 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4099 // V2 is a splat, so the mask may be malformed. That is, it may point
4100 // to any V2 element. The instruction selectior won't like this. Get
4101 // a corrected mask and commute to form a proper MOVS{S|D}.
4102 SDValue NewMask = getMOVLMask(NumElems, DAG);
4103 if (NewMask.getNode() != PermMask.getNode())
4104 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4109 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4110 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4111 X86::isUNPCKLMask(PermMask.getNode()) ||
4112 X86::isUNPCKHMask(PermMask.getNode()))
4116 // Normalize mask so all entries that point to V2 points to its first
4117 // element then try to match unpck{h|l} again. If match, return a
4118 // new vector_shuffle with the corrected mask.
4119 SDValue NewMask = NormalizeMask(PermMask, DAG);
4120 if (NewMask.getNode() != PermMask.getNode()) {
4121 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4122 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4123 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4124 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4125 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4126 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4131 // Normalize the node to match x86 shuffle ops if needed
4132 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4133 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4136 // Commute is back and try unpck* again.
4137 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4138 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4139 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4140 X86::isUNPCKLMask(PermMask.getNode()) ||
4141 X86::isUNPCKHMask(PermMask.getNode()))
4145 // Try PSHUF* first, then SHUFP*.
4146 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4147 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4148 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4149 if (V2.getOpcode() != ISD::UNDEF)
4150 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4151 DAG.getNode(ISD::UNDEF, VT), PermMask);
4156 if (Subtarget->hasSSE2() &&
4157 (X86::isPSHUFDMask(PermMask.getNode()) ||
4158 X86::isPSHUFHWMask(PermMask.getNode()) ||
4159 X86::isPSHUFLWMask(PermMask.getNode()))) {
4161 if (VT == MVT::v4f32) {
4163 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4164 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4165 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4166 } else if (V2.getOpcode() != ISD::UNDEF)
4167 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4168 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4170 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4174 // Binary or unary shufps.
4175 if (X86::isSHUFPMask(PermMask.getNode()) ||
4176 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4180 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4181 if (VT == MVT::v8i16) {
4182 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4183 if (NewOp.getNode())
4187 // Handle all 4 wide cases with a number of shuffles except for MMX.
4188 if (NumElems == 4 && !isMMX)
4189 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4195 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4196 SelectionDAG &DAG) {
4197 MVT VT = Op.getValueType();
4198 if (VT.getSizeInBits() == 8) {
4199 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4200 Op.getOperand(0), Op.getOperand(1));
4201 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4202 DAG.getValueType(VT));
4203 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4204 } else if (VT.getSizeInBits() == 16) {
4205 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4206 Op.getOperand(0), Op.getOperand(1));
4207 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4208 DAG.getValueType(VT));
4209 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4210 } else if (VT == MVT::f32) {
4211 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4212 // the result back to FR32 register. It's only worth matching if the
4213 // result has a single use which is a store or a bitcast to i32. And in
4214 // the case of a store, it's not worth it if the index is a constant 0,
4215 // because a MOVSSmr can be used instead, which is smaller and faster.
4216 if (!Op.hasOneUse())
4218 SDNode *User = *Op.getNode()->use_begin();
4219 if ((User->getOpcode() != ISD::STORE ||
4220 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4221 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4222 (User->getOpcode() != ISD::BIT_CONVERT ||
4223 User->getValueType(0) != MVT::i32))
4225 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4226 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4228 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4235 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4236 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4239 if (Subtarget->hasSSE41()) {
4240 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4245 MVT VT = Op.getValueType();
4246 // TODO: handle v16i8.
4247 if (VT.getSizeInBits() == 16) {
4248 SDValue Vec = Op.getOperand(0);
4249 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4251 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4252 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4253 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4255 // Transform it so it match pextrw which produces a 32-bit result.
4256 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4257 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4258 Op.getOperand(0), Op.getOperand(1));
4259 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4260 DAG.getValueType(VT));
4261 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4262 } else if (VT.getSizeInBits() == 32) {
4263 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4266 // SHUFPS the element to the lowest double word, then movss.
4267 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4268 SmallVector<SDValue, 8> IdxVec;
4270 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4272 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4274 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4276 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4277 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4278 &IdxVec[0], IdxVec.size());
4279 SDValue Vec = Op.getOperand(0);
4280 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4281 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4282 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4283 DAG.getIntPtrConstant(0));
4284 } else if (VT.getSizeInBits() == 64) {
4285 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4286 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4287 // to match extract_elt for f64.
4288 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4292 // UNPCKHPD the element to the lowest double word, then movsd.
4293 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4294 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4295 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4296 SmallVector<SDValue, 8> IdxVec;
4297 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4299 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4300 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4301 &IdxVec[0], IdxVec.size());
4302 SDValue Vec = Op.getOperand(0);
4303 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4304 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4305 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4306 DAG.getIntPtrConstant(0));
4313 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4314 MVT VT = Op.getValueType();
4315 MVT EVT = VT.getVectorElementType();
4317 SDValue N0 = Op.getOperand(0);
4318 SDValue N1 = Op.getOperand(1);
4319 SDValue N2 = Op.getOperand(2);
4321 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4322 isa<ConstantSDNode>(N2)) {
4323 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4325 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4327 if (N1.getValueType() != MVT::i32)
4328 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4329 if (N2.getValueType() != MVT::i32)
4330 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4331 return DAG.getNode(Opc, VT, N0, N1, N2);
4332 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4333 // Bits [7:6] of the constant are the source select. This will always be
4334 // zero here. The DAG Combiner may combine an extract_elt index into these
4335 // bits. For example (insert (extract, 3), 2) could be matched by putting
4336 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4337 // Bits [5:4] of the constant are the destination select. This is the
4338 // value of the incoming immediate.
4339 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4340 // combine either bitwise AND or insert of float 0.0 to set these bits.
4341 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4342 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4348 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4349 MVT VT = Op.getValueType();
4350 MVT EVT = VT.getVectorElementType();
4352 if (Subtarget->hasSSE41())
4353 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4358 SDValue N0 = Op.getOperand(0);
4359 SDValue N1 = Op.getOperand(1);
4360 SDValue N2 = Op.getOperand(2);
4362 if (EVT.getSizeInBits() == 16) {
4363 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4364 // as its second argument.
4365 if (N1.getValueType() != MVT::i32)
4366 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4367 if (N2.getValueType() != MVT::i32)
4368 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4369 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4375 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4376 if (Op.getValueType() == MVT::v2f32)
4377 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4378 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4379 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4380 Op.getOperand(0))));
4382 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4383 MVT VT = MVT::v2i32;
4384 switch (Op.getValueType().getSimpleVT()) {
4391 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4392 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4395 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4396 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4397 // one of the above mentioned nodes. It has to be wrapped because otherwise
4398 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4399 // be used to form addressing mode. These wrapped nodes will be selected
4402 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4403 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4404 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4406 CP->getAlignment());
4407 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4408 // With PIC, the address is actually $g + Offset.
4409 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4410 !Subtarget->isPICStyleRIPRel()) {
4411 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4412 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4420 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4422 SelectionDAG &DAG) const {
4423 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4424 bool ExtraLoadRequired =
4425 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4427 // Create the TargetGlobalAddress node, folding in the constant
4428 // offset if it is legal.
4430 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4431 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4434 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4435 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4437 // With PIC, the address is actually $g + Offset.
4438 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4439 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4440 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4444 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4445 // load the value at address GV, not the value of GV itself. This means that
4446 // the GlobalAddress must be in the base or index register of the address, not
4447 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4448 // The same applies for external symbols during PIC codegen
4449 if (ExtraLoadRequired)
4450 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4451 PseudoSourceValue::getGOT(), 0);
4453 // If there was a non-zero offset that we didn't fold, create an explicit
4456 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4457 DAG.getConstant(Offset, getPointerTy()));
4463 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4464 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4465 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4466 return LowerGlobalAddress(GV, Offset, DAG);
4469 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4471 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4474 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4475 DAG.getNode(X86ISD::GlobalBaseReg,
4477 InFlag = Chain.getValue(1);
4479 // emit leal symbol@TLSGD(,%ebx,1), %eax
4480 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4481 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4482 GA->getValueType(0),
4484 SDValue Ops[] = { Chain, TGA, InFlag };
4485 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4486 InFlag = Result.getValue(2);
4487 Chain = Result.getValue(1);
4489 // call ___tls_get_addr. This function receives its argument in
4490 // the register EAX.
4491 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4492 InFlag = Chain.getValue(1);
4494 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4495 SDValue Ops1[] = { Chain,
4496 DAG.getTargetExternalSymbol("___tls_get_addr",
4498 DAG.getRegister(X86::EAX, PtrVT),
4499 DAG.getRegister(X86::EBX, PtrVT),
4501 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4502 InFlag = Chain.getValue(1);
4504 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4507 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4509 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4511 SDValue InFlag, Chain;
4513 // emit leaq symbol@TLSGD(%rip), %rdi
4514 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4515 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4516 GA->getValueType(0),
4518 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4519 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4520 Chain = Result.getValue(1);
4521 InFlag = Result.getValue(2);
4523 // call __tls_get_addr. This function receives its argument in
4524 // the register RDI.
4525 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4526 InFlag = Chain.getValue(1);
4528 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4529 SDValue Ops1[] = { Chain,
4530 DAG.getTargetExternalSymbol("__tls_get_addr",
4532 DAG.getRegister(X86::RDI, PtrVT),
4534 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4535 InFlag = Chain.getValue(1);
4537 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4540 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4541 // "local exec" model.
4542 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4544 // Get the Thread Pointer
4545 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4546 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4548 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4549 GA->getValueType(0),
4551 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4553 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4554 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4555 PseudoSourceValue::getGOT(), 0);
4557 // The address of the thread local variable is the add of the thread
4558 // pointer with the offset of the variable.
4559 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4563 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4564 // TODO: implement the "local dynamic" model
4565 // TODO: implement the "initial exec"model for pic executables
4566 assert(Subtarget->isTargetELF() &&
4567 "TLS not implemented for non-ELF targets");
4568 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4569 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4570 // otherwise use the "Local Exec"TLS Model
4571 if (Subtarget->is64Bit()) {
4572 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4574 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4575 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4577 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4582 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4583 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4584 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4585 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4586 // With PIC, the address is actually $g + Offset.
4587 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4588 !Subtarget->isPICStyleRIPRel()) {
4589 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4590 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4597 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4598 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4599 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4600 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4601 // With PIC, the address is actually $g + Offset.
4602 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4603 !Subtarget->isPICStyleRIPRel()) {
4604 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4605 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4612 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4613 /// take a 2 x i32 value to shift plus a shift amount.
4614 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4615 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4616 MVT VT = Op.getValueType();
4617 unsigned VTBits = VT.getSizeInBits();
4618 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4619 SDValue ShOpLo = Op.getOperand(0);
4620 SDValue ShOpHi = Op.getOperand(1);
4621 SDValue ShAmt = Op.getOperand(2);
4622 SDValue Tmp1 = isSRA ?
4623 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4624 DAG.getConstant(0, VT);
4627 if (Op.getOpcode() == ISD::SHL_PARTS) {
4628 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4629 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4631 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4632 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4635 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4636 DAG.getConstant(VTBits, MVT::i8));
4637 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4638 AndNode, DAG.getConstant(0, MVT::i8));
4641 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4642 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4643 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4645 if (Op.getOpcode() == ISD::SHL_PARTS) {
4646 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4647 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4649 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4650 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4653 SDValue Ops[2] = { Lo, Hi };
4654 return DAG.getMergeValues(Ops, 2);
4657 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4658 MVT SrcVT = Op.getOperand(0).getValueType();
4659 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4660 "Unknown SINT_TO_FP to lower!");
4662 // These are really Legal; caller falls through into that case.
4663 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4665 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4666 Subtarget->is64Bit())
4669 unsigned Size = SrcVT.getSizeInBits()/8;
4670 MachineFunction &MF = DAG.getMachineFunction();
4671 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4672 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4673 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4675 PseudoSourceValue::getFixedStack(SSFI), 0);
4679 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4681 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4683 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4684 SmallVector<SDValue, 8> Ops;
4685 Ops.push_back(Chain);
4686 Ops.push_back(StackSlot);
4687 Ops.push_back(DAG.getValueType(SrcVT));
4688 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4689 Tys, &Ops[0], Ops.size());
4692 Chain = Result.getValue(1);
4693 SDValue InFlag = Result.getValue(2);
4695 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4696 // shouldn't be necessary except that RFP cannot be live across
4697 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4698 MachineFunction &MF = DAG.getMachineFunction();
4699 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4700 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4701 Tys = DAG.getVTList(MVT::Other);
4702 SmallVector<SDValue, 8> Ops;
4703 Ops.push_back(Chain);
4704 Ops.push_back(Result);
4705 Ops.push_back(StackSlot);
4706 Ops.push_back(DAG.getValueType(Op.getValueType()));
4707 Ops.push_back(InFlag);
4708 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4709 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4710 PseudoSourceValue::getFixedStack(SSFI), 0);
4716 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4717 MVT SrcVT = Op.getOperand(0).getValueType();
4718 assert(SrcVT.getSimpleVT() == MVT::i64 && "Unknown UINT_TO_FP to lower!");
4720 // We only handle SSE2 f64 target here; caller can handle the rest.
4721 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4724 // This algorithm is not obvious. Here it is in C code, more or less:
4726 double uint64_to_double( uint32_t hi, uint32_t lo )
4728 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4729 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4731 // copy ints to xmm registers
4732 __m128i xh = _mm_cvtsi32_si128( hi );
4733 __m128i xl = _mm_cvtsi32_si128( lo );
4735 // combine into low half of a single xmm register
4736 __m128i x = _mm_unpacklo_epi32( xh, xl );
4740 // merge in appropriate exponents to give the integer bits the
4742 x = _mm_unpacklo_epi32( x, exp );
4744 // subtract away the biases to deal with the IEEE-754 double precision
4746 d = _mm_sub_pd( (__m128d) x, bias );
4748 // All conversions up to here are exact. The correctly rounded result is
4749 // calculated using the
4750 // current rounding mode using the following horizontal add.
4751 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4752 _mm_store_sd( &sd, d ); //since we are returning doubles in XMM, this
4753 // store doesn't really need to be here (except maybe to zero the other
4759 // Build some magic constants.
4760 std::vector<Constant*>CV0;
4761 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4762 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4763 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4764 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4765 Constant *C0 = ConstantVector::get(CV0);
4766 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4768 std::vector<Constant*>CV1;
4769 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4770 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4771 Constant *C1 = ConstantVector::get(CV1);
4772 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4774 SmallVector<SDValue, 4> MaskVec;
4775 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4776 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4777 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4778 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4779 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
4781 SmallVector<SDValue, 4> MaskVec2;
4782 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4783 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4784 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
4787 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4788 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4790 DAG.getIntPtrConstant(1)));
4791 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4792 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4794 DAG.getIntPtrConstant(0)));
4795 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4796 XR1, XR2, UnpcklMask);
4797 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
4798 PseudoSourceValue::getConstantPool(), 0, false, 16);
4799 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4800 Unpck1, CLod0, UnpcklMask);
4801 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
4802 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
4803 PseudoSourceValue::getConstantPool(), 0, false, 16);
4804 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
4805 // Add the halves; easiest way is to swap them into another reg first.
4806 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
4807 Sub, Sub, ShufMask);
4808 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
4809 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
4810 DAG.getIntPtrConstant(0));
4813 std::pair<SDValue,SDValue> X86TargetLowering::
4814 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4815 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4816 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4817 "Unknown FP_TO_SINT to lower!");
4819 // These are really Legal.
4820 if (Op.getValueType() == MVT::i32 &&
4821 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4822 return std::make_pair(SDValue(), SDValue());
4823 if (Subtarget->is64Bit() &&
4824 Op.getValueType() == MVT::i64 &&
4825 Op.getOperand(0).getValueType() != MVT::f80)
4826 return std::make_pair(SDValue(), SDValue());
4828 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4830 MachineFunction &MF = DAG.getMachineFunction();
4831 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4832 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4833 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4835 switch (Op.getValueType().getSimpleVT()) {
4836 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4837 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4838 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4839 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4842 SDValue Chain = DAG.getEntryNode();
4843 SDValue Value = Op.getOperand(0);
4844 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4845 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4846 Chain = DAG.getStore(Chain, Value, StackSlot,
4847 PseudoSourceValue::getFixedStack(SSFI), 0);
4848 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4850 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4852 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4853 Chain = Value.getValue(1);
4854 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4855 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4858 // Build the FP_TO_INT*_IN_MEM
4859 SDValue Ops[] = { Chain, Value, StackSlot };
4860 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4862 return std::make_pair(FIST, StackSlot);
4865 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4866 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4867 SDValue FIST = Vals.first, StackSlot = Vals.second;
4868 if (FIST.getNode() == 0) return SDValue();
4871 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4874 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4875 MVT VT = Op.getValueType();
4878 EltVT = VT.getVectorElementType();
4879 std::vector<Constant*> CV;
4880 if (EltVT == MVT::f64) {
4881 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4885 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4891 Constant *C = ConstantVector::get(CV);
4892 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4893 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4894 PseudoSourceValue::getConstantPool(), 0,
4896 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4899 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4900 MVT VT = Op.getValueType();
4902 unsigned EltNum = 1;
4903 if (VT.isVector()) {
4904 EltVT = VT.getVectorElementType();
4905 EltNum = VT.getVectorNumElements();
4907 std::vector<Constant*> CV;
4908 if (EltVT == MVT::f64) {
4909 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4913 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4919 Constant *C = ConstantVector::get(CV);
4920 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4921 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4922 PseudoSourceValue::getConstantPool(), 0,
4924 if (VT.isVector()) {
4925 return DAG.getNode(ISD::BIT_CONVERT, VT,
4926 DAG.getNode(ISD::XOR, MVT::v2i64,
4927 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4928 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4930 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4934 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4935 SDValue Op0 = Op.getOperand(0);
4936 SDValue Op1 = Op.getOperand(1);
4937 MVT VT = Op.getValueType();
4938 MVT SrcVT = Op1.getValueType();
4940 // If second operand is smaller, extend it first.
4941 if (SrcVT.bitsLT(VT)) {
4942 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4945 // And if it is bigger, shrink it first.
4946 if (SrcVT.bitsGT(VT)) {
4947 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4951 // At this point the operands and the result should have the same
4952 // type, and that won't be f80 since that is not custom lowered.
4954 // First get the sign bit of second operand.
4955 std::vector<Constant*> CV;
4956 if (SrcVT == MVT::f64) {
4957 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4958 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4960 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4961 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4962 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4963 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4965 Constant *C = ConstantVector::get(CV);
4966 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4967 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4968 PseudoSourceValue::getConstantPool(), 0,
4970 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4972 // Shift sign bit right or left if the two operands have different types.
4973 if (SrcVT.bitsGT(VT)) {
4974 // Op0 is MVT::f32, Op1 is MVT::f64.
4975 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4976 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4977 DAG.getConstant(32, MVT::i32));
4978 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4979 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4980 DAG.getIntPtrConstant(0));
4983 // Clear first operand sign bit.
4985 if (VT == MVT::f64) {
4986 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4987 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4989 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4990 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4991 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4992 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4994 C = ConstantVector::get(CV);
4995 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4996 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4997 PseudoSourceValue::getConstantPool(), 0,
4999 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
5001 // Or the value with the sign bit.
5002 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
5005 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5006 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5008 SDValue Op0 = Op.getOperand(0);
5009 SDValue Op1 = Op.getOperand(1);
5010 SDValue CC = Op.getOperand(2);
5011 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5014 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
5016 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
5017 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5018 DAG.getConstant(X86CC, MVT::i8), Cond);
5021 assert(0 && "Illegal SetCC!");
5025 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5027 SDValue Op0 = Op.getOperand(0);
5028 SDValue Op1 = Op.getOperand(1);
5029 SDValue CC = Op.getOperand(2);
5030 MVT VT = Op.getValueType();
5031 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5032 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5036 MVT VT0 = Op0.getValueType();
5037 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5038 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5041 switch (SetCCOpcode) {
5044 case ISD::SETEQ: SSECC = 0; break;
5046 case ISD::SETGT: Swap = true; // Fallthrough
5048 case ISD::SETOLT: SSECC = 1; break;
5050 case ISD::SETGE: Swap = true; // Fallthrough
5052 case ISD::SETOLE: SSECC = 2; break;
5053 case ISD::SETUO: SSECC = 3; break;
5055 case ISD::SETNE: SSECC = 4; break;
5056 case ISD::SETULE: Swap = true;
5057 case ISD::SETUGE: SSECC = 5; break;
5058 case ISD::SETULT: Swap = true;
5059 case ISD::SETUGT: SSECC = 6; break;
5060 case ISD::SETO: SSECC = 7; break;
5063 std::swap(Op0, Op1);
5065 // In the two special cases we can't handle, emit two comparisons.
5067 if (SetCCOpcode == ISD::SETUEQ) {
5069 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5070 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5071 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
5073 else if (SetCCOpcode == ISD::SETONE) {
5075 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5076 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5077 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
5079 assert(0 && "Illegal FP comparison");
5081 // Handle all other FP comparisons here.
5082 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5085 // We are handling one of the integer comparisons here. Since SSE only has
5086 // GT and EQ comparisons for integer, swapping operands and multiple
5087 // operations may be required for some comparisons.
5088 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5089 bool Swap = false, Invert = false, FlipSigns = false;
5091 switch (VT.getSimpleVT()) {
5093 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5094 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5095 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5096 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5099 switch (SetCCOpcode) {
5101 case ISD::SETNE: Invert = true;
5102 case ISD::SETEQ: Opc = EQOpc; break;
5103 case ISD::SETLT: Swap = true;
5104 case ISD::SETGT: Opc = GTOpc; break;
5105 case ISD::SETGE: Swap = true;
5106 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5107 case ISD::SETULT: Swap = true;
5108 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5109 case ISD::SETUGE: Swap = true;
5110 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5113 std::swap(Op0, Op1);
5115 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5116 // bits of the inputs before performing those operations.
5118 MVT EltVT = VT.getVectorElementType();
5119 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5120 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5121 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5123 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5124 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5127 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5129 // If the logical-not of the result is required, perform that now.
5131 MVT EltVT = VT.getVectorElementType();
5132 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
5133 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
5134 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
5136 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
5141 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5142 static bool isX86LogicalCmp(unsigned Opc) {
5143 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
5146 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5147 bool addTest = true;
5148 SDValue Cond = Op.getOperand(0);
5151 if (Cond.getOpcode() == ISD::SETCC)
5152 Cond = LowerSETCC(Cond, DAG);
5154 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5155 // setting operand in place of the X86ISD::SETCC.
5156 if (Cond.getOpcode() == X86ISD::SETCC) {
5157 CC = Cond.getOperand(0);
5159 SDValue Cmp = Cond.getOperand(1);
5160 unsigned Opc = Cmp.getOpcode();
5161 MVT VT = Op.getValueType();
5163 bool IllegalFPCMov = false;
5164 if (VT.isFloatingPoint() && !VT.isVector() &&
5165 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5166 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5168 if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
5175 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5176 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5179 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5181 SmallVector<SDValue, 4> Ops;
5182 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5183 // condition is true.
5184 Ops.push_back(Op.getOperand(2));
5185 Ops.push_back(Op.getOperand(1));
5187 Ops.push_back(Cond);
5188 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5191 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5192 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5193 // from the AND / OR.
5194 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5195 Opc = Op.getOpcode();
5196 if (Opc != ISD::OR && Opc != ISD::AND)
5198 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5199 Op.getOperand(0).hasOneUse() &&
5200 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5201 Op.getOperand(1).hasOneUse());
5204 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5205 bool addTest = true;
5206 SDValue Chain = Op.getOperand(0);
5207 SDValue Cond = Op.getOperand(1);
5208 SDValue Dest = Op.getOperand(2);
5211 if (Cond.getOpcode() == ISD::SETCC)
5212 Cond = LowerSETCC(Cond, DAG);
5213 else if (Cond.getOpcode() == X86ISD::ADD ||
5214 Cond.getOpcode() == X86ISD::SUB ||
5215 Cond.getOpcode() == X86ISD::MUL)
5216 Cond = LowerXALUO(Cond, DAG);
5218 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5219 // setting operand in place of the X86ISD::SETCC.
5220 if (Cond.getOpcode() == X86ISD::SETCC) {
5221 CC = Cond.getOperand(0);
5223 SDValue Cmp = Cond.getOperand(1);
5224 unsigned Opc = Cmp.getOpcode();
5225 if (isX86LogicalCmp(Opc)) {
5229 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5233 // These can only come from an arithmetic instruction with overflow, e.g.
5235 Cond = Cond.getNode()->getOperand(1);
5242 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5243 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5244 unsigned Opc = Cmp.getOpcode();
5245 if (CondOpc == ISD::OR) {
5246 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5247 // two branches instead of an explicit OR instruction with a
5249 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5250 isX86LogicalCmp(Opc)) {
5251 CC = Cond.getOperand(0).getOperand(0);
5252 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5253 Chain, Dest, CC, Cmp);
5254 CC = Cond.getOperand(1).getOperand(0);
5258 } else { // ISD::AND
5259 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5260 // two branches instead of an explicit AND instruction with a
5261 // separate test. However, we only do this if this block doesn't
5262 // have a fall-through edge, because this requires an explicit
5263 // jmp when the condition is false.
5264 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5265 isX86LogicalCmp(Opc) &&
5266 Op.getNode()->hasOneUse()) {
5267 X86::CondCode CCode =
5268 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5269 CCode = X86::GetOppositeBranchCondition(CCode);
5270 CC = DAG.getConstant(CCode, MVT::i8);
5271 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5272 // Look for an unconditional branch following this conditional branch.
5273 // We need this because we need to reverse the successors in order
5274 // to implement FCMP_OEQ.
5275 if (User.getOpcode() == ISD::BR) {
5276 SDValue FalseBB = User.getOperand(1);
5278 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5279 assert(NewBR == User);
5282 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5283 Chain, Dest, CC, Cmp);
5284 X86::CondCode CCode =
5285 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5286 CCode = X86::GetOppositeBranchCondition(CCode);
5287 CC = DAG.getConstant(CCode, MVT::i8);
5297 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5298 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5300 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5301 Chain, Dest, CC, Cond);
5305 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5306 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5307 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5308 // that the guard pages used by the OS virtual memory manager are allocated in
5309 // correct sequence.
5311 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5312 SelectionDAG &DAG) {
5313 assert(Subtarget->isTargetCygMing() &&
5314 "This should be used only on Cygwin/Mingw targets");
5317 SDValue Chain = Op.getOperand(0);
5318 SDValue Size = Op.getOperand(1);
5319 // FIXME: Ensure alignment here
5323 MVT IntPtr = getPointerTy();
5324 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5326 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5328 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5329 Flag = Chain.getValue(1);
5331 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5332 SDValue Ops[] = { Chain,
5333 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5334 DAG.getRegister(X86::EAX, IntPtr),
5335 DAG.getRegister(X86StackPtr, SPTy),
5337 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5338 Flag = Chain.getValue(1);
5340 Chain = DAG.getCALLSEQ_END(Chain,
5341 DAG.getIntPtrConstant(0, true),
5342 DAG.getIntPtrConstant(0, true),
5345 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5347 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5348 return DAG.getMergeValues(Ops1, 2);
5352 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5354 SDValue Dst, SDValue Src,
5355 SDValue Size, unsigned Align,
5357 uint64_t DstSVOff) {
5358 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5360 // If not DWORD aligned or size is more than the threshold, call the library.
5361 // The libc version is likely to be faster for these cases. It can use the
5362 // address value and run time information about the CPU.
5363 if ((Align & 3) != 0 ||
5365 ConstantSize->getZExtValue() >
5366 getSubtarget()->getMaxInlineSizeThreshold()) {
5367 SDValue InFlag(0, 0);
5369 // Check to see if there is a specialized entry-point for memory zeroing.
5370 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5372 if (const char *bzeroEntry = V &&
5373 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5374 MVT IntPtr = getPointerTy();
5375 const Type *IntPtrTy = TD->getIntPtrType();
5376 TargetLowering::ArgListTy Args;
5377 TargetLowering::ArgListEntry Entry;
5379 Entry.Ty = IntPtrTy;
5380 Args.push_back(Entry);
5382 Args.push_back(Entry);
5383 std::pair<SDValue,SDValue> CallResult =
5384 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5385 CallingConv::C, false,
5386 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
5387 return CallResult.second;
5390 // Otherwise have the target-independent code call memset.
5394 uint64_t SizeVal = ConstantSize->getZExtValue();
5395 SDValue InFlag(0, 0);
5398 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5399 unsigned BytesLeft = 0;
5400 bool TwoRepStos = false;
5403 uint64_t Val = ValC->getZExtValue() & 255;
5405 // If the value is a constant, then we can potentially use larger sets.
5406 switch (Align & 3) {
5407 case 2: // WORD aligned
5410 Val = (Val << 8) | Val;
5412 case 0: // DWORD aligned
5415 Val = (Val << 8) | Val;
5416 Val = (Val << 16) | Val;
5417 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5420 Val = (Val << 32) | Val;
5423 default: // Byte aligned
5426 Count = DAG.getIntPtrConstant(SizeVal);
5430 if (AVT.bitsGT(MVT::i8)) {
5431 unsigned UBytes = AVT.getSizeInBits() / 8;
5432 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5433 BytesLeft = SizeVal % UBytes;
5436 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5438 InFlag = Chain.getValue(1);
5441 Count = DAG.getIntPtrConstant(SizeVal);
5442 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5443 InFlag = Chain.getValue(1);
5446 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5448 InFlag = Chain.getValue(1);
5449 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5451 InFlag = Chain.getValue(1);
5453 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5454 SmallVector<SDValue, 8> Ops;
5455 Ops.push_back(Chain);
5456 Ops.push_back(DAG.getValueType(AVT));
5457 Ops.push_back(InFlag);
5458 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5461 InFlag = Chain.getValue(1);
5463 MVT CVT = Count.getValueType();
5464 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5465 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5466 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5468 InFlag = Chain.getValue(1);
5469 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5471 Ops.push_back(Chain);
5472 Ops.push_back(DAG.getValueType(MVT::i8));
5473 Ops.push_back(InFlag);
5474 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5475 } else if (BytesLeft) {
5476 // Handle the last 1 - 7 bytes.
5477 unsigned Offset = SizeVal - BytesLeft;
5478 MVT AddrVT = Dst.getValueType();
5479 MVT SizeVT = Size.getValueType();
5481 Chain = DAG.getMemset(Chain,
5482 DAG.getNode(ISD::ADD, AddrVT, Dst,
5483 DAG.getConstant(Offset, AddrVT)),
5485 DAG.getConstant(BytesLeft, SizeVT),
5486 Align, DstSV, DstSVOff + Offset);
5489 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5494 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5495 SDValue Chain, SDValue Dst, SDValue Src,
5496 SDValue Size, unsigned Align,
5498 const Value *DstSV, uint64_t DstSVOff,
5499 const Value *SrcSV, uint64_t SrcSVOff) {
5500 // This requires the copy size to be a constant, preferrably
5501 // within a subtarget-specific limit.
5502 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5505 uint64_t SizeVal = ConstantSize->getZExtValue();
5506 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5509 /// If not DWORD aligned, call the library.
5510 if ((Align & 3) != 0)
5515 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5518 unsigned UBytes = AVT.getSizeInBits() / 8;
5519 unsigned CountVal = SizeVal / UBytes;
5520 SDValue Count = DAG.getIntPtrConstant(CountVal);
5521 unsigned BytesLeft = SizeVal % UBytes;
5523 SDValue InFlag(0, 0);
5524 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5526 InFlag = Chain.getValue(1);
5527 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5529 InFlag = Chain.getValue(1);
5530 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5532 InFlag = Chain.getValue(1);
5534 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5535 SmallVector<SDValue, 8> Ops;
5536 Ops.push_back(Chain);
5537 Ops.push_back(DAG.getValueType(AVT));
5538 Ops.push_back(InFlag);
5539 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5541 SmallVector<SDValue, 4> Results;
5542 Results.push_back(RepMovs);
5544 // Handle the last 1 - 7 bytes.
5545 unsigned Offset = SizeVal - BytesLeft;
5546 MVT DstVT = Dst.getValueType();
5547 MVT SrcVT = Src.getValueType();
5548 MVT SizeVT = Size.getValueType();
5549 Results.push_back(DAG.getMemcpy(Chain,
5550 DAG.getNode(ISD::ADD, DstVT, Dst,
5551 DAG.getConstant(Offset, DstVT)),
5552 DAG.getNode(ISD::ADD, SrcVT, Src,
5553 DAG.getConstant(Offset, SrcVT)),
5554 DAG.getConstant(BytesLeft, SizeVT),
5555 Align, AlwaysInline,
5556 DstSV, DstSVOff + Offset,
5557 SrcSV, SrcSVOff + Offset));
5560 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5563 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5564 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5566 if (!Subtarget->is64Bit()) {
5567 // vastart just stores the address of the VarArgsFrameIndex slot into the
5568 // memory location argument.
5569 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5570 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5574 // gp_offset (0 - 6 * 8)
5575 // fp_offset (48 - 48 + 8 * 16)
5576 // overflow_arg_area (point to parameters coming in memory).
5578 SmallVector<SDValue, 8> MemOps;
5579 SDValue FIN = Op.getOperand(1);
5581 SDValue Store = DAG.getStore(Op.getOperand(0),
5582 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5584 MemOps.push_back(Store);
5587 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5588 Store = DAG.getStore(Op.getOperand(0),
5589 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5591 MemOps.push_back(Store);
5593 // Store ptr to overflow_arg_area
5594 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5595 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5596 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5597 MemOps.push_back(Store);
5599 // Store ptr to reg_save_area.
5600 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5601 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5602 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5603 MemOps.push_back(Store);
5604 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5607 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5608 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5609 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5610 SDValue Chain = Op.getOperand(0);
5611 SDValue SrcPtr = Op.getOperand(1);
5612 SDValue SrcSV = Op.getOperand(2);
5614 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5619 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5620 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5621 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5622 SDValue Chain = Op.getOperand(0);
5623 SDValue DstPtr = Op.getOperand(1);
5624 SDValue SrcPtr = Op.getOperand(2);
5625 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5626 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5628 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5629 DAG.getIntPtrConstant(24), 8, false,
5630 DstSV, 0, SrcSV, 0);
5634 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5635 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5637 default: return SDValue(); // Don't custom lower most intrinsics.
5638 // Comparison intrinsics.
5639 case Intrinsic::x86_sse_comieq_ss:
5640 case Intrinsic::x86_sse_comilt_ss:
5641 case Intrinsic::x86_sse_comile_ss:
5642 case Intrinsic::x86_sse_comigt_ss:
5643 case Intrinsic::x86_sse_comige_ss:
5644 case Intrinsic::x86_sse_comineq_ss:
5645 case Intrinsic::x86_sse_ucomieq_ss:
5646 case Intrinsic::x86_sse_ucomilt_ss:
5647 case Intrinsic::x86_sse_ucomile_ss:
5648 case Intrinsic::x86_sse_ucomigt_ss:
5649 case Intrinsic::x86_sse_ucomige_ss:
5650 case Intrinsic::x86_sse_ucomineq_ss:
5651 case Intrinsic::x86_sse2_comieq_sd:
5652 case Intrinsic::x86_sse2_comilt_sd:
5653 case Intrinsic::x86_sse2_comile_sd:
5654 case Intrinsic::x86_sse2_comigt_sd:
5655 case Intrinsic::x86_sse2_comige_sd:
5656 case Intrinsic::x86_sse2_comineq_sd:
5657 case Intrinsic::x86_sse2_ucomieq_sd:
5658 case Intrinsic::x86_sse2_ucomilt_sd:
5659 case Intrinsic::x86_sse2_ucomile_sd:
5660 case Intrinsic::x86_sse2_ucomigt_sd:
5661 case Intrinsic::x86_sse2_ucomige_sd:
5662 case Intrinsic::x86_sse2_ucomineq_sd: {
5664 ISD::CondCode CC = ISD::SETCC_INVALID;
5667 case Intrinsic::x86_sse_comieq_ss:
5668 case Intrinsic::x86_sse2_comieq_sd:
5672 case Intrinsic::x86_sse_comilt_ss:
5673 case Intrinsic::x86_sse2_comilt_sd:
5677 case Intrinsic::x86_sse_comile_ss:
5678 case Intrinsic::x86_sse2_comile_sd:
5682 case Intrinsic::x86_sse_comigt_ss:
5683 case Intrinsic::x86_sse2_comigt_sd:
5687 case Intrinsic::x86_sse_comige_ss:
5688 case Intrinsic::x86_sse2_comige_sd:
5692 case Intrinsic::x86_sse_comineq_ss:
5693 case Intrinsic::x86_sse2_comineq_sd:
5697 case Intrinsic::x86_sse_ucomieq_ss:
5698 case Intrinsic::x86_sse2_ucomieq_sd:
5699 Opc = X86ISD::UCOMI;
5702 case Intrinsic::x86_sse_ucomilt_ss:
5703 case Intrinsic::x86_sse2_ucomilt_sd:
5704 Opc = X86ISD::UCOMI;
5707 case Intrinsic::x86_sse_ucomile_ss:
5708 case Intrinsic::x86_sse2_ucomile_sd:
5709 Opc = X86ISD::UCOMI;
5712 case Intrinsic::x86_sse_ucomigt_ss:
5713 case Intrinsic::x86_sse2_ucomigt_sd:
5714 Opc = X86ISD::UCOMI;
5717 case Intrinsic::x86_sse_ucomige_ss:
5718 case Intrinsic::x86_sse2_ucomige_sd:
5719 Opc = X86ISD::UCOMI;
5722 case Intrinsic::x86_sse_ucomineq_ss:
5723 case Intrinsic::x86_sse2_ucomineq_sd:
5724 Opc = X86ISD::UCOMI;
5730 SDValue LHS = Op.getOperand(1);
5731 SDValue RHS = Op.getOperand(2);
5732 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5734 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5735 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5736 DAG.getConstant(X86CC, MVT::i8), Cond);
5737 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5740 // Fix vector shift instructions where the last operand is a non-immediate
5742 case Intrinsic::x86_sse2_pslli_w:
5743 case Intrinsic::x86_sse2_pslli_d:
5744 case Intrinsic::x86_sse2_pslli_q:
5745 case Intrinsic::x86_sse2_psrli_w:
5746 case Intrinsic::x86_sse2_psrli_d:
5747 case Intrinsic::x86_sse2_psrli_q:
5748 case Intrinsic::x86_sse2_psrai_w:
5749 case Intrinsic::x86_sse2_psrai_d:
5750 case Intrinsic::x86_mmx_pslli_w:
5751 case Intrinsic::x86_mmx_pslli_d:
5752 case Intrinsic::x86_mmx_pslli_q:
5753 case Intrinsic::x86_mmx_psrli_w:
5754 case Intrinsic::x86_mmx_psrli_d:
5755 case Intrinsic::x86_mmx_psrli_q:
5756 case Intrinsic::x86_mmx_psrai_w:
5757 case Intrinsic::x86_mmx_psrai_d: {
5758 SDValue ShAmt = Op.getOperand(2);
5759 if (isa<ConstantSDNode>(ShAmt))
5762 unsigned NewIntNo = 0;
5763 MVT ShAmtVT = MVT::v4i32;
5765 case Intrinsic::x86_sse2_pslli_w:
5766 NewIntNo = Intrinsic::x86_sse2_psll_w;
5768 case Intrinsic::x86_sse2_pslli_d:
5769 NewIntNo = Intrinsic::x86_sse2_psll_d;
5771 case Intrinsic::x86_sse2_pslli_q:
5772 NewIntNo = Intrinsic::x86_sse2_psll_q;
5774 case Intrinsic::x86_sse2_psrli_w:
5775 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5777 case Intrinsic::x86_sse2_psrli_d:
5778 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5780 case Intrinsic::x86_sse2_psrli_q:
5781 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5783 case Intrinsic::x86_sse2_psrai_w:
5784 NewIntNo = Intrinsic::x86_sse2_psra_w;
5786 case Intrinsic::x86_sse2_psrai_d:
5787 NewIntNo = Intrinsic::x86_sse2_psra_d;
5790 ShAmtVT = MVT::v2i32;
5792 case Intrinsic::x86_mmx_pslli_w:
5793 NewIntNo = Intrinsic::x86_mmx_psll_w;
5795 case Intrinsic::x86_mmx_pslli_d:
5796 NewIntNo = Intrinsic::x86_mmx_psll_d;
5798 case Intrinsic::x86_mmx_pslli_q:
5799 NewIntNo = Intrinsic::x86_mmx_psll_q;
5801 case Intrinsic::x86_mmx_psrli_w:
5802 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5804 case Intrinsic::x86_mmx_psrli_d:
5805 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5807 case Intrinsic::x86_mmx_psrli_q:
5808 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5810 case Intrinsic::x86_mmx_psrai_w:
5811 NewIntNo = Intrinsic::x86_mmx_psra_w;
5813 case Intrinsic::x86_mmx_psrai_d:
5814 NewIntNo = Intrinsic::x86_mmx_psra_d;
5816 default: abort(); // Can't reach here.
5821 MVT VT = Op.getValueType();
5822 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5823 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5824 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5825 DAG.getConstant(NewIntNo, MVT::i32),
5826 Op.getOperand(1), ShAmt);
5831 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5832 // Depths > 0 not supported yet!
5833 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5836 // Just load the return address
5837 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5838 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5841 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5842 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5843 MFI->setFrameAddressIsTaken(true);
5844 MVT VT = Op.getValueType();
5845 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5846 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
5847 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
5849 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
5853 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5854 SelectionDAG &DAG) {
5855 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5858 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5860 MachineFunction &MF = DAG.getMachineFunction();
5861 SDValue Chain = Op.getOperand(0);
5862 SDValue Offset = Op.getOperand(1);
5863 SDValue Handler = Op.getOperand(2);
5865 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5867 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5869 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5870 DAG.getIntPtrConstant(-TD->getPointerSize()));
5871 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5872 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5873 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5874 MF.getRegInfo().addLiveOut(StoreAddrReg);
5876 return DAG.getNode(X86ISD::EH_RETURN,
5878 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5881 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5882 SelectionDAG &DAG) {
5883 SDValue Root = Op.getOperand(0);
5884 SDValue Trmp = Op.getOperand(1); // trampoline
5885 SDValue FPtr = Op.getOperand(2); // nested function
5886 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5888 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5890 const X86InstrInfo *TII =
5891 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5893 if (Subtarget->is64Bit()) {
5894 SDValue OutChains[6];
5896 // Large code-model.
5898 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5899 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5901 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5902 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5904 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5906 // Load the pointer to the nested function into R11.
5907 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5908 SDValue Addr = Trmp;
5909 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5912 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5913 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5915 // Load the 'nest' parameter value into R10.
5916 // R10 is specified in X86CallingConv.td
5917 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5918 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5919 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5922 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5923 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5925 // Jump to the nested function.
5926 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5927 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5928 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5931 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5932 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5933 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5937 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5938 return DAG.getMergeValues(Ops, 2);
5940 const Function *Func =
5941 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5942 unsigned CC = Func->getCallingConv();
5947 assert(0 && "Unsupported calling convention");
5948 case CallingConv::C:
5949 case CallingConv::X86_StdCall: {
5950 // Pass 'nest' parameter in ECX.
5951 // Must be kept in sync with X86CallingConv.td
5954 // Check that ECX wasn't needed by an 'inreg' parameter.
5955 const FunctionType *FTy = Func->getFunctionType();
5956 const AttrListPtr &Attrs = Func->getAttributes();
5958 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5959 unsigned InRegCount = 0;
5962 for (FunctionType::param_iterator I = FTy->param_begin(),
5963 E = FTy->param_end(); I != E; ++I, ++Idx)
5964 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
5965 // FIXME: should only count parameters that are lowered to integers.
5966 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5968 if (InRegCount > 2) {
5969 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5975 case CallingConv::X86_FastCall:
5976 case CallingConv::Fast:
5977 // Pass 'nest' parameter in EAX.
5978 // Must be kept in sync with X86CallingConv.td
5983 SDValue OutChains[4];
5986 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5987 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5989 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5990 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5991 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5994 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5995 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5997 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5998 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5999 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
6000 TrmpAddr, 5, false, 1);
6002 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
6003 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
6006 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
6007 return DAG.getMergeValues(Ops, 2);
6011 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6013 The rounding mode is in bits 11:10 of FPSR, and has the following
6020 FLT_ROUNDS, on the other hand, expects the following:
6027 To perform the conversion, we do:
6028 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6031 MachineFunction &MF = DAG.getMachineFunction();
6032 const TargetMachine &TM = MF.getTarget();
6033 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6034 unsigned StackAlignment = TFI.getStackAlignment();
6035 MVT VT = Op.getValueType();
6037 // Save FP Control Word to stack slot
6038 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6039 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6041 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
6042 DAG.getEntryNode(), StackSlot);
6044 // Load FP Control Word from stack slot
6045 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
6047 // Transform as necessary
6049 DAG.getNode(ISD::SRL, MVT::i16,
6050 DAG.getNode(ISD::AND, MVT::i16,
6051 CWD, DAG.getConstant(0x800, MVT::i16)),
6052 DAG.getConstant(11, MVT::i8));
6054 DAG.getNode(ISD::SRL, MVT::i16,
6055 DAG.getNode(ISD::AND, MVT::i16,
6056 CWD, DAG.getConstant(0x400, MVT::i16)),
6057 DAG.getConstant(9, MVT::i8));
6060 DAG.getNode(ISD::AND, MVT::i16,
6061 DAG.getNode(ISD::ADD, MVT::i16,
6062 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
6063 DAG.getConstant(1, MVT::i16)),
6064 DAG.getConstant(3, MVT::i16));
6067 return DAG.getNode((VT.getSizeInBits() < 16 ?
6068 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
6071 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6072 MVT VT = Op.getValueType();
6074 unsigned NumBits = VT.getSizeInBits();
6076 Op = Op.getOperand(0);
6077 if (VT == MVT::i8) {
6078 // Zero extend to i32 since there is not an i8 bsr.
6080 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6083 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6084 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6085 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
6087 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6088 SmallVector<SDValue, 4> Ops;
6090 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6091 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6092 Ops.push_back(Op.getValue(1));
6093 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6095 // Finally xor with NumBits-1.
6096 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6099 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6103 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6104 MVT VT = Op.getValueType();
6106 unsigned NumBits = VT.getSizeInBits();
6108 Op = Op.getOperand(0);
6109 if (VT == MVT::i8) {
6111 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6114 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6115 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6116 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
6118 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6119 SmallVector<SDValue, 4> Ops;
6121 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6122 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6123 Ops.push_back(Op.getValue(1));
6124 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6127 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6131 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6132 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6133 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6134 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6135 // has only one use.
6136 SDNode *N = Op.getNode();
6137 SDValue LHS = N->getOperand(0);
6138 SDValue RHS = N->getOperand(1);
6139 unsigned BaseOp = 0;
6142 switch (Op.getOpcode()) {
6143 default: assert(0 && "Unknown ovf instruction!");
6145 BaseOp = X86ISD::ADD;
6149 BaseOp = X86ISD::ADD;
6153 BaseOp = X86ISD::SUB;
6157 BaseOp = X86ISD::SUB;
6161 BaseOp = X86ISD::MUL;
6165 BaseOp = X86ISD::MUL;
6170 // Also sets EFLAGS.
6171 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6172 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS);
6175 DAG.getNode(X86ISD::SETCC, N->getValueType(1),
6176 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6178 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6182 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6183 MVT T = Op.getValueType();
6186 switch(T.getSimpleVT()) {
6188 assert(false && "Invalid value type!");
6189 case MVT::i8: Reg = X86::AL; size = 1; break;
6190 case MVT::i16: Reg = X86::AX; size = 2; break;
6191 case MVT::i32: Reg = X86::EAX; size = 4; break;
6193 assert(Subtarget->is64Bit() && "Node not type legal!");
6194 Reg = X86::RAX; size = 8;
6197 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
6198 Op.getOperand(2), SDValue());
6199 SDValue Ops[] = { cpIn.getValue(0),
6202 DAG.getTargetConstant(size, MVT::i8),
6204 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6205 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
6207 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6211 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6212 SelectionDAG &DAG) {
6213 assert(Subtarget->is64Bit() && "Result not type legalized?");
6214 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6215 SDValue TheChain = Op.getOperand(0);
6216 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6217 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
6218 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
6220 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
6221 DAG.getConstant(32, MVT::i8));
6223 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp),
6226 return DAG.getMergeValues(Ops, 2);
6229 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6230 SDNode *Node = Op.getNode();
6231 MVT T = Node->getValueType(0);
6232 SDValue negOp = DAG.getNode(ISD::SUB, T,
6233 DAG.getConstant(0, T), Node->getOperand(2));
6234 return DAG.getAtomic((Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_8 ?
6235 ISD::ATOMIC_LOAD_ADD_8 :
6236 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_16 ?
6237 ISD::ATOMIC_LOAD_ADD_16 :
6238 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_32 ?
6239 ISD::ATOMIC_LOAD_ADD_32 :
6240 ISD::ATOMIC_LOAD_ADD_64),
6241 Node->getOperand(0),
6242 Node->getOperand(1), negOp,
6243 cast<AtomicSDNode>(Node)->getSrcValue(),
6244 cast<AtomicSDNode>(Node)->getAlignment());
6247 /// LowerOperation - Provide custom lowering hooks for some operations.
6249 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6250 switch (Op.getOpcode()) {
6251 default: assert(0 && "Should not custom lower this!");
6252 case ISD::ATOMIC_CMP_SWAP_8:
6253 case ISD::ATOMIC_CMP_SWAP_16:
6254 case ISD::ATOMIC_CMP_SWAP_32:
6255 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
6256 case ISD::ATOMIC_LOAD_SUB_8:
6257 case ISD::ATOMIC_LOAD_SUB_16:
6258 case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
6259 case ISD::ATOMIC_LOAD_SUB_64: return LowerLOAD_SUB(Op,DAG);
6260 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6261 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6262 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6263 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6264 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6265 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6266 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6267 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6268 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6269 case ISD::SHL_PARTS:
6270 case ISD::SRA_PARTS:
6271 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6272 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6273 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6274 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6275 case ISD::FABS: return LowerFABS(Op, DAG);
6276 case ISD::FNEG: return LowerFNEG(Op, DAG);
6277 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6278 case ISD::SETCC: return LowerSETCC(Op, DAG);
6279 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6280 case ISD::SELECT: return LowerSELECT(Op, DAG);
6281 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6282 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6283 case ISD::CALL: return LowerCALL(Op, DAG);
6284 case ISD::RET: return LowerRET(Op, DAG);
6285 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6286 case ISD::VASTART: return LowerVASTART(Op, DAG);
6287 case ISD::VAARG: return LowerVAARG(Op, DAG);
6288 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6289 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6290 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6291 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6292 case ISD::FRAME_TO_ARGS_OFFSET:
6293 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6294 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6295 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6296 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6297 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6298 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6299 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6305 case ISD::UMULO: return LowerXALUO(Op, DAG);
6306 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6310 void X86TargetLowering::
6311 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6312 SelectionDAG &DAG, unsigned NewOp) {
6313 MVT T = Node->getValueType(0);
6314 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6316 SDValue Chain = Node->getOperand(0);
6317 SDValue In1 = Node->getOperand(1);
6318 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6319 Node->getOperand(2), DAG.getIntPtrConstant(0));
6320 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6321 Node->getOperand(2), DAG.getIntPtrConstant(1));
6322 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6323 // have a MemOperand. Pass the info through as a normal operand.
6324 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6325 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6326 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6327 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6328 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6329 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6330 Results.push_back(Result.getValue(2));
6333 /// ReplaceNodeResults - Replace a node with an illegal result type
6334 /// with a new node built out of custom code.
6335 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6336 SmallVectorImpl<SDValue>&Results,
6337 SelectionDAG &DAG) {
6338 switch (N->getOpcode()) {
6340 assert(false && "Do not know how to custom type legalize this operation!");
6342 case ISD::FP_TO_SINT: {
6343 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6344 SDValue FIST = Vals.first, StackSlot = Vals.second;
6345 if (FIST.getNode() != 0) {
6346 MVT VT = N->getValueType(0);
6347 // Return a load from the stack slot.
6348 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0));
6352 case ISD::READCYCLECOUNTER: {
6353 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6354 SDValue TheChain = N->getOperand(0);
6355 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6356 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
6357 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
6359 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6360 SDValue Ops[] = { eax, edx };
6361 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2));
6362 Results.push_back(edx.getValue(1));
6365 case ISD::ATOMIC_CMP_SWAP_64: {
6366 MVT T = N->getValueType(0);
6367 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6368 SDValue cpInL, cpInH;
6369 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6370 DAG.getConstant(0, MVT::i32));
6371 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6372 DAG.getConstant(1, MVT::i32));
6373 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
6374 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
6376 SDValue swapInL, swapInH;
6377 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6378 DAG.getConstant(0, MVT::i32));
6379 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6380 DAG.getConstant(1, MVT::i32));
6381 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
6383 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
6384 swapInL.getValue(1));
6385 SDValue Ops[] = { swapInH.getValue(0),
6387 swapInH.getValue(1) };
6388 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6389 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6390 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6391 Result.getValue(1));
6392 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6393 cpOutL.getValue(2));
6394 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6395 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6396 Results.push_back(cpOutH.getValue(1));
6399 case ISD::ATOMIC_LOAD_ADD_64:
6400 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6402 case ISD::ATOMIC_LOAD_AND_64:
6403 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6405 case ISD::ATOMIC_LOAD_NAND_64:
6406 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6408 case ISD::ATOMIC_LOAD_OR_64:
6409 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6411 case ISD::ATOMIC_LOAD_SUB_64:
6412 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6414 case ISD::ATOMIC_LOAD_XOR_64:
6415 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6417 case ISD::ATOMIC_SWAP_64:
6418 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6423 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6425 default: return NULL;
6426 case X86ISD::BSF: return "X86ISD::BSF";
6427 case X86ISD::BSR: return "X86ISD::BSR";
6428 case X86ISD::SHLD: return "X86ISD::SHLD";
6429 case X86ISD::SHRD: return "X86ISD::SHRD";
6430 case X86ISD::FAND: return "X86ISD::FAND";
6431 case X86ISD::FOR: return "X86ISD::FOR";
6432 case X86ISD::FXOR: return "X86ISD::FXOR";
6433 case X86ISD::FSRL: return "X86ISD::FSRL";
6434 case X86ISD::FILD: return "X86ISD::FILD";
6435 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6436 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6437 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6438 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6439 case X86ISD::FLD: return "X86ISD::FLD";
6440 case X86ISD::FST: return "X86ISD::FST";
6441 case X86ISD::CALL: return "X86ISD::CALL";
6442 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6443 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6444 case X86ISD::CMP: return "X86ISD::CMP";
6445 case X86ISD::COMI: return "X86ISD::COMI";
6446 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6447 case X86ISD::SETCC: return "X86ISD::SETCC";
6448 case X86ISD::CMOV: return "X86ISD::CMOV";
6449 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6450 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6451 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6452 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6453 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6454 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6455 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6456 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6457 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6458 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6459 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6460 case X86ISD::FMAX: return "X86ISD::FMAX";
6461 case X86ISD::FMIN: return "X86ISD::FMIN";
6462 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6463 case X86ISD::FRCP: return "X86ISD::FRCP";
6464 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6465 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6466 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6467 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6468 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6469 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6470 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6471 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6472 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6473 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6474 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6475 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6476 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6477 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6478 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6479 case X86ISD::VSHL: return "X86ISD::VSHL";
6480 case X86ISD::VSRL: return "X86ISD::VSRL";
6481 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6482 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6483 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6484 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6485 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6486 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6487 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6488 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6489 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6490 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6491 case X86ISD::ADD: return "X86ISD::ADD";
6492 case X86ISD::SUB: return "X86ISD::SUB";
6493 case X86ISD::MUL: return "X86ISD::MUL";
6497 // isLegalAddressingMode - Return true if the addressing mode represented
6498 // by AM is legal for this target, for a load/store of the specified type.
6499 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6500 const Type *Ty) const {
6501 // X86 supports extremely general addressing modes.
6503 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6504 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6508 // We can only fold this if we don't need an extra load.
6509 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6511 // If BaseGV requires a register, we cannot also have a BaseReg.
6512 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
6516 // X86-64 only supports addr of globals in small code model.
6517 if (Subtarget->is64Bit()) {
6518 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6520 // If lower 4G is not available, then we must use rip-relative addressing.
6521 if (AM.BaseOffs || AM.Scale > 1)
6532 // These scales always work.
6537 // These scales are formed with basereg+scalereg. Only accept if there is
6542 default: // Other stuff never works.
6550 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6551 if (!Ty1->isInteger() || !Ty2->isInteger())
6553 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6554 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6555 if (NumBits1 <= NumBits2)
6557 return Subtarget->is64Bit() || NumBits1 < 64;
6560 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6561 if (!VT1.isInteger() || !VT2.isInteger())
6563 unsigned NumBits1 = VT1.getSizeInBits();
6564 unsigned NumBits2 = VT2.getSizeInBits();
6565 if (NumBits1 <= NumBits2)
6567 return Subtarget->is64Bit() || NumBits1 < 64;
6570 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6571 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6572 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6573 /// are assumed to be legal.
6575 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6576 // Only do shuffles on 128-bit vector types for now.
6577 if (VT.getSizeInBits() == 64) return false;
6578 return (Mask.getNode()->getNumOperands() <= 4 ||
6579 isIdentityMask(Mask.getNode()) ||
6580 isIdentityMask(Mask.getNode(), true) ||
6581 isSplatMask(Mask.getNode()) ||
6582 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6583 X86::isUNPCKLMask(Mask.getNode()) ||
6584 X86::isUNPCKHMask(Mask.getNode()) ||
6585 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6586 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6590 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6591 MVT EVT, SelectionDAG &DAG) const {
6592 unsigned NumElts = BVOps.size();
6593 // Only do shuffles on 128-bit vector types for now.
6594 if (EVT.getSizeInBits() * NumElts == 64) return false;
6595 if (NumElts == 2) return true;
6597 return (isMOVLMask(&BVOps[0], 4) ||
6598 isCommutedMOVL(&BVOps[0], 4, true) ||
6599 isSHUFPMask(&BVOps[0], 4) ||
6600 isCommutedSHUFP(&BVOps[0], 4));
6605 //===----------------------------------------------------------------------===//
6606 // X86 Scheduler Hooks
6607 //===----------------------------------------------------------------------===//
6609 // private utility function
6611 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6612 MachineBasicBlock *MBB,
6620 TargetRegisterClass *RC,
6622 // For the atomic bitwise operator, we generate
6625 // ld t1 = [bitinstr.addr]
6626 // op t2 = t1, [bitinstr.val]
6628 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6630 // fallthrough -->nextMBB
6631 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6632 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6633 MachineFunction::iterator MBBIter = MBB;
6636 /// First build the CFG
6637 MachineFunction *F = MBB->getParent();
6638 MachineBasicBlock *thisMBB = MBB;
6639 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6640 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6641 F->insert(MBBIter, newMBB);
6642 F->insert(MBBIter, nextMBB);
6644 // Move all successors to thisMBB to nextMBB
6645 nextMBB->transferSuccessors(thisMBB);
6647 // Update thisMBB to fall through to newMBB
6648 thisMBB->addSuccessor(newMBB);
6650 // newMBB jumps to itself and fall through to nextMBB
6651 newMBB->addSuccessor(nextMBB);
6652 newMBB->addSuccessor(newMBB);
6654 // Insert instructions into newMBB based on incoming instruction
6655 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6656 MachineOperand& destOper = bInstr->getOperand(0);
6657 MachineOperand* argOpers[6];
6658 int numArgs = bInstr->getNumOperands() - 1;
6659 for (int i=0; i < numArgs; ++i)
6660 argOpers[i] = &bInstr->getOperand(i+1);
6662 // x86 address has 4 operands: base, index, scale, and displacement
6663 int lastAddrIndx = 3; // [0,3]
6666 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6667 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6668 for (int i=0; i <= lastAddrIndx; ++i)
6669 (*MIB).addOperand(*argOpers[i]);
6671 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6673 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6678 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6679 assert((argOpers[valArgIndx]->isReg() ||
6680 argOpers[valArgIndx]->isImm()) &&
6682 if (argOpers[valArgIndx]->isReg())
6683 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6685 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6687 (*MIB).addOperand(*argOpers[valArgIndx]);
6689 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6692 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6693 for (int i=0; i <= lastAddrIndx; ++i)
6694 (*MIB).addOperand(*argOpers[i]);
6696 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6697 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6699 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6703 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6705 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6709 // private utility function: 64 bit atomics on 32 bit host.
6711 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6712 MachineBasicBlock *MBB,
6718 // For the atomic bitwise operator, we generate
6719 // thisMBB (instructions are in pairs, except cmpxchg8b)
6720 // ld t1,t2 = [bitinstr.addr]
6722 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6723 // op t5, t6 <- out1, out2, [bitinstr.val]
6724 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6725 // mov ECX, EBX <- t5, t6
6726 // mov EAX, EDX <- t1, t2
6727 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6728 // mov t3, t4 <- EAX, EDX
6730 // result in out1, out2
6731 // fallthrough -->nextMBB
6733 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6734 const unsigned LoadOpc = X86::MOV32rm;
6735 const unsigned copyOpc = X86::MOV32rr;
6736 const unsigned NotOpc = X86::NOT32r;
6737 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6738 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6739 MachineFunction::iterator MBBIter = MBB;
6742 /// First build the CFG
6743 MachineFunction *F = MBB->getParent();
6744 MachineBasicBlock *thisMBB = MBB;
6745 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6746 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6747 F->insert(MBBIter, newMBB);
6748 F->insert(MBBIter, nextMBB);
6750 // Move all successors to thisMBB to nextMBB
6751 nextMBB->transferSuccessors(thisMBB);
6753 // Update thisMBB to fall through to newMBB
6754 thisMBB->addSuccessor(newMBB);
6756 // newMBB jumps to itself and fall through to nextMBB
6757 newMBB->addSuccessor(nextMBB);
6758 newMBB->addSuccessor(newMBB);
6760 // Insert instructions into newMBB based on incoming instruction
6761 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6762 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6763 MachineOperand& dest1Oper = bInstr->getOperand(0);
6764 MachineOperand& dest2Oper = bInstr->getOperand(1);
6765 MachineOperand* argOpers[6];
6766 for (int i=0; i < 6; ++i)
6767 argOpers[i] = &bInstr->getOperand(i+2);
6769 // x86 address has 4 operands: base, index, scale, and displacement
6770 int lastAddrIndx = 3; // [0,3]
6772 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6773 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6774 for (int i=0; i <= lastAddrIndx; ++i)
6775 (*MIB).addOperand(*argOpers[i]);
6776 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6777 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6778 // add 4 to displacement.
6779 for (int i=0; i <= lastAddrIndx-1; ++i)
6780 (*MIB).addOperand(*argOpers[i]);
6781 MachineOperand newOp3 = *(argOpers[3]);
6783 newOp3.setImm(newOp3.getImm()+4);
6785 newOp3.setOffset(newOp3.getOffset()+4);
6786 (*MIB).addOperand(newOp3);
6788 // t3/4 are defined later, at the bottom of the loop
6789 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6790 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6791 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6792 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6793 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6794 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6796 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6797 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6799 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6800 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6806 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
6808 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6809 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6810 if (argOpers[4]->isReg())
6811 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6813 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6814 if (regOpcL != X86::MOV32rr)
6816 (*MIB).addOperand(*argOpers[4]);
6817 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6818 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6819 if (argOpers[5]->isReg())
6820 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6822 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6823 if (regOpcH != X86::MOV32rr)
6825 (*MIB).addOperand(*argOpers[5]);
6827 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
6829 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
6832 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
6834 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
6837 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
6838 for (int i=0; i <= lastAddrIndx; ++i)
6839 (*MIB).addOperand(*argOpers[i]);
6841 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6842 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6844 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
6845 MIB.addReg(X86::EAX);
6846 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
6847 MIB.addReg(X86::EDX);
6850 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6852 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6856 // private utility function
6858 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6859 MachineBasicBlock *MBB,
6861 // For the atomic min/max operator, we generate
6864 // ld t1 = [min/max.addr]
6865 // mov t2 = [min/max.val]
6867 // cmov[cond] t2 = t1
6869 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6871 // fallthrough -->nextMBB
6873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6874 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6875 MachineFunction::iterator MBBIter = MBB;
6878 /// First build the CFG
6879 MachineFunction *F = MBB->getParent();
6880 MachineBasicBlock *thisMBB = MBB;
6881 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6882 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6883 F->insert(MBBIter, newMBB);
6884 F->insert(MBBIter, nextMBB);
6886 // Move all successors to thisMBB to nextMBB
6887 nextMBB->transferSuccessors(thisMBB);
6889 // Update thisMBB to fall through to newMBB
6890 thisMBB->addSuccessor(newMBB);
6892 // newMBB jumps to newMBB and fall through to nextMBB
6893 newMBB->addSuccessor(nextMBB);
6894 newMBB->addSuccessor(newMBB);
6896 // Insert instructions into newMBB based on incoming instruction
6897 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6898 MachineOperand& destOper = mInstr->getOperand(0);
6899 MachineOperand* argOpers[6];
6900 int numArgs = mInstr->getNumOperands() - 1;
6901 for (int i=0; i < numArgs; ++i)
6902 argOpers[i] = &mInstr->getOperand(i+1);
6904 // x86 address has 4 operands: base, index, scale, and displacement
6905 int lastAddrIndx = 3; // [0,3]
6908 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6909 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6910 for (int i=0; i <= lastAddrIndx; ++i)
6911 (*MIB).addOperand(*argOpers[i]);
6913 // We only support register and immediate values
6914 assert((argOpers[valArgIndx]->isReg() ||
6915 argOpers[valArgIndx]->isImm()) &&
6918 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6919 if (argOpers[valArgIndx]->isReg())
6920 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6922 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6923 (*MIB).addOperand(*argOpers[valArgIndx]);
6925 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6928 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6933 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6934 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6938 // Cmp and exchange if none has modified the memory location
6939 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6940 for (int i=0; i <= lastAddrIndx; ++i)
6941 (*MIB).addOperand(*argOpers[i]);
6943 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6944 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6946 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6947 MIB.addReg(X86::EAX);
6950 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6952 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6958 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6959 MachineBasicBlock *BB) {
6960 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6961 switch (MI->getOpcode()) {
6962 default: assert(false && "Unexpected instr type to insert");
6963 case X86::CMOV_FR32:
6964 case X86::CMOV_FR64:
6965 case X86::CMOV_V4F32:
6966 case X86::CMOV_V2F64:
6967 case X86::CMOV_V2I64: {
6968 // To "insert" a SELECT_CC instruction, we actually have to insert the
6969 // diamond control-flow pattern. The incoming instruction knows the
6970 // destination vreg to set, the condition code register to branch on, the
6971 // true/false values to select between, and a branch opcode to use.
6972 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6973 MachineFunction::iterator It = BB;
6979 // cmpTY ccX, r1, r2
6981 // fallthrough --> copy0MBB
6982 MachineBasicBlock *thisMBB = BB;
6983 MachineFunction *F = BB->getParent();
6984 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6985 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6987 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6988 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6989 F->insert(It, copy0MBB);
6990 F->insert(It, sinkMBB);
6991 // Update machine-CFG edges by transferring all successors of the current
6992 // block to the new block which will contain the Phi node for the select.
6993 sinkMBB->transferSuccessors(BB);
6995 // Add the true and fallthrough blocks as its successors.
6996 BB->addSuccessor(copy0MBB);
6997 BB->addSuccessor(sinkMBB);
7000 // %FalseValue = ...
7001 // # fallthrough to sinkMBB
7004 // Update machine-CFG edges
7005 BB->addSuccessor(sinkMBB);
7008 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7011 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
7012 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7013 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7015 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7019 case X86::FP32_TO_INT16_IN_MEM:
7020 case X86::FP32_TO_INT32_IN_MEM:
7021 case X86::FP32_TO_INT64_IN_MEM:
7022 case X86::FP64_TO_INT16_IN_MEM:
7023 case X86::FP64_TO_INT32_IN_MEM:
7024 case X86::FP64_TO_INT64_IN_MEM:
7025 case X86::FP80_TO_INT16_IN_MEM:
7026 case X86::FP80_TO_INT32_IN_MEM:
7027 case X86::FP80_TO_INT64_IN_MEM: {
7028 // Change the floating point control register to use "round towards zero"
7029 // mode when truncating to an integer value.
7030 MachineFunction *F = BB->getParent();
7031 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7032 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7034 // Load the old value of the high byte of the control word...
7036 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7037 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
7039 // Set the high part to be round to zero...
7040 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
7043 // Reload the modified control word now...
7044 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7046 // Restore the memory image of control word to original value
7047 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
7050 // Get the X86 opcode to use.
7052 switch (MI->getOpcode()) {
7053 default: assert(0 && "illegal opcode!");
7054 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7055 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7056 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7057 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7058 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7059 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7060 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7061 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7062 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7066 MachineOperand &Op = MI->getOperand(0);
7068 AM.BaseType = X86AddressMode::RegBase;
7069 AM.Base.Reg = Op.getReg();
7071 AM.BaseType = X86AddressMode::FrameIndexBase;
7072 AM.Base.FrameIndex = Op.getIndex();
7074 Op = MI->getOperand(1);
7076 AM.Scale = Op.getImm();
7077 Op = MI->getOperand(2);
7079 AM.IndexReg = Op.getImm();
7080 Op = MI->getOperand(3);
7081 if (Op.isGlobal()) {
7082 AM.GV = Op.getGlobal();
7084 AM.Disp = Op.getImm();
7086 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
7087 .addReg(MI->getOperand(4).getReg());
7089 // Reload the original control word now.
7090 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7092 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7095 case X86::ATOMAND32:
7096 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7097 X86::AND32ri, X86::MOV32rm,
7098 X86::LCMPXCHG32, X86::MOV32rr,
7099 X86::NOT32r, X86::EAX,
7100 X86::GR32RegisterClass);
7102 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7103 X86::OR32ri, X86::MOV32rm,
7104 X86::LCMPXCHG32, X86::MOV32rr,
7105 X86::NOT32r, X86::EAX,
7106 X86::GR32RegisterClass);
7107 case X86::ATOMXOR32:
7108 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7109 X86::XOR32ri, X86::MOV32rm,
7110 X86::LCMPXCHG32, X86::MOV32rr,
7111 X86::NOT32r, X86::EAX,
7112 X86::GR32RegisterClass);
7113 case X86::ATOMNAND32:
7114 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7115 X86::AND32ri, X86::MOV32rm,
7116 X86::LCMPXCHG32, X86::MOV32rr,
7117 X86::NOT32r, X86::EAX,
7118 X86::GR32RegisterClass, true);
7119 case X86::ATOMMIN32:
7120 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7121 case X86::ATOMMAX32:
7122 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7123 case X86::ATOMUMIN32:
7124 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7125 case X86::ATOMUMAX32:
7126 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7128 case X86::ATOMAND16:
7129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7130 X86::AND16ri, X86::MOV16rm,
7131 X86::LCMPXCHG16, X86::MOV16rr,
7132 X86::NOT16r, X86::AX,
7133 X86::GR16RegisterClass);
7135 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7136 X86::OR16ri, X86::MOV16rm,
7137 X86::LCMPXCHG16, X86::MOV16rr,
7138 X86::NOT16r, X86::AX,
7139 X86::GR16RegisterClass);
7140 case X86::ATOMXOR16:
7141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7142 X86::XOR16ri, X86::MOV16rm,
7143 X86::LCMPXCHG16, X86::MOV16rr,
7144 X86::NOT16r, X86::AX,
7145 X86::GR16RegisterClass);
7146 case X86::ATOMNAND16:
7147 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7148 X86::AND16ri, X86::MOV16rm,
7149 X86::LCMPXCHG16, X86::MOV16rr,
7150 X86::NOT16r, X86::AX,
7151 X86::GR16RegisterClass, true);
7152 case X86::ATOMMIN16:
7153 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7154 case X86::ATOMMAX16:
7155 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7156 case X86::ATOMUMIN16:
7157 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7158 case X86::ATOMUMAX16:
7159 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7162 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7163 X86::AND8ri, X86::MOV8rm,
7164 X86::LCMPXCHG8, X86::MOV8rr,
7165 X86::NOT8r, X86::AL,
7166 X86::GR8RegisterClass);
7168 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7169 X86::OR8ri, X86::MOV8rm,
7170 X86::LCMPXCHG8, X86::MOV8rr,
7171 X86::NOT8r, X86::AL,
7172 X86::GR8RegisterClass);
7174 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7175 X86::XOR8ri, X86::MOV8rm,
7176 X86::LCMPXCHG8, X86::MOV8rr,
7177 X86::NOT8r, X86::AL,
7178 X86::GR8RegisterClass);
7179 case X86::ATOMNAND8:
7180 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7181 X86::AND8ri, X86::MOV8rm,
7182 X86::LCMPXCHG8, X86::MOV8rr,
7183 X86::NOT8r, X86::AL,
7184 X86::GR8RegisterClass, true);
7185 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7186 // This group is for 64-bit host.
7187 case X86::ATOMAND64:
7188 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7189 X86::AND64ri32, X86::MOV64rm,
7190 X86::LCMPXCHG64, X86::MOV64rr,
7191 X86::NOT64r, X86::RAX,
7192 X86::GR64RegisterClass);
7194 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7195 X86::OR64ri32, X86::MOV64rm,
7196 X86::LCMPXCHG64, X86::MOV64rr,
7197 X86::NOT64r, X86::RAX,
7198 X86::GR64RegisterClass);
7199 case X86::ATOMXOR64:
7200 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7201 X86::XOR64ri32, X86::MOV64rm,
7202 X86::LCMPXCHG64, X86::MOV64rr,
7203 X86::NOT64r, X86::RAX,
7204 X86::GR64RegisterClass);
7205 case X86::ATOMNAND64:
7206 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7207 X86::AND64ri32, X86::MOV64rm,
7208 X86::LCMPXCHG64, X86::MOV64rr,
7209 X86::NOT64r, X86::RAX,
7210 X86::GR64RegisterClass, true);
7211 case X86::ATOMMIN64:
7212 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7213 case X86::ATOMMAX64:
7214 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7215 case X86::ATOMUMIN64:
7216 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7217 case X86::ATOMUMAX64:
7218 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7220 // This group does 64-bit operations on a 32-bit host.
7221 case X86::ATOMAND6432:
7222 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7223 X86::AND32rr, X86::AND32rr,
7224 X86::AND32ri, X86::AND32ri,
7226 case X86::ATOMOR6432:
7227 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7228 X86::OR32rr, X86::OR32rr,
7229 X86::OR32ri, X86::OR32ri,
7231 case X86::ATOMXOR6432:
7232 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7233 X86::XOR32rr, X86::XOR32rr,
7234 X86::XOR32ri, X86::XOR32ri,
7236 case X86::ATOMNAND6432:
7237 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7238 X86::AND32rr, X86::AND32rr,
7239 X86::AND32ri, X86::AND32ri,
7241 case X86::ATOMADD6432:
7242 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7243 X86::ADD32rr, X86::ADC32rr,
7244 X86::ADD32ri, X86::ADC32ri,
7246 case X86::ATOMSUB6432:
7247 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7248 X86::SUB32rr, X86::SBB32rr,
7249 X86::SUB32ri, X86::SBB32ri,
7251 case X86::ATOMSWAP6432:
7252 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7253 X86::MOV32rr, X86::MOV32rr,
7254 X86::MOV32ri, X86::MOV32ri,
7259 //===----------------------------------------------------------------------===//
7260 // X86 Optimization Hooks
7261 //===----------------------------------------------------------------------===//
7263 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7267 const SelectionDAG &DAG,
7268 unsigned Depth) const {
7269 unsigned Opc = Op.getOpcode();
7270 assert((Opc >= ISD::BUILTIN_OP_END ||
7271 Opc == ISD::INTRINSIC_WO_CHAIN ||
7272 Opc == ISD::INTRINSIC_W_CHAIN ||
7273 Opc == ISD::INTRINSIC_VOID) &&
7274 "Should use MaskedValueIsZero if you don't know whether Op"
7275 " is a target node!");
7277 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7281 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7282 Mask.getBitWidth() - 1);
7287 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7288 /// node is a GlobalAddress + offset.
7289 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7290 GlobalValue* &GA, int64_t &Offset) const{
7291 if (N->getOpcode() == X86ISD::Wrapper) {
7292 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7293 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7294 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7298 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7301 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7302 const TargetLowering &TLI) {
7305 if (TLI.isGAPlusOffset(Base, GV, Offset))
7306 return (GV->getAlignment() >= N && (Offset % N) == 0);
7307 // DAG combine handles the stack object case.
7311 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7312 unsigned NumElems, MVT EVT,
7314 SelectionDAG &DAG, MachineFrameInfo *MFI,
7315 const TargetLowering &TLI) {
7317 for (unsigned i = 0; i < NumElems; ++i) {
7318 SDValue Idx = PermMask.getOperand(i);
7319 if (Idx.getOpcode() == ISD::UNDEF) {
7325 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7326 if (!Elt.getNode() ||
7327 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7330 Base = Elt.getNode();
7331 if (Base->getOpcode() == ISD::UNDEF)
7335 if (Elt.getOpcode() == ISD::UNDEF)
7338 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7339 EVT.getSizeInBits()/8, i, MFI))
7345 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7346 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7347 /// if the load addresses are consecutive, non-overlapping, and in the right
7349 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7350 const TargetLowering &TLI) {
7351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7352 MVT VT = N->getValueType(0);
7353 MVT EVT = VT.getVectorElementType();
7354 SDValue PermMask = N->getOperand(2);
7355 unsigned NumElems = PermMask.getNumOperands();
7356 SDNode *Base = NULL;
7357 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7361 LoadSDNode *LD = cast<LoadSDNode>(Base);
7362 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7363 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7364 LD->getSrcValueOffset(), LD->isVolatile());
7365 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7366 LD->getSrcValueOffset(), LD->isVolatile(),
7367 LD->getAlignment());
7370 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7371 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7372 const X86Subtarget *Subtarget,
7373 const TargetLowering &TLI) {
7374 unsigned NumOps = N->getNumOperands();
7376 // Ignore single operand BUILD_VECTOR.
7380 MVT VT = N->getValueType(0);
7381 MVT EVT = VT.getVectorElementType();
7382 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7383 // We are looking for load i64 and zero extend. We want to transform
7384 // it before legalizer has a chance to expand it. Also look for i64
7385 // BUILD_PAIR bit casted to f64.
7387 // This must be an insertion into a zero vector.
7388 SDValue HighElt = N->getOperand(1);
7389 if (!isZeroNode(HighElt))
7392 // Value must be a load.
7393 SDNode *Base = N->getOperand(0).getNode();
7394 if (!isa<LoadSDNode>(Base)) {
7395 if (Base->getOpcode() != ISD::BIT_CONVERT)
7397 Base = Base->getOperand(0).getNode();
7398 if (!isa<LoadSDNode>(Base))
7402 // Transform it into VZEXT_LOAD addr.
7403 LoadSDNode *LD = cast<LoadSDNode>(Base);
7405 // Load must not be an extload.
7406 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7409 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7410 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7411 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7412 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7416 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7417 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7418 const X86Subtarget *Subtarget) {
7419 SDValue Cond = N->getOperand(0);
7421 // If we have SSE[12] support, try to form min/max nodes.
7422 if (Subtarget->hasSSE2() &&
7423 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7424 if (Cond.getOpcode() == ISD::SETCC) {
7425 // Get the LHS/RHS of the select.
7426 SDValue LHS = N->getOperand(1);
7427 SDValue RHS = N->getOperand(2);
7428 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7430 unsigned Opcode = 0;
7431 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7434 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7437 if (!UnsafeFPMath) break;
7439 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7441 Opcode = X86ISD::FMIN;
7444 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7447 if (!UnsafeFPMath) break;
7449 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7451 Opcode = X86ISD::FMAX;
7454 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7457 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7460 if (!UnsafeFPMath) break;
7462 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7464 Opcode = X86ISD::FMIN;
7467 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7470 if (!UnsafeFPMath) break;
7472 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7474 Opcode = X86ISD::FMAX;
7480 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7488 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7489 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7490 const X86Subtarget *Subtarget) {
7491 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7492 // the FP state in cases where an emms may be missing.
7493 // A preferable solution to the general problem is to figure out the right
7494 // places to insert EMMS. This qualifies as a quick hack.
7495 StoreSDNode *St = cast<StoreSDNode>(N);
7496 if (St->getValue().getValueType().isVector() &&
7497 St->getValue().getValueType().getSizeInBits() == 64 &&
7498 isa<LoadSDNode>(St->getValue()) &&
7499 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7500 St->getChain().hasOneUse() && !St->isVolatile()) {
7501 SDNode* LdVal = St->getValue().getNode();
7503 int TokenFactorIndex = -1;
7504 SmallVector<SDValue, 8> Ops;
7505 SDNode* ChainVal = St->getChain().getNode();
7506 // Must be a store of a load. We currently handle two cases: the load
7507 // is a direct child, and it's under an intervening TokenFactor. It is
7508 // possible to dig deeper under nested TokenFactors.
7509 if (ChainVal == LdVal)
7510 Ld = cast<LoadSDNode>(St->getChain());
7511 else if (St->getValue().hasOneUse() &&
7512 ChainVal->getOpcode() == ISD::TokenFactor) {
7513 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7514 if (ChainVal->getOperand(i).getNode() == LdVal) {
7515 TokenFactorIndex = i;
7516 Ld = cast<LoadSDNode>(St->getValue());
7518 Ops.push_back(ChainVal->getOperand(i));
7522 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7523 if (Subtarget->is64Bit()) {
7524 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7525 Ld->getBasePtr(), Ld->getSrcValue(),
7526 Ld->getSrcValueOffset(), Ld->isVolatile(),
7527 Ld->getAlignment());
7528 SDValue NewChain = NewLd.getValue(1);
7529 if (TokenFactorIndex != -1) {
7530 Ops.push_back(NewChain);
7531 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7534 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7535 St->getSrcValue(), St->getSrcValueOffset(),
7536 St->isVolatile(), St->getAlignment());
7539 // Otherwise, lower to two 32-bit copies.
7540 SDValue LoAddr = Ld->getBasePtr();
7541 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7542 DAG.getConstant(4, MVT::i32));
7544 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7545 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7546 Ld->isVolatile(), Ld->getAlignment());
7547 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7548 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7550 MinAlign(Ld->getAlignment(), 4));
7552 SDValue NewChain = LoLd.getValue(1);
7553 if (TokenFactorIndex != -1) {
7554 Ops.push_back(LoLd);
7555 Ops.push_back(HiLd);
7556 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7560 LoAddr = St->getBasePtr();
7561 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7562 DAG.getConstant(4, MVT::i32));
7564 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7565 St->getSrcValue(), St->getSrcValueOffset(),
7566 St->isVolatile(), St->getAlignment());
7567 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7569 St->getSrcValueOffset() + 4,
7571 MinAlign(St->getAlignment(), 4));
7572 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7578 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7579 /// X86ISD::FXOR nodes.
7580 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7581 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7582 // F[X]OR(0.0, x) -> x
7583 // F[X]OR(x, 0.0) -> x
7584 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7585 if (C->getValueAPF().isPosZero())
7586 return N->getOperand(1);
7587 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7588 if (C->getValueAPF().isPosZero())
7589 return N->getOperand(0);
7593 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7594 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7595 // FAND(0.0, x) -> 0.0
7596 // FAND(x, 0.0) -> 0.0
7597 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7598 if (C->getValueAPF().isPosZero())
7599 return N->getOperand(0);
7600 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7601 if (C->getValueAPF().isPosZero())
7602 return N->getOperand(1);
7607 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7608 DAGCombinerInfo &DCI) const {
7609 SelectionDAG &DAG = DCI.DAG;
7610 switch (N->getOpcode()) {
7612 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7613 case ISD::BUILD_VECTOR:
7614 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7615 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7616 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7618 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7619 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7625 //===----------------------------------------------------------------------===//
7626 // X86 Inline Assembly Support
7627 //===----------------------------------------------------------------------===//
7629 /// getConstraintType - Given a constraint letter, return the type of
7630 /// constraint it is for this target.
7631 X86TargetLowering::ConstraintType
7632 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7633 if (Constraint.size() == 1) {
7634 switch (Constraint[0]) {
7646 return C_RegisterClass;
7651 return TargetLowering::getConstraintType(Constraint);
7654 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7655 /// with another that has more specific requirements based on the type of the
7656 /// corresponding operand.
7657 const char *X86TargetLowering::
7658 LowerXConstraint(MVT ConstraintVT) const {
7659 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7660 // 'f' like normal targets.
7661 if (ConstraintVT.isFloatingPoint()) {
7662 if (Subtarget->hasSSE2())
7664 if (Subtarget->hasSSE1())
7668 return TargetLowering::LowerXConstraint(ConstraintVT);
7671 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7672 /// vector. If it is invalid, don't add anything to Ops.
7673 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7676 std::vector<SDValue>&Ops,
7677 SelectionDAG &DAG) const {
7678 SDValue Result(0, 0);
7680 switch (Constraint) {
7683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7684 if (C->getZExtValue() <= 31) {
7685 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7692 if (C->getZExtValue() <= 63) {
7693 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7699 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7700 if (C->getZExtValue() <= 255) {
7701 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7707 // Literal immediates are always ok.
7708 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7709 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7713 // If we are in non-pic codegen mode, we allow the address of a global (with
7714 // an optional displacement) to be used with 'i'.
7715 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7718 // Match either (GA) or (GA+C)
7720 Offset = GA->getOffset();
7721 } else if (Op.getOpcode() == ISD::ADD) {
7722 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7723 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7725 Offset = GA->getOffset()+C->getZExtValue();
7727 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7728 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7730 Offset = GA->getOffset()+C->getZExtValue();
7738 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
7740 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7746 // Otherwise, not valid for this mode.
7751 if (Result.getNode()) {
7752 Ops.push_back(Result);
7755 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
7759 std::vector<unsigned> X86TargetLowering::
7760 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7762 if (Constraint.size() == 1) {
7763 // FIXME: not handling fp-stack yet!
7764 switch (Constraint[0]) { // GCC X86 Constraint Letters
7765 default: break; // Unknown constraint letter
7766 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7769 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7770 else if (VT == MVT::i16)
7771 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7772 else if (VT == MVT::i8)
7773 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7774 else if (VT == MVT::i64)
7775 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7780 return std::vector<unsigned>();
7783 std::pair<unsigned, const TargetRegisterClass*>
7784 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7786 // First, see if this is a constraint that directly corresponds to an LLVM
7788 if (Constraint.size() == 1) {
7789 // GCC Constraint Letters
7790 switch (Constraint[0]) {
7792 case 'r': // GENERAL_REGS
7793 case 'R': // LEGACY_REGS
7794 case 'l': // INDEX_REGS
7796 return std::make_pair(0U, X86::GR8RegisterClass);
7798 return std::make_pair(0U, X86::GR16RegisterClass);
7799 if (VT == MVT::i32 || !Subtarget->is64Bit())
7800 return std::make_pair(0U, X86::GR32RegisterClass);
7801 return std::make_pair(0U, X86::GR64RegisterClass);
7802 case 'f': // FP Stack registers.
7803 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7804 // value to the correct fpstack register class.
7805 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7806 return std::make_pair(0U, X86::RFP32RegisterClass);
7807 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7808 return std::make_pair(0U, X86::RFP64RegisterClass);
7809 return std::make_pair(0U, X86::RFP80RegisterClass);
7810 case 'y': // MMX_REGS if MMX allowed.
7811 if (!Subtarget->hasMMX()) break;
7812 return std::make_pair(0U, X86::VR64RegisterClass);
7813 case 'Y': // SSE_REGS if SSE2 allowed
7814 if (!Subtarget->hasSSE2()) break;
7816 case 'x': // SSE_REGS if SSE1 allowed
7817 if (!Subtarget->hasSSE1()) break;
7819 switch (VT.getSimpleVT()) {
7821 // Scalar SSE types.
7824 return std::make_pair(0U, X86::FR32RegisterClass);
7827 return std::make_pair(0U, X86::FR64RegisterClass);
7835 return std::make_pair(0U, X86::VR128RegisterClass);
7841 // Use the default implementation in TargetLowering to convert the register
7842 // constraint into a member of a register class.
7843 std::pair<unsigned, const TargetRegisterClass*> Res;
7844 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7846 // Not found as a standard register?
7847 if (Res.second == 0) {
7848 // GCC calls "st(0)" just plain "st".
7849 if (StringsEqualNoCase("{st}", Constraint)) {
7850 Res.first = X86::ST0;
7851 Res.second = X86::RFP80RegisterClass;
7853 // 'A' means EAX + EDX.
7854 if (Constraint == "A") {
7855 Res.first = X86::EAX;
7856 Res.second = X86::GRADRegisterClass;
7861 // Otherwise, check to see if this is a register class of the wrong value
7862 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7863 // turn into {ax},{dx}.
7864 if (Res.second->hasType(VT))
7865 return Res; // Correct type already, nothing to do.
7867 // All of the single-register GCC register classes map their values onto
7868 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7869 // really want an 8-bit or 32-bit register, map to the appropriate register
7870 // class and return the appropriate register.
7871 if (Res.second == X86::GR16RegisterClass) {
7872 if (VT == MVT::i8) {
7873 unsigned DestReg = 0;
7874 switch (Res.first) {
7876 case X86::AX: DestReg = X86::AL; break;
7877 case X86::DX: DestReg = X86::DL; break;
7878 case X86::CX: DestReg = X86::CL; break;
7879 case X86::BX: DestReg = X86::BL; break;
7882 Res.first = DestReg;
7883 Res.second = Res.second = X86::GR8RegisterClass;
7885 } else if (VT == MVT::i32) {
7886 unsigned DestReg = 0;
7887 switch (Res.first) {
7889 case X86::AX: DestReg = X86::EAX; break;
7890 case X86::DX: DestReg = X86::EDX; break;
7891 case X86::CX: DestReg = X86::ECX; break;
7892 case X86::BX: DestReg = X86::EBX; break;
7893 case X86::SI: DestReg = X86::ESI; break;
7894 case X86::DI: DestReg = X86::EDI; break;
7895 case X86::BP: DestReg = X86::EBP; break;
7896 case X86::SP: DestReg = X86::ESP; break;
7899 Res.first = DestReg;
7900 Res.second = Res.second = X86::GR32RegisterClass;
7902 } else if (VT == MVT::i64) {
7903 unsigned DestReg = 0;
7904 switch (Res.first) {
7906 case X86::AX: DestReg = X86::RAX; break;
7907 case X86::DX: DestReg = X86::RDX; break;
7908 case X86::CX: DestReg = X86::RCX; break;
7909 case X86::BX: DestReg = X86::RBX; break;
7910 case X86::SI: DestReg = X86::RSI; break;
7911 case X86::DI: DestReg = X86::RDI; break;
7912 case X86::BP: DestReg = X86::RBP; break;
7913 case X86::SP: DestReg = X86::RSP; break;
7916 Res.first = DestReg;
7917 Res.second = Res.second = X86::GR64RegisterClass;
7920 } else if (Res.second == X86::FR32RegisterClass ||
7921 Res.second == X86::FR64RegisterClass ||
7922 Res.second == X86::VR128RegisterClass) {
7923 // Handle references to XMM physical registers that got mapped into the
7924 // wrong class. This can happen with constraints like {xmm0} where the
7925 // target independent register mapper will just pick the first match it can
7926 // find, ignoring the required type.
7928 Res.second = X86::FR32RegisterClass;
7929 else if (VT == MVT::f64)
7930 Res.second = X86::FR64RegisterClass;
7931 else if (X86::VR128RegisterClass->hasType(VT))
7932 Res.second = X86::VR128RegisterClass;
7938 //===----------------------------------------------------------------------===//
7939 // X86 Widen vector type
7940 //===----------------------------------------------------------------------===//
7942 /// getWidenVectorType: given a vector type, returns the type to widen
7943 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
7944 /// If there is no vector type that we want to widen to, returns MVT::Other
7945 /// When and where to widen is target dependent based on the cost of
7946 /// scalarizing vs using the wider vector type.
7948 MVT X86TargetLowering::getWidenVectorType(MVT VT) {
7949 assert(VT.isVector());
7950 if (isTypeLegal(VT))
7953 // TODO: In computeRegisterProperty, we can compute the list of legal vector
7954 // type based on element type. This would speed up our search (though
7955 // it may not be worth it since the size of the list is relatively
7957 MVT EltVT = VT.getVectorElementType();
7958 unsigned NElts = VT.getVectorNumElements();
7960 // On X86, it make sense to widen any vector wider than 1
7964 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
7965 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
7966 MVT SVT = (MVT::SimpleValueType)nVT;
7968 if (isTypeLegal(SVT) &&
7969 SVT.getVectorElementType() == EltVT &&
7970 SVT.getVectorNumElements() > NElts)