1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
87 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
97 setOperationAction(ISD::FREM , MVT::f64 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
109 setOperationAction(ISD::READIO , MVT::i1 , Expand);
110 setOperationAction(ISD::READIO , MVT::i8 , Expand);
111 setOperationAction(ISD::READIO , MVT::i16 , Expand);
112 setOperationAction(ISD::READIO , MVT::i32 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
118 // These should be promoted to a larger select which is supported.
119 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
120 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
121 // X86 wants to expand cmov itself.
123 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
124 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
125 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
126 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
127 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
128 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
131 // We don't have line number support yet.
132 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
135 // Set up the FP register classes.
136 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
137 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
139 // SSE has no load+extend ops
140 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
141 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
143 // SSE has no i16 to fp conversion, only i32
144 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
145 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
147 // Expand FP_TO_UINT into a select.
148 // FIXME: We would like to use a Custom expander here eventually to do
149 // the optimal thing for SSE vs. the default expansion in the legalizer.
150 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
152 // We don't support sin/cos/sqrt/fmod
153 setOperationAction(ISD::FSIN , MVT::f64, Expand);
154 setOperationAction(ISD::FCOS , MVT::f64, Expand);
155 setOperationAction(ISD::FABS , MVT::f64, Expand);
156 setOperationAction(ISD::FNEG , MVT::f64, Expand);
157 setOperationAction(ISD::FREM , MVT::f64, Expand);
158 setOperationAction(ISD::FSIN , MVT::f32, Expand);
159 setOperationAction(ISD::FCOS , MVT::f32, Expand);
160 setOperationAction(ISD::FABS , MVT::f32, Expand);
161 setOperationAction(ISD::FNEG , MVT::f32, Expand);
162 setOperationAction(ISD::FREM , MVT::f32, Expand);
164 addLegalFPImmediate(+0.0); // xorps / xorpd
166 // Set up the FP register classes.
167 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
170 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
171 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
174 addLegalFPImmediate(+0.0); // FLD0
175 addLegalFPImmediate(+1.0); // FLD1
176 addLegalFPImmediate(-0.0); // FLD0/FCHS
177 addLegalFPImmediate(-1.0); // FLD1/FCHS
179 computeRegisterProperties();
181 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
182 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
183 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
184 allowUnalignedMemoryAccesses = true; // x86 supports it!
187 std::vector<SDOperand>
188 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
189 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
190 return LowerFastCCArguments(F, DAG);
191 return LowerCCCArguments(F, DAG);
194 std::pair<SDOperand, SDOperand>
195 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
196 bool isVarArg, unsigned CallingConv,
198 SDOperand Callee, ArgListTy &Args,
200 assert((!isVarArg || CallingConv == CallingConv::C) &&
201 "Only C takes varargs!");
202 if (CallingConv == CallingConv::Fast && EnableFastCC)
203 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
204 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
207 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
210 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
213 MVT::ValueType OpVT = Op.getValueType();
215 default: assert(0 && "Unknown type to return!");
217 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
220 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
221 DAG.getConstant(1, MVT::i32));
222 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
223 DAG.getConstant(0, MVT::i32));
224 Copy = DAG.getCopyToReg(Chain, X86::EAX, Hi, SDOperand());
225 Copy = DAG.getCopyToReg(Copy, X86::EDX, Lo, Copy.getValue(1));
231 std::vector<MVT::ValueType> Tys;
232 Tys.push_back(MVT::Other);
233 Tys.push_back(MVT::Flag);
234 std::vector<SDOperand> Ops;
235 Ops.push_back(Chain);
236 if (OpVT == MVT::f32)
237 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
239 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
241 // Spill the value to memory and reload it into top of stack.
242 unsigned Size = MVT::getSizeInBits(OpVT)/8;
243 MachineFunction &MF = DAG.getMachineFunction();
244 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
245 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
246 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
247 StackSlot, DAG.getSrcValue(NULL));
248 std::vector<MVT::ValueType> Tys;
249 Tys.push_back(MVT::f64);
250 Tys.push_back(MVT::Other);
251 std::vector<SDOperand> Ops;
252 Ops.push_back(Chain);
253 Ops.push_back(StackSlot);
254 Ops.push_back(DAG.getValueType(OpVT));
255 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
257 Tys.push_back(MVT::Other);
258 Tys.push_back(MVT::Flag);
260 Ops.push_back(Copy.getValue(1));
262 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
267 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
268 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
272 //===----------------------------------------------------------------------===//
273 // C Calling Convention implementation
274 //===----------------------------------------------------------------------===//
276 std::vector<SDOperand>
277 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
278 std::vector<SDOperand> ArgValues;
280 MachineFunction &MF = DAG.getMachineFunction();
281 MachineFrameInfo *MFI = MF.getFrameInfo();
283 // Add DAG nodes to load the arguments... On entry to a function on the X86,
284 // the stack frame looks like this:
286 // [ESP] -- return address
287 // [ESP + 4] -- first argument (leftmost lexically)
288 // [ESP + 8] -- second argument, if first argument is four bytes in size
291 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
292 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
293 MVT::ValueType ObjectVT = getValueType(I->getType());
294 unsigned ArgIncrement = 4;
297 default: assert(0 && "Unhandled argument type!");
299 case MVT::i8: ObjSize = 1; break;
300 case MVT::i16: ObjSize = 2; break;
301 case MVT::i32: ObjSize = 4; break;
302 case MVT::i64: ObjSize = ArgIncrement = 8; break;
303 case MVT::f32: ObjSize = 4; break;
304 case MVT::f64: ObjSize = ArgIncrement = 8; break;
306 // Create the frame index object for this incoming parameter...
307 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
309 // Create the SelectionDAG nodes corresponding to a load from this parameter
310 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
312 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
316 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
317 DAG.getSrcValue(NULL));
319 if (MVT::isInteger(ObjectVT))
320 ArgValue = DAG.getConstant(0, ObjectVT);
322 ArgValue = DAG.getConstantFP(0, ObjectVT);
324 ArgValues.push_back(ArgValue);
326 ArgOffset += ArgIncrement; // Move on to the next argument...
329 // If the function takes variable number of arguments, make a frame index for
330 // the start of the first vararg value... for expansion of llvm.va_start.
332 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
333 ReturnAddrIndex = 0; // No return address slot generated yet.
334 BytesToPopOnReturn = 0; // Callee pops nothing.
335 BytesCallerReserves = ArgOffset;
337 // Finally, inform the code generator which regs we return values in.
338 switch (getValueType(F.getReturnType())) {
339 default: assert(0 && "Unknown type!");
340 case MVT::isVoid: break;
345 MF.addLiveOut(X86::EAX);
348 MF.addLiveOut(X86::EAX);
349 MF.addLiveOut(X86::EDX);
353 MF.addLiveOut(X86::ST0);
359 std::pair<SDOperand, SDOperand>
360 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
361 bool isVarArg, bool isTailCall,
362 SDOperand Callee, ArgListTy &Args,
364 // Count how many bytes are to be pushed on the stack.
365 unsigned NumBytes = 0;
369 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
370 DAG.getConstant(0, getPointerTy()));
372 for (unsigned i = 0, e = Args.size(); i != e; ++i)
373 switch (getValueType(Args[i].second)) {
374 default: assert(0 && "Unknown value type!");
388 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
389 DAG.getConstant(NumBytes, getPointerTy()));
391 // Arguments go on the stack in reverse order, as specified by the ABI.
392 unsigned ArgOffset = 0;
393 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
395 std::vector<SDOperand> Stores;
397 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
398 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
399 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
401 switch (getValueType(Args[i].second)) {
402 default: assert(0 && "Unexpected ValueType for argument!");
406 // Promote the integer to 32 bits. If the input type is signed use a
407 // sign extend, otherwise use a zero extend.
408 if (Args[i].second->isSigned())
409 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
411 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
416 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
417 Args[i].first, PtrOff,
418 DAG.getSrcValue(NULL)));
423 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
424 Args[i].first, PtrOff,
425 DAG.getSrcValue(NULL)));
430 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
433 std::vector<MVT::ValueType> RetVals;
434 MVT::ValueType RetTyVT = getValueType(RetTy);
435 RetVals.push_back(MVT::Other);
437 // The result values produced have to be legal. Promote the result.
439 case MVT::isVoid: break;
441 RetVals.push_back(RetTyVT);
446 RetVals.push_back(MVT::i32);
450 RetVals.push_back(MVT::f32);
452 RetVals.push_back(MVT::f64);
455 RetVals.push_back(MVT::i32);
456 RetVals.push_back(MVT::i32);
461 std::vector<MVT::ValueType> NodeTys;
462 NodeTys.push_back(MVT::Other); // Returns a chain
463 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
465 std::vector<SDOperand> Ops;
466 Ops.push_back(Chain);
467 Ops.push_back(Callee);
469 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
471 SDOperand InFlag = Chain.getValue(1);
474 if (RetTyVT != MVT::isVoid) {
476 default: assert(0 && "Unknown value type to return!");
479 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
480 Chain = RetVal.getValue(1);
483 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
484 Chain = RetVal.getValue(1);
487 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
488 Chain = RetVal.getValue(1);
491 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
492 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
494 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
495 Chain = Hi.getValue(1);
500 std::vector<MVT::ValueType> Tys;
501 Tys.push_back(MVT::f64);
502 Tys.push_back(MVT::Other);
503 std::vector<SDOperand> Ops;
504 Ops.push_back(Chain);
505 Ops.push_back(InFlag);
506 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
507 Chain = RetVal.getValue(1);
509 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
510 MachineFunction &MF = DAG.getMachineFunction();
511 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
512 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
514 Tys.push_back(MVT::Other);
516 Ops.push_back(Chain);
517 Ops.push_back(RetVal);
518 Ops.push_back(StackSlot);
519 Ops.push_back(DAG.getValueType(RetTyVT));
520 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
521 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
522 DAG.getSrcValue(NULL));
523 Chain = RetVal.getValue(1);
524 } else if (RetTyVT == MVT::f32)
525 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
531 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
532 DAG.getConstant(NumBytes, getPointerTy()),
533 DAG.getConstant(0, getPointerTy()));
534 return std::make_pair(RetVal, Chain);
536 std::vector<SDOperand> Ops;
537 Ops.push_back(Chain);
538 Ops.push_back(Callee);
539 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
540 Ops.push_back(DAG.getConstant(0, getPointerTy()));
542 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
547 case MVT::isVoid: break;
549 ResultVal = TheCall.getValue(1);
554 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
557 // FIXME: we would really like to remember that this FP_ROUND operation is
558 // okay to eliminate if we allow excess FP precision.
559 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
562 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
563 TheCall.getValue(2));
567 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
568 return std::make_pair(ResultVal, Chain);
573 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
574 Value *VAListV, SelectionDAG &DAG) {
575 // vastart just stores the address of the VarArgsFrameIndex slot.
576 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
577 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
578 DAG.getSrcValue(VAListV));
582 std::pair<SDOperand,SDOperand>
583 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
584 Value *VAListV, const Type *ArgTy,
586 MVT::ValueType ArgVT = getValueType(ArgTy);
587 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
588 VAListP, DAG.getSrcValue(VAListV));
589 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
590 DAG.getSrcValue(NULL));
592 if (ArgVT == MVT::i32)
595 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
596 "Other types should have been promoted for varargs!");
599 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
600 DAG.getConstant(Amt, Val.getValueType()));
601 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
602 Val, VAListP, DAG.getSrcValue(VAListV));
603 return std::make_pair(Result, Chain);
606 //===----------------------------------------------------------------------===//
607 // Fast Calling Convention implementation
608 //===----------------------------------------------------------------------===//
610 // The X86 'fast' calling convention passes up to two integer arguments in
611 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
612 // and requires that the callee pop its arguments off the stack (allowing proper
613 // tail calls), and has the same return value conventions as C calling convs.
615 // This calling convention always arranges for the callee pop value to be 8n+4
616 // bytes, which is needed for tail recursion elimination and stack alignment
619 // Note that this can be enhanced in the future to pass fp vals in registers
620 // (when we have a global fp allocator) and do other tricks.
623 /// AddLiveIn - This helper function adds the specified physical register to the
624 /// MachineFunction as a live in value. It also creates a corresponding virtual
626 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
627 TargetRegisterClass *RC) {
628 assert(RC->contains(PReg) && "Not the correct regclass!");
629 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
630 MF.addLiveIn(PReg, VReg);
635 std::vector<SDOperand>
636 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
637 std::vector<SDOperand> ArgValues;
639 MachineFunction &MF = DAG.getMachineFunction();
640 MachineFrameInfo *MFI = MF.getFrameInfo();
642 // Add DAG nodes to load the arguments... On entry to a function the stack
643 // frame looks like this:
645 // [ESP] -- return address
646 // [ESP + 4] -- first nonreg argument (leftmost lexically)
647 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
649 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
651 // Keep track of the number of integer regs passed so far. This can be either
652 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
654 unsigned NumIntRegs = 0;
656 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
657 MVT::ValueType ObjectVT = getValueType(I->getType());
658 unsigned ArgIncrement = 4;
659 unsigned ObjSize = 0;
663 default: assert(0 && "Unhandled argument type!");
666 if (NumIntRegs < 2) {
667 if (!I->use_empty()) {
668 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
669 X86::R8RegisterClass);
670 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
671 DAG.setRoot(ArgValue.getValue(1));
672 if (ObjectVT == MVT::i1)
673 // FIXME: Should insert a assertzext here.
674 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
683 if (NumIntRegs < 2) {
684 if (!I->use_empty()) {
685 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
686 X86::R16RegisterClass);
687 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
688 DAG.setRoot(ArgValue.getValue(1));
696 if (NumIntRegs < 2) {
697 if (!I->use_empty()) {
698 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
699 X86::R32RegisterClass);
700 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
701 DAG.setRoot(ArgValue.getValue(1));
709 if (NumIntRegs == 0) {
710 if (!I->use_empty()) {
711 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
712 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
714 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
715 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
716 DAG.setRoot(Hi.getValue(1));
718 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
722 } else if (NumIntRegs == 1) {
723 if (!I->use_empty()) {
724 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
725 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
726 DAG.setRoot(Low.getValue(1));
728 // Load the high part from memory.
729 // Create the frame index object for this incoming parameter...
730 int FI = MFI->CreateFixedObject(4, ArgOffset);
731 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
732 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
733 DAG.getSrcValue(NULL));
734 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
740 ObjSize = ArgIncrement = 8;
742 case MVT::f32: ObjSize = 4; break;
743 case MVT::f64: ObjSize = ArgIncrement = 8; break;
746 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
748 if (ObjSize && !I->use_empty()) {
749 // Create the frame index object for this incoming parameter...
750 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
752 // Create the SelectionDAG nodes corresponding to a load from this
754 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
756 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
757 DAG.getSrcValue(NULL));
758 } else if (ArgValue.Val == 0) {
759 if (MVT::isInteger(ObjectVT))
760 ArgValue = DAG.getConstant(0, ObjectVT);
762 ArgValue = DAG.getConstantFP(0, ObjectVT);
764 ArgValues.push_back(ArgValue);
767 ArgOffset += ArgIncrement; // Move on to the next argument.
770 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
771 // arguments and the arguments after the retaddr has been pushed are aligned.
772 if ((ArgOffset & 7) == 0)
775 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
776 ReturnAddrIndex = 0; // No return address slot generated yet.
777 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
778 BytesCallerReserves = 0;
780 // Finally, inform the code generator which regs we return values in.
781 switch (getValueType(F.getReturnType())) {
782 default: assert(0 && "Unknown type!");
783 case MVT::isVoid: break;
788 MF.addLiveOut(X86::EAX);
791 MF.addLiveOut(X86::EAX);
792 MF.addLiveOut(X86::EDX);
796 MF.addLiveOut(X86::ST0);
802 std::pair<SDOperand, SDOperand>
803 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
804 bool isTailCall, SDOperand Callee,
805 ArgListTy &Args, SelectionDAG &DAG) {
806 // Count how many bytes are to be pushed on the stack.
807 unsigned NumBytes = 0;
809 // Keep track of the number of integer regs passed so far. This can be either
810 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
812 unsigned NumIntRegs = 0;
814 for (unsigned i = 0, e = Args.size(); i != e; ++i)
815 switch (getValueType(Args[i].second)) {
816 default: assert(0 && "Unknown value type!");
821 if (NumIntRegs < 2) {
830 if (NumIntRegs == 0) {
833 } else if (NumIntRegs == 1) {
845 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
846 // arguments and the arguments after the retaddr has been pushed are aligned.
847 if ((NumBytes & 7) == 0)
850 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
851 DAG.getConstant(NumBytes, getPointerTy()));
853 // Arguments go on the stack in reverse order, as specified by the ABI.
854 unsigned ArgOffset = 0;
855 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
858 std::vector<SDOperand> Stores;
859 std::vector<SDOperand> RegValuesToPass;
860 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
861 switch (getValueType(Args[i].second)) {
862 default: assert(0 && "Unexpected ValueType for argument!");
864 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
869 if (NumIntRegs < 2) {
870 RegValuesToPass.push_back(Args[i].first);
876 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
877 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
878 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
879 Args[i].first, PtrOff,
880 DAG.getSrcValue(NULL)));
885 if (NumIntRegs < 2) { // Can pass part of it in regs?
886 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
887 Args[i].first, DAG.getConstant(1, MVT::i32));
888 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
889 Args[i].first, DAG.getConstant(0, MVT::i32));
890 RegValuesToPass.push_back(Lo);
892 if (NumIntRegs < 2) { // Pass both parts in regs?
893 RegValuesToPass.push_back(Hi);
896 // Pass the high part in memory.
897 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
898 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
899 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
900 Hi, PtrOff, DAG.getSrcValue(NULL)));
907 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
908 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
909 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
910 Args[i].first, PtrOff,
911 DAG.getSrcValue(NULL)));
917 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
919 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
920 // arguments and the arguments after the retaddr has been pushed are aligned.
921 if ((ArgOffset & 7) == 0)
924 std::vector<MVT::ValueType> RetVals;
925 MVT::ValueType RetTyVT = getValueType(RetTy);
927 RetVals.push_back(MVT::Other);
929 // The result values produced have to be legal. Promote the result.
931 case MVT::isVoid: break;
933 RetVals.push_back(RetTyVT);
938 RetVals.push_back(MVT::i32);
942 RetVals.push_back(MVT::f32);
944 RetVals.push_back(MVT::f64);
947 RetVals.push_back(MVT::i32);
948 RetVals.push_back(MVT::i32);
952 std::vector<SDOperand> Ops;
953 Ops.push_back(Chain);
954 Ops.push_back(Callee);
955 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
956 // Callee pops all arg values on the stack.
957 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
959 // Pass register arguments as needed.
960 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
962 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
964 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
968 case MVT::isVoid: break;
970 ResultVal = TheCall.getValue(1);
975 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
978 // FIXME: we would really like to remember that this FP_ROUND operation is
979 // okay to eliminate if we allow excess FP precision.
980 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
983 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
984 TheCall.getValue(2));
988 return std::make_pair(ResultVal, Chain);
991 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
992 if (ReturnAddrIndex == 0) {
993 // Set up a frame object for the return address.
994 MachineFunction &MF = DAG.getMachineFunction();
995 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
998 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1003 std::pair<SDOperand, SDOperand> X86TargetLowering::
1004 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1005 SelectionDAG &DAG) {
1007 if (Depth) // Depths > 0 not supported yet!
1008 Result = DAG.getConstant(0, getPointerTy());
1010 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1011 if (!isFrameAddress)
1012 // Just load the return address
1013 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1014 DAG.getSrcValue(NULL));
1016 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1017 DAG.getConstant(4, MVT::i32));
1019 return std::make_pair(Result, Chain);
1022 //===----------------------------------------------------------------------===//
1023 // X86 Custom Lowering Hooks
1024 //===----------------------------------------------------------------------===//
1026 /// LowerOperation - Provide custom lowering hooks for some operations.
1028 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1029 switch (Op.getOpcode()) {
1030 default: assert(0 && "Should not custom lower this!");
1031 case ISD::SINT_TO_FP: {
1032 assert(Op.getValueType() == MVT::f64 &&
1033 Op.getOperand(0).getValueType() == MVT::i64 &&
1034 "Unknown SINT_TO_FP to lower!");
1035 // We lower sint64->FP into a store to a temporary stack slot, followed by a
1037 MachineFunction &MF = DAG.getMachineFunction();
1038 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1039 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1040 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1041 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
1042 std::vector<MVT::ValueType> RTs;
1043 RTs.push_back(MVT::f64);
1044 RTs.push_back(MVT::Other);
1045 std::vector<SDOperand> Ops;
1046 Ops.push_back(Store);
1047 Ops.push_back(StackSlot);
1048 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
1050 case ISD::FP_TO_SINT: {
1051 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1052 Op.getOperand(0).getValueType() == MVT::f64 &&
1053 "Unknown FP_TO_SINT to lower!");
1054 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1056 MachineFunction &MF = DAG.getMachineFunction();
1057 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1058 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1059 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1062 switch (Op.getValueType()) {
1063 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1064 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1065 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1066 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1069 // Build the FP_TO_INT*_IN_MEM
1070 std::vector<SDOperand> Ops;
1071 Ops.push_back(DAG.getEntryNode());
1072 Ops.push_back(Op.getOperand(0));
1073 Ops.push_back(StackSlot);
1074 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1077 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1078 DAG.getSrcValue(NULL));
1080 case ISD::READCYCLECOUNTER: {
1081 std::vector<MVT::ValueType> Tys;
1082 Tys.push_back(MVT::Other);
1083 Tys.push_back(MVT::Flag);
1084 std::vector<SDOperand> Ops;
1085 Ops.push_back(Op.getOperand(0));
1086 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1088 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1089 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1090 MVT::i32, Ops[0].getValue(2)));
1091 Ops.push_back(Ops[1].getValue(1));
1092 Tys[0] = Tys[1] = MVT::i32;
1093 Tys.push_back(MVT::Other);
1094 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1097 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1098 SDOperand CC = Op.getOperand(2);
1099 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1100 Op.getOperand(0), Op.getOperand(1));
1101 return DAG.getNode(X86ISD::SETCC, MVT::i8, CC, Cond);
1104 SDOperand Cond = Op.getOperand(0);
1106 if (Cond.getOpcode() == X86ISD::SETCC) {
1107 CC = Cond.getOperand(0);
1108 Cond = Cond.getOperand(1);
1109 } else if (Cond.getOpcode() == ISD::SETCC) {
1110 CC = Cond.getOperand(2);
1111 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1112 Cond.getOperand(0), Cond.getOperand(1));
1114 CC = DAG.getCondCode(ISD::SETEQ);
1115 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1117 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
1118 Op.getOperand(1), Op.getOperand(2), CC, Cond);
1121 SDOperand Cond = Op.getOperand(1);
1122 SDOperand Dest = Op.getOperand(2);
1124 // TODO: handle Cond == OR / AND / XOR
1125 if (Cond.getOpcode() == X86ISD::SETCC) {
1126 CC = Cond.getOperand(0);
1127 Cond = Cond.getOperand(1);
1128 } else if (Cond.getOpcode() == ISD::SETCC) {
1129 CC = Cond.getOperand(2);
1130 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1131 Cond.getOperand(0), Cond.getOperand(1));
1133 CC = DAG.getCondCode(ISD::SETNE);
1134 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1136 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1137 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1139 case ISD::GlobalAddress: {
1140 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1141 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
1142 // For Darwin, external and weak symbols are indirect, so we want to load
1143 // the value at address GV, not the value of GV itself. This means that
1144 // the GlobalAddress must be in the base or index register of the address,
1145 // not the GV offset field.
1146 if (getTargetMachine().
1147 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1148 (GV->hasWeakLinkage() || GV->isExternal()))
1149 return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1150 GVOp, DAG.getSrcValue(NULL));
1158 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1160 default: return NULL;
1161 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1162 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1163 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1164 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1165 case X86ISD::FLD: return "X86ISD::FLD";
1166 case X86ISD::FST: return "X86ISD::FST";
1167 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1168 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1169 case X86ISD::CALL: return "X86ISD::CALL";
1170 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1171 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1172 case X86ISD::CMP: return "X86ISD::CMP";
1173 case X86ISD::TEST: return "X86ISD::TEST";
1174 case X86ISD::SETCC: return "X86ISD::SETCC";
1175 case X86ISD::CMOV: return "X86ISD::CMOV";
1176 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1177 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1181 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1182 uint64_t Mask) const {
1184 unsigned Opc = Op.getOpcode();
1188 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1190 case X86ISD::SETCC: return (Mask & 1) == 0;